From 3fb6e3bd8aa968c703637f880745c9a927dae2f7 Mon Sep 17 00:00:00 2001
From: aschi54 <aschi54>
Date: Mon, 27 Dec 2010 13:20:36 +0000
Subject: [PATCH 01/16] Initial commit

---
 FPGA_by_Fredi/Coldari1.qsf                    |    44 +
 FPGA_by_Fredi/DSP/DSP.vhd                     |    79 +
 FPGA_by_Fredi/DSP/DSP.vhd.bak                 |    79 +
 FPGA_by_Fredi/DSP/dsp56k.zip                  |   Bin 0 -> 39208 bytes
 FPGA_by_Fredi/DSP/src/adgen_stage.vhd         |   216 +
 FPGA_by_Fredi/DSP/src/constants_pkg.vhd       |    62 +
 FPGA_by_Fredi/DSP/src/decode_stage.vhd        |  1221 ++
 FPGA_by_Fredi/DSP/src/exec_stage_alu.vhd      |   603 +
 .../DSP/src/exec_stage_bit_modify.vhd         |    79 +
 FPGA_by_Fredi/DSP/src/exec_stage_branch.vhd   |   117 +
 .../DSP/src/exec_stage_cc_flag_calc.vhd       |    75 +
 FPGA_by_Fredi/DSP/src/exec_stage_cr_mod.vhd   |    72 +
 FPGA_by_Fredi/DSP/src/exec_stage_loops.vhd    |   200 +
 FPGA_by_Fredi/DSP/src/fetch_stage.vhd         |    60 +
 FPGA_by_Fredi/DSP/src/mem_control.vhd         |  1519 +++
 FPGA_by_Fredi/DSP/src/memory_management.vhd   |   206 +
 FPGA_by_Fredi/DSP/src/parameter_pkg.vhd       |    10 +
 FPGA_by_Fredi/DSP/src/pipeline.vhd            |   968 ++
 FPGA_by_Fredi/DSP/src/reg_file.vhd            |   679 +
 FPGA_by_Fredi/DSP/src/types_pkg.vhd           |   167 +
 .../FalconIO_SDCard_IDE_CF.vhd                |   971 ++
 .../FalconIO_SDCard_IDE_CF.vhd.bak            |   971 ++
 .../FalconIO_SDCard_IDE_CF_pgk.vhd            |   406 +
 .../FalconIO_SDCard_IDE_CF_pgk.vhd.bak        |   406 +
 .../WF5380/wf5380_control.vhd                 |   631 +
 .../WF5380/wf5380_pkg.vhd                     |   139 +
 .../WF5380/wf5380_registers.vhd               |   265 +
 .../WF5380/wf5380_soc_top.vhd                 |   300 +
 .../WF5380/wf5380_top.vhd                     |   275 +
 .../WF_FDC1772_IP/wf1772ip_am_detector.vhd    |   253 +
 .../WF_FDC1772_IP/wf1772ip_control.vhd        |  1463 +++
 .../WF_FDC1772_IP/wf1772ip_crc_logic.vhd      |   162 +
 .../WF_FDC1772_IP/wf1772ip_digital_pll.vhd    |   426 +
 .../WF_FDC1772_IP/wf1772ip_pkg.vhd            |   232 +
 .../WF_FDC1772_IP/wf1772ip_registers.vhd      |   264 +
 .../WF_FDC1772_IP/wf1772ip_top.vhd            |   154 +
 .../WF_FDC1772_IP/wf1772ip_top_soc.vhd        |   333 +
 .../WF_FDC1772_IP/wf1772ip_transceiver.vhd    |   517 +
 .../WF_MFP68901_IP/wf68901ip_gpio.vhd         |   141 +
 .../WF_MFP68901_IP/wf68901ip_interrupts.vhd   |   391 +
 .../WF_MFP68901_IP/wf68901ip_pkg.vhd          |   263 +
 .../WF_MFP68901_IP/wf68901ip_timers.vhd       |   533 +
 .../WF_MFP68901_IP/wf68901ip_top.vhd          |   213 +
 .../WF_MFP68901_IP/wf68901ip_top_soc.vhd      |   309 +
 .../WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd   |   191 +
 .../WF_MFP68901_IP/wf68901ip_usart_rx.vhd     |   590 +
 .../WF_MFP68901_IP/wf68901ip_usart_top.vhd    |   238 +
 .../WF_MFP68901_IP/wf68901ip_usart_tx.vhd     |   387 +
 .../WF_SDC_IF/sd-card-interface.vhd           |   228 +
 .../WF_SDC_IF/sd-card-interface_soc.vhd       |   240 +
 .../WF_SDC_IF/sd-card-interface_soc.vhd.bak   |   239 +
 .../WF_SND2149_IP/wf2149ip_pkg.vhd            |    84 +
 .../WF_SND2149_IP/wf2149ip_top.vhd            |   170 +
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd        |   229 +
 .../WF_SND2149_IP/wf2149ip_wave.vhd           |   533 +
 .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd   |   244 +
 .../wf6850ip_ctrl_status.vhd.bak              |   244 +
 .../WF_UART6850_IP/wf6850ip_receive.vhd       |   415 +
 .../WF_UART6850_IP/wf6850ip_receive.vhd.bak   |   415 +
 .../WF_UART6850_IP/wf6850ip_top.vhd           |   135 +
 .../WF_UART6850_IP/wf6850ip_top_soc.vhd       |   255 +
 .../WF_UART6850_IP/wf6850ip_top_soc.vhd.bak   |   252 +
 .../WF_UART6850_IP/wf6850ip_transmit.vhd      |   339 +
 .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak  |   339 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.bsf        |    95 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.cmp        |    28 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.qip        |     5 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd        |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak    |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.bsf        |    95 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.cmp        |    28 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.qip        |     5 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd        |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak    |   202 +
 .../Interrupt_Handler/interrupt_handler.tdf   |   478 +
 .../interrupt_handler.tdf.bak                 |   478 +
 FPGA_by_Fredi/UNUSED                          |    27 +
 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd       |    75 +
 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak   |    75 +
 FPGA_by_Fredi/Video/DDR_CTR.tdf               |   659 +
 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak           |   660 +
 FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak   |   352 +
 FPGA_by_Fredi/Video/UNUSED                    |   267 +
 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf |   675 +
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       |   675 +
 FPGA_by_Fredi/Video/Video.bdf                 | 10651 ++++++++++++++++
 FPGA_by_Fredi/Video/altddio_bidir0.bsf        |    99 +
 FPGA_by_Fredi/Video/altddio_bidir0.cmp        |    29 +
 FPGA_by_Fredi/Video/altddio_bidir0.inc        |    30 +
 FPGA_by_Fredi/Video/altddio_bidir0.ppf        |    16 +
 FPGA_by_Fredi/Video/altddio_bidir0.qip        |     7 +
 FPGA_by_Fredi/Video/altddio_bidir0.vhd        |   172 +
 FPGA_by_Fredi/Video/altddio_out0.bsf          |    64 +
 FPGA_by_Fredi/Video/altddio_out0.cmp          |    24 +
 FPGA_by_Fredi/Video/altddio_out0.inc          |    25 +
 FPGA_by_Fredi/Video/altddio_out0.ppf          |    11 +
 FPGA_by_Fredi/Video/altddio_out0.qip          |     7 +
 FPGA_by_Fredi/Video/altddio_out0.vhd          |   136 +
 FPGA_by_Fredi/Video/altddio_out1.bsf          |    64 +
 FPGA_by_Fredi/Video/altddio_out1.cmp          |    24 +
 FPGA_by_Fredi/Video/altddio_out1.inc          |    25 +
 FPGA_by_Fredi/Video/altddio_out1.ppf          |    11 +
 FPGA_by_Fredi/Video/altddio_out1.qip          |     7 +
 FPGA_by_Fredi/Video/altddio_out1.vhd          |   146 +
 FPGA_by_Fredi/Video/altddio_out2.bsf          |    64 +
 FPGA_by_Fredi/Video/altddio_out2.cmp          |    24 +
 FPGA_by_Fredi/Video/altddio_out2.inc          |    25 +
 FPGA_by_Fredi/Video/altddio_out2.ppf          |    11 +
 FPGA_by_Fredi/Video/altddio_out2.qip          |     7 +
 FPGA_by_Fredi/Video/altddio_out2.vhd          |   136 +
 FPGA_by_Fredi/Video/altdpram0.bsf             |   173 +
 FPGA_by_Fredi/Video/altdpram0.cmp             |    30 +
 FPGA_by_Fredi/Video/altdpram0.inc             |    31 +
 FPGA_by_Fredi/Video/altdpram0.qip             |     6 +
 FPGA_by_Fredi/Video/altdpram0.vhd             |   273 +
 FPGA_by_Fredi/Video/altdpram0_wave0.jpg       |   Bin 0 -> 125146 bytes
 FPGA_by_Fredi/Video/altdpram0_wave1.jpg       |   Bin 0 -> 171723 bytes
 FPGA_by_Fredi/Video/altdpram0_waveforms.html  |    16 +
 FPGA_by_Fredi/Video/altdpram1.bsf             |   173 +
 FPGA_by_Fredi/Video/altdpram1.cmp             |    30 +
 FPGA_by_Fredi/Video/altdpram1.inc             |    31 +
 FPGA_by_Fredi/Video/altdpram1.qip             |     6 +
 FPGA_by_Fredi/Video/altdpram1.vhd             |   273 +
 FPGA_by_Fredi/Video/altdpram1_wave0.jpg       |   Bin 0 -> 151954 bytes
 FPGA_by_Fredi/Video/altdpram1_wave1.jpg       |   Bin 0 -> 203609 bytes
 FPGA_by_Fredi/Video/altdpram1_waveforms.html  |    16 +
 FPGA_by_Fredi/Video/altdpram2.bsf             |   173 +
 FPGA_by_Fredi/Video/altdpram2.cmp             |    30 +
 FPGA_by_Fredi/Video/altdpram2.inc             |    31 +
 FPGA_by_Fredi/Video/altdpram2.qip             |     6 +
 FPGA_by_Fredi/Video/altdpram2.vhd             |   273 +
 FPGA_by_Fredi/Video/altdpram2_wave0.jpg       |   Bin 0 -> 152433 bytes
 FPGA_by_Fredi/Video/altdpram2_wave1.jpg       |   Bin 0 -> 204342 bytes
 FPGA_by_Fredi/Video/altdpram2_waveforms.html  |    16 +
 FPGA_by_Fredi/Video/lpm_bustri0.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri0.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri0.inc           |    24 +
 FPGA_by_Fredi/Video/lpm_bustri0.qip           |     6 +
 FPGA_by_Fredi/Video/lpm_bustri0.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri1.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri1.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri1.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri1.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri2.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri2.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri2.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri2.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri3.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri3.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri3.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri3.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri4.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri4.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri4.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri4.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri5.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri5.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri5.inc           |    24 +
 FPGA_by_Fredi/Video/lpm_bustri5.qip           |     6 +
 FPGA_by_Fredi/Video/lpm_bustri5.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri6.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri6.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri6.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri6.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_bustri7.bsf           |    56 +
 FPGA_by_Fredi/Video/lpm_bustri7.cmp           |    23 +
 FPGA_by_Fredi/Video/lpm_bustri7.qip           |     5 +
 FPGA_by_Fredi/Video/lpm_bustri7.vhd           |   107 +
 FPGA_by_Fredi/Video/lpm_compare1.bsf          |    54 +
 FPGA_by_Fredi/Video/lpm_compare1.cmp          |    23 +
 FPGA_by_Fredi/Video/lpm_compare1.inc          |    24 +
 FPGA_by_Fredi/Video/lpm_compare1.qip          |     6 +
 FPGA_by_Fredi/Video/lpm_compare1.vhd          |   127 +
 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg    |   Bin 0 -> 30655 bytes
 .../Video/lpm_compare1_waveforms.html         |    13 +
 FPGA_by_Fredi/Video/lpm_constant0.bsf         |    42 +
 FPGA_by_Fredi/Video/lpm_constant0.cmp         |    21 +
 FPGA_by_Fredi/Video/lpm_constant0.qip         |     5 +
 FPGA_by_Fredi/Video/lpm_constant0.vhd         |   108 +
 FPGA_by_Fredi/Video/lpm_constant1.bsf         |    42 +
 FPGA_by_Fredi/Video/lpm_constant1.cmp         |    21 +
 FPGA_by_Fredi/Video/lpm_constant1.inc         |    23 +
 FPGA_by_Fredi/Video/lpm_constant1.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_constant1.vhd         |   108 +
 FPGA_by_Fredi/Video/lpm_constant2.bsf         |    42 +
 FPGA_by_Fredi/Video/lpm_constant2.cmp         |    21 +
 FPGA_by_Fredi/Video/lpm_constant2.qip         |     5 +
 FPGA_by_Fredi/Video/lpm_constant2.vhd         |   108 +
 FPGA_by_Fredi/Video/lpm_constant3.bsf         |    42 +
 FPGA_by_Fredi/Video/lpm_constant3.cmp         |    21 +
 FPGA_by_Fredi/Video/lpm_constant3.qip         |     5 +
 FPGA_by_Fredi/Video/lpm_constant3.vhd         |   108 +
 FPGA_by_Fredi/Video/lpm_constant4.bsf         |    42 +
 FPGA_by_Fredi/Video/lpm_constant4.cmp         |    21 +
 FPGA_by_Fredi/Video/lpm_constant4.inc         |    23 +
 FPGA_by_Fredi/Video/lpm_constant4.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_constant4.vhd         |   108 +
 FPGA_by_Fredi/Video/lpm_ff0.bsf               |    63 +
 FPGA_by_Fredi/Video/lpm_ff0.cmp               |    24 +
 FPGA_by_Fredi/Video/lpm_ff0.qip               |     5 +
 FPGA_by_Fredi/Video/lpm_ff0.vhd               |   127 +
 FPGA_by_Fredi/Video/lpm_ff1.bsf               |    56 +
 FPGA_by_Fredi/Video/lpm_ff1.cmp               |    23 +
 FPGA_by_Fredi/Video/lpm_ff1.qip               |     5 +
 FPGA_by_Fredi/Video/lpm_ff1.vhd               |   122 +
 FPGA_by_Fredi/Video/lpm_ff2.bsf               |    56 +
 FPGA_by_Fredi/Video/lpm_ff2.cmp               |    23 +
 FPGA_by_Fredi/Video/lpm_ff2.qip               |     5 +
 FPGA_by_Fredi/Video/lpm_ff2.vhd               |   122 +
 FPGA_by_Fredi/Video/lpm_ff3.bsf               |    56 +
 FPGA_by_Fredi/Video/lpm_ff3.cmp               |    23 +
 FPGA_by_Fredi/Video/lpm_ff3.qip               |     5 +
 FPGA_by_Fredi/Video/lpm_ff3.vhd               |   122 +
 FPGA_by_Fredi/Video/lpm_ff4.bsf               |    56 +
 FPGA_by_Fredi/Video/lpm_ff4.cmp               |    23 +
 FPGA_by_Fredi/Video/lpm_ff4.inc               |    24 +
 FPGA_by_Fredi/Video/lpm_ff4.qip               |     6 +
 FPGA_by_Fredi/Video/lpm_ff4.vhd               |   122 +
 FPGA_by_Fredi/Video/lpm_ff5.bsf               |    56 +
 FPGA_by_Fredi/Video/lpm_ff5.cmp               |    23 +
 FPGA_by_Fredi/Video/lpm_ff5.inc               |    24 +
 FPGA_by_Fredi/Video/lpm_ff5.qip               |     6 +
 FPGA_by_Fredi/Video/lpm_ff5.vhd               |   122 +
 FPGA_by_Fredi/Video/lpm_ff6.bsf               |    63 +
 FPGA_by_Fredi/Video/lpm_ff6.cmp               |    24 +
 FPGA_by_Fredi/Video/lpm_ff6.inc               |    25 +
 FPGA_by_Fredi/Video/lpm_ff6.qip               |     6 +
 FPGA_by_Fredi/Video/lpm_ff6.vhd               |   127 +
 FPGA_by_Fredi/Video/lpm_fifoDZ.bsf            |    79 +
 FPGA_by_Fredi/Video/lpm_fifoDZ.cmp            |    26 +
 FPGA_by_Fredi/Video/lpm_fifoDZ.qip            |     5 +
 FPGA_by_Fredi/Video/lpm_fifoDZ.vhd            |   178 +
 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg      |   Bin 0 -> 86257 bytes
 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html |    13 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf          |   102 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp          |    29 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0.inc          |    30 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0.qip          |     6 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd          |   203 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg    |   Bin 0 -> 121926 bytes
 .../Video/lpm_fifo_dc0_waveforms.html         |    13 +
 FPGA_by_Fredi/Video/lpm_latch1.bsf            |    53 +
 FPGA_by_Fredi/Video/lpm_latch1.cmp            |    23 +
 FPGA_by_Fredi/Video/lpm_latch1.qip            |     5 +
 FPGA_by_Fredi/Video/lpm_latch1.vhd            |   110 +
 FPGA_by_Fredi/Video/lpm_mux0.bsf              |    83 +
 FPGA_by_Fredi/Video/lpm_mux0.cmp              |    27 +
 FPGA_by_Fredi/Video/lpm_mux0.inc              |    28 +
 FPGA_by_Fredi/Video/lpm_mux0.qip              |     6 +
 FPGA_by_Fredi/Video/lpm_mux0.vhd              |   251 +
 FPGA_by_Fredi/Video/lpm_mux1.bsf              |   111 +
 FPGA_by_Fredi/Video/lpm_mux1.cmp              |    31 +
 FPGA_by_Fredi/Video/lpm_mux1.inc              |    32 +
 FPGA_by_Fredi/Video/lpm_mux1.qip              |     6 +
 FPGA_by_Fredi/Video/lpm_mux1.vhd              |   271 +
 FPGA_by_Fredi/Video/lpm_mux2.bsf              |   167 +
 FPGA_by_Fredi/Video/lpm_mux2.cmp              |    39 +
 FPGA_by_Fredi/Video/lpm_mux2.inc              |    40 +
 FPGA_by_Fredi/Video/lpm_mux2.qip              |     6 +
 FPGA_by_Fredi/Video/lpm_mux2.vhd              |   311 +
 FPGA_by_Fredi/Video/lpm_mux3.bsf              |    60 +
 FPGA_by_Fredi/Video/lpm_mux3.cmp              |    24 +
 FPGA_by_Fredi/Video/lpm_mux3.qip              |     5 +
 FPGA_by_Fredi/Video/lpm_mux3.vhd              |   115 +
 FPGA_by_Fredi/Video/lpm_mux4.bsf              |    60 +
 FPGA_by_Fredi/Video/lpm_mux4.cmp              |    24 +
 FPGA_by_Fredi/Video/lpm_mux4.qip              |     5 +
 FPGA_by_Fredi/Video/lpm_mux4.vhd              |   125 +
 FPGA_by_Fredi/Video/lpm_mux5.bsf              |    74 +
 FPGA_by_Fredi/Video/lpm_mux5.cmp              |    26 +
 FPGA_by_Fredi/Video/lpm_mux5.inc              |    27 +
 FPGA_by_Fredi/Video/lpm_mux5.qip              |     6 +
 FPGA_by_Fredi/Video/lpm_mux5.vhd              |   373 +
 FPGA_by_Fredi/Video/lpm_mux6.bsf              |   111 +
 FPGA_by_Fredi/Video/lpm_mux6.cmp              |    31 +
 FPGA_by_Fredi/Video/lpm_mux6.inc              |    32 +
 FPGA_by_Fredi/Video/lpm_mux6.qip              |     6 +
 FPGA_by_Fredi/Video/lpm_mux6.vhd              |   335 +
 FPGA_by_Fredi/Video/lpm_muxDZ.bsf             |    76 +
 FPGA_by_Fredi/Video/lpm_muxDZ.cmp             |    26 +
 FPGA_by_Fredi/Video/lpm_muxDZ.qip             |     5 +
 FPGA_by_Fredi/Video/lpm_muxDZ.vhd             |   377 +
 FPGA_by_Fredi/Video/lpm_muxDZ2.bsf            |    60 +
 FPGA_by_Fredi/Video/lpm_muxDZ2.cmp            |    24 +
 FPGA_by_Fredi/Video/lpm_muxDZ2.qip            |     5 +
 FPGA_by_Fredi/Video/lpm_muxDZ2.vhd            |   115 +
 FPGA_by_Fredi/Video/lpm_muxVDM.bsf            |   158 +
 FPGA_by_Fredi/Video/lpm_muxVDM.cmp            |    38 +
 FPGA_by_Fredi/Video/lpm_muxVDM.qip            |     5 +
 FPGA_by_Fredi/Video/lpm_muxVDM.vhd            |  2225 ++++
 FPGA_by_Fredi/Video/lpm_shiftreg0.bsf         |    70 +
 FPGA_by_Fredi/Video/lpm_shiftreg0.cmp         |    25 +
 FPGA_by_Fredi/Video/lpm_shiftreg0.inc         |    26 +
 FPGA_by_Fredi/Video/lpm_shiftreg0.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_shiftreg0.vhd         |   135 +
 FPGA_by_Fredi/Video/lpm_shiftreg1.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg1.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg1.qip         |     5 +
 FPGA_by_Fredi/Video/lpm_shiftreg1.vhd         |   125 +
 FPGA_by_Fredi/Video/lpm_shiftreg2.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg2.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg2.qip         |     5 +
 FPGA_by_Fredi/Video/lpm_shiftreg2.vhd         |   125 +
 FPGA_by_Fredi/Video/lpm_shiftreg3.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg3.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg3.inc         |    24 +
 FPGA_by_Fredi/Video/lpm_shiftreg3.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_shiftreg3.vhd         |   125 +
 FPGA_by_Fredi/Video/lpm_shiftreg4.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg4.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg4.inc         |    24 +
 FPGA_by_Fredi/Video/lpm_shiftreg4.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_shiftreg4.vhd         |   125 +
 FPGA_by_Fredi/Video/lpm_shiftreg5.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg5.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg5.inc         |    24 +
 FPGA_by_Fredi/Video/lpm_shiftreg5.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_shiftreg5.vhd         |   125 +
 FPGA_by_Fredi/Video/lpm_shiftreg6.bsf         |    56 +
 FPGA_by_Fredi/Video/lpm_shiftreg6.cmp         |    23 +
 FPGA_by_Fredi/Video/lpm_shiftreg6.inc         |    24 +
 FPGA_by_Fredi/Video/lpm_shiftreg6.qip         |     6 +
 FPGA_by_Fredi/Video/lpm_shiftreg6.vhd         |   125 +
 FPGA_by_Fredi/altddio_out0.bsf                |    64 +
 FPGA_by_Fredi/altddio_out0.cmp                |    24 +
 FPGA_by_Fredi/altddio_out0.inc                |    25 +
 FPGA_by_Fredi/altddio_out0.ppf                |    11 +
 FPGA_by_Fredi/altddio_out0.qip                |     7 +
 FPGA_by_Fredi/altddio_out0.vhd                |   146 +
 FPGA_by_Fredi/altddio_out3.bsf                |    64 +
 FPGA_by_Fredi/altddio_out3.cmp                |    24 +
 FPGA_by_Fredi/altddio_out3.inc                |    25 +
 FPGA_by_Fredi/altddio_out3.ppf                |    11 +
 FPGA_by_Fredi/altddio_out3.qip                |     7 +
 FPGA_by_Fredi/altddio_out3.vhd                |   146 +
 FPGA_by_Fredi/altpll0.bsf                     |   117 +
 FPGA_by_Fredi/altpll0.cmp                     |    26 +
 FPGA_by_Fredi/altpll0.inc                     |    27 +
 FPGA_by_Fredi/altpll0.ppf                     |    13 +
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 FPGA_by_Fredi/altpll0.vhd                     |   477 +
 FPGA_by_Fredi/altpll0_waveforms.html          |    10 +
 FPGA_by_Fredi/altpll1.bsf                     |   100 +
 FPGA_by_Fredi/altpll1.cmp                     |    25 +
 FPGA_by_Fredi/altpll1.inc                     |    26 +
 FPGA_by_Fredi/altpll1.ppf                     |    12 +
 FPGA_by_Fredi/altpll1.qip                     |     7 +
 FPGA_by_Fredi/altpll1.vhd                     |   423 +
 FPGA_by_Fredi/altpll1_waveforms.html          |    10 +
 FPGA_by_Fredi/altpll2.bsf                     |   117 +
 FPGA_by_Fredi/altpll2.cmp                     |    26 +
 FPGA_by_Fredi/altpll2.inc                     |    27 +
 FPGA_by_Fredi/altpll2.ppf                     |    13 +
 FPGA_by_Fredi/altpll2.qip                     |     7 +
 FPGA_by_Fredi/altpll2.vhd                     |   477 +
 FPGA_by_Fredi/altpll2_waveforms.html          |    10 +
 FPGA_by_Fredi/altpll3.bsf                     |   105 +
 FPGA_by_Fredi/altpll3.cmp                     |    25 +
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 FPGA_by_Fredi/altpll3.ppf                     |    12 +
 FPGA_by_Fredi/altpll3.qip                     |     7 +
 FPGA_by_Fredi/altpll3.vhd                     |   445 +
 FPGA_by_Fredi/altpll3_waveforms.html          |    10 +
 FPGA_by_Fredi/altpll4.bsf                     |   125 +
 FPGA_by_Fredi/altpll4.cmp                     |    30 +
 FPGA_by_Fredi/altpll4.inc                     |    31 +
 FPGA_by_Fredi/altpll4.mif                     |   174 +
 FPGA_by_Fredi/altpll4.ppf                     |    17 +
 FPGA_by_Fredi/altpll4.qip                     |     7 +
 FPGA_by_Fredi/altpll4.tdf                     |   298 +
 FPGA_by_Fredi/altpll_reconfig0.bsf            |   162 +
 FPGA_by_Fredi/altpll_reconfig0.qip            |     5 +
 FPGA_by_Fredi/altpll_reconfig1.bsf            |   162 +
 FPGA_by_Fredi/altpll_reconfig1.cmp            |    38 +
 FPGA_by_Fredi/altpll_reconfig1.inc            |    39 +
 FPGA_by_Fredi/altpll_reconfig1.qip            |     6 +
 FPGA_by_Fredi/altpll_reconfig1.tdf            |   144 +
 .../altpll_reconfig1_pllrcfg_bju.tdf          |   583 +
 .../altpll_reconfig1_pllrcfg_t4q.tdf          |   582 +
 FPGA_by_Fredi/firebee1.asm.rpt                |   128 +
 FPGA_by_Fredi/firebee1.bdf                    |  5837 +++++++++
 FPGA_by_Fredi/firebee1.done                   |     1 +
 FPGA_by_Fredi/firebee1.dpf                    |    12 +
 FPGA_by_Fredi/firebee1.fit.rpt                |  6866 ++++++++++
 FPGA_by_Fredi/firebee1.fit.summary            |    16 +
 FPGA_by_Fredi/firebee1.flow.rpt               |   380 +
 FPGA_by_Fredi/firebee1.map.rpt                |  8590 +++++++++++++
 FPGA_by_Fredi/firebee1.map.summary            |    14 +
 FPGA_by_Fredi/firebee1.pin                    |   557 +
 FPGA_by_Fredi/firebee1.qsf                    |   740 ++
 FPGA_by_Fredi/firebee1.qws                    |     4 +
 FPGA_by_Fredi/firebee1.rbf                    |   Bin 0 -> 428953 bytes
 FPGA_by_Fredi/firebee1.sof                    |   Bin 0 -> 1171297 bytes
 FPGA_by_Fredi/firebee1.tan.rpt                |  6936 ++++++++++
 FPGA_by_Fredi/firebee1.tan.summary            |   296 +
 .../firebee1_assignment_defaults.qdf          |   687 +
 FPGA_by_Fredi/firebeei1.qpf                   |    23 +
 FPGA_by_Fredi/firebeei1.qws                   |    27 +
 FPGA_by_Fredi/lpm_bustri_BYT.bsf              |    56 +
 FPGA_by_Fredi/lpm_bustri_BYT.cmp              |    23 +
 FPGA_by_Fredi/lpm_bustri_BYT.inc              |    24 +
 FPGA_by_Fredi/lpm_bustri_BYT.qip              |     6 +
 FPGA_by_Fredi/lpm_bustri_BYT.vhd              |   107 +
 FPGA_by_Fredi/lpm_bustri_LONG.bsf             |    56 +
 FPGA_by_Fredi/lpm_bustri_LONG.cmp             |    23 +
 FPGA_by_Fredi/lpm_bustri_LONG.inc             |    24 +
 FPGA_by_Fredi/lpm_bustri_LONG.qip             |     6 +
 FPGA_by_Fredi/lpm_bustri_LONG.vhd             |   107 +
 FPGA_by_Fredi/lpm_bustri_WORD.bsf             |    56 +
 FPGA_by_Fredi/lpm_bustri_WORD.cmp             |    23 +
 FPGA_by_Fredi/lpm_bustri_WORD.inc             |    24 +
 FPGA_by_Fredi/lpm_bustri_WORD.qip             |     6 +
 FPGA_by_Fredi/lpm_bustri_WORD.vhd             |   107 +
 FPGA_by_Fredi/lpm_counter0.bsf                |    49 +
 FPGA_by_Fredi/lpm_counter0.cmp                |    22 +
 FPGA_by_Fredi/lpm_counter0.qip                |     5 +
 FPGA_by_Fredi/lpm_counter0.vhd                |   126 +
 FPGA_by_Fredi/lpm_counter0_wave0.jpg          |   Bin 0 -> 56372 bytes
 FPGA_by_Fredi/lpm_counter0_waveforms.html     |    13 +
 FPGA_by_Fredi/lpm_counter1_waveforms.html     |    16 +
 FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html     |    16 +
 FPGA_by_Fredi/lpm_latch0.bsf                  |    53 +
 FPGA_by_Fredi/lpm_latch0.cmp                  |    23 +
 FPGA_by_Fredi/lpm_latch0.qip                  |     5 +
 FPGA_by_Fredi/lpm_latch0.vhd                  |   110 +
 FPGA_by_Fredi/serv_req_info.txt               |   115 +
 FPGA_by_Fredi/undo_redo.txt                   |     0
 427 files changed, 91737 insertions(+)
 create mode 100644 FPGA_by_Fredi/Coldari1.qsf
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 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
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 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
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 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
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 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.qip
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 create mode 100644 FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
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 create mode 100644 FPGA_by_Fredi/Video/DDR_CTR.tdf
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 create mode 100644 FPGA_by_Fredi/Video/altddio_bidir0.inc
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 create mode 100644 FPGA_by_Fredi/Video/altddio_out0.ppf
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 create mode 100644 FPGA_by_Fredi/Video/altdpram0.inc
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 create mode 100644 FPGA_by_Fredi/Video/altdpram1.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_bustri0.cmp
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 create mode 100644 FPGA_by_Fredi/Video/lpm_mux6.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_muxDZ.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_muxDZ2.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_muxVDM.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_shiftreg0.bsf
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 create mode 100644 FPGA_by_Fredi/Video/lpm_shiftreg5.bsf
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 create mode 100644 FPGA_by_Fredi/altddio_out0.bsf
 create mode 100644 FPGA_by_Fredi/altddio_out0.cmp
 create mode 100644 FPGA_by_Fredi/altddio_out0.inc
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 create mode 100644 FPGA_by_Fredi/altddio_out3.bsf
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 create mode 100644 FPGA_by_Fredi/altddio_out3.inc
 create mode 100644 FPGA_by_Fredi/altddio_out3.ppf
 create mode 100644 FPGA_by_Fredi/altddio_out3.qip
 create mode 100644 FPGA_by_Fredi/altddio_out3.vhd
 create mode 100644 FPGA_by_Fredi/altpll0.bsf
 create mode 100644 FPGA_by_Fredi/altpll0.cmp
 create mode 100644 FPGA_by_Fredi/altpll0.inc
 create mode 100644 FPGA_by_Fredi/altpll0.ppf
 create mode 100644 FPGA_by_Fredi/altpll0.qip
 create mode 100644 FPGA_by_Fredi/altpll0.vhd
 create mode 100644 FPGA_by_Fredi/altpll0_waveforms.html
 create mode 100644 FPGA_by_Fredi/altpll1.bsf
 create mode 100644 FPGA_by_Fredi/altpll1.cmp
 create mode 100644 FPGA_by_Fredi/altpll1.inc
 create mode 100644 FPGA_by_Fredi/altpll1.ppf
 create mode 100644 FPGA_by_Fredi/altpll1.qip
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 create mode 100644 FPGA_by_Fredi/altpll1_waveforms.html
 create mode 100644 FPGA_by_Fredi/altpll2.bsf
 create mode 100644 FPGA_by_Fredi/altpll2.cmp
 create mode 100644 FPGA_by_Fredi/altpll2.inc
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 create mode 100644 FPGA_by_Fredi/altpll3.bsf
 create mode 100644 FPGA_by_Fredi/altpll3.cmp
 create mode 100644 FPGA_by_Fredi/altpll3.inc
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 create mode 100644 FPGA_by_Fredi/altpll3_waveforms.html
 create mode 100644 FPGA_by_Fredi/altpll4.bsf
 create mode 100644 FPGA_by_Fredi/altpll4.cmp
 create mode 100644 FPGA_by_Fredi/altpll4.inc
 create mode 100644 FPGA_by_Fredi/altpll4.mif
 create mode 100644 FPGA_by_Fredi/altpll4.ppf
 create mode 100644 FPGA_by_Fredi/altpll4.qip
 create mode 100644 FPGA_by_Fredi/altpll4.tdf
 create mode 100644 FPGA_by_Fredi/altpll_reconfig0.bsf
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 create mode 100644 FPGA_by_Fredi/altpll_reconfig1.inc
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 create mode 100644 FPGA_by_Fredi/altpll_reconfig1.tdf
 create mode 100644 FPGA_by_Fredi/altpll_reconfig1_pllrcfg_bju.tdf
 create mode 100644 FPGA_by_Fredi/altpll_reconfig1_pllrcfg_t4q.tdf
 create mode 100644 FPGA_by_Fredi/firebee1.asm.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.bdf
 create mode 100644 FPGA_by_Fredi/firebee1.done
 create mode 100644 FPGA_by_Fredi/firebee1.dpf
 create mode 100644 FPGA_by_Fredi/firebee1.fit.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.fit.summary
 create mode 100644 FPGA_by_Fredi/firebee1.flow.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.map.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.map.summary
 create mode 100644 FPGA_by_Fredi/firebee1.pin
 create mode 100644 FPGA_by_Fredi/firebee1.qsf
 create mode 100644 FPGA_by_Fredi/firebee1.qws
 create mode 100644 FPGA_by_Fredi/firebee1.rbf
 create mode 100644 FPGA_by_Fredi/firebee1.sof
 create mode 100644 FPGA_by_Fredi/firebee1.tan.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.tan.summary
 create mode 100644 FPGA_by_Fredi/firebee1_assignment_defaults.qdf
 create mode 100644 FPGA_by_Fredi/firebeei1.qpf
 create mode 100644 FPGA_by_Fredi/firebeei1.qws
 create mode 100644 FPGA_by_Fredi/lpm_bustri_BYT.bsf
 create mode 100644 FPGA_by_Fredi/lpm_bustri_BYT.cmp
 create mode 100644 FPGA_by_Fredi/lpm_bustri_BYT.inc
 create mode 100644 FPGA_by_Fredi/lpm_bustri_BYT.qip
 create mode 100644 FPGA_by_Fredi/lpm_bustri_BYT.vhd
 create mode 100644 FPGA_by_Fredi/lpm_bustri_LONG.bsf
 create mode 100644 FPGA_by_Fredi/lpm_bustri_LONG.cmp
 create mode 100644 FPGA_by_Fredi/lpm_bustri_LONG.inc
 create mode 100644 FPGA_by_Fredi/lpm_bustri_LONG.qip
 create mode 100644 FPGA_by_Fredi/lpm_bustri_LONG.vhd
 create mode 100644 FPGA_by_Fredi/lpm_bustri_WORD.bsf
 create mode 100644 FPGA_by_Fredi/lpm_bustri_WORD.cmp
 create mode 100644 FPGA_by_Fredi/lpm_bustri_WORD.inc
 create mode 100644 FPGA_by_Fredi/lpm_bustri_WORD.qip
 create mode 100644 FPGA_by_Fredi/lpm_bustri_WORD.vhd
 create mode 100644 FPGA_by_Fredi/lpm_counter0.bsf
 create mode 100644 FPGA_by_Fredi/lpm_counter0.cmp
 create mode 100644 FPGA_by_Fredi/lpm_counter0.qip
 create mode 100644 FPGA_by_Fredi/lpm_counter0.vhd
 create mode 100644 FPGA_by_Fredi/lpm_counter0_wave0.jpg
 create mode 100644 FPGA_by_Fredi/lpm_counter0_waveforms.html
 create mode 100644 FPGA_by_Fredi/lpm_counter1_waveforms.html
 create mode 100644 FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
 create mode 100644 FPGA_by_Fredi/lpm_latch0.bsf
 create mode 100644 FPGA_by_Fredi/lpm_latch0.cmp
 create mode 100644 FPGA_by_Fredi/lpm_latch0.qip
 create mode 100644 FPGA_by_Fredi/lpm_latch0.vhd
 create mode 100644 FPGA_by_Fredi/serv_req_info.txt
 create mode 100644 FPGA_by_Fredi/undo_redo.txt

diff --git a/FPGA_by_Fredi/Coldari1.qsf b/FPGA_by_Fredi/Coldari1.qsf
new file mode 100644
index 0000000..da581cf
--- /dev/null
+++ b/FPGA_by_Fredi/Coldari1.qsf
@@ -0,0 +1,44 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 222 10/21/2009 SJ Web Edition
+# Date created = 12:11:46  March 06, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Coldari1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name TOP_LEVEL_ENTITY Coldari1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46  MARCH 06, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION 9.1
\ No newline at end of file
diff --git a/FPGA_by_Fredi/DSP/DSP.vhd b/FPGA_by_Fredi/DSP/DSP.vhd
new file mode 100644
index 0000000..26f8e2e
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/DSP.vhd
@@ -0,0 +1,79 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:57 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY DSP IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nRSTO : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		nSRCS : INOUT STD_LOGIC;
+		nSRBLE : OUT STD_LOGIC;
+		nSRBHE : OUT STD_LOGIC;
+		nSRWE : OUT STD_LOGIC;
+		nSROE : OUT STD_LOGIC;
+		DSP_INT : OUT STD_LOGIC;
+		DSP_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END DSP;
+
+
+--  Architecture Body
+
+ARCHITECTURE DSP_architecture OF DSP IS
+
+	
+BEGIN
+	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	DSP_INT <= '0';
+	DSP_TA <= '0';
+	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	
+	
+END DSP_architecture;
diff --git a/FPGA_by_Fredi/DSP/DSP.vhd.bak b/FPGA_by_Fredi/DSP/DSP.vhd.bak
new file mode 100644
index 0000000..2d4811a
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/DSP.vhd.bak
@@ -0,0 +1,79 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:57 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY DSP IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nRSTO : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		nSRCS : OUT STD_LOGIC;
+		nSRBLE : OUT STD_LOGIC;
+		nSRBHE : OUT STD_LOGIC;
+		nSRWE : OUT STD_LOGIC;
+		nSROE : OUT STD_LOGIC;
+		DSP_INT : OUT STD_LOGIC;
+		DSP_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END DSP;
+
+
+--  Architecture Body
+
+ARCHITECTURE DSP_architecture OF DSP IS
+
+	
+BEGIN
+	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	DSP_INT <= '0';
+	DSP_TA <= '0';
+	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	
+	
+END DSP_architecture;
diff --git a/FPGA_by_Fredi/DSP/dsp56k.zip b/FPGA_by_Fredi/DSP/dsp56k.zip
new file mode 100644
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HcmV?d00001

diff --git a/FPGA_by_Fredi/DSP/src/adgen_stage.vhd b/FPGA_by_Fredi/DSP/src/adgen_stage.vhd
new file mode 100644
index 0000000..1ff7e59
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/adgen_stage.vhd
@@ -0,0 +1,216 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity adgen_stage is port(
+	activate_adgen    : in  std_logic;
+	activate_x_mem    : in  std_logic;
+	activate_y_mem    : in  std_logic;
+	activate_l_mem    : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	optional_ea_word  : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	adgen_mode_a      : in  adgen_mode_type;
+	adgen_mode_b      : in  adgen_mode_type;
+	address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+	address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+	wr_R_port_A_valid : out std_logic;
+	wr_R_port_A       : out addr_wr_port_type;
+	wr_R_port_B_valid : out std_logic;
+	wr_R_port_B       : out addr_wr_port_type
+);
+end entity;
+
+
+architecture rtl of adgen_stage is
+
+	signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0);
+
+
+begin
+
+	address_out_x <= address_out_x_int;
+
+	address_generator_X: process(activate_adgen, instr_word, register_file, adgen_mode_a) is
+		variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable op1         : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable addr_mod    : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0);
+		variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0);
+		variable bit_set     : std_logic;
+	begin
+		r_reg_local := register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8))));
+		n_reg_local := register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8))));
+		m_reg_local := register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8))));
+
+		-- select the operands for the calculation
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  addr_mod := unsigned(- signed(n_reg_local));
+			-- (Rn) + Nn
+			when POST_PLUS_N => addr_mod :=   n_reg_local;
+			-- (Rn)-
+			when POST_MIN_1 =>  addr_mod := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when NOP =>         addr_mod := (others => '0');
+			-- (Rn + Nn)
+			when INDEXED_N =>   addr_mod := n_reg_local;
+			-- -(Rn)
+			when PRE_MIN_1 =>   addr_mod := (others => '1'); -- - 1
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    addr_mod := (others => '0');
+			when IMMEDIATE =>   addr_mod := (others => '0');
+		end case;
+
+		op1 := r_reg_local;
+		op2 := addr_mod;
+		-- linear addressing
+		if m_reg_local = 2**BW_ADDRESS-1 then 
+			op1 := r_reg_local;
+			op2 := addr_mod;
+		-- bit reverse operation
+		elsif m_reg_local = 0 then
+			-- reverse the input to the adder bit wise
+			-- so we just need to use a single adder
+			for i in 0 to BW_ADDRESS-1 loop
+				op1(BW_ADDRESS - 1 - i) := r_reg_local(i);
+				op2(BW_ADDRESS - 1 - i) := addr_mod(i);
+			end loop;
+		-- modulo arithmetic
+		else
+			bit_set := '0';
+			for i in BW_ADDRESS-1 downto 0 loop
+				if m_reg_local(i) = '1' then
+					bit_set := '1';
+				end if;
+				if bit_set = '1' then
+					modulo_bitmask(i) := '0';
+				else
+					modulo_bitmask(i) := '1';
+				end if;
+			end loop;
+		end if;
+
+		new_r_reg_interm := op1 + op2;
+
+		new_r_reg := new_r_reg_interm;
+		-- linear addressing
+		if m_reg_local = 2**BW_ADDRESS-1 then 
+			new_r_reg := new_r_reg_interm;
+		-- bit reverse operation
+		elsif m_reg_local = 0 then
+			for i in 0 to BW_ADDRESS-1 loop
+				new_r_reg(BW_ADDRESS - 1 - i) := new_r_reg_interm(i);
+			end loop;
+		else
+
+		end if;
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		-- LUA instructions DO NOT UPDATE the source register!!
+		if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then
+			wr_R_port_A_valid <= '0';
+		else
+			wr_R_port_A_valid <= '1';
+		end if;
+		wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8));
+		wr_R_port_A.reg_value  <= new_r_reg;
+
+		-- select the output of the AGU
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  address_out_x_int <= r_reg_local;
+			-- (Rn) + Nn
+			when POST_PLUS_N => address_out_x_int <= r_reg_local;
+			-- (Rn)-
+			when POST_MIN_1 =>  address_out_x_int <= r_reg_local;
+			-- (Rn)+
+			when POST_PLUS_1 => address_out_x_int <= r_reg_local;
+			-- (Rn)
+			when NOP =>         address_out_x_int <= r_reg_local;
+			-- (Rn + Nn)
+			when INDEXED_N =>   address_out_x_int <= new_r_reg;
+			-- -(Rn)
+			when PRE_MIN_1 =>   address_out_x_int <= new_r_reg;
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0));
+			when IMMEDIATE =>   address_out_x_int <= r_reg_local; -- Done externally, value never used
+		end case;
+		-- LUA instructions only use the updated address!
+		if instr_array = INSTR_LUA then
+			address_out_x_int <= new_r_reg;
+		end if;
+
+	end process address_generator_X;
+
+	address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word,
+	                             register_file, adgen_mode_b, address_out_x_int) is
+		variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+	begin
+		r_reg_local := register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+		n_reg_local := register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+		m_reg_local := register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+
+		-- select the operands for the calculation
+		case adgen_mode_b is
+			-- (Rn) + Nn
+			when POST_PLUS_N => op2 :=   n_reg_local;
+			-- (Rn)-
+			when POST_MIN_1  => op2 := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => op2 := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when others      => op2 := (others => '0');
+		end case;
+
+		new_r_reg := r_reg_local + op2;
+		-- TODO: USE modifier register!
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		if adgen_mode_b = NOP then
+			wr_R_port_B_valid <= '0';
+		else
+			wr_R_port_B_valid <= '1';
+		end if;
+		wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13));
+		wr_R_port_B.reg_value  <= new_r_reg;
+
+		-- the address for the y memory is calculated in the first AGU if the x memory is not accessed!
+		-- so use the other output as address output for the y memory!
+		-- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!)
+		if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then
+			address_out_y <= address_out_x_int;
+		-- in any other case use the locally computed value
+		else
+			-- select the output of the AGU
+			case adgen_mode_b is
+				-- (Rn) + Nn
+				when POST_PLUS_N => address_out_y <= r_reg_local;
+				-- (Rn)-
+				when POST_MIN_1  => address_out_y <= r_reg_local;
+				-- (Rn)+
+				when POST_PLUS_1 => address_out_y <= r_reg_local;
+				-- (Rn)
+				when others      => address_out_y <= r_reg_local;
+			end case;
+		end if;
+	end process address_generator_Y;
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/constants_pkg.vhd b/FPGA_by_Fredi/DSP/src/constants_pkg.vhd
new file mode 100644
index 0000000..4b8122d
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/constants_pkg.vhd
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+package constants_pkg is
+
+	-------------------------
+	-- Flags in CCR register
+	-------------------------
+	constant C_FLAG : natural := 0;
+	constant V_FLAG : natural := 1;
+	constant Z_FLAG : natural := 2;
+	constant N_FLAG : natural := 3;
+	constant U_FLAG : natural := 4;
+	constant E_FLAG : natural := 5;
+	constant L_FLAG : natural := 6;
+	constant S_FLAG : natural := 7;
+
+	-------------------
+	-- Pipeline stages
+	-------------------
+	constant ST_FETCH  : natural := 0;
+	constant ST_FETCH2 : natural := 1;
+	constant ST_DECODE : natural := 2;
+	constant ST_ADGEN  : natural := 3;
+	constant ST_EXEC   : natural := 4;
+
+	----------------------
+	-- Activation signals
+	----------------------
+	constant ACT_ADGEN       : natural := 0; -- Run the address generator
+	constant ACT_ALU         : natural := 1; -- Activation of ALU results in modification of the status register
+	constant ACT_EXEC_BRA    : natural := 2; -- Branch (in execute stage)
+	constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage)
+	constant ACT_EXEC_LOOP   : natural := 4; -- Loop instruction (REP, DO)
+	constant ACT_X_MEM_RD    : natural := 5; -- Init read from X memory
+	constant ACT_Y_MEM_RD    : natural := 6; -- Init read from Y memory
+	constant ACT_P_MEM_RD    : natural := 7; -- Init read from P memory
+	constant ACT_X_MEM_WR    : natural := 8; -- Init write to  X memory
+	constant ACT_Y_MEM_WR    : natural := 9; -- Init write to  Y memory
+	constant ACT_P_MEM_WR    : natural := 10; -- Init write to P memory
+	constant ACT_REG_RD      : natural := 11; -- Read from register (6 bit addressing)
+	constant ACT_REG_WR      : natural := 12; -- Write to register (6 bit addressing)
+	constant ACT_IMM_8BIT    : natural := 13; -- 8 bit  immediate operand (in instruction word)
+	constant ACT_IMM_12BIT   : natural := 14; -- 12 bit immediate operand (in instruction word)
+	constant ACT_IMM_LONG    : natural := 15; -- 24 bit immediate operant (in optional instruction word)
+	constant ACT_X_BUS_RD    : natural := 16; -- Read  data via X-bus (from x0,x1,a,b)
+	constant ACT_X_BUS_WR    : natural := 17; -- Write data via X-bus (to   x0,x1,a,b)
+	constant ACT_Y_BUS_RD    : natural := 18; -- Read  data via Y-bus (from y0,y1,a,b)
+	constant ACT_Y_BUS_WR    : natural := 19; -- Write data via Y-bus (to   y0,y1,a,b)
+	constant ACT_L_BUS_RD    : natural := 20; -- Read  data via L-bus (from a10, b10,x,y,a,b,ab,ba)
+	constant ACT_L_BUS_WR    : natural := 21; -- Write data via L-bus (to   a10, b10,x,y,a,b,ab,ba)
+	constant ACT_BIT_MOD_WR  : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG)
+	constant ACT_REG_WR_CC   : natural := 23; -- Write to register file conditionally (Tcc)
+	constant ACT_ALU_WR_CC   : natural := 24; -- Write ALU result conditionally (Tcc)
+	constant ACT_NORM        : natural := 25; -- NORM instruction needs special handling
+
+end package constants_pkg;
diff --git a/FPGA_by_Fredi/DSP/src/decode_stage.vhd b/FPGA_by_Fredi/DSP/src/decode_stage.vhd
new file mode 100644
index 0000000..0c62149
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/decode_stage.vhd
@@ -0,0 +1,1221 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity decode_stage is port(
+	activate_dec    : in  std_logic;
+	instr_word      : in  std_logic_vector(23 downto 0);
+	dble_word_instr : out std_logic;
+	instr_array     : out instructions_type;
+	act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	reg_wr_addr     : out std_logic_vector(5 downto 0);
+	reg_rd_addr     : out std_logic_vector(5 downto 0);
+	x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	l_bus_addr      : out std_logic_vector(2 downto 0); 
+	adgen_mode_a    : out adgen_mode_type;
+	adgen_mode_b    : out adgen_mode_type;
+	alu_ctrl        : out alu_ctrl_type
+);
+end entity;
+
+
+architecture rtl of decode_stage is
+
+	signal instr_array_int : instructions_type;
+--	signal activate_pm_int : std_logic;
+	type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y);
+	-- SINGLE_X       : MMMRRR
+	-- SINGLE_X_SHORT :  MMRRR
+	-- DOUBLE_X_Y     : mmrrMMRRR
+	signal adgen_bittype : adgen_bittype_type;
+
+	signal ea_extension_available : std_logic;
+
+	signal alu_tcc_decoded : std_logic;
+	signal alu_div_decoded : std_logic;
+	signal alu_norm_decoded : std_logic;
+
+begin
+
+
+	-- output the decoded instruction
+	instr_array <= instr_array_int;
+
+	-- calculate whether this is a double word instruction
+	dble_word_instr <= '1' when ea_extension_available = '1'  or 
+	                            instr_array_int = INSTR_DO    or 
+	                            instr_array_int = INSTR_JCLR  or
+	                            instr_array_int = INSTR_JSCLR or
+	                            instr_array_int = INSTR_JSET  or
+	                            instr_array_int = INSTR_JSSET else
+	                   '0';
+
+	alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded,
+	                                 alu_div_decoded, alu_norm_decoded) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+	begin
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+		
+		alu_ctrl.mul_op1 <= (others => '0');
+		alu_ctrl.mul_op2 <= (others => '0');
+		alu_ctrl.rotate <= '0';
+		alu_ctrl.div_instr <= '0';
+		alu_ctrl.norm_instr <= '0';
+		alu_ctrl.shift_src <= '0';
+		alu_ctrl.shift_src_sign <= (others => '0');
+		alu_ctrl.shift_mode <= ZEROS;
+		alu_ctrl.add_src_stage_1 <= (others => '0');
+		alu_ctrl.add_src_stage_2 <= (others => '0');
+		alu_ctrl.add_src_sign    <= (others => '0');
+		alu_ctrl.logic_function  <= (others => '0');
+		alu_ctrl.word_24_update  <= '0';
+		alu_ctrl.rounding_used   <= (others => '0');
+		alu_ctrl.store_result    <= '0';
+		for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C)
+			alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH;
+		end loop;
+		alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations
+
+		-- check wether instruction that allows parallel moves 
+		-- has to be decoded, then it is an ALU operation in the 8 LSBs
+		-- Only exceptions are DIV, NORM, and Tcc
+		if instr_word_var(23 downto 20) /= "0000" then
+			-- ABS
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- source/dst are the same register 
+				alu_ctrl.shift_src_sign <= "10";  -- the sign of the operand depends on the operand 
+				                                  -- negative operand will negate the content of the accu as
+				                                  -- needed by the ABS instruction
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.store_result <= '1';     -- store the result
+				-- set all flags but carry
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "10"; -- add carry to result of addition
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADD
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- AND / OR / EOR
+			if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and
+			                                          instr_word_var(2 downto 0) = "010" or -- or
+				                                      instr_word_var(2 downto 0) = "011") then -- eor
+				alu_ctrl.logic_function <= instr_word_var(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+				alu_ctrl.word_24_update <= '1';  -- only accumulator bits 47 downto 24 affected?
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- ASL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ASR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+--				alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+--				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				-- set all flags, V-flag will be cleared due to shifting
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CLR
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- CMP
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CMPM
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+		       instr_word_var(2 downto 0) = "111" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "10";          -- with the sign dependant sign (magnitude!)
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "10"; -- with sign dependant sign (magnitude!)
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- MPY, MPYR, MAC, MACR
+			if instr_word_var(7) = '1' then
+				case instr_word_var(6 downto 4) is
+					when "000"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0
+					when "001"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0
+					when "010"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0
+					when "011"  => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0
+					when "100"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1
+					when "101"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0
+					when "110"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0
+					when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1
+				end case;
+				alu_ctrl.store_result    <= '1';  -- store result in accu
+				alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder!
+				alu_ctrl.add_src_sign    <= '0' & instr_word_var(2); -- select +/-
+				alu_ctrl.rounding_used   <= '0' & instr_word_var(0); -- rounding is determined by that bit!
+				if instr_word_var(1) = '0' then -- MPY(R)
+					alu_ctrl.shift_mode <= ZEROS;
+				else -- MAC(R)
+					alu_ctrl.shift_mode <= NO_SHIFT;
+					alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+					alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				end if;
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NEG
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+--				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+--				alu_ctrl.shift_src_sign <= "01";          -- with negative sign
+				-- Read Accu
+				alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register
+				alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NOT
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.logic_function  <= instr_word_var(2 downto 0); -- select not operation
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- RND
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "01"; -- normal rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ROL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- ROR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- SBC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "11"; -- subtract carry
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUB
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- TFR 
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- do not set any flag at all!
+			end if;
+			-- TST
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;          -- no shift
+				alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+				alu_ctrl.shift_src_sign  <= "00";         -- sign unchanged
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+		end if; -- Parallel move ALU instructions
+
+		-- Tcc
+		if alu_tcc_decoded = '1' then
+			-- Read source
+			if instr_word_var(6) = '1' then
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			else
+				alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+			end if;
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			-- The .store_result flag is generated in the execute stage
+			-- depending on the condition codes
+			-- do not set any flag at all!
+		end if;
+--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--shift_src  : std_logic; -- a,b
+--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+--shift_mode : alu_shift_mode;
+--add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+--add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+--add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction!
+--logic_function : std_logic_vector(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+--word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+--rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+--store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+--dst_accu       : std_logic; -- 0: a, 1: b
+		-- DIV
+		if alu_div_decoded = '1' then
+			alu_ctrl.store_result    <= '1';          -- do store the result
+			-- shifter operation
+			alu_ctrl.shift_mode <= SHIFT_LEFT;        -- shift left
+			alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+			alu_ctrl.div_instr  <= '1';               -- this is THE div instruction, special handling needed
+			-- source operand loading
+			alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			alu_ctrl.add_src_sign    <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] 
+			                                  -- if 1: positive, if 0: negative
+			alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY;
+		end if;
+		-- NORM
+		if alu_norm_decoded = '1' then
+			-- set all alu-ctrl signals to ASL/ASR already here
+			-- depending on the condition code registers the flags
+			-- will be completed in the execute stage
+			alu_ctrl.norm_instr <= '1';
+			-- Read accu
+			--alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT;
+			alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+			alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+			-- Read S
+			alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+			alu_ctrl.add_src_sign    <= "00"; -- with original sign
+			alu_ctrl.store_result    <= '1';  -- store the result
+			alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+			-- set all flags, V-flag will be cleared due to shifting
+			for i in 0 to 7 loop
+				alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+			end loop;
+
+		end if;
+	end process;
+
+
+	instruction_decoder: process(instr_word, activate_dec) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+		procedure activate_AGU is
+		begin
+			-- check for immediate long addressing
+			if instr_word_var(13 downto 8) = "110100" then
+				act_array(ACT_IMM_LONG) <= '1';
+				act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+				act_array(ACT_Y_MEM_RD) <= '0';
+				act_array(ACT_X_MEM_WR) <= '0';
+				act_array(ACT_Y_MEM_WR) <= '0';
+			else
+				act_array(ACT_ADGEN) <= '1';
+			end if;
+		end procedure activate_AGU;
+	begin
+		instr_array_int <= INSTR_NOP;
+		act_array   <= (others => '0');
+		adgen_bittype <= NOP;
+		reg_rd_addr <= (others => '0');
+		reg_wr_addr <= (others => '0');
+		x_bus_rd_addr <= (others => '0');
+		x_bus_wr_addr <= (others => '0');
+		y_bus_rd_addr <= (others => '0');
+		y_bus_wr_addr <= (others => '0');
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+
+		alu_tcc_decoded <= '0';
+		alu_div_decoded <= '0';
+		alu_norm_decoded <= '0';
+
+		-- in case the decoding is not activated we insert a nop
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+
+		if instr_word_var(23 downto 16) = X"00" then
+			case instr_word_var(15 downto 0) is
+				when X"0000" => instr_array_int <= INSTR_NOP;
+				when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0005" => instr_array_int <= INSTR_ILLEGAL;
+				when X"0006" => instr_array_int <= INSTR_SWI;
+				when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0084" => instr_array_int <= INSTR_RESET;
+				when X"0086" => instr_array_int <= INSTR_WAIT;
+				when X"0087" => instr_array_int <= INSTR_STOP;
+				when X"008C" => instr_array_int <= INSTR_ENDDO;
+				                act_array(ACT_EXEC_LOOP) <= '1';
+				when others =>
+					act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register
+					if instr_word_var(7 downto 2) = "101110" then
+						instr_array_int <= INSTR_ANDI;
+					elsif instr_word_var(7 downto 2) = "111110" then
+						instr_array_int <= INSTR_ORI;
+					end if;
+			end case;
+		end if;
+		---------------------------------------------------------
+		-- DIV and NORM
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"01" then
+			-- DIV
+			if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then
+				alu_div_decoded <= '1';
+				act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+			end if;
+			-- NORM
+			if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and
+		   	   instr_word_var(2 downto 0) = "101" then
+				alu_norm_decoded <= '1';
+				act_array(ACT_NORM) <= '1'; -- NORM instruction decoded, 
+				                            -- special handling in exec-stage is caused
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- Tcc
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and
+		       instr_word_var(2 downto 0) = "000" then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and 
+		   	      instr_word_var(7) = '0' then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+				act_array(ACT_REG_WR_CC) <= '1';
+				reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn
+				reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- MOVEC and LUA instruction with registers
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"04" then
+			act_array(ACT_REG_WR) <= '1';
+			-- LUA instruction
+			if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then
+				instr_array_int <= INSTR_LUA;
+				act_array(ACT_ADGEN) <= '1';
+				adgen_bittype <= SINGLE_X_SHORT;
+				reg_wr_addr <= instr_word_var(5 downto 0);
+			end if;
+			-- MOVEC instruction (S1, D2) or (S2, D1)
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then
+				instr_array_int <= INSTR_MOVEC;
+				act_array(ACT_REG_RD) <= '1';
+				-- Write D1
+				if instr_word_var(15) = '1' then
+					reg_wr_addr <= instr_word_var(5 downto 0);
+					reg_rd_addr <= instr_word_var(13 downto 8);
+				-- Read S1
+				else
+					reg_wr_addr <= instr_word_var(13 downto 8);
+					reg_rd_addr <= instr_word_var(5 downto 0);
+				end if;
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with memory access/absolute address
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and 
+		   instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+			
+			instr_array_int <= INSTR_MOVEC;
+			-- read from memory, write to register
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				-- X Memory read?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- write to memory, read register
+			else
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				-- X Memory write?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- check for immediate long addressing
+				if instr_word_var(13 downto 8) = "110100" then
+					act_array(ACT_IMM_LONG) <= '1';
+					act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+					act_array(ACT_Y_MEM_RD) <= '0';
+					act_array(ACT_X_MEM_WR) <= '0';
+					act_array(ACT_Y_MEM_WR) <= '0';
+				else
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with immediate
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then
+			instr_array_int <= INSTR_MOVEC;
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= instr_word_var(5 downto 0);
+		end if;
+		---------------------------------
+		-- REP or DO loop?
+		---------------------------------
+		if instr_word_var(23 downto 16) = X"06" then
+			-- Instruction encoding is the same for both except of this bit
+			if instr_word_var(5) = '1' then
+				instr_array_int <= INSTR_REP;
+			else
+				instr_array_int <= INSTR_DO;
+			end if;
+			act_array(ACT_EXEC_LOOP) <= '1';
+			-- Init reading of loop counter from memory
+			if instr_word_var(15) = '0' and instr_word_var(7) = '0' then
+				-- X/Y: ea?
+				if instr_word_var(14) = '1' then
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+				-- X/Y: aa?
+				-- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not!
+				-- If not the absolute address stored in the instruction word is used.
+				-------
+				-- only a single memory access is required
+				adgen_bittype <= SINGLE_X;
+				-- X/Y as source?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				else 
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then
+				-- S (register as source)
+				reg_rd_addr <= instr_word_var(13 downto 8);
+				act_array(ACT_REG_RD) <= '1';
+				-- #xxx ,12 bit immediate
+			elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then
+				act_array(ACT_IMM_12BIT) <= '1';
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEM (Program memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = X"07" then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_RD) <= '1';
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_WR) <= '1';
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEP (Peripheral memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = "0000100-" then
+			-- TODO?? Why parallel moves in software model??
+			case instr_word_var(15 downto 0) is
+--				when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1';
+				when others =>
+			end case;
+		end if;
+		-- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR
+		if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then
+
+			reg_rd_addr <= instr_word_var(13 downto 8);
+			reg_wr_addr <= instr_word_var(13 downto 8);
+
+			if instr_word_var(16) = '0' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCLR;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BSET;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSET;
+				end if;
+			elsif instr_word_var(16) = '1' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCHG;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BTST;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JSCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSSET;
+				end if;
+			end if;
+			if instr_word_var(7) = '1' then
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+
+			-- memory access?
+			if instr_word_var(15) = '0' then
+				-- X:
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_X_MEM_WR) <= '1';
+					end if;
+				-- Y:
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_Y_MEM_WR) <= '1';
+					end if;
+				end if;
+			end if;
+
+			case instr_word_var(15 downto 14) is
+				-- X:/Y: aa
+				when "00" =>
+
+				-- X:/Y: ea
+				when "01" =>
+					act_array(ACT_ADGEN) <= '1';
+					adgen_bittype <= SINGLE_X;
+
+				-- X:/Y: pp 
+				-- TODO!
+				when "10" =>
+
+				when others => -- "11"
+					if instr_word_var(7 downto 0) = "10000000" then
+						-- JMP/JSR ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JMP;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSR;
+						end if;
+					elsif instr_word_var(7 downto 4) = "1010" then
+						-- JCC/JSCC ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JCC;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSCC;
+						end if;
+					-- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D
+					else
+						act_array(ACT_REG_RD) <= '1';
+						-- if not a jump instruction and not BTST write back the result
+						if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+							act_array(ACT_REG_WR) <= '1';
+						end if;
+					end if;
+			end case;
+		end if;
+		-- JMP xxx (absoulute short)
+		if instr_word_var(23 downto 16) = X"0C" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JMP;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JSR xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0D" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JSR;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0E" then
+			instr_array_int <= INSTR_JCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+		-- JSCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0F" then
+			instr_array_int <= INSTR_JSCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+
+		------------------------------------------------
+		-- PARALLEL MOVE SECTION!!
+		------------------------------------------------
+		-- Here are the ALU operations that allow for parallel moves
+		if instr_word_var(23 downto 20) /= "0000" then
+			act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+		end if;
+		-- PM: I
+		if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(20 downto 16);
+		end if;
+		-- PM: R
+		if instr_word_var(23 downto 18) = "001000" then
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(12 downto  8);
+			act_array(ACT_REG_RD) <= '1';
+			reg_rd_addr <= '0' & instr_word_var(17 downto 13);
+		end if;
+		-- PM: U
+		if instr_word_var(23 downto 13) = "00100000010" then
+			act_array(ACT_ADGEN) <= '1';
+			adgen_bittype <= SINGLE_X_SHORT;
+		end if;
+		-- PM: X or PM:Y
+		if instr_word_var(23 downto 22) = "01" and 
+		   -- Check whether L: type parallel move. If so do not enter this branch!
+		   not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory read?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory write?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-- PM: X:R or R:Y (Class I)
+		if instr_word_var(23 downto 20) = "0001" then
+			adgen_bittype <= SINGLE_X;
+			-- X:R
+			if instr_word_var(14) = '0' then
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				y_bus_rd_addr <= '1' & instr_word_var(17);
+				y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs!
+				-- S2,D2 in any case!
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					act_array(ACT_X_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_X_MEM_WR) <= '1';
+					act_array(ACT_X_BUS_RD) <= '1';
+				end if;
+			-- R:Y
+			elsif instr_word_var(14) = '1' then
+				x_bus_rd_addr <= '1' & instr_word_var(19);
+				x_bus_wr_addr <= '0' & instr_word_var(18);
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				-- S1,D1 in any case!
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_Y_MEM_RD) <= '1';
+					act_array(ACT_Y_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_Y_MEM_WR) <= '1';
+					act_array(ACT_Y_BUS_RD) <= '1';
+				end if;
+
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: X:R or R:Y (Class II)
+		if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then
+			act_array(ACT_REG_RD) <= '1';
+			-- X:R
+			if instr_word_var(15) = '0' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory
+				x_bus_rd_addr <= "00"; -- read x0
+				x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+			-- R:Y
+			elsif instr_word_var(15) = '1' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory
+				y_bus_rd_addr <= "00"; -- read y0
+				y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: L:
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+		if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then
+			-- Read S?
+			if instr_word_var(15) = '0' then
+				act_array(ACT_L_BUS_RD) <= '1';
+				act_array(ACT_X_MEM_WR) <= '1';
+				act_array(ACT_Y_MEM_WR) <= '1';
+			else -- Write D
+				act_array(ACT_L_BUS_WR) <= '1';
+				act_array(ACT_X_MEM_RD) <= '1';
+				act_array(ACT_Y_MEM_RD) <= '1';
+			end if;
+			if instr_word_var(14) = '1' then
+				adgen_bittype <= SINGLE_X;
+				activate_AGU;
+			else
+				-- L:aa automatically performed in ADGEN stage
+			end if;
+		end if;
+		-- PM: X: Y:
+		if instr_word_var(23) = '1' then
+			adgen_bittype <= DOUBLE_X_Y;
+			-- No immediate value allowed, so activate in any case!
+			act_array(ACT_ADGEN) <= '1';
+			-- S1, X:
+			if instr_word_var(15) = '0' then
+				act_array(ACT_X_BUS_RD) <= '1';
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_WR) <= '1'; 
+			-- X:, D1
+			else
+				act_array(ACT_X_BUS_WR) <= '1';
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_RD) <= '1'; 
+			end if;
+			-- S2, Y:
+			if instr_word_var(22) = '0' then
+				act_array(ACT_Y_BUS_RD) <= '1';
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_WR) <= '1'; 
+			-- Y:, D2
+			else
+				act_array(ACT_Y_BUS_WR) <= '1';
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_RD) <= '1'; 
+			end if;
+		end if;
+	end process;
+
+	adgen_decoder: process(adgen_bittype, instr_word) is
+	begin
+		adgen_mode_a <= NOP;
+		adgen_mode_b <= NOP;
+		ea_extension_available <= '0';
+
+		case adgen_bittype is
+			when SINGLE_X =>
+				case instr_word(13 downto 11) is
+					when "000" => adgen_mode_a <= POST_MIN_N;
+					when "001" => adgen_mode_a <= POST_PLUS_N;
+					when "010" => adgen_mode_a <= POST_MIN_1;
+					when "011" => adgen_mode_a <= POST_PLUS_1;
+					when "100" => adgen_mode_a <= NOP;
+					when "101" => adgen_mode_a <= INDEXED_N;
+					when "111" => adgen_mode_a <= PRE_MIN_1;
+					when "110" => 
+						if instr_word(10 downto 8) = "000" then
+							adgen_mode_a <= ABSOLUTE;
+							ea_extension_available <= '1';
+						elsif instr_word(10 downto 8) = "100" then
+							adgen_mode_a <= IMMEDIATE;
+							ea_extension_available <= '1';
+						else 
+							adgen_mode_a <= NOP; -- INVALID OPCODE!
+						end if;
+					when others =>
+				end case;
+			when SINGLE_X_SHORT =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= POST_MIN_N;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others => 
+				end case;
+			when DOUBLE_X_Y =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= NOP;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others =>
+				end case;
+				case instr_word(21 downto 20) is
+					when "00" => adgen_mode_b <= NOP;
+					when "01" => adgen_mode_b <= POST_PLUS_N;
+					when "10" => adgen_mode_b <= POST_MIN_1;
+					when "11" => adgen_mode_b <= POST_PLUS_1;
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process adgen_decoder;
+
+end architecture rtl;
+
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_alu.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_alu.vhd
new file mode 100644
index 0000000..9f3c3b9
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_alu.vhd
@@ -0,0 +1,603 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_alu is port(
+	alu_activate      : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	alu_ctrl          : in  alu_ctrl_type;
+	register_file     : in  register_file_type;
+	addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+	addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_accu       : out std_logic;
+	dst_accu          : out std_logic;
+	modified_accu     : out signed(55 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+architecture rtl of exec_stage_alu is 
+
+	signal alu_shifter_out          : signed(55 downto 0);
+	signal alu_shifter_carry_out    : std_logic;
+	signal alu_shifter_overflow_out : std_logic;
+
+	signal alu_logic_conj        : signed(55 downto 0);
+	signal alu_multiplier_out    : signed(55 downto 0);
+	signal alu_src_op            : signed(55 downto 0);
+	signal alu_add_result        : signed(56 downto 0);
+	signal alu_add_carry_out     : std_logic;
+	signal alu_post_adder_result : signed(56 downto 0);
+
+	signal scaling_mode          : std_logic_vector(1 downto 0);
+
+	signal modified_accu_int     : signed(55 downto 0);
+
+	signal norm_instr_asl  : std_logic;
+	signal norm_instr_asr  : std_logic;
+	signal norm_instr_nop  : std_logic;
+	signal norm_update_ccr : std_logic; 
+
+begin
+
+
+	-- store calculated value?
+	modify_accu <= alu_ctrl.store_result;
+	modified_accu <= modified_accu_int;
+	-- for the norm instruction we first need to determine whether we have to
+	-- update the CCR register or not
+	modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else
+	             norm_update_ccr;
+	dst_accu <= alu_ctrl.dst_accu;
+
+	scaling_mode <= register_file.sr(11 downto 10);
+
+
+	calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out,
+	                           alu_post_adder_result, modified_accu_int, alu_add_carry_out) is
+	begin
+		-- by default do not modify the flags in the status register
+		modified_sr <= register_file.sr;
+		
+		-- Carry flag generation
+		-------------------------
+		case alu_ctrl.ccr_flags_ctrl(C_FLAG) is
+			when CLEAR  => modified_sr(C_FLAG) <= '0';
+			when SET    => modified_sr(C_FLAG) <= '1';
+			when MODIFY =>
+				-- the carry flag can stem from the shifter or from the post adder
+				-- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR)
+				-- take the carry flag from the shifter, else from the post adder
+				if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and
+				    alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting?
+					modified_sr(C_FLAG) <= alu_shifter_carry_out;
+				elsif alu_ctrl.div_instr = '1' then
+					modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55));
+				else
+--					modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57));
+					modified_sr(C_FLAG) <= alu_add_carry_out;
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Overflow flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(V_FLAG) is
+			when CLEAR  => modified_sr(V_FLAG) <= '0';
+			when SET    => modified_sr(V_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+			   	   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(V_FLAG) <= '1';
+				else
+					modified_sr(V_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+		
+		-- Zero flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is
+			when CLEAR  => modified_sr(Z_FLAG) <= '0';
+			when SET    => modified_sr(Z_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is zero set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or
+				   (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto  0) = 0) then
+					modified_sr(Z_FLAG) <= '1';
+				else
+					modified_sr(Z_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Negative flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(N_FLAG) is
+			when CLEAR  => modified_sr(N_FLAG) <= '0';
+			when SET    => modified_sr(N_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is negative set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if alu_ctrl.word_24_update = '1' then
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(47));
+				else
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(55));
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Unnormalized flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(U_FLAG) is
+			when CLEAR  => modified_sr(U_FLAG) <= '0';
+			when SET    => modified_sr(U_FLAG) <= '1';
+			when MODIFY =>
+				-- Set unnormalized bit according to the scaling mode
+				if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or
+				   (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or
+				   (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then
+					modified_sr(U_FLAG) <= '1';
+				else
+					modified_sr(U_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Extension flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(E_FLAG) is
+			when CLEAR  => modified_sr(E_FLAG) <= '0';
+			when SET    => modified_sr(E_FLAG) <= '1';
+			when MODIFY =>
+				-- Set extension flag by default
+				modified_sr(E_FLAG) <= '1';
+				-- Clear extension flag according to the scaling mode
+				case scaling_mode is
+					when "00" =>
+						if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "01" =>
+						if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "10" =>
+						if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when others =>
+						modified_sr(E_FLAG) <= '0';
+				end case;
+			when others => -- Don't touch
+		end case;
+
+		-- Limit flag generation (equals overflow flag generaton!)
+		-- Clearing of the Limit flag has to be done by the user!
+		-----------------------------------------------------------
+		case alu_ctrl.ccr_flags_ctrl(L_FLAG) is
+			when CLEAR  => modified_sr(L_FLAG) <= '0';
+			when SET    => modified_sr(L_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+			   	   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(L_FLAG) <= '1';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Scaling flag generation (DSP56002 and up)
+		--------------------------------------------
+		-- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB
+
+	end process;
+
+
+	src_operand_select: process(register_file, alu_ctrl) is
+	begin
+		-- decoding according similar to JJJ representation
+		case alu_ctrl.add_src_stage_1 is 
+			when "000" =>
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.a;
+				else
+					alu_src_op <= register_file.b;
+				end if;
+			when "001" => -- A,B or B,A
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.b;
+				else
+					alu_src_op <= register_file.a;
+				end if;
+			when "010" =>  -- X
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto  0) <= register_file.x1 & register_file.x0;
+			when "011" =>  -- Y
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto  0) <= register_file.y1 & register_file.y0;
+			when "100" =>  -- x0
+				alu_src_op(55 downto 48) <= (others => register_file.x0(23));
+				alu_src_op(47 downto 24) <= register_file.x0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "101" =>  -- y0
+				alu_src_op(55 downto 48) <= (others => register_file.y0(23));
+				alu_src_op(47 downto 24) <= register_file.y0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "110" =>  -- x1
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto 24) <= register_file.x1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "111" =>  -- y1
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto 24) <= register_file.y1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when others =>
+		end case;
+	end process;
+
+	alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is
+	begin
+		alu_logic_conj <= alu_shifter_out;
+		case alu_ctrl.logic_function is
+			when "110" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24);
+			when "010" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or  alu_src_op(47 downto 24);
+			when "011" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24);
+			when "111" =>
+				alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24);
+			when others =>
+		end case;
+	end process;
+
+	alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is
+		variable add_src_op_1 : signed(56 downto 0);
+		variable add_src_op_2 : signed(56 downto 0);
+		variable carry_const  : signed(56 downto 0);
+		variable alu_shifter_out_57 : signed(56 downto 0);
+		variable alu_add_result_58  : signed(57 downto 0);
+		variable alu_add_result_interm : signed(56 downto 0);
+		variable invert_carry_flag : std_logic;
+	begin
+
+		-- by default do not invert the carry
+		invert_carry_flag := '0';
+
+		-- determine whether to use multiplier output, the operand defined above, or zeros!
+		-- resizing is done here already. Like that we can see whether an overflow
+		-- occurs due to negating the source operand
+		case alu_ctrl.add_src_stage_2 is
+			when "00" => add_src_op_1 := (others => '0');
+			when "10" => add_src_op_1 := resize(alu_multiplier_out, 57);
+			when others => add_src_op_1 := resize(alu_src_op, 57);
+		end case;
+
+		-- determine the sign for the 1st operand!
+		case alu_ctrl.add_src_sign is
+			-- normal operation
+			when "00" => add_src_op_1 := add_src_op_1;
+			-- negative sign
+			when "01" => add_src_op_1 := - add_src_op_1;
+			             invert_carry_flag := not invert_carry_flag;
+			-- change according to sign
+			-- performs - | accu | for the CMPM instruction
+			when "10" =>
+				-- we subtract in any case, so invert the carry!
+				invert_carry_flag := not invert_carry_flag;
+				if add_src_op_1(55) = '0' then 
+					add_src_op_1 := - add_src_op_1;
+				else
+					add_src_op_1 :=   add_src_op_1;
+				end if;
+			-- div instruction!
+			-- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative
+			-- add_src_op_1 holds S[23] (sign extension!)
+			when others => 
+				if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or
+			   	   (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then 
+					add_src_op_1 :=   add_src_op_1;
+				else
+					add_src_op_1 := - add_src_op_1;
+--					invert_carry_flag := not invert_carry_flag;
+				end if;
+		end case;
+
+		alu_shifter_out_57 := resize(alu_shifter_out, 57);
+
+		-- determine the sign for the 2nd operand (coming from the shifter)!
+		case alu_ctrl.shift_src_sign is
+			-- negative sign
+			when "01" =>
+			   	add_src_op_2 := - alu_shifter_out_57;
+			-- change according to sign
+			-- this allows to build the magnitude (ABS, CMPM)
+			when "10" =>
+				if alu_shifter_out(55) = '1' then 
+					add_src_op_2 := - alu_shifter_out_57;
+				else
+					add_src_op_2 :=   alu_shifter_out_57;
+				end if;
+			when others =>
+			   	add_src_op_2 := alu_shifter_out_57;
+		end case;
+
+		-- determine whether carry flag has to be added or subtracted
+		if alu_ctrl.rounding_used = "10" then
+			-- add carry flag
+			carry_const(0) := register_file.sr(C_FLAG);
+		elsif alu_ctrl.rounding_used = "11" then
+			-- subtract carry flag
+			carry_const := (others => register_file.sr(0)); -- carry flag
+		else
+			carry_const := (others => '0');
+		end if;
+
+		-- add the values and calculate the carry bit
+		alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + 
+		                         ('0' & add_src_op_2(55 downto 0)) +
+		                         ('0' & carry_const(55 downto 0));
+
+		-- here pops the new carry out of the adder
+		if invert_carry_flag = '0' then
+			alu_add_carry_out <= alu_add_result_interm(56);
+		else 
+			alu_add_carry_out <= not alu_add_result_interm(56);
+		end if;
+
+		-- calculate the last bit (56), in order to test for overflow later on
+		alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0);
+--		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56);
+		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) 
+		                      xor carry_const(56) xor alu_add_result_interm(56);
+
+	end process alu_adder;
+
+
+	-- Adder after the normal arithmetic adder
+	-- This adder is responsible for
+--	-- 1) carry addition
+--	-- 2) carry subtration
+	-- 3) convergent rounding
+	alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is
+		variable post_adder_constant : signed(56 downto 0);
+		variable testing_constant    : signed(24 downto 0);
+	begin
+		-- by default add nothing
+		post_adder_constant := (others => '0');
+
+		case alu_ctrl.rounding_used is
+			-- rounding dependant on scaling bits
+			when "01" =>
+				case scaling_mode is 
+					-- no scaling
+					when "00" => testing_constant := alu_add_result(23 downto 0) & '0';
+					-- scale down
+					when "01" => testing_constant := alu_add_result(24 downto 0);
+					-- scale up
+					when "10" => testing_constant := alu_add_result(22 downto 0) & "00";
+					when others =>
+					             testing_constant := alu_add_result(23 downto 0) & '0';
+				end case;
+
+				-- Special case!
+				if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then
+					-- add depending on bit left to the rounding position
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := alu_add_result(24);
+						-- scale down
+						when "01" => post_adder_constant(24) := alu_add_result(25);
+						-- scale up
+						when "10" => post_adder_constant(22) := alu_add_result(23);
+						when others =>
+					end case;
+				else -- testing_constant /= X"1000000" 
+					-- add rounding constant depending on scaling mode
+					-- results in round up if MSB of testing constant is set, else nothing happens
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := '1';
+						-- scale down
+						when "01" => post_adder_constant(24) := '1';
+						-- scale up
+						when "10" => post_adder_constant(22) := '1';
+						when others =>
+					end case;
+				end if;
+			-- no rounding
+			when others =>
+				post_adder_constant := (others => '0');
+
+		end case;
+
+		-- Add the result of the first adder to the constant (e.g., carry flag)
+		alu_post_adder_result <= alu_add_result + post_adder_constant;
+
+		-- When rounding is used set 24 LSBs to zero!
+		if alu_ctrl.rounding_used = "01" then
+			alu_post_adder_result(23 downto 0) <= (others => '0');
+		end if;
+	end process;
+
+
+
+	alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is
+	begin
+		if alu_ctrl.logic_function /= "000" then
+			modified_accu_int <= alu_logic_conj;
+		else
+			modified_accu_int <= alu_post_adder_result(55 downto 0);
+		end if;
+	end process;
+
+
+	-- contains the 24*24 bit fractional multiplier
+	alu_multiplier : process(register_file, alu_ctrl) is
+		variable src_op1: signed(23 downto 0);
+		variable src_op2: signed(23 downto 0);
+		variable mul_result_interm : signed(47 downto 0);
+	begin
+		-- select source operands for multiplication
+		case alu_ctrl.mul_op1 is
+			when "00"   => src_op1 := register_file.x0;
+			when "01"   => src_op1 := register_file.x1;
+			when "10"   => src_op1 := register_file.y0;
+			when others => src_op1 := register_file.y1;
+		end case;
+		case alu_ctrl.mul_op2 is
+			when "00"   => src_op2 := register_file.x0;
+			when "01"   => src_op2 := register_file.x1;
+			when "10"   => src_op2 := register_file.y0;
+			when others => src_op2 := register_file.y1;
+		end case;
+
+		-- perform integer multiplication
+		mul_result_interm := src_op1 * src_op2;
+
+		-- sign extension of result
+		alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47));
+		-- convert from two's complement representation to fractional format
+		-- signed integer multiplication delivers twice the sign bit, but only one is needed for the
+		-- fractional multiplication, so remove one and append a zero to the result
+		alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0';
+
+	end process alu_multiplier;
+
+
+	-- contains the data shifter
+	alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is
+		variable src_accu : signed(55 downto 0);
+		variable shift_to_perform : alu_shift_mode;
+	begin
+		-- read source accumulator
+		if alu_ctrl.shift_src = '0' then
+			src_accu := register_file.a;
+		else
+			src_accu := register_file.b;
+		end if;
+
+		alu_shifter_carry_out <= '0';
+		alu_shifter_overflow_out <= '0';
+
+		-- NORM instruction determines the shift value just
+		-- in time, so overwrite the flag from the alu_ctrl
+ 		-- for this instruction by the calculated value
+		if alu_ctrl.norm_instr = '0' then
+			shift_to_perform := alu_ctrl.shift_mode;
+		else
+			if norm_instr_asl = '1' then
+				shift_to_perform := SHIFT_LEFT;
+			elsif norm_instr_asr = '1' then
+				shift_to_perform := SHIFT_RIGHT;
+			else
+				shift_to_perform := NO_SHIFT;
+			end if;
+		end if;
+
+		case shift_to_perform is
+			when NO_SHIFT => 
+				alu_shifter_out <= src_accu;
+			when SHIFT_LEFT => 
+				-- ASL, ADDL, DIV?
+				if alu_ctrl.word_24_update = '0' then
+					-- special handling for div instruction required
+					if alu_ctrl.div_instr = '1' then
+						alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG);
+					else
+						alu_shifter_out <= src_accu(54 downto 0) & '0';
+					end if;
+					alu_shifter_carry_out <= src_accu(55);
+					-- detect overflow that results from left shifting 
+					-- Needed for ASL, ADDL, DIV instructions
+					if src_accu(55) /= src_accu(54) then
+						alu_shifter_overflow_out <= '1';
+					end if;
+				-- LSL/ROL?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(47);
+					if alu_ctrl.rotate = '0' then -- LSL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0';
+					else -- ROL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG);
+					end if;
+				end if;
+			when SHIFT_RIGHT => 
+				-- ASR?
+				if alu_ctrl.word_24_update = '0' then
+					alu_shifter_out <= src_accu(55) & src_accu(55 downto 1);
+					alu_shifter_carry_out <= src_accu(0);
+				-- LSR/ROR?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(24);
+					if alu_ctrl.rotate = '0' then -- LSR
+						alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25);
+					else -- ROR
+						alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25);
+					end if;
+				end if;
+			when ZEROS =>
+				alu_shifter_out <= (others => '0');
+		end case;
+	end process alu_shifter;
+
+
+	-- Special handling for NORM instruction
+ 	-- Determine which case occurs (see User's Manual for more information)
+	norm_instr_logic: process(register_file, addr_r_in) is
+	begin
+		norm_instr_asl <= '0';
+		norm_instr_asr <= '0';
+
+		-- Either left shift
+		if register_file.sr(E_FLAG) = '0' and
+		   register_file.sr(U_FLAG) = '1' and
+		   register_file.sr(Z_FLAG) = '0' then
+			norm_instr_asl <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in - 1;
+		-- Or right shift
+		elsif register_file.sr(E_FLAG) = '1' then
+			norm_instr_asr <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in + 1;
+		-- Or do nothing!
+		else 
+			norm_update_ccr <= '0';
+			addr_r_out <= addr_r_in;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_bit_modify.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_bit_modify.vhd
new file mode 100644
index 0000000..68fecbb
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_bit_modify.vhd
@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_bit_modify is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	src_operand       : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	dst_operand       : out std_logic_vector(23 downto 0);
+	bit_cond_met      : out std_logic;
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_bit_modify is 
+
+	signal operand_bit : std_logic;
+	signal src_operand_32 : std_logic_vector(31 downto 0);
+
+begin
+
+	-- this is just a helper signal to prevent the simulator
+	-- to stop when accessing a bit > 23.
+	src_operand_32 <= "00000000" & src_operand;
+	-- read the bit we want to test (and modify)
+	operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0))));
+
+	-- modify the Carry flag only for the bit modify instructions!
+	modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0';
+	modified_sr <= register_file.sr(15 downto 1) & operand_bit;
+
+	bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is
+		variable new_bit : std_logic;
+	begin
+		-- do nothing by default!
+		dst_operand <= src_operand;
+		bit_cond_met <= '0';
+
+		-- determine which bit to write
+		if instr_array = INSTR_BCLR then
+			new_bit := '0';
+		elsif instr_array = INSTR_BSET then
+			new_bit := '1';
+		else -- BCHG
+			new_bit := not operand_bit;
+		end if;
+
+		if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then
+			dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit;
+		end if;
+
+
+		-- check for the jump instructions whether condition is met or not!
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then
+			if operand_bit = '0' then
+				bit_cond_met <= '1';
+			else
+				bit_cond_met <= '0';
+			end if;
+		end if;
+		if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
+			if operand_bit = '0' then
+				bit_cond_met <= '0';
+			else
+				bit_cond_met <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_branch.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_branch.vhd
new file mode 100644
index 0000000..9b07913
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_branch.vhd
@@ -0,0 +1,117 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_branch is port(
+	activate_exec_bra : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	bit_cond_met      : in  std_logic;
+	cc_flag_set       : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_branch is 
+
+	signal branch_condition_met : std_logic;
+	signal modify_pc_int        : std_logic;
+
+begin
+
+	modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0';
+	modify_pc     <= modify_pc_int;
+
+	calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met)
+	begin
+		branch_condition_met <= '0';
+
+		-- unconditional jumps
+		if instr_array = INSTR_JMP or 
+		   instr_array = INSTR_JSR or
+		   instr_array = INSTR_RTI or
+		   instr_array = INSTR_RTS then
+			-- jump always
+			branch_condition_met <= '1';
+		end if;
+		--  then see whether the branch condition is satisfied
+		if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then
+			branch_condition_met <= cc_flag_set;
+		end if;
+		-- jmp that is executed according to a certain bit condition
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSET or instr_array = INSTR_JSSET then 
+			branch_condition_met <= bit_cond_met;
+		end if;
+	end process calculate_branch_condition;
+
+
+	calculate_branch_target : process(instr_array, instr_word, jump_address)
+	begin
+		modified_pc <= jump_address;
+
+		-- address calculation is the same for the following instructions
+		if instr_array = INSTR_JMP  or 
+		   instr_array = INSTR_JCC  or 
+		   instr_array = INSTR_JSCC or
+		   instr_array = INSTR_JSR then
+			if instr_word(18) = '1' then
+				-- short jump address included in opcode (bits 11 downto 0)
+				modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0));
+			elsif instr_word(18) = '0' then
+				-- effective address defined by opcode and coming from address generator unit
+				modified_pc <= jump_address;
+			end if;
+		end if;
+
+		-- jump address contains the obligatory address of the second
+		-- instruction word
+		if instr_array = INSTR_JCLR or
+		   instr_array = INSTR_JSET or
+		   instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSSET then
+			   modified_pc <= jump_address;
+		end if;
+
+		-- target address is stored on the stack
+		if instr_array = INSTR_RTS or
+		   instr_array = INSTR_RTI then
+			   modified_pc <= unsigned(register_file.current_ssh);
+		end if;
+	end process calculate_branch_target;
+
+	-- Subroutine functions need to store PC and SR on the stack
+	push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC  or instr_array = INSTR_JSR or 
+	                                                      instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0';
+	push_stack.content <= PC_AND_SR;
+	-- pc is set externally!
+	push_stack.pc <= (others => '0');
+
+	-- RTI/RTS instructions need to read from the stack
+	pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0';
+
+	-- some instructions require to set the SR 
+	calculate_status_register : process(instr_array)
+	begin
+		modify_sr <= '0';
+		modified_sr <= (others => '0');
+		if instr_array = INSTR_RTI then
+			modify_sr <= '1';
+			modified_sr <= register_file.current_ssl;
+		end if;
+	end process calculate_status_register;
+
+
+end architecture rtl;
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_cc_flag_calc.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_cc_flag_calc.vhd
new file mode 100644
index 0000000..63a0b2c
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_cc_flag_calc.vhd
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cc_flag_calc is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	cc_flag_set       : out std_logic
+);
+end entity;
+
+
+architecture rtl of exec_stage_cc_flag_calc is
+
+
+begin
+
+	calculate_cc_flag : process(instr_word, instr_array, register_file)
+
+		variable cc_select : std_logic_vector(3 downto 0);
+
+		procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is
+			variable c_flag : std_logic := register_file.ccr(0);
+			variable v_flag : std_logic := register_file.ccr(1);
+			variable z_flag : std_logic := register_file.ccr(2);
+			variable n_flag : std_logic := register_file.ccr(3);
+			variable u_flag : std_logic := register_file.ccr(4);
+			variable e_flag : std_logic := register_file.ccr(5);
+			variable l_flag : std_logic := register_file.ccr(6);
+
+		begin
+			if (cc = "0000" and c_flag = '0')  or -- CC: carry clear 
+			   (cc = "1000" and c_flag = '1')  or -- CS: carry set
+			   (cc = "0101" and e_flag = '0')  or -- EC: extension clear
+			   (cc = "1010" and z_flag = '1')  or -- EQ: equal
+			   (cc = "1101" and e_flag = '1')  or -- ES: extension set
+			   (cc = "0001" and (n_flag = v_flag))  or -- GE: greater than or equal
+			   (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0')  or -- GT: greater than
+			   (cc = "0110" and l_flag = '0')  or -- LC: limit clear 
+			   (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1')  or -- LE: less or equal
+			   (cc = "1110" and l_flag = '1')  or -- LS: limit set
+			   (cc = "1001" and (n_flag /= v_flag))  or -- LT: less than
+			   (cc = "1011" and n_flag = '1')  or -- MI: minus
+			   (cc = "0010" and z_flag = '0')  or -- NE: not equal
+			   (cc = "1100" and (( not u_flag and not  e_flag) or z_flag) = '1') or -- NR: normalized
+			   (cc = "0011" and n_flag = '0')  or -- PL: plus
+			   (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0')   -- NN: not normalized
+			then
+				cc_flag_set <= '1';
+			end if;
+		end procedure;
+	
+	begin
+
+		cc_flag_set <= '0';
+
+		-- Rip the flags we have to test for from the instruction word
+		if (instr_array = INSTR_JCC and instr_word(18) = '0') or
+		   (instr_array = INSTR_JSCC) then
+			   cc_select := instr_word(3 downto 0);
+		else
+			   cc_select := instr_word(15 downto 12);
+		end if;
+	
+		calculate_cc_flag(cc_select);
+
+	end process;
+
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_cr_mod.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_cr_mod.vhd
new file mode 100644
index 0000000..c236db7
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_cr_mod.vhd
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cr_mod is port (
+	activate_exec_cr_mod : in  std_logic;
+	instr_word           : in  std_logic_vector(23 downto 0);
+	instr_array          : in  instructions_type;
+	register_file        : in  register_file_type;
+	modify_sr            : out std_logic;
+	modified_sr          : out std_logic_vector(15 downto 0);
+	modify_omr           : out std_logic;
+	modified_omr         : out std_logic_vector(7 downto 0)
+);
+end exec_stage_cr_mod;
+
+
+architecture rtl of exec_stage_cr_mod is
+
+begin
+
+	process(activate_exec_cr_mod, instr_word, instr_array, register_file) is
+		variable imm8 : std_logic_vector(7 downto 0);
+		variable op8  : std_logic_vector(7 downto 0);
+		variable res8 : std_logic_vector(7 downto 0);
+	begin
+		modify_sr    <= '0';
+		modify_omr   <= '0';
+		modified_sr  <= (others => '0');
+		modified_omr <= (others => '0');
+
+		imm8 := instr_word(15 downto 8);
+		if instr_word(1 downto 0) = "00" then
+			-- read MR
+			op8 := register_file.mr;
+		elsif instr_word(1 downto 0) = "01" then
+			-- read CCR
+			op8 := register_file.ccr;
+		else  -- instr_word(1 downto 0) = "10"
+			-- read OMR
+			op8 := register_file.omr;
+		end if;
+
+		if instr_array = INSTR_ANDI then
+			res8 := imm8 and op8;
+		else -- instr_array = INSTR_ORI
+			res8 := imm8 or op8;
+		end if;
+
+		-- only write the result when activated
+		if activate_exec_cr_mod = '1' then
+			if instr_word(1 downto 0) = "00" then
+				-- update MR
+				modify_sr    <= '1';
+				modified_sr  <= res8 & register_file.ccr;
+			elsif instr_word(1 downto 0) = "01" then
+				-- update CCR
+				modify_sr    <= '1';
+				modified_sr  <= register_file.mr & res8;
+			elsif instr_word(1 downto 0) = "10" then
+				-- update OMR
+				modify_omr   <= '1';
+				modified_omr <= res8;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/exec_stage_loops.vhd b/FPGA_by_Fredi/DSP/src/exec_stage_loops.vhd
new file mode 100644
index 0000000..cc32692
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/exec_stage_loops.vhd
@@ -0,0 +1,200 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_loop is port(
+	clk, rst           : in  std_logic;
+	activate_exec_loop : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	loop_iterations   : in  unsigned(15 downto 0);
+	loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file     : in  register_file_type;
+	fetch_perform_enddo: in std_logic;
+	memory_stall      : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	stall_rep         : out std_logic;
+	stall_do          : out std_logic;
+	decrement_lc      : out std_logic;
+	modify_lc         : out std_logic;
+	modified_lc       : out unsigned(15 downto 0);
+	modify_la         : out std_logic;
+	modified_la       : out unsigned(15 downto 0);
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_loop is
+
+	signal rep_loop_polling : std_logic;
+	signal do_loop_polling  : std_logic;
+	signal enddo_polling    : std_logic;
+	signal lc_temp          : unsigned(15 downto 0);
+	signal rf_lc_eq_1       : std_logic;
+	signal memory_stall_t   : std_logic;
+
+begin
+
+	modified_pc <= loop_start_address;
+
+
+	-- loop counter in register file equal to 1?
+	rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0';
+
+	process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo,
+	        rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is
+	begin
+		stall_rep <= '0';
+		stall_do  <= '0';
+
+		modify_la <= '0';
+		modify_lc <= '0';
+		modify_pc <= '0';
+		modify_sr <= '0';
+		modified_la <= loop_address;
+		modified_lc <= loop_iterations; -- default
+		-- set the loop flag LF (bit 15) of Status register
+		modified_sr(15) <= '1';
+		modified_sr(14 downto 0) <= register_file.sr(14 downto 0);
+
+		push_stack.valid <= '0'; -- push PC and SR on the stack
+		push_stack.pc    <= loop_start_address;
+		push_stack.content <= LA_AND_LC;
+
+		pop_stack.valid <= '0';
+		decrement_lc <= '0';
+		------------------
+		-- DO instruction
+		------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_DO then
+			-- first instruction of the do loop instruction?
+			if do_loop_polling = '0' then
+				stall_do <= '1';
+				modify_lc <= '1'; -- store the new loop counter
+				modify_la <= '1'; -- store the new loop address 
+				push_stack.valid <= '1'; -- push LA and LC on the stack
+				push_stack.content <= LA_AND_LC;
+			else  -- second clock cycle of the do loop instruction ?
+				push_stack.valid <= '1'; -- push PC and SR on the stack
+				push_stack.pc    <= loop_start_address;
+				push_stack.content <= PC_AND_SR;
+				-- set the PC to the first instruction of the loop
+				-- the already fetched instruction are flushed from the pipeline
+				-- this prevents problems, when the loop consists of only one or two instructions
+				modify_pc   <= '1';
+				-- set the loop flag
+				modify_sr   <= '1';
+			end if;
+		end if;
+		-----------------------------------------------
+		-- ENDDO instruction / loop end in fetch stage
+		-----------------------------------------------
+		if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then
+			pop_stack.valid <= '1';
+			if enddo_polling = '0' then
+				-- only restore the LF from the stack
+				modified_sr(15) <= register_file.current_ssl(15);
+				modify_sr <= '1';
+				stall_do <= '1'; -- stall one clock cycle 
+			else
+				-- restore loop counter and loop address in second clock cycle
+				modified_lc <= unsigned(register_file.current_ssl);
+				modify_lc <= '1';
+				modified_la <= unsigned(register_file.current_ssh);
+				modify_la <= '1';
+			end if;
+		end if;
+		-------------------
+		-- REP instruction
+		-------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_REP then
+			-- only do something when there are more than 1 iterations
+			-- the first execution is already on the way
+			if loop_iterations /= 1 then
+				stall_rep <= '1'; -- stall the fetch and decode stages
+				modify_lc <= '1'; -- store the loop counter
+				modified_lc <= loop_iterations - 1;
+			end if;
+		end if;
+
+		-- keep processing the single instruction
+		if rep_loop_polling = '1' then
+			stall_rep <= '1';
+			-- if the REP instruction cause a  stall do not modify the lc!
+			if memory_stall_t = '0' then
+				if rf_lc_eq_1 = '0' then
+					decrement_lc <= '1';
+				-- when the instruction to repeat caused a memory stall
+				-- do not continue!
+				else
+					-- finish the REP instruction by restoring the LC
+					stall_rep <= '0';
+					modify_lc <= '1';
+					modified_lc <= lc_temp;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	-- process that allows to remember that we are processing a REP/DO instruction
+	-- even though the REP instruction is not available in the pipeline anymore
+	-- also store the old loop counter
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				rep_loop_polling <= '0';
+				do_loop_polling  <= '0';
+				enddo_polling    <= '0';
+				lc_temp <= (others => '0');
+				memory_stall_t <= '0';
+			else
+				memory_stall_t <= memory_stall;
+
+				if activate_exec_loop = '1' and instr_array = INSTR_REP then
+					-- only do something when there are more than 1 iterations
+					-- the first execution is already on the way
+					if loop_iterations /= 1 then
+						rep_loop_polling <= '1';
+						lc_temp <= register_file.lc;
+					end if;
+				end if;
+				-- test whether the REP instruction has been executed
+				if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0'  then
+					rep_loop_polling <= '0';
+				end if;
+
+				-- do loop execution takes two clock cycles
+				-- in the first  clock cycle we store loop address and loop counter on the stack
+				-- in the second clock cycle we store programm counter and status register on the stack
+				if activate_exec_loop = '1' and instr_array = INSTR_DO then
+					do_loop_polling <= '1';
+				end if;
+				-- clear the flag immediately again (only two cycles execution time!)
+				if do_loop_polling = '1' then
+					do_loop_polling <= '0';
+				end if;
+
+				-- ENDDO instructions take two clock cycles as well!
+				if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then
+					enddo_polling <= '1';
+				end if;
+				if enddo_polling = '1' then
+					enddo_polling <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_by_Fredi/DSP/src/fetch_stage.vhd b/FPGA_by_Fredi/DSP/src/fetch_stage.vhd
new file mode 100644
index 0000000..6b22f09
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/fetch_stage.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+entity fetch_stage is port(
+
+	pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+	pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_pc     : in  std_logic;
+	modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file : in  register_file_type;
+	decrement_lc  : out std_logic;
+	perform_enddo : out std_logic
+
+);
+end fetch_stage;
+
+
+architecture rtl of fetch_stage is
+
+
+begin
+
+	pc_calculation: process(pc_old, modify_pc, modified_pc, register_file)  is
+	begin
+		decrement_lc  <= '0';
+		perform_enddo <= '0';
+
+		-- by default increment pc by one
+		pc_new <= pc_old + 1;
+		if modify_pc = '1' then
+			pc_new <= modified_pc;
+		end if;
+		-- Loop Flag set?
+		if register_file.sr(15) = '1' then
+			if register_file.la = pc_old then
+				-- Loop not finished?
+				-- => start from the beginning if necessary
+				if register_file.lc /= 1 then
+					-- if the last address was LA and the loop is not finished yet, we have to 
+					-- read now from the beginning of the loop again
+					pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0));
+					-- decrement loop counter
+					decrement_lc <= '1';
+				else
+					-- loop done!
+					-- => tell the loop controller in the exec stage to perform the enddo operation
+					-- (without flushing of the pipeline!)
+					perform_enddo <= '1';
+				end if;
+		   	end if;
+		end if;
+	end process pc_calculation;
+
+end architecture rtl;
+
diff --git a/FPGA_by_Fredi/DSP/src/mem_control.vhd b/FPGA_by_Fredi/DSP/src/mem_control.vhd
new file mode 100644
index 0000000..091fcf0
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/mem_control.vhd
@@ -0,0 +1,1519 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+entity mem_control is
+	generic(
+		mem_type : memory_type := P_MEM
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+end entity mem_control;
+
+
+architecture rtl of mem_control is
+
+	signal int_mem_rd_addr : std_logic_vector(7 downto 0);
+	type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0);
+	signal int_mem : int_mem_type;
+	signal int_pmem : int_mem_type := (
+-- ABS begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200026",
+--X"56F400",
+--X"E00000",
+--X"200026",
+--X"56F400",
+--X"000000",
+--X"200026",
+--X"52F400",
+--X"000080",
+--X"200026",
+-- ABS end
+
+-- ADC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200039",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200039",
+-- ADC end
+
+-- ADD begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200038",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200038",
+-- ADD end
+
+-- ADDL begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20001A",
+--X"56F400",
+--X"0000AA",
+--X"20001A",
+--X"53F400",
+--X"000080",
+--X"20001A",
+-- ADDL end
+
+-- ADDR begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20000A",
+--X"56F400",
+--X"0000AA",
+--X"20000A",
+--X"53F400",
+--X"000080",
+--X"20000A",
+-- ADDR end
+
+-- AND begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"FFF000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+-- AND end
+
+-- EOR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005B",
+--X"46F400",
+--X"FFFFFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005B",
+-- EOR end
+
+-- OR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005A",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"000000",
+--X"0000B9",
+--X"20005A",
+-- OR end
+
+-- NOT begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"7F00FF",
+--X"0000B9",
+--X"20001F",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20001F",
+-- NOT end
+
+-- ASL begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20003A",
+-- ASL end
+
+-- ASR begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20002A",
+-- ASR end
+
+-- CLR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200013",
+--X"56F400",
+--X"E00000",
+--X"0000B9",
+--X"0001F9",
+--X"200013",
+-- CLR end
+
+-- CMP begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005D",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005D",
+-- CMP end
+
+-- CMPM begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005F",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005F",
+-- CMPM end
+
+-- DIV begin
+--X"00FEB9",
+--X"44F400",
+--X"600000",
+--X"56F400",
+--X"200000",
+--X"0618A0",
+--X"018040",
+--X"210E00",
+-- DIV end
+
+-- LSL begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200033",
+-- LSL end
+
+-- LSR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200023",
+-- LSR end
+
+-- MPY begin
+--X"0000B9",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D0",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D4",
+-- MPY end
+
+-- MAC begin
+--X"0000B9",
+--X"200013",
+--X"2A8000",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D6",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D6",
+-- MAC end
+
+-- MACR begin
+--X"0000B9",
+--X"200013",
+--X"2E1000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"56F400",
+--X"100001",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"2E1000",
+--X"50F400",
+--X"800000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+-- MACR end
+
+-- MPYR begin
+--X"0000B9",
+--X"46F400",
+--X"654321",
+--X"200095",
+-- MPYR end
+
+-- NEG begin
+--X"0000B9",
+--X"56F400",
+--X"654321",
+--X"200036",
+--X"200013",
+--X"52F400",
+--X"000080",
+--X"200036",
+--X"56F400",
+--X"800000",
+--X"200036",
+-- NEG end
+
+-- NORM begin
+X"200013",
+X"2C0100",
+X"200003",
+X"062FA0",
+X"01DB15",
+X"200013",
+X"2EFF00",
+X"2A8400",
+X"200003",
+X"062FA0",
+X"01D915",
+X"200013",
+X"062FA0",
+X"01DA15",
+-- NORM end
+
+-- RND begin
+--X"0000B9",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"789ABC",
+--X"200011",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"800000",
+--X"200011",
+--X"54F400",
+--X"123455",
+--X"50F400",
+--X"800000",
+--X"200011",
+-- RND end
+
+-- ROR begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200027",
+-- ROR end
+
+-- ROL begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200037",
+-- ROL end
+
+
+-- SUB begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003C",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003C",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20007C",
+-- SUB end
+
+-- SUBL begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20001E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20001E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20001E",
+-- SUBL end
+
+-- SUBR begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20000E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20000E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20000E",
+-- SUBR end
+
+-- SBC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003D",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003D",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20003D",
+-- SBC end
+
+-- TCC begin
+--X"311400",
+--X"44F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"0000B9",
+--X"038143",
+--X"03014A",
+--X"0004F9",
+--X"03A143",
+--X"03214A",
+-- TCC end
+
+-- TFR begin
+--X"56F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"21EE09",
+--X"44F400",
+--X"555555",
+--X"47F400",
+--X"AAAAAA",
+--X"21C441",
+--X"21E679",
+-- TFR end
+
+-- TST begin
+--X"20001B",
+--X"20000B",
+--X"0000B9",
+--X"0001F9",
+--X"53F400",
+--X"000080",
+--X"20000B",
+--X"53F400",
+--X"00007F",
+--X"20000B",
+-- TST end
+
+
+--X"2AFF00",
+--X"54F400",
+--X"FFFFFF",
+--X"50F400",
+--X"FFFFF2",
+--X"200026",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+--X"44F400",
+--X"100010",
+--X"45F400",
+--X"100011",
+--X"0B5880",
+--X"000017",
+--X"46F400",
+--X"100026",
+--X"47F400",
+--X"100027",
+--X"425800",
+--X"435800",
+--X"420A00",
+--X"431F00",
+--X"437000",
+--X"0000A0",
+--X"427000",
+--X"00004F",
+--  X"42F800",
+--  X"43F800",
+--  X"428A00",
+--  X"439F00",
+--	"001100000100100000000000",  -- 0 move #72,r0
+--	"001110000000100000000000",  -- 1 move #8,n0
+--	"000001010000000010100000",  -- 2 move #0,m0
+--	"000001010001000010100001",  -- 3 move #16,m1
+--	"000001101110000100100000",  -- 4 rep m1
+--	"010001001100100000000000",  -- 5 move x:(r0)+n0,x0
+--	"000000000000000000000000",  -- 6
+--	"000000000000000000000000",  -- 7
+--	"000000000000000000000000",  -- 8
+--	"000000000000000000000000",  -- 9 
+--	"000000000000000000000000",  -- 10
+--	"000000000000000000000000",  -- 11
+--	"000000000000000000000000",  -- 12
+--	"000000000000000000000000",  -- 13
+--	"000000000000000000000000",  -- 14
+--	"000000000000000000000000",  -- 15
+--	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+--	"000000000000000000000000",  -- 18
+--	"000000000000000000000000",  -- 19
+--	"000010101101101010000000",  -- 20 -- JMP (r2)+
+--	"000000000000000000000000",  -- 20
+--	"000000000000000000000000",  -- 21
+--	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_xmem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000001100",  -- 0 -- REP
+	"000000000000000000000101",  -- 1 -- ORI #$0E, MR
+	"000000000000111011111010",  -- 2 -- ORI #$0E, OMR
+	"000000000000100010111010",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000000",  -- 4
+	"000000000000000000000000",  -- 5
+	"000000000000000000000000",  -- 6
+	"000000000000000000000000",  -- 7
+	"000000000000000000000000",  -- 8
+	"000000000000000000000000",  -- 9
+	"000000000000000000000000",  -- 10
+	"000000000000000000000000",  -- 11
+	"000000000000000000000000",  -- 12
+	"000000000000000000000000",  -- 13
+	"000000000000000000000000",  -- 14
+	"000000000000000000000000",  -- 15
+	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_ymem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000000001",  -- 0 -- REP
+	"000000000000000000000010",  -- 1 -- ORI #$0E, MR
+	"000000000000000000000011",  -- 2 -- ORI #$0E, OMR
+	"000000000000000000000100",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000101",  -- 4
+	"000000000000000000000110",  -- 5
+	"000000000000000000000111",  -- 6
+	"000000000000000000001000",  -- 7
+	"000000000000000000001001",  -- 8
+	"000000000000000000001010",  -- 9
+	"000000000000000000001011",  -- 10
+	"000000000000000000001100",  -- 11
+	"000000000000000000001101",  -- 12
+	"000000000000000000001110",  -- 13
+	"000000000000000000001111",  -- 14
+	"000000000000000000010000",  -- 15
+	"000000000000000000010001",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+
+begin
+
+--	int_mem <= int_pmem when mem_type = P_MEM else
+--	           int_xmem when mem_type = X_MEM else
+--	           int_ymem when mem_type = Y_MEM;
+
+	wr_accomplished <= wr_en;
+
+	PMEM_GEN: if mem_type = P_MEM generate
+		data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_pmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	XMEM_GEN: if mem_type = X_MEM generate
+		data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_xmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	YMEM_GEN: if mem_type = Y_MEM generate
+		data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_ymem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+--	process(clk, rst) is
+--	begin
+--		if rising_edge(clk) then
+--			if rst = '1' then
+--				data_out_valid <= '0';
+--				int_mem_rd_addr <= (others => '0');
+--			else
+--				int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+--				data_out_valid <= rd_en;
+--				if wr_en = '1' then
+--					if mem_type = P_MEM then
+--						int_pmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = X_MEM then
+--						int_xmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = Y_MEM then
+--						int_ymem(to_integer(wr_addr)) <= data_in;
+--					end if;
+--				end if;
+--			end if;
+--		end if;
+--	end process;
+
+end architecture rtl;
+
diff --git a/FPGA_by_Fredi/DSP/src/memory_management.vhd b/FPGA_by_Fredi/DSP/src/memory_management.vhd
new file mode 100644
index 0000000..6a25ac8
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/memory_management.vhd
@@ -0,0 +1,206 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity memory_management is port (
+	clk, rst : in std_logic;
+	stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+	memory_stall   : out std_logic;
+	data_rom_enable: in  std_logic;
+	pmem_ctrl_in   : in  mem_ctrl_type_in;
+	pmem_ctrl_out  : out mem_ctrl_type_out;
+	xmem_ctrl_in   : in  mem_ctrl_type_in;
+	xmem_ctrl_out  : out mem_ctrl_type_out;
+	ymem_ctrl_in   : in  mem_ctrl_type_in;
+	ymem_ctrl_out  : out mem_ctrl_type_out
+);
+end memory_management;
+
+
+architecture rtl of memory_management is
+
+
+	component mem_control is 
+	generic(
+		mem_type : memory_type
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+	end component mem_control;
+
+	signal pmem_data_out        : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid  : std_logic;
+
+	signal pmem_rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+	signal pmem_rd_en     : std_logic;
+
+	signal xmem_rd_en          : std_logic;
+	signal xmem_data_out       : std_logic_vector(23 downto 0);
+	signal xmem_data_out_valid : std_logic;
+	signal xmem_rd_polling : std_logic;
+
+	signal ymem_rd_en          : std_logic;
+	signal ymem_data_out       : std_logic_vector(23 downto 0);
+	signal ymem_data_out_valid : std_logic;
+	signal ymem_rd_polling : std_logic;
+
+	signal pmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal pmem_stall_buffer_valid : std_logic;
+	signal xmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal ymem_stall_buffer : std_logic_vector(23 downto 0);
+
+	signal stall_flags_d    : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+begin
+
+	-- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall
+	-- when the pipeline wakes up, this temporal result is inserted into the pipeline
+	stall_buffer: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				pmem_stall_buffer <= (others => '0');
+				pmem_stall_buffer_valid <= '0';
+				xmem_stall_buffer <= (others => '0');
+				ymem_stall_buffer <= (others => '0');
+				stall_flags_d <= (others => '0');
+			else
+				stall_flags_d <= stall_flags;
+				if stall_flags(ST_FETCH2) = '1' and stall_flags_d(ST_FETCH2) = '0' then
+					if pmem_data_out_valid = '1' then
+						pmem_stall_buffer <= pmem_data_out;
+						pmem_stall_buffer_valid <= '1';
+					end if;
+				end if;
+				if stall_flags(ST_FETCH2) = '0' and stall_flags_d(ST_FETCH2) = '1' then
+						pmem_stall_buffer_valid <= '0';
+				end if;
+
+
+			end if;
+		end if;
+	end process stall_buffer;
+	
+	memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or
+	                         ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else
+	                '0';
+
+	-------------------------------
+	-- PMEM CONTROLLER
+	-------------------------------
+	inst_pmem_ctrl : mem_control 
+	generic map(
+		mem_type => P_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => pmem_ctrl_in.rd_addr,
+		rd_en   => pmem_ctrl_in.rd_en,
+		data_out => pmem_data_out,
+		data_out_valid => pmem_data_out_valid,
+		wr_addr => pmem_ctrl_in.wr_addr,
+		wr_en   => pmem_ctrl_in.wr_en,
+		data_in => pmem_ctrl_in.data_in
+	);
+
+	-- In case we wake up from a stall use the buffered value
+	pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FETCH2) = '0' and 
+	                                                 stall_flags_d(ST_FETCH2) = '1' and 
+	                                                 pmem_stall_buffer_valid = '1'  else
+	                          pmem_data_out;
+
+	pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FETCH2) = '0' and 
+	                                                             stall_flags_d(ST_FETCH2) = '1' else
+	                                '0'                     when stall_flags(ST_FETCH2) = '1' else
+	                                pmem_data_out_valid;
+
+	-------------------------------
+	-- XMEM CONTROLLER
+	-------------------------------
+	inst_xmem_ctrl : mem_control 
+	generic map(
+		mem_type => X_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => xmem_ctrl_in.rd_addr,
+		rd_en   => xmem_rd_en,
+		data_out => xmem_data_out,
+		data_out_valid => xmem_data_out_valid,
+		wr_addr => xmem_ctrl_in.wr_addr,
+		wr_en   => xmem_ctrl_in.wr_en,
+		data_in => xmem_ctrl_in.data_in
+	);
+
+	xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0';
+
+	xmem_ctrl_out.data_out <= xmem_data_out;
+	xmem_ctrl_out.data_out_valid <= xmem_data_out_valid;
+
+	-------------------------------
+	-- YMEM CONTROLLER
+	-------------------------------
+	inst_ymem_ctrl : mem_control 
+	generic map(
+		mem_type => Y_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => ymem_ctrl_in.rd_addr,
+		rd_en   => ymem_rd_en,
+		data_out => ymem_data_out,
+		data_out_valid => ymem_data_out_valid,
+		wr_addr => ymem_ctrl_in.wr_addr,
+		wr_en   => ymem_ctrl_in.wr_en,
+		data_in => ymem_ctrl_in.data_in
+	);
+
+	ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0';
+
+	ymem_ctrl_out.data_out <= ymem_data_out;
+	ymem_ctrl_out.data_out_valid <= ymem_data_out_valid;
+
+	mem_stall_control: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				xmem_rd_polling <= '0';
+				ymem_rd_polling <= '0';
+			else
+				if xmem_rd_en = '1' then
+					xmem_rd_polling <= '1';
+				end if;
+
+				if xmem_data_out_valid = '1' then
+					xmem_rd_polling <= '0';
+				end if;
+
+				if ymem_rd_en = '1' then
+					ymem_rd_polling <= '1';
+				end if;
+
+				if ymem_data_out_valid = '1' then
+					ymem_rd_polling <= '0';
+				end if;
+
+			end if;
+		end if;
+	end process;
+end architecture;
+
diff --git a/FPGA_by_Fredi/DSP/src/parameter_pkg.vhd b/FPGA_by_Fredi/DSP/src/parameter_pkg.vhd
new file mode 100644
index 0000000..9e3c301
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/parameter_pkg.vhd
@@ -0,0 +1,10 @@
+
+package parameter_pkg is
+
+	constant BW_ADDRESS : natural := 16;
+
+	constant PIPELINE_DEPTH : natural := 5;
+
+	constant NUM_ACT_SIGNALS : natural := 26;
+
+end package;
diff --git a/FPGA_by_Fredi/DSP/src/pipeline.vhd b/FPGA_by_Fredi/DSP/src/pipeline.vhd
new file mode 100644
index 0000000..5b5a98e
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/pipeline.vhd
@@ -0,0 +1,968 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity pipeline is port (
+	clk, rst : in std_logic;
+	register_file_out : out register_file_type
+
+);
+end pipeline;
+
+-- TODOs:
+-- External memory accesses
+-- ROM tables
+-- Reading from SSH flag has to modify stack pointer
+-- Memory access (x,y,p) and talling accordingly
+-- Address Generator: ring buffers are not yet supported
+
+-- List of BUGS:
+-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!!
+-- - SBC instruction has errorneous carry flag calculation
+
+-- List of probable issues:
+-- - Reading from XMEM/YMEM with stalls probably results in corrupted data
+-- - ENDDO instruction probably has to flush the pipeline afterwards
+-- - Writing to memory occurs twice, when stalls occur
+
+-- Things to optimize: 
+--  - RTS/RTI could be executed in the ADGEN Stage already
+--  - DO loops always flush the pipeline. This is necessary in case we have a very short loop.
+--     The single instruction of the loop then has passed the fetch stage already without the branch
+
+
+architecture rtl of pipeline is
+
+	signal pipeline_regs : pipeline_type;
+	signal stall_flags   : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+	component fetch_stage is port(
+		pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+		pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_pc     : in  std_logic;
+		modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file : in  register_file_type;
+		decrement_lc  : out std_logic;
+		perform_enddo : out std_logic
+	);
+	end component fetch_stage;
+
+	signal pc_old, pc_new    : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_modify_pc   : std_logic;
+	signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_perform_enddo: std_logic;
+	signal fetch_decrement_lc: std_logic;
+
+
+	component decode_stage is port(
+		activate_dec    : in  std_logic;
+		instr_word      : in  std_logic_vector(23 downto 0);
+		dble_word_instr : out std_logic;
+		instr_array     : out instructions_type;
+		act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		reg_wr_addr     : out std_logic_vector(5 downto 0);
+		reg_rd_addr     : out std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		l_bus_addr      : out std_logic_vector(2 downto 0); 
+		adgen_mode_a    : out adgen_mode_type;
+		adgen_mode_b    : out adgen_mode_type;
+		alu_ctrl        : out alu_ctrl_type
+	);
+	end component decode_stage;
+
+	signal dec_activate : std_logic;
+	signal dec_instr_word      : std_logic_vector(23 downto 0);
+	signal dec_dble_word_instr : std_logic;
+	signal dec_instr_array     : instructions_type;
+	signal dec_act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	signal dec_reg_wr_addr     : std_logic_vector(5 downto 0);
+	signal dec_reg_rd_addr     : std_logic_vector(5 downto 0);
+	signal dec_x_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_x_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_l_bus_addr      : std_logic_vector(2 downto 0);
+	signal dec_adgen_mode_a    : adgen_mode_type;
+	signal dec_adgen_mode_b    : adgen_mode_type;
+	signal dec_alu_ctrl        : alu_ctrl_type;
+
+	component adgen_stage is port(
+		activate_adgen    : in  std_logic;
+		activate_x_mem    : in  std_logic;
+		activate_y_mem    : in  std_logic;
+		activate_l_mem    : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		optional_ea_word  : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		adgen_mode_a      : in  adgen_mode_type;
+		adgen_mode_b      : in  adgen_mode_type;
+		address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+		address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+		wr_R_port_A_valid : out std_logic;
+		wr_R_port_A       : out addr_wr_port_type;
+		wr_R_port_B_valid : out std_logic;
+		wr_R_port_B       : out addr_wr_port_type
+	);
+	end component adgen_stage;
+
+	signal adgen_activate          : std_logic;
+	signal adgen_activate_x_mem    : std_logic;
+	signal adgen_activate_y_mem    : std_logic;
+	signal adgen_activate_l_mem    : std_logic;
+	signal adgen_instr_word        : std_logic_vector(23 downto 0);
+	signal adgen_instr_array       : instructions_type;
+	signal adgen_optional_ea_word  : std_logic_vector(23 downto 0);
+	signal adgen_register_file     : register_file_type;
+	signal adgen_mode_a            : adgen_mode_type;
+	signal adgen_mode_b            : adgen_mode_type;
+	signal adgen_address_out_x     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_address_out_y     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_wr_R_port_A_valid : std_logic;
+	signal adgen_wr_R_port_A       : addr_wr_port_type;
+	signal adgen_wr_R_port_B_valid : std_logic;
+	signal adgen_wr_R_port_B       : addr_wr_port_type;
+
+	component exec_stage_bit_modify is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		src_operand       : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		dst_operand       : out std_logic_vector(23 downto 0);
+		bit_cond_met      : out std_logic;
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_bit_modify;
+
+	signal exec_bit_modify_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_instr_array   : instructions_type;
+	signal exec_bit_modify_src_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_dst_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_bit_cond_met  : std_logic;
+	signal exec_bit_modify_modify_sr     : std_logic;
+	signal exec_bit_modify_modified_sr   : std_logic_vector(15 downto 0);
+
+	component exec_stage_branch is port(
+		activate_exec_bra : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		bit_cond_met      : in  std_logic;
+		cc_flag_set       : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_branch;
+
+	signal exec_bra_activate     : std_logic;
+	signal exec_bra_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_bra_instr_array  : instructions_type;
+	signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_bit_cond_met : std_logic;
+	signal exec_bra_push_stack   : push_stack_type;
+	signal exec_bra_pop_stack    : pop_stack_type;
+	signal exec_bra_modify_pc    : std_logic;
+	signal exec_bra_modified_pc  : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_modify_sr    : std_logic;
+	signal exec_bra_modified_sr  : std_logic_vector(15 downto 0);
+
+	component exec_stage_cr_mod is port(
+		activate_exec_cr_mod : in  std_logic;
+		instr_word           : in  std_logic_vector(23 downto 0);
+		instr_array          : in  instructions_type;
+		register_file        : in  register_file_type;
+		modify_sr            : out std_logic;
+		modified_sr          : out std_logic_vector(15 downto 0);
+		modify_omr           : out std_logic;
+		modified_omr         : out std_logic_vector(7 downto 0)
+	);
+	end component exec_stage_cr_mod;
+
+	signal exec_cr_mod_activate     : std_logic;
+	signal exec_cr_mod_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cr_mod_instr_array  : instructions_type;
+	signal exec_cr_mod_modify_sr    : std_logic;
+	signal exec_cr_mod_modified_sr  : std_logic_vector(15 downto 0);
+	signal exec_cr_mod_modify_omr   : std_logic;
+	signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0);
+
+	component exec_stage_loop is port(
+		clk, rst           : in  std_logic;
+		activate_exec_loop : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		loop_iterations   : in  unsigned(15 downto 0);
+		loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file     : in  register_file_type;
+		fetch_perform_enddo: in std_logic;
+		memory_stall      : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		stall_rep         : out std_logic;
+		stall_do          : out std_logic;
+		decrement_lc      : out std_logic;
+		modify_lc         : out std_logic;
+		modified_lc       : out unsigned(15 downto 0);
+		modify_la         : out std_logic;
+		modified_la       : out unsigned(15 downto 0);
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_loop;
+
+	signal exec_loop_activate : std_logic;
+	signal exec_loop_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_loop_instr_array   : instructions_type;
+	signal exec_loop_iterations    : unsigned(15 downto 0);
+	signal exec_loop_address       : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_register_file : register_file_type;
+	signal exec_loop_push_stack    : push_stack_type;
+	signal exec_loop_pop_stack     : pop_stack_type;
+	signal exec_loop_stall_rep     : std_logic;
+	signal exec_loop_stall_do      : std_logic;
+	signal exec_loop_decrement_lc  : std_logic;
+	signal exec_loop_modify_lc     : std_logic;
+	signal exec_loop_modified_lc   : unsigned(15 downto 0);
+	signal exec_loop_modify_la     : std_logic;
+	signal exec_loop_modified_la   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_pc     : std_logic;
+	signal exec_loop_modified_pc   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_sr     : std_logic;
+	signal exec_loop_modified_sr   : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	component exec_stage_alu is port(
+		alu_activate      : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		alu_ctrl          : in  alu_ctrl_type;
+		register_file     : in  register_file_type;
+		addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+		addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_accu       : out std_logic;
+		dst_accu          : out std_logic;
+		modified_accu     : out signed(55 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_alu;
+
+	signal exec_alu_activate      : std_logic;
+	signal exec_alu_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_alu_ctrl          : alu_ctrl_type;
+	signal exec_alu_addr_r_in     : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_addr_r_out    : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_modify_accu   : std_logic;
+	signal exec_alu_dst_accu      : std_logic;
+	signal exec_alu_modified_accu : signed(55 downto 0);
+	signal exec_alu_modify_sr     : std_logic;
+	signal exec_alu_modified_sr   : std_logic_vector(15 downto 0);
+
+	signal exec_imm_8bit    : std_logic_vector(23 downto 0);
+	signal exec_imm_12bit   : std_logic_vector(23 downto 0);
+	signal exec_src_operand : std_logic_vector(23 downto 0);
+	signal exec_dst_operand : std_logic_vector(23 downto 0);
+
+	component exec_stage_cc_flag_calc is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		cc_flag_set       : out std_logic
+	);
+	end component exec_stage_cc_flag_calc;
+
+	signal exec_cc_flag_calc_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cc_flag_calc_instr_array  : instructions_type;
+	signal exec_cc_flag_set : std_logic;
+
+	component reg_file is port(
+		clk, rst          : in  std_logic;
+		register_file     : out register_file_type;
+		wr_R_port_A_valid : in  std_logic;
+		wr_R_port_A       : in  addr_wr_port_type;
+		wr_R_port_B_valid : in  std_logic;
+		wr_R_port_B       : in  addr_wr_port_type;
+		alu_wr_valid      : in  std_logic;
+		alu_wr_addr       : in  std_logic;
+		alu_wr_data       : in  signed(55 downto 0);
+		reg_wr_addr       : in  std_logic_vector(5 downto 0);
+		reg_wr_addr_valid : in  std_logic;
+		reg_wr_data       : in  std_Logic_vector(23 downto 0);
+		reg_rd_addr       : in  std_logic_vector(5 downto 0);
+		reg_rd_data       : out std_Logic_vector(23 downto 0);
+		X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_data_out    : out std_logic_vector(23 downto 0);
+		X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_wr_valid    : in  std_logic;
+		X_bus_data_in     : in  std_logic_vector(23 downto 0);
+		Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_data_out    : out std_logic_vector(23 downto 0);
+		Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_wr_valid    : in  std_logic;
+		Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+		L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_rd_valid    : in  std_logic;
+		L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_wr_valid    : in  std_logic;
+		push_stack        : in  push_stack_type;
+		pop_stack         : in  pop_stack_type;
+		set_sr            : in  std_logic;
+		new_sr            : in  std_logic_vector(15 downto 0);
+		set_omr           : in  std_logic;
+		new_omr           : in  std_logic_vector(7 downto 0);
+		set_lc            : in  std_logic;
+		new_lc            : in  unsigned(15 downto 0);
+		dec_lc            : in  std_logic;
+		set_la            : in  std_logic;
+		new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+	);
+	end component reg_file;
+
+	signal register_file        : register_file_type;
+	signal rf_wr_R_port_A_valid : std_logic;
+	signal rf_wr_R_port_B_valid : std_logic;
+	signal rf_reg_wr_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_wr_addr_valid : std_logic;
+	signal rf_reg_wr_data       : std_logic_vector(23 downto 0);
+	signal rf_reg_rd_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_rd_data       : std_logic_vector(23 downto 0);
+	signal rf_X_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_X_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_wr_valid    : std_logic;
+	signal rf_X_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_wr_valid    : std_logic;
+	signal rf_Y_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_L_bus_rd_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_rd_valid    : std_logic;
+	signal rf_L_bus_wr_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_wr_valid    : std_logic;
+	signal push_stack           : push_stack_type;
+	signal pop_stack            : pop_stack_type;
+	signal rf_set_sr            : std_logic;
+	signal rf_new_sr            : std_logic_vector(15 downto 0);
+	signal rf_set_omr           : std_logic;
+	signal rf_new_omr           : std_logic_vector(7 downto 0);
+	signal rf_dec_lc            : std_logic;
+	signal rf_set_lc            : std_logic;
+	signal rf_new_lc            : unsigned(15 downto 0);
+	signal rf_set_la            : std_logic;
+	signal rf_new_la            : unsigned(BW_ADDRESS-1 downto 0);
+	signal rf_alu_wr_valid      : std_logic;
+
+	component memory_management is port (
+		clk, rst : in std_logic;
+		stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+		memory_stall   : out std_logic;
+		data_rom_enable: in  std_logic;
+		pmem_ctrl_in   : in  mem_ctrl_type_in;
+		pmem_ctrl_out  : out mem_ctrl_type_out;
+		xmem_ctrl_in   : in  mem_ctrl_type_in;
+		xmem_ctrl_out  : out mem_ctrl_type_out;
+		ymem_ctrl_in   : in  mem_ctrl_type_in;
+		ymem_ctrl_out  : out mem_ctrl_type_out
+	);
+	end component memory_management;
+
+	signal memory_stall   : std_logic;
+	signal pmem_ctrl_in   : mem_ctrl_type_in;
+	signal pmem_ctrl_out  : mem_ctrl_type_out;
+	signal xmem_ctrl_in   : mem_ctrl_type_in;
+	signal xmem_ctrl_out  : mem_ctrl_type_out;
+	signal ymem_ctrl_in   : mem_ctrl_type_in;
+	signal ymem_ctrl_out  : mem_ctrl_type_out;
+
+	signal pmem_data_out       : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid : std_logic;
+	signal xmem_data_out       : std_logic_vector(23 downto 0);
+	signal xmem_data_out_valid : std_logic;
+	signal ymem_data_out       : std_logic_vector(23 downto 0);
+	signal ymem_data_out_valid : std_logic;
+
+begin
+	register_file_out <= register_file;
+
+	-- merge all stall sources
+	stall_flags(ST_FETCH)  <= '1' when exec_loop_stall_rep   = '1' or 
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do    = '1' else '0';
+	stall_flags(ST_FETCH2) <= '1' when exec_loop_stall_rep = '1' or 
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_DECODE) <= '1' when exec_loop_stall_rep = '1' or
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_ADGEN)   <= exec_loop_stall_do;
+--	stall_flags(ST_ADGEN)  <= '1' when memory_stall = '1' or
+--	                                   exec_loop_stall_do = '1' else '0';
+--	stall_flags(ST_EXEC)   <= '0';
+	stall_flags(ST_EXEC)   <= exec_loop_stall_do;
+--	stall_flags(ST_EXEC)   <= '1' when memory_stall = '1' or
+--	                                   exec_loop_stall_do = '1' else '0';
+
+	shift_pipeline: process(clk, rst) is
+		procedure flush_pipeline_stage(stage: natural) is
+		begin
+			pipeline_regs(stage).pc <= (others => '1');
+			pipeline_regs(stage).instr_word <= (others => '0');
+			pipeline_regs(stage).act_array   <= (others => '0');
+			pipeline_regs(stage).instr_array <= INSTR_NOP;
+			pipeline_regs(stage).dble_word_instr <= '0';
+			pipeline_regs(stage).dec_activate <= '0';
+			pipeline_regs(stage).adgen_mode_a <= NOP;
+			pipeline_regs(stage).adgen_mode_b <= NOP;
+			pipeline_regs(stage).reg_wr_addr  <= (others => '0');
+			pipeline_regs(stage).reg_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).l_bus_addr     <= (others => '0');
+			pipeline_regs(stage).adgen_address_x <= (others => '0');
+			pipeline_regs(stage).adgen_address_y <= (others => '0');
+			pipeline_regs(stage).RAM_out_x <= (others => '0');
+			pipeline_regs(stage).RAM_out_y <= (others => '0');
+			pipeline_regs(stage).alu_ctrl.store_result <= '0';
+		end procedure flush_pipeline_stage;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				for i in 0 to PIPELINE_DEPTH-1 loop
+					flush_pipeline_stage(i);
+				end loop;
+			else
+				-- shift the pipeline registers when no stall applies
+				for i in 1 to PIPELINE_DEPTH-1 loop
+					if stall_flags(i) = '0' then
+						-- do not copy the pipeline registers from a stalled pipeline stage
+						-- for REP we do not flush
+--						if stall_flags(i-1) = '1' then
+						if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or
+						   (i = ST_ADGEN and memory_stall = '1' and exec_loop_stall_rep = '1') then
+							flush_pipeline_stage(i);
+						else
+							pipeline_regs(i) <= pipeline_regs(i-1);
+						end if;
+					end if;
+				end loop;
+				-- FETCH Pipeline Registers 
+				if stall_flags(ST_FETCH) = '0' then
+					pipeline_regs(ST_FETCH).pc <= pc_new;
+					pipeline_regs(ST_FETCH).dec_activate <= '1';
+				end if;
+
+				-- FETCH2 Pipeline Registers
+				if stall_flags(ST_FETCH2) = '0' then
+					-- Normal pipeline operation?
+					-- Buffering of RAM output when stalling is performed in the memory management
+					if pmem_data_out_valid = '1' then
+						pipeline_regs(ST_FETCH2).instr_word <= pmem_data_out;
+					end if;
+				end if;
+
+				-- DECODE Pipeline registers
+				if stall_flags(ST_DECODE) = '0' then
+					pipeline_regs(ST_DECODE).act_array   <= dec_act_array;
+					pipeline_regs(ST_DECODE).instr_array <= dec_instr_array;
+					pipeline_regs(ST_DECODE).dble_word_instr <= dec_dble_word_instr;
+					pipeline_regs(ST_DECODE).reg_wr_addr     <= dec_reg_wr_addr;
+					pipeline_regs(ST_DECODE).reg_rd_addr     <= dec_reg_rd_addr;
+					pipeline_regs(ST_DECODE).x_bus_wr_addr   <= dec_x_bus_wr_addr;
+					pipeline_regs(ST_DECODE).x_bus_rd_addr   <= dec_x_bus_rd_addr;
+					pipeline_regs(ST_DECODE).y_bus_wr_addr   <= dec_y_bus_wr_addr;
+					pipeline_regs(ST_DECODE).y_bus_rd_addr   <= dec_y_bus_rd_addr;
+					pipeline_regs(ST_DECODE).l_bus_addr      <= dec_l_bus_addr;
+					pipeline_regs(ST_DECODE).adgen_mode_a    <= dec_adgen_mode_a;
+					pipeline_regs(ST_DECODE).adgen_mode_b    <= dec_adgen_mode_b;
+					pipeline_regs(ST_DECODE).alu_ctrl        <= dec_alu_ctrl;
+				end if;
+
+				-- ADGEN Pipeline registers
+				if stall_flags(ST_ADGEN) = '0' then
+					pipeline_regs(ST_ADGEN).adgen_address_x <= adgen_address_out_x;
+					pipeline_regs(ST_ADGEN).adgen_address_y <= adgen_address_out_y;
+				end if;
+				if xmem_data_out_valid = '1' then
+					pipeline_regs(ST_ADGEN).RAM_out_x <= xmem_data_out;
+				end if;
+				if ymem_data_out_valid = '1' then
+					pipeline_regs(ST_ADGEN).RAM_out_y <= ymem_data_out;
+				end if;
+
+				-- EXEC Pipeline stuff
+				if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then
+					-- clear the following pipeline stages,
+					-- since we modified the pc. 
+					-- Do not flush ST_FETCH - it will hold the correct pc.
+					flush_pipeline_stage(ST_FETCH2);
+					flush_pipeline_stage(ST_DECODE);
+					flush_pipeline_stage(ST_ADGEN);
+				end if;
+			end if;
+		end if;
+	end process shift_pipeline;
+
+	-------------------------------
+	-- FETCH STAGE INSTANTIATION
+	-------------------------------
+	inst_fetch_stage: fetch_stage port map(
+		pc_old => pc_old,
+		pc_new => pc_new,
+		modify_pc => fetch_modify_pc,
+		modified_pc => fetch_modified_pc,
+		register_file => register_file,
+		decrement_lc  => fetch_decrement_lc,
+		perform_enddo => fetch_perform_enddo
+	);
+
+	pc_old <= pipeline_regs(ST_FETCH).pc;
+
+	fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0';
+	fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else
+	                     exec_loop_modified_pc;
+
+	-------------------------------
+	-- DECODE STAGE INSTANTIATION
+	-------------------------------
+	inst_decode_stage : decode_stage port map(
+		activate_dec    => dec_activate,
+		instr_word      => dec_instr_word,
+		dble_word_instr => dec_dble_word_instr,
+		instr_array     => dec_instr_array,
+		act_array       => dec_act_array,
+		reg_wr_addr     => dec_reg_wr_addr,
+		reg_rd_addr     => dec_reg_rd_addr,
+		x_bus_wr_addr   => dec_x_bus_wr_addr,
+		x_bus_rd_addr   => dec_x_bus_rd_addr,
+		y_bus_wr_addr   => dec_y_bus_wr_addr,
+		y_bus_rd_addr   => dec_y_bus_rd_addr,
+		l_bus_addr      => dec_l_bus_addr,
+		adgen_mode_a    => dec_adgen_mode_a,
+		adgen_mode_b    => dec_adgen_mode_b,
+		alu_ctrl        => dec_alu_ctrl
+	);
+
+	dec_instr_word <= pipeline_regs(ST_DECODE-1).instr_word;
+	-- do not decode, when we have no valid instruction. This can happen when
+	--  1) the pipeline just started its operation
+	--  2) the pipeline was flushed due to a jump
+	--  3) we are processing a instruction that consists of two words
+	dec_activate   <= '1' when pipeline_regs(ST_DECODE-1).dec_activate = '1' and pipeline_regs(ST_DECODE).dble_word_instr = '0' else '0';
+
+	-------------------------------
+	-- AGU STAGE INSTANTIATION
+	-------------------------------
+	inst_adgen_stage: adgen_stage port map(
+		activate_adgen    => adgen_activate,
+		activate_x_mem    => adgen_activate_x_mem,
+		activate_y_mem    => adgen_activate_y_mem,
+		activate_l_mem    => adgen_activate_l_mem,
+		instr_word        => adgen_instr_word,
+		instr_array       => adgen_instr_array,
+		optional_ea_word  => adgen_optional_ea_word,
+		register_file     => register_file,
+		adgen_mode_a      => adgen_mode_a,
+		adgen_mode_b      => adgen_mode_b,
+		address_out_x     => adgen_address_out_x,
+		address_out_y     => adgen_address_out_y,
+		wr_R_port_A_valid => adgen_wr_R_port_A_valid,
+		wr_R_port_A       => adgen_wr_R_port_A,
+		wr_R_port_B_valid => adgen_wr_R_port_B_valid,
+		wr_R_port_B       => adgen_wr_R_port_B
+	);
+
+	adgen_activate          <= pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN);
+	adgen_activate_x_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_WR) = '1' else '0';
+	adgen_activate_y_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	adgen_activate_l_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_WR) = '1' else '0';
+	adgen_instr_word        <= pipeline_regs(ST_ADGEN-1).instr_word;
+	adgen_instr_array       <= pipeline_regs(ST_ADGEN-1).instr_array;
+	adgen_optional_ea_word  <= pipeline_regs(ST_ADGEN-2).instr_word;
+	adgen_mode_a            <= pipeline_regs(ST_ADGEN-1).adgen_mode_a;
+	adgen_mode_b            <= pipeline_regs(ST_ADGEN-1).adgen_mode_b;
+
+	-------------------------------
+	-- EXECUTE STAGE INSTANTIATIONS
+	-------------------------------
+	inst_exec_stage_alu: exec_stage_alu port map(
+		alu_activate  => exec_alu_activate,
+		instr_word    => exec_alu_instr_word,
+		alu_ctrl      => exec_alu_ctrl,
+		register_file => register_file,
+		addr_r_in     => exec_alu_addr_r_in,
+		addr_r_out    => exec_alu_addr_r_out,
+		modify_accu   => exec_alu_modify_accu,
+		dst_accu      => exec_alu_dst_accu,
+		modified_accu => exec_alu_modified_accu,
+		modify_sr     => exec_alu_modify_sr,
+		modified_sr   => exec_alu_modified_sr
+	);
+
+	exec_alu_activate   <= pipeline_regs(ST_EXEC-1).act_array(ACT_ALU);
+	exec_alu_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_alu_ctrl       <= pipeline_regs(ST_EXEC-1).alu_ctrl;
+
+	exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0));
+
+	inst_exec_stage_bit_modify: exec_stage_bit_modify port map(
+		instr_word     => exec_bit_modify_instr_word,
+		instr_array    => exec_bit_modify_instr_array,
+		src_operand    => exec_bit_modify_src_operand,
+		register_file  => register_file,
+		dst_operand    => exec_bit_modify_dst_operand,
+		bit_cond_met   => exec_bit_modify_bit_cond_met,
+		modify_sr      => exec_bit_modify_modify_sr,
+		modified_sr    => exec_bit_modify_modified_sr
+	);
+
+	exec_bit_modify_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_bit_modify_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_bit_modify_src_operand  <= exec_src_operand;
+
+	-- Writing to the register file using the 6 bit addressing scheme
+	-- sources are:
+	-- 1) X-RAM output
+	-- 2) Y-RAM output
+	-- 3) register file itself
+	-- 4) short immediate value (8 bit stored in instruction word)
+	-- 5) long immediate value (from optional effective address extension)
+	-- 5) address generated by the address generation unit (LUA instr)
+	exec_src_operand <= pipeline_regs(ST_EXEC-1).RAM_out_x  when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD)  = '1' else
+	                    pipeline_regs(ST_EXEC-1).RAM_out_y  when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD)  = '1' else
+	                    rf_reg_rd_data                      when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD)    = '1' else
+	                    exec_imm_8bit                       when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_8BIT)  = '1' else
+	                    exec_imm_12bit                      when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_12BIT) = '1' else
+	                    pipeline_regs(ST_EXEC-2).instr_word when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_LONG)  = '1' else
+	                    std_logic_vector(resize(pipeline_regs(ST_EXEC-1).adgen_address_x, 24)); -- for LUA instr.
+
+	-- Destination for the register file using the 6 bit addressing scheme.
+	-- Either read the bit modified version of the read value
+	-- or use the modified Rn in case of a NORM instruction
+--	exec_dst_operand <= exec_bit_modify_dst_operand;
+	exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_EXEC-1).act_array(ACT_NORM) = '0' else
+	                    std_logic_vector(resize(exec_alu_addr_r_out,24));
+
+	-- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true
+	inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map(
+		instr_word        => exec_cc_flag_calc_instr_word,
+		instr_array       => exec_cc_flag_calc_instr_array,
+		register_file     => register_file,
+		cc_flag_set       => exec_cc_flag_set
+	);
+
+	exec_cc_flag_calc_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_cc_flag_calc_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+
+
+	inst_exec_stage_branch : exec_stage_branch port map(
+		activate_exec_bra => exec_bra_activate,
+		instr_word        => exec_bra_instr_word,
+		instr_array       => exec_bra_instr_array,
+		register_file     => register_file,
+		jump_address      => exec_bra_jump_address,
+		bit_cond_met      => exec_bra_bit_cond_met,
+		cc_flag_set       => exec_cc_flag_set,
+		push_stack        => exec_bra_push_stack,
+		pop_stack         => exec_bra_pop_stack,
+		modify_pc         => exec_bra_modify_pc,
+		modified_pc       => exec_bra_modified_pc,
+		modify_sr         => exec_bra_modify_sr,
+		modified_sr       => exec_bra_modified_sr
+	);
+
+	exec_bra_activate     <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_BRA);
+	exec_bra_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_bra_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_bra_jump_address <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
+	                         unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0));
+	exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met;
+
+	inst_exec_stage_cr_mod : exec_stage_cr_mod port map(
+		activate_exec_cr_mod => exec_cr_mod_activate,
+		instr_word           => exec_cr_mod_instr_word,
+		instr_array          => exec_cr_mod_instr_array,
+		register_file        => register_file,
+		modify_sr            => exec_cr_mod_modify_sr,
+		modified_sr          => exec_cr_mod_modified_sr,
+		modify_omr           => exec_cr_mod_modify_omr,
+		modified_omr         => exec_cr_mod_modified_omr
+	);
+
+	exec_cr_mod_activate    <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_CR_MOD);
+	exec_cr_mod_instr_word  <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_cr_mod_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
+
+	inst_exec_stage_loop: exec_stage_loop port map(
+		clk                => clk,
+		rst                => rst,
+		activate_exec_loop => exec_loop_activate,
+		instr_word         => exec_loop_instr_word,
+		instr_array        => exec_loop_instr_array,
+		loop_iterations    => exec_loop_iterations,
+		loop_address       => exec_loop_address,
+		loop_start_address => exec_loop_start_address,
+		register_file      => register_file,
+		fetch_perform_enddo=> fetch_perform_enddo,
+		memory_stall       => memory_stall,
+		push_stack         => exec_loop_push_stack,
+		pop_stack          => exec_loop_pop_stack,
+		stall_rep          => exec_loop_stall_rep,
+		stall_do           => exec_loop_stall_do,
+		modify_lc          => exec_loop_modify_lc,
+		decrement_lc       => exec_loop_decrement_lc,
+		modified_lc        => exec_loop_modified_lc,
+		modify_la          => exec_loop_modify_la,
+		modified_la        => exec_loop_modified_la,
+		modify_pc          => exec_loop_modify_pc,
+		modified_pc        => exec_loop_modified_pc,
+		modify_sr          => exec_loop_modify_sr,
+		modified_sr        => exec_loop_modified_sr
+	);
+
+	exec_loop_activate    <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_LOOP);
+	exec_loop_instr_word  <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_loop_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_loop_iterations  <= unsigned(exec_src_operand(15 downto 0));
+	-- from which source is our operand?
+	--  - XMEM
+	--  - YMEM
+	--  - Any register
+	--  - Immediate (from instruction word)
+--	exec_src_operand      <= unsigned(pipeline_regs(ST_EXEC-1).RAM_out_x(BW_ADDRESS-1 downto 0)) when 
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
+--	                         unsigned(pipeline_regs(ST_EXEC-1).RAM_out_y(BW_ADDRESS-1 downto 0)) when 
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
+--	                         unsigned(rf_reg_rd_data(15 downto 0)) when
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else
+--	                         "00000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(15 downto 8));
+
+	-- Loop address is given by the second instruction word of the DO instruction.
+	-- This address is available one previous stage within the pipeline
+	exec_loop_address     <= unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)) - 1; 
+	-- one more stage before we find the programm counter of the first instruction to be executed in a DO loop
+	exec_loop_start_address <= unsigned(pipeline_regs(ST_EXEC-3).pc);
+
+	-- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest)
+	exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else
+	                               pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	exec_imm_8bit(15 downto  8) <= (others => '0');
+	exec_imm_8bit( 7 downto  0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else
+	                               pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	-- The 12 bit immediate stems from the instruction word
+	exec_imm_12bit(23 downto 12) <= (others => '0');
+	exec_imm_12bit(11 downto  0) <= pipeline_regs(ST_EXEC-1).instr_word(3 downto 0) & pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	-----------------
+	-- REGISTER FILE 
+	-----------------
+	inst_reg_file: reg_file port map(
+		clk                => clk,
+		rst                => rst,
+		register_file      => register_file,
+		wr_R_port_A_valid  => rf_wr_R_port_A_valid,
+		wr_R_port_A        => adgen_wr_R_port_A,
+		wr_R_port_B_valid  => rf_wr_R_port_B_valid,
+		wr_R_port_B        => adgen_wr_R_port_B,
+		reg_wr_addr        => rf_reg_wr_addr,
+		reg_wr_addr_valid  => rf_reg_wr_addr_valid,
+		reg_wr_data        => rf_reg_wr_data,
+		reg_rd_addr        => rf_reg_rd_addr,
+		reg_rd_data        => rf_reg_rd_data,
+		alu_wr_valid       => rf_alu_wr_valid,
+		alu_wr_addr        => exec_alu_dst_accu,
+		alu_wr_data        => exec_alu_modified_accu,
+		X_bus_rd_addr      => rf_X_bus_rd_addr, 
+		X_bus_data_out     => rf_X_bus_data_out,
+		X_bus_wr_addr      => rf_X_bus_wr_addr ,
+		X_bus_wr_valid     => rf_X_bus_wr_valid,
+		X_bus_data_in      => rf_X_bus_data_in ,
+		Y_bus_rd_addr      => rf_Y_bus_rd_addr ,
+		Y_bus_data_out     => rf_Y_bus_data_out,
+		Y_bus_wr_addr      => rf_Y_bus_wr_addr ,
+		Y_bus_wr_valid     => rf_Y_bus_wr_valid,
+		Y_bus_data_in      => rf_Y_bus_data_in ,
+		L_bus_rd_addr      => rf_L_bus_rd_addr ,
+		L_bus_rd_valid     => rf_L_bus_rd_valid,
+		L_bus_wr_addr      => rf_L_bus_wr_addr ,
+		L_bus_wr_valid     => rf_L_bus_wr_valid,
+		push_stack         => push_stack,
+		pop_stack          => pop_stack,
+		set_sr             => rf_set_sr,
+		new_sr             => rf_new_sr,
+		set_omr            => rf_set_omr,
+		new_omr            => rf_new_omr,
+		set_la             => rf_set_la,
+		new_la             => rf_new_la,
+		dec_lc             => rf_dec_lc,
+		set_lc             => rf_set_lc,
+		new_lc             => rf_new_lc
+	);
+
+	-----------------
+	-- BUSES (X,Y,L)
+	-----------------
+	rf_X_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_WR);
+	rf_X_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).x_bus_wr_addr;
+	rf_X_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).x_bus_rd_addr;
+	rf_X_bus_data_in  <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' else
+	                     pipeline_regs(ST_EXEC-1).RAM_out_x; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
+
+	rf_Y_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_WR);
+	rf_Y_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).y_bus_wr_addr;
+	rf_Y_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).y_bus_rd_addr;
+	rf_Y_bus_data_in  <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' else
+	                     pipeline_regs(ST_EXEC-1).RAM_out_y; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
+
+	rf_L_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_WR);
+	rf_L_bus_rd_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD);
+	rf_L_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- equal to bits in instruction word
+	rf_L_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- could be simplified by taking these bits..
+
+	-- writing to the R registers within the ADGEN stage has to be prevented when
+	-- 1) a jump is currently being executed (which is detected in the exec stage)
+	-- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling.
+	-- 3) a memory access results in a stall (e.g. caused by the instruction to REP)
+	rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADGEN) = '1' or 
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_A_valid;
+	rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADGEN) = '1' or 
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_B_valid;
+
+
+	rf_reg_wr_addr <= pipeline_regs(ST_EXEC-1).reg_wr_addr;
+	-- can be set due to
+	-- 1) normal write operation (e.g., move)
+	-- 2) conditional move (Tcc)
+	rf_reg_wr_addr_valid <= '1'              when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR) = '1' else
+	                        exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR_CC) = '1' else '0';
+	rf_reg_wr_data <= exec_dst_operand;
+
+	rf_reg_rd_addr <= pipeline_regs(ST_EXEC-1).reg_rd_addr;
+
+	-- Writing from the ALU can depend on the condition code (Tcc) instruction
+	rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_ALU_WR_CC) = '1' else
+	                   exec_alu_modify_accu;
+
+	push_stack.valid   <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0';
+	push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else
+	                      exec_loop_push_stack.content;
+	-- for jump to subroutine store the pc of the subsequent instruction
+	push_stack.pc <= pipeline_regs(ST_EXEC-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
+	                 pipeline_regs(ST_EXEC-3).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '1' else
+					 exec_loop_push_stack.pc     when exec_loop_push_stack.valid = '1' else
+	                 (others => '0');
+
+	pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0';
+
+	rf_set_sr <= '1' when exec_bra_modify_sr = '1' or 
+	                      exec_cr_mod_modify_sr = '1' or 
+	                      exec_loop_modify_sr = '1' or 
+	                      exec_alu_modify_sr = '1' or 
+	                      exec_bit_modify_modify_sr = '1' else '0';
+	rf_new_sr <= exec_bra_modified_sr    when exec_bra_modify_sr = '1'    else 
+	             exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else
+				 exec_loop_modified_sr   when exec_loop_modify_sr = '1' else
+				 exec_alu_modified_sr    when exec_alu_modify_sr = '1' else
+	             exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else
+
+	rf_set_omr <= exec_cr_mod_modify_omr;
+	rf_new_omr <= exec_cr_mod_modified_omr;
+	rf_set_lc <= exec_loop_modify_lc;
+	rf_new_lc <= exec_loop_modified_lc;
+	rf_set_la <= exec_loop_modify_la;
+	rf_new_la <= exec_loop_modified_la;
+
+	rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0';
+
+	---------------------
+	-- MEMORY MANAGEMENT 
+	---------------------
+	MMU_inst: memory_management port map (
+		clk => clk,
+		rst => rst,
+		stall_flags   => stall_flags,
+		memory_stall  => memory_stall,
+		data_rom_enable => register_file.omr(2),
+		pmem_ctrl_in  => pmem_ctrl_in,
+		pmem_ctrl_out => pmem_ctrl_out,
+		xmem_ctrl_in  => xmem_ctrl_in,
+		xmem_ctrl_out => xmem_ctrl_out,
+		ymem_ctrl_in  => ymem_ctrl_in,
+		ymem_ctrl_out => ymem_ctrl_out
+	);
+
+	------------------
+	-- Program Memory
+	------------------
+	pmem_ctrl_in.rd_addr <= pc_new;
+	pmem_ctrl_in.rd_en   <= '1' when stall_flags(ST_FETCH) = '0' else '0';
+	-- TODO: Writing to PMEM!
+	pmem_ctrl_in.wr_addr <= (others => '0');
+	pmem_ctrl_in.wr_en   <= '0';
+	pmem_ctrl_in.data_in <= (others => '0');
+
+	pmem_data_out       <= pmem_ctrl_out.data_out;
+	pmem_data_out_valid <= pmem_ctrl_out.data_out_valid;
+
+
+	------------------
+	-- X Memory
+	------------------
+	-- Either take the result of the AGU or use the short absolute value stored in the instruction word
+	xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
+	xmem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	xmem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
+	xmem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_WR) = '1' else '0';
+	xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' or 
+	                                               pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+	xmem_data_out       <= xmem_ctrl_out.data_out;
+	xmem_data_out_valid <= xmem_ctrl_out.data_out_valid;
+
+	------------------
+	-- Y Memory
+	------------------
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
+	ymem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_y when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
+	ymem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' or
+	                                               pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+	ymem_data_out       <= ymem_ctrl_out.data_out;
+	ymem_data_out_valid <= ymem_ctrl_out.data_out_valid;
+
+
+end architecture rtl;
diff --git a/FPGA_by_Fredi/DSP/src/reg_file.vhd b/FPGA_by_Fredi/DSP/src/reg_file.vhd
new file mode 100644
index 0000000..7f3244c
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/reg_file.vhd
@@ -0,0 +1,679 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity reg_file is port(
+	clk, rst          : in  std_logic;
+	register_file     : out register_file_type;
+	wr_R_port_A_valid : in  std_logic;
+	wr_R_port_A       : in  addr_wr_port_type;
+	wr_R_port_B_valid : in  std_logic;
+	wr_R_port_B       : in  addr_wr_port_type;
+	alu_wr_valid      : in  std_logic;
+	alu_wr_addr       : in  std_logic;
+	alu_wr_data       : in  signed(55 downto 0);
+	reg_wr_addr       : in  std_logic_vector(5 downto 0);
+	reg_wr_addr_valid : in  std_logic;
+	reg_wr_data       : in  std_Logic_vector(23 downto 0);
+	reg_rd_addr       : in  std_logic_vector(5 downto 0);
+	reg_rd_data       : out std_Logic_vector(23 downto 0);
+	X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_data_out    : out std_logic_vector(23 downto 0);
+	X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_wr_valid    : in  std_logic;
+	X_bus_data_in     : in  std_logic_vector(23 downto 0);
+	Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_data_out    : out std_logic_vector(23 downto 0);
+	Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_wr_valid    : in  std_logic;
+	Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+	L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_rd_valid    : in  std_logic;
+	L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_wr_valid    : in  std_logic;
+	push_stack        : in  push_stack_type;
+	pop_stack         : in  pop_stack_type;
+	set_sr            : in  std_logic;
+	new_sr            : in  std_logic_vector(15 downto 0);
+	set_omr           : in  std_logic;
+	new_omr           : in  std_logic_vector(7 downto 0);
+	dec_lc            : in  std_logic;
+	set_lc            : in  std_logic;
+	new_lc            : in  unsigned(15 downto 0);
+	set_la            : in  std_logic;
+	new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+);
+end entity;
+
+
+architecture rtl of reg_file is
+
+	signal addr_r : addr_array;
+	signal addr_m : addr_array;
+	signal addr_n : addr_array;
+
+	signal loop_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal loop_counter : unsigned(15 downto 0);
+
+	-- condition code register
+	signal ccr : std_logic_vector(7 downto 0);
+	-- mode register
+	signal mr  : std_logic_vector(7 downto 0);
+	-- status register = mode register + condition code register
+	signal sr  : std_logic_vector(15 downto 0);
+	-- operation mode register
+	signal omr : std_logic_vector(7 downto 0);
+
+	signal stack_pointer    : unsigned(5 downto 0);
+	signal system_stack_ssh : stack_array_type;
+	signal system_stack_ssl : stack_array_type;
+
+	signal x0 : signed(23 downto 0);
+	signal x1 : signed(23 downto 0);
+	signal y0 : signed(23 downto 0);
+	signal y1 : signed(23 downto 0);
+
+	signal a0 : signed(23 downto 0);
+	signal a1 : signed(23 downto 0);
+	signal a2 : signed(7 downto 0);
+
+	signal b0 : signed(23 downto 0);
+	signal b1 : signed(23 downto 0);
+	signal b2 : signed(7 downto 0);
+	
+	signal limited_a1 : signed(23 downto 0);
+	signal limited_b1 : signed(23 downto 0);
+	signal limited_a0 : signed(23 downto 0);
+	signal limited_b0 : signed(23 downto 0);
+	signal set_limiting_flag  : std_logic;
+	signal X_bus_rd_limited_a : std_logic;
+	signal X_bus_rd_limited_b : std_logic;
+	signal Y_bus_rd_limited_a : std_logic;
+	signal Y_bus_rd_limited_b : std_logic;
+	signal reg_rd_limited_a   : std_logic;
+	signal reg_rd_limited_b   : std_logic;
+	signal rd_limited_a       : std_logic;
+	signal rd_limited_b       : std_logic;
+
+begin
+
+
+
+	sr <= mr & ccr;
+
+	register_file.addr_r <= addr_r;
+	register_file.addr_n <= addr_n;
+	register_file.addr_m <= addr_m;
+	register_file.lc <= loop_counter;
+	register_file.la <= loop_address;
+	register_file.ccr <= ccr;
+	register_file.mr <= mr;
+	register_file.sr <= sr;
+	register_file.omr <= omr;
+	register_file.stack_pointer <= stack_pointer;
+	register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0)));
+	register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0)));
+	register_file.a  <= a2 & a1 & a0;
+	register_file.b  <= b2 & b1 & b0;
+	register_file.x0 <= x0;
+	register_file.x1 <= x1;
+	register_file.y0 <= y0;
+	register_file.y1 <= y1;
+
+
+	global_register_file: process(clk) is
+		variable stack_pointer_plus_1 : unsigned(3 downto 0);
+		variable reg_addr : integer range 0 to 7;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				addr_r <= (others => (others => '0'));
+				addr_n <= (others => (others => '0'));
+				addr_m <= (others => (others => '1'));
+				ccr    <= (others => '0');
+				mr     <= (others => '0');
+				omr    <= (others => '0');
+				system_stack_ssl <= (others => (others => '0'));
+				system_stack_ssh <= (others => (others => '0'));
+				stack_pointer    <= (others => '0');
+				loop_counter <= (others => '0');
+				loop_address <= (others => '0');
+				x0 <= (others => '0');
+				x1 <= (others => '0');
+				y0 <= (others => '0');
+				y1 <= (others => '0');
+				a0 <= (others => '0');
+				a1 <= (others => '0');
+				a2 <= (others => '0');
+				b0 <= (others => '0');
+				b1 <= (others => '0');
+				b2 <= (others => '0');
+			else
+				reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0)));
+				-----------------------------------------------------------------------
+				-- General write port to register file using 6 bit addressing scheme
+				-----------------------------------------------------------------------
+				if reg_wr_addr_valid = '1' then
+					case reg_wr_addr(5 downto 3) is
+						-- X0, X1, Y0, Y1
+						when "000" =>
+							case reg_wr_addr(2 downto 0) is
+								when "100" =>
+									x0 <= signed(reg_wr_data);
+								when "101" =>
+									x1 <= signed(reg_wr_data);
+								when "110" =>
+									y0 <= signed(reg_wr_data);
+								when "111" =>
+									y1 <= signed(reg_wr_data);
+								when others =>
+							end case;
+
+						-- A0, B0, A2, B2, A1, B1, A, B
+						when "001" =>
+							case reg_wr_addr(2 downto 0) is
+								when "000" =>
+									a0 <= signed(reg_wr_data);
+								when "001" =>
+									b0 <= signed(reg_wr_data);
+								when "010" =>
+									a2 <= signed(reg_wr_data(7 downto 0));
+								when "011" =>
+									b2 <= signed(reg_wr_data(7 downto 0));
+								when "100" =>
+									a1 <= signed(reg_wr_data);
+								when "101" =>
+									b1 <= signed(reg_wr_data);
+								when "110" =>
+									a2 <= (others => reg_wr_data(23));
+									a1 <= signed(reg_wr_data);
+									a0 <= (others => '0');
+								when "111" =>
+									b2 <= (others => reg_wr_data(23));
+									b1 <= signed(reg_wr_data);
+									b0 <= (others => '0');
+								when others =>
+							end case;
+
+						-- R0-R7
+						when "010" =>
+							addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- N0-N7
+						when "011" =>
+							addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- M0-M7
+						when "100" =>
+							addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- SR, OMR, SP, SSH, SSL, LA, LC
+						when "111" =>
+							case reg_wr_addr(2 downto 0) is
+								-- SR
+								when "001" =>
+									mr  <= reg_wr_data(15 downto 8);
+									ccr <= reg_wr_data( 7 downto 0);
+
+								-- OMR
+								when "010" =>
+									omr  <= reg_wr_data(7 downto 0);
+
+								-- SP
+								when "011" =>
+									stack_pointer <= unsigned(reg_wr_data(5 downto 0));
+
+								-- SSH
+								when "100" =>
+									system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+									-- increase stack after writing
+									stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+									-- test whether stack is full, if so set the stack error flag (SE)
+									if stack_pointer(3 downto 0) = "1111" then
+										stack_pointer(4) <= '1';
+									end if;
+
+								-- SSL
+								when "101" =>
+									system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+
+								-- LA
+								when "110" =>
+									loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+								-- LC
+								when "111" =>
+									loop_counter <= unsigned(reg_wr_data(15 downto 0));
+
+								when others =>
+							end case;
+						when others =>
+					end case;
+				end if;
+
+				----------------
+				-- X BUS Write
+				----------------
+				if X_bus_wr_valid = '1' then
+					case X_bus_wr_addr is
+						when "00" =>
+							x0 <= signed(X_bus_data_in);
+						when "01" =>
+							x1 <= signed(X_bus_data_in);
+						when "10" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				----------------
+				-- Y BUS Write
+				----------------
+				if Y_bus_wr_valid = '1' then
+					case Y_bus_wr_addr is
+						when "00" =>
+							y0 <= signed(Y_bus_data_in);
+						when "01" =>
+							y1 <= signed(Y_bus_data_in);
+						when "10" =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				------------------
+				-- L BUS Write
+				------------------
+				if L_bus_wr_valid = '1' then
+					case L_bus_wr_addr is
+						-- A10
+						when "000" =>
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B10
+						when "001" =>
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- X
+						when "010" =>
+							x1 <= signed(X_bus_data_in);
+							x0 <= signed(Y_bus_data_in);
+						-- Y
+						when "011" =>
+							y1 <= signed(X_bus_data_in);
+							y0 <= signed(Y_bus_data_in);
+						-- A
+						when "100" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B
+						when "101" =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- AB
+						when "110" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+						-- BA
+						when others =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+
+				---------------------
+				-- STATUS REGISTERS
+				---------------------
+				if set_sr = '1' then
+					ccr <= new_sr( 7 downto 0);
+					mr  <= new_sr(15 downto 8);
+				end if;
+				if set_omr = '1' then
+					omr <= new_omr;
+				end if;
+				-- data limiter active?
+				-- listing this statement after the set_sr test results
+				-- in the correct behaviour for ALU operations with parallel move
+				if set_limiting_flag = '1' then
+					ccr(6) <= '1';
+				end if;
+
+				--------------------
+				-- LOOP REGISTERS 
+				--------------------
+				if set_la = '1' then
+					loop_address <= new_la;
+				end if;
+				if set_lc = '1' then
+					loop_counter <= new_lc;
+				end if;
+				if dec_lc = '1' then
+					loop_counter <= loop_counter - 1;
+				end if;
+
+				---------------------
+				-- ADDRESS REGISTER
+				---------------------
+				if wr_R_port_A_valid = '1' then
+					addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value;
+				end if;
+				if wr_R_port_B_valid = '1' then
+					addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value;
+				end if;
+
+				-------------------------
+				-- ALU ACCUMULATOR WRITE
+				-------------------------
+				if alu_wr_valid = '1' then
+					if alu_wr_addr = '0' then
+						a2 <= alu_wr_data(55 downto 48);
+						a1 <= alu_wr_data(47 downto 24);
+						a0 <= alu_wr_data(23 downto  0);
+					else
+						b2 <= alu_wr_data(55 downto 48);
+						b1 <= alu_wr_data(47 downto 24);
+						b0 <= alu_wr_data(23 downto  0);
+					end if;
+				end if;
+
+				---------------------
+				-- STACK CONTROLLER 
+				---------------------
+				stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1;
+				if push_stack.valid = '1' then
+					-- increase stack after writing
+					stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+					-- test whether stack is full, if so set the stack error flag (SE)
+					if stack_pointer(3 downto 0) = "1111" then
+						stack_pointer(4) <= '1';
+					end if;
+					case push_stack.content is
+						when PC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+
+						when PC_AND_SR =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR;
+
+						when LA_AND_LC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter);
+
+					end case;
+				end if;
+
+				-- decrease stack pointer
+				if pop_stack.valid = '1' then
+					stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1;
+					-- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE)
+					if stack_pointer(3 downto 0) = "0000" then
+						stack_pointer(5) <= '1';
+						stack_pointer(4) <= '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,y1) is
+	begin
+		X_bus_rd_limited_a <= '0';
+		X_bus_rd_limited_b <= '0';
+		case X_bus_rd_addr is
+			when "00" =>   X_bus_data_out <= std_logic_vector(x0);
+			when "01" =>   X_bus_data_out <= std_logic_vector(x1);
+			when "10" =>   X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+			when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  X_bus_data_out <= std_logic_vector(a1);
+				when "001" =>  X_bus_data_out <= std_logic_vector(b1);
+				when "010" =>  X_bus_data_out <= std_logic_vector(x1);
+				when "011" =>  X_bus_data_out <= std_logic_vector(y1);
+				when "100" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when "101" =>  X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+				when "110" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+			end case;
+		end if;
+	end process x_bus_rd_port;
+
+	y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is
+	begin
+		Y_bus_rd_limited_a <= '0';
+		Y_bus_rd_limited_b <= '0';
+		case Y_bus_rd_addr is
+			when "00" =>   Y_bus_data_out <= std_logic_vector(y0);
+			when "01" =>   Y_bus_data_out <= std_logic_vector(y1);
+			when "10" =>   Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  Y_bus_data_out <= std_logic_vector(a0);
+				when "001" =>  Y_bus_data_out <= std_logic_vector(b0);
+				when "010" =>  Y_bus_data_out <= std_logic_vector(x0);
+				when "011" =>  Y_bus_data_out <= std_logic_vector(y0);
+				when "100" =>  Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1';
+				when "101" =>  Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1';
+				when "110" =>  Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+				when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			end case;
+		end if;
+	end process y_bus_rd_port;
+
+
+	reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2,
+	                     omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer,
+	                     loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is
+		variable reg_addr : integer range 0 to 7;
+	begin
+		reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0)));
+		reg_rd_data <= (others => '0');
+		reg_rd_limited_a <= '0';
+		reg_rd_limited_b <= '0';
+
+		case reg_rd_addr(5 downto 3) is
+			-- X0, X1, Y0, Y1
+			when "000" =>
+				case reg_rd_addr(2 downto 0) is
+					when "100" =>
+						reg_rd_data <= std_logic_vector(x0);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(x1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(y0);
+					when "111" =>
+						reg_rd_data <= std_logic_vector(y1);
+					when others =>
+				end case;
+
+			-- A0, B0, A2, B2, A1, B1, A, B
+			when "001" =>
+				case reg_rd_addr(2 downto 0) is
+					when "000" =>
+						reg_rd_data <= std_logic_vector(a0);
+					when "001" =>
+						reg_rd_data <= std_logic_vector(b0);
+					when "010" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(a2);
+					when "011" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(b2);
+					when "100" =>
+						reg_rd_data <= std_logic_vector(a1);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(b1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(limited_a1);
+						reg_rd_limited_a <= '1';
+					when "111" =>
+						reg_rd_data <= std_logic_vector(limited_b1);
+						reg_rd_limited_b <= '1';
+					when others =>
+				end case;
+
+			-- R0-R7
+			when "010" =>
+				reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24));
+
+			-- N0-N7
+			when "011" =>
+				reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24));
+
+			-- M0-M7
+			when "100" =>
+				reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24));
+
+			-- SR, OMR, SP, SSH, SSL, LA, LC
+			when "111" =>
+				case reg_wr_addr(2 downto 0) is
+					-- SR
+					when "001" =>
+						reg_rd_data(23 downto 16) <= (others => '0');
+						reg_rd_data(15 downto  0) <= mr & ccr;
+
+					-- OMR
+					when "010" =>
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data( 7 downto 0) <= omr;
+
+					-- SP
+					when "011" =>
+						reg_rd_data(23 downto 6) <= (others => '0');
+						reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer);
+
+					-- SSH
+					when "100" =>
+-- TODO!
+--						system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+--						-- increase stack after writing
+--						stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+--						-- test whether stack is full, if so set the stack error flag (SE)
+--						if stack_pointer(3 downto 0) = "1111" then
+--							stack_pointer(4) <= '1';
+--						end if;
+
+					-- SSL
+					when "101" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer)));
+
+					-- LA
+					when "110" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address);
+
+					-- LC
+					when "111" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter);
+
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process;
+
+	rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0';
+	rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0';
+
+	data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is
+		variable scaled_a : signed(55 downto 0);
+		variable scaled_b : signed(55 downto 0);
+	begin
+
+		set_limiting_flag <= '0';
+		-----------------
+		-- DATA SCALING
+		-----------------
+		-- test against scaling bits S1, S0
+		case sr(11 downto 10) is
+			-- scale down (right shift)
+			when "01" =>
+				scaled_a := a2(7) & a2 & a1 & a0(23 downto 1);
+				scaled_b := b2(7) & b2 & b1 & b0(23 downto 1);
+			-- scale up (arithmetic left shift)
+			when "10" =>
+				scaled_a := a2(6 downto 0) & a1 & a0 & '0';
+				scaled_b := b2(6 downto 0) & b1 & b0 & '0';
+			-- "00" do not scale!
+			when others =>
+				scaled_a := a2 & a1 & a0;
+				scaled_b := b2 & b1 & b0;
+		end case;
+
+		-- only sign extension stored in a2?
+		-- Yes: No limiting needed!
+		if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then
+			limited_a1 <= scaled_a(47 downto 24);
+			limited_a0 <= scaled_a(23 downto  0);
+		else
+			-- positive value in a?
+			if scaled_a(55) = '0' then
+				limited_a1 <= X"7FFFFF";
+				limited_a0 <= X"FFFFFF";
+			-- negative value in a?
+			else
+				limited_a1 <= X"800000";
+				limited_a0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_a = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+		-- only sign extension stored in b2?
+		-- Yes: No limiting needed!
+		if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then
+			limited_b1 <= scaled_b(47 downto 24);
+			limited_b0 <= scaled_b(23 downto  0);
+		else
+			-- positive value in b?
+			if scaled_b(55) = '0' then
+				limited_b1 <= X"7FFFFF";
+				limited_b0 <= X"FFFFFF";
+			-- negative value in b?
+			else
+				limited_b1 <= X"800000";
+				limited_b0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_b = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture rtl;
diff --git a/FPGA_by_Fredi/DSP/src/types_pkg.vhd b/FPGA_by_Fredi/DSP/src/types_pkg.vhd
new file mode 100644
index 0000000..131f7fa
--- /dev/null
+++ b/FPGA_by_Fredi/DSP/src/types_pkg.vhd
@@ -0,0 +1,167 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+
+
+
+package types_pkg is
+
+	-- the different addressing modes
+	type adgen_mode_type is (NOP, POST_MIN_N, POST_PLUS_N, POST_MIN_1, POST_PLUS_1, INDEXED_N, PRE_MIN_1, ABSOLUTE, IMMEDIATE);
+	------------------------
+	-- Decoded instructions
+	------------------------
+	type instructions_type is (
+	INSTR_NOP     ,
+	INSTR_RTI     ,
+	INSTR_ILLEGAL ,
+	INSTR_SWI     ,
+	INSTR_RTS     ,
+	INSTR_RESET   ,
+	INSTR_WAIT    ,
+	INSTR_STOP    ,
+	INSTR_ENDDO   ,
+	INSTR_ANDI    ,
+	INSTR_ORI     ,
+	INSTR_DIV     ,
+	INSTR_NORM    ,
+	INSTR_LUA     ,
+	INSTR_MOVEC   ,
+	INSTR_REP     ,
+	INSTR_DO      ,
+	INSTR_MOVEM   ,
+	INSTR_MOVEP   ,
+	INSTR_PM_MOVEM,
+	INSTR_BCLR    ,
+	INSTR_BSET    ,
+	INSTR_JCLR    ,
+	INSTR_JSET    ,
+	INSTR_JMP     ,
+	INSTR_JCC     ,
+	INSTR_BCHG    ,
+	INSTR_BTST    ,
+	INSTR_JSCLR   ,
+	INSTR_JSSET   ,
+	INSTR_JSR     ,
+	INSTR_JSCC    );
+
+	type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0);
+
+	type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS);
+	type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET);
+	type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag;
+
+	type alu_ctrl_type is record
+		mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		shift_src  : std_logic; -- a,b
+		shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		shift_mode : alu_shift_mode;
+		rotate     : std_logic;  -- 0: logical shift, 1: rotate shift
+		add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+		add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+		add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		logic_function : std_logic_vector(2 downto 0);  -- 000: none, 001: and, 010: or, 011: eor, 100: not
+		word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+		rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+		store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+		dst_accu       : std_logic; -- 0: a, 1: b
+		div_instr      : std_logic; -- DIV instruction? Special ALU operations needed!
+		norm_instr     : std_logic; -- NORM instruction? Special ALU operations needed!
+		ccr_flags_ctrl : alu_ccr_flag_array;
+	end record;
+
+	type pipeline_signals is record
+		instr_word: std_logic_vector(23 downto 0);
+		pc        : unsigned(BW_ADDRESS-1 downto 0);
+		dble_word_instr : std_logic;
+		instr_array     : instructions_type;
+		act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		dec_activate    : std_logic;
+		adgen_mode_a    : adgen_mode_type;
+		adgen_mode_b    : adgen_mode_type;
+		reg_wr_addr     : std_logic_vector(5 downto 0);
+		reg_rd_addr     : std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : std_logic_vector(1 downto 0);
+		x_bus_wr_addr   : std_logic_vector(1 downto 0);
+		y_bus_rd_addr   : std_logic_vector(1 downto 0);
+		y_bus_wr_addr   : std_logic_vector(1 downto 0);
+		l_bus_addr      : std_logic_vector(2 downto 0);
+		adgen_address_x : unsigned(BW_ADDRESS-1 downto 0);
+		adgen_address_y : unsigned(BW_ADDRESS-1 downto 0);
+		RAM_out_x       : std_logic_vector(23 downto 0);
+		RAM_out_y       : std_logic_vector(23 downto 0);
+		alu_ctrl        : alu_ctrl_type;
+	end record;
+
+	type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals;
+
+
+	type register_file_type is record 
+		a            : signed(55 downto 0);
+		b            : signed(55 downto 0);
+		x0           : signed(23 downto 0);
+		x1           : signed(23 downto 0);
+		y0           : signed(23 downto 0);
+		y1           : signed(23 downto 0);
+		la           : unsigned(BW_ADDRESS-1 downto 0);
+		lc           : unsigned(15 downto 0);
+		addr_r       : addr_array;
+		addr_n       : addr_array;
+		addr_m       : addr_array;
+		ccr          : std_logic_vector(7 downto 0);
+		mr           : std_logic_vector(7 downto 0);
+		sr           : std_logic_vector(15 downto 0);
+		omr          : std_logic_vector(7 downto 0);
+		stack_pointer    : unsigned(5 downto 0);
+--		system_stack_ssh : stack_array_type;
+--		system_stack_ssl : stack_array_type;
+		current_ssh      : std_logic_vector(BW_ADDRESS-1 downto 0);
+		current_ssl      : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	end record;
+
+	type addr_wr_port_type is record
+--		write_valid : std_logic;
+		reg_number  : unsigned(2 downto 0);
+		reg_value   : unsigned(15 downto 0);
+	end record;
+
+	type mem_ctrl_type_in is record
+		rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		rd_en     : std_logic;
+		wr_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		wr_en     : std_logic;
+		data_in   : std_logic_vector(23 downto 0);
+	end record;
+
+	type mem_ctrl_type_out is record
+		data_out       : std_logic_vector(23 downto 0);
+		data_out_valid : std_logic;
+	end record;
+
+	type memory_type is (X_MEM, Y_MEM, P_MEM);
+	---------------
+	-- STACK TYPES
+	---------------
+	type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC);
+
+	type push_stack_type is record
+		valid   : std_logic;
+		pc      : unsigned(BW_ADDRESS-1 downto 0);
+		content : push_stack_content_type;
+	end record;
+
+--	type pop_stack_content_type is (PC, PC_AND_SR, SR, LA_AND_LC);
+
+--	type pop_stack_type is std_logic;
+	type pop_stack_type is record
+		valid : std_logic;
+--		content : pop_stack_content_type;
+	end record;
+
+end package types_pkg;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
new file mode 100644
index 0000000..b2b8dbb
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
@@ -0,0 +1,971 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:20 2009
+
+library work;
+use work.FalconIO_SDCard_IDE_CF_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+--  Entity Declaration
+
+
+--  Entity Declaration
+
+ENTITY FalconIO_SDCard_IDE_CF IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		CLK2M : IN STD_LOGIC;
+		CLK500k : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		LP_BUSY : IN STD_LOGIC;
+		nACSI_DRQ : IN STD_LOGIC;
+		nACSI_INT : IN STD_LOGIC;
+		nSCSI_DRQ : IN STD_LOGIC;
+		nSCSI_MSG : IN STD_LOGIC;
+		MIDI_IN : IN STD_LOGIC;
+		RxD : IN STD_LOGIC;
+		CTS : IN STD_LOGIC;
+		RI : IN STD_LOGIC;
+		DCD : IN STD_LOGIC;
+		AMKB_RX : IN STD_LOGIC;
+		PIC_AMKB_RX : IN STD_LOGIC;
+		IDE_RDY : IN STD_LOGIC;
+		IDE_INT : IN STD_LOGIC;
+		WP_CS_CARD : IN STD_LOGIC;
+		nINDEX : IN STD_LOGIC;
+		TRACK00 : IN STD_LOGIC;
+		nRD_DATA : IN STD_LOGIC;
+		nDCHG : IN STD_LOGIC;
+		SD_DATA0 : IN STD_LOGIC;
+		SD_DATA1 : IN STD_LOGIC;
+		SD_DATA2 : IN STD_LOGIC;
+		SD_CARD_DEDECT : IN STD_LOGIC;
+		SD_WP : IN STD_LOGIC;
+		nDACK0 : IN STD_LOGIC;
+		nFB_WR : INOUT STD_LOGIC;
+		WP_CF_CARD : IN STD_LOGIC;
+		nWP : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nRSTO : IN STD_LOGIC;
+		HD_DD : IN STD_LOGIC;
+		nSCSI_C_D : IN STD_LOGIC;
+		nSCSI_I_O : IN STD_LOGIC;
+		CLK2M4576 : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		VSYNC : IN STD_LOGIC;
+		HSYNC : IN STD_LOGIC;
+		DSP_INT : IN STD_LOGIC;
+		nBLANK : IN STD_LOGIC;
+		FDC_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
+		nIDE_CS1 : OUT STD_LOGIC;
+		nIDE_CS0 : OUT STD_LOGIC;
+		LP_STR : OUT STD_LOGIC;
+		LP_DIR : OUT STD_LOGIC;
+		nACSI_ACK : OUT STD_LOGIC;
+		nACSI_RESET : OUT STD_LOGIC;
+		nACSI_CS : OUT STD_LOGIC;
+		ACSI_DIR : OUT STD_LOGIC;
+		ACSI_A1 : OUT STD_LOGIC;
+		nSCSI_ACK : OUT STD_LOGIC;
+		nSCSI_ATN : OUT STD_LOGIC;
+		SCSI_DIR : OUT STD_LOGIC;
+		SD_CLK : OUT STD_LOGIC;
+		YM_QA : OUT STD_LOGIC;
+		YM_QC : OUT STD_LOGIC;
+		YM_QB : OUT STD_LOGIC;
+		nSDSEL : OUT STD_LOGIC;
+		STEP : OUT STD_LOGIC;
+		MOT_ON : OUT STD_LOGIC;
+		nRP_LDS : OUT STD_LOGIC;
+		nRP_UDS : OUT STD_LOGIC;
+		nROM4 : OUT STD_LOGIC;
+		nROM3 : OUT STD_LOGIC;
+		nCF_CS1 : OUT STD_LOGIC;
+		nCF_CS0 : OUT STD_LOGIC;
+		nIDE_RD : INOUT STD_LOGIC;
+		nIDE_WR : INOUT STD_LOGIC;
+		AMKB_TX : OUT STD_LOGIC;
+		IDE_RES : OUT STD_LOGIC;
+		DTR : OUT STD_LOGIC;
+		RTS : OUT STD_LOGIC;
+		TxD : OUT STD_LOGIC;
+		MIDI_OLR : OUT STD_LOGIC;
+		MIDI_TLR : OUT STD_LOGIC;
+		nDREQ0 : OUT STD_LOGIC;
+		DSA_D : OUT STD_LOGIC;
+		nMFP_INT : OUT STD_LOGIC;
+		FALCON_IO_TA : OUT STD_LOGIC;
+		STEP_DIR : OUT STD_LOGIC;
+		WR_DATA : OUT STD_LOGIC;
+		WR_GATE : OUT STD_LOGIC;
+		DMA_DRQ : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_PAR : INOUT STD_LOGIC;
+		nSCSI_SEL : INOUT STD_LOGIC;
+		nSCSI_BUSY : INOUT STD_LOGIC;
+		nSCSI_RST : INOUT STD_LOGIC;
+		SD_CD_DATA3 : INOUT STD_LOGIC;
+		SD_CDM_D1 : INOUT STD_LOGIC
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END FalconIO_SDCard_IDE_CF;
+
+
+--  Architecture Body
+
+ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
+-- system
+signal SYS_CLK					: STD_LOGIC;
+signal RESETn					: STD_LOGIC;
+signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
+signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
+signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
+signal LONG						: STD_LOGIC;	-- WENN  -> 1
+-- KEYBOARD MIDI
+signal ACIA_CS_I				: STD_LOGIC;
+signal IRQ_KEYBDn				: STD_LOGIC;
+signal IRQ_MIDIn				: STD_LOGIC;
+signal KEYB_RxD					: STD_LOGIC;
+signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal MIDI_OUT					: STD_LOGIC;
+signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
+signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
+-- MFP
+signal MFP_CS					: STD_LOGIC;
+signal MFP_INTACK				: STD_LOGIC;
+signal LDS						: STD_LOGIC;
+signal DTACK_OUT_MFPn			: STD_LOGIC;
+signal IRQ_ACIAn				: STD_LOGIC;
+signal DINTn					: STD_LOGIC;
+signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
+signal TDO						: STD_LOGIC;
+-- SOUND
+signal SNDCS					: STD_LOGIC;
+signal SNDCS_I					: STD_LOGIC;
+signal SNDIR_I					: STD_LOGIC;
+signal LP_DIR_X					: STD_LOGIC;
+signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+-- DIV
+signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
+signal ROM_CS					: STD_LOGIC;
+-- DMA UND FLOPPY
+signal DMA_DATEN_CS				: STD_LOGIC;
+signal DMA_MODUS_CS				: STD_LOGIC;
+signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
+signal WDC_BSL_CS				: STD_LOGIC;
+signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal HD_DD_OUT				: STD_LOGIC;
+signal FDCS_In					: STD_LOGIC;
+signal CA0						: STD_LOGIC;
+signal CA1						: STD_LOGIC;
+signal CA2						: STD_LOGIC;
+signal FDINT					: STD_LOGIC;
+signal FDRQ						: STD_LOGIC;
+signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_TOP_CS				: STD_LOGIC;
+signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_HIGH_CS				: STD_LOGIC;
+signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_MID_CS				: STD_LOGIC;
+signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_LOW_CS				: STD_LOGIC;
+signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_DIRM_CS				: STD_LOGIC;
+signal DMA_ADR_CS				: STD_LOGIC;
+signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
+signal DMA_DIR_OLD				: STD_LOGIC;
+signal DMA_BYT_CNT_CS			: STD_LOGIC;
+signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
+signal CLR_FIFO					: STD_LOGIC;
+signal DMA_DRQ_I				: STD_LOGIC;
+signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
+signal DMA_DRQQ					: STD_LOGIC;
+signal DMA_DRQ_Q				: STD_LOGIC;
+signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
+signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal RDF_RDE					: STD_LOGIC;
+signal RDF_WRE					: STD_LOGIC;
+signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal WRF_RDE					: STD_LOGIC;
+signal WRF_WRE					: STD_LOGIC;
+signal nFDC_WR					: STD_LOGIC;
+type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
+signal FCF_STATE				: FCF_STATES;
+signal NEXT_FCF_STATE			: FCF_STATES;
+signal DMA_REQ					: STD_LOGIC;
+signal FDC_CS					: STD_LOGIC;
+signal FCF_CS					: STD_LOGIC;
+signal FCF_APH					: STD_LOGIC;
+signal DMA_AZ_CS				: STD_LOGIC;
+signal DMA_ACTIV				: STD_LOGIC;
+signal DMA_ACTIV_NEW			: STD_LOGIC;
+signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
+-- SCSI
+signal SCSI_CS					: STD_LOGIC;
+signal SCSI_CSn					: STD_LOGIC;
+signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
+signal nSCSI_DACK				: STD_LOGIC;
+signal SCSI_DRQ					: STD_LOGIC;
+signal SCSI_INT					: STD_LOGIC;
+signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
+signal DB_EN					: STD_LOGIC;
+signal DBP_OUTn					: STD_LOGIC;
+signal DBP_EN					: STD_LOGIC;
+signal RST_OUTn					: STD_LOGIC;
+signal RST_EN					: STD_LOGIC;
+signal BSY_OUTn					: STD_LOGIC;
+signal BSY_EN					: STD_LOGIC;
+signal SEL_OUTn					: STD_LOGIC;
+signal SEL_EN					: STD_LOGIC;
+-- IDE
+signal nnIDE_RES				: STD_LOGIC;
+signal IDE_CF_CS				: STD_LOGIC;
+signal IDE_CF_TA				: STD_LOGIC;
+signal NEXT_nIDE_RD				: STD_LOGIC;
+signal NEXT_nIDE_WR				: STD_LOGIC;
+type CMD_STATES is(	IDLE, T1, T6, T7);
+signal CMD_STATE				: CMD_STATES;
+signal NEXT_CMD_STATE			: CMD_STATES;
+
+	
+BEGIN
+LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
+BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
+FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
+FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
+
+FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
+           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
+nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nDREQ0 <= '0';
+----------------------------------------------------------------------------
+-- SD
+----------------------------------------------------------------------------
+SD_CLK <= 'Z';
+SD_CD_DATA3 <= 'Z';
+SD_CDM_D1 <= 'Z';
+----------------------------------------------------------------------------
+-- IDE
+----------------------------------------------------------------------------
+CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
+	begin
+		if nRSTO = '0' then
+			CMD_STATE <= IDLE;
+		elsif rising_edge(MAIN_CLK) then
+				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
+				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
+				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
+			else
+				CMD_STATE <= CMD_STATE; 		-- halten
+				nIDE_RD   <= nIDE_RD;			-- halten
+				nIDE_WR   <= nIDE_WR;			-- halten
+			end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
+	begin
+		case CMD_STATE is
+			when IDLE =>
+				IDE_CF_TA <= '0';
+				if  IDE_CF_CS = '1' then
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T1;
+				else
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= IDLE; 		 
+				end if;
+			when T1 =>
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= not nFB_WR;
+				NEXT_nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T6;
+			when T6 =>
+				IF IDE_RDY = '1' then
+					IDE_CF_TA <= '1';
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= T7;
+				else
+					IDE_CF_TA <= '0';
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T6;
+				end if;
+			when T7 => 
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= '1';
+				NEXT_nIDE_WR <= '1';
+				NEXT_CMD_STATE <= IDLE;
+		end case;
+	end process CMD_DECODER;
+	
+IDE_RES <= not nnIDE_RES and nRSTO;
+IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
+nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
+nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
+nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
+nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- ACSI, SCSI UND FLOPPY WD1772 
+-------------------------------------------------------------------------------------------------------------------------------------------
+-- daten read fifo
+	RDF: dcfifo0
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> RDF_DIN,
+			rdclk				=> MAIN_CLK,
+			rdreq				=> RDF_RDE,
+			wrclk				=> FDC_CLK,
+			wrreq				=> RDF_WRE,
+			q					=> RDF_DOUT,
+			wrusedw				=> RDF_AZ
+	);
+FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
+FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
+RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
+FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
+RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
+-- daten write fifo
+	WRF: dcfifo1
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
+			rdclk				=> FDC_CLK,
+			rdreq				=> WRF_RDE,
+			wrclk				=> MAIN_CLK,
+			wrreq				=> WRF_WRE,
+			q					=> WRF_DOUT,
+			rdusedw				=> WRF_AZ
+	);
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
+FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
+	begin
+		if nRSTO = '0' THEN
+			WRF_WRE <= '0';
+		elsif rising_edge(MAIN_CLK) then
+				IF FCF_APH = '1' and nFB_WR = '0' then
+					WRF_WRE <= '1';
+				else
+					WRF_WRE <= '0';
+				end if;
+			else
+				WRF_WRE <= WRF_WRE;
+			end if;
+	END PROCESS;
+ 
+FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
+	begin
+		if nRSTO = '0' then
+			FCF_STATE <= FCF_IDLE;
+			DMA_ACTIV <= '0';
+		elsif rising_edge(FDC_CLK) then
+				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
+				DMA_ACTIV <= DMA_ACTIV_NEW;
+			else
+				FCF_STATE <= FCF_STATE; 					-- halten
+				DMA_ACTIV <= DMA_ACTIV;
+			end if;
+	end process FCF_REG;
+
+FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
+	begin
+		if nRSTO = '0' then
+			FDC_OUT <= x"00";
+		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
+				FDC_OUT <= CD_OUT_FDC; 						-- set
+			else
+				FDC_OUT <= FDC_OUT; 						-- halten
+			end if;
+	end process FDC_REG;
+
+DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
+FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
+SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
+
+	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
+	begin
+		case FCF_STATE is
+			when FCF_IDLE =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
+					DMA_ACTIV_NEW <= DMA_REQ;
+					NEXT_FCF_STATE <= FCF_T0;
+				else
+					DMA_ACTIV_NEW <= '0';
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+			when FCF_T0 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= DMA_REQ;
+				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
+				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
+					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
+				else
+					NEXT_FCF_STATE <= FCF_T1;
+				end if;
+			when FCF_T1 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T2;
+			when FCF_T2 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T3;
+			when FCF_T3 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T6;
+			when FCF_T6 =>
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
+				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
+				NEXT_FCF_STATE <= FCF_T7;
+			when FCF_T7 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= '0';
+				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
+					NEXT_FCF_STATE <= FCF_T7;
+				else
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+		end case;
+	end process FCF_DECODER;
+
+	I_FDC: WF1772IP_TOP_SOC
+		port map(
+            CLK					=> FDC_CLK,
+			RESETn				=> nRSTO,
+			CSn					=> FDCS_In,
+			RWn					=> nFDC_WR,
+			A1					=> CA2,
+			A0					=> CA1,
+			DATA_IN				=> CD_IN_FDC,
+			DATA_OUT			=> CD_OUT_FDC,
+--			DATA_EN				=> CD_EN_FDC,
+			RDn					=> nRD_DATA,
+			TR00n				=> TRACK00,
+			IPn					=> nINDEX,
+			WPRTn				=> nWP,
+			DDEn				=> '0', -- Fixed to MFM.
+			HDTYPE				=> HD_DD_OUT,  
+			MO					=> MOT_ON,
+			WG					=> WR_GATE,
+			WD					=> WR_DATA,
+			STEP				=> STEP,
+			DIRC				=> STEP_DIR,
+			DRQ					=> DMA_DRQ_I,
+			INTRQ				=> FDINT 
+		);
+DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
+DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
+WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
+HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
+nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
+CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
+CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
+CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
+FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
+                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
+      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
+--- WDC BSL REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			WDC_BSL <= "00";
+		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
+			else
+				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
+			end if;
+		end if;
+	END PROCESS;
+--- DMA MODUS REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			DMA_MODUS <= x"0000";
+		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
+			else
+				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
+			end if;
+			IF FB_B1 = '1' THEN
+				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
+			else
+				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
+			end if;
+		else
+			DMA_MODUS <= DMA_MODUS;
+		end if;
+	END PROCESS;
+-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
+	begin
+		if nRSTO = '0' or CLR_FIFO = '1' THEN
+			DMA_BYT_CNT <= x"00000000";													 
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
+				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
+				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
+				DMA_BYT_CNT(8 downto 0) <= "000000000";
+			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
+					DMA_BYT_CNT <= FB_AD;
+				else
+					DMA_BYT_CNT <= DMA_BYT_CNT;
+				end if;
+	END PROCESS;
+--------------------------------------------------------------------
+FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+DMA_STATUS(0) <= '1';													-- DMA OK
+DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
+DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
+DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
+            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
+DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
+	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DRQ_REG <= "00";
+		elsif rising_edge(FDC_CLK) then
+				DMA_DRQ_REG(0) <= DMA_DRQQ;
+				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
+			else
+				DMA_DRQ_REG <= DMA_DRQ_REG;
+			end if;
+	END PROCESS;
+-- DMA ADRESSE ------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_TOP <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_TOP <= FB_AD(31 downto 24);
+			else 
+				DMA_TOP <= DMA_TOP;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_HIGH <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_HIGH <= FB_AD(23 downto 16);
+			else
+				DMA_HIGH <= DMA_HIGH;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
+	begin
+		DMA_MID <= DMA_MID;
+		if nRSTO = '0' THEN
+			DMA_MID <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_MID_CS = '1' then
+					DMA_MID <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_MID <= FB_AD(15 downto 8);
+					end if;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
+	begin
+		DMA_LOW <= DMA_LOW;
+		if nRSTO = '0' THEN
+			DMA_LOW <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_LOW_CS = '1'then
+					DMA_LOW <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_LOW <= FB_AD(7 downto 0);
+					end if;
+			end if;
+	END PROCESS;
+--------------------------------------------------------------------------------------------
+DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
+DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
+DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
+DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
+FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+-- DIRECTZUGRIFF
+DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
+DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
+DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
+FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+-- DMA RW TOGGLE ------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DIR_OLD <= '0';
+		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
+				DMA_DIR_OLD <= DMA_MODUS(8);
+			else
+				DMA_DIR_OLD <= DMA_DIR_OLD;
+			end if;
+	END PROCESS;
+CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
+-- SCSI ----------------------------------------------------------------------------------
+    I_SCSI: WF5380_TOP_SOC
+        port map(
+            CLK					=> FDC_CLK,
+            RESETn				=> nRSTO,
+			ADR			        => CA2 & CA1 & CA0,
+			DATA_IN		        => CD_IN_FDC,	
+			DATA_OUT			=> SCSI_DOUT,
+			--DATA_EN			: out bit;
+            -- Bus and DMA controls:
+			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			RDn		            => (not nFDC_WR) or (not SCSI_CS),
+			WRn	                =>      nFDC_WR  or (not SCSI_CS),
+            EOPn                => '1',
+			DACKn	            => nSCSI_DACK,
+			DRQ		            => SCSI_DRQ,
+			INT		            => SCSI_INT,
+--            READY                	=> 
+            -- SCSI bus:
+            DB_INn		        => SCSI_D,
+            DB_OUTn		        => DB_OUTn,
+            DB_EN               => DB_EN,
+            DBP_INn		        => SCSI_PAR,
+            DBP_OUTn	        => DBP_OUTn,
+            DBP_EN              => DBP_EN,				-- wenn 1 dann output
+            RST_INn             => nSCSI_RST,
+            RST_OUTn            => RST_OUTn,
+            RST_EN              => RST_EN,
+            BSY_INn             => nSCSI_BUSY,
+            BSY_OUTn            => BSY_OUTn,
+            BSY_EN              => BSY_EN,
+            SEL_INn             => nSCSI_SEL,
+            SEL_OUTn            => SEL_OUTn,
+            SEL_EN              => SEL_EN,
+            ACK_INn             => '1',
+            ACK_OUTn            => nSCSI_ACK,
+--            ACK_EN              => ACK_EN,
+            ATN_INn             => '1',
+            ATN_OUTn            => nSCSI_ATN,
+--            ATN_EN              => ATN_EN,
+            REQ_INn             => nSCSI_DRQ,
+--            REQ_OUTn            => REQ_OUTn,
+--            REQ_EN              => REQ_EN,
+            IOn_IN              => nSCSI_I_O,
+--            IOn_OUT             => IOn_OUT,
+--            IO_EN               => IO_EN,
+            CDn_IN              => nSCSI_C_D,
+--            CDn_OUT             => CDn_OUT,
+--            CD_EN               => CD_EN,
+            MSG_INn             => nSCSI_MSG
+--            MSG_OUTn            => MSG_OUTn,
+--            MSG_EN              => MSG_EN
+        );              
+-- SCSI ACSI ---------------------------------------------------------------
+SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
+nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+ACSI_DIR <= '0';
+ACSI_D <= "ZZZZZZZZ";
+nACSI_CS <= '1';
+ACSI_A1 <= CA1;
+nACSI_RESET <= nRSTO;
+nACSI_ACK <= '1';
+----------------------------------------------------------------------------
+-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
+----------------------------------------------------------------------------
+ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
+nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
+nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
+----------------------------------------------------------------------------
+-- ACIA KEYBOARD
+----------------------------------------------------------------------------
+	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
+	  port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> FB_ADR(2),
+			CS1					=> '1',
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_I,
+--			DATA_EN				=> DATA_EN_ACIA_I,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> KEYB_RxD,
+
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_KEYBDn,
+			TXDATA				=> AMKB_TX
+			--RTSn				=> -- Not used.
+		);                                              
+ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
+KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+	process(CLK2M, AMKB_RX, AMKB_REG)
+	begin
+		if rising_edge(CLK2M) then
+			IF AMKB_RX = '0' THEN
+				IF AMKB_REG < 16 THEN
+					AMKB_REG <= "00000";
+				ELSE
+					AMKB_REG <= AMKB_REG - 1;
+				END IF;
+			ELSE
+				IF AMKB_REG > 15 THEN
+					AMKB_REG <= "11111";
+				ELSE
+					AMKB_REG <= AMKB_REG + 1;
+				END IF;
+			END IF;
+		ELSE
+			AMKB_REG <= AMKB_REG;
+		end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- ACIA MIDI
+----------------------------------------------------------------------------
+	I_ACIA_MIDI: WF6850IP_TOP_SOC
+		port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> '0',
+			CS1					=> FB_ADR(2),
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_II,
+--			DATA_EN				=> DATA_EN_ACIA_II,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> MIDI_IN,
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_MIDIn,
+			TXDATA				=> MIDI_OUT
+			--RTSn				=> -- Not used.
+	    );                                              
+MIDI_TLR <= MIDI_OUT;
+MIDI_OLR <= MIDI_OUT;
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+----------------------------------------------------------------------------
+-- MFP
+----------------------------------------------------------------------------
+	I_MFP: WF68901IP_TOP_SOC
+		port map(  
+			-- System control:
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+			-- Asynchronous bus control:
+			DSn					=> not LDS,
+			CSn					=> not MFP_CS,
+			RWn					=> nFB_WR,
+ 			DTACKn				=> DTACK_OUT_MFPn,
+			-- Data and Adresses:
+			RS					=> FB_ADR(5 downto 1),
+			DATA_IN				=> FB_AD(23 downto 16),
+			DATA_OUT			=> DATA_OUT_MFP,
+--			DATA_EN				=> DATA_EN_MFP,
+            GPIP_IN(7)			=> not DMA_DRQ_Q,
+            GPIP_IN(6)			=> not RI,
+			GPIP_IN(5)			=> DINTn,
+			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(3)			=> DSP_INT,
+            GPIP_IN(2)			=> not CTS,
+            GPIP_IN(1)			=> not DCD,
+            GPIP_IN(0)			=> LP_BUSY,
+			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
+			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
+			-- Interrupt control:
+			IACKn				=> not MFP_INTACK,
+			IEIn				=> '0',
+			-- IEOn				=>, -- Not used.
+			IRQn				=> nMFP_INT,
+			-- Timers and timer control:
+			XTAL1				=> CLK2M4576,
+            TAI					=> '0',
+			TBI				    => nBLANK,
+            -- TAO				=>,
+			-- TBO				=>,
+            -- TCO				=>,
+			TDO					=> TDO,
+			-- Serial I/O control:
+			RC					=> TDO,
+			TC					=> TDO,
+			SI					=> RxD, 
+			SO					=> TxD
+			-- SO_EN			=> MFP_SO_EN
+			-- DMA control:
+			-- RRn				=>,
+			-- TRn				=>
+		);
+
+MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
+MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
+LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
+FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
+DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
+         '0' when FDINT = '1' else
+         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
+-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
+	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
+	begin
+		if nRSTO = '0' THEN
+			IRQ_ACIAn <= '1';
+		elsif rising_edge(MAIN_CLK) then
+				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
+			else
+				IRQ_ACIAn <= IRQ_ACIAn;
+			end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- Sound
+----------------------------------------------------------------------------
+ 	I_SOUND: WF2149IP_TOP_SOC
+		port map(
+			SYS_CLK				=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			WAV_CLK				=> CLK2M,
+			SELn				=> '1',
+
+			BDIR				=> SNDIR_I,
+			BC2					=> '1',
+			BC1					=> SNDCS_I,
+
+			A9n					=> '0',
+			A8					=> '1',
+			DA_IN				=> FB_AD(31 downto 24),
+			DA_OUT 				=> DA_OUT_X,
+
+			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
+			IO_A_OUT(7)			=> nnIDE_RES,
+            IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> LP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+--			IO_A_OUT(2)			=> FDD_D1SEL,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> nSDSEL,
+			-- IO_A_EN			=>, -- Not required.
+			IO_B_IN				=> LP_D,
+			IO_B_OUT			=> LP_D_X,
+ --			IO_B_EN				=> IO_B_EN,
+
+			OUT_A				=> YM_QA,
+			OUT_B				=> YM_QB,
+			OUT_C				=> YM_QC
+		);
+
+SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
+SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
+SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
+FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
+LP_DIR <= LP_DIR_X;
+
+END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
new file mode 100644
index 0000000..a339eda
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
@@ -0,0 +1,971 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:20 2009
+
+library work;
+use work.FalconIO_SDCard_IDE_CF_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+--  Entity Declaration
+
+
+--  Entity Declaration
+
+ENTITY FalconIO_SDCard_IDE_CF IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		CLK2M : IN STD_LOGIC;
+		CLK500k : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		LP_BUSY : IN STD_LOGIC;
+		nACSI_DRQ : IN STD_LOGIC;
+		nACSI_INT : IN STD_LOGIC;
+		nSCSI_DRQ : IN STD_LOGIC;
+		nSCSI_MSG : IN STD_LOGIC;
+		MIDI_IN : IN STD_LOGIC;
+		RxD : IN STD_LOGIC;
+		CTS : IN STD_LOGIC;
+		RI : IN STD_LOGIC;
+		DCD : IN STD_LOGIC;
+		AMKB_RX : IN STD_LOGIC;
+		PIC_AMKB_RX : IN STD_LOGIC;
+		IDE_RDY : IN STD_LOGIC;
+		IDE_INT : IN STD_LOGIC;
+		WP_CS_CARD : IN STD_LOGIC;
+		nINDEX : IN STD_LOGIC;
+		TRACK00 : IN STD_LOGIC;
+		nRD_DATA : IN STD_LOGIC;
+		nDCHG : IN STD_LOGIC;
+		SD_DATA0 : IN STD_LOGIC;
+		SD_DATA1 : IN STD_LOGIC;
+		SD_DATA2 : IN STD_LOGIC;
+		SD_CARD_DEDECT : IN STD_LOGIC;
+		SD_WP : IN STD_LOGIC;
+		nDACK0 : IN STD_LOGIC;
+		nFB_WR : INOUT STD_LOGIC;
+		WP_CF_CARD : IN STD_LOGIC;
+		nWP : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nRSTO : IN STD_LOGIC;
+		HD_DD : IN STD_LOGIC;
+		nSCSI_C_D : IN STD_LOGIC;
+		nSCSI_I_O : IN STD_LOGIC;
+		CLK2M4576 : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		VSYNC : IN STD_LOGIC;
+		HSYNC : IN STD_LOGIC;
+		DSP_INT : IN STD_LOGIC;
+		nBLANK : IN STD_LOGIC;
+		FDC_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
+		nIDE_CS1 : OUT STD_LOGIC;
+		nIDE_CS0 : OUT STD_LOGIC;
+		LP_STR : OUT STD_LOGIC;
+		LP_DIR : OUT STD_LOGIC;
+		nACSI_ACK : OUT STD_LOGIC;
+		nACSI_RESET : OUT STD_LOGIC;
+		nACSI_CS : OUT STD_LOGIC;
+		ACSI_DIR : OUT STD_LOGIC;
+		ACSI_A1 : OUT STD_LOGIC;
+		nSCSI_ACK : OUT STD_LOGIC;
+		nSCSI_ATN : OUT STD_LOGIC;
+		SCSI_DIR : OUT STD_LOGIC;
+		SD_CLK : OUT STD_LOGIC;
+		YM_QA : OUT STD_LOGIC;
+		YM_QC : OUT STD_LOGIC;
+		YM_QB : OUT STD_LOGIC;
+		nSDSEL : OUT STD_LOGIC;
+		STEP : OUT STD_LOGIC;
+		MOT_ON : OUT STD_LOGIC;
+		nRP_LDS : OUT STD_LOGIC;
+		nRP_UDS : OUT STD_LOGIC;
+		nROM4 : OUT STD_LOGIC;
+		nROM3 : OUT STD_LOGIC;
+		nCF_CS1 : OUT STD_LOGIC;
+		nCF_CS0 : OUT STD_LOGIC;
+		nIDE_RD : INOUT STD_LOGIC;
+		nIDE_WR : INOUT STD_LOGIC;
+		AMKB_TX : OUT STD_LOGIC;
+		IDE_RES : OUT STD_LOGIC;
+		DTR : OUT STD_LOGIC;
+		RTS : OUT STD_LOGIC;
+		TxD : OUT STD_LOGIC;
+		MIDI_OLR : OUT STD_LOGIC;
+		MIDI_TLR : OUT STD_LOGIC;
+		nDREQ0 : OUT STD_LOGIC;
+		DSA_D : OUT STD_LOGIC;
+		nMFP_INT : OUT STD_LOGIC;
+		FALCON_IO_TA : OUT STD_LOGIC;
+		STEP_DIR : OUT STD_LOGIC;
+		WR_DATA : OUT STD_LOGIC;
+		WR_GATE : OUT STD_LOGIC;
+		DMA_DRQ : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_PAR : INOUT STD_LOGIC;
+		nSCSI_SEL : INOUT STD_LOGIC;
+		nSCSI_BUSY : INOUT STD_LOGIC;
+		nSCSI_RST : INOUT STD_LOGIC;
+		SD_CD_DATA3 : INOUT STD_LOGIC;
+		SD_CDM_D1 : INOUT STD_LOGIC
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END FalconIO_SDCard_IDE_CF;
+
+
+--  Architecture Body
+
+ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
+-- system
+signal SYS_CLK					: STD_LOGIC;
+signal RESETn					: STD_LOGIC;
+signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
+signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
+signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
+signal LONG						: STD_LOGIC;	-- WENN  -> 1
+-- KEYBOARD MIDI
+signal ACIA_CS_I				: STD_LOGIC;
+signal IRQ_KEYBDn				: STD_LOGIC;
+signal IRQ_MIDIn				: STD_LOGIC;
+signal KEYB_RxD					: STD_LOGIC;
+signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal MIDI_OUT					: STD_LOGIC;
+signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
+signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
+-- MFP
+signal MFP_CS					: STD_LOGIC;
+signal MFP_INTACK				: STD_LOGIC;
+signal LDS						: STD_LOGIC;
+signal DTACK_OUT_MFPn			: STD_LOGIC;
+signal IRQ_ACIAn				: STD_LOGIC;
+signal DINTn					: STD_LOGIC;
+signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
+signal TDO						: STD_LOGIC;
+-- SOUND
+signal SNDCS					: STD_LOGIC;
+signal SNDCS_I					: STD_LOGIC;
+signal SNDIR_I					: STD_LOGIC;
+signal LP_DIR_X					: STD_LOGIC;
+signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+-- DIV
+signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
+signal ROM_CS					: STD_LOGIC;
+-- DMA UND FLOPPY
+signal DMA_DATEN_CS				: STD_LOGIC;
+signal DMA_MODUS_CS				: STD_LOGIC;
+signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
+signal WDC_BSL_CS				: STD_LOGIC;
+signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal HD_DD_OUT				: STD_LOGIC;
+signal FDCS_In					: STD_LOGIC;
+signal CA0						: STD_LOGIC;
+signal CA1						: STD_LOGIC;
+signal CA2						: STD_LOGIC;
+signal FDINT					: STD_LOGIC;
+signal FDRQ						: STD_LOGIC;
+signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_TOP_CS				: STD_LOGIC;
+signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_HIGH_CS				: STD_LOGIC;
+signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_MID_CS				: STD_LOGIC;
+signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_LOW_CS				: STD_LOGIC;
+signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_DIRM_CS				: STD_LOGIC;
+signal DMA_ADR_CS				: STD_LOGIC;
+signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
+signal DMA_DIR_OLD				: STD_LOGIC;
+signal DMA_BYT_CNT_CS			: STD_LOGIC;
+signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
+signal CLR_FIFO					: STD_LOGIC;
+signal DMA_DRQ_I				: STD_LOGIC;
+signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
+signal DMA_DRQQ					: STD_LOGIC;
+signal DMA_DRQ_Q				: STD_LOGIC;
+signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
+signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal RDF_RDE					: STD_LOGIC;
+signal RDF_WRE					: STD_LOGIC;
+signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal WRF_RDE					: STD_LOGIC;
+signal WRF_WRE					: STD_LOGIC;
+signal nFDC_WR					: STD_LOGIC;
+type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
+signal FCF_STATE				: FCF_STATES;
+signal NEXT_FCF_STATE			: FCF_STATES;
+signal DMA_REQ					: STD_LOGIC;
+signal FDC_CS					: STD_LOGIC;
+signal FCF_CS					: STD_LOGIC;
+signal FCF_APH					: STD_LOGIC;
+signal DMA_AZ_CS				: STD_LOGIC;
+signal DMA_ACTIV				: STD_LOGIC;
+signal DMA_ACTIV_NEW			: STD_LOGIC;
+signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
+-- SCSI
+signal SCSI_CS					: STD_LOGIC;
+signal SCSI_CSn					: STD_LOGIC;
+signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
+signal nSCSI_DACK				: STD_LOGIC;
+signal SCSI_DRQ					: STD_LOGIC;
+signal SCSI_INT					: STD_LOGIC;
+signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
+signal DB_EN					: STD_LOGIC;
+signal DBP_OUTn					: STD_LOGIC;
+signal DBP_EN					: STD_LOGIC;
+signal RST_OUTn					: STD_LOGIC;
+signal RST_EN					: STD_LOGIC;
+signal BSY_OUTn					: STD_LOGIC;
+signal BSY_EN					: STD_LOGIC;
+signal SEL_OUTn					: STD_LOGIC;
+signal SEL_EN					: STD_LOGIC;
+-- IDE
+signal nnIDE_RES				: STD_LOGIC;
+signal IDE_CF_CS				: STD_LOGIC;
+signal IDE_CF_TA				: STD_LOGIC;
+signal NEXT_nIDE_RD				: STD_LOGIC;
+signal NEXT_nIDE_WR				: STD_LOGIC;
+type CMD_STATES is(	IDLE, T1, T6, T7);
+signal CMD_STATE				: CMD_STATES;
+signal NEXT_CMD_STATE			: CMD_STATES;
+
+	
+BEGIN
+LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
+BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
+FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
+FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
+
+FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
+           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
+nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nDREQ0 <= '0';
+----------------------------------------------------------------------------
+-- SD
+----------------------------------------------------------------------------
+SD_CLK <= 'Z';
+SD_CD_DATA3 <= 'Z';
+SD_CDM_D1 <= 'Z';
+----------------------------------------------------------------------------
+-- IDE
+----------------------------------------------------------------------------
+CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
+	begin
+		if nRSTO = '0' then
+			CMD_STATE <= IDLE;
+		elsif rising_edge(MAIN_CLK) then
+				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
+				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
+				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
+			else
+				CMD_STATE <= CMD_STATE; 		-- halten
+				nIDE_RD   <= nIDE_RD;			-- halten
+				nIDE_WR   <= nIDE_WR;			-- halten
+			end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
+	begin
+		case CMD_STATE is
+			when IDLE =>
+				IDE_CF_TA <= '0';
+				if  IDE_CF_CS = '1' then
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T1;
+				else
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= IDLE; 		 
+				end if;
+			when T1 =>
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= not nFB_WR;
+				NEXT_nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T6;
+			when T6 =>
+				IF IDE_RDY = '1' then
+					IDE_CF_TA <= '1';
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= T7;
+				else
+					IDE_CF_TA <= '0';
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T6;
+				end if;
+			when T7 => 
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= '1';
+				NEXT_nIDE_WR <= '1';
+				NEXT_CMD_STATE <= IDLE;
+		end case;
+	end process CMD_DECODER;
+	
+IDE_RES <= not nnIDE_RES and nRSTO;
+IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
+nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
+nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
+nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
+nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- ACSI, SCSI UND FLOPPY WD1772 
+-------------------------------------------------------------------------------------------------------------------------------------------
+-- daten read fifo
+	RDF: dcfifo0
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> RDF_DIN,
+			rdclk				=> MAIN_CLK,
+			rdreq				=> RDF_RDE,
+			wrclk				=> FDC_CLK,
+			wrreq				=> RDF_WRE,
+			q					=> RDF_DOUT,
+			wrusedw				=> RDF_AZ
+	);
+FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
+FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
+RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
+FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
+RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
+-- daten write fifo
+	WRF: dcfifo1
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
+			rdclk				=> FDC_CLK,
+			rdreq				=> WRF_RDE,
+			wrclk				=> MAIN_CLK,
+			wrreq				=> WRF_WRE,
+			q					=> WRF_DOUT,
+			rdusedw				=> WRF_AZ
+	);
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
+FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
+	begin
+		if nRSTO = '0' THEN
+			WRF_WRE <= '0';
+		elsif rising_edge(MAIN_CLK) then
+				IF FCF_APH = '1' and nFB_WR = '0' then
+					WRF_WRE <= '1';
+				else
+					WRF_WRE <= '0';
+				end if;
+			else
+				WRF_WRE <= WRF_WRE;
+			end if;
+	END PROCESS;
+ 
+FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
+	begin
+		if nRSTO = '0' then
+			FCF_STATE <= FCF_IDLE;
+			DMA_ACTIV <= '0';
+		elsif rising_edge(FDC_CLK) then
+				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
+				DMA_ACTIV <= DMA_ACTIV_NEW;
+			else
+				FCF_STATE <= FCF_STATE; 					-- halten
+				DMA_ACTIV <= DMA_ACTIV;
+			end if;
+	end process FCF_REG;
+
+FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
+	begin
+		if nRSTO = '0' then
+			FDC_OUT <= x"00";
+		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
+				FDC_OUT <= CD_OUT_FDC; 						-- set
+			else
+				FDC_OUT <= FDC_OUT; 						-- halten
+			end if;
+	end process FDC_REG;
+
+DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
+FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
+SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
+
+	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
+	begin
+		case FCF_STATE is
+			when FCF_IDLE =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
+					DMA_ACTIV_NEW <= DMA_REQ;
+					NEXT_FCF_STATE <= FCF_T0;
+				else
+					DMA_ACTIV_NEW <= '0';
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+			when FCF_T0 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= DMA_REQ;
+				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
+				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
+					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
+				else
+					NEXT_FCF_STATE <= FCF_T1;
+				end if;
+			when FCF_T1 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T2;
+			when FCF_T2 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T3;
+			when FCF_T3 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T6;
+			when FCF_T6 =>
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
+				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
+				NEXT_FCF_STATE <= FCF_T7;
+			when FCF_T7 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= '0';
+				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
+					NEXT_FCF_STATE <= FCF_T7;
+				else
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+		end case;
+	end process FCF_DECODER;
+
+	I_FDC: WF1772IP_TOP_SOC
+		port map(
+            CLK					=> FDC_CLK,
+			RESETn				=> nRSTO,
+			CSn					=> FDCS_In,
+			RWn					=> nFDC_WR,
+			A1					=> CA2,
+			A0					=> CA1,
+			DATA_IN				=> CD_IN_FDC,
+			DATA_OUT			=> CD_OUT_FDC,
+--			DATA_EN				=> CD_EN_FDC,
+			RDn					=> nRD_DATA,
+			TR00n				=> TRACK00,
+			IPn					=> nINDEX,
+			WPRTn				=> nWP,
+			DDEn				=> '0', -- Fixed to MFM.
+			HDTYPE				=> HD_DD_OUT,  
+			MO					=> MOT_ON,
+			WG					=> WR_GATE,
+			WD					=> WR_DATA,
+			STEP				=> STEP,
+			DIRC				=> STEP_DIR,
+			DRQ					=> DMA_DRQ_I,
+			INTRQ				=> FDINT 
+		);
+DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
+DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
+WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
+HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
+nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
+CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
+CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
+CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
+FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
+                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
+      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
+--- WDC BSL REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			WDC_BSL <= "00";
+		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
+			else
+				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
+			end if;
+		end if;
+	END PROCESS;
+--- DMA MODUS REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			DMA_MODUS <= x"0000";
+		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
+			else
+				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
+			end if;
+			IF FB_B1 = '1' THEN
+				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
+			else
+				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
+			end if;
+		else
+			DMA_MODUS <= DMA_MODUS;
+		end if;
+	END PROCESS;
+-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
+	begin
+		if nRSTO = '0' or CLR_FIFO = '1' THEN
+			DMA_BYT_CNT <= x"00000000";													 
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
+				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
+				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
+				DMA_BYT_CNT(8 downto 0) <= "000000000";
+			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
+					DMA_BYT_CNT <= FB_AD;
+				else
+					DMA_BYT_CNT <= DMA_BYT_CNT;
+				end if;
+	END PROCESS;
+--------------------------------------------------------------------
+FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+DMA_STATUS(0) <= '1';													-- DMA OK
+DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
+DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
+DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
+            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
+DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
+	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DRQ_REG <= "00";
+		elsif rising_edge(FDC_CLK) then
+				DMA_DRQ_REG(0) <= DMA_DRQQ;
+				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
+			else
+				DMA_DRQ_REG <= DMA_DRQ_REG;
+			end if;
+	END PROCESS;
+-- DMA ADRESSE ------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_TOP <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_TOP <= FB_AD(31 downto 24);
+			else 
+				DMA_TOP <= DMA_TOP;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_HIGH <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_HIGH <= FB_AD(23 downto 16);
+			else
+				DMA_HIGH <= DMA_HIGH;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
+	begin
+		DMA_MID <= DMA_MID;
+		if nRSTO = '0' THEN
+			DMA_MID <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_MID_CS = '1' then
+					DMA_MID <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_MID <= FB_AD(15 downto 8);
+					end if;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
+	begin
+		DMA_LOW <= DMA_LOW;
+		if nRSTO = '0' THEN
+			DMA_LOW <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_LOW_CS = '1'then
+					DMA_LOW <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_LOW <= FB_AD(7 downto 0);
+					end if;
+			end if;
+	END PROCESS;
+--------------------------------------------------------------------------------------------
+DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
+DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
+DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
+DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
+FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+-- DIRECTZUGRIFF
+DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
+DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
+DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
+FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+-- DMA RW TOGGLE ------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DIR_OLD <= '0';
+		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
+				DMA_DIR_OLD <= DMA_MODUS(8);
+			else
+				DMA_DIR_OLD <= DMA_DIR_OLD;
+			end if;
+	END PROCESS;
+CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
+-- SCSI ----------------------------------------------------------------------------------
+    I_SCSI: WF5380_TOP_SOC
+        port map(
+            CLK					=> FDC_CLK,
+            RESETn				=> nRSTO,
+			ADR			        => CA2 & CA1 & CA0,
+			DATA_IN		        => CD_IN_FDC,	
+			DATA_OUT			=> SCSI_DOUT,
+			--DATA_EN			: out bit;
+            -- Bus and DMA controls:
+			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			RDn		            => (not nFDC_WR) or (not SCSI_CS),
+			WRn	                =>      nFDC_WR  or (not SCSI_CS),
+            EOPn                => '1',
+			DACKn	            => nSCSI_DACK,
+			DRQ		            => SCSI_DRQ,
+			INT		            => SCSI_INT,
+--            READY                	=> 
+            -- SCSI bus:
+            DB_INn		        => SCSI_D,
+            DB_OUTn		        => DB_OUTn,
+            DB_EN               => DB_EN,
+            DBP_INn		        => SCSI_PAR,
+            DBP_OUTn	        => DBP_OUTn,
+            DBP_EN              => DBP_EN,				-- wenn 1 dann output
+            RST_INn             => nSCSI_RST,
+            RST_OUTn            => RST_OUTn,
+            RST_EN              => RST_EN,
+            BSY_INn             => nSCSI_BUSY,
+            BSY_OUTn            => BSY_OUTn,
+            BSY_EN              => BSY_EN,
+            SEL_INn             => nSCSI_SEL,
+            SEL_OUTn            => SEL_OUTn,
+            SEL_EN              => SEL_EN,
+            ACK_INn             => '1',
+            ACK_OUTn            => nSCSI_ACK,
+--            ACK_EN              => ACK_EN,
+            ATN_INn             => '1',
+            ATN_OUTn            => nSCSI_ATN,
+--            ATN_EN              => ATN_EN,
+            REQ_INn             => nSCSI_DRQ,
+--            REQ_OUTn            => REQ_OUTn,
+--            REQ_EN              => REQ_EN,
+            IOn_IN              => nSCSI_I_O,
+--            IOn_OUT             => IOn_OUT,
+--            IO_EN               => IO_EN,
+            CDn_IN              => nSCSI_C_D,
+--            CDn_OUT             => CDn_OUT,
+--            CD_EN               => CD_EN,
+            MSG_INn             => nSCSI_MSG
+--            MSG_OUTn            => MSG_OUTn,
+--            MSG_EN              => MSG_EN
+        );              
+-- SCSI ACSI ---------------------------------------------------------------
+SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
+nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+ACSI_DIR <= '0';
+ACSI_D <= "ZZZZZZZZ";
+nACSI_CS <= '1';
+ACSI_A1 <= CA1;
+nACSI_RESET <= nRSTO;
+nACSI_ACK <= '1';
+----------------------------------------------------------------------------
+-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
+----------------------------------------------------------------------------
+ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
+nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
+nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
+----------------------------------------------------------------------------
+-- ACIA KEYBOARD
+----------------------------------------------------------------------------
+	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
+	  port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> FB_ADR(2),
+			CS1					=> '1',
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_I,
+--			DATA_EN				=> DATA_EN_ACIA_I,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> KEYB_RxD,
+
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_KEYBDn,
+			TXDATA				=> AMKB_TX
+			--RTSn				=> -- Not used.
+		);                                              
+ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
+KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+	process(CLK2M, AMKB_RX, AMKB_REG)
+	begin
+		if rising_edge(CLK2M) then
+			IF AMKB_RX = '0' THEN
+				IF AMKB_REG < 16 THEN
+					AMKB_REG <= "00000";
+				ELSE
+					AMKB_REG <= AMKB_REG - 1;
+				END IF;
+			ELSE
+				IF AMKB_REG > 15 THEN
+					AMKB_REG <= "11111";
+				ELSE
+					AMKB_REG <= AMKB_REG + 1;
+				END IF;
+			END IF;
+		ELSE
+			AMKB_REG <= AMKB_REG;
+		end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- ACIA MIDI
+----------------------------------------------------------------------------
+	I_ACIA_MIDI: WF6850IP_TOP_SOC
+		port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> '0',
+			CS1					=> FB_ADR(2),
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_II,
+--			DATA_EN				=> DATA_EN_ACIA_II,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> MIDI_IN,
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_MIDIn,
+			TXDATA				=> MIDI_OUT
+			--RTSn				=> -- Not used.
+	    );                                              
+MIDI_TLR <= MIDI_OUT;
+MIDI_OLR <= MIDI_OUT;
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+----------------------------------------------------------------------------
+-- MFP
+----------------------------------------------------------------------------
+	I_MFP: WF68901IP_TOP_SOC
+		port map(  
+			-- System control:
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+			-- Asynchronous bus control:
+			DSn					=> not LDS,
+			CSn					=> not MFP_CS,
+			RWn					=> nFB_WR,
+ 			DTACKn				=> DTACK_OUT_MFPn,
+			-- Data and Adresses:
+			RS					=> FB_ADR(5 downto 1),
+			DATA_IN				=> FB_AD(23 downto 16),
+			DATA_OUT			=> DATA_OUT_MFP,
+--			DATA_EN				=> DATA_EN_MFP,
+            GPIP_IN(7)			=> not DMA_DRQ_Q,
+            GPIP_IN(6)			=> not RI,
+			GPIP_IN(5)			=> DINTn,
+			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(3)			=> DSP_INT,
+            GPIP_IN(2)			=> not CTS,
+            GPIP_IN(1)			=> not DCD,
+            GPIP_IN(0)			=> LP_BUSY,
+			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
+			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
+			-- Interrupt control:
+			IACKn				=> not MFP_INTACK,
+			IEIn				=> '0',
+			-- IEOn				=>, -- Not used.
+			IRQn				=> nMFP_INT,
+			-- Timers and timer control:
+			XTAL1				=> CLK2M4576,
+            TAI					=> '0',
+			TBI				    => nBLANK,
+            -- TAO				=>,
+			-- TBO				=>,
+            -- TCO				=>,
+			TDO					=> TDO,
+			-- Serial I/O control:
+			RC					=> TDO,
+			TC					=> TDO,
+			SI					=> RxD, 
+			SO					=> TxD
+			-- SO_EN			=> MFP_SO_EN
+			-- DMA control:
+			-- RRn				=>,
+			-- TRn				=>
+		);
+
+MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
+MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
+LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
+FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
+DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
+         '0' when FDINT = '1' else
+         '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
+-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
+	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
+	begin
+		if nRSTO = '0' THEN
+			IRQ_ACIAn <= '1';
+		elsif rising_edge(MAIN_CLK) then
+				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
+			else
+				IRQ_ACIAn <= IRQ_ACIAn;
+			end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- Sound
+----------------------------------------------------------------------------
+ 	I_SOUND: WF2149IP_TOP_SOC
+		port map(
+			SYS_CLK				=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			WAV_CLK				=> CLK2M,
+			SELn				=> '1',
+
+			BDIR				=> SNDIR_I,
+			BC2					=> '1',
+			BC1					=> SNDCS_I,
+
+			A9n					=> '0',
+			A8					=> '1',
+			DA_IN				=> FB_AD(31 downto 24),
+			DA_OUT 				=> DA_OUT_X,
+
+			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
+			IO_A_OUT(7)			=> nnIDE_RES,
+            IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> LP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+--			IO_A_OUT(2)			=> FDD_D1SEL,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> nSDSEL,
+			-- IO_A_EN			=>, -- Not required.
+			IO_B_IN				=> LP_D,
+			IO_B_OUT			=> LP_D_X,
+ --			IO_B_EN				=> IO_B_EN,
+
+			OUT_A				=> YM_QA,
+			OUT_B				=> YM_QB,
+			OUT_C				=> YM_QC
+		);
+
+SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
+SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
+SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
+FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
+LP_DIR <= LP_DIR_X;
+
+END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
new file mode 100644
index 0000000..edef447
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
@@ -0,0 +1,406 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Atari Coldfire IP Core				                          ----
+----                                                              ----
+---- This file is part of the Atari Coldfire project.             ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 1.0 Initial Release, 20090925.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package FalconIO_SDCard_IDE_CF_PKG is
+	component WF25915IP_TOP_V1_SOC -- GLUE.
+		port (
+		    -- Clock system:
+			GL_CLK		: in std_logic; -- Originally 8MHz.
+			GL_CLK_016	: in std_logic; -- One sixteenth of GL_CLK.
+			
+            -- Core address select:
+            GL_ROMSEL_FC_E0n    : in std_logic;
+            EN_RAM_14MB         : in std_logic;
+			-- Adress decoder outputs:
+			GL_ROM_6n	: out std_logic;	-- STE.
+			GL_ROM_5n	: out std_logic;	-- STE.
+			GL_ROM_4n	: out std_logic;	-- ST.
+			GL_ROM_3n	: out std_logic;	-- ST.
+			GL_ROM_2n	: out std_logic;
+			GL_ROM_1n	: out std_logic;
+			GL_ROM_0n	: out std_logic;
+			
+			GL_ACIACS	: out std_logic;
+			GL_MFPCSn	: out std_logic;
+			GL_SNDCSn	: out std_logic;
+			GL_FCSn		: out std_logic;
+
+			GL_STE_SNDCS	: out std_logic; 	-- STE: Sound chip select.
+			GL_STE_SNDIR	: out std_logic; 	-- STE: Data flow direction control.
+
+			GL_STE_RTCCSn	: out std_logic; 	--STE only.
+			GL_STE_RTC_WRn	: out std_logic; 	--STE only.
+			GL_STE_RTC_RDn	: out std_logic;	--STE only.
+
+			-- 6800 peripheral control, 
+			GL_VPAn			: out std_logic;
+			GL_VMAn 		: in std_logic;
+			
+			GL_DMA_SYNC		: in std_logic;
+			GL_DEVn			: out std_logic;
+			GL_RAMn			: out std_logic;
+			GL_DMAn			: out std_logic;
+			
+			-- Interrupt system:
+			-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
+			GL_AVECn		: out std_logic;
+			GL_STE_FDINT	: in std_logic; 	-- Floppy disk interrupt; STE only.
+			GL_STE_HDINTn	: in std_logic; 	-- Hard disk interrupt; STE only.
+			GL_MFPINTn		: in std_logic; 	-- ST.
+			GL_STE_EINT3n	: in std_logic; 	--STE only.
+			GL_STE_EINT5n	: in std_logic; 	--STE only.
+			GL_STE_EINT7n	: in std_logic; 	--STE only.
+			GL_STE_DINTn	: out std_logic; 	-- Disk interrupt (floppy or hard disk); STE only.
+			GL_IACKn		: out std_logic; 	-- ST.
+			GL_STE_IPL2n	: out std_logic; 	--STE only.
+			GL_STE_IPL1n	: out std_logic; 	--STE only.
+			GL_STE_IPL0n	: out std_logic; 	--STE only.
+			
+			-- Video timing:
+			GL_BLANKn		: out std_logic;
+			GL_DE			: out std_logic;
+			GL_MULTISYNC	: in std_logic_vector(3 downto 2);
+            GL_VIDEO_HIMODE : out std_logic;
+			GL_HSYNC_INn	: in std_logic;
+			GL_HSYNC_OUTn	: out std_logic;
+			GL_VSYNC_INn	: in std_logic;
+			GL_VSYNC_OUTn	: out std_logic;
+			GL_SYNC_OUT_EN	: out std_logic;
+			
+			-- Bus arstd_logicration control:
+			GL_RDY_INn		: in std_logic;
+			GL_RDY_OUTn		: out std_logic;
+			GL_BRn			: out std_logic;
+			GL_BGIn			: in std_logic;
+			GL_BGOn			: out std_logic;
+			GL_BGACK_INn	: in std_logic;
+			GL_BGACK_OUTn	: out std_logic;
+
+			-- Adress and data bus:
+			GL_ADDRESS		: in std_logic_vector(23 downto 1);
+			-- ST: put the data bus to 1 downto 0. 
+			-- STE: put the data out bus to 15 downto 0. 
+			GL_DATA_IN		: in std_logic_vector(7 downto 0);
+			GL_DATA_OUT		: out std_logic_vector(15 downto 0);
+			GL_DATA_EN		: out std_logic;
+			
+			-- Asynchronous bus control:
+			GL_RWn_IN		: in std_logic;
+			GL_RWn_OUT		: out std_logic;
+			GL_AS_INn		: in std_logic;
+			GL_AS_OUTn		: out std_logic;
+			GL_UDS_INn		: in std_logic;
+			GL_UDS_OUTn		: out std_logic;
+			GL_LDS_INn		: in std_logic;
+			GL_LDS_OUTn		: out std_logic;
+			GL_DTACK_INn	: in std_logic;
+			GL_DTACK_OUTn	: out std_logic;
+			GL_CTRL_EN		: out std_logic;
+			
+			-- System control:
+			GL_RESETn		: in std_logic;
+			GL_BERRn		: out std_logic;
+			
+			-- Processor function codes:
+			GL_FC	: in std_logic_vector(2 downto 0);
+
+			-- STE enhancements:
+			GL_STE_FDDS		: out std_logic; 		-- Floppy type select (HD or DD).
+			GL_STE_FCCLK	: out std_logic; 		-- Floppy controller clock select.
+			GL_STE_JOY_RHn	: out std_logic; 		-- Read only FF9202 high byte.
+			GL_STE_JOY_RLn	: out std_logic; 		-- Read only FF9202 low byte.
+			GL_STE_JOY_WL	: out std_logic; 		-- Write only FF9202 low byte.
+			GL_STE_JOY_WEn	: out std_logic; 		-- Write only FF9202 output enable.
+			GL_STE_BUTTONn	: out std_logic; 		-- Read only FF9000 low byte.		
+			GL_STE_PAD0Xn	: in std_logic; 		-- Counter input for the Paddle 0X.
+			GL_STE_PAD0Yn	: in std_logic; 		-- Counter input for the Paddle 0Y.
+			GL_STE_PAD1Xn	: in std_logic; 		-- Counter input for the Paddle 1X.
+			GL_STE_PAD1Yn	: in std_logic; 		-- Counter input for the Paddle 1Y.
+			GL_STE_PADRSTn	: out std_logic; 		-- Paddle monoflops reset.
+			GL_STE_PENn		: in std_logic; 		-- Input of the light pen.
+			GL_STE_SCCn		: out std_logic;	-- Select signal for the STE or TT SCC chip.
+			GL_STE_CPROGn	: out std_logic	-- Select signal for the STE's cache processor.
+			);
+	end component WF25915IP_TOP_V1_SOC;
+
+    component WF5380_TOP_SOC
+        port (
+            CLK			: in std_logic;
+            RESETn	    : in std_logic;
+            ADR			: in std_logic_vector(2 downto 0);
+            DATA_IN		: in std_logic_vector(7 downto 0);
+            DATA_OUT	: out std_logic_vector(7 downto 0);
+            DATA_EN		: out std_logic;
+            CSn			: in std_logic;
+            RDn		    : in std_logic;
+            WRn	        : in std_logic;
+            EOPn        : in std_logic;
+            DACKn	    : in std_logic;
+            DRQ		    : out std_logic;
+            INT		    : out std_logic;
+            READY       : out std_logic;
+            DB_INn		: in std_logic_vector(7 downto 0);
+            DB_OUTn		: out std_logic_vector(7 downto 0);
+            DB_EN       : out std_logic;
+            DBP_INn		: in std_logic;
+            DBP_OUTn	: out std_logic;
+            DBP_EN      : out std_logic;
+            RST_INn     : in std_logic;
+            RST_OUTn    : out std_logic;
+            RST_EN      : out std_logic;
+            BSY_INn     : in std_logic;
+            BSY_OUTn    : out std_logic;
+            BSY_EN      : out std_logic;
+            SEL_INn     : in std_logic;
+            SEL_OUTn    : out std_logic;
+            SEL_EN      : out std_logic;
+            ACK_INn     : in std_logic;
+            ACK_OUTn    : out std_logic;
+            ACK_EN      : out std_logic;
+            ATN_INn     : in std_logic;
+            ATN_OUTn    : out std_logic;
+            ATN_EN      : out std_logic;
+            REQ_INn     : in std_logic;
+            REQ_OUTn    : out std_logic;
+            REQ_EN      : out std_logic;
+            IOn_IN      : in std_logic;
+            IOn_OUT     : out std_logic;
+            IO_EN       : out std_logic;
+            CDn_IN      : in std_logic;
+            CDn_OUT     : out std_logic;
+            CD_EN       : out std_logic;
+            MSG_INn     : in std_logic;
+            MSG_OUTn    : out std_logic;
+            MSG_EN      : out std_logic
+        );
+    end component WF5380_TOP_SOC;
+
+	component WF1772IP_TOP_SOC -- FDC.
+		port (
+			CLK			: in std_logic; -- 16MHz clock!
+			RESETn		: in std_logic;
+			CSn			: in std_logic;
+			RWn			: in std_logic;
+			A1, A0		: in std_logic;
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out std_logic;
+			RDn			: in std_logic;
+			TR00n		: in std_logic;
+			IPn			: in std_logic;
+			WPRTn		: in std_logic;
+			DDEn		: in std_logic;
+			HDTYPE		: in std_logic; -- '0' = DD disks, '1' = HD disks.
+			MO			: out std_logic;
+			WG			: out std_logic;
+			WD			: out std_logic;
+			STEP		: out std_logic;
+			DIRC		: out std_logic;
+			DRQ			: out std_logic;
+			INTRQ		: out std_logic
+		);
+	end component WF1772IP_TOP_SOC;
+
+	component WF68901IP_TOP_SOC -- MFP.
+		port (  -- System control:
+				CLK			: in std_logic;
+				RESETn		: in std_logic;
+				
+				-- Asynchronous bus control:
+				DSn			: in std_logic;
+				CSn			: in std_logic;
+				RWn			: in std_logic;
+				DTACKn		: out std_logic;
+				
+				-- Data and Adresses:
+				RS			: in std_logic_vector(5 downto 1);
+				DATA_IN		: in std_logic_vector(7 downto 0);
+				DATA_OUT	: out std_logic_vector(7 downto 0);
+				DATA_EN		: out std_logic;
+				GPIP_IN		: in std_logic_vector(7 downto 0);
+				GPIP_OUT	: out std_logic_vector(7 downto 0);
+				GPIP_EN		: out std_logic_vector(7 downto 0);
+				
+				-- Interrupt control:
+				IACKn		: in std_logic;
+				IEIn		: in std_logic;
+				IEOn		: out std_logic;
+				IRQn		: out std_logic;
+				
+				-- Timers and timer control:
+				XTAL1		: in std_logic; -- Use an oszillator instead of a quartz.
+				TAI			: in std_logic;
+				TBI			: in std_logic;
+				TAO			: out std_logic;			
+				TBO			: out std_logic;			
+				TCO			: out std_logic;			
+				TDO			: out std_logic;			
+				
+				-- Serial I/O control:
+				RC			: in std_logic;
+				TC			: in std_logic;
+				SI			: in std_logic;
+				SO			: out std_logic;
+				SO_EN		: out std_logic;
+				
+				-- DMA control:
+				RRn			: out std_logic;
+				TRn			: out std_logic			
+		);
+	end component WF68901IP_TOP_SOC;
+
+	component WF2149IP_TOP_SOC -- Sound.
+		port(
+			
+			SYS_CLK		: in std_logic; -- Read the inforation in the header!
+			RESETn   	: in std_logic;
+
+			WAV_CLK		: in std_logic; -- Read the inforation in the header!
+			SELn		: in std_logic;
+			
+			BDIR		: in std_logic;
+			BC2, BC1	: in std_logic;
+
+			A9n, A8		: in std_logic;
+			DA_IN		: in std_logic_vector(7 downto 0);
+			DA_OUT		: out std_logic_vector(7 downto 0);
+			DA_EN		: out std_logic;
+			
+			IO_A_IN		: in std_logic_vector(7 downto 0);
+			IO_A_OUT	: out std_logic_vector(7 downto 0);
+			IO_A_EN		: out std_logic;
+			IO_B_IN		: in std_logic_vector(7 downto 0);
+			IO_B_OUT	: out std_logic_vector(7 downto 0);
+			IO_B_EN		: out std_logic;
+
+			OUT_A		: out std_logic; -- Analog (PWM) outputs.
+			OUT_B		: out std_logic;
+			OUT_C		: out std_logic
+		);
+	end component WF2149IP_TOP_SOC;
+
+	component WF6850IP_TOP_SOC -- ACIA.
+	  port (
+			CLK					: in std_logic;
+	        RESETn				: in std_logic;
+
+	        CS2n, CS1, CS0		: in std_logic;
+	        E		       		: in std_logic;   
+	        RWn              	: in std_logic;
+	        RS					: in std_logic;
+
+	        DATA_IN		        : in std_logic_vector(7 downto 0);   
+	        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+			DATA_EN				: out std_logic;
+
+	        TXCLK				: in std_logic;
+	        RXCLK				: in std_logic;
+	        RXDATA				: in std_logic;
+	        CTSn				: in std_logic;
+	        DCDn				: in std_logic;
+	        
+	        IRQn				: out std_logic;
+	        TXDATA				: out std_logic;   
+	        RTSn				: out std_logic
+	       );                                              
+	end component WF6850IP_TOP_SOC;
+
+	component WF_SD_CARD
+		port (
+			RESETn			: in std_logic;
+			CLK				: in std_logic;
+			ACSI_A1			: in std_logic;
+			ACSI_CSn		: in std_logic;
+			ACSI_ACKn		: in std_logic;
+			ACSI_INTn		: out std_logic;
+			ACSI_DRQn		: out std_logic;
+			ACSI_D_IN		: in std_logic_vector(7 downto 0);
+			ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+			ACSI_D_EN		: out std_logic;
+			MC_DO			: in std_logic;
+			MC_PIO_DMAn		: in std_logic;
+			MC_RWn			: in std_logic;
+			MC_CLR_CMD		: in std_logic;
+			MC_DONE			: out std_logic;
+			MC_GOT_CMD		: out std_logic;
+			MC_D_IN			: in std_logic_vector(7 downto 0);
+			MC_D_OUT		: out std_logic_vector(7 downto 0);
+			MC_D_EN			: out std_logic
+	      );
+	end component WF_SD_CARD;
+
+	component dcfifo0 
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrusedw			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 
+	);
+	end component dcfifo0;
+	
+	component dcfifo1
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdusedw			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 
+		);
+	end component;
+
+
+end FalconIO_SDCard_IDE_CF_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
new file mode 100644
index 0000000..4f42cf2
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
@@ -0,0 +1,406 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Atari Coldfire IP Core				                          ----
+----                                                              ----
+---- This file is part of the Atari Coldfire project.             ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 1.0 Initial Release, 20090925.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package FalconIO_SDCard_IDE_CF_PKG is
+	component WF25915IP_TOP_V1_SOC -- GLUE.
+		port (
+		    -- Clock system:
+			GL_CLK		: in std_logic; -- Originally 8MHz.
+			GL_CLK_016	: in std_logic; -- One sixteenth of GL_CLK.
+			
+            -- Core address select:
+            GL_ROMSEL_FC_E0n    : in std_logic;
+            EN_RAM_14MB         : in std_logic;
+			-- Adress decoder outputs:
+			GL_ROM_6n	: out std_logic;	-- STE.
+			GL_ROM_5n	: out std_logic;	-- STE.
+			GL_ROM_4n	: out std_logic;	-- ST.
+			GL_ROM_3n	: out std_logic;	-- ST.
+			GL_ROM_2n	: out std_logic;
+			GL_ROM_1n	: out std_logic;
+			GL_ROM_0n	: out std_logic;
+			
+			GL_ACIACS	: out std_logic;
+			GL_MFPCSn	: out std_logic;
+			GL_SNDCSn	: out std_logic;
+			GL_FCSn		: out std_logic;
+
+			GL_STE_SNDCS	: out std_logic; 	-- STE: Sound chip select.
+			GL_STE_SNDIR	: out std_logic; 	-- STE: Data flow direction control.
+
+			GL_STE_RTCCSn	: out std_logic; 	--STE only.
+			GL_STE_RTC_WRn	: out std_logic; 	--STE only.
+			GL_STE_RTC_RDn	: out std_logic;	--STE only.
+
+			-- 6800 peripheral control, 
+			GL_VPAn			: out std_logic;
+			GL_VMAn 		: in std_logic;
+			
+			GL_DMA_SYNC		: in std_logic;
+			GL_DEVn			: out std_logic;
+			GL_RAMn			: out std_logic;
+			GL_DMAn			: out std_logic;
+			
+			-- Interrupt system:
+			-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
+			GL_AVECn		: out std_logic;
+			GL_STE_FDINT	: in std_logic; 	-- Floppy disk interrupt; STE only.
+			GL_STE_HDINTn	: in std_logic; 	-- Hard disk interrupt; STE only.
+			GL_MFPINTn		: in std_logic; 	-- ST.
+			GL_STE_EINT3n	: in std_logic; 	--STE only.
+			GL_STE_EINT5n	: in std_logic; 	--STE only.
+			GL_STE_EINT7n	: in std_logic; 	--STE only.
+			GL_STE_DINTn	: out std_logic; 	-- Disk interrupt (floppy or hard disk); STE only.
+			GL_IACKn		: out std_logic; 	-- ST.
+			GL_STE_IPL2n	: out std_logic; 	--STE only.
+			GL_STE_IPL1n	: out std_logic; 	--STE only.
+			GL_STE_IPL0n	: out std_logic; 	--STE only.
+			
+			-- Video timing:
+			GL_BLANKn		: out std_logic;
+			GL_DE			: out std_logic;
+			GL_MULTISYNC	: in std_logic_vector(3 downto 2);
+            GL_VIDEO_HIMODE : out std_logic;
+			GL_HSYNC_INn	: in std_logic;
+			GL_HSYNC_OUTn	: out std_logic;
+			GL_VSYNC_INn	: in std_logic;
+			GL_VSYNC_OUTn	: out std_logic;
+			GL_SYNC_OUT_EN	: out std_logic;
+			
+			-- Bus arstd_logicration control:
+			GL_RDY_INn		: in std_logic;
+			GL_RDY_OUTn		: out std_logic;
+			GL_BRn			: out std_logic;
+			GL_BGIn			: in std_logic;
+			GL_BGOn			: out std_logic;
+			GL_BGACK_INn	: in std_logic;
+			GL_BGACK_OUTn	: out std_logic;
+
+			-- Adress and data bus:
+			GL_ADDRESS		: in std_logic_vector(23 downto 1);
+			-- ST: put the data bus to 1 downto 0. 
+			-- STE: put the data out bus to 15 downto 0. 
+			GL_DATA_IN		: in std_logic_vector(7 downto 0);
+			GL_DATA_OUT		: out std_logic_vector(15 downto 0);
+			GL_DATA_EN		: out std_logic;
+			
+			-- Asynchronous bus control:
+			GL_RWn_IN		: in std_logic;
+			GL_RWn_OUT		: out std_logic;
+			GL_AS_INn		: in std_logic;
+			GL_AS_OUTn		: out std_logic;
+			GL_UDS_INn		: in std_logic;
+			GL_UDS_OUTn		: out std_logic;
+			GL_LDS_INn		: in std_logic;
+			GL_LDS_OUTn		: out std_logic;
+			GL_DTACK_INn	: in std_logic;
+			GL_DTACK_OUTn	: out std_logic;
+			GL_CTRL_EN		: out std_logic;
+			
+			-- System control:
+			GL_RESETn		: in std_logic;
+			GL_BERRn		: out std_logic;
+			
+			-- Processor function codes:
+			GL_FC	: in std_logic_vector(2 downto 0);
+
+			-- STE enhancements:
+			GL_STE_FDDS		: out std_logic; 		-- Floppy type select (HD or DD).
+			GL_STE_FCCLK	: out std_logic; 		-- Floppy controller clock select.
+			GL_STE_JOY_RHn	: out std_logic; 		-- Read only FF9202 high byte.
+			GL_STE_JOY_RLn	: out std_logic; 		-- Read only FF9202 low byte.
+			GL_STE_JOY_WL	: out std_logic; 		-- Write only FF9202 low byte.
+			GL_STE_JOY_WEn	: out std_logic; 		-- Write only FF9202 output enable.
+			GL_STE_BUTTONn	: out std_logic; 		-- Read only FF9000 low byte.		
+			GL_STE_PAD0Xn	: in std_logic; 		-- Counter input for the Paddle 0X.
+			GL_STE_PAD0Yn	: in std_logic; 		-- Counter input for the Paddle 0Y.
+			GL_STE_PAD1Xn	: in std_logic; 		-- Counter input for the Paddle 1X.
+			GL_STE_PAD1Yn	: in std_logic; 		-- Counter input for the Paddle 1Y.
+			GL_STE_PADRSTn	: out std_logic; 		-- Paddle monoflops reset.
+			GL_STE_PENn		: in std_logic; 		-- Input of the light pen.
+			GL_STE_SCCn		: out std_logic;	-- Select signal for the STE or TT SCC chip.
+			GL_STE_CPROGn	: out std_logic	-- Select signal for the STE's cache processor.
+			);
+	end component WF25915IP_TOP_V1_SOC;
+
+    component WF5380_TOP_SOC
+        port (
+            CLK			: in std_logic;
+            RESETn	    : in std_logic;
+            ADR			: in std_logic_vector(2 downto 0);
+            DATA_IN		: in std_logic_vector(7 downto 0);
+            DATA_OUT	: out std_logic_vector(7 downto 0);
+            DATA_EN		: out std_logic;
+            CSn			: in std_logic;
+            RDn		    : in std_logic;
+            WRn	        : in std_logic;
+            EOPn        : in std_logic;
+            DACKn	    : in std_logic;
+            DRQ		    : out std_logic;
+            INT		    : out std_logic;
+            READY       : out std_logic;
+            DB_INn		: in std_logic_vector(7 downto 0);
+            DB_OUTn		: out std_logic_vector(7 downto 0);
+            DB_EN       : out std_logic;
+            DBP_INn		: in std_logic;
+            DBP_OUTn	: out std_logic;
+            DBP_EN      : out std_logic;
+            RST_INn     : in std_logic;
+            RST_OUTn    : out std_logic;
+            RST_EN      : out std_logic;
+            BSY_INn     : in std_logic;
+            BSY_OUTn    : out std_logic;
+            BSY_EN      : out std_logic;
+            SEL_INn     : in std_logic;
+            SEL_OUTn    : out std_logic;
+            SEL_EN      : out std_logic;
+            ACK_INn     : in std_logic;
+            ACK_OUTn    : out std_logic;
+            ACK_EN      : out std_logic;
+            ATN_INn     : in std_logic;
+            ATN_OUTn    : out std_logic;
+            ATN_EN      : out std_logic;
+            REQ_INn     : in std_logic;
+            REQ_OUTn    : out std_logic;
+            REQ_EN      : out std_logic;
+            IOn_IN      : in std_logic;
+            IOn_OUT     : out std_logic;
+            IO_EN       : out std_logic;
+            CDn_IN      : in std_logic;
+            CDn_OUT     : out std_logic;
+            CD_EN       : out std_logic;
+            MSG_INn     : in std_logic;
+            MSG_OUTn    : out std_logic;
+            MSG_EN      : out std_logic
+        );
+    end component WF5380_TOP_SOC;
+
+	component WF1772IP_TOP_SOC -- FDC.
+		port (
+			CLK			: in std_logic; -- 16MHz clock!
+			RESETn		: in std_logic;
+			CSn			: in std_logic;
+			RWn			: in std_logic;
+			A1, A0		: in std_logic;
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out std_logic;
+			RDn			: in std_logic;
+			TR00n		: in std_logic;
+			IPn			: in std_logic;
+			WPRTn		: in std_logic;
+			DDEn		: in std_logic;
+			HDTYPE		: in std_logic; -- '0' = DD disks, '1' = HD disks.
+			MO			: out std_logic;
+			WG			: out std_logic;
+			WD			: out std_logic;
+			STEP		: out std_logic;
+			DIRC		: out std_logic;
+			DRQ			: out std_logic;
+			INTRQ		: out std_logic
+		);
+	end component WF1772IP_TOP_SOC;
+
+	component WF68901IP_TOP_SOC -- MFP.
+		port (  -- System control:
+				CLK			: in std_logic;
+				RESETn		: in std_logic;
+				
+				-- Asynchronous bus control:
+				DSn			: in std_logic;
+				CSn			: in std_logic;
+				RWn			: in std_logic;
+				DTACKn		: out std_logic;
+				
+				-- Data and Adresses:
+				RS			: in std_logic_vector(5 downto 1);
+				DATA_IN		: in std_logic_vector(7 downto 0);
+				DATA_OUT	: out std_logic_vector(7 downto 0);
+				DATA_EN		: out std_logic;
+				GPIP_IN		: in std_logic_vector(7 downto 0);
+				GPIP_OUT	: out std_logic_vector(7 downto 0);
+				GPIP_EN		: out std_logic_vector(7 downto 0);
+				
+				-- Interrupt control:
+				IACKn		: in std_logic;
+				IEIn		: in std_logic;
+				IEOn		: out std_logic;
+				IRQn		: out std_logic;
+				
+				-- Timers and timer control:
+				XTAL1		: in std_logic; -- Use an oszillator instead of a quartz.
+				TAI			: in std_logic;
+				TBI			: in std_logic;
+				TAO			: out std_logic;			
+				TBO			: out std_logic;			
+				TCO			: out std_logic;			
+				TDO			: out std_logic;			
+				
+				-- Serial I/O control:
+				RC			: in std_logic;
+				TC			: in std_logic;
+				SI			: in std_logic;
+				SO			: out std_logic;
+				SO_EN		: out std_logic;
+				
+				-- DMA control:
+				RRn			: out std_logic;
+				TRn			: out std_logic			
+		);
+	end component WF68901IP_TOP_SOC;
+
+	component WF2149IP_TOP_SOC -- Sound.
+		port(
+			
+			SYS_CLK		: in std_logic; -- Read the inforation in the header!
+			RESETn   	: in std_logic;
+
+			WAV_CLK		: in std_logic; -- Read the inforation in the header!
+			SELn		: in std_logic;
+			
+			BDIR		: in std_logic;
+			BC2, BC1	: in std_logic;
+
+			A9n, A8		: in std_logic;
+			DA_IN		: in std_logic_vector(7 downto 0);
+			DA_OUT		: out std_logic_vector(7 downto 0);
+			DA_EN		: out std_logic;
+			
+			IO_A_IN		: in std_logic_vector(7 downto 0);
+			IO_A_OUT	: out std_logic_vector(7 downto 0);
+			IO_A_EN		: out std_logic;
+			IO_B_IN		: in std_logic_vector(7 downto 0);
+			IO_B_OUT	: out std_logic_vector(7 downto 0);
+			IO_B_EN		: out std_logic;
+
+			OUT_A		: out std_logic; -- Analog (PWM) outputs.
+			OUT_B		: out std_logic;
+			OUT_C		: out std_logic
+		);
+	end component WF2149IP_TOP_SOC;
+
+	component WF6850IP_TOP_SOC -- ACIA.
+	  port (
+			CLK					: in std_logic;
+	        RESETn				: in std_logic;
+
+	        CS2n, CS1, CS0		: in std_logic;
+	        E		       		: in std_logic;   
+	        RWn              	: in std_logic;
+	        RS					: in std_logic;
+
+	        DATA_IN		        : in std_logic_vector(7 downto 0);   
+	        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+			DATA_EN				: out std_logic;
+
+	        TXCLK				: in std_logic;
+	        RXCLK				: in std_logic;
+	        RXDATA				: in std_logic;
+	        CTSn				: in std_logic;
+	        DCDn				: in std_logic;
+	        
+	        IRQn				: out std_logic;
+	        TXDATA				: out std_logic;   
+	        RTSn				: out std_logic
+	       );                                              
+	end component WF6850IP_TOP_SOC;
+
+	component WF_SD_CARD
+		port (
+			RESETn			: in std_logic;
+			CLK				: in std_logic;
+			ACSI_A1			: in std_logic;
+			ACSI_CSn		: in std_logic;
+			ACSI_ACKn		: in std_logic;
+			ACSI_INTn		: out std_logic;
+			ACSI_DRQn		: out std_logic;
+			ACSI_D_IN		: in std_logic_vector(7 downto 0);
+			ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+			ACSI_D_EN		: out std_logic;
+			MC_DO			: in std_logic;
+			MC_PIO_DMAn		: in std_logic;
+			MC_RWn			: in std_logic;
+			MC_CLR_CMD		: in std_logic;
+			MC_DONE			: out std_logic;
+			MC_GOT_CMD		: out std_logic;
+			MC_D_IN			: in std_logic_vector(7 downto 0);
+			MC_D_OUT		: out std_logic_vector(7 downto 0);
+			MC_D_EN			: out std_logic
+	      );
+	end component WF_SD_CARD;
+
+	component dcfifo0 
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
+	);
+	end component dcfifo0;
+	
+	component dcfifo1
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
+		);
+	end component;
+
+
+end FalconIO_SDCard_IDE_CF_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
new file mode 100644
index 0000000..4453332
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
@@ -0,0 +1,631 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the 5380's system controller.                   ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_CONTROL is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit; -- System reset.
+		
+        -- System controls:
+        BSY_INn     : in bit; -- SCSI BSY_INn bit.
+        BSY_OUTn    : out bit; -- SCSI BSY_INn bit.
+        DATA_EN     : out bit; -- Enable the SCSI data lines.
+        SEL_INn     : in bit; -- SCSI SEL_INn bit.
+        ARB_EN      : in bit; -- Arbitration enable.
+        BSY_DISn    : in bit; -- BSY monitoring enable.
+		RSTn	    : in bit; -- SCSI reset.
+        
+        ARB         : out bit; -- Arbitration flag.
+        AIP         : out bit; -- Arbitration in progress flag.
+        LA          : out bit; -- Lost arbitration flag.
+
+        ACK_INn     : in bit;
+        ACK_OUTn    : out bit;
+        REQ_INn     : in bit;
+        REQ_OUTn    : out bit;
+
+        DACKn       : in bit; -- Data acknowledge.
+        READY       : out bit;
+        DRQ         : out bit; -- Data request.
+
+        TARG        : in bit; -- Target mode indicator.
+        BLK         : in bit; -- Block mode indicator.
+        PINT_EN     : in bit; -- Parity interrupt enable.
+        SPER        : in bit; -- Parity error.
+        SER_ID      : in bit; -- SER matches ODR bits.
+        RPI         : in bit; -- Reset interrupts.
+        DMA_EN      : in bit; -- DMA mode enable.
+		SDS         : in bit; -- Start DMA send, write only.
+		SDT         : in bit; -- Start DMA target receive, write only.
+		SDI         : in bit; -- Start DMA initiator receive, write only.
+        EOP_EN      : in bit; -- EOP interrupt enable.
+        EOPn        : in bit; -- End of process indicator.
+        PHSM        : in bit; -- Phase match flag.
+
+        INT         : out bit; -- Interrupt.
+        IDR_WR      : out bit; -- Write input data register during DMA.
+        ODR_WR      : out bit; -- Write output data register, during DMA.
+        CHK_PAR     : out bit; -- Check Parity during DMA operation.
+        BSY_ERR     : out bit; -- Busy monitoring error.
+        DMA_SND     : out bit; -- Indicates direction of target DMA.
+        DMA_ACTIVE  : out bit -- DMA is active.
+    );
+end entity WF5380_CONTROL;
+	
+architecture BEHAVIOUR of WF5380_CONTROL is
+type CTRL_STATES is (IDLE, WAIT_800ns, WAIT_2200ns, DMA_SEND, DMA_TARG_RCV, DMA_INIT_RCV);
+type DMA_STATES is (IDLE, DMA_STEP_1, DMA_STEP_2, DMA_STEP_3, DMA_STEP_4);
+signal CTRL_STATE       : CTRL_STATES;
+signal NEXT_CTRL_STATE  : CTRL_STATES;
+signal DMA_STATE        : DMA_STATES;
+signal NEXT_DMA_STATE   : DMA_STATES;
+signal BUS_FREE         : bit;
+signal DELAY_800ns      : boolean;
+signal DELAY_2200ns     : boolean;
+signal DMA_ACTIVE_I     : bit;
+signal EOP_In           : bit;
+begin
+    IN_BUFFER: process
+    -- This buffer shall prevent some signals against
+    -- setup hold effects and thus the state machine
+    -- against unpredictable behaviour.
+    begin
+        wait until CLK = '1' and CLK' event;
+        EOP_In <= EOPn;
+    end process IN_BUFFER;
+
+    STATE_REGISTERS: process(RESETn, CLK)
+    -- This is the controller's state machine register.
+    variable BSY_LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            CTRL_STATE <= IDLE;
+            DMA_STATE <= IDLE;
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' then -- SCSI reset.
+                CTRL_STATE <= IDLE;
+                DMA_STATE <= IDLE;
+            else
+                CTRL_STATE <= NEXT_CTRL_STATE;
+                DMA_STATE <= NEXT_DMA_STATE;
+            end if;
+            --
+            if DMA_EN = '0' then
+                DMA_STATE <= IDLE;
+            end if;
+        end if;
+    end process STATE_REGISTERS;
+
+    CTRL_DECODER: process(CTRL_STATE, ARB_EN, BUS_FREE, DELAY_800ns, SEL_INn, DMA_ACTIVE_I, SDS, SDT, SDI)
+    -- This is the controller's state machine decoder.
+    variable BSY_LOCK   : boolean;
+    begin
+        -- Defaults.
+        DMA_SND <= '0';
+        --
+        case CTRL_STATE is
+            when IDLE =>
+                if ARB_EN = '1' and BUS_FREE = '1' then
+                    NEXT_CTRL_STATE <= WAIT_800ns;
+                else
+                    NEXT_CTRL_STATE <= IDLE;
+                end if;
+            when WAIT_800ns =>
+                if DELAY_800ns = true then
+                    NEXT_CTRL_STATE <= WAIT_2200ns;
+                else
+                    NEXT_CTRL_STATE <= WAIT_800ns;
+                end if;
+            when WAIT_2200ns =>
+                -- In this state the delay is provided by the
+                -- microprocessor and is at least 2.2us. The
+                -- delay is released by deasserting SELn.
+                if SEL_INn = '1' and SDS = '1' then
+                    NEXT_CTRL_STATE <= DMA_SEND;
+                elsif SEL_INn = '1' and SDT = '1' then
+                    NEXT_CTRL_STATE <= DMA_TARG_RCV;
+                elsif SEL_INn = '1' and SDI = '1' then
+                    NEXT_CTRL_STATE <= DMA_INIT_RCV;
+                else
+                    NEXT_CTRL_STATE <= WAIT_2200ns;
+                end if;
+            when DMA_SEND =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_SEND;
+                end if;
+                --
+                DMA_SND <= '1';
+            when DMA_TARG_RCV =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_TARG_RCV;
+                end if;
+            when DMA_INIT_RCV =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_INIT_RCV;
+                end if;
+        end case;
+    end process CTRL_DECODER;
+
+    DMA_DECODER: process(CTRL_STATE, DMA_STATE, TARG, BLK, DACKn, REQ_INn, ACK_INn)
+    -- This is the DMA state machine decoder.
+    begin
+        -- Defaults:
+        IDR_WR <= '0';
+        ODR_WR <= '0';
+        CHK_PAR <= '0';
+        --
+        case DMA_STATE is
+            when IDLE =>
+                if CTRL_STATE = DMA_SEND then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                elsif CTRL_STATE = DMA_INIT_RCV then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                elsif CTRL_STATE = DMA_TARG_RCV then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                else
+                    NEXT_DMA_STATE <= IDLE;
+                end if;
+        when DMA_STEP_1 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted.
+                IDR_WR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted.
+                IDR_WR <= '1';
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted.
+                IDR_WR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted.
+                IDR_WR <= '1';
+            else
+                NEXT_DMA_STATE <= DMA_STEP_1;
+            end if;
+        when DMA_STEP_2 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted.
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted.
+            else
+                NEXT_DMA_STATE <= DMA_STEP_2;
+            end if;
+        when DMA_STEP_3 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            else
+                NEXT_DMA_STATE <= DMA_STEP_3;
+            end if;
+        when DMA_STEP_4 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            else
+                NEXT_DMA_STATE <= DMA_STEP_4;
+            end if;
+        end case;
+    end process DMA_DECODER;
+
+    P_REQn: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the REQn output in target mode.
+    begin
+        if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+            REQ_OUTn <= '0';
+        else
+            REQ_OUTn <= '1';
+        end if;
+    end process P_REQn;
+    
+    P_ACKn: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the ACKn output in initiator mode.
+    begin
+        if DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then
+            ACK_OUTn <= '0';
+        else
+            ACK_OUTn <= '1';
+        end if;
+    end process P_ACKn;
+
+    P_READY: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the READY output in initiator and target block mode.
+    begin
+        if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+            READY <= '1';
+        else
+            READY <= '0';
+        end if;
+    end process P_READY;
+    
+    P_DRQ: process(RESETn, CLK)
+    -- This flip flop controls the DRQ flag during all initiator and all target modes
+    -- for both block mode and non block mode operation.
+    variable LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            DRQ <= '0';
+            LOCK := false;
+        elsif CLK = '1' and CLK' event then
+            -- Initiator modes:
+            if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and LOCK = false then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            -- Target modes:
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DACKn = '0' and LOCK = false then
+                DRQ <= '0';
+            elsif EOPn = '0' and DACKn = '0' then
+                DRQ <= '0';
+                LOCK := false;
+            end if;
+        end if;
+    end process P_DRQ;
+
+    P_BUSFREE: process(RESETn, CLK)
+    -- This is the logic for the bus free signal.
+    -- A bus free is valid if the BSY_INn signal is
+    -- at least 437.5ns inactive ans SEL_INn is inactive.
+    -- The delay are 7 clock cycles of 16MHz.
+    variable TMP    : std_logic_vector(2 downto 0);
+    begin
+        if RESETn = '0' then
+            BUS_FREE <= '0';
+            TMP := "000";
+        elsif CLK = '1' and CLK' event then
+            if BSY_INn = '1' and TMP < x"111" then
+                TMP := TMP + '1';
+            elsif BSY_INn = '0' then
+                TMP := "000";
+            end if;
+            --
+            if RSTn = '0' then -- SCSI reset.
+                BUS_FREE <= '0';
+            elsif SEL_INn = '1' and TMP = "111" then
+                BUS_FREE <= '1';
+            else
+                BUS_FREE <= '0';
+            end if;
+        end if;
+    end process P_BUSFREE;
+
+    DELAY_800: process(RESETn, CLK)
+    -- This is the delay of 812.5ns.
+    -- It is derived from 13 16MHz clock cycles.
+    variable TMP    : std_logic_vector(3 downto 0);
+    begin
+        if RESETn = '0' then
+            DELAY_800ns <= false;
+            TMP := x"0";
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE /= WAIT_800ns then
+                TMP := x"0";
+            elsif TMP <= x"D" then
+                TMP := TMP + '1';
+            end if;
+            --
+            if TMP = x"D" then
+                DELAY_800ns <= true;
+            else
+                DELAY_800ns <= false;
+            end if;
+        end if;
+    end process DELAY_800;
+
+    P_ARB: process(RESETn, CLK)
+    -- This flip flop controls the ARB flag read back
+    -- by the microcontroller.
+    begin
+        if RESETn = '0' then
+            ARB <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE /= WAIT_800ns and NEXT_CTRL_STATE = WAIT_800ns then
+                ARB <= '1';
+            elsif ARB_EN = '0' then
+                ARB <= '0';
+            end if;
+        end if;
+    end process P_ARB;
+
+    P_AIP: process(RESETn, CLK)
+    -- This flip flop controls the AIP flag read back
+    -- by the microcontroller.
+    begin
+        if RESETn = '0' then
+            AIP <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+                AIP <= '1';
+            elsif ARB_EN = '0' then
+                AIP <= '0';
+            end if;
+        end if;
+    end process P_AIP;
+    
+    P_BSY: process
+    -- This flip flop controls the BSYn output
+    -- to the SCSI bus.
+    begin
+        wait until CLK = '1' and CLK' event;
+        if RESETn = '0' then
+            BSY_OUTn <= '1';
+        elsif CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+            BSY_OUTn <= '0';
+        elsif ARB_EN = '0' then
+            BSY_OUTn <= '1';
+        end if;
+    end process P_BSY;
+    
+    P_DATA_EN: process(RESETn, CLK)
+    -- This flip flop controls the data enable
+    -- of the SCSI bus.
+    begin
+        if RESETn = '0' then
+            DATA_EN <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+                DATA_EN <= '1';
+            elsif ARB_EN = '0' then
+                DATA_EN <= '0';
+            end if;
+        end if;
+    end process P_DATA_EN;
+    
+    P_LA: process(RESETn, CLK)
+    -- This flip flop controls the LA
+    -- (lost arbitration) flag.
+    begin
+        if RESETn = '0' then
+            LA <= '0';
+        elsif CLK = '1' and CLK' event then
+            if (CTRL_STATE = WAIT_800ns or CTRL_STATE = WAIT_2200ns) and SEL_INn = '0' then
+                LA <= '1';
+            elsif ARB_EN = '0' then
+                LA <= '0';
+            end if;
+        end if;
+    end process P_LA;
+
+    P_DMA_ACTIVE: process(RESETn, CLK, DMA_ACTIVE_I)
+    -- This is the Flip Flop indicating if there is DMA
+    -- operation.
+    begin
+        if RESETn = '0' then
+            DMA_ACTIVE_I <= '0';
+        elsif CLK = '1' and CLK' event then
+            if DMA_EN = '1' and SDS = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA send.
+            elsif DMA_EN = '1' and SDT = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA target receive.
+            elsif DMA_EN = '1' and SDI = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA initiator receive.
+            elsif DMA_EN = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via DMA flag in MR2.
+            elsif EOP_In = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via EOPn.
+            elsif PHSM = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via phase mismatch.
+            end if;
+        end if;
+        --
+        DMA_ACTIVE <= DMA_ACTIVE_I;
+    end process P_DMA_ACTIVE;
+
+    INTERRUPTS: process(RESETn, CLK)
+    -- This is the logic for all DP5380's interrupt sources.
+    -- A busy interrupt occurs if the BSY_INn signal is at 
+    -- least 437.5ns inactive. The delay are 7 clock cycles
+    -- of 16MHz. This logic also provides the respective 
+    -- error flags for the BSR.
+    variable TMP    : std_logic_vector(2 downto 0);
+    begin
+        if RESETn = '0' then
+            INT <= '0';
+            BSY_ERR <= '0';
+            TMP := "000";
+        elsif CLK = '1' and CLK' event then
+            if SPER = '1' and PINT_EN = '1' then
+                INT <= '1'; -- Parity interrupt.
+            elsif RPI = '0' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if EOP_In = '0' and CTRL_STATE = DMA_SEND then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif DMA_EN = '0' then -- Reset error.
+                INT <= '0';
+            end if;
+            --
+            if EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_SEND then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif DMA_EN = '0' then -- Reset interrupt.
+                INT <= '0';
+            end if;
+
+            --
+            if PHSM = '0' then
+                INT <= '1'; -- Phase mismatch interrupt.
+            elsif DMA_EN = '0' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if SEL_INn = '0' and BSY_INn = '1' and SER_ID = '1' then
+                INT <= '1'; -- (Re)Selection interrupt.
+            elsif RPI = '1' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if BSY_INn = '1' and TMP < x"111" then
+                TMP := TMP + '1'; -- Bus settle delay.
+            elsif BSY_INn = '0' then
+                TMP := "000";
+            end if;
+            --
+            if BSY_DISn = '1' and BSY_INn = '1' and TMP = x"111" then
+                INT <= '1'; -- Busy monitoring interrupt.
+                BSY_ERR <= '1';
+            elsif RPI = '1' then -- Reset interrupts.
+                INT <= '0';
+                BSY_ERR <= '0';
+            end if;
+            --
+        end if;
+    end process INTERRUPTS;
+end BEHAVIOUR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
new file mode 100644
index 0000000..57cf305
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
@@ -0,0 +1,139 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the package file of the ip core.                ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF5380_PKG is
+    component WF5380_REGISTERS
+        port (
+            CLK			: in bit;
+            RESETn	    : in bit;
+            ADR			: in bit_vector(2 downto 0);
+            DATA_IN		: in bit_vector(7 downto 0);
+            DATA_OUT	: out bit_vector(7 downto 0);
+            DATA_EN		: out bit;
+            CSn			: in bit;
+            RDn		    : in bit;
+            WRn	        : in bit;
+            RSTn	    : in bit;
+            RST         : out bit;
+            ARB_EN      : out bit;
+            DMA_ACTIVE  : in bit;
+            DMA_EN      : out bit;
+            BSY_DISn    : out bit;
+            EOP_EN      : out bit;
+            PINT_EN     : out bit;
+            SPER        : out bit;
+            TARG        : out bit;
+            BLK         : out bit;
+            DMA_DIS     : in bit;
+            IDR_WR      : in bit;
+            ODR_WR      : in bit;
+            CHK_PAR     : in bit;
+            AIP         : in bit;
+            ARB         : in bit;
+            LA          : in bit;
+            CSD         : in bit_vector(7 downto 0);
+            CSB         : in bit_vector(7 downto 0);
+            BSR         : in bit_vector(7 downto 0);
+            ODR_OUT     : out bit_vector(7 downto 0);
+            ICR_OUT     : out bit_vector(7 downto 0);
+            TCR_OUT     : out bit_vector(3 downto 0);
+            SER_OUT     : out bit_vector(7 downto 0);
+            SDS         : out bit;
+            SDT         : out bit;
+            SDI         : out bit;
+            RPI         : out bit
+        );
+    end component;
+
+    component WF5380_CONTROL
+        port (
+            CLK			: in bit;
+            RESETn	    : in bit;
+            BSY_INn     : in bit;
+            BSY_OUTn    : out bit;
+            DATA_EN     : out bit;
+            SEL_INn     : in bit;
+            ARB_EN      : in bit;
+            BSY_DISn    : in bit;
+            RSTn	    : in bit;
+            ARB         : out bit;
+            AIP         : out bit;
+            LA          : out bit;
+            ACK_INn     : in bit;
+            ACK_OUTn    : out bit;
+            REQ_INn     : in bit;
+            REQ_OUTn    : out bit;
+            DACKn       : in bit;
+            READY       : out bit;
+            DRQ         : out bit;
+            TARG        : in bit;
+            BLK         : in bit;
+            PINT_EN     : in bit;
+            SPER        : in bit;
+            SER_ID      : in bit;
+            RPI         : in bit;
+            DMA_EN      : in bit;
+            SDS         : in bit;
+            SDT         : in bit;
+            SDI         : in bit;
+            EOP_EN      : in bit;
+            EOPn        : in bit;
+            PHSM        : in bit;
+            INT         : out bit;
+            IDR_WR      : out bit;
+            ODR_WR      : out bit;
+            CHK_PAR     : out bit;
+            BSY_ERR     : out bit;
+            DMA_SND     : out bit;
+            DMA_ACTIVE  : out bit
+        );
+    end component;
+end WF5380_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
new file mode 100644
index 0000000..2c21c12
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
@@ -0,0 +1,265 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the 5380's register model.                      ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Register description (for more information see the DP5380    ----
+---- data sheet:                                                  ----
+----   ODR (address 0) Output data register, write only.          ----
+----   CSD (address 0) Current SCSI data, read only.              ----
+----   ICR (address 1) Initiator command register, read/write.    ----
+----   MR2 (address 2) Mode register 2, read/write.               ----
+----   TCR (address 3) Target command register, read/write.       ----
+----   SER (address 4) Select enable register, write only.        ----
+----   CSB (address 4) Current SCSI bus status, read only.        ----
+----   BSR (address 5) Start DMA send, write only.                ----
+----   SDS (address 5) Bus and status, read only.                 ----
+----   SDT (address 6) Start DMA target receive, write only.      ----
+----   IDR (address 6) Input data register, read only.            ----
+----   SDI (address 7) Start DMA initiator recive, write only.    ----
+----   RPI (address 7) Reset parity / interrupts, read only.      ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_REGISTERS is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit; -- System reset.
+		
+		-- Address and data:
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+
+        -- Core controls:
+		RSTn	    : in bit; -- SCSI reset.
+		RST         : out bit; -- Programmed SCSI reset.
+        ARB_EN      : out bit; -- Arbitration enable.
+        DMA_ACTIVE  : in bit; -- DMA is running.
+        DMA_EN      : out bit; -- DMA mode enable.
+        BSY_DISn    : out bit; -- BSY monitoring enable.
+        EOP_EN      : out bit; -- EOP interrupt enable.
+        PINT_EN     : out bit; -- Parity interrupt enable.
+        SPER        : out bit; -- Parity error.
+        TARG        : out bit; -- Target mode.
+        BLK         : out bit; -- Block DMA mode.
+        DMA_DIS     : in bit; -- Reset the DMA_EN by this signal.
+        IDR_WR      : in bit; -- Write input data register during DMA.
+        ODR_WR      : in bit; -- Write output data register, during DMA.
+        CHK_PAR     : in bit; -- Check Parity during DMA operation.
+        AIP         : in bit; -- Arbitration in progress.
+        ARB         : in bit; -- Arbitration.
+        LA          : in bit; -- Lost arbitration.
+
+        CSD         : in bit_vector(7 downto 0); -- SCSI data.
+        CSB         : in bit_vector(7 downto 0); -- Current SCSI bus status.
+        BSR         : in bit_vector(7 downto 0); -- Bus and status.
+
+        ODR_OUT     : out bit_vector(7 downto 0); -- This is the ODR register.
+        ICR_OUT     : out bit_vector(7 downto 0); -- This is the ICR register.
+        TCR_OUT     : out bit_vector(3 downto 0); -- This is the TCR register.
+        SER_OUT     : out bit_vector(7 downto 0); -- This is the SER register.
+        
+		SDS         : out bit; -- Start DMA send, write only.
+		SDT         : out bit; -- Start DMA target receive, write only.
+		SDI         : out bit; -- Start DMA initiator receive, write only.
+		RPI         : out bit
+    );
+end entity WF5380_REGISTERS;
+	
+architecture BEHAVIOUR of WF5380_REGISTERS is
+signal ICR  : bit_vector(7 downto 0); -- Initiator command register, read/write.
+signal IDR  : bit_vector(7 downto 0); -- Input data register.
+signal MR2  : bit_vector(7 downto 0); -- Mode register 2, read/write.
+signal ODR  : bit_vector(7 downto 0); -- Output data register, write only.
+signal SER  : bit_vector(7 downto 0); -- Select enable register, write only.
+signal TCR  : bit_vector(3 downto 0); -- Target command register, read/write.
+begin
+    REGISTERS: process(RESETn, CLK)
+    -- This process reflects all registers in the 5380.
+    variable BSY_LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            ODR <= (others => '0');
+            ICR <= (others => '0');
+            MR2 <= (others => '0');
+            TCR <= (others => '0');
+            SER <= (others => '0');
+            BSY_LOCK  := false;
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' then -- SCSI reset.
+                ODR <= (others => '0');
+                ICR(6 downto 0) <= (others => '0');
+                MR2(7) <= '0';
+                MR2(5 downto 0) <= (others => '0');
+                TCR <= (others => '0');
+                SER <= (others => '0');
+                BSY_LOCK  := false;
+            elsif ADR = "000" and CSn = '0' and WRn = '0' then
+                ODR <= DATA_IN;
+            elsif ADR = "001" and CSn = '0' and WRn = '0' then
+                ICR <= DATA_IN;
+            elsif ADR = "010" and CSn = '0' and WRn = '0' then
+                MR2 <= DATA_IN;
+            elsif ADR = "011" and CSn = '0' and WRn = '0' then
+                TCR <= DATA_IN(3 downto 0);
+            elsif ADR = "100" and CSn = '0' and WRn = '0' then
+                SER <= DATA_IN;
+            end if;
+            --
+            if ODR_WR = '1' then
+                ODR <= DATA_IN;
+            end if;
+            --
+            -- This reset function is edge triggered on the 'Monitor Busy'
+            -- MR2(2).
+            if MR2(2) = '1' and BSY_LOCK = false then
+                ICR(5 downto 0) <= "000000";
+                BSY_LOCK := true;
+            elsif MR2(2) = '0' then
+                BSY_LOCK := false;
+            end if;
+            --
+            if DMA_DIS = '1' then
+                MR2(1) <= '0';
+            end if;
+        end if;
+    end process REGISTERS;
+    
+    IDR_REGISTER: process(RESETn, CLK)
+    begin
+        if RESETn = '0' then
+            IDR <= x"00";
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' or ICR(7) = '1' then
+                IDR <= x"00"; -- SCSI reset.
+            elsif IDR_WR = '1' then
+                IDR <= CSD;
+            end if;
+        end if;
+    end process IDR_REGISTER;
+    
+    PARITY: process(RESETn, CLK)
+    -- This is the parity generating logic with it's related
+    -- error generation.
+	variable PAR_VAR : bit;
+	variable LOCK : boolean;
+    begin
+        if RESETn = '0' then
+            SPER <= '0';
+            LOCK := false;
+        elsif CLK = '1' and CLK' event then
+            -- Parity checked during 'Read from CSD' 
+            -- (registered I/O and selection/reselection):
+            if ADR = "000" and CSn = '0' and RDn = '0' and LOCK = false then
+                for i in 1 to 7 loop
+                    PAR_VAR := CSD(i) xor CSD(i-1);
+                end loop;
+                SPER <= not PAR_VAR;
+                LOCK := true;
+            end if;
+            --
+            -- Parity checking during DMA operation:
+            if DMA_ACTIVE = '1' and CHK_PAR = '1' then
+                for i in 1 to 7 loop
+                    PAR_VAR := IDR(i) xor IDR(i-1);
+                end loop;
+                SPER <= not PAR_VAR;
+                LOCK := true;
+            end if;
+            --
+            -- Reset parity flag:
+            if MR2(5) <= '0' then -- MR2(5) = PCHK (disabled).
+                SPER <= '0';
+            elsif ADR = "111" and CSn = '0' and RDn = '0' then -- Reset parity/interrupts.
+                SPER <= '0';
+                LOCK := false;
+            end if;
+        end if;
+    end process PARITY;
+
+    DATA_EN <= '1' when ADR < "101" and CSn = '0' and WRn = '0' else '0';
+
+    SDS <= '1' when ADR = "101" and CSn = '0' and WRn = '0' else '0';
+    SDT <= '1' when ADR = "110" and CSn = '0' and WRn = '0' else '0';
+    SDI <= '1' when ADR = "111" and CSn = '0' and WRn = '0' else '0';
+    
+    ICR_OUT <= ICR;
+    TCR_OUT <= TCR;
+    SER_OUT <= SER;
+    ODR_OUT <= ODR;
+    
+    ARB_EN  <= MR2(0);
+    DMA_EN  <= MR2(1);
+    BSY_DISn  <= MR2(2);
+    EOP_EN  <= MR2(3);
+    PINT_EN <= MR2(4);
+    TARG    <= MR2(6);
+    BLK     <= MR2(7);
+    
+    RST     <= ICR(7);
+       
+    -- Readback, unused bit positions are read back zero.
+    DATA_OUT <= CSD when ADR = "000" and CSn = '0' and RDn = '0' else -- Current SCSI data.
+                ICR(7) & AIP & LA & ICR(4 downto 0) when ADR = "001" and CSn = '0' and RDn = '0' else
+                MR2 when ADR = "010" and CSn = '0' and RDn = '0' else
+                x"0" & TCR when ADR = "011" and CSn = '0' and RDn = '0' else
+                CSB when ADR = "100" and CSn = '0' and RDn = '0' else -- Current SCSI bus status.
+                BSR when ADR = "101" and CSn = '0' and RDn = '0' else -- Bus and status.
+                IDR when ADR = "110" and CSn = '0' and RDn = '0' else x"00"; -- Input data register.
+
+    RPI <= '1' when ADR = "111" and CSn = '0' and RDn = '0' else '0'; -- Reset parity/interrupts.
+end BEHAVIOUR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
new file mode 100644
index 0000000..abc0400
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
@@ -0,0 +1,300 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- Some remarks to the required input clock:                    ----
+---- This core is provided for a 16MHz input clock. To use other  ----
+---- frequencies, it is necessary to modify the following proces- ----
+---- ses in the control file section:                             ----
+---- P_BUSFREE, DELAY_800, INTERRUPTS.                            ----
+----                                                              ----
+---- This file is the top level file without tree state buses for ----
+---- use in 'systems on chip' designs.                            ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library work;
+use work.wf5380_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_TOP_SOC is
+	port (
+        -- System controls:
+		CLK			: in bit; -- Use a 16MHz Clock.
+		RESETn	    : in bit;
+		
+		-- Address and data:
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		
+		-- SCSI bus:
+		DB_INn		: in bit_vector(7 downto 0);
+		DB_OUTn		: out bit_vector(7 downto 0);
+		DB_EN       : out bit;
+		DBP_INn		: in bit;
+		DBP_OUTn	: out bit;
+		DBP_EN      : out bit;
+		RST_INn     : in bit;
+		RST_OUTn    : out bit;
+		RST_EN      : out bit;
+		BSY_INn     : in bit;
+		BSY_OUTn    : out bit;
+		BSY_EN      : out bit;
+		SEL_INn     : in bit;
+		SEL_OUTn    : out bit;
+		SEL_EN      : out bit;
+		ACK_INn     : in bit;
+		ACK_OUTn    : out bit;
+		ACK_EN      : out bit;
+		ATN_INn     : in bit;
+		ATN_OUTn    : out bit;
+		ATN_EN      : out bit;
+		REQ_INn     : in bit;
+		REQ_OUTn    : out bit;
+		REQ_EN      : out bit;
+		IOn_IN      : in bit;
+		IOn_OUT     : out bit;
+		IO_EN       : out bit;
+		CDn_IN      : in bit;
+		CDn_OUT     : out bit;
+		CD_EN       : out bit;
+		MSG_INn     : in bit;
+		MSG_OUTn    : out bit;
+		MSG_EN      : out bit
+	);
+end entity WF5380_TOP_SOC;
+	
+architecture STRUCTURE of WF5380_TOP_SOC is
+signal ACK_OUT_CTRLn    : bit;
+signal AIP              : bit;
+signal ARB              : bit;
+signal ARB_EN           : bit;
+signal BLK              : bit;
+signal BSR              : bit_vector(7 downto 0);
+signal BSY_DISn         : bit;
+signal BSY_ERR          : bit;
+signal BSY_OUT_CTRLn    : bit;
+signal CHK_PAR          : bit;
+signal CSD              : bit_vector(7 downto 0);
+signal CSB              : bit_vector(7 downto 0);
+signal DATA_EN_CTRL     : bit;
+signal DB_EN_I          : bit;
+signal DMA_ACTIVE       : bit;
+signal DMA_EN           : bit;
+signal DMA_DIS          : bit;
+signal DMA_SND          : bit;
+signal DRQ_I            : bit;
+signal EDMA             : bit;
+signal EOP_EN           : bit;
+signal ICR              : bit_vector(7 downto 0);
+signal IDR_WR           : bit;
+signal INT_I            : bit;
+signal LA               : bit;
+signal ODR              : bit_vector(7 downto 0);
+signal ODR_WR           : bit;
+signal PCHK             : bit;
+signal PHSM             : bit;
+signal PINT_EN          : bit;
+signal REQ_OUT_CTRLn    : bit;
+signal RPI              : bit;
+signal RST              : bit;
+signal SDI              : bit;
+signal SDS              : bit;
+signal SDT              : bit;
+signal SER              : bit_vector(7 downto 0);
+signal SER_ID           : bit;
+signal SPER             : bit;
+signal TARG             : bit;
+signal TCR              : bit_vector(3 downto 0);
+begin
+    EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else
+            '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0';
+
+    PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA.
+            '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch.
+
+    DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0';
+
+    SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0';
+
+    DRQ <= DRQ_I;
+    INT <= INT_I;
+
+    -- Pay attention: the SCSI bus is driven with inverted signals.
+    ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode.
+    REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3);  -- Valid in Target mode.
+    BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode.
+                '0' when ICR(3) = '1' else '1';
+    ATN_OUTn <= not ICR(1); -- Valid in initiator mode.
+    SEL_OUTn <= not ICR(2); -- Valid in initiator mode.
+    IOn_OUT <= not TCR(0);  -- Valid in Target mode.
+    CDn_OUT <= not TCR(1);  -- Valid in Target mode.
+    MSG_OUTn <= not TCR(2);  -- Valid in Target mode.
+    RST_OUTn <= not RST;
+
+    DB_OUTn <= not ODR;
+    DBP_OUTn <= not SPER; 
+
+    CSD <= not DB_INn;
+    CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn;
+    BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn;
+
+    -- Hi impedance control:
+    ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    IO_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    CD_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    RST_EN <= '1' when RST = '1' else '0'; -- Open drain control.
+    
+    -- Data enables:
+    DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arbitration.
+               '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode.
+               '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else 
+               '1' when ICR(6) = '1' else '0'; -- Test mode enable.
+
+    DB_EN <= DB_EN_I;
+    DBP_EN <= DB_EN_I;
+
+    I_REGISTERS: WF5380_REGISTERS
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            ADR			=> ADR,
+            DATA_IN		=> DATA_IN,
+            DATA_OUT	=> DATA_OUT,
+            DATA_EN		=> DATA_EN,
+            CSn			=> CSn,
+            RDn		    => RDn,
+            WRn	        => WRn,
+            RSTn	    => RST_INn,
+            RST         => RST,
+            ARB_EN      => ARB_EN,
+            DMA_ACTIVE  => DMA_ACTIVE,
+            DMA_EN      => DMA_EN,
+            BSY_DISn    => BSY_DISn,
+            EOP_EN      => EOP_EN,
+            PINT_EN     => PINT_EN,
+            SPER        => SPER,
+            TARG        => TARG,
+            BLK         => BLK,
+            DMA_DIS     => DMA_DIS,
+            IDR_WR      => IDR_WR,
+            ODR_WR      => ODR_WR,
+            CHK_PAR     => CHK_PAR,
+            AIP         => AIP,
+            ARB         => ARB,
+            LA          => LA,
+            CSD         => CSD,
+            CSB         => CSB,
+            BSR         => BSR,
+            ODR_OUT     => ODR,
+            ICR_OUT     => ICR,
+            TCR_OUT     => TCR,
+            SER_OUT     => SER,
+            SDS         => SDS,
+            SDT         => SDT,
+            SDI         => SDI,
+            RPI         => RPI
+        );
+
+    I_CONTROL: WF5380_CONTROL
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            BSY_INn     => BSY_INn,
+            BSY_OUTn    => BSY_OUT_CTRLn,
+            DATA_EN     => DATA_EN_CTRL,
+            SEL_INn     => SEL_INn,
+            ARB_EN      => ARB_EN,
+            BSY_DISn    => BSY_DISn,
+            RSTn	    => RST_INn,
+            ARB         => ARB,
+            AIP         => AIP,
+            LA          => LA,
+            ACK_INn     => ACK_INn,
+            ACK_OUTn    => ACK_OUT_CTRLn,
+            REQ_INn     => REQ_INn,
+            REQ_OUTn    => REQ_OUT_CTRLn,
+            DACKn       => DACKn,
+            READY       => READY,
+            DRQ         => DRQ_I,
+            TARG        => TARG,
+            BLK         => BLK,
+            PINT_EN     => PINT_EN,
+            SPER        => SPER,
+            SER_ID      => SER_ID,
+            RPI         => RPI,
+            DMA_EN      => DMA_EN,
+            SDS         => SDS,
+            SDT         => SDT,
+            SDI         => SDI,
+            EOP_EN      => EOP_EN,
+            EOPn        => EOPn,
+            PHSM        => PHSM,
+            INT         => INT_I,
+            IDR_WR      => IDR_WR,
+            ODR_WR      => ODR_WR,
+            CHK_PAR     => CHK_PAR,
+            BSY_ERR     => BSY_ERR,
+            DMA_SND     => DMA_SND,
+            DMA_ACTIVE  => DMA_ACTIVE
+        );
+end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
new file mode 100644
index 0000000..bfb31fb
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
@@ -0,0 +1,275 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the top level file with tree state buses.       ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library work;
+use work.wf5380_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_TOP is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit;
+		
+		-- Address and data:
+		ADR			: in std_logic_vector(2 downto 0);
+		DATA		: inout std_logic_vector(7 downto 0);
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		
+		-- SCSI bus:
+		DBn		    : inout std_logic_vector(7 downto 0);
+		DBPn        : inout std_logic;
+		RSTn        : inout std_logic;
+		BSYn        : inout std_logic;
+		SELn        : inout std_logic;
+		ACKn        : inout std_logic;
+		ATNn        : inout std_logic;
+		REQn        : inout std_logic;
+		IOn         : inout std_logic;
+		CDn         : inout std_logic;
+		MSGn        : inout std_logic
+	);
+end entity WF5380_TOP;
+	
+architecture STRUCTURE of WF5380_TOP is
+component WF5380_TOP_SOC
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit;
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		DB_INn		: in bit_vector(7 downto 0);
+		DB_OUTn		: out bit_vector(7 downto 0);
+		DB_EN       : out bit;
+		DBP_INn		: in bit;
+		DBP_OUTn	: out bit;
+		DBP_EN      : out bit;
+		RST_INn     : in bit;
+		RST_OUTn    : out bit;
+		RST_EN      : out bit;
+		BSY_INn     : in bit;
+		BSY_OUTn    : out bit;
+		BSY_EN      : out bit;
+		SEL_INn     : in bit;
+		SEL_OUTn    : out bit;
+		SEL_EN      : out bit;
+		ACK_INn     : in bit;
+		ACK_OUTn    : out bit;
+		ACK_EN      : out bit;
+		ATN_INn     : in bit;
+		ATN_OUTn    : out bit;
+		ATN_EN      : out bit;
+		REQ_INn     : in bit;
+		REQ_OUTn    : out bit;
+		REQ_EN      : out bit;
+		IOn_IN      : in bit;
+		IOn_OUT     : out bit;
+		IO_EN       : out bit;
+		CDn_IN      : in bit;
+		CDn_OUT     : out bit;
+		CD_EN       : out bit;
+		MSG_INn     : in bit;
+		MSG_OUTn    : out bit;
+		MSG_EN      : out bit
+	);
+end component;
+--
+signal ADR_IN       : bit_vector(2 downto 0);
+signal DATA_IN      : bit_vector(7 downto 0);
+signal DATA_OUT     : bit_vector(7 downto 0);
+signal DATA_EN      : bit;
+signal DB_INn	    : bit_vector(7 downto 0);
+signal DB_OUTn	    : bit_vector(7 downto 0);
+signal DB_EN        : bit;
+signal DBP_INn	    : bit;
+signal DBP_OUTn	    : bit;
+signal DBP_EN       : bit;
+signal RST_INn      : bit;
+signal RST_OUTn     : bit;
+signal RST_EN       : bit;
+signal BSY_INn      : bit;
+signal BSY_OUTn     : bit;
+signal BSY_EN       : bit;
+signal SEL_INn      : bit;
+signal SEL_OUTn     : bit;
+signal SEL_EN       : bit;
+signal ACK_INn      : bit;
+signal ACK_OUTn     : bit;
+signal ACK_EN       : bit;
+signal ATN_INn      : bit;
+signal ATN_OUTn     : bit;
+signal ATN_EN       : bit;
+signal REQ_INn      : bit;
+signal REQ_OUTn     : bit;
+signal REQ_EN       : bit;
+signal IOn_IN       : bit;
+signal IOn_OUT      : bit;
+signal IO_EN        : bit;
+signal CDn_IN       : bit;
+signal CDn_OUT      : bit;
+signal CD_EN        : bit;
+signal MSG_INn      : bit;
+signal MSG_OUTn     : bit;
+signal MSG_EN       : bit;
+begin
+    ADR_IN <= To_BitVector(ADR);
+
+    DATA_IN <= To_BitVector(DATA);
+    DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z');
+
+    DB_INn <= To_BitVector(DBn);
+    DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z');
+
+    DBP_INn <= To_Bit(DBPn);
+
+    RST_INn <= To_Bit(RSTn);
+    BSY_INn <= To_Bit(BSYn);
+    SEL_INn <= To_Bit(SELn);
+    ACK_INn <= To_Bit(ACKn);
+    ATN_INn <= To_Bit(ATNn);
+    REQ_INn <= To_Bit(REQn);
+    IOn_IN <= To_Bit(IOn);
+    CDn_IN <= To_Bit(CDn);
+    MSG_INn <= To_Bit(MSGn);
+
+    DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else
+            '0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z';
+    RSTn <= '1' when RST_OUTn = '1' and RST_EN = '1'else
+            '0' when RST_OUTn = '0' and RST_EN = '1' else 'Z';
+    BSYn <= '1' when BSY_OUTn = '1' and BSY_EN = '1' else
+            '0' when BSY_OUTn = '0' and BSY_EN = '1' else 'Z';
+    SELn <= '1' when SEL_OUTn = '1' and SEL_EN = '1' else
+            '0' when SEL_OUTn = '0' and SEL_EN = '1' else 'Z';
+    ACKn <= '1' when ACK_OUTn = '1' and ACK_EN = '1' else
+            '0' when ACK_OUTn = '0' and ACK_EN = '1' else 'Z';
+    ATNn <= '1' when ATN_OUTn = '1' and ATN_EN = '1' else
+            '0' when ATN_OUTn = '0' and ATN_EN = '1' else 'Z';
+    REQn <= '1' when REQ_OUTn = '1' and REQ_EN = '1' else
+            '0' when REQ_OUTn = '0' and REQ_EN = '1' else 'Z';
+    IOn <=  '1' when IOn_OUT = '1' and IO_EN = '1' else
+            '0' when IOn_OUT = '0' and IO_EN = '1' else 'Z';
+    CDn <=  '1' when CDn_OUT = '1' and CD_EN = '1' else
+            '0' when CDn_OUT = '0' and CD_EN = '1' else 'Z';
+    MSGn <= '1' when MSG_OUTn = '1' and MSG_EN = '1' else
+            '0' when MSG_OUTn = '0' and MSG_EN = '1' else 'Z';
+
+    I_5380: WF5380_TOP_SOC
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            ADR			=> ADR_IN,
+            DATA_IN		=> DATA_IN,
+            DATA_OUT	=> DATA_OUT,
+            DATA_EN		=> DATA_EN,
+            CSn			=> CSn,
+            RDn		    => RDn,
+            WRn	        => WRn,
+            EOPn        => EOPn,
+            DACKn	    => DACKn,
+            DRQ		    => DRQ,
+            INT		    => INT,
+            READY       => READY,
+            DB_INn		=> DB_INn,
+            DB_OUTn		=> DB_OUTn,
+            DB_EN       => DB_EN,
+            DBP_INn     => DBP_INn,
+            DBP_OUTn    => DBP_OUTn,
+            DBP_EN      => DBP_EN,
+            RST_INn     => RST_INn,
+            RST_OUTn    => RST_OUTn,
+            RST_EN      => RST_EN,
+            BSY_INn     => BSY_INn,
+            BSY_OUTn    => BSY_OUTn,
+            BSY_EN      => BSY_EN,
+            SEL_INn     => SEL_INn,
+            SEL_OUTn    => SEL_OUTn,
+            SEL_EN      => SEL_EN,
+            ACK_INn     => ACK_INn,
+            ACK_OUTn    => ACK_OUTn,
+            ACK_EN      => ACK_EN,
+            ATN_INn     => ATN_INn,
+            ATN_OUTn    => ATN_OUTn,
+            ATN_EN      => ATN_EN,
+            REQ_INn     => REQ_INn,
+            REQ_OUTn    => REQ_OUTn,
+            REQ_EN      => REQ_EN,
+            IOn_IN      => IOn_IN,
+            IOn_OUT     => IOn_OUT,
+            IO_EN       => IO_EN,
+            CDn_IN      => CDn_IN,
+            CDn_OUT     => CDn_OUT,
+            CD_EN       => CD_EN,
+            MSG_INn     => MSG_INn,
+            MSG_OUTn    => MSG_OUTn,
+            MSG_EN      => MSG_EN
+        );
+end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
new file mode 100644
index 0000000..10a86f9
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
@@ -0,0 +1,253 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- Address mark detector file. This part detects the address    ----
+---- mark in the incoming data stream in FM and also in MFM mode  ----
+---- and provides therewith synchronisation information for the   ----
+---- control state machine and for the data separator in the      ----
+---- transceiver unit.                                            ----
+----                                                              ----
+------------------------------- Some theory -------------------------------------
+---- Frequency modulation FM:                                                ----
+---- The frequency modulation works as follows:                              ----
+---- 1. every first pulse of the clock and data line is a clock.             ----
+---- 2. every second pulse is a data.                                        ----
+---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ----
+---- 4. a logic 0 is represented by one clock pulse and no data pulse.       ----
+---- 5. Hence there are a maximum of two pulses per data bit.                ----
+---- 6. one clock and one data pulse come together in one bit cell.          ----
+---- 7. the duration of a bit cell in FM is 4 microseconds.                  ----
+---- 8. an ID address mark is represented as data FE with clock C7.          ----
+---- 9. a DATA address mark is represented as data FB with clock C7.         ----
+---- Examples:                                                               ----
+---- Binary data 1 1 0 0 1 0 1 1 is represented in FM as follows:            ----
+----            1111101011101111                                             ----
+---- the FE data           1 1 1 1 1 1 1 0 is represented as follows:        ----
+----                      1111111111111110                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101111110 this is the ID address mark.      ----
+---- the FB data           1 1 1 1 1 0 1 1 is represented as follows:        ----
+----                      1111111111101111                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101101111 this is the DATA address mark.    ----
+---- the F8 data           1 1 1 1 1 0 0 0 is represented as follows:        ----
+----                      1111111111101010                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101101010 this is the deleted DATA mark.    ----
+----                                                                         ----
+----                                                                         ----
+---- Modified frequency modulation MFM:                                      ----
+---- The modified frequency modulation works as follows:                     ----
+---- 1. every first pulse of the clock and data line is a clock.             ----
+---- 2. every second pulse is a data.                                        ----
+---- 3. a logic 1 is represented by no clock but a data pulse.               ----
+---- 4. a logic 0 is represented by a clock pulse and no data pulse if       ---- 
+---- following a 0.                                                          ----
+---- 5. a logic 0 is represented by no pulse if following a 1.               ----
+---- 6. Hence there are a maximum of one pulse per data bit.                 ----
+---- 7. one clock and one data pulse form together one bit cell.             ----
+---- 8. the duration of a bit cell in MFM is 2 microseconds.                 ----
+---- 9. an address mark sync is represented as data A1 with missing clock    ----
+---- pulse between bit 4 and 5.                                              ----
+---- Examples:                                                               ----
+---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows:        ----
+----               0101010101010100 this is the ID address mark.             ----
+---- Binary data FB 1 1 1 1 1 0 1 1 is represented in MFM as follows:        ----
+----               0101010101000101 this is the DATA address mark.           ----
+---- Binary data F8 1 1 1 1 1 0 0 0 is represented in MFM as follows:        ----
+----               0101010101001010 this is the deleted DATA address mark.   ----
+---- the A1 data           1 0 1 0 0 0 0 1 is represented as follows:        ----
+----                      0100010010101001                                   ----
+---- with the missing clock pulse between bits 4 and 5 there results:        ----
+---- results:             0100010010001001 this is the address mark sync.    ----
+----                                                                         ----
+---- Both MFM and FM are during read and write shifted with most significant ----
+---- bit (MSB) first. During the FM address marks are written without a      ----
+---- SYNC pulse the MFM coded data requires a synchronisation (A1 with       ----
+---- missing clock pulse because at the beginning of the data stream it is   ----
+---- not defined wether a clock pulse or a data pulse appears first. In FM   ----
+---- coding the first pulse is in any case a clock pulse.                    ----
+---------------------------------------------------------------------------------
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_AM_DETECTOR is
+	port(
+		-- System control
+		CLK				: in bit;
+		RESETn			: in bit;
+
+		-- Controls:
+		DDEn		    : in bit;
+		
+		-- Serial data and clock:
+		DATA			: in bit;
+		DATA_STRB		: in bit;
+
+		-- Address mark detector:
+		ID_AM		: out bit; -- ID address mark strobe.
+		DATA_AM		: out bit; -- Data address mark strobe.
+		DDATA_AM	: out bit -- Deleted data address mark strobe.
+	);
+end WF1772IP_AM_DETECTOR;
+
+architecture BEHAVIOR of WF1772IP_AM_DETECTOR is
+signal SHIFT		: bit_vector(15 downto 0);
+signal SYNC			: boolean;
+signal ID_AM_I		: bit;
+signal DATA_AM_I	: bit;
+signal DDATA_AM_I	: bit;
+begin
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				-- MSB first leads to a shift left operation.
+				SHIFT <= SHIFT(14 downto 0) & DATA;
+            elsif DDEn = '0' and SHIFT = "0100010010001001" then -- This is the synchronisation in MFM.
+				SHIFT <= (others => '0');
+			end if;
+		end if;
+	end process SHIFTREG;
+
+	MFM_SYNCLOCK: process(RESETn, CLK)
+	-- The SYNC pulse is generated in MFM mode only when the sync character
+	-- appears in the shift register (A1 sync mark, see file header).
+	-- After the sync character is detected, the sync time counter is loaded
+	-- with a value of 17. During counting the following 17 read clock pulses
+	-- down, the SYNC is true. After exactly 16 pulses the address mark is 
+	-- detected if the pattern in the shift register fits one of the address 
+	-- marks. The address mark pulses are valid for one read clock cycle until 
+	-- SYNC  goes low again. This mechanism is used to detect the correct address 
+	-- marks in the MFM data stream during the type III read track command. 
+	-- This is an improvement over the original WD1772 chip.
+	variable TMP : std_logic_vector(4 downto 0);
+	begin
+		if RESETn = '0' then
+			TMP := "00000";
+		elsif CLK = '1' and CLK' event then
+			if SHIFT = "0100010010001001" and DDEn = '0' then
+                TMP := "10001"; -- Load sync time counter.
+			elsif DATA_STRB = '1' and TMP > "00000" then
+				TMP := TMP - '1';
+			end if;
+		end if;
+		case TMP is
+			when "00000" => SYNC <= false;
+			when others => SYNC <= true;
+		end case;
+	end process MFM_SYNCLOCK;
+
+	-- The addressmark is nominally valid for one data pulse cycle (1us, 2us, 4us).
+	-- The pulse is shorter due to the fact that the detected address marks change the
+	-- state of the control state machine and so clear the address mark shift register...
+	ID_AM_I <=	 '1' when DDEn = '1' and SHIFT = "1111010101111110" else
+				 '1' when DDEn = '0' and SHIFT = "0101010101010100" and SYNC = true else '0';
+	DATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101111" else
+				 -- Normal data address mark...
+				 '1' when DDEn = '0' and SHIFT = "0101010101000101"  and SYNC = true else '0';
+	DDATA_AM_I <= 	'1' when DDEn = '1' and SHIFT = "1111010101101010" else
+					-- ... and deleted address mark in MFM mode:
+					'1' when DDEn = '0' and SHIFT = "0101010101001010"  and SYNC = true else '0';
+					
+	ADRMARK_STROBES: process(RESETn, CLK)
+	-- ... nevertheless The controller and the transceiver require ID address mark strobes 
+	-- and DATA address mark strobes. Therefore this process provides these strobe
+	-- signals independant of any 'feedbacks' like pulse shortening by the controller
+	-- state machine itself.
+	variable ID_AM_LOCK, DATA_AM_LOCK, DDATA_AM_LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			ID_AM_LOCK := false;
+			DATA_AM_LOCK := false;
+			ID_AM <= '0';
+			DATA_AM <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- ID address mark:
+			if ID_AM_I = '1' and ID_AM_LOCK = false then
+				ID_AM <= '1';
+				ID_AM_LOCK := true;
+			elsif ID_AM_I = '0' then
+				ID_AM <= '0';
+				ID_AM_LOCK := false;
+			else
+				ID_AM <= '0';
+			end if;
+			-- Data address mark:
+			if DATA_AM_I = '1' and DATA_AM_LOCK = false then
+				DATA_AM <= '1';
+				DATA_AM_LOCK := true;
+			elsif DATA_AM_I = '0' then
+				DATA_AM <= '0';
+				DATA_AM_LOCK := false;
+			else
+				DATA_AM <= '0';
+			end if;
+			-- Deleted data address mark:
+			if DDATA_AM_I = '1' and DDATA_AM_LOCK = false then
+				DDATA_AM <= '1';
+				DDATA_AM_LOCK := true;
+			elsif DDATA_AM_I = '0' then
+				DDATA_AM <= '0';
+				DDATA_AM_LOCK := false;
+			else
+				DDATA_AM <= '0';
+			end if;
+		end if;
+	end process ADRMARK_STROBES;
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
new file mode 100644
index 0000000..ce4c346
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
@@ -0,0 +1,1463 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is file the control unit providing all signals for the  ----
+---- data processing units like registers, addressmark detector,  ----
+---- data separator, CRC redundancy checker or transceiver.       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma
+--   Oksanen for the information.
+-- Revision 2K8A  2008/02/26 WF
+--   Fixed a bug in the 6ms delay. Thanks to Lyndon Amsdon.
+-- Revision 2K8B  2008/12/24 WF
+--   Bugfixes to avoid hanging state machine.
+--   Changed DELAY_30MS to DELAY_15MS, which is the correct value. Thanks to L. Amsdon for the information.
+--   Removed CRC_BUSY.
+--   Fixed a bug in the Delay for the state T2_VERIFY_AM.
+-- Revision 2K9A  2009/06/20 WF
+--   Fix to provide correct LOST_DATA_TR00 flag during seek command.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_CONTROL is
+	port(
+		-- System control:
+		CLK		: in bit;
+		RESETn	: in bit;
+
+		-- Chip control signals:
+		A1, A0	: in bit;
+		RWn		: in bit;
+		CSn		: in bit;
+		DDEn	: in bit;
+
+		-- Registers:
+		DR	: in bit_vector(7 downto 0); -- Data register.
+		CMD	: in std_logic_vector(7 downto 0); -- Command register.
+		DSR	: in std_logic_vector(7 downto 0); -- Shift register.
+		TR	: in std_logic_vector(7 downto 0); -- Track register.
+		SR	: in std_logic_vector(7 downto 0); -- Sector register.
+
+		-- Status flags:
+		MO				: buffer bit; -- Motor on status flag.
+		WR_PR			: out bit; -- Write protect status flag.
+		SPINUP_RECTYPE	: out bit; -- Spin up / record type status flag.
+        SEEK_RNF		: out bit; -- Seek error / record not found status flag.
+		CRC_ERRFLAG		: out bit; -- CRC status flag.
+		LOST_DATA_TR00	: out bit; -- Status flag indicates lost data or track 00 position.
+        DRQ				: out bit; -- Data request.
+		DRQ_IPn			: out bit; -- Data request status flag.
+		BUSY			: buffer bit; -- BUSY status flag.
+
+		-- Address mark detector controls:
+		AM_2_DISK	: out bit;	-- Enables / disables the address mark detector.
+		ID_AM		: in bit; 	-- Address mark of the ID field
+		DATA_AM		: in bit; 	-- Address mark of the data field
+		DDATA_AM	: in bit; 	-- Address mark of a deleted data field
+
+		-- CRC unit controls:
+		CRC_ERR		: in bit; 	-- CRC decoder's error.
+		CRC_PRES	: out bit;	-- Preset CRC during write operations.
+
+		-- Track register controls:
+		TR_PRES		: out bit;	-- Set x"FF".
+		TR_CLR		: out bit;	-- Clear.
+		TR_INC		: out bit;	-- Increment.
+		TR_DEC		: out bit;	-- Decrement.
+
+		-- Sector register control:
+		SR_LOAD		: out bit; -- Load.
+		SR_INC		: out bit; -- Increment.
+		-- The TRACK_NR is required during the type III command
+		--  'Read Address'. TRACK_NR is the content of the TRACKMEM.
+		TRACK_NR	: out std_logic_vector(7 downto 0);
+
+		-- DATA register control:
+		DR_CLR		: out bit; -- Clear.
+		DR_LOAD		: out bit; -- LOAD.
+
+		-- Shift register control:
+		SHFT_LOAD_ND	: out bit; -- Load normal data.
+		SHFT_LOAD_SD	: out bit; -- Load special data.
+
+		-- Transceiver controls:
+		CRC_2_DISK	: out bit;	-- Cause the Transceiver to write out CRC data.
+		DSR_2_DISK	: out bit;	-- Cause the Transceiver to write normal data.
+		FF_2_DISK	: out bit;	-- Cause the Transceiver to write x"FF" bytes.
+		PRECOMP_EN	: out bit; 	-- Enables the write precompensation.
+
+		-- Miscellaneous Controls:
+		DATA_STRB 	: in bit;	-- Data strobe (read and write operation)
+		WPRTn		: in bit; 	-- Write protect flag
+		IPn			: in bit; 	-- Index pulse flag
+		TRACK00n	: in bit; 	-- Track zero flag
+		DISK_RWn	: out bit;  -- This signal reflects the data direction.
+		DIRC		: out bit;	-- Step direction control.
+		STEP		: out bit;	-- Step pulse.
+		WG			: out bit;	-- Write gate control.
+		INTRQ		: out bit 	-- Interrupt request flag.
+	);
+end WF1772IP_CONTROL;
+
+architecture BEHAVIOR of WF1772IP_CONTROL is
+-- The control state machine for the three command types I, II and III 
+-- (10 commands) has 73 states:
+type CMD_STATES is(	IDLE, INIT, SPINUP, DELAY_15MS, DECODE, T1_SEEK_RESTORE, T1_STEPPING, 
+					T1_LOAD_SHFT, T1_COMP_TR_DSR, T1_CHECK_DIR, T1_HEAD_CTRL, T1_STEP, T1_TRAP, T1_STEP_DELAY,
+					T1_SPINDOWN, T1_SCAN_TRACK, T1_SCAN_CRC, T1_VERIFY_DELAY, T1_VERIFY_CRC, T2_RD_WR_SECT, 
+					T2_INIT, T2_SCAN_TRACK, T2_SCAN_SECT, T2_SCAN_LEN, T2_VERIFY_CRC_1, T2_VERIFY_AM, T2_FIRSTBYTE, 
+					T2_LOAD_DATA, T2_NEXTBYTE, T2_VERIFY_DRQ_1, T2_RDSTAT, T2_VERIFY_CRC_2, 
+					T2_MULTISECT, T2_DELAY_B2, T2_SET_DRQ, T2_DELAY_B8, T2_VERIFY_DRQ_2, 
+					T2_DELAY_B1, T2_CHECK_MODE, T2_DELAY_B11, T2_WR_LEADIN, T2_WR_AM, 
+					T2_LOAD_SHFT, T2_WR_BYTE, T2_VERIFY_DRQ_3, T2_DATALOST, T2_WRSTAT, T2_WR_CRC, 
+					T2_WR_FF, T3_WR, T3_DELAY_B3, T3_VERIFY_DRQ, T3_CHECK_INDEX_1, T3_LOAD_SHFT, 
+					T3_WR_DATA, T3_CHECK_INDEX_2, T3_DATALOST, T3_RD_TRACK, T3_SHIFT, 
+					T3_CHECK_INDEX_3, T3_DETECT_AM, T3_CHECK_BYTE, T3_CHECK_DR, T3_LOAD_DATA_1, 
+					T3_SET_DRQ_1, T3_RD_ADR, T3_VERIFY_AM, T3_SHIFT_ADR, T3_LOAD_DATA_2, 
+					T3_SET_DRQ_2, T3_CHECK_RD, T3_LOAD_SR, T3_VERIFY_CRC);
+signal CMD_STATE		: CMD_STATES;
+signal NEXT_CMD_STATE	: CMD_STATES;
+signal DATA_WR			: boolean;
+signal DATA_RD			: boolean;
+signal CMD_WR			: boolean;
+signal STAT_RD			: boolean;
+signal DELAY			: boolean;
+signal DRQ_I            : bit;
+signal INDEX_CNT		: boolean;
+signal DIR				: bit;
+signal INDEX_MARK		: bit;
+signal STEP_TRAP		: boolean;
+signal TYPE_IV_BREAK	: boolean;
+signal BYTE_RDY			: boolean;
+signal SECT_LEN 		: std_logic_vector(10 downto 0);
+signal TRACKMEM			: std_logic_vector(7 downto 0);
+signal T3_TRADR			: boolean;
+signal T3_DATATYPE		: bit_vector(7 downto 0);
+begin
+	-- The Forced interrupt stops any command at the end of an internal micro instruction.
+	-- Forced interrupt waits until ALU operations in progress are complete (CRC calculations,
+	-- compares etc.). the TYPE_IV_BREAK controls this behavior.
+    TYPE_IV_BREAK <= true when CMD(7 downto 4) = x"D" and DELAY = true else false;
+
+	CMD_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			CMD_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if TYPE_IV_BREAK = true then
+				CMD_STATE <= IDLE; -- Forced interrupt break.
+			else
+				CMD_STATE <= NEXT_CMD_STATE; -- Normal operation.
+			end if;
+		end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, CMD, DSR, TR, SR, INDEX_CNT, IPn, INDEX_MARK, DELAY, DIR, MO, CMD_WR, DRQ_I, 
+						 DDEn, CRC_ERR, TRACK00n, STEP_TRAP, ID_AM, DATA_AM, DDATA_AM, WPRTn, SECT_LEN, BYTE_RDY,
+						 T3_TRADR)
+	begin
+		case CMD_STATE is
+			--------------------------------------------------------------------
+			------------------ type1, -2, -3 command stuff ---------------------
+			--------------------------------------------------------------------
+			when IDLE =>
+				-- The write access to the command register indicates a new command.
+				-- Any command received (type1, -2 or -3 but not type4):
+				if CMD_WR = true and CMD /= x"FF" and CMD(7 downto 4) /= "1101" then
+					NEXT_CMD_STATE <= INIT;
+				else
+					NEXT_CMD_STATE <= IDLE; -- No CMD detected.
+				end if;
+			when INIT =>
+				-- The process goes on when the CMD_WR flag is released.
+				if CMD_WR = false and CMD(3) = '0' and MO = '0' then
+					-- Do not enter the SPINUP sequence 
+					-- when the motor is already on (MO = '1').
+					NEXT_CMD_STATE <= SPINUP;
+				elsif CMD_WR = false then
+					-- Proceed with the DELAY_15MS when the motor was
+					-- already on or when the SPINUP sequence is
+					-- disabled (CMD(3) = '1').
+					NEXT_CMD_STATE <= DELAY_15MS;
+				else
+					NEXT_CMD_STATE <= INIT;
+				end if;
+			when SPINUP =>
+				if INDEX_CNT = true then -- proceed after 6 revolutions
+					NEXT_CMD_STATE <= DELAY_15MS;
+				else
+					NEXT_CMD_STATE <= SPINUP;
+				end if;
+			when DELAY_15MS =>
+				if CMD(7) = '0' then -- No delay for type1 commands.
+					NEXT_CMD_STATE <= DECODE;
+				elsif CMD(7) = '1' and CMD(2) = '0' then -- Delay for type2 and -3 disabled.
+					NEXT_CMD_STATE <= DECODE;
+				elsif CMD(7) = '1' and CMD(2) = '1' and DELAY = true then -- Delay enabled by CMD(2).
+					NEXT_CMD_STATE <= DECODE;
+				else
+					NEXT_CMD_STATE <= DELAY_15MS;
+				end if;
+			when DECODE =>
+				case CMD(7 downto 5) is 
+					when "000" => -- 'restore', 'seek'.
+						NEXT_CMD_STATE <= T1_SEEK_RESTORE;
+					when "001" |"010" | "011" => -- 'step', 'step in', 'step out'.
+						NEXT_CMD_STATE <= T1_STEPPING;
+					when "100" | "101" => -- 'read sector', 'write sector'
+						NEXT_CMD_STATE <= T2_RD_WR_SECT;
+					when "110" => -- 'read address'.
+						-- "110" is also used by the 'force interrupt'.
+						-- There will result no wrong encoding because
+						-- the 'force intterrupt' is predecoded in IDLE.
+						NEXT_CMD_STATE <= T3_RD_ADR;
+					when "111" => -- 'read track', 'write track'.
+						case CMD(4) is
+							when '0' =>	NEXT_CMD_STATE <= T3_RD_TRACK;
+							when '1' => NEXT_CMD_STATE <= T3_WR;
+							when others => NEXT_CMD_STATE <= T3_WR; -- Dummy for U, X, Z, W, H, L, -.
+						end case;
+					when others => 
+						-- The following NEXT_CMD_STATE is chosen to compile fine with
+						-- the Xilinx ISE not to produce a latch.
+						NEXT_CMD_STATE <= IDLE; -- Never true due to IDLE preselection.
+				end case;
+			--------------------------------------------------------------------
+			------------------ special type1 command stuff ---------------------
+			--------------------------------------------------------------------
+			when T1_SEEK_RESTORE =>
+				-- In this state, the data register and the track register are updated, if the
+				-- command is a RESTORE. The update is done further down with the track register
+				-- and the data register controls.
+				NEXT_CMD_STATE <= T1_LOAD_SHFT;
+			when T1_STEPPING =>
+				if CMD(4) = '1' then -- '1' means update track register.
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				else
+					NEXT_CMD_STATE <= T1_HEAD_CTRL;
+				end if;
+			when T1_LOAD_SHFT =>
+				NEXT_CMD_STATE <= T1_COMP_TR_DSR;
+			when T1_COMP_TR_DSR =>
+				if DSR = TR then
+					NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+				else
+					-- The direction control is done further down.
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				end if;
+			when T1_CHECK_DIR =>
+				-- Track register modifications are done in
+				-- statements further down.
+				-- The delay is to provide the timing of the WD1772 which is DIR to step =
+				-- 24us in MFM mode and 48us in FM mode.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T1_HEAD_CTRL;
+				else
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				end if;
+			when T1_HEAD_CTRL =>
+				if TRACK00n = '0' and DIR = '0' then
+					NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+				else
+					NEXT_CMD_STATE <= T1_STEP;
+				end if;
+			when T1_STEP =>
+				NEXT_CMD_STATE <= T1_TRAP;
+			when T1_TRAP =>
+				if STEP_TRAP = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to seek error.
+				else
+					NEXT_CMD_STATE <= T1_STEP_DELAY;
+				end if;
+			when T1_STEP_DELAY =>
+				-- The delay in here is according to the CMD(1 downto 0) as follows:
+				-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.				
+				if DELAY = true then
+					case CMD(7 downto 5) is
+						when "001" | "010" | "011" => -- STEP - STEP IN - STEP OUT.
+							NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+						when others => -- Seek or restore command.
+							NEXT_CMD_STATE <= T1_LOAD_SHFT;
+					end case;
+				else
+					NEXT_CMD_STATE <= T1_STEP_DELAY;
+				end if;
+			when T1_VERIFY_DELAY =>
+				if CMD(2) = '0' then -- No verify.
+					NEXT_CMD_STATE <= IDLE;
+				else
+					if DELAY = true then -- Wait, if verify is active.
+						NEXT_CMD_STATE <= T1_SPINDOWN;
+					else
+						NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+					end if;
+				end if;
+			when T1_SPINDOWN => -- Detect ID address mark in here.
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				elsif ID_AM = '1' then -- Addressmark found.
+					NEXT_CMD_STATE <= T1_SCAN_TRACK;
+				else
+					NEXT_CMD_STATE <= T1_SPINDOWN;
+				end if;
+			when T1_SCAN_TRACK =>
+				if DELAY = true then
+					-- Track found if shift register (DSR) equals track register (TR).
+					if DSR = TR then
+						NEXT_CMD_STATE <= T1_SCAN_CRC;
+					else
+						NEXT_CMD_STATE <= T1_SPINDOWN;
+					end if;
+				else
+					NEXT_CMD_STATE <= T1_SCAN_TRACK;
+				end if;
+			when T1_SCAN_CRC =>
+				-- Scan the rest of the data header for correct CRC generation (3 Bytes).
+				-- Sector number side select byte and data length byte.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T1_VERIFY_CRC;
+				else
+					NEXT_CMD_STATE <= T1_SCAN_CRC;
+				end if;
+			when T1_VERIFY_CRC =>
+                -- The CRC logic starts during T1_SPINDOWN (missing clock transitions).
+                if DELAY = true then
+                    if CRC_ERR = '1' then
+                        NEXT_CMD_STATE <= T1_SPINDOWN; -- CRC error.
+                    else
+                        NEXT_CMD_STATE <= IDLE; -- Operation finished.
+                    end if;		
+                else
+                    NEXT_CMD_STATE <= T1_VERIFY_CRC; -- Wait until CRC logic is ready.
+                end if;
+			--------------------------------------------------------------------
+			------------------ special type2 command stuff ---------------------
+			--------------------------------------------------------------------
+			when T2_RD_WR_SECT =>
+				if CMD(7 downto 5) = "101" and WPRTn = '0' then
+					NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk.
+				else
+					NEXT_CMD_STATE <= T2_INIT;
+				end if;
+			when T2_INIT =>
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				elsif ID_AM = '0' then
+					NEXT_CMD_STATE <= T2_INIT; -- Wait for address mark.
+				else -- INDEX_CNT = false and ID_AM = '1' -> ID address mark detected
+					NEXT_CMD_STATE <= T2_SCAN_TRACK;
+				end if;
+			when T2_SCAN_TRACK =>
+				-- Track found if shift register (DSR) equals track register (TR).
+				if DELAY = true then
+					if DSR = TR then
+						NEXT_CMD_STATE <= T2_SCAN_SECT;
+					else
+						NEXT_CMD_STATE <= T2_INIT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_TRACK;
+				end if;
+			when T2_SCAN_SECT =>
+				-- Sector found if shift register (DSR) equals sector register (SR).
+				if DELAY = true then
+					if DSR = SR then
+						NEXT_CMD_STATE <= T2_SCAN_LEN;
+					else
+						NEXT_CMD_STATE <= T2_INIT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_SECT;
+				end if;
+			when T2_SCAN_LEN =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_1;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_LEN;
+				end if;
+			when T2_VERIFY_CRC_1 =>
+				-- The CRC logic starts after T2_INIT (missing clock transitions).
+				if DELAY = true then
+					if CRC_ERR = '1' then
+						NEXT_CMD_STATE <= T2_INIT; -- CRC error.
+					elsif CRC_ERR = '0' and CMD(7 downto 5) = "101" then
+						NEXT_CMD_STATE <= T2_DELAY_B2; -- Comand is a write.
+					else -- Command is a read.
+						NEXT_CMD_STATE <= T2_VERIFY_AM;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_1; -- Wait until CRC logic is ready.
+				end if;
+			when T2_VERIFY_AM =>
+				if DATA_AM = '1' or DDATA_AM = '1' then -- Data address mark detected, go on.
+					NEXT_CMD_STATE <= T2_FIRSTBYTE;
+				elsif DELAY = false then -- Stay in this state.
+					NEXT_CMD_STATE <= T2_VERIFY_AM;
+				else
+					NEXT_CMD_STATE <= T2_INIT; -- No addressmark detected.
+				end if;
+			when T2_FIRSTBYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_LOAD_DATA;
+				else
+					NEXT_CMD_STATE <= T2_FIRSTBYTE;
+				end if;
+			when T2_LOAD_DATA =>
+				NEXT_CMD_STATE <= T2_NEXTBYTE;
+			when T2_NEXTBYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_1;
+				else
+					NEXT_CMD_STATE <= T2_NEXTBYTE;
+				end if;
+			when T2_VERIFY_DRQ_1 =>
+				NEXT_CMD_STATE <= T2_RDSTAT;
+			when T2_RDSTAT =>
+				if SECT_LEN = "00000000000" then
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_2;
+				else
+					NEXT_CMD_STATE <= T2_LOAD_DATA;
+				end if;
+			when T2_VERIFY_CRC_2 =>
+				-- The CRC logic starts after T2_VERIFY_AM (missing clock transitions).
+				if DELAY = true then
+					if CRC_ERR = '1' then
+						NEXT_CMD_STATE <= IDLE; -- Break due to CRC error.
+					else
+						NEXT_CMD_STATE <= T2_MULTISECT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_2; -- Wait until CRC logic is ready.
+				end if;
+			when T2_MULTISECT =>
+				if  CMD(4) = '1' then
+					NEXT_CMD_STATE <= T2_RD_WR_SECT;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Operation finished.
+				end if;
+			when T2_DELAY_B2 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_SET_DRQ;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B2;
+				end if;
+			when T2_SET_DRQ =>
+				NEXT_CMD_STATE <= T2_DELAY_B8;
+			when T2_DELAY_B8 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_2;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B8;
+				end if;
+			when T2_VERIFY_DRQ_2 =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T2_DELAY_B1;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host).
+				end if;
+			when T2_DELAY_B1 => 
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_CHECK_MODE;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B1;
+				end if;
+			when T2_CHECK_MODE =>
+				if DDEn = '1' then -- FM mode
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B11;
+				end if;
+			when T2_DELAY_B11 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B11;
+				end if;
+			when T2_WR_LEADIN =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_AM;
+				else
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				end if;
+			when T2_WR_AM => -- Write data address mark.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_LOAD_SHFT;
+				else
+					NEXT_CMD_STATE <= T2_WR_AM;
+				end if;
+			when T2_LOAD_SHFT =>
+					NEXT_CMD_STATE <= T2_WR_BYTE;
+			when T2_WR_BYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_3;
+				else
+					NEXT_CMD_STATE <= T2_WR_BYTE;
+				end if;
+			when T2_VERIFY_DRQ_3 =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T2_WRSTAT;
+				else
+					NEXT_CMD_STATE <= T2_DATALOST;
+				end if;
+			when T2_DATALOST =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WRSTAT;
+				else
+					NEXT_CMD_STATE <= T2_DATALOST;
+				end if;
+			when T2_WRSTAT =>
+				if SECT_LEN = "00000000000" then
+					NEXT_CMD_STATE <= T2_WR_CRC; -- Write operation finished.
+				else
+					NEXT_CMD_STATE <= T2_LOAD_SHFT;
+				end if;
+			when T2_WR_CRC =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_FF;
+				else
+					NEXT_CMD_STATE <= T2_WR_CRC;
+				end if;
+			when T2_WR_FF =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_MULTISECT;
+				else
+					NEXT_CMD_STATE <= T2_WR_FF;
+				end if;
+			--------------------------------------------------------------------
+			---------------- type3 write track command stuff -------------------
+			--------------------------------------------------------------------
+			when T3_WR =>
+				if WPRTn = '0' then
+					NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk.
+				else
+					NEXT_CMD_STATE <= T3_DELAY_B3;
+				end if;
+			when T3_DELAY_B3 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_VERIFY_DRQ;
+				else
+					NEXT_CMD_STATE <= T3_DELAY_B3;
+				end if;
+			when T3_VERIFY_DRQ =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_1;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host).
+				end if;				
+			when T3_CHECK_INDEX_1 =>
+				if IPn = '0' then
+					NEXT_CMD_STATE <= T3_LOAD_SHFT;
+				else
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_1;
+				end if;				
+			when T3_LOAD_SHFT =>
+				NEXT_CMD_STATE <= T3_WR_DATA;
+			when T3_WR_DATA =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_2;
+				else
+					NEXT_CMD_STATE <= T3_WR_DATA;
+				end if;
+			when T3_CHECK_INDEX_2 =>
+				if INDEX_MARK = '1' then
+					NEXT_CMD_STATE <= IDLE; -- End of track reached.
+				elsif DRQ_I = '0' then -- New data has been loaded.
+					NEXT_CMD_STATE <= T3_LOAD_SHFT; -- Fetch new data.
+				else
+					NEXT_CMD_STATE <= T3_DATALOST; -- Fill in nullbyte.
+				end if;
+			when T3_DATALOST =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_2;
+				else
+					NEXT_CMD_STATE <= T3_DATALOST;
+				end if;
+			--------------------------------------------------------------------
+			--------------- type3 read track command stuff --------------------
+			--------------------------------------------------------------------
+			when T3_RD_TRACK =>
+				-- wait for index pulse:
+				if IPn = '0' then
+					NEXT_CMD_STATE <= T3_SHIFT;
+				else
+					NEXT_CMD_STATE <= T3_RD_TRACK;
+				end if;
+			when T3_SHIFT =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_3;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT;
+				end if;
+			when T3_CHECK_INDEX_3 =>
+				if INDEX_MARK = '1' then
+					NEXT_CMD_STATE <= IDLE; -- End of track reached.
+				else
+					NEXT_CMD_STATE <= T3_DETECT_AM;
+				end if;
+			when T3_DETECT_AM => -- Detect for ID address mark.
+				if ID_AM = '1' then
+					NEXT_CMD_STATE <= T3_CHECK_DR;
+				else
+					NEXT_CMD_STATE <= T3_CHECK_BYTE;
+				end if;
+			when T3_CHECK_BYTE =>
+				if BYTE_RDY = true then
+					NEXT_CMD_STATE <= T3_CHECK_DR;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT;
+				end if;
+			when T3_CHECK_DR =>
+				NEXT_CMD_STATE <= T3_LOAD_DATA_1;
+			when T3_LOAD_DATA_1 =>
+				NEXT_CMD_STATE <= T3_SET_DRQ_1;
+			when T3_SET_DRQ_1 =>
+				NEXT_CMD_STATE <= T3_SHIFT;
+			--------------------------------------------------------------------
+			---------------- type3 read address command stuff ------------------
+			--------------------------------------------------------------------
+			when T3_RD_ADR =>
+				-- check for 6 index holes
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				else
+					NEXT_CMD_STATE <= T3_VERIFY_AM;
+				end if;
+			when T3_VERIFY_AM => -- Check for existing ID address mark
+				if ID_AM = '1' then
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				else
+					NEXT_CMD_STATE <= T3_RD_ADR;
+				end if;
+			when T3_SHIFT_ADR =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_LOAD_DATA_2;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				end if;
+			when T3_LOAD_DATA_2 =>
+				NEXT_CMD_STATE <= T3_SET_DRQ_2;
+			when T3_SET_DRQ_2 =>
+				NEXT_CMD_STATE <= T3_CHECK_RD;
+			when T3_CHECK_RD =>
+				if T3_TRADR = true then
+					NEXT_CMD_STATE <= T3_LOAD_SR;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				end if;
+			when T3_LOAD_SR =>
+				NEXT_CMD_STATE <= T3_VERIFY_CRC;
+			when T3_VERIFY_CRC =>
+				-- The CRC logic starts during T3_VERIFY_AM (missing clock transitions).
+				if DELAY = true then
+					NEXT_CMD_STATE <= IDLE; -- Operation finished (with or without CRC error).
+				else
+					NEXT_CMD_STATE <= T3_VERIFY_CRC; -- Wait until CRC logic is ready.
+				end if;
+		end case;
+	end process CMD_DECODER;
+
+	P_DELAY: process(RESETn, CLK, CMD_STATE, T3_DATATYPE, DDEn, CMD)
+	-- This process is responsible to control the DELAY signal in the different command
+	-- states of the main state machine. These states finish, if the signal DELAY is
+	-- asserted. The condition for asserted DELAY is the correct number of data strobes
+	-- which are supervised by the DATA_STRB inputs.
+	-- Another condition is a time delay required in the following states:
+	-- In DELAY_15MS there is a delay of 30ms.
+	-- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows: 
+	-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.
+	-- In T1_VERIFY_DELAY there is a delay of 30ms.
+	variable DELCNT : std_logic_vector(19 downto 0);
+	begin
+		if RESETn = '0' then
+			DELCNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			-- Reset the delay right after it occurs:
+			if DELAY = true then
+				DELCNT := (others => '0');
+			elsif DATA_AM = '1' or DDATA_AM = '1' then -- Reset in command state T2_VERIFY_AM.
+				DELCNT := (others => '0');
+			else
+				case CMD_STATE is
+					-- Time delays work on CLK edges.
+					when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY =>
+						DELCNT := DELCNT + '1';
+					-- Bit count delays work on data strobes.
+					-- Read from disk operation:
+                    when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT |
+						 T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM  | T2_FIRSTBYTE |
+						 T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC =>
+						if DATA_STRB = '1' then
+							DELCNT := DELCNT + '1';
+						end if;
+					-- Write to disk operation:
+					when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN |
+						 T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST |
+						 T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST   =>
+						if DATA_STRB = '1' then
+							DELCNT := DELCNT + '1';
+						end if;
+					when others =>
+						DELCNT := (others => '0'); -- Clear the delay counter if not used.
+				end case;
+			end if;
+		end if;
+
+		case CMD_STATE is
+			when DELAY_15MS | T1_VERIFY_DELAY =>
+				case DELCNT is
+                    --when x"75300" => DELAY <= true; -- 30ms
+                    when x"3A980" => DELAY <= true; -- 15ms, thanks to L. Amsdon.
+					when others => DELAY <= false;
+				end case;
+			when T1_CHECK_DIR =>
+				if DDEn = '1' and DELCNT = x"00300" then -- 48us in FM
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00180" then -- 24us in MFM.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T1_STEP_DELAY =>
+				if CMD(1 downto 0) = "11" and DELCNT >= x"0BB80" then -- 3ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "10" and DELCNT >= x"07D00" then -- 2ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "01" and DELCNT >= x"2EE00"  then -- 12ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "00" and DELCNT >= x"17700" then -- 6ms
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;			
+			when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE |
+							T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR =>
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times.
+					when others => DELAY <= false;
+				end case;
+			when T1_SCAN_CRC =>
+				case DELCNT is
+                    when x"00018" => DELAY <= true; -- Scan for 3 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_WR_AM =>
+				if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode).
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode).
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T2_VERIFY_AM =>
+                if DDEn = '1' and DELCNT >= x"00148" then -- FM mode.
+					DELAY <= true; -- (11+6+1)+1 = 19 Byte Times, plus 10 Byte times uncertainty.
+                elsif DDEn = '0' and DELCNT >= x"00188" then -- MFM mode.
+					DELAY <= true; -- (22+12+3+1)+1 = 39 Byte Times, plus 10 Byte times uncertainty.
+				else
+					DELAY <= false;
+				end if;
+			when T2_WR_LEADIN =>
+				if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode.
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T2_DELAY_B1 =>
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- Delay is 1 byte.
+					when others => DELAY <= false;
+				end case;
+			when T3_DELAY_B3 =>
+				case DELCNT is
+					when x"00018" => DELAY <= true; -- Delay is 3 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_DELAY_B8 =>
+				case DELCNT is
+					when x"00040" => DELAY <= true; -- Delay is 8 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_DELAY_B11 =>
+				case DELCNT is
+					when x"00058" => DELAY <= true; -- Delay is 11 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_VERIFY_CRC_2 =>
+				-- In this state the original WD1772 state machine causes the CRC data to appear 1 byte
+				-- too early. The reason is the construction of the states T2_LOAD_DATA and T2_NEXTBYTE
+				-- where the length counter and the DRQ flag are serviced in T2_LOAD_DATA. Therefore the
+				-- delay is only 1 byte instead of 2.
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- Scan for 2 bytes but wait only 1 byte.
+					when others => DELAY <= false;
+				end case;
+            when T1_VERIFY_CRC | T2_SCAN_SECT | T2_VERIFY_CRC_1 | T2_DELAY_B2 | T2_WR_CRC | T3_VERIFY_CRC =>
+				case DELCNT is
+            when x"00010" => DELAY <= true; -- Scan for 2 bytes (e. g. side and sector in T2_SCAN_SECT).
+					when others => DELAY <= false;
+				end case;
+			when T3_WR_DATA =>
+				if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits.
+					DELAY <= true;
+				elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T3_SHIFT =>
+				case DELCNT is
+					when x"00001" => DELAY <= true; -- Scan just one data bit.
+					when others => DELAY <= false;
+				end case;
+			when others =>
+				DELAY <= false;
+			end case;
+	end process P_DELAY;
+
+	INDEX_COUNTER: process(RESETn, CLK, CMD_STATE)
+	-- This process is intended to control some command states via the index pulse behavior.
+	-- In the original WD177x there is foreseen a delay of several index pulses (about 1s). 
+	-- It is achieved by counting the index pulses of the disk. This encounters problems, 
+	-- if the disk is not inserted. For this reason there is additionally to the index counter 
+	-- a timeout which is active if there are no index pulses.
+	variable CNT : std_logic_vector(3 downto 0);
+	variable TIMEOUT : std_logic_vector(27 downto 0);
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			CNT := x"0";
+			TIMEOUT := (others => '0');
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				-- Be aware that there must sometimes checked several states for the presence of IPn!
+                when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC |
+                              T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM =>
+					if IPn = '0' and LOCK = false then -- Count the index pulses.
+						CNT := CNT + '1';
+						LOCK := true;
+					elsif IPn = '1' then
+						LOCK := false;
+					end if;
+					--
+					if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s.
+						TIMEOUT := TIMEOUT + '1';
+					end if;
+				when others =>
+					CNT := x"0";
+					TIMEOUT := (others => '0');
+			end case;
+		end if;
+		--
+		if CMD_STATE = SPINUP and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T1_SPINDOWN and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T2_INIT and (CNT = "101" or TIMEOUT = x"17FFFFF") then -- 5 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T3_RD_ADR and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		else
+			INDEX_CNT <= false;
+		end if;
+	end process INDEX_COUNTER;
+
+	P_INDEX_MARK: process
+	-- This process controls the occurence of an index pulse during read track
+	-- and write track commands. The flag INDEX_MARK is cleared at the
+	-- beginning of these two commands during the first check for an index
+	-- pulse and is set right after the next index pulse occurs, which means
+	-- track processing has completed.
+	variable LOCK: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CMD_STATE = T3_RD_TRACK and IPn = '0' then
+			INDEX_MARK <= '0'; -- Reset the flag.
+			LOCK := true;
+		elsif CMD_STATE = T3_CHECK_INDEX_1 and IPn = '0' then
+			INDEX_MARK <= '0'; -- Reset the flag.
+			LOCK := true;
+		elsif IPn = '0' and LOCK = false then
+			INDEX_MARK <= '1'; -- Index pulse has passed.
+			LOCK := true;
+		elsif IPn = '1' then
+			LOCK := false;
+		end if;
+	end process P_INDEX_MARK;
+	
+	P_T3_DATATYPE: process(RESETn, CLK)
+	-- In type 3 write track command, it is necessary to store the information, which data
+	-- has to be written to disk (in command state T3_WR_DATA. This information is sampled
+	-- in the command state T3_LOAD_SHFT which preceeds the command state T3_WR_DATA.
+	begin
+		if RESETn = '0' then
+			T3_DATATYPE <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = T3_LOAD_SHFT then
+				T3_DATATYPE <= DR;
+			end if;
+		end if;
+	end process P_T3_DATATYPE;
+	
+	CNT_T3BYTES: process(RESETn, CLK, CMD_STATE)
+	-- This process counts the bytes read in the type III read address
+	-- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2,
+	-- T3_SET_DRQ_2 and T3_CHECK_RD.
+	variable CNT 	: std_logic_vector(2 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := "000";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T3_VERIFY_AM =>
+					CNT := "000"; -- Clear the counter right befor the count operation.
+				when T3_SET_DRQ_2 =>
+					CNT := CNT + '1'; -- Increment after each read cycle.
+				when others =>
+					null;
+			end case;
+		end if;
+		case CNT is
+			when "100" => T3_TRADR <= true;
+			when others => T3_TRADR <= false;
+		end case;
+	end process CNT_T3BYTES;
+
+	BYTEASMBLY: process(RESETn, CLK)
+	-- This process controls the condition in the CMD_STATE T3_CHECK_DR.
+	-- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted.
+	-- The count condition is entering the command state T3_CHECK_INDEX_3. The clear
+	-- condition is either the command state IDLE or the command state T3_CHECK_DR.
+	variable CNT : std_logic_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := x"0";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when IDLE => CNT := x"0";
+				when T3_CHECK_INDEX_3 => CNT := CNT + '1';
+				when T3_CHECK_DR => CNT := (others => '0');
+				when others => null;
+			end case;
+		end if;
+		case CNT is
+			when x"8" => BYTE_RDY <= true;
+			when others => BYTE_RDY <= false;
+		end case;
+	end process BYTEASMBLY;
+
+	P_DIR: process(RESETn, CLK, DIR)
+	-- This portion of code is responsible to control the right stepping
+	-- direction in type I commands.
+	begin
+		if RESETn = '0' then
+			DIR <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = DECODE and CMD(7 downto 5) = "010" then -- Step in.
+				DIR <= '1';
+			elsif CMD_STATE = DECODE and CMD(7 downto 5) = "011" then -- Step out.
+				DIR <= '0';
+			elsif CMD_STATE = T1_COMP_TR_DSR and DSR > TR then -- Seek.
+				DIR <= '1';
+			elsif CMD_STATE = T1_COMP_TR_DSR and DSR < TR then -- Seek.
+				DIR <= '0';
+			end if;
+		end if;
+		DIRC <= DIR; -- Copy signal to the output.
+	end process P_DIR;
+
+	P_DRQ: process(RESETn, CLK, DRQ_I)
+	begin
+		if RESETn = '0' then
+			DRQ_I <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when INIT =>
+					DRQ_I <= '0';
+				when T2_LOAD_DATA | T2_SET_DRQ | T2_LOAD_SHFT =>
+					DRQ_I <= '1';
+				when T3_WR | T3_LOAD_SHFT | T3_SET_DRQ_1 | T3_SET_DRQ_2 =>
+					DRQ_I <= '1';
+				when others =>
+					null;
+			end case;
+			-- The data request bit is also cleared by reading or writing the
+			-- data register (direct memory access operation).
+			if (DATA_RD = true or DATA_WR = true) then
+				DRQ_I <= '0';
+			end if;
+		end if;
+		--
+        DRQ <= DRQ_I; -- Copy to entity.
+		--
+	end process P_DRQ;
+
+	-- The DRQ_IPn detects the index pulse during type I commands and a forced interrupt or 
+	-- DRQ during type II and III commands.
+	-- The index pulse flag is active high and can be used for the detection of an inserted disk.
+	DRQ_IPn <=  not IPn when CMD(7) = '0' else
+				not IPn when CMD(7 downto 4) = x"D" and BUSY = '0' else DRQ_I;
+
+	P_BUSY: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			BUSY <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- During forced interrupt, the busy flag is reset when the command
+			-- state machine enters the IDLE state.
+			if CMD_STATE = INIT then
+				BUSY <= '1'; -- set BUSY flag for all command types I ... III.
+			elsif CMD_STATE = IDLE then
+				BUSY <= '0'; -- Reset BUSY after entering IDLE in any case.
+			end if;
+		end if;
+	end process P_BUSY;
+
+	P_SEEK_RNF: process(RESETn, CLK)
+	-- Seek error or record not found error flag.
+	begin
+		if RESETn = '0' then
+			SEEK_RNF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT then
+				SEEK_RNF <= '0'; -- Clear the flag for all command types I ... III.
+			elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then
+				SEEK_RNF <= '1'; -- Seek error (SEEK).
+			elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Seek error (SEEK).
+			elsif CMD_STATE = T2_INIT and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Record not found (RNF).
+			elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Record not found (RNF).
+			end if;
+		end if;
+	end process P_SEEK_RNF;
+
+	P_INTRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INTRQ <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- Interrupt reset conditions:
+			if STAT_RD = true and CMD /= x"D8" then
+				-- No clear during immediately forced interrupt.
+				INTRQ <= '0'; -- Clear the flag when status register is read.
+			elsif CMD_WR = true and CMD = x"D0" then
+				-- Clear with the next write access to the command register after the
+				-- forced interrupt x"D0" was written.
+				INTRQ <= '0';
+			elsif CMD_STATE = INIT and CMD(7 downto 6) /= "11" then
+				INTRQ <= '0'; -- Clear the flag for type I and type II commands during start of execution.
+            -- Interrupt set conditions.
+			elsif CMD = x"D8" and CMD_STATE = IDLE then
+				INTRQ <= '1'; -- Force interrupt immediately (after the break took affect).
+			elsif CMD = x"D4" and IPn = '0' and CMD_STATE = IDLE then
+				INTRQ <= '1'; -- Force interrupt on next index pulse (after the break took affect).
+			elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then
+				INTRQ <= '1'; -- Indicate interrupt request due to seek error.
+			elsif CMD_STATE = T1_VERIFY_DELAY and CMD(2) = '0' then
+				INTRQ <= '1'; -- Indicate interrupt: command finished or interrupted.
+			elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: seek error.
+			elsif CMD_STATE = T1_VERIFY_CRC and CRC_ERR = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request; command correct, no CRC error.
+			elsif CMD_STATE = T2_RD_WR_SECT and CMD(7 downto 5) = "101" and WPRTn = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request because disk is write protected.
+			elsif CMD_STATE = T2_INIT and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: timeout.
+			elsif CMD_STATE = T2_VERIFY_CRC_2 and DELAY = true and CRC_ERR = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request due to CRC error.
+			elsif CMD_STATE = T2_MULTISECT and CMD(4) = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request, command correct finished.
+			elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: lost data.
+			elsif CMD_STATE = T3_WR and WPRTn = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: disk is write protected.
+			elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request due to lost data.
+			elsif CMD_STATE = T3_CHECK_INDEX_2 and INDEX_MARK = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly.
+            elsif CMD_STATE = T3_CHECK_INDEX_3 and INDEX_MARK = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly.
+			elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request because record was not found.
+			elsif CMD_STATE = T3_VERIFY_CRC then
+				INTRQ <= '1'; -- Indicate interrupt request; command finished with or without CRC error.
+			end if;
+		end if;
+	end process P_INTRQ;
+
+	P_LOST_DATA_TR00: process(RESETn, CLK)
+	-- Logic for the status bit number 2:
+	-- The TRACK00 flag is used to detect wether a floppy disk drive
+	-- is connected or not.
+	begin
+		if RESETn = '0' then
+			LOST_DATA_TR00 <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD(7 downto 4) = x"D" and BUSY = '0' then -- Forced interrupt.
+				LOST_DATA_TR00 <= not TRACK00n;
+			elsif CMD_STATE = INIT then
+				LOST_DATA_TR00 <= '0';
+            elsif CMD_STATE = T1_VERIFY_DELAY then
+				LOST_DATA_TR00 <= not TRACK00n;
+			elsif CMD_STATE = T2_VERIFY_DRQ_1 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T2_VERIFY_DRQ_3 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_DATALOST then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_CHECK_DR and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			end if;
+		end if;
+	end process P_LOST_DATA_TR00;
+
+	MOTORSWITCH: process(RESETn, CLK)
+	variable INDEXCNT	: std_logic_vector(3 downto 0);
+	variable LOCK		: boolean;
+	begin
+		if RESETn = '0' then
+			MO <= '0';
+			INDEXCNT := x"0";
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE /= IDLE then
+				INDEXCNT := x"9"; -- Initialise the index counter.
+				LOCK := false;
+			elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then
+				INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state.
+				LOCK := true;
+			elsif IPn = '1' then
+				LOCK := false;
+			end if;
+            --
+            if CMD_STATE = INIT and CMD_WR = false then
+				MO <= '1'; -- Start the motor for all command types I ... III in this state.
+			elsif INDEXCNT = x"0" then
+				MO <= '0'; -- The motor stops after 9 index pulses in idle state.
+			end if;
+		end if;
+	end process MOTORSWITCH;
+
+	WRITE_PROTECT: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			WR_PR <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT and CMD(7) = '1' then
+				WR_PR <= '0'; -- Clear the flag for type II and type III  commands.
+			elsif CMD_STATE = T2_RD_WR_SECT and WPRTn = '0' then
+				WR_PR <= '1';
+			elsif CMD_STATE = T3_WR and WPRTn = '0' then
+				WR_PR <= '1';
+			end if;
+		end if;
+	end process WRITE_PROTECT;
+
+	RECTYPE_SPINUP: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SPINUP_RECTYPE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT then
+				SPINUP_RECTYPE <= '0'; -- Clear the flag for type II...III  commands.
+			elsif CMD_STATE = SPINUP and CMD(7) = '0' and INDEX_CNT = true then
+				SPINUP_RECTYPE <= '1'; -- SPINUP SEQUENCE for type I commands has finished.
+			elsif CMD_STATE = T2_VERIFY_AM and (DATA_AM = '1' or DDATA_AM = '1') then
+				case DSR is
+					when x"F8" => SPINUP_RECTYPE <= '1'; -- Deleted data address mark.
+					when x"FB" => SPINUP_RECTYPE <= '0'; -- Normal data address mark.
+					when others => null; -- Forbidden, should never appear.
+				end case;
+			end if;
+		end if;
+	end process RECTYPE_SPINUP;
+
+	WRITEGATE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			WG <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T2_WR_LEADIN | T3_LOAD_SHFT =>
+					WG <= '1';
+				when T2_MULTISECT | IDLE =>
+					WG <= '0';
+				when others =>
+					null;
+			end case;
+		end if;
+	end process WRITEGATE;
+
+	RESTORE_TRAP: process(RESETn, CLK)
+	-- This process is responsible to supervise the RESTORE command.
+	-- If after 255 stepping pulses no TRACK00n was not detected, the
+	-- RESTORE command is terminated and the interrupt request and the
+	-- seek error are set.
+	variable STEP_CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			STEP_CNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = IDLE then
+				STEP_CNT := x"00";
+			elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command.
+				STEP_CNT := x"00";
+			elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then
+				STEP_CNT := STEP_CNT + '1';
+			end if;
+		end if;
+		--
+		case STEP_CNT is
+			when x"FF" => STEP_TRAP <= true;
+			when others => STEP_TRAP <= false;
+		end case;
+	end process RESTORE_TRAP;
+
+	STEPPULSE: process(RESETn, CLK)
+	-- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us.
+	-- in FM mode This process is responsible to provide the correct pulse lengths.
+	variable CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = T1_STEP then
+				case DDEn is
+					when '1' => CNT := x"80"; --Start counter for FM step pulse.
+                    when '0' => CNT := x"40"; --Start counter for MFM step pulse.
+				end case;
+			elsif CNT > x"00" then
+				CNT := CNT -1; -- Count 63 or 127 CLK cycles ...
+			end if;
+			case CNT is
+				when x"00" => STEP <= '0';
+				when others => STEP <= '1'; --...result in 3.875us or 7.75us pulse.
+			end case;
+		end if;
+	end process STEPPULSE;
+
+	TRACK_MEM: process(RESETn, CLK, TRACKMEM)
+	-- This process is necessary to store the actual track number in the
+	-- type III command 'read address' because the track number is written
+	-- to the sector register some byte times after the detection of the 
+	-- track number from disk.
+	begin
+		if RESETn = '0' then
+			TRACKMEM <= x"00";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when IDLE =>
+					TRACKMEM <= x"00"; -- Clear the Track memory.
+				when T3_LOAD_DATA_2 =>
+					TRACKMEM <= DSR; -- Store the actual track number.
+				when others =>
+					null;
+			end case;
+		end if;
+		TRACK_NR <= TRACKMEM; -- Output the TRACKMEM.
+	end process TRACK_MEM;
+
+	SECT_LENGTH: process(RESETn, CLK, SECT_LEN)
+	-- This process supervises the read sector and write sector
+	-- commands. If the sector read or write are equal to the
+	-- sector length, the commands read sector and write sector
+	-- are ready.
+	begin
+		if RESETn = '0' then
+			SECT_LEN <= "00000000000";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T2_SCAN_LEN =>
+					-- Bring in the correct sector length.
+					case DSR(1 downto 0) is
+						when "00" => SECT_LEN <= "00010000000"; -- 128 Byte per sector.
+						when "01" => SECT_LEN <= "00100000000"; -- 256 Byte per sector.
+						when "10" => SECT_LEN <= "01000000000"; -- 512 Byte per sector.
+						when "11" => SECT_LEN <= "10000000000"; -- 1024 Byte per sector.
+						when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -.
+					end case;
+				when T2_LOAD_DATA | T2_LOAD_SHFT =>
+					SECT_LEN <= SECT_LEN - '1';
+				when others =>
+					null;
+			end case;
+		end if;
+	end process SECT_LENGTH;
+
+	P_CRC_ERR: process(RESETn, CLK)
+	-- This code checks the CRC status in the right command states
+	-- and sets or resets the CRC error status flag.
+	begin
+		if RESETn = '0' then
+			CRC_ERRFLAG <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when INIT =>
+					if CMD(7) = '0' then
+						CRC_ERRFLAG <= '0'; -- Reset for type I commands only.
+					end if;
+				when T1_VERIFY_CRC | T2_VERIFY_CRC_1  =>
+					if CRC_ERR = '1' and DELAY = true then
+						CRC_ERRFLAG <= '1'; -- Set CRC error flag...
+					elsif CRC_ERR = '0' and DELAY = true then
+						CRC_ERRFLAG <= '0'; -- ... or reset CRC error flag.
+					end if;
+				when T2_VERIFY_CRC_2 | T3_VERIFY_CRC =>
+					if CRC_ERR = '1' and DELAY = true then
+						-- Set CRC error flag but no reset in here.
+						-- The CRC is already reset by the previous checks.
+						CRC_ERRFLAG <= '1';
+					end if;
+				when others =>
+					null;
+			end case;
+		end if;
+	end process P_CRC_ERR;
+
+    CMD_WR <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '0' else false; -- Command register write.
+	STAT_RD <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '1' else false; -- Status register read.
+	DATA_WR <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '0' else false; -- Data register write.
+	DATA_RD <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '1' else false; -- Data register read.
+
+	-- Track register arithmetics controls:
+	TR_PRES <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command.
+	TR_CLR 	<= '1' when CMD_STATE = T1_HEAD_CTRL and TRACK00n = '0' and DIR = '0' else '0';
+	TR_INC	<= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '1' else '0';
+	TR_DEC	<= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '0' else '0';
+
+	-- Sector register arithmetics:
+	SR_INC	<= '1' when CMD_STATE = T2_MULTISECT and CMD(4) = '1' else '0'; -- Multi sector enabled.
+	SR_LOAD <= '1' when CMD_STATE = T3_LOAD_SR else '0';
+
+	-- Data register arithmetics controls:
+	DR_CLR 	<= 	'1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command.
+	DR_LOAD <= 	'1' when CMD_STATE = T2_LOAD_DATA else
+				'1' when CMD_STATE = T3_LOAD_DATA_1 else
+				'1' when CMD_STATE = T3_LOAD_DATA_2 else '0';
+	
+	-- Shift register arithmetics controls:
+	-- During type I and type II commands all characters are allowed as data.
+	-- During the type III write track command, there are some special characters
+	-- which may not appear as normal data. See the register file for more information.
+	SHFT_LOAD_SD <= '1' when CMD_STATE = T3_LOAD_SHFT else '0'; -- Special data.
+	SHFT_LOAD_ND <= '1' when CMD_STATE = T1_LOAD_SHFT else 
+				 	'1' when CMD_STATE = T2_LOAD_SHFT else '0'; -- Normal data.
+	
+	P_CRC_PRES: process(RESETn, CLK)
+	-- CRC preset during write sector and write track commands.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			CRC_PRES <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			-- In write track command, the CRC is initialised at the beginning of the
+			-- first A1 data and released during shifting the CRC out.
+			if CMD_STATE = T2_WR_AM and LOCK = false then
+				CRC_PRES <= '1'; -- Write sector command.
+				LOCK := true;
+			elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F5" and LOCK = false then -- x"F5" means write A1.
+				CRC_PRES <= '1'; -- Write track command.
+				LOCK := true;
+			elsif CMD_STATE = T2_WR_CRC then
+				CRC_PRES <= '0'; -- Write sector command.
+				LOCK := false;
+			elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F7" then
+				CRC_PRES <= '0'; -- Write track command.
+				LOCK := false;
+			else
+				CRC_PRES <= '0';
+			end if;
+		end if;
+	end process P_CRC_PRES;
+	
+	-- Write control signals:
+	AM_2_DISK <= 	'1' when CMD_STATE = T2_WR_AM else '0';
+	FF_2_DISK <= 	'1' when CMD_STATE = T2_WR_FF else '0';
+	DSR_2_DISK <= 	'1' when CMD_STATE = T2_WR_BYTE else
+					'1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE /= x"F7" else '0'; -- not during CRC.
+	CRC_2_DISK <= 	'1' when CMD_STATE = T2_WR_CRC else 
+					'1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE = x"F7" else '0';
+
+	-- Write precompensation control:
+	PRECOMP_EN <= 	'1' when CMD(7 downto 4) = x"A" and CMD(1) = '0' else -- Write single sector.
+					'1' when CMD(7 downto 4) = x"B" and CMD(1) = '0' else -- Write multiple sector.
+					'1' when CMD(7 downto 4) = x"F" and CMD(1) = '0' else '0'; -- Write track.
+
+	-- Disk data flow direction:
+	DISK_RWn <= -- Write sector command:
+				'0' when CMD_STATE = T2_WR_LEADIN else
+				'0' when CMD_STATE = T2_WR_AM else
+				'0' when CMD_STATE = T2_LOAD_SHFT else
+				'0' when CMD_STATE = T2_WR_BYTE else
+				'0' when CMD_STATE = T2_VERIFY_DRQ_3 else
+				'0' when CMD_STATE = T2_DATALOST else
+				'0' when CMD_STATE = T2_WRSTAT else
+				'0' when CMD_STATE = T2_WR_CRC else
+				'0' when CMD_STATE = T2_WR_FF else
+				-- Write track command:
+				'0' when CMD_STATE = T3_LOAD_SHFT else
+				'0' when CMD_STATE = T3_WR_DATA else
+				'0' when CMD_STATE = T3_CHECK_INDEX_2 else
+				'0' when CMD_STATE = T3_DATALOST else '1';
+end BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
new file mode 100644
index 0000000..54b2060
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
@@ -0,0 +1,162 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The CRC cyclic redundancy checker unit. Further description  ----
+---- see below.                                                   ----
+----                                                              ----
+---- Working principle of the CRC generator and verify unit:      ----
+---- During read operation:                                       ----
+---- The CRC generator is switched on via after the detection of  ----
+---- the address ID of the data ID mark. The CRC generation last  ----
+---- in case of the address ID until the lenght byte is read.     ----
+---- In case of generation after the data address mark the CRC    ----
+---- generator is activated until the last data byte is read.     ----
+---- The number of data bytes to be read depends on the LENGHT    ----
+---- information in the header file. After generation of the CRC  ----
+---- the CRC_GEN is switched off and the VERIFY procedure begins  ----
+---- by activating CRC_VERIFY. The previously generated CRC is    ----
+---- then compared (serially) with the two consecutive read CRC   ----
+---- bytes. The CRC error appeas, when the comparision fails.     ----
+---- During write operation:                                      ----
+---- The CRC generator is switched on via after the detection of  ----
+---- the address ID of the data ID mark. The CRC generation last  ----
+---- in case of the address ID until the lenght byte is read.     ----
+---- In case of generation after the data address mark the CRC    ----
+---- generator is activated until the last data byte is read.     ----
+---- The number of data bytes to be read depends on the LENGHT    ----
+---- information in the header file. After the generation of the  ----
+---- two CRC bytes, the write out process begins by activating    ----
+---- CRC_SHFTOUT. The CRC data appears in this case serially on   ----
+---- the CRC_SDOUT.                                               ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CRC_SHIFT has now synchronous reset to meeet preset behaviour.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_CRC_LOGIC is
+	port(
+		-- System control
+		CLK				: in bit;
+		RESETn			: in bit;
+		DISK_RWn		: in bit;
+
+		-- Preset controls:
+		DDEn		: in bit;
+		ID_AM		: in bit;
+		DATA_AM		: in Bit;
+		DDATA_AM	: in Bit;
+		
+		-- CRC unit:
+		SD			: in bit; -- Serial data input.
+		CRC_STRB	: in bit; -- Data strobe.
+		CRC_2_DISK	: in bit; -- Forces the unit to flush the CRC remainder.
+		CRC_PRES	: in bit; -- Presets the CRC unit during write to disk.
+		CRC_SDOUT	: out bit; -- Serial data output.
+		CRC_ERR		: out bit -- Indicates CRC error.
+	);
+end WF1772IP_CRC_LOGIC;
+
+architecture BEHAVIOR of WF1772IP_CRC_LOGIC is
+signal CRC_SHIFT	: bit_vector(15 downto 0);
+begin
+	P_CRC: process
+	-- The shift register is initialised with appropriate values in HD or DD mode.
+	-- In theory the shift register should be preset to ones. Due to a latency of one byte 
+	-- in FM mode or 4 bytes in MFM mode it is necessary to preset the shift register with 
+	-- the CRC values of this ID address mark, data address mark and the A1 sync bytes. The 
+	-- latency is caused by the addressmark detector which needs one or 4 byte time(s) for 
+	-- detection. The CRC unit therefore starts with every detection of an address mark and
+	-- ends if the CRC unit is flushed.
+	begin 
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CRC_SHIFT <= (others => '1');
+		elsif CRC_2_DISK = '1' then
+			if CRC_STRB = '1' then
+				CRC_SHIFT <= CRC_SHIFT(14 downto 0) & '0';
+			end if;
+		elsif CRC_PRES = '1' then -- Preset during write sector or write track command.
+			CRC_SHIFT <= x"FFFF";
+		elsif DDEn = '1' and ID_AM = '1' then -- DD mode and ID address mark detected.
+			CRC_SHIFT <= x"EF21"; -- The CRC-CCITT for data x"FE" is x"EF21"
+		elsif DDEn = '1' and DATA_AM = '1' then -- DD mode and data address mark detected.
+			CRC_SHIFT <= x"BF84"; -- The CRC-CCITT for data x"FB" is x"BF84"
+		elsif DDEn = '1' and DDATA_AM = '1' then -- DD mode and deleted data address mark detected.
+			CRC_SHIFT <= x"8FE7"; -- The CRC-CCITT for data x"F8" is x"8FE7"
+		elsif DDEn = '0' and ID_AM = '1' then -- HD mode and ID address mark detected.
+			CRC_SHIFT <= x"B230"; -- The CRC-CCITT for data x"A1A1A1FE" is x"B230"
+		elsif DDEn = '0' and DATA_AM = '1' then -- HD mode and data address mark detected.
+			CRC_SHIFT <= x"E295"; -- The CRC-CCITT for data x"A1A1A1FB" is x"E295"
+		elsif DDEn = '0' and DDATA_AM = '1' then -- HD mode and deleted data address mark detected.
+			CRC_SHIFT <= x"D2F6"; -- The CRC-CCITT for data x"A1A1A1F8" is x"D2F6"
+		elsif CRC_STRB = '1' then
+			-- CRC-CCITT (xFFFF):
+			-- the polynomial is G(x) = x^16 + x^12 + x^5 + 1
+			-- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC
+			-- verification. In this operating condition the ID or the data field is compared 
+			-- against the CRC checksum. if there are no errors, the shift register's value is 
+			-- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the
+			-- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the
+			-- ID or data field.
+			CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) &
+						 CRC_SHIFT(10 downto 5) & (CRC_SHIFT(15) xor CRC_SHIFT(4) xor SD) &
+						 CRC_SHIFT(3 downto 0) & (CRC_SHIFT(15) xor SD);
+		end if;
+	end process P_CRC;
+
+	CRC_SDOUT <= CRC_SHIFT(15);
+    CRC_ERR <= '0' when CRC_SHIFT = x"0000" else '1';
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
new file mode 100644
index 0000000..95ce08c
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
@@ -0,0 +1,426 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The digital PLL is responsible to detect the incoming serial ----
+---- data stream and provide a system clock synchronous signal    ----
+---- containing the data and clock information.                   ----
+---- To understand how the code works in detail refer to the free ----
+---- US patent no. 4,780,844.                                     ----
+----                                                              ----
+---- Attention: The settings for TOP and BOTTOM, which control    ----
+---- the PLL frequency and for PHASE_CORR which control the PLL   ----
+---- phase are rather critical for a good read condition! To test ----
+---- the PLL in the WD1772 compatible core do the following:      ----
+---- Sample on an oscilloscope on one channel the falling edge of ----
+---- the RDn pulse and on the other channel the PLL_DSTRB. The    ----
+---- RDn must be located exactly between the PLL_DSTRB pulses.    ----
+---- Otherwise, the parameters TOP, BOTTOM and PHASE_CORR have to ----
+---- be optimized.                                                ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to lack of FM
+--   drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/12/24 WF
+--   Improvement of the INPORT process.
+--   Bugfix of the FREQ_AMOUNT counter: now stops if its value is zero.
+--   Several changes concerning the PLL parameters to improve the
+--     stability of the PLL.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_DIGITAL_PLL is
+	generic(
+		-- The valid range of the period counter of the PLL is given by the TOP and BOTTOM 
+		-- limits. The counter range is therefore BOTTOM <= counter value <= TOP.
+		-- The generic PHASE_CORR is responsible fo the center setting of PLL_DSTRB concerning
+		-- the RDn period.
+		-- The nominal frequency setting is 128. So it is recommended to use TOP and BOTTOM
+		-- settings symmetrically around 128. If TOP = BOTTOM = 128, the frequency control 
+        -- is disabled. TOP + PHASE_CORR may not exceed a value of 255. BOTTOM - PHASE_CORR
+        -- may not drop below zero.
+        TOP			: integer range 0 to 255 := 152; -- +18.0%
+        BOTTOM		: integer range 0 to 255 := 104; -- -18.0%
+        PHASE_CORR	: integer range 0 to 128 := 75
+	);
+	port(
+		-- System control
+		CLK		: in bit; -- 16MHz clock.
+		RESETn	: in bit;
+
+		-- Controls
+		DDEn		: in bit; -- Double density enable.
+		HDTYPE		: in bit; -- This control is '1' when HD disks are inserted.
+		DISK_RWn	: in bit; -- Read write control.
+
+		-- Data and clock lines
+		RDn			: in bit; -- Read signal from the disk.
+		PLL_D		: out bit; -- Synchronous read signal.
+		PLL_DSTRB	: out bit -- Read strobe.
+	);
+end WF1772IP_DIGITAL_PLL;
+
+architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is
+signal RD_In				: bit;
+signal UP, DOWN				: bit;
+signal PHASE_DECREASE		: bit;
+signal PHASE_INCREASE		: bit;
+signal HI_STOP, LOW_STOP	: bit;
+signal PER_CNT				: std_logic_vector(7 downto 0);
+signal ADDER_IN				: std_logic_vector(7 downto 0);
+signal ADDER_MSBs			: bit_vector(2 downto 0);
+signal RD_PULSE				: bit;
+signal ROLL_OVER			: bit;
+signal HISTORY_REG			: bit_vector(1 downto 0);
+signal ERROR_HISTORY		: integer range 0 to 2;
+begin
+	INPORT: process
+	-- This process is necessary due to the poor quality of the rising
+	-- edge of RDn. Let it work on the negative clock edge.
+	begin
+        wait until CLK = '0' and CLK' event;
+         RD_In <= RDn;
+	end process INPORT;
+
+	EDGEDETECT: process(RESETn, CLK)
+    -- This process forms a falling edge detector for the incoming
+	-- data read port. The output (RD_PULSE) goes high for exactly
+	-- one clock period after the RDn is low and the positive
+	-- clock edge is detected.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			RD_PULSE <= '0';
+			LOCK := false;
+        elsif CLK = '1' and CLK' event then
+			if DISK_RWn = '0' then -- Disable detector in write mode.
+				RD_PULSE <= '0';
+            elsif RD_In = '0' and LOCK = false then
+				RD_PULSE <= '1'; -- READ_PULSE is inverted against RDn
+				LOCK := true;
+            elsif RD_In = '1' then
+				LOCK := false;
+				RD_PULSE <= '0';
+			else
+				RD_PULSE <= '0';
+			end if;
+		end if;
+	end process EDGEDETECT;
+
+	PERIOD_CNT: process(RESETn, CLK)
+	-- This process provides the nominal variable added to the adder. To achieve a good 
+    -- settling time of the PLL in all cases, the period counter is controlled via the DDEn
+    -- and HDTYPE flags respective to its added value. Be aware, that in case of adding "10"
+    -- or "11", the TOP value may be exceeded or the period counter may drop below the BOTTOM
+	-- value. The higher the value added, the faster will be the settling time of phase locked
+	-- loop .
+	begin
+		if RESETn = '0' then
+			PER_CNT <= "10000000"; -- Initial value is 128.
+		elsif CLK = '1' and CLK' event then
+            if UP = '1' then
+                PER_CNT <= PER_CNT + '1';
+            elsif DOWN = '1' then
+                PER_CNT <= PER_CNT - '1';
+			end if;
+		end if;
+	end process PERIOD_CNT;
+
+    HI_STOP <= 	'1' when PER_CNT >= TOP else '0';
+    LOW_STOP <= '1' when PER_CNT <= BOTTOM else '0';
+
+	ADDER_IN <= -- This DISK_RWn = '0' implementation keeps the last phase information
+				-- of the PLL in read from disk mode. It should be a good solution concer-
+				-- ning alternative read write cycles.
+				"10000000" when DISK_RWn = '0' else -- Nominal value for write to disk. 
+                PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags.
+                PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds.
+				PER_CNT; -- No phase correction;
+
+	ADDER: process(RESETn, CLK, DDEn, HDTYPE)
+	-- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock. 
+	-- The offset (LSBs) of the adder input is chosen to be conform with the required
+	-- rollover period in the different DDEn and HDTYPE modi as follows:
+	-- With a nominal adder input term of 128:
+	-- The adder rolls over every 4us for DDEn = 1 and HDTYPE = 0.
+	-- The adder rolls over every 2us for DDEn = 1 and HDTYPE = 1.
+	-- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0.
+	-- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1.
+	-- The given times are the half of a data period time in MFM or FM.
+	variable ADDER_DATA	: std_logic_vector(12 downto 0);
+	begin
+		if RESETn = '0' then
+			ADDER_DATA := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			ADDER_DATA := ADDER_DATA + ADDER_IN;
+		end if;
+		--
+		case DDEn & HDTYPE is
+			when "01" => -- MFM mode using HD disks, results in 1us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8));
+			when "00" => -- MFM mode using DD disks, results in 2us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
+			when "11" => -- FM mode using HD disks, results in 2us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
+			when "10" => -- FM mode using DD disks, results in 4us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10));
+		end case;
+	end process ADDER;
+
+	ROLLOVER: process(RESETn, CLK)
+	-- This process forms a falling edge detector for the detection
+	-- of the adder's rollover time. The output goes low for exactly
+	-- one clock period after the rollover is detected and the positive
+	-- clock edge appears.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			ROLL_OVER <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if ADDER_MSBs /= "111" and LOCK = false then
+				ROLL_OVER <= '1';
+				LOCK := true;
+			elsif ADDER_MSBs = "111" then
+				LOCK := false;
+				ROLL_OVER <= '0';
+			else
+				ROLL_OVER <= '0';
+			end if;
+		end if;
+	end process ROLLOVER;
+	PLL_DSTRB <= ROLL_OVER;
+
+	DATA_FLIP_FLOP: process(RESETn, CLK, RD_PULSE)
+	-- This flip-flop is responsible for 'catching' the read pulses of the
+	-- serial data input. 
+	begin
+		if RESETn = '0' then
+			PLL_D <= '0'; -- Asynchronous reset.
+		elsif CLK = '1' and CLK' event then
+			if RD_PULSE = '1' then
+				PLL_D <= '1'; -- Read pulse detected.
+			elsif ROLL_OVER = '1' then
+				PLL_D <= '0';
+			end if;
+		end if;
+	end process DATA_FLIP_FLOP;
+
+	WIN_HISTORY: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HISTORY_REG <= "00";
+		elsif CLK = '1' and CLK' event then
+			if RD_PULSE = '1' then
+				HISTORY_REG <= ADDER_MSBs(2) & HISTORY_REG(1);
+			end if;
+		end if;
+	end process WIN_HISTORY;
+	
+	-- Error history:
+	-- This signal indicates the number of consequtive levels of the adder's
+	-- MSB and the history register as shown in the following table. The default
+	-- setting of 0 was added to compile with the Xilinx ISE.
+	ERROR_HISTORY <= 	2 when ADDER_MSBs(2) = '0' and HISTORY_REG = "00" else -- Speed strongly up.
+						1 when ADDER_MSBs(2) = '0' and HISTORY_REG = "01" else -- Speed up.
+						0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "10" else -- o.k.
+						0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "11" else -- Now adjusted.
+						0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "00" else -- Now adjusted.
+						0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "01" else -- o.k.
+						1 when ADDER_MSBs(2) = '1' and HISTORY_REG = "10" else -- Slow down.
+						2 when ADDER_MSBs(2) = '1' and HISTORY_REG = "11" else 0; -- Slow strongly down.
+
+	FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP)
+	-- The frequency decoder controls the period of the data inspection window respective to the
+	-- ERROR_HISTORY for the 11 bit adder is as follows:
+	-- ERROR_HISTORY = 0: 
+	--						-> no correction necessary <-
+	-- ERROR_HISTORY = 1:
+	-- MSBs input:			7	6	5	4	3	2	1	0
+	-- Correction output:  -3  -2  -1   0   0  +1  +2  +3
+	-- ERROR_HISTORY = 2:
+	-- MSBs input:			7	6	5	4	3	2	1	0
+	-- Correction output:  -4  -3  -2  -1  +1  +2  +3  +4
+	-- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation
+	-- of the adder (0 is up).
+	variable FREQ_AMOUNT: std_logic_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			FREQ_AMOUNT := "0000";
+		elsif CLK = '1' and CLK' event then
+            if RD_PULSE = '1' then -- Load the frequency amount register.
+				case ERROR_HISTORY is
+					when 2 =>
+						case ADDER_MSBs is
+							when "000" => FREQ_AMOUNT := "0100";
+							when "001" => FREQ_AMOUNT := "0011";
+							when "010" => FREQ_AMOUNT := "0010";
+							when "011" => FREQ_AMOUNT := "0001";
+							when "100" => FREQ_AMOUNT := "1001";
+							when "101" => FREQ_AMOUNT := "1010";
+							when "110" => FREQ_AMOUNT := "1011";
+							when "111" => FREQ_AMOUNT := "1100";
+						end case;
+					when 1 =>
+						case ADDER_MSBs is
+							when "000" => FREQ_AMOUNT := "0011";
+							when "001" => FREQ_AMOUNT := "0010";
+							when "010" => FREQ_AMOUNT := "0001";
+							when "011" => FREQ_AMOUNT := "0000";
+							when "100" => FREQ_AMOUNT := "1000";
+							when "101" => FREQ_AMOUNT := "1001";
+							when "110" => FREQ_AMOUNT := "1010";
+							when "111" => FREQ_AMOUNT := "1011";
+						end case;
+					when others =>
+						FREQ_AMOUNT := "0000";
+				end case;
+            elsif FREQ_AMOUNT(2 downto 0) > "000" then
+				FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register.
+			end if;
+		end if;
+		--
+		if FREQ_AMOUNT(3) = '0' and FREQ_AMOUNT(2 downto 0) /= "000" and HI_STOP = '0' then
+		-- FREQ_AMOUNT(3) = '0' means Frequency is too low. Count up when counter is not at HI_STOP.
+			UP <= '1';
+			DOWN <= '0';
+		elsif FREQ_AMOUNT(3) = '1' and FREQ_AMOUNT (2 downto 0) /= "000" and LOW_STOP = '0' then
+		-- FREQ_AMOUNT(3) = '1' means Frequency is too high. Count down when counter is not at LOW_STOP.
+			UP <= '0';
+			DOWN <= '1';
+		else
+			UP <= '0';
+			DOWN <= '0';
+		end if;
+	end process FREQUENCY_DECODER;
+
+	PHASE_DECODER: process(RESETn, CLK)
+	-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit
+	-- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a
+	-- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of
+	-- PHASE_AMOUNT).
+	-- This implementation gives the freedom to adjust the phase amount individually for every mode
+	-- depending on DDEn and HDTYPE.
+	variable PHASE_AMOUNT: std_logic_vector(5 downto 0);
+	begin
+		if RESETn = '0' then
+			PHASE_AMOUNT := "000000";
+		elsif CLK = '1' and CLK' event then
+            if RD_PULSE = '1' and DDEn = '1' and HDTYPE = '0' then -- FM mode, single density.
+				case ADDER_MSBs is -- Multiplier: 4.
+					when "000" => PHASE_AMOUNT := "010000";
+					when "001" => PHASE_AMOUNT := "001101";
+					when "010" => PHASE_AMOUNT := "001000";
+					when "011" => PHASE_AMOUNT := "000100";
+					when "100" => PHASE_AMOUNT := "100100";
+					when "101" => PHASE_AMOUNT := "101000";
+					when "110" => PHASE_AMOUNT := "101100";
+					when "111" => PHASE_AMOUNT := "110000";
+				end case;
+			elsif RD_PULSE = '1' and DDEn = '1' and HDTYPE = '1' then -- FM mode, double density
+				case ADDER_MSBs is -- Multiplier: 2.
+					when "000" => PHASE_AMOUNT := "001000";
+					when "001" => PHASE_AMOUNT := "000110";
+					when "010" => PHASE_AMOUNT := "000100";
+					when "011" => PHASE_AMOUNT := "000010";
+					when "100" => PHASE_AMOUNT := "100010";
+					when "101" => PHASE_AMOUNT := "100100";
+					when "110" => PHASE_AMOUNT := "100110";
+					when "111" => PHASE_AMOUNT := "101000";
+				end case;
+            elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '0' then -- MFM mode, single density
+				case ADDER_MSBs is -- Multiplier: 2.
+					when "000" => PHASE_AMOUNT := "000110";
+					when "001" => PHASE_AMOUNT := "000100";
+					when "010" => PHASE_AMOUNT := "000011";
+					when "011" => PHASE_AMOUNT := "000010";
+					when "100" => PHASE_AMOUNT := "100010";
+					when "101" => PHASE_AMOUNT := "100011";
+					when "110" => PHASE_AMOUNT := "100100";
+					when "111" => PHASE_AMOUNT := "100110";
+				end case;
+			elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '1' then -- MFM mode, double density.
+				case ADDER_MSBs is -- Multiplier: 1.
+					when "000" => PHASE_AMOUNT := "000100";
+					when "001" => PHASE_AMOUNT := "000011";
+					when "010" => PHASE_AMOUNT := "000010";
+					when "011" => PHASE_AMOUNT := "000001";
+					when "100" => PHASE_AMOUNT := "100001";
+					when "101" => PHASE_AMOUNT := "100010";
+					when "110" => PHASE_AMOUNT := "100011";
+					when "111" => PHASE_AMOUNT := "100100";
+				end case;
+			else -- Modify phase amount register:
+                if PHASE_AMOUNT(4 downto 0) > x"0" then
+                    PHASE_AMOUNT := PHASE_AMOUNT - 1;
+				end if;
+			end if;
+		end if;
+		--
+        if PHASE_AMOUNT(5) = '0' and PHASE_AMOUNT(4 downto 0) > x"0" then
+		-- PHASE_AMOUNT(5) = '0' means, that the phase leeds.
+			PHASE_INCREASE <= '1'; -- Speed phase up, accelerate next rollover.
+			PHASE_DECREASE <= '0';
+        elsif PHASE_AMOUNT(5) = '1' and PHASE_AMOUNT(4 downto 0) > x"0" then
+		-- PHASE_AMOUNT(5) = '1' means, that the phase lags.
+			PHASE_INCREASE <= '0';
+			PHASE_DECREASE <= '1'; -- Speed phase down, delay of next rollover.
+		else
+			PHASE_INCREASE <= '0';
+			PHASE_DECREASE <= '0';
+		end if;
+	end process PHASE_DECODER;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
new file mode 100644
index 0000000..b365b3d
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
@@ -0,0 +1,232 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--   Removed CRC_BUSY.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF1772IP_PKG is
+-- component declarations:
+component WF1772IP_AM_DETECTOR
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		DATA		: in bit;
+		DATA_STRB	: in bit;
+		ID_AM		: out bit;
+		DATA_AM		: out bit;
+		DDATA_AM	: out bit
+	);
+end component;
+
+component WF1772IP_CONTROL
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		A1, A0			: in bit;
+		RWn				: in bit;
+		CSn				: in bit;
+		DDEn			: in bit;
+		DR				: in bit_vector(7 downto 0);
+		CMD				: in std_logic_vector(7 downto 0);
+		DSR				: in std_logic_vector(7 downto 0);
+		TR				: in std_logic_vector(7 downto 0);
+		SR				: in std_logic_vector(7 downto 0);
+		MO				: out bit;
+		WR_PR			: out bit;
+		SPINUP_RECTYPE	: out bit;
+		SEEK_RNF		: out bit;
+		CRC_ERRFLAG		: out bit;
+		LOST_DATA_TR00	: out bit;
+		DRQ				: out bit;
+		DRQ_IPn			: out bit;
+		BUSY			: out bit;
+		AM_2_DISK		: out bit;
+		ID_AM			: in bit;
+		DATA_AM			: in bit;
+		DDATA_AM		: in bit;
+		CRC_ERR			: in bit;
+		CRC_PRES		: out bit;
+		TR_PRES			: out bit;
+		TR_CLR			: out bit;
+		TR_INC			: out bit;
+		TR_DEC			: out bit;
+		SR_LOAD			: out bit;
+		SR_INC			: out bit;
+		TRACK_NR		: out std_logic_vector(7 downto 0);
+		DR_CLR			: out bit;
+		DR_LOAD			: out bit;
+		SHFT_LOAD_SD	: out bit;
+		SHFT_LOAD_ND	: out bit;
+		CRC_2_DISK		: out bit;
+		DSR_2_DISK		: out bit;
+		FF_2_DISK		: out bit;
+		PRECOMP_EN		: out bit;
+		DATA_STRB 		: in bit;
+		DISK_RWn		: out bit;
+		WPRTn			: in bit;
+		TRACK00n		: in bit;
+		IPn				: in bit;
+		DIRC			: out bit;
+		STEP			: out bit;
+		WG				: out bit;
+		INTRQ			: out bit
+	);
+end component;
+
+component WF1772IP_CRC_LOGIC
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		DISK_RWn	: in bit;
+		ID_AM		: in bit;
+		DATA_AM		: in bit;
+		DDATA_AM	: in bit;
+		SD			: in bit;
+		CRC_STRB	: in bit;
+		CRC_2_DISK	: in bit;
+		CRC_PRES	: in bit;
+		CRC_SDOUT	: out bit;
+		CRC_ERR		: out bit
+	);
+end component;
+
+component WF1772IP_DIGITAL_PLL
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit;
+		DISK_RWn	: in bit;
+		RDn			: in bit;
+		PLL_D		: out bit;
+		PLL_DSTRB	: out bit
+	);
+end component;
+
+component WF1772IP_REGISTERS
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		CSn				: in bit;
+		ADR				: in bit_vector(1 downto 0);
+		RWn				: in bit;
+		DATA_IN			: in std_logic_vector (7 downto 0);
+		DATA_OUT		: out std_logic_vector (7 downto 0);
+		DATA_EN			: out bit;
+		CMD				: out std_logic_vector(7 downto 0);
+		SR				: out std_logic_vector(7 downto 0);
+		TR				: out std_logic_vector(7 downto 0);
+		DSR				: out std_logic_vector(7 downto 0);
+		DR				: out bit_vector(7 downto 0);
+		SD_R			: in bit;
+		DATA_STRB		: in bit;
+		DR_CLR			: in bit;
+		DR_LOAD			: in bit;
+		TR_PRES			: in bit;
+		TR_CLR			: in bit;
+		TR_INC			: in bit;
+		TR_DEC			: in bit;
+		TRACK_NR 		: in std_logic_vector(7 downto 0);
+		SR_LOAD			: in bit;
+		SR_INC			: in bit;
+		SHFT_LOAD_SD	: in bit;
+		SHFT_LOAD_ND	: in bit;
+		MOTOR_ON		: in bit;
+		WRITE_PROTECT	: in bit;
+		SPINUP_RECTYPE	: in bit;
+		SEEK_RNF		: in bit;
+		CRC_ERRFLAG		: in bit;
+		LOST_DATA_TR00	: in bit;
+		DRQ				: in bit;
+		DRQ_IPn			: in bit;
+		BUSY			: in bit;
+		DDEn			: in bit
+	);
+end component;
+
+component WF1772IP_TRANSCEIVER
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		DDEn			: in bit;
+		HDTYPE			: in bit;
+		ID_AM			: in bit;
+		DATA_AM			: in bit;
+		DDATA_AM		: in bit;
+		SHFT_LOAD_SD	: in bit;
+		DR				: in bit_vector(7 downto 0);
+		PRECOMP_EN		: in bit;
+		AM_TYPE			: in bit;
+		AM_2_DISK		: in bit;
+		CRC_2_DISK		: in bit;
+		DSR_2_DISK		: in bit;
+		FF_2_DISK		: in bit;
+		SR_SDOUT		: in std_logic;
+		CRC_SDOUT		: in bit;
+		WRn				: out bit;
+		PLL_DSTRB		: in bit;
+		PLL_D			: in bit;
+		WDATA 			: out bit;
+		DATA_STRB 		: out bit;
+		SD_R			: out bit
+	);
+end component;
+end WF1772IP_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
new file mode 100644
index 0000000..7556fe5
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
@@ -0,0 +1,264 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This file models all the five WD1772 registers: DATA-,       ----
+---- COMMAND-, SECTOR-, TRACK- and STATUS register as also the    ----
+---- shift register.                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_REGISTERS is
+	port(
+		-- System control:
+		CLK			: in bit;
+		RESETn		: in bit;
+
+		-- Bus interface:
+		CSn			: in bit;
+		ADR			: in bit_vector(1 downto 0);
+		RWn			: in bit;
+		DATA_IN		: in std_logic_vector (7 downto 0);
+		DATA_OUT	: out std_logic_vector (7 downto 0);
+		DATA_EN		: out bit;
+
+		-- FDC data:
+		CMD			: out std_logic_vector(7 downto 0); -- Command register.
+		SR			: out std_logic_vector(7 downto 0); -- Sector register.
+		TR			: out std_logic_vector(7 downto 0); -- Track register.
+		DSR			: out std_logic_vector(7 downto 0); -- Data shift register.
+		DR			: out bit_vector(7 downto 0); -- Data register.
+
+		-- Serial data and clock strobes (in and out):
+		DATA_STRB	: in bit; -- Strobe for the incoming data.
+		SD_R		: in bit; -- Serial data input.
+		
+		-- DATA register control:
+		DR_CLR		: in bit; -- Clear.
+		DR_LOAD		: in bit; -- LOAD.
+
+		-- Track register controls:
+		TR_PRES		: in bit;	-- Set x"FF".
+		TR_CLR		: in bit;	-- Clear.
+		TR_INC		: in bit;	-- Increment.
+		TR_DEC		: in bit;	-- Decrement.
+
+		-- Sector register control:
+		TRACK_NR 	: in std_logic_vector(7 downto 0);
+		SR_LOAD		: in bit; -- Load.
+		SR_INC		: in bit; -- Increment.
+
+		-- Shift register control:
+		SHFT_LOAD_SD	: in bit;
+		SHFT_LOAD_ND	: in bit;
+
+		-- Status register stuff
+		MOTOR_ON		: in bit;
+		WRITE_PROTECT	: in bit;
+		SPINUP_RECTYPE	: in bit; -- Disk is on speed / data mark status.
+		SEEK_RNF		: in bit; -- Seek error / record not found status flag.
+		CRC_ERRFLAG		: in bit; -- CRC status flag.
+		LOST_DATA_TR00	: in bit;
+		DRQ				: in bit;
+		DRQ_IPn			: in bit;
+		BUSY			: in bit;
+
+		-- Others:
+		DDEn			: in bit
+	);
+end WF1772IP_REGISTERS;
+
+architecture BEHAVIOR of WF1772IP_REGISTERS is
+-- Remark: In the original data sheet 'WD17X-00' there is the following statement:
+-- "After any register is written to, the same register cannot be read from until
+-- 16us in MFM or 32us in FMMM have elapsed." If this is a hint for a hardware read
+-- lock ... this lock is not implemented in this code.
+signal SHIFT_REG	: std_logic_vector(7 downto 0);
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal COMMAND_REG	: std_logic_vector(7 downto 0);
+signal SECTOR_REG	: std_logic_vector(7 downto 0);
+signal TRACK_REG	: std_logic_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal SD_R_I		: std_logic;
+begin
+	-- Type conversion To_Std_Logic:
+	SD_R_I <= '1' when SD_R = '1' else '0';
+
+	P_SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if SHFT_LOAD_ND = '1' then
+				SHIFT_REG <= DATA_REG; -- Load data register stuff.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '1' then
+				SHIFT_REG <= DATA_REG; -- Normal data in FM mode.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode:
+				case DATA_REG is
+					when x"F5" => SHIFT_REG <= x"A1"; -- Special character.
+					when x"F6" => SHIFT_REG <= x"C2"; -- Special character.
+					when others => SHIFT_REG <= DATA_REG; -- Normal MFM data.
+				end case;
+			elsif DATA_STRB = '1' then -- Shift left during read from disk or write to disk.
+				SHIFT_REG <= SHIFT_REG(6 downto 0) & SD_R_I; -- for write operation SD_R_I is a dummy.
+			end if;
+		end if;
+	end process P_SHIFTREG;
+	DSR <= SHIFT_REG;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "11" and RWn = '0' then
+				DATA_REG <= DATA_IN; -- Write bus data to register
+			elsif DR_LOAD = '1' and DRQ = '0' then
+				DATA_REG <= SHIFT_REG; -- Correct data loaded to shift register.
+			elsif DR_LOAD = '1' and DRQ = '1' then
+				DATA_REG <= x"00"; -- Dummy byte due to lost data loaded to shift register.
+			elsif DR_CLR = '1' then
+				DATA_REG <= (others => '0');
+			end if;
+		end if;
+	end process DATAREG;
+	-- Data register buffered for further data processing.
+	DR <= To_BitVector(DATA_REG);
+
+	SECTORREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SECTOR_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+            if CSn = '0' and ADR = "10" and RWn = '0' and BUSY = '0' then
+				SECTOR_REG <= DATA_IN; -- Write to register when device is not busy.
+			elsif SR_LOAD = '1' then
+				-- Load the track number to the sector register in the type III command
+				-- 'Read Address'.
+				SECTOR_REG <= TRACK_NR;
+			elsif SR_INC = '1' then
+				SECTOR_REG <= SECTOR_REG + '1';
+			end if;
+		end if;
+	end process SECTORREG;
+	SR <= SECTOR_REG;
+
+	TRACKREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TRACK_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "01" and RWn = '0' and BUSY = '0' then
+				TRACK_REG <= DATA_IN; -- Write to register when device is busy.
+			elsif TR_PRES = '1' then
+				TRACK_REG <= (others => '1'); -- Preset the track register.
+			elsif TR_CLR = '1' then
+				TRACK_REG <= (others => '0'); -- Reset the track register.
+			elsif TR_INC = '1' then
+				TRACK_REG <= TRACK_REG + '1'; -- Increment register contents.
+			elsif TR_DEC = '1' then
+				TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents.
+			end if;
+		end if;
+	end process TRACKREG;
+	TR <= TRACK_REG;
+
+	COMMANDREG: process(RESETn, CLK)
+	-- The command register is write only.
+	begin
+		if RESETn = '0' then
+			COMMAND_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "00" and RWn = '0' and BUSY = '0' then
+				COMMAND_REG <= DATA_IN; -- Write to register when device is not busy.
+			-- Write 'force interrupt' to register even when device is busy:
+			elsif CSn = '0' and ADR = "00" and RWn = '0' and DATA_IN(7 downto 4) = x"D" then
+				COMMAND_REG <= DATA_IN;
+			end if;
+		end if;
+	end process COMMANDREG;
+	CMD <= COMMAND_REG;
+
+	STATUSREG: process(RESETn, CLK)
+	-- The status register is read only to the data bus.
+	begin
+		-- Status register wiring:
+		if RESETn = '0' then
+			STATUS_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			STATUS_REG(7) <= MOTOR_ON;
+			STATUS_REG(6) <= WRITE_PROTECT;
+			STATUS_REG(5) <= SPINUP_RECTYPE;
+			STATUS_REG(4) <= SEEK_RNF;
+			STATUS_REG(3) <= CRC_ERRFLAG;
+			STATUS_REG(2) <= LOST_DATA_TR00;
+			STATUS_REG(1) <= DRQ_IPn;
+			STATUS_REG(0) <= BUSY;
+		end if;
+	end process STATUSREG;
+	-- Read from track, sector or data register:
+	-- The register data after writing to the track register is valid at least
+	-- after 32us in FM mode and after 16us in MFM mode.
+	-- Read from status register. This register is read only:
+	-- Be aware, that the status register data bits 7 to 1 after writing 
+	-- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and
+	-- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
+	DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else
+				SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else
+				DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else
+				To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
+	DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0';
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
new file mode 100644
index 0000000..71ef3f3
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
@@ -0,0 +1,154 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is the top level file.                                  ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- - Test of the FM portion of the code (if there is any need). ----
+---- - Test of the read track command.                            ----
+---- - Test of the read address command.                          ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to the lack 
+--   of FM drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma
+--   Oksanen for the information.
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+
+library work;
+use work.WF1772IP_PKG.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TOP is
+	port (
+		CLK			: in bit; -- 16MHz clock!
+		MRn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA		: inout std_logic_vector(7 downto 0);
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit; -- '0' = DD disks, '1' = HD disks.
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end entity WF1772IP_TOP;
+	
+architecture STRUCTURE of WF1772IP_TOP is
+component WF1772IP_TOP_SOC
+	port (
+		CLK			: in bit;
+		RESETn		: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit;
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end component;
+signal DATA_OUT : std_logic_vector(7 downto 0);
+signal DATA_EN  : bit;
+begin
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+
+    I_1772: WF1772IP_TOP_SOC
+        port map(
+            CLK         => CLK,
+            RESETn      => MRn,
+            CSn         => CSn,
+            RWn         => RWn,
+            A1          => A1,
+            A0          => A0,
+            DATA_IN     => DATA,
+            DATA_OUT    => DATA_OUT,
+            DATA_EN     => DATA_EN,
+            RDn         => RDn,
+            TR00n       => TR00n,
+            IPn         => IPn,
+            WPRTn       => WPRTn,
+            DDEn        => DDEn,
+            HDTYPE      => HDTYPE,
+            MO          => MO,
+            WG          => WG,
+            WD          => WD,
+            STEP        => STEP,
+            DIRC        => DIRC,
+            DRQ         => DRQ,
+            INTRQ       => INTRQ
+        );
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
new file mode 100644
index 0000000..9cfd111
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
@@ -0,0 +1,333 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- - Test of the FM portion of the code (if there is any need). ----
+---- - Test of the read track command.                            ----
+---- - Test of the read address command.                          ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to the lack 
+--   of FM drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma Oksanen for the information.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/12/24 WF
+--   Bugfixes in the controller due to hanging state machine.
+--   Removed CRC_BUSY.
+--
+
+library work;
+use work.WF1772IP_PKG.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TOP_SOC is
+	port (
+		CLK			: in bit; -- 16MHz clock!
+		RESETn		: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit; -- '0' = DD disks, '1' = HD disks.
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end entity WF1772IP_TOP_SOC;
+	
+architecture STRUCTURE of WF1772IP_TOP_SOC is
+signal DATA_OUT_REG		: std_logic_vector(7 downto 0);
+signal DATA_EN_REG		: bit;
+signal CMD_I			: std_logic_vector(7 downto 0);
+signal DR_I				: bit_vector(7 downto 0);
+signal DSR_I			: std_logic_vector(7 downto 0);
+signal TR_I				: std_logic_vector(7 downto 0);
+signal SR_I				: std_logic_vector(7 downto 0);
+signal ID_AM_I			: bit;
+signal DATA_AM_I		: bit;
+signal DDATA_AM_I		: bit;
+signal AM_TYPE_I		: bit;
+signal AM_2_DISK_I		: bit;
+signal DATA_STRB_I		: bit;
+signal BUSY_I			: bit;
+signal DRQ_I			: bit;
+signal DRQ_IPn_I		: bit;
+signal LD_TR00_I		: bit;
+signal SP_RT_I			: bit;
+signal SEEK_RNF_I		: bit;
+signal WR_PR_I			: bit;
+signal MO_I				: bit;
+signal PLL_DSTRB_I		: bit;
+signal PLL_D_I			: bit;
+signal CRC_SD_I			: bit;
+signal CRC_ERR_I		: bit;
+signal CRC_PRES_I		: bit;
+signal CRC_ERRFLAG_I	: bit;
+signal SD_R_I			: bit;
+signal CRC_SDOUT_I		: bit;
+signal SHFT_LOAD_SD_I	: bit;
+signal SHFT_LOAD_ND_I	: bit;
+signal WR_In			: bit;
+signal TR_PRES_I		: bit;
+signal TR_CLR_I			: bit;
+signal TR_INC_I			: bit;
+signal TR_DEC_I			: bit;
+signal SR_LOAD_I		: bit;
+signal SR_INC_I			: bit;
+signal DR_CLR_I			: bit;
+signal DR_LOAD_I		: bit;
+signal TRACK_NR_I		: std_logic_vector(7 downto 0);
+signal CRC_2_DISK_I		: bit;
+signal DSR_2_DISK_I		: bit;
+signal FF_2_DISK_I		: bit;
+signal PRECOMP_EN_I		: bit;
+signal DISK_RWn_I		: bit;
+signal WDATA_I			: bit;
+begin
+	-- Three state data bus:
+	DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0');
+	DATA_EN <= DATA_EN_REG;
+
+	-- Some signals copied to the outputs:
+    WD <= not WR_In;
+	MO <= MO_I;
+	DRQ <= DRQ_I;
+
+	-- Write deleted data address mark in MFM mode in 'Write Sector' command in
+	-- case of asserted command bit 0.
+	AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1';
+
+	-- The CRC unit is used during read from disk and write to disk.
+	-- This is the data multiplexer for the data stream to encode.
+	CRC_SD_I <= SD_R_I when DISK_RWn_I = '1' else WDATA_I;
+
+	I_CONTROL: WF1772IP_CONTROL
+		port map(
+            CLK				=> CLK,
+			RESETn			=> RESETn,
+			A1				=> A0,
+			A0				=> A1,
+			RWn				=> RWn,
+			CSn				=> CSn,
+			DDEn			=> DDEn,
+			DR				=> DR_I,
+			CMD				=> CMD_I,
+			DSR				=> DSR_I,
+			TR				=> TR_I,
+			SR				=> SR_I,
+			MO				=> MO_I,
+			WR_PR			=> WR_PR_I,
+			SPINUP_RECTYPE	=> SP_RT_I,
+			SEEK_RNF		=> SEEK_RNF_I,
+			CRC_ERRFLAG		=> CRC_ERRFLAG_I,
+			LOST_DATA_TR00	=> LD_TR00_I,
+			DRQ				=> DRQ_I,
+			DRQ_IPn			=> DRQ_IPn_I,
+			BUSY			=> BUSY_I,
+			AM_2_DISK		=> AM_2_DISK_I,
+			ID_AM			=> ID_AM_I,
+			DATA_AM			=> DATA_AM_I,
+			DDATA_AM		=> DDATA_AM_I,
+			CRC_ERR			=> CRC_ERR_I,
+			CRC_PRES		=> CRC_PRES_I,
+			TR_PRES			=> TR_PRES_I,
+			TR_CLR			=> TR_CLR_I,
+			TR_INC			=> TR_INC_I,
+			TR_DEC			=> TR_DEC_I,
+			SR_LOAD			=> SR_LOAD_I,
+			SR_INC			=> SR_INC_I,
+			TRACK_NR		=> TRACK_NR_I,
+			DR_CLR			=> DR_CLR_I,
+			DR_LOAD			=> DR_LOAD_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			SHFT_LOAD_ND	=> SHFT_LOAD_ND_I,
+			CRC_2_DISK		=> CRC_2_DISK_I,
+			DSR_2_DISK		=> DSR_2_DISK_I,
+			FF_2_DISK		=> FF_2_DISK_I,
+			PRECOMP_EN		=> PRECOMP_EN_I,
+			DATA_STRB		=> DATA_STRB_I,
+			DISK_RWn		=> DISK_RWn_I,
+			WPRTn			=> WPRTn,
+			TRACK00n		=> TR00n,
+			IPn				=> IPn,
+			DIRC			=> DIRC,
+			STEP			=> STEP,
+			WG				=> WG,
+			INTRQ			=> INTRQ
+		);
+
+	I_REGISTERS: WF1772IP_REGISTERS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			CSn				=> CSn,
+			ADR(1)			=> A1,
+			ADR(0)			=> A0,
+			RWn				=> RWn,
+			DATA_IN			=> DATA_IN,
+			DATA_OUT		=> DATA_OUT_REG,
+			DATA_EN			=> DATA_EN_REG,
+			CMD				=> CMD_I,
+			TR				=> TR_I,
+			SR				=> SR_I,
+			DSR				=> DSR_I,
+			DR				=> DR_I,
+			SD_R			=> SD_R_I,
+			DATA_STRB		=> DATA_STRB_I,
+			DR_CLR			=> DR_CLR_I,
+			DR_LOAD			=> DR_LOAD_I,
+			TR_PRES			=> TR_PRES_I,
+			TR_CLR			=> TR_CLR_I,
+			TR_INC			=> TR_INC_I,
+			TR_DEC			=> TR_DEC_I,
+			TRACK_NR		=> TRACK_NR_I,
+			SR_LOAD			=> SR_LOAD_I,
+			SR_INC			=> SR_INC_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			SHFT_LOAD_ND	=> SHFT_LOAD_ND_I,
+			MOTOR_ON		=> MO_I,
+			WRITE_PROTECT	=> WR_PR_I,
+			SPINUP_RECTYPE	=> SP_RT_I,
+			SEEK_RNF		=> SEEK_RNF_I,
+			CRC_ERRFLAG		=> CRC_ERRFLAG_I,
+			LOST_DATA_TR00	=> LD_TR00_I,
+			DRQ				=> DRQ_I,
+			DRQ_IPn			=> DRQ_IPn_I,
+			BUSY			=> BUSY_I,
+			DDEn			=> DDEn
+		);
+
+	I_DIGITAL_PLL: WF1772IP_DIGITAL_PLL
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			HDTYPE 		=> HDTYPE,
+			DISK_RWn	=> DISK_RWn_I,
+			RDn			=> RDn,
+			PLL_D		=> PLL_D_I,
+			PLL_DSTRB	=> PLL_DSTRB_I
+		);
+
+	I_AM_DETECTOR: WF1772IP_AM_DETECTOR
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			DATA		=> PLL_D_I,
+			DATA_STRB	=> PLL_DSTRB_I,
+			ID_AM		=> ID_AM_I,
+			DATA_AM		=> DATA_AM_I,
+			DDATA_AM	=> DDATA_AM_I
+		);
+
+	I_CRC_LOGIC: WF1772IP_CRC_LOGIC
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			DISK_RWn	=> DISK_RWn_I,
+			ID_AM		=> ID_AM_I,
+			DATA_AM		=> DATA_AM_I,
+			DDATA_AM	=> DDATA_AM_I,
+			SD			=> CRC_SD_I,
+			CRC_STRB	=> DATA_STRB_I,
+			CRC_2_DISK	=> CRC_2_DISK_I,
+			CRC_PRES	=> CRC_PRES_I,
+			CRC_SDOUT	=> CRC_SDOUT_I,
+			CRC_ERR		=> CRC_ERR_I
+		);
+
+	I_TRANSCEIVER: WF1772IP_TRANSCEIVER
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DDEn			=> DDEn,
+			HDTYPE 			=> HDTYPE,
+			ID_AM			=> ID_AM_I,
+			DATA_AM			=> DATA_AM_I,
+			DDATA_AM		=> DDATA_AM_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			DR				=> DR_I,
+			PRECOMP_EN		=> PRECOMP_EN_I,
+			AM_TYPE			=> AM_TYPE_I,
+			AM_2_DISK		=> AM_2_DISK_I,
+			CRC_2_DISK		=> CRC_2_DISK_I,
+			DSR_2_DISK		=> DSR_2_DISK_I,
+			FF_2_DISK		=> FF_2_DISK_I,
+			SR_SDOUT		=> DSR_I(7),
+			CRC_SDOUT		=> CRC_SDOUT_I,
+			WRn				=> WR_In,
+			WDATA			=> WDATA_I,
+			PLL_DSTRB		=> PLL_DSTRB_I,
+			PLL_D			=> PLL_D_I,
+			DATA_STRB		=> DATA_STRB_I,
+			SD_R			=> SD_R_I
+		);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
new file mode 100644
index 0000000..c836716
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
@@ -0,0 +1,517 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The transceiver unit contains on the one hand the receiver   ----
+---- part which strips off the clock signal from the data stream  ----
+---- and on the other hand the transmitter unit which provides in ----
+---- the different modes (FM and MFM) all functions which are     ----
+---- necessary to send data, CRC bytes, 'FF', '00' or the address ----
+---- marks.                                                       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   MFM_In and MASK_SHFT have now synchronous reset to meet preset requirement.
+-- 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TRANSCEIVER is
+	port(
+		-- System control
+		CLK		: in bit; -- must be 16MHz
+		RESETn	: in bit;
+
+		-- Data and Control:
+		HDTYPE			: in bit; -- Floppy type HD or DD.
+		DDEn			: in bit; -- Double density select (FM or MFM).
+		ID_AM			: in bit; -- ID addressmark strobe.
+		DATA_AM			: in Bit; -- Data addressmark strobe.
+		DDATA_AM		: in Bit; -- Deleted data addressmark strobe.
+		SHFT_LOAD_SD	: in bit; -- Indication for shift register load time.
+		DR				: in bit_vector(7 downto 0); -- Content of the data register.
+
+		-- Data strobes:
+		PLL_DSTRB	: in bit; -- Clock strobe for RD serial data input.
+		DATA_STRB 	: buffer bit;
+		
+		-- Data strobe and data for the CRC during write operation:
+		WDATA 		: buffer bit;
+
+		-- Encoder (logic to disk):
+		PRECOMP_EN	: in bit; -- control signal for MFM write precompensation.
+		AM_TYPE		: in bit; -- Write deleted address mark in MFM mode when 0.
+		AM_2_DISK	: in bit;
+		DSR_2_DISK	: in bit;
+		FF_2_DISK	: in bit;
+		CRC_2_DISK	: in bit;
+		SR_SDOUT	: in std_logic; -- encoder's data input from the shift register (serial).
+		CRC_SDOUT	: in bit; -- encoder's data input from the CRC unit (serial).
+		WRn			: out bit; -- write output for the MFM drive containing clock and data.
+
+		-- Decoder (disk to logic):
+		PLL_D		: in bit; -- Serial data input.
+		SD_R		: out bit -- Serial (decoded) data output.
+	);
+end WF1772IP_TRANSCEIVER;
+
+architecture BEHAVIOR of WF1772IP_TRANSCEIVER is
+type MFM_STATES is (A_00, B_01, C_10);
+type PRECOMP_VALUES is (EARLY, NOMINAL, LATE);
+type DEC_STATES is (CLK_PHASE, DATA_PHASE);
+
+signal MFM_STATE		: MFM_STATES;
+signal NEXT_MFM_STATE	: MFM_STATES;
+signal PRECOMP			: PRECOMP_VALUES;
+signal DEC_STATE		: DEC_STATES;
+signal NEXT_DEC_STATE	: DEC_STATES;
+
+signal FM_In			: bit;
+
+signal CLKMASK 			: bit; -- Control for suppression of FM clock transitions.
+
+signal MFM_10_STRB		: bit;
+signal MFM_01_STRB		: bit;
+
+signal WR_CNT 			: std_logic_vector(3 downto 0);
+signal MFM_In			: bit;
+
+signal AM_SHFT			: bit_vector(31 downto 0);
+
+begin
+	-- #######################  encoder stuff  ###########################
+	ADRMARK: process(RESETn, CLK)
+	-- This process provides the address mark data for both FM and MFM in
+	-- write to disk mode. In FM only one byte is written where in MFM
+	-- 3 sync bytes x"A1" and one data address mark is written. 
+	-- In this process only the data address mark is provided. The only way
+	-- writing the ID address mark is the write track command.
+	begin
+		if RESETn = '0' then
+			AM_SHFT <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if AM_2_DISK = '1' and DATA_STRB = '1' then
+				AM_SHFT <= AM_SHFT (30 downto 0) & '0'; -- Shift out.
+			elsif AM_2_DISK = '0' and DDEn = '1'  and AM_TYPE = '0' then -- FM mode.
+				AM_SHFT <= x"F8000000"; -- Load deleted FM address mark.
+			elsif AM_2_DISK = '0' and DDEn = '1'  and AM_TYPE = '1' then -- FM mode.
+				AM_SHFT <= x"FB000000"; -- Load normal FM address mark.
+			elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '0' then -- MFM mode deleted data mark.
+				AM_SHFT <= x"A1A1A1F8"; -- Load MFM syncs and address mark.
+			elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '1' then -- Default: MFM mode normal data mark.
+				AM_SHFT <= x"A1A1A1FB"; -- Load MFM syncs and address mark.
+			end if;
+		end if;
+	end process ADRMARK;
+
+	-- Input multiplexer:
+	WDATA <= 	AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data.
+				To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
+				CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data.
+				'1' when FF_2_DISK = '1' else '0'; -- Write zeros is default.
+
+	-- Output multiplexer:
+	WRn <= 	'0' when FM_In = '0' and DDEn = '1' else -- FM portion.
+			'0' when MFM_In = '0' and DDEn = '0' else '1'; -- MFM portion and default.
+
+	CLK_MASK: process(CLK)
+	-- This part of software controls the suppression of the clock pulses
+	-- during transmission of several FM special characters. During writing
+	-- 'normal' data to the disk, only 8 mask bits of the shift register are
+	-- used. During writing MFM sync and address mark bits, the register is
+	-- used with 32 mask bits.
+	variable MASK_SHFT	: bit_vector(23 downto 0);
+	variable LOCK		: boolean;
+	begin
+		if CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				MASK_SHFT := (others => '1');
+				LOCK := false;
+			-- Load the mask shift register just in time when the shift register is
+			-- loaded with valid data from the data register.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '1' then -- FM mode.
+				case DR is
+					when x"F8" | x"F9" | x"FA" | x"FB" | x"FE" => MASK_SHFT := x"C7FFFF";
+					when x"FC" => MASK_SHFT := x"D7FFFF";
+					when x"F5" | x"F6" => MASK_SHFT := (others => '0'); -- Not allowed.
+					when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
+				end case;
+			elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode.
+				case DR is
+					when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5.
+					when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4.
+					when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
+				end case;
+			elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode.
+				MASK_SHFT := x"C7FFFF"; -- Load just once per AM_2_DISK rising edge.
+				LOCK := true;
+			elsif AM_2_DISK = '1' and DDEn = '0' and LOCK = false then -- MFM mode.
+				MASK_SHFT := x"FBFBFB"; -- Three syncs with suppressed clock pulse then transparent mask.
+				LOCK := true;
+			elsif DATA_STRB = '1' then  -- shift as long as transmission is active
+				-- The Shift register is shifted left. After shifting the clockmasks out it is
+				-- transparent due to the '1's filled up from the left.
+				MASK_SHFT := MASK_SHFT(22 downto 0) & '1'; -- Shift left.
+			elsif AM_2_DISK = '0' then
+				LOCK := false; -- Release the lock after address mark has been written.
+			end if;
+		end if;
+		CLKMASK <= MASK_SHFT(23);
+	end process CLK_MASK;
+
+	FM_ENCODER: process (RESETn, DATA_STRB, CLK)
+	-- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles
+	-- per FM bit. 
+	-- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles
+	-- per FM bit. 
+	-- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies.
+	-- This process provides the FM encoded signal. The first pulse is in any case the clock
+	-- pulse and the second pulse is due to data. The FM encoding is very simple and therefore
+	-- self explaining.
+	variable CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			FM_In <= '1';
+			CNT := x"00";
+		elsif CLK = '1' and CLK' event then
+			-- In case of HD type floppies the counter reaches a value of b"0100000"
+			-- In case of DD type floppies the counter reaches a value of b"1000000"
+			if DATA_STRB = '1' then
+				CNT := x"00";
+			else
+				CNT := CNT + '1';
+			end if;
+			-- The flux reversal pulses are centered between the DATA_STRB pulses.
+			-- In detail: the clock pulse appears in the middle of the first half
+			-- of the DATA_STRB period and the data pulse appears in the middle of
+			-- the second half.
+			case HDTYPE is
+				when '0' => -- DD type floppies:
+					if CNT > "00010101" and CNT <= "00101011" then
+						FM_In <= not CLKMASK; -- FM clock.
+					elsif CNT > "01010101" and CNT <= "01101011" then
+						FM_In <= not WDATA; -- FM data.
+					else
+						FM_In <= '1';
+					end if;
+				when '1' => -- HD type floppies:
+					if CNT > "00001010" and CNT <= "00010110" then
+						FM_In <= not CLKMASK; -- FM clock.
+					elsif CNT > "00101010" and CNT <= "00110110" then
+						FM_In <= not WDATA; -- FM data.
+					else
+						FM_In <= '1';
+					end if;
+			end case;
+		end if;
+	end process FM_ENCODER;
+	
+	MFM_ENCODE_REG: process(RESETn, CLK)
+	-- This process is the first portion of the more complicated MFM encoder. It can be interpreted
+	-- as a Moore machine. This part is the current state register.
+	begin
+		if RESETn = '0' then
+			MFM_STATE <= A_00;
+		elsif CLK = '1' and CLK' event then
+			MFM_STATE <= NEXT_MFM_STATE;
+		end if;
+	end process MFM_ENCODE_REG;
+
+	MFM_ENCODE_LOGIC: process(MFM_STATE, WDATA, DATA_STRB)
+	-- Rules for Encoding:
+		-- transitions are never located at the mid point of a 'zero'.
+		-- transistions are always located at the mid point of a '1'.
+		-- no transitions at the borders of a '1'.
+		-- transitions appear between two adjacent 'zeros'.
+	-- states are as follows:
+	-- A_00: idle state, no transition.
+	-- B_01: transistion between the MFM clock edges.
+	-- C_10: transition on the leading MFM clock edges.
+	-- The timing of the MFM output is done in the process MFM_WR_OUT.
+	begin
+		case MFM_STATE is
+			when A_00 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= C_10;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= A_00; -- Stay, if there is no strobe.
+				end if;
+			when C_10 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= C_10;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= C_10; -- Stay, if there is no strobe.
+				end if;
+			when B_01 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= A_00;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= B_01; -- Stay, if there is no strobe.
+				end if;
+		end case;
+	end process MFM_ENCODE_LOGIC;
+
+	MFM_PRECOMPENSATION: process(RESETn, CLK)
+	-- The write pattern is adjusted in the MFM write timing process as follows:
+	-- after DATA_STRB (the duty cycle of this strobe is exactly one CLK) the
+	-- incoming data is bufferd in WRITEPATTERN. After the following DATA_STRB
+	-- the WDATA is shifted through WRITEPATTERN. After further DATA_STRBs the
+	-- WRITEPATTERN consists of previous, current and next WDATA like this:
+	-- WRITEPATTERN(3) is the second previous WDATA.
+	-- WRITEPATTERN(2) is the previous WDATA.
+	-- WRITEPATTERN(1) is the current WDATA to be sent.
+	-- WRITEPATTERN(0) is the next WDATA to be sent.
+	variable WRITEPATTERN : bit_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			PRECOMP <= NOMINAL;
+			WRITEPATTERN := "0000";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				WRITEPATTERN := WRITEPATTERN(2 downto 0) & WDATA; -- shift left
+			end if;
+			if PRECOMP_EN = '0' then
+				PRECOMP <= NOMINAL; -- no precompensation
+			else
+				case WRITEPATTERN is
+					when "1110" | "0110" => PRECOMP <= EARLY;
+					when "1011" | "0011" => PRECOMP <= LATE;
+					when "0001" => PRECOMP <= EARLY;
+					when "1000" => PRECOMP <= LATE;
+					when others => PRECOMP <= NOMINAL;
+				end case;
+			end if;
+		end if;
+	end process MFM_PRECOMPENSATION;
+
+	MFM_STROBES: process (RESETn, DATA_STRB, CLK)
+	-- For the MFM frequency is 250 kBps for DD type floppies, there are 64 
+	-- 16 MHz clock cycles per MFM bit and for HD type floppies, which have
+	-- 500 kBps there are 32 16MHz clock pulses for one MFM bit.
+	-- The MFM state machine (Moore) switches on the DATA_STRB. 
+	-- During one cycle there are the two further strobes MFM_10_STRB and 
+	-- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT.
+	-- The strobes are centered in the middle of the first half and in the
+	-- middle of the second half of the DATA_STRB cycle.
+	variable CNT : std_logic_vector(5 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := "000000";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				CNT := (others => '0');
+			else
+				CNT := CNT + '1';
+			end if;
+			if HDTYPE = '1' then
+				case CNT is
+					-- encoder timing for MFM and HD type floppies.
+				when "000100" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half.
+				when "010100" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half.
+					when others =>  MFM_10_STRB <= '0'; MFM_01_STRB <= '0';
+				end case;
+			else
+				case CNT is
+					-- encoder timing for MFM and DD type floppies.
+				when "001010" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half.
+				when "101000" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half.
+					when others =>  MFM_10_STRB <= '0'; MFM_01_STRB <= '0';
+				end case;
+			end if;
+		end if;
+	end process MFM_STROBES;
+
+	-- MFM_WR_TIMING generates the timing for the write pulses which are 
+	-- required by a MFM device like floppy disk drive. The pulse timing 
+	-- meets the timing of the MFM data with pulse width of 700ns +/- 100ns 
+	-- depending on write precompensation.
+	-- The original WD1772 (CLK = 8MHz) data timing was as follows:
+	-- The output is asserted as long as CNT is active; in detail
+	-- this are 4,5; 5,5 or 6,5 CLK cycles depending on the write
+	-- precompensation.
+	-- The new design which works with a 16MHz clock requires the following
+	-- timing: 9; 11 or 13 CLK cycles depending on the writeprecompensation
+	-- for DD floppies and 5; 6 or 7 CLK cycles depending on the write
+	-- precompensation for HD floppies.
+	-- To meet the timing requirements of half clocks
+	-- the WRn is controlled by the following three processes where the one
+	-- syncs on the positive clock edge and the other on the negative.
+	-- For more information on the WTn timing see the datasheet of the
+	-- WD177x floppy disc controller.
+
+	MFM_WR_TIMING: process(RESETn, CLK)
+	variable CLKMASK_MFM	: bit;
+	begin
+		if RESETn = '0' then
+			WR_CNT <= x"F";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				-- The CLKMASK_MFM is synchronised to DATA_STRB. This brings one strobe latency.
+				-- The timing in connection with the data is correct because the MFM encoder state machine
+				-- causes the data to be 1 DATA_STRB late too.
+				CLKMASK_MFM := CLKMASK;
+			end if;
+			if MFM_STATE = C_10 and MFM_10_STRB = '1' and CLKMASK_MFM = '1' then
+				WR_CNT <= x"0";
+			elsif MFM_STATE =  B_01 and MFM_01_STRB = '1' then
+				WR_CNT <= x"0";
+			elsif WR_CNT < x"F" then
+				WR_CNT <= WR_CNT + '1';
+			end if;
+		end if;
+	end process MFM_WR_TIMING;
+
+	MFM_WR_OUT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			MFM_In <= '1';
+		else
+			case HDTYPE is
+				when '1' => -- HD type.
+					if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"9" then
+						MFM_In <= '0'; -- 9,0 clock cycles for WRn --> early timing
+					elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"8" then
+						MFM_In <= '0'; -- 8,0 clock cycles for WRn --> nominal timing
+					elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"7" then
+						MFM_In <= '0'; -- 7,0 clock cycles for WRn --> late timing
+					else
+						MFM_In <= '1';
+					end if;
+				when '0' => -- DD type.
+					if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"D" then
+						MFM_In <= '0'; -- 13,0 clock cycles for WRn --> early timing
+					elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"B" then
+						MFM_In <= '0'; -- 11,0 clock cycles for WRn --> nominal timing
+					elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"9" then
+						MFM_In <= '0'; -- 9,0 clock cycles for WRn --> late timing
+					else
+						MFM_In <= '1';
+					end if;
+			end case;
+		end if;
+	end process MFM_WR_OUT;
+
+	-- #######################  Decoder stuff  ###########################
+	-- The decoding of the serial FM or MFM encoded data stream
+	-- is done in the following two processes (Moore machine).
+	-- The decoder works in principle like a simple toggle Flip-Flop.
+	-- It is important to synchronise it in a way, that the clock
+	-- pulses are separated from the data pulses. The principle
+	-- works for both FM and MFM data due to the digital phase
+	-- locked loop, which delivers the serial data and the clock
+	-- strobe. In general this decoder can be understood as the
+	-- data separator where the digital phase locked loop provides
+	-- the FM or the MFM decoding. The data separation lives from
+	-- the fact, that FM and also MFM encoded signals consist of a
+	-- mixture of alternating data and clock pulses. 
+	-- FM works as follows:
+	-- every first pulse of the FM signal is a clock pulse and every
+	-- second pulse is a logic '1' of the data. A missing second 
+	-- pulse represents a logic '0' of the data.
+	-- MFM works as follows:
+	-- every first pulse of the MFM signal is a clock pulse. The coding
+	-- principle causes clock pulses to be absent in some conditions.
+	-- Every second pulse is a logic '1' of the data. A missing second 
+	-- pulse represents a logic '0' of the data.
+	-- So FM and MFM compared, the data is represented directly by the
+	-- second pulses and the data separator has to look only for these.
+	-- The missing MFM clock pulses do not cause a problem because the
+	-- digital PLL used in conjunction with this data separator fills
+	-- up the clock pulses and delivers a PLL_DSTRB containing aequidistant
+	-- clock strobes and data strobes.
+
+	DEC_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DEC_STATE <= CLK_PHASE;
+		elsif CLK = '1' and CLK' event then
+			DEC_STATE <= NEXT_DEC_STATE;
+		end if;
+	end process DEC_REG;
+
+	DEC_LOGIC: process(DEC_STATE, ID_AM, DATA_AM, DDATA_AM, PLL_DSTRB, PLL_D)
+	begin
+		case DEC_STATE is
+			when CLK_PHASE =>
+				if PLL_DSTRB = '1' then
+					NEXT_DEC_STATE <= DATA_PHASE;
+				else
+					NEXT_DEC_STATE <= CLK_PHASE;
+				end if;
+				DATA_STRB <= '0'; -- Inactive during clock pulse time.
+				SD_R <= '0'; -- Inactive during clock pulse time.
+			when DATA_PHASE =>
+				if ID_AM = '1' or DATA_AM = '1' or DDATA_AM = '1' then
+					-- Here the state machine is synchronised
+					-- to separate data and clock pulses correctly.
+					NEXT_DEC_STATE <= CLK_PHASE;
+				elsif PLL_DSTRB = '1' then
+					NEXT_DEC_STATE <= CLK_PHASE;
+				else
+					NEXT_DEC_STATE <= DATA_PHASE;
+				end if;
+				-- During the data phase valid data appears at SD.
+				-- The data is valid during DATA_STRB.
+				DATA_STRB <= PLL_DSTRB;
+				SD_R <= PLL_D;
+		end case;
+	end process DEC_LOGIC;
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
new file mode 100644
index 0000000..7660aa2
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
@@ -0,0 +1,141 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This are the SUSKA MFP IP core's general purpose I/Os.       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_GPIO is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Timer controls:
+			AER_4		: out bit;
+			AER_3		: out bit;
+
+			GPIP_IN		: in bit_vector(7 downto 0);
+			GPIP_OUT	: out bit_vector(7 downto 0);
+			GPIP_OUT_EN	: buffer bit_vector(7 downto 0);
+			GP_INT		: out bit_vector(7 downto 0)
+	);
+end entity WF68901IP_GPIO;
+
+architecture BEHAVIOR of WF68901IP_GPIO is
+signal GPDR		: bit_vector(7 downto 0);
+signal DDR		: bit_vector(7 downto 0);
+signal AER		: bit_vector(7 downto 0);
+signal GPDR_I	: bit_vector(7 downto 0);
+begin
+	-- These two bits control the timers A and B pulse width operation and the
+	-- timers A and B event count operation.
+	AER_4 <= AER(4);
+	AER_3 <= AER(3);
+	-- This statement provides 8 XOR units setting the desired interrupt polarity.
+	-- While the level control is done here, the edge triggering is provided by
+	-- the interrupt control hardware. The level control is individually for each
+	-- GPIP port pin. The interrupt edge trigger unit must operate in any case on
+	-- the low to high transistion of the respective port pin.
+	GP_INT <= AER xnor GPIP_IN;
+	
+	GPIO_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GPDR <= (others => '0');
+			DDR <= (others => '0');
+			AER <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "00000"	=> GPDR <= DATA_IN;
+					when "00001"	=> AER <= DATA_IN;
+					when "00010"	=> DDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+		end if;
+	end process GPIO_REGISTERS;
+	GPIP_OUT <= GPDR; -- Port outputs.
+	GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP.
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0';
+	DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else
+				AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else
+				GPDR_I when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00000" else (others => '0');
+	
+	P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR)
+	-- Read back control: Read the port pins, if the data direction is configured as input.
+	-- Read the respective GPDR register bit, if the data direction is configured as output.
+	begin
+		for i in 7 downto 0 loop
+			if GPIP_OUT_EN(i) = '1' then -- Port is configured output.
+				GPDR_I(i) <= GPDR(i);
+			else
+				GPDR_I(i) <= GPIP_IN(i); -- Port is configured input.
+			end if;
+		end loop;
+	end process P_GPDR;
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
new file mode 100644
index 0000000..91417f8
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
@@ -0,0 +1,391 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core interrupt logic file.          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/06/03 WF
+--   Fixed Pending register logic.
+-- Revision 2K9A  2009/06/20 WF
+--   Fixed interrupt polarity for TA_I and TB_I.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_INTERRUPTS is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out bit;
+			
+			-- Interrupt sources:
+			GP_INT		: in bit_vector(7 downto 0);
+
+			AER_4		: in bit;
+			AER_3		: in bit;
+			TAI			: in bit;
+			TBI			: in bit;
+			TA_PWM		: in bit;
+			TB_PWM		: in bit;
+			TIMER_A_INT	: in bit;
+			TIMER_B_INT	: in bit;
+			TIMER_C_INT	: in bit;
+			TIMER_D_INT	: in bit;
+
+			RCV_ERR		: in bit;
+			TRM_ERR		: in bit;
+			RCV_BUF_F	: in bit;
+			TRM_BUF_E	: in bit
+	);
+end entity WF68901IP_INTERRUPTS;
+
+architecture BEHAVIOR of WF68901IP_INTERRUPTS is
+-- Interrupt state machine:
+type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
+signal INT_STATE : INT_STATES;
+-- The registers:
+signal IERA			: bit_vector(7 downto 0);
+signal IERB			: bit_vector(7 downto 0);
+signal IPRA			: bit_vector(7 downto 0);
+signal IPRB			: bit_vector(7 downto 0);
+signal ISRA			: bit_vector(7 downto 0);
+signal ISRB			: bit_vector(7 downto 0);
+signal IMRA			: bit_vector(7 downto 0);
+signal IMRB			: bit_vector(7 downto 0);
+signal VR			: bit_vector(7 downto 3);
+-- Interconnect:
+signal VECT_NUMBER	: bit_vector(7 downto 0);
+signal INT_SRC		: bit_vector(15 downto 0);
+signal INT_SRC_EDGE	: bit_vector(15 downto 0);
+signal INT_ENA		: bit_vector(15 downto 0);
+signal INT_MASK		: bit_vector(15 downto 0);
+signal INT_PENDING	: bit_vector(15 downto 0);
+signal INT_SERVICE	: bit_vector(15 downto 0);
+signal INT_PASS		: bit_vector(15 downto 0);
+signal INT_OUT		: bit_vector(15 downto 0);
+signal GP_INT_4		: bit;
+signal GP_INT_3		: bit;
+begin
+	-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
+	-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
+	-- to timer A and timer B.
+	-- The xor logic provides polarity control for the interrupt transition. Be aware,
+	-- that the PWM signals cause an interrupt on the opposite transition like the
+	-- respective GPIP port pins (with the same AER settings).
+    --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4;
+    --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3;
+    GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct.
+    GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3;
+
+
+	-- Interrupt source priority sorted (15 = highest):
+    INT_SRC <= 	GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & 
+    GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0);
+
+	INT_ENA 	<= IERA & IERB;
+	INT_MASK 	<= IMRA & IMRB;
+	INT_PENDING <= IPRA & IPRB;
+	INT_SERVICE <= ISRA & ISRB;
+	INT_OUT 	<= INT_PENDING and INT_MASK; -- Masking:
+
+	-- Enable the daisy chain, if there is no pending interrupt and
+	-- the interrupt state machine is not in service.
+	IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
+
+	-- Interrupt request:
+	IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
+
+	EDGE_ENA: process(RESETn, CLK)
+	-- These are the 16 edge detectors of the 16 interrupt input sources. This
+	-- process also provides the disabling or enabling via the IERA and IERB registers.
+	variable LOCK : bit_vector(15 downto 0);
+	begin
+		if RESETn = '0' then
+			INT_SRC_EDGE <= x"0000";
+			LOCK := x"0000";
+		elsif CLK = '1' and CLK' event then
+			for i in 15 downto 0 loop
+				if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then
+					LOCK(i) := '1';
+					INT_SRC_EDGE(i) <= '1';
+				elsif INT_SRC(i) = '0' then
+					LOCK(i) := '0';
+					INT_SRC_EDGE(i) <= '0';
+				else
+					INT_SRC_EDGE(i) <= '0';
+				end if;
+			end loop;
+		end if;
+	end process EDGE_ENA;
+	
+	INT_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			IERA <= (others => '0');
+			IERB <= (others => '0');
+			IPRA <= (others => '0');
+			IPRB <= (others => '0');
+			ISRA <= (others => '0');
+			ISRB <= (others => '0');
+			IMRA <= (others => '0');
+			IMRB <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "00011"	=> IERA <= DATA_IN; -- Enable A.
+					when "00100"	=> IERB <= DATA_IN; -- Enable B.
+					when "00101"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRA(i) <= '0'; -- Pending A.
+							end if;
+						end loop;
+					when "00110"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRB(i) <= '0'; -- Pending B.
+							end if;
+						end loop;
+					when "00111"	=> 
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRA(i) <= '0'; -- In Service A.
+							end if;
+						end loop;
+					when "01000"	=>
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRB(i) <= '0'; -- In Service B.
+							end if;
+						end loop;
+					when "01001"	=> IMRA <= DATA_IN; -- Mask A.
+					when "01010"	=> IMRB <= DATA_IN; -- Mask B.
+					when "01011"	=> VR <= DATA_IN(7 downto 3); -- Vector register.
+					when others		=> null;
+				end case;
+			end if;
+
+			-- Pending register:
+			-- set and clear bit logic.
+			for i in 15 downto 8 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRA(i-8) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRA(i-8) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRA(i-8) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRB(i) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRB(i) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRB(i) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+
+			-- In-Service register:
+			-- Set bit logic, VR(3) is the service register enable.
+			for i in 15 downto 8 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRA(i-8) <= '1';
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRB(i) <= '1';
+				end if;
+			end loop;
+		end if;
+	end process INT_REGISTERS;
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else 																	 '1' when INT_STATE = VECTOR_OUT else '0';
+
+	DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else
+				IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else
+				IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else
+				IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else
+				ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else
+				ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else
+				IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else
+				IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else
+				VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else
+				VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00";
+
+	P_INT_STATE	: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_STATE <= SCAN;
+		elsif CLK = '1' and CLK' event then
+			case INT_STATE is
+				when SCAN =>
+					INT_PASS <= x"0000";
+					-- Automatic End of Interrupt mode. Service register disabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0").
+					if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then
+						INT_STATE <= REQUEST; -- Non masked interrupt is pending.
+					-- The following 16 are the Software end of interrupt mode. Service register enabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized.
+					elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then
+						if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then
+							INT_STATE <= REQUEST;
+						else
+							INT_STATE <= SCAN; -- Wait for interrupt.
+						end if;
+					else
+						INT_STATE <= SCAN;
+					end if;
+				when REQUEST =>
+					if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode.
+						INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending.
+						if INT_OUT(15) = '1' then 
+							INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7.
+						elsif INT_OUT(14) = '1' then 
+							INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6.
+						elsif INT_OUT(13) = '1' then 
+							INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A.
+						elsif INT_OUT(12) = '1' then 
+							INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full.
+						elsif INT_OUT(11) = '1' then 
+							INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error.
+						elsif INT_OUT(10) = '1' then 
+							INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty.
+						elsif INT_OUT(9) = '1' then 
+							INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error.
+						elsif INT_OUT(8) = '1' then 
+							INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B.
+						elsif INT_OUT(7) = '1' then 
+							INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5.
+						elsif INT_OUT(6) = '1' then 
+							INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4.
+						elsif INT_OUT(5) = '1' then 
+							INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C.
+						elsif INT_OUT(4) = '1' then 
+							INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D.
+						elsif INT_OUT(3) = '1' then 
+							INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3.
+						elsif INT_OUT(2) = '1' then 
+							INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2.
+						elsif INT_OUT(1) = '1' then 
+							INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1.
+						elsif INT_OUT(0) = '1' then 
+							INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0.
+						end if;
+					 -- Polled interrupt mode: End of interrupt by writing to the pending registers.
+					elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then
+						INT_STATE <= SCAN;
+					else
+						INT_STATE <= REQUEST; -- Wait.
+					end if;
+				when VECTOR_OUT =>
+					INT_PASS <= x"0000";
+					if DSn = '1' or IACKn = '1' then
+						INT_STATE <= SCAN; -- Finished.
+					else
+						INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector.
+					end if;
+			end case;
+		end if;
+	end process P_INT_STATE;
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
new file mode 100644
index 0000000..73c0cdc
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
@@ -0,0 +1,263 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF68901IP_PKG is
+component WF68901IP_USART_TOP
+	port (  CLK			: in bit;
+			RESETn		: in bit;
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out bit;
+			SO_EN		: out bit;
+			RX_ERR_INT	: out bit;
+			RX_BUFF_INT	: out bit;
+			TX_ERR_INT	: out bit;
+			TX_BUFF_INT	: out bit;
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end component;
+
+component WF68901IP_USART_CTRL
+	port (
+		CLK				: in bit;
+        RESETn			: in bit;
+        DSn				: in bit;
+        CSn				: in bit;   
+        RWn     		: in bit;
+        RS				: in bit_vector(5 downto 1);
+        DATA_IN			: in bit_vector(7 downto 0);   
+        DATA_OUT		: out bit_vector(7 downto 0);   
+		DATA_OUT_EN		: out bit;
+		RX_SAMPLE		: in bit;
+        RX_DATA			: in bit_vector(7 downto 0);   
+        TX_DATA			: out bit_vector(7 downto 0);   
+        SCR_OUT			: out bit_vector(7 downto 0);   
+		BF				: in bit;
+		BE				: in bit;
+		FE				: in bit;
+		OE				: in bit;
+		UE				: in bit;
+		PE				: in bit;
+		M_CIP			: in bit;
+		FS_B			: in bit;
+		TX_END			: in bit;
+		CL				: out bit_vector(1 downto 0);
+		ST				: out bit_vector(1 downto 0);
+		FS_CLR			: out bit;
+		RSR_READ		: out bit;
+		TSR_READ		: out bit;
+		UDR_READ		: out bit;
+		UDR_WRITE		: out bit;
+		LOOPBACK		: out bit;
+		SDOUT_EN		: out bit;
+		SD_LEVEL		: out bit;
+		CLK_MODE		: out bit;
+		RE				: out bit;
+		TE				: out bit;
+		P_ENA			: out bit;
+		P_EOn			: out bit;
+		SS				: out bit;
+		BR				: out bit
+	);                                              
+end component;
+
+component WF68901IP_USART_TX
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+		SCR			: in bit_vector(7 downto 0);
+		TX_DATA		: in bit_vector(7 downto 0);
+        SDATA_OUT	: out bit;
+        TXCLK		: in bit;
+		CL			: in bit_vector(1 downto 0);
+		ST			: in bit_vector(1 downto 0);
+		TE			: in bit;
+		BR			: in bit;
+		P_ENA		: in bit;
+		P_EOn		: in bit;
+		UDR_WRITE	: in bit;
+		TSR_READ	: in bit;
+		CLK_MODE	: in bit;
+		TX_END		: out bit;
+		UE			: out bit;
+		BE			: out bit
+	);                                              
+end component;
+
+component WF68901IP_USART_RX
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+		SCR			: in bit_vector(7 downto 0);
+		RX_SAMPLE	: out bit;
+        RX_DATA	  	: out bit_vector(7 downto 0);   
+        RXCLK		: in bit;
+        SDATA_IN	: in bit;
+		CL			: in bit_vector(1 downto 0);
+		ST			: in bit_vector(1 downto 0);
+		P_ENA		: in bit;
+		P_EOn		: in bit;
+		CLK_MODE	: in bit;
+		RE			: in bit;
+		FS_CLR		: in bit;
+		SS			: in bit;
+		RSR_READ	: in bit;
+		UDR_READ	: in bit;
+		M_CIP		: out bit;
+		FS_B		: out bit;
+		BF			: out bit;
+		OE			: out bit;
+		PE			: out bit;
+		FE			: out bit
+	);                                              
+end component;
+
+component WF68901IP_INTERRUPTS
+	port ( 	
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		IACKn		: in bit;
+		IEIn		: in bit;
+		IEOn		: out bit;
+		IRQn		: out bit;
+		GP_INT		: in bit_vector(7 downto 0);
+		AER_4		: in bit;
+		AER_3		: in bit;
+		TAI			: in bit;
+		TBI			: in bit;
+		TA_PWM		: in bit;
+		TB_PWM		: in bit;
+		TIMER_A_INT	: in bit;
+		TIMER_B_INT	: in bit;
+		TIMER_C_INT	: in bit;
+		TIMER_D_INT	: in bit;
+		RCV_ERR		: in bit;
+		TRM_ERR		: in bit;
+		RCV_BUF_F	: in bit;
+		TRM_BUF_E	: in bit
+	);
+end component;
+
+component WF68901IP_GPIO
+	port (  
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		AER_4		: out bit;
+		AER_3		: out bit;
+		GPIP_IN		: in bit_vector(7 downto 0);
+		GPIP_OUT	: out bit_vector(7 downto 0);
+		GPIP_OUT_EN	: out bit_vector(7 downto 0);
+		GP_INT		: out bit_vector(7 downto 0)
+	);
+end component;
+
+component WF68901IP_TIMERS
+	port (  
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		XTAL1		: in bit;
+		TAI			: in bit;
+		TBI			: in bit;
+		AER_4		: in bit;
+		AER_3		: in bit;
+		TA_PWM		: out bit;
+		TB_PWM		: out bit;
+		TAO			: out bit;			
+		TBO			: out bit;			
+		TCO			: out bit;			
+		TDO			: out bit;
+		TIMER_A_INT	: out bit;
+		TIMER_B_INT	: out bit;
+		TIMER_C_INT	: out bit;
+		TIMER_D_INT	: out bit
+	);
+end component;
+
+end WF68901IP_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
new file mode 100644
index 0000000..b339af5
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
@@ -0,0 +1,533 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core timers logic file.             ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7A	2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8A	2008/02/29 WF
+--   Fixed a serious prescaler bug.
+-- Revision 2K9A 20090620 WF
+--   Introduced timer readback registers.
+--   TIMER_x_INT is now a strobe.
+--   Minor improvements.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TIMERS is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			AER_4		: in bit;
+			AER_3		: in bit;
+			TA_PWM		: out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
+			TB_PWM		: out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
+			TAO			: buffer bit;
+			TBO			: buffer bit;
+			TCO			: buffer bit;
+			TDO			: buffer bit;
+			TIMER_A_INT	: out bit;
+			TIMER_B_INT	: out bit;
+			TIMER_C_INT	: out bit;
+			TIMER_D_INT	: out bit
+	);
+end entity WF68901IP_TIMERS;
+
+architecture BEHAVIOR of WF68901IP_TIMERS is
+signal XTAL1_S		: bit;
+signal XTAL_STRB	: bit;
+signal TACR			: bit_vector(4 downto 0); -- Timer A control register.
+signal TBCR			: bit_vector(4 downto 0); -- Timer B control register.
+signal TCDCR		: bit_vector(5 downto 0); -- Timer C and D control register.
+signal TADR			: bit_vector(7 downto 0); -- Timer A data register.
+signal TBDR			: bit_vector(7 downto 0); -- Timer B data register.
+signal TCDR			: bit_vector(7 downto 0); -- Timer C data register.
+signal TDDR			: bit_vector(7 downto 0); -- Timer D data register.
+signal TIMER_A 		: std_logic_vector(7 downto 0); -- Timer A count register.
+signal TIMER_B 		: std_logic_vector(7 downto 0); -- Timer B count register.
+signal TIMER_C 		: std_logic_vector(7 downto 0); -- Timer C count register.
+signal TIMER_D 		: std_logic_vector(7 downto 0); -- Timer D count register.
+signal TIMER_R_A    : bit_vector(7 downto 0); -- Timer A readback register.
+signal TIMER_R_B    : bit_vector(7 downto 0); -- Timer B readback register.
+signal TIMER_R_C    : bit_vector(7 downto 0); -- Timer C readback register.
+signal TIMER_R_D    : bit_vector(7 downto 0); -- Timer D readback register.
+signal A_CNTSTRB	: bit;
+signal B_CNTSTRB	: bit;
+signal C_CNTSTRB	: bit;
+signal D_CNTSTRB	: bit;
+signal TAI_I		: bit;
+signal TBI_I		: bit;
+signal TAI_STRB		: bit; -- Strobe for the event counter mode.
+signal TBI_STRB		: bit; -- Strobe for the event counter mode.
+signal TAO_I		: bit; -- Timer A output signal.
+signal TBO_I		: bit; -- Timer A output signal.
+begin
+	SYNC: process
+	-- This process provides a 'clean' XTAL1.
+	-- Without this sync, the edge detector for
+	-- XTAL_STRB does not work properly.
+	begin
+		wait until CLK = '1' and CLK' event;
+		XTAL1_S <= XTAL1;
+        -- Polarity control for the event counter and the PWM mode:
+        TAI_I <= TAI xnor AER_4;
+        TBI_I <= TBI xnor AER_3;
+	end process SYNC;
+	
+	-- Output enables for timer A and timer B:
+	-- The outputs are held low for asserted reset flags in the control registers TACR
+	-- and TBCR but also during a write operation to these registers.
+	TAO <=	'0' when TACR(4) = '1' else
+			'0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01100" else TAO_I;
+	TBO <=	'0' when TBCR(4) = '1' else
+			'0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01101" else TBO_I;
+
+	-- Control outputs for the PWM modi of the timers A and B. These
+	-- controls are used in the interrupt logic to select the interrupt
+	-- sources GPIP4 or TAI repective GPIP3 or TBI.
+	TA_PWM <= '1' when TACR(3 downto 0) > x"8" else '0';
+	TB_PWM <= '1' when TBCR(3 downto 0) > x"8" else '0';
+
+	TIMER_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TACR <= (others => '0');
+			TBCR <= (others => '0');
+			TCDCR <= (others => '0');
+			-- TADR <= Do not clear during reset!
+			-- TBDR <= Do not clear during reset!
+			-- TCDR <= Do not clear during reset!
+			-- TDDR <= Do not clear during reset!
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "01100"	=> TACR <= DATA_IN(4 downto 0);
+					when "01101"	=> TBCR <= DATA_IN(4 downto 0);
+					when "01110"	=> TCDCR <= DATA_IN(6 downto 4) & DATA_IN(2 downto 0);
+					when "01111"	=> TADR <= DATA_IN;
+					when "10000"	=> TBDR <= DATA_IN;
+					when "10001"	=> TCDR <= DATA_IN;
+					when "10010"	=> TDDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+		end if;
+	end process TIMER_REGISTERS;
+
+    TIMER_READBACK	: process(RESETn, CLK)
+    -- This process provides the readback information for the
+    -- timers A to D. The information read is the information
+    -- last clocked into the timer read register when the DSn
+    -- pin had last gone high prior to the current read cycle.
+    variable READ_A : boolean;
+    variable READ_B : boolean;
+    variable READ_C : boolean;
+    variable READ_D : boolean;
+    begin
+        if RESETn = '0' then
+            TIMER_R_A <= x"00";
+            TIMER_R_B <= x"00";
+            TIMER_R_C <= x"00";
+            TIMER_R_D <= x"00";
+        elsif CLK = '1' and CLK' event then
+            if DSn = '0' and RS = "01111" then
+                READ_A := true;
+            elsif DSn = '0' and RS = "10000" then
+                READ_B := true;
+            elsif DSn = '0' and RS = "10001" then
+                READ_C := true;
+            elsif DSn = '0' and RS = "10010" then
+                READ_D := true;
+            elsif DSn = '1' and READ_A = true then
+                TIMER_R_A <= To_BitVector(TIMER_A);
+                READ_A := false;
+            elsif DSn = '1' and READ_B = true then
+                TIMER_R_B <= To_BitVector(TIMER_B);
+                READ_B := false;
+            elsif DSn = '1' and READ_C = true then
+                TIMER_R_C <= To_BitVector(TIMER_C);
+                READ_C := false;
+            elsif DSn = '1' and READ_D = true then
+                TIMER_R_D <= To_BitVector(TIMER_D);
+                READ_D := false;
+            end if;
+        end if;
+    end process TIMER_READBACK;
+
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "01011" and RS <= "10010" else '0';
+	DATA_OUT <= "000" & TACR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01100" else
+				"000" & TBCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01101" else
+				'0' & TCDCR(5 downto 3) & '0' & TCDCR(2 downto 0) when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01110" else
+				TIMER_R_A when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01111" else
+				TIMER_R_B when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10000" else
+				TIMER_R_C when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10001" else
+				TIMER_R_D when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10010" else (others => '0');
+
+	XTAL_STROBE: process(RESETn, CLK)
+	-- This process provides a strobe with 1 clock cycle
+	-- (CLK) length after every rising edge of XTAL1.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			XTAL_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if XTAL1_S = '1' and LOCK = false then
+				XTAL_STRB <= '1';
+				LOCK := true;
+			elsif XTAL1_S = '0' then
+				XTAL_STRB <= '0';
+				LOCK := false;
+			else
+				XTAL_STRB <= '0';
+			end if;
+		end if;
+	end process XTAL_STROBE;
+
+	TAI_STROBE: process(RESETn, CLK)
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			TAI_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if TAI_I = '1' and XTAL_STRB = '1' and LOCK = false then
+				LOCK := true;
+				TAI_STRB <= '1';
+			elsif TAI_I = '0' then
+				LOCK := false;
+				TAI_STRB <= '0';
+			else
+				TAI_STRB <= '0';
+			end if;
+		end if;
+	end process TAI_STROBE;
+
+	TBI_STROBE: process(RESETn, CLK)
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			TBI_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if TBI_I = '1' and XTAL_STRB = '1' and LOCK = false then
+				LOCK := true;
+				TBI_STRB <= '1';
+			elsif TBI_I = '0' then
+				LOCK := false;
+				TBI_STRB <= '0';
+			else
+				TBI_STRB <= '0';
+			end if;
+		end if;
+	end process TBI_STROBE;
+
+	PRESCALE_A: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		A_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TACR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+			end case;
+			A_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_A;
+
+	PRESCALE_B: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		B_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TBCR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+			end case;
+			B_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_B;
+
+	PRESCALE_C: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		C_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TCDCR(5 downto 3) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped.
+			end case;
+			C_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_C;
+
+	PRESCALE_D: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		D_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TCDCR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped.
+			end case;
+			D_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_D;
+
+	TIMERA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TAO_I <= '0';
+			TIMER_A_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_A_INT <= '0';
+            --
+			if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_A <= To_StdLogicVector(DATA_IN);
+			else
+				case TACR(3 downto 0) is
+					when x"0" => -- Timer is off.
+                        TAO_I <= '0';
+					when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
+						if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+					when x"8" => -- Event count operation.
+						if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+					when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
+						if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERA;
+
+	TIMERB: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TBO_I <= '0';
+			TIMER_B_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_B_INT <= '0';
+            --
+			if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_B <= To_StdLogicVector(DATA_IN);
+			else
+				case TBCR(3 downto 0) is
+					when x"0" => -- Timer is off.
+                        TBO_I <= '0';
+					when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
+						if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+					when x"8" => -- Event count operation.
+						if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+					when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
+						if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERB;
+
+	TIMERC: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TCO <= '0';
+			TIMER_C_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_C_INT <= '0';
+            --
+			if 	CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_C <= To_StdLogicVector(DATA_IN);
+			else
+				case TCDCR(5 downto 3) is
+					when "000" => -- Timer is off.
+                        TCO <= '0';
+					when others => -- Delay counter mode.
+						if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count.
+							TIMER_C <= TIMER_C - '1';
+						elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload.
+							TIMER_C <= To_StdLogicVector(TCDR);
+							TCO <= not TCO; -- Toggle the timer C output pin.
+							TIMER_C_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERC;
+
+	TIMERD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TDO <= '0';
+			TIMER_D_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_D_INT <= '0';
+            --
+ 			if 	CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_D <= To_StdLogicVector(DATA_IN);
+			else
+				case TCDCR(2 downto 0) is
+					when "000" => -- Timer is off.
+                        TDO <= '0';
+					when others => -- Delay counter mode.
+						if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count.
+							TIMER_D <= TIMER_D - '1';
+						elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload.
+							TIMER_D <= To_StdLogicVector(TDDR);
+							TDO <= not TDO; -- Toggle the timer D output pin.
+							TIMER_D_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
new file mode 100644
index 0000000..783ba56
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
@@ -0,0 +1,213 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core top level file.                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7A	2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TOP is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			DTACKn		: out std_logic;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA		: inout std_logic_vector(7 downto 0);
+			GPIP		: inout std_logic_vector(7 downto 0);
+			
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out std_logic;
+			
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			TAO			: out bit;			
+			TBO			: out bit;			
+			TCO			: out bit;			
+			TDO			: out bit;			
+			
+			-- Serial I/O control:
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out std_logic;
+			
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_TOP;
+
+architecture STRUCTURE of WF68901IP_TOP is
+component WF68901IP_TOP_SOC
+	port(CLK			: in bit;
+         RESETn		    : in bit;
+         DSn			: in bit;
+         CSn			: in bit;
+         RWn			: in bit;
+         DTACKn		    : out bit;
+         RS			    : in bit_vector(5 downto 1);
+         DATA_IN		: in std_logic_vector(7 downto 0);
+         DATA_OUT	    : out std_logic_vector(7 downto 0);
+         DATA_EN		: out bit;
+         GPIP_IN		: in bit_vector(7 downto 0);
+         GPIP_OUT	    : out bit_vector(7 downto 0);
+         GPIP_EN		: out bit_vector(7 downto 0);
+         IACKn		    : in bit;
+         IEIn		    : in bit;
+         IEOn		    : out bit;
+         IRQn		    : out bit;
+         XTAL1		    : in bit;
+         TAI			: in bit;
+         TBI			: in bit;
+         TAO			: out bit;			
+         TBO			: out bit;			
+         TCO			: out bit;			
+         TDO			: out bit;			
+         RC			    : in bit;
+         TC			    : in bit;
+         SI			    : in bit;
+         SO			    : out bit;
+         SO_EN		    : out bit;
+         RRn			: out bit;
+         TRn			: out bit			
+	);
+end component;
+--
+signal DTACK_In         : bit;
+signal IRQ_In           : bit;
+signal DATA_OUT         : std_logic_vector(7 downto 0);
+signal DATA_EN          : bit;
+signal GPIP_IN          : bit_vector(7 downto 0);
+signal GPIP_OUT         : bit_vector(7 downto 0);
+signal GPIP_EN          : bit_vector(7 downto 0);
+signal SO_I             : bit;
+signal SO_EN            : bit;
+begin
+    DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
+    IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
+
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+
+    GPIP_IN <= To_BitVector(GPIP);
+
+	P_GPIP_OUT: process(GPIP_OUT, GPIP_EN)
+	begin
+		for i in 7 downto 0 loop
+			if GPIP_EN(i) = '1' then
+				case GPIP_OUT(i) is
+					when '0' => GPIP(i) <= '0';
+					when others => GPIP(i) <= '1';
+				end case;
+			else
+				GPIP(i) <= 'Z';
+			end if;
+		end loop;
+	end process P_GPIP_OUT;
+
+    SO <= '0' when SO_I = '0' and SO_EN = '1' else
+          '1' when SO_I = '1' and SO_EN = '1' else 'Z';
+
+    I_MFP: WF68901IP_TOP_SOC
+        port map(CLK            => CLK,
+                 RESETn         => RESETn,
+                 DSn            => DSn,
+                 CSn            => CSn,
+                 RWn            => RWn,
+                 DTACKn         => DTACK_In,
+                 RS             => RS,
+                 DATA_IN        => DATA,
+                 DATA_OUT       => DATA_OUT,
+                 DATA_EN        => DATA_EN,
+                 GPIP_IN        => GPIP_IN,
+                 GPIP_OUT       => GPIP_OUT,
+                 GPIP_EN        => GPIP_EN,
+                 IACKn          => IACKn,
+                 IEIn           => IEIn,
+                 IEOn           => IEOn,
+                 IRQn           => IRQ_In,
+                 XTAL1          => XTAL1,
+                 TAI            => TAI,
+                 TBI            => TBI,
+                 TAO            => TAO,
+                 TBO            => TBO,
+                 TCO            => TCO,
+                 TDO            => TDO,
+                 RC             => RC,
+                 TC             => TC,
+                 SI             => SI,
+                 SO             => SO_I,
+                 SO_EN          => SO_EN,
+                 RRn            => RRn,
+                 TRn            => TRn
+        );
+end architecture STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
new file mode 100644
index 0000000..1e559d9
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
@@ -0,0 +1,309 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core top level file.                ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K7A  2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   DTACK_OUTn has now synchronous reset to meet preset requirement.
+--
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TOP_SOC is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			DTACKn		: out bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out bit;
+			GPIP_IN		: in bit_vector(7 downto 0);
+			GPIP_OUT	: out bit_vector(7 downto 0);
+			GPIP_EN		: out bit_vector(7 downto 0);
+			
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out bit;
+			
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			TAO			: out bit;			
+			TBO			: out bit;			
+			TCO			: out bit;			
+			TDO			: out bit;			
+			
+			-- Serial I/O control:
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out bit;
+			SO_EN		: out bit;
+			
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_TOP_SOC;
+
+architecture STRUCTURE of WF68901IP_TOP_SOC is
+signal DATA_IN_I				: bit_vector(7 downto 0);
+signal DTACK_In					: bit;
+signal DTACK_LOCK				: boolean;
+signal DTACK_OUTn				: bit;
+signal RX_ERR_INT_I				: bit;
+signal TX_ERR_INT_I				: bit;
+signal RX_BUFF_INT_I			: bit;
+signal TX_BUFF_INT_I			: bit;
+signal DATA_OUT_USART_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_USART_I		: bit;
+signal DATA_OUT_INT_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_INT_I		: bit;
+signal DATA_OUT_GPIO_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_GPIO_I		: bit;
+signal DATA_OUT_TIMERS_I		: bit_vector(7 downto 0);
+signal DATA_OUT_EN_TIMERS_I		: bit;
+signal SO_I						: bit;
+signal SO_EN_I					: bit;
+signal GPIP_IN_I				: bit_vector(7 downto 0);
+signal GPIP_OUT_I				: bit_vector(7 downto 0);
+signal GPIP_EN_I				: bit_vector(7 downto 0);
+signal GP_INT_I					: bit_vector(7 downto 0);
+signal TIMER_A_INT_I			: bit;
+signal TIMER_B_INT_I			: bit;
+signal TIMER_C_INT_I			: bit;
+signal TIMER_D_INT_I			: bit;
+signal IRQ_In					: bit;
+signal AER_4_I					: bit;
+signal AER_3_I					: bit;
+signal TA_PWM_I					: bit;
+signal TB_PWM_I					: bit;
+begin
+	-- Interrupt request (open drain):
+	IRQn <= IRQ_In;
+
+	-- Serial data output:
+	SO <= 	SO_I;
+	SO_EN <= SO_EN_I and RESETn;
+
+	-- General purpose port:
+	GPIP_IN_I	<= GPIP_IN;
+	GPIP_OUT <= GPIP_OUT_I;
+	GPIP_EN <= GPIP_EN_I;
+
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I;
+	-- Output data multiplexer:
+	DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else
+				To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else
+				To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else
+				To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
+
+	-- Data acknowledge handshake is provided by the following statement and the consecutive two
+	-- processes. For more information refer to the M68000 family reference manual.
+	DTACK_In <= '0' when CSn = '0' and DSn = '0' and RS <= "10111" else -- Read and write operation.
+				'0' when IACKn = '0' and DSn = '0' and IEIn = '0' else '1'; -- Interrupt vector data acknowledge.
+
+	P_DTACK_LOCK: process
+	-- This process releases a data acknowledge detect, one rising clock
+	-- edge after the DTACK_In occured. This is necessary to ensure write
+	-- data to registers for there is one rising clock edge required.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if DTACK_In = '0' then
+			DTACK_LOCK <= false;
+		else
+			DTACK_LOCK <= true;
+		end if;
+	end process P_DTACK_LOCK;
+
+	DTACK_OUT: process
+	-- The DTACKn port pin is released on the falling clock edge after the data
+	-- acknowledge detect (DTACK_LOCK) is asserted. The DTACKn is deasserted
+	-- immediately when there is no further register access DTACK_In = '1';
+	begin
+		wait until CLK = '0' and CLK' event;
+		if RESETn = '0' then
+			DTACK_OUTn <= '1';
+		elsif DTACK_In = '1' then
+			DTACK_OUTn <= '1';
+		elsif DTACK_LOCK = false then
+			DTACK_OUTn <= '0';
+		end if;
+	end process DTACK_OUT;
+	DTACKn <= '0' when DTACK_OUTn = '0' else '1';
+
+	I_USART: WF68901IP_USART_TOP
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_USART_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_USART_I,
+			RC				=> RC,
+			TC				=> TC,
+			SI				=> SI,
+			SO				=> SO_I,
+			SO_EN			=> SO_EN_I,
+			RX_ERR_INT		=> RX_ERR_INT_I,
+			RX_BUFF_INT		=> RX_BUFF_INT_I,
+			TX_ERR_INT		=> TX_ERR_INT_I,
+			TX_BUFF_INT		=> TX_BUFF_INT_I,
+			RRn				=> RRn,
+			TRn				=> TRn
+		);
+
+	I_INTERRUPTS: WF68901IP_INTERRUPTS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_INT_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_INT_I,
+			IACKn			=> IACKn,
+			IEIn			=> IEIn,
+			IEOn			=> IEOn,
+			IRQn			=> IRQ_In,
+			GP_INT			=> GP_INT_I,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			TAI				=> TAI,
+			TBI				=> TBI,
+			TA_PWM 			=> TA_PWM_I,
+			TB_PWM 			=> TB_PWM_I,
+			TIMER_A_INT		=> TIMER_A_INT_I,
+			TIMER_B_INT		=> TIMER_B_INT_I,
+			TIMER_C_INT		=> TIMER_C_INT_I,
+			TIMER_D_INT		=> TIMER_D_INT_I,
+			RCV_ERR			=> RX_ERR_INT_I,
+			TRM_ERR			=> TX_ERR_INT_I,
+			RCV_BUF_F		=> RX_BUFF_INT_I,
+			TRM_BUF_E		=> TX_BUFF_INT_I
+     	 );
+
+	I_GPIO: WF68901IP_GPIO
+		port map(  
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_GPIO_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_GPIO_I,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			GPIP_IN			=> GPIP_IN_I,
+			GPIP_OUT		=> GPIP_OUT_I,
+			GPIP_OUT_EN		=> GPIP_EN_I,
+			GP_INT			=> GP_INT_I
+      	);
+
+	I_TIMERS: WF68901IP_TIMERS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_TIMERS_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_TIMERS_I,
+			XTAL1			=> XTAL1,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			TAI				=> TAI,
+			TBI				=> TBI,
+			TAO				=> TAO,
+			TBO				=> TBO,
+			TCO				=> TCO,
+			TDO				=> TDO,
+			TA_PWM 			=> TA_PWM_I,
+			TB_PWM 			=> TB_PWM_I,
+			TIMER_A_INT		=> TIMER_A_INT_I,
+			TIMER_B_INT		=> TIMER_B_INT_I,
+			TIMER_C_INT		=> TIMER_C_INT_I,
+			TIMER_D_INT		=> TIMER_D_INT_I
+      	);
+end architecture STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
new file mode 100644
index 0000000..8e7c3cc
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
@@ -0,0 +1,191 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART control file.            ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_CTRL is
+	port (
+		-- System Control:
+		CLK				: in bit;
+        RESETn			: in bit;
+
+		-- Bus control:
+        DSn				: in bit;
+        CSn				: in bit;   
+        RWn     		: in bit;
+        RS				: in bit_vector(5 downto 1);
+        DATA_IN			: in bit_vector(7 downto 0);   
+        DATA_OUT		: out bit_vector(7 downto 0);   
+		DATA_OUT_EN		: out bit;
+
+		-- USART data register
+		RX_SAMPLE		: in bit;
+        RX_DATA			: in bit_vector(7 downto 0);
+        TX_DATA			: out bit_vector(7 downto 0);   
+        SCR_OUT			: out bit_vector(7 downto 0);   
+
+		-- USART control inputs:
+		BF				: in bit;
+		BE				: in bit;
+		FE				: in bit;
+		OE				: in bit;
+		UE				: in bit;
+		PE				: in bit;
+		M_CIP			: in bit;
+		FS_B			: in bit;
+		TX_END			: in bit;
+
+		-- USART control outputs:
+		CL				: out bit_vector(1 downto 0);
+		ST				: out bit_vector(1 downto 0);
+		FS_CLR			: out bit;
+		UDR_WRITE		: out bit;
+		UDR_READ		: out bit;
+		RSR_READ		: out bit;
+		TSR_READ		: out bit;
+		LOOPBACK		: out bit;
+		SDOUT_EN		: out bit;
+		SD_LEVEL		: out bit;
+		CLK_MODE		: out bit;
+		RE				: out bit;
+		TE				: out bit;
+		P_ENA			: out bit;
+		P_EOn			: out bit;
+		SS				: out bit;
+		BR				: out bit
+       );                                              
+end entity WF68901IP_USART_CTRL;
+
+architecture BEHAVIOR of WF68901IP_USART_CTRL is
+signal SCR	: bit_vector(7 downto 0); -- Synchronous data register.
+signal UCR	: bit_vector(7 downto 1); -- USART control register.
+signal RSR	: bit_vector(7 downto 0); -- Receiver status register.
+signal TSR	: bit_vector(7 downto 0); -- Transmitter status register.
+signal UDR	: bit_vector(7 downto 0); -- USART data register.
+begin
+	USART_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SCR <= (others => '0');
+			UCR <= (others => '0');
+			RSR <= (others => '0');
+			-- TSR and UDR are not cleared during an asserted RESETn
+		elsif CLK = '1' and CLK' event then
+			-- Loading via receiver shift register
+			-- has priority over data buss access:
+			if RX_SAMPLE = '1' then
+				UDR <= RX_DATA;
+			elsif 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "10011"	=> SCR <= DATA_IN;
+					when "10100"	=> UCR <= DATA_IN(7 downto 1);
+					when "10101"	=> RSR(1 downto 0) <= DATA_IN(1 downto 0); -- Only the two LSB are read/write.
+					when "10110"	=> TSR(5) <= DATA_IN(5); TSR(3 downto 0) <= DATA_IN(3 downto 0);
+					when "10111"	=> UDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+			RSR(7 downto 2) <= BF & OE & PE & FE & FS_B & M_CIP;
+			TSR(7 downto 6) <= BE & UE;
+			TSR(4) <= TX_END;
+			TX_DATA <= UDR;		
+		end if;
+	end process USART_REGISTERS;
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS >= "10011" and RS <= "10111" else '0';
+	DATA_OUT <= SCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10011" else
+				UCR & '0' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10100" else
+				RSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else
+				TSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else
+				UDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else x"00";
+
+	UDR_WRITE 	<= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10111" else '0';
+	UDR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else '0';
+	RSR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else '0';
+	TSR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else '0';
+	FS_CLR		<= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10011" else '0';
+
+	RE <= '1' when RSR(0) = '1' else -- Receiver enable.
+		  '1' when TSR(5) = '1' and TX_END = '1' else '0'; -- Auto Turnaround.
+	SS <= RSR(1); -- Synchronous strip enable.
+	BR <= TSR(3); -- Send break.
+	TE <= TSR(0); -- Transmitter enable.
+
+	SCR_OUT <= SCR;
+
+	CLK_MODE <= UCR(7); -- Clock mode.
+	CL <= UCR(6 downto 5); -- Character length.
+	ST <= UCR(4 downto 3); -- Start/Stop configuration.
+	P_ENA <= UCR(2); -- Parity enable.
+	P_EOn <= UCR(1); -- Even or odd parity.
+	
+	SOUT_CONFIG: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		-- Do not change the output configuration until the transmitter is disabled and
+		-- current character has been transmitted (TX_END = '1').
+		if TX_END = '1' then
+			case TSR(2 downto 1) is
+				when "00" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '0';
+				when "01" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '1';
+				when "10" => LOOPBACK <= '0'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
+				when "11" => LOOPBACK <= '1'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
+			end case;			
+		end if;
+	end process SOUT_CONFIG;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
new file mode 100644
index 0000000..eb00a11
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
@@ -0,0 +1,590 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART receiver file.           ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+-- Process P_STARTBIT has now synchronous reset to meet preset requirement.
+-- Process P_SAMPLE has now synchronous reset to meet preset requirement.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_RX is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+		SCR			: in bit_vector(7 downto 0); -- Synchronous character. 
+		RX_SAMPLE	: buffer bit; -- Flag indicating valid shift register data.
+        RX_DATA		: out bit_vector(7 downto 0); -- Received data.
+
+        RXCLK		: in bit; -- Receiver clock.
+        SDATA_IN	: in bit; -- Serial data input.
+
+		CL			: in bit_vector(1 downto 0); -- Character length.
+		ST			: in bit_vector(1 downto 0); -- Start and stop bit configuration.
+		P_ENA		: in bit; -- Parity enable.
+		P_EOn		: in bit; -- Even or odd parity.
+		CLK_MODE	: in bit; -- Clock mode configuration bit.
+		RE			: in bit; -- Receiver enable.
+		FS_CLR		: in bit; -- Clear the Found/Search flag for resynchronisation purpose.
+		SS			: in bit; -- Synchronous strip enable.
+		UDR_READ	: in bit; -- Flag indicating reading the data register.
+		RSR_READ	: in bit; -- Flag indicating reading the receiver status register.
+
+		M_CIP		: out bit; -- Match/Character in progress.
+		FS_B		: buffer bit; -- Find/Search or Break detect flag.
+		BF			: out bit; -- Buffer full.
+		OE			: out bit; -- Overrun error.
+		PE			: out bit; -- Parity error.
+		FE			: out bit  -- Framing error.
+       );                                              
+end entity WF68901IP_USART_RX;
+
+architecture BEHAVIOR of WF68901IP_USART_RX is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal SDATA_DIV16					: bit;
+signal SDATA_IN_I					: bit;
+signal SDATA_EDGE					: bit;
+signal SHIFT_REG					: bit_vector(7 downto 0);
+signal CLK_STRB						: bit;
+signal CLK_2_STRB					: bit;
+signal BITCNT						: std_logic_vector(2 downto 0);
+signal BREAK						: boolean;
+signal RDRF							: bit;
+signal STARTBIT						: boolean;
+begin
+	BF <= RDRF; -- Buffer full = Receiver Data Register Full.
+	RX_SAMPLE <= '1' when RCV_STATE = SYNC and ST /= "00" else -- Asynchronous mode:
+			     -- Synchronous modes:
+				 '1' when RCV_STATE = SYNC and ST = "00" and SS = '0' else
+			     '1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0';
+
+	-- Data multiplexer for the received data:
+	RX_DATA <= 	"000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits.
+				"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits.
+				'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits.
+				SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits.
+
+	P_SAMPLE: process
+	-- This process provides the 'valid transition logic' of the originally MC68901. For further
+	-- details see the 'M68000 FAMILY REFERENCE MANUAL'.
+	variable LOW_FLT		: std_logic_vector(1 downto 0);
+	variable HI_FLT			: std_logic_vector(1 downto 0);
+	variable CLK_LOCK		: boolean;
+	variable EDGE_LOCK		: boolean;
+	variable TIMER			: std_logic_vector(2 downto 0);
+	variable TIMER_LOCK		: boolean;
+	variable NEW_SDATA 		: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' or RE = '0' then
+			-- The reset condition assumes the SDATA_IN logic high. Otherwise
+			-- one not valid SDATA_EDGE pulse occurs during system startup.
+			CLK_LOCK := true;
+			EDGE_LOCK := true;
+			HI_FLT := "11";
+			LOW_FLT := "11";
+			SDATA_EDGE <= '0';
+			NEW_SDATA := '1';
+		-- Positive or negative edge detector for the incoming data.
+		-- Any transition must be valid for at least three receiver clock
+		-- cycles. The TIMER locking inhibits detecting four receiver
+		-- clock cycles after a valid transition.
+		elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then
+			CLK_LOCK := true;
+			EDGE_LOCK := false;
+			HI_FLT := "00";
+			LOW_FLT := LOW_FLT - '1';
+		elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then
+			CLK_LOCK := true;
+			EDGE_LOCK := false;
+			LOW_FLT := "11";
+			HI_FLT := HI_FLT + '1';
+		elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then
+			EDGE_LOCK := true;
+			SDATA_EDGE <= '1'; -- Falling edge detected.
+			NEW_SDATA := '0';
+		elsif RXCLK = '1' and EDGE_LOCK = false and HI_FLT = "11" then
+			EDGE_LOCK := true;
+			SDATA_EDGE <= '1'; -- Rising edge detected.
+			NEW_SDATA := '1';
+		elsif RXCLK = '1' and CLK_LOCK = false then
+			CLK_LOCK := true;
+			SDATA_EDGE <= '0';
+		elsif RXCLK = '0' then
+			CLK_LOCK := false;
+		end if;
+		--
+		if RESETn = '0' or RE = '0' then
+			-- The reset condition assumes the SDATA_IN logic high. Otherwise
+			-- one not valid SDATA_EDGE pulse occurs during system startup.
+			TIMER := "111";
+			TIMER_LOCK := true;
+			SDATA_DIV16 <= '1';
+		-- The timer controls the SDATA in a way, that after a detected valid
+		-- Transistion, the serial data is sampled on the 8th receiver clock
+		-- edge after the initial valid transition occured.
+		elsif RXCLK = '1' and SDATA_EDGE = '1' and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			TIMER := "000"; -- Resynchronisation.
+		elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			SDATA_DIV16 <= NEW_SDATA; -- Scan the new data.
+			TIMER := TIMER + '1'; -- Timing is active.
+		elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			TIMER := TIMER + '1'; -- Timing is active.
+		elsif RXCLK = '0' then
+			TIMER_LOCK := false;
+		end if;
+	end process P_SAMPLE;
+
+	P_START_BIT: process(CLK)
+	-- This is the valid start bit logic of the original MC68901 multi function
+	-- port's USART receiver.
+	variable TMP	: std_logic_vector(2 downto 0);
+	variable LOCK 	: boolean;
+	begin
+		if CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				TMP := "000";
+				LOCK := true;
+			elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled.
+				TMP := "000";
+				LOCK := true;
+			elsif SDATA_EDGE = '1' then
+				TMP := "000"; -- (Re)-Initialize.
+				LOCK := false; -- Start counting.
+			elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then
+				LOCK := true;
+				TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid.
+			elsif RXCLK = '0' then
+				LOCK := false;
+			end if;
+		end if;
+
+		case TMP is
+			when "111" => STARTBIT <= true;
+			when others => STARTBIT <= false;
+		end case;
+	end process P_START_BIT;
+
+	SDATA_IN_I <= 	SDATA_IN when CLK_MODE = '0' else -- Clock div by 1 mode.
+					SDATA_IN when ST = "00" else SDATA_DIV16; -- Synchronous mode.
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(4 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CLK_MODE = '0' then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+			CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
+		elsif SDATA_EDGE = '1' then
+CLK_DIVCNT := "01100"; -- Div by 16 mode.
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+		else
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+			if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_LOCK := true;
+				if CLK_DIVCNT = "01000" then
+					-- This strobe is asserted at half of the clock cycle.
+					-- It is used for the stop bit timing.
+					CLK_2_STRB <= '1';
+				end if;
+			elsif CLK_DIVCNT = "00000" then
+				CLK_DIVCNT := "10000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= SDATA_IN_I & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_M_CIP: process(RESETn, CLK)
+	-- In Synchronous mode this flag indicates wether a synchronous character M_CIP = '1' 
+	-- or another character (M_CIP = '0') is transferred to the receive buffer.
+	-- In asynchronous mode the flag indicates sampling condition.
+	begin
+		if RESETn = '0' then
+			M_CIP <= '0';
+		elsif CLK = '0' and CLK' event then
+			if RE = '0' then
+				M_CIP <= '0';
+			elsif ST = "00" then -- Synchronous mode.
+				if RCV_STATE = SYNC and SHIFT_REG = SCR and RDRF = '0' then
+					M_CIP <= '1'; -- SCR transferred.
+				elsif RCV_STATE = SYNC and RDRF = '0' then
+					M_CIP <= '0'; -- No SCR transferred.
+				end if;
+			else -- Asynchronous mode.
+				case RCV_STATE is
+					when SAMPLE | PARITY | STOP1 | STOP2 => M_CIP <= '1'; -- Sampling.
+					when others => M_CIP <= '0'; -- No Sampling.
+				end case;
+			end if;
+		end if;
+	end process P_M_CIP;
+
+	BREAK_DETECT: process(RESETn, CLK)
+	-- A break condition occurs, if there is no  STOP1 bit and the
+	-- shift register contains zero data.
+	begin
+		if RESETn = '0' then
+			BREAK <= false;
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				BREAK <= false;
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then
+					BREAK <= true; -- Break detected (empty shift register and no stop bit).
+				elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then
+					BREAK <= false; -- UPDATE.
+				elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					BREAK <= false; -- UPDATE, but framing error.
+				end if;
+			end if;
+		end if;
+	end process BREAK_DETECT;
+
+	P_FS_B: process(RESETn, CLK)
+	-- In the synchronous mode, this process provides the flag detecting the synchronous 
+	-- character. In the asynchronous mode, the flag indicates a break condition.
+	variable FS_B_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			FS_B <= '0';
+			FIRST_READ := false;
+			FS_B_I := '0';
+		elsif CLK = '0' and CLK' event then
+			if RE = '0' then
+				FS_B <= '0';
+				FS_B_I := '0';
+			else
+				if ST = "00" then -- Synchronous operation.
+					if FS_CLR = '1' then
+						FS_B <= '0'; -- Clear during writing to the SCR.
+					elsif SHIFT_REG = SCR then
+						FS_B <= '1'; -- SCR detected.
+					end if;
+				else -- Asynchronous operation.
+					if RX_SAMPLE = '1' and BREAK = true then -- Break condition detected.
+						FS_B_I := '1'; -- Update.
+					elsif RX_SAMPLE = '1' then -- No break condition.
+						FS_B_I := '0'; -- Update.
+					elsif RSR_READ = '1' and FS_B_I = '1' then
+						-- If a break condition was detected, the concerning flag is
+						-- set when the valid data word in the receiver data
+						-- register is read. Thereafter the break flag is reset
+						-- and the break condition disappears after a second read
+						-- (in time) of the receiver status register.
+						if FIRST_READ = false then
+							FS_B <= '1';
+							FIRST_READ := true;
+						else
+							FS_B <= '0';
+							FIRST_READ := false;
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process P_FS_B;
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode.
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode.
+			BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1').
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	BUFFER_FULL: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				RDRF <= '0';
+			elsif RX_SAMPLE = '1' then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif UDR_READ = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process BUFFER_FULL;
+	
+	OVERRUN: process(RESETn, CLK)
+	variable OE_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OE_I := '0';
+			OE <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				OE_I := '0';
+				OE <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = SYNC and BREAK = false then
+				-- Overrun appears if RDRF is '1' in this state and there
+				-- is no break condition.
+				OE_I := RDRF;
+			end if;
+			if RSR_READ = '1' and OE_I = '1' then
+				-- if an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OE_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OE <= '1';
+					FIRST_READ := true;
+				else
+					OE <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable P_ERR		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				PE <= '0';
+			elsif RX_SAMPLE = '1' then
+				PE <= P_ERR; -- Update on load shift register to data register.
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				P_ERR := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if P_ENA = '1' and P_EOn = '1' then -- Even parity.
+				    	P_ERR := PAR_TMP xor SDATA_IN_I;
+					elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity.
+						P_ERR := not PAR_TMP xor SDATA_IN_I;
+					elsif P_ENA = '0' then -- No parity.
+						P_ERR := '0';		
+					end if;
+				end if;
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, SDATA_IN_I, BITCNT, CLK_STRB, STARTBIT,
+						  CLK_2_STRB, ST, CLK_MODE, CL, P_ENA, SHIFT_REG)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if ST = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode.
+				elsif SDATA_IN_I = '0' and CLK_MODE = '0' then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif STARTBIT = true and CLK_MODE = '1' then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				-- This state delays the sample process by one CLK_STRB pulse
+				-- to eliminate the start bit.
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SAMPLE;
+				else
+					RCV_NEXT_STATE <= WAIT_START;
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if CL = "11"  and BITCNT < "100" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits.
+					elsif CL = "10" and BITCNT < "101" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits.
+					elsif CL = "01" and BITCNT < "110" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif CL = "00" and BITCNT < "111" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits).
+						RCV_NEXT_STATE <= IDLE; -- No parity check enabled.
+					elsif P_ENA = '0' then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if ST = "00" then -- Synchronous mode (no stop bits).
+						RCV_NEXT_STATE <= IDLE;
+					else
+						RCV_NEXT_STATE <= STOP1;
+					end if;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data.
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif ST = "11" or ST = "10" then
+						RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_2_STRB = '1'  and ST = "10" then
+					RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected.
+				elsif CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC; -- Two stop bits selected.
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
new file mode 100644
index 0000000..fd06bf1
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
@@ -0,0 +1,238 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core USART top level file.          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_TOP is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Serial I/O control:
+			RC			: in bit; -- Receiver clock.
+			TC			: in bit; -- Transmitter clock.
+			SI			: in bit; -- Serial input.
+			SO			: out bit; -- Serial output.
+			SO_EN		: out bit; -- Serial output enable.
+			
+			-- Interrupt channels:
+			RX_ERR_INT	: out bit; -- Receiver errors.
+			RX_BUFF_INT	: out bit; -- Receiver buffer full.
+			TX_ERR_INT	: out bit; -- Transmitter errors.
+			TX_BUFF_INT	: out bit; -- Transmitter buffer empty.
+
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_USART_TOP;
+
+architecture STRUCTURE of WF68901IP_USART_TOP is
+	signal BF_I				: bit;
+	signal BE_I				: bit;
+	signal FE_I				: bit;
+	signal OE_I				: bit;
+	signal UE_I				: bit;
+	signal PE_I				: bit;
+	signal LOOPBACK_I		: bit;
+	signal SD_LEVEL_I		: bit;
+	signal SDATA_IN_I		: bit;
+	signal SDATA_OUT_I		: bit;
+	signal RXCLK_I			: bit;
+	signal CLK_MODE_I		: bit;
+	signal SCR_I			: bit_vector(7 downto 0);
+	signal RX_SAMPLE_I		: bit;
+	signal RX_DATA_I		: bit_vector(7 downto 0);
+	signal TX_DATA_I		: bit_vector(7 downto 0);
+	signal CL_I				: bit_vector(1 downto 0);
+	signal ST_I				: bit_vector(1 downto 0);
+	signal P_ENA_I			: bit;
+	signal P_EOn_I			: bit;
+	signal RE_I				: bit;
+	signal TE_I				: bit;
+	signal FS_CLR_I			: bit;
+	signal SS_I				: bit;
+	signal M_CIP_I			: bit;
+	signal FS_B_I			: bit;
+	signal BR_I				: bit;
+	signal UDR_READ_I		: bit;
+	signal UDR_WRITE_I		: bit;
+	signal RSR_READ_I		: bit;
+	signal TSR_READ_I		: bit;
+	signal TX_END_I			: bit;
+begin
+	SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I;
+	-- Loopback mode:
+	SDATA_IN_I 	<= 	SDATA_OUT_I when LOOPBACK_I = '1' and TE_I = '1' else 	  -- Loopback, transmitter enabled.
+					'1' 		when LOOPBACK_I = '1' and TE_I = '0' else SI; -- Loopback, transmitter disabled.
+
+	RXCLK_I 	<= 	TC when LOOPBACK_I = '1' else RC;
+	RRn <= '0' when BF_I = '1' and PE_I = '0' and FE_I = '0' else '1';
+	TRn <= not BE_I;
+
+	-- Interrupt sources:
+	RX_ERR_INT 	<= OE_I or PE_I or FE_I or FS_B_I;
+	RX_BUFF_INT	<= BF_I;
+	TX_ERR_INT 	<= UE_I or TX_END_I;
+	TX_BUFF_INT <= BE_I;
+
+	I_USART_CTRL: WF68901IP_USART_CTRL
+	port map(
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+	        RWn     		=> RWn,
+	        RS				=> RS,
+			DATA_IN			=> DATA_IN,
+			DATA_OUT		=> DATA_OUT,
+			DATA_OUT_EN		=> DATA_OUT_EN,
+			LOOPBACK		=> LOOPBACK_I,
+			SDOUT_EN		=> SO_EN,
+			SD_LEVEL		=> SD_LEVEL_I,
+			CLK_MODE		=> CLK_MODE_I,
+			RE				=> RE_I,
+			TE				=> TE_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			BF				=> BF_I,
+			BE				=> BE_I,
+			FE				=> FE_I,
+			OE				=> OE_I,
+			UE				=> UE_I,
+			PE				=> PE_I,
+			M_CIP			=> M_CIP_I,	
+			FS_B			=> FS_B_I,
+			SCR_OUT			=> SCR_I,
+			TX_DATA			=> TX_DATA_I,
+			RX_SAMPLE		=> RX_SAMPLE_I,
+			RX_DATA			=> RX_DATA_I,
+			SS				=> SS_I,
+			BR				=> BR_I,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			FS_CLR			=> FS_CLR_I,
+			UDR_READ		=> UDR_READ_I,
+			UDR_WRITE		=> UDR_WRITE_I,
+			RSR_READ		=> RSR_READ_I,
+			TSR_READ		=> TSR_READ_I,
+			TX_END			=> TX_END_I
+	);                                              
+
+	I_USART_RECEIVE: WF68901IP_USART_RX
+	port map (
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			SCR				=> SCR_I,
+			RX_SAMPLE		=> RX_SAMPLE_I,
+			RX_DATA			=> RX_DATA_I,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			CLK_MODE		=> CLK_MODE_I,
+			RE				=> RE_I,
+			FS_CLR			=> FS_CLR_I,
+			SS				=> SS_I,
+			RXCLK			=> RXCLK_I,
+			SDATA_IN		=> SDATA_IN_I,
+			RSR_READ		=> RSR_READ_I,
+			UDR_READ		=> UDR_READ_I,
+			M_CIP			=> M_CIP_I,	
+			FS_B			=> FS_B_I,
+			BF				=> BF_I,
+			OE				=> OE_I,
+			PE				=> PE_I,
+			FE				=> FE_I
+	);                                              
+
+	I_USART_TRANSMIT: WF68901IP_USART_TX
+	port map (
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			SCR				=> SCR_I,
+			TX_DATA			=> TX_DATA_I,
+	        SDATA_OUT		=> SDATA_OUT_I,
+	        TXCLK			=> TC,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			TE				=> TE_I,
+			BR				=> BR_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			UDR_WRITE		=> UDR_WRITE_I,
+			TSR_READ		=> TSR_READ_I,
+			CLK_MODE		=> CLK_MODE_I,
+			TX_END			=> TX_END_I,
+			UE				=> UE_I,
+			BE				=> BE_I
+	);                  
+end architecture STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
new file mode 100644
index 0000000..8de27f3
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
@@ -0,0 +1,387 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART transmitter file.        ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   TDRE has now synchronous reset to meet preset requirement.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_TX is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+		SCR			: in bit_vector(7 downto 0); -- Synchronous character.
+		TX_DATA		: in bit_vector(7 downto 0); -- Normal data.
+
+        SDATA_OUT	: out bit; -- Serial data output.
+        TXCLK		: in bit;  -- Transmitter clock.
+
+		CL			: in bit_vector(1 downto 0); -- Character length.
+		ST			: in bit_vector(1 downto 0); -- Start and stop bit configuration.
+		TE			: in bit; -- Transmitter enable.
+		BR			: in bit; -- BREAK character send enable (all '0' without stop bit).
+		P_ENA		: in bit; -- Parity enable.
+		P_EOn		: in bit; -- Even or odd parity.
+		UDR_WRITE	: in bit; -- Flag indicating writing the data register.
+		TSR_READ	: in bit; -- Flag indicating reading the transmitter status register.
+		CLK_MODE	: in bit; -- Transmitter clock mode.
+
+		TX_END		: out bit; -- End of transmission flag.
+		UE			: out bit; -- Underrun Flag.
+		BE			: out bit  -- Buffer empty flag.
+       );                                              
+end entity WF68901IP_USART_TX;
+
+architecture BEHAVIOR of WF68901IP_USART_TX is
+type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal CLK_2_STRB	: bit;
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+signal TDRE			: bit;
+signal BREAK		: bit;
+begin
+	BE <= TDRE; -- Buffer empty flag.
+	
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	SDATA_OUT <= 	'0'				when BREAK = '1'			else
+					'1' 			when TR_STATE = IDLE 		else
+					'1' 			when TR_STATE = LOAD_SHFT 	else
+					'0' 			when TR_STATE = START 		else
+					SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+					PARITY_I		when TR_STATE = PARITY 		else
+					'1'				when TR_STATE = STOP1 		else
+					'1'				when TR_STATE = STOP2 		else '1';
+
+	P_BREAK : process(RESETn, CLK)
+	-- This process is responsible to control the BREAK signal. After the break request
+	-- is asserted via BR, the break character will be sent after the current transmission has
+	-- finished. The BREAK character is sent until the BR is disabled.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			BREAK <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- Break is only available in the asynchronous mode (ST /= "00").
+			-- The LOCK mechanism is reponsible for sending the BREAK character just once.
+			if TE = '1' and BR = '1' and ST /= "00" and TR_STATE = IDLE and LOCK = false then
+				BREAK <= '1'; -- Break for the case that there is no current transmission.
+				LOCK := true;
+			elsif BR = '1' and ST /= "00" and TR_STATE = STOP1 then
+				BREAK <= '0'; -- Break character sent.
+			elsif BR = '0' then
+				BREAK <= '0';
+				LOCK := false;
+			else
+				BREAK <= '0';	
+			end if;
+		end if;
+	end process P_BREAK;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(4 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CLK_MODE = '0' then -- Divider off.
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+			CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
+		elsif TR_STATE = IDLE then
+			CLK_DIVCNT := "10000"; -- Div by 16 mode.
+			CLK_STRB <= '0';
+		else
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_LOCK := true;
+				if CLK_DIVCNT = "01000" then
+					-- This strobe is asserted at half of the clock cycle.
+					-- It is used for the stop bit timing.
+					CLK_2_STRB <= '1';
+				end if;
+			elsif CLK_DIVCNT = "00000" then
+				CLK_DIVCNT := "10000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+			end if;
+		end if;
+	end process CLKDIV;
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if TR_STATE = LOAD_SHFT and TDRE = '1' then -- Lost data ...
+				case ST is
+					when "00" => -- Synchronous mode.
+						SHIFT_REG <= SCR; -- Send the synchronous character.
+					when others => -- Asynchronous mode.
+						SHIFT_REG <= x"5A"; -- Load the shift register with a mark (underrun).
+				end case;
+			elsif TR_STATE = LOAD_SHFT then
+				-- Load 'normal' data if there is no break condition:
+				case CL is
+					when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits.
+					when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits.
+					when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits.
+					when "00" => SHIFT_REG <= TX_DATA; -- 8 databits.
+				end case;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	BUFFER_EMPTY: process
+	-- Transmit data register empty flag.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			TDRE <= '1';
+		elsif TE = '0' then
+			TDRE <= '1';
+		elsif TR_STATE = START and BREAK = '0' then
+			-- Data has been loaded to the shift register,
+			-- thus data register is free again.
+			-- If the BREAK flag is enabled, the BE flag
+			-- respective TDRE flag cannot be set.
+			TDRE <= '1';
+		elsif  UDR_WRITE = '1' then
+			TDRE <= '0';
+		end if;
+	end process BUFFER_EMPTY;
+
+	UNDERRUN: process(RESETn, CLK)
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			UE <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if TE = '0' then
+				UE <= '0';
+				LOCK := false;
+			elsif CLK_STRB = '1' and TR_STATE = START then
+				-- Underrun appears if TDRE is '0' at the end of this state.
+				UE <= TDRE; -- Never true for enabled BREAK flag. See alos process BUFFER_EMPTY.
+				LOCK := true;
+			elsif CLK_STRB = '1' then
+				LOCK := false; -- Disables clearing UE one transmit clock cycle.
+			elsif TSR_READ = '1' and LOCK = false then
+				UE <= '0';
+			end if;
+		end if;
+	end process UNDERRUN;
+	
+	P_TX_END: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TX_END <= '0';
+		elsif CLK = '1' and CLK' event then
+			if TE = '1' then -- Transmitter enabled.
+				TX_END <= '0';
+			elsif TE = '0' and TR_STATE = IDLE then
+				TX_END <= '1';
+			end if;
+		end if;
+	end process P_TX_END;
+	
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if P_ENA = '1' and P_EOn = '1' then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity.
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			TR_STATE <= TR_NEXT_STATE;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, CLK_2_STRB, BITCNT, TDRE, BREAK, TE, ST, P_ENA, CL, BR)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				-- This IDLE state is just one clock cycle and is required to give the
+				-- break process time to set the BREAK flag.
+				TR_NEXT_STATE <= CHECK_BREAK;
+			when CHECK_BREAK =>
+				if BREAK = '1' then -- Send break character.
+					-- Do not load any data to the shift register, go directly
+					-- to the START state.
+					TR_NEXT_STATE <= START;
+				-- Start enabled transmitter, if the data register is not empty.
+				 -- Do not send any further data for the case of an asserted BR flag.
+				elsif TE = '1' and TDRE = '0' and BR = '0' then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE; -- Go back, scan for BREAK.
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START => -- Send the start bit.
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "100" and CL = "11" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits.
+					elsif BITCNT < "101" and CL = "10" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits.
+					elsif BITCNT < "110" and CL = "01" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and CL = "00" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif P_ENA = '0' and BREAK = '1' then
+						TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits.
+					elsif P_ENA = '0' and ST = "00" then
+						TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled.
+					elsif P_ENA = '0' then
+						TR_NEXT_STATE <= STOP1; -- Asynchronous mode, no parity check enabled.
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if ST = "00" then -- Synchronous mode (no stop bits).
+						TR_NEXT_STATE <= IDLE;
+					elsif BREAK = '1' then -- No stop bits during break condition.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1;
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (ST = "11" or ST = "10") then
+					TR_NEXT_STATE <= STOP2; -- More than one stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_2_STRB = '1' and ST = "10" then
+					TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- Two stop bits detected.
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd
new file mode 100644
index 0000000..685fc02
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd
@@ -0,0 +1,228 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 1.0  2007/01/05 WF
+--   Initial Release.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D			: inout std_logic_vector(7 downto 0);
+
+		-- Microcontroller interface:
+		MC_D			: inout std_logic_vector(7 downto 0);
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => 'Z');
+	ACSI_D <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => 'Z');
+	ACSI_INTn <= INT_REG;
+	ACSI_DRQn <= DRQ_REG;
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
new file mode 100644
index 0000000..b1dfe91
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
@@ -0,0 +1,240 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K7A  2007/01/05 WF
+--   Initial Release.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D_IN		: in std_logic_vector(7 downto 0);
+		ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+		ACSI_D_EN		: out bit;
+
+		-- Microcontroller interface:
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit;
+		MC_D_IN			: in std_logic_vector(7 downto 0);
+		MC_D_OUT		: out std_logic_vector(7 downto 0);
+		MC_D_EN			: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0');
+	MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0';
+	ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0');
+--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0';
+ACSI_D_EN <= '0'; -- Disabled.
+--ACSI_INTn <= INT_REG;
+ACSI_INTn <= '1'; -- Disabled.
+--ACSI_DRQn <= DRQ_REG;
+ACSI_DRQn <= '1'; -- Disabled.
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D_IN;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+-- ?? ACSI_CSn doppelt!
+if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
new file mode 100644
index 0000000..0200dea
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
@@ -0,0 +1,239 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K7A  2007/01/05 WF
+--   Initial Release.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D_IN		: in std_logic_vector(7 downto 0);
+		ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+		ACSI_D_EN		: out bit;
+
+		-- Microcontroller interface:
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit;
+		MC_D_IN			: in std_logic_vector(7 downto 0);
+		MC_D_OUT		: out std_logic_vector(7 downto 0);
+		MC_D_EN			: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0');
+	MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0';
+	ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0');
+-- ???:
+--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0';
+ACSI_D_EN <= '0';
+	ACSI_INTn <= INT_REG;
+	ACSI_DRQn <= DRQ_REG;
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D_IN;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+-- ?? ACSI_CSn doppelt!
+--if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
new file mode 100644
index 0000000..9d048de
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- YM2149 compatible sound generator.				              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF2149IP_PKG is
+type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
+
+component WF2149IP_WAVE
+	port(
+		RESETn		: in bit;
+		SYS_CLK		: in bit;
+
+		WAV_STRB	: in bit;
+
+		ADR			: in bit_vector(3 downto 0);
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		
+		BUSCYCLE	: in BUSCYCLES;
+		CTRL_REG	: in bit_vector(5 downto 0);
+
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end component;
+end WF2149IP_PKG;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
new file mode 100644
index 0000000..3f5024a
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
@@ -0,0 +1,170 @@
+----------------------------------------------------------------------
+----                                                              ----
+----  YM2149 compatible sound generator.			              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+---- This IP core of the sound generator differs slightly from    ----
+---- the original. Firstly it is a synchronous design without any ----
+---- latches (like assumed in the original chip). This required   ----
+---- the introduction of a system adequate clock. In detail this  ----
+---- SYS_CLK should on the one hand be fast enough to meet the    ----
+---- timing requirements of the system's bus cycle and should one ----
+---- the other hand drive the PWM modules correctly. To meet both ----
+---- a SYS_CLK of 16MHz or above is recommended.                  ----
+---- Secondly, the original chip has an implemented DA converter. ----
+---- This feature is not possible in today's FPGAs. Therefore the ----
+---- converter is replaced by pulse width modulators. This solu-  ----
+---- tion is very simple in comparison to other approaches like   ----
+---- external DA converters with wave tables etc. The soltution   ----
+---- with the pulse width modulators is probably not as accurate  ----
+---- DAs with wavetables. For a detailed descrition of the hard-  ----
+---- ware PWM filter look at the end of the wave file, where the  ----
+---- pulse width modulators can be found.                         ----
+---- For a proper operation it is required, that the wave clock   ----
+---- is lower than the system clock. A good choice is for example ----
+---- 2MHz for the wave clock and 16MHz for the system clock.      ----
+----                                                              ----
+---- Main module file.                                            ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_TOP is
+	port(
+		
+		SYS_CLK		: in bit; -- Read the inforation in the header!
+		RESETn   	: in bit;
+
+		WAV_CLK		: in bit; -- Read the inforation in the header!
+		SELn		: in bit;
+		
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+
+		A9n, A8		: in bit;
+		DA			: inout std_logic_vector(7 downto 0);
+		
+		IO_A		: inout std_logic_vector(7 downto 0);
+		IO_B		: inout std_logic_vector(7 downto 0);
+		
+		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end WF2149IP_TOP;
+
+architecture STRUCTURE of WF2149IP_TOP is
+component WF2149IP_TOP_SOC
+	port(
+		SYS_CLK		: in bit;
+		RESETn   	: in bit;
+		WAV_CLK		: in bit;
+		SELn		: in bit;
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+		A9n, A8		: in bit;
+		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_EN		: out bit;
+		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_EN		: out bit;
+		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_EN		: out bit;
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end component;
+--
+signal DA_OUT       : std_logic_vector(7 downto 0);
+signal DA_EN        : bit;
+signal IO_A_IN      : bit_vector(7 downto 0);
+signal IO_A_OUT     : bit_vector(7 downto 0);
+signal IO_A_EN      : bit;
+signal IO_B_IN      : bit_vector(7 downto 0);
+signal IO_B_OUT     : bit_vector(7 downto 0);
+signal IO_B_EN      : bit;
+begin
+    IO_A_IN <= To_BitVector(IO_A);
+    IO_B_IN <= To_BitVector(IO_B);
+
+    IO_A <= To_StdLogicVector(IO_A_OUT) when IO_A_EN = '1' else (others => 'Z');
+    IO_B <= To_StdLogicVector(IO_B_OUT) when IO_B_EN = '1' else (others => 'Z');
+
+    DA <= DA_OUT when DA_EN = '1' else (others => 'Z');
+
+    I_SOUND: WF2149IP_TOP_SOC
+        port map(SYS_CLK            => SYS_CLK,
+                 RESETn             => RESETn,
+                 WAV_CLK            => WAV_CLK,
+                 SELn               => SELn,
+                 BDIR               => BDIR,
+                 BC2                => BC2,
+                 BC1                => BC1,
+                 A9n                => A9n,
+                 A8                 => A8,
+                 DA_IN              => DA,
+                 DA_OUT             => DA_OUT,
+                 DA_EN              => DA_EN,
+                 IO_A_IN            => IO_A_IN,
+                 IO_A_OUT           => IO_A_OUT,
+                 IO_A_EN            => IO_A_EN,
+                 IO_B_IN            => IO_B_IN,
+                 IO_B_OUT           => IO_B_OUT,
+                 IO_B_EN            => IO_B_EN,
+                 OUT_A              => OUT_A,
+                 OUT_B              => OUT_B,
+                 OUT_C              => OUT_C
+        );
+end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
new file mode 100644
index 0000000..77ea5ef
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
@@ -0,0 +1,229 @@
+----------------------------------------------------------------------
+----                                                              ----
+----  YM2149 compatible sound generator.			              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+---- This IP core of the sound generator differs slightly from    ----
+---- the original. Firstly it is a synchronous design without any ----
+---- latches (like assumed in the original chip). This required   ----
+---- the introduction of a system adequate clock. In detail this  ----
+---- SYS_CLK should on the one hand be fast enough to meet the    ----
+---- timing requirements of the system's bus cycle and should one ----
+---- the other hand drive the PWM modules correctly. To meet both ----
+---- a SYS_CLK of 16MHz or above is recommended.                  ----
+---- Secondly, the original chip has an implemented DA converter. ----
+---- This feature is not possible in today's FPGAs. Therefore the ----
+---- converter is replaced by pulse width modulators. This solu-  ----
+---- tion is very simple in comparison to other approaches like   ----
+---- external DA converters with wave tables etc. The soltution   ----
+---- with the pulse width modulators is probably not as accurate  ----
+---- DAs with wavetables. For a detailed descrition of the hard-  ----
+---- ware PWM filter look at the end of the wave file, where the  ----
+---- pulse width modulators can be found.                         ----
+---- For a proper operation it is required, that the wave clock   ----
+---- is lower than the system clock. A good choice is for example ----
+---- 2MHz for the wave clock and 16MHz for the system clock.      ----
+----                                                              ----
+---- Main module file.                                            ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_TOP_SOC is
+	port(
+		
+		SYS_CLK		: in bit; -- Read the inforation in the header!
+		RESETn   	: in bit;
+
+		WAV_CLK		: in bit; -- Read the inforation in the header!
+		SELn		: in bit;
+		
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+
+		A9n, A8		: in bit;
+		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_EN		: out bit;
+		
+		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_EN		: out bit;
+		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_EN		: out bit;
+
+		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end WF2149IP_TOP_SOC;
+
+architecture STRUCTURE of WF2149IP_TOP_SOC is
+signal BUSCYCLE		: BUSCYCLES;
+signal DATA_OUT_I	: std_logic_vector(7 downto 0);
+signal DATA_EN_I	: bit;
+signal WAV_STRB		: bit;
+signal ADR_I		: bit_vector(3 downto 0);
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal PORT_A		: bit_vector(7 downto 0);
+signal PORT_B		: bit_vector(7 downto 0);
+begin
+	P_WAVSTRB: process(RESETn, SYS_CLK)
+	variable LOCK	: boolean;
+	variable TMP	: bit;
+	begin
+		if RESETn = '0' then
+			LOCK := false;
+			TMP := '0';
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_CLK = '1' and LOCK = false then
+				LOCK := true;
+				TMP := not TMP; -- Divider by 2.
+				case SELn is
+					when '1' 	=> WAV_STRB <= '1';
+					when others => WAV_STRB <= TMP;
+				end case;
+			elsif WAV_CLK = '0' then
+				LOCK := false;
+				WAV_STRB <= '0';
+			else
+				WAV_STRB <= '0';
+			end if;
+		end if;
+	end process P_WAVSTRB;		
+
+	with BDIR & BC2 & BC1 select
+		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
+					ADDRESS 	when "001" | "100" | "111",
+					R_READ 		when "011",
+					R_WRITE 	when "110";
+
+	ADDRESSLATCH: process(RESETn, SYS_CLK)
+	-- This process is responsible to store the desired register
+	-- address. The default (after reset) is channel A fine tone 
+	-- adjustment.
+	begin
+		if RESETn = '0' then
+			ADR_I <= (others => '0');
+        elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
+				ADR_I <= To_BitVector(DA_IN(3 downto 0));
+			end if;
+		end if;
+	end process ADDRESSLATCH;	
+
+	P_CTRL_REG: process(RESETn, SYS_CLK)
+	-- THIS is the Control register for the mixer and for the I/O ports.
+	begin
+		if RESETn = '0' then
+			CTRL_REG <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
+				CTRL_REG <= To_BitVector(DA_IN);
+			end if;
+		end if;
+	end process P_CTRL_REG;
+	
+	DIG_PORTS: process(RESETn, SYS_CLK)
+	begin
+		if RESETn = '0' then
+			PORT_A <= x"00";
+			PORT_B <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
+				PORT_A <= To_BitVector(DA_IN);
+			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
+				PORT_B <= To_BitVector(DA_IN);
+			end if;
+		end if;	
+	end process DIG_PORTS;
+	-- Set port direction to input or to output:
+	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
+	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
+	IO_A_OUT <= PORT_A;
+	IO_B_OUT <= PORT_B;
+
+	I_PSG_WAVE: WF2149IP_WAVE
+		port map(
+			RESETn		=> RESETn,
+			SYS_CLK	=> SYS_CLK,
+
+			WAV_STRB	=> WAV_STRB,
+
+			ADR			=> ADR_I,
+			DATA_IN		=> DA_IN,
+			DATA_OUT	=> DATA_OUT_I,
+			DATA_EN		=> DATA_EN_I,
+			
+			BUSCYCLE	=> BUSCYCLE,
+			CTRL_REG	=> CTRL_REG(5 downto 0),
+						
+			OUT_A		=> OUT_A,
+			OUT_B		=> OUT_B,
+			OUT_C		=> OUT_C
+		);
+
+	-- Read the ports and registers:
+	DA_EN <= 	'1' when DATA_EN_I = '1' else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
+				
+	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
+				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
+				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
+				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
+
+end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
new file mode 100644
index 0000000..d829f9b
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
@@ -0,0 +1,533 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- YM2149 compatible sound generator.				              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+----                                                              ----
+---- Waveform generator.                                          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   NOISE_OUT has now synchronous reset to meet preset requirement.
+--   Fixed a bug in the envelope generator. Thanks to Lyndon Amsdon finding it.
+--   Correction of the schematic given in the end of this file.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_WAVE is
+	port(
+		RESETn		: in bit;
+		SYS_CLK		: in bit;
+
+		WAV_STRB	: in bit;
+
+		ADR			: in bit_vector(3 downto 0);
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		
+		BUSCYCLE	: in BUSCYCLES;
+		CTRL_REG	: in bit_vector(5 downto 0);
+
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end entity WF2149IP_WAVE;
+
+architecture BEHAVIOR of WF2149IP_WAVE is
+signal FREQUENCY_A	: std_logic_vector(11 downto 0);
+signal FREQUENCY_B	: std_logic_vector(11 downto 0);
+signal FREQUENCY_C	: std_logic_vector(11 downto 0);
+signal NOISE_FREQ	: std_logic_vector(4 downto 0);
+signal LEVEL_A		: std_logic_vector(4 downto 0);
+signal LEVEL_B		: std_logic_vector(4 downto 0);
+signal LEVEL_C		: std_logic_vector(4 downto 0);
+signal ENV_FREQ		: std_logic_vector(15 downto 0);
+signal ENV_SHAPE	: std_logic_vector(3 downto 0);
+signal ENV_RESET	: boolean;
+signal ENV_STRB		: bit;
+signal OSC_A_OUT	: bit;
+signal OSC_B_OUT	: bit;
+signal OSC_C_OUT	: bit;
+signal NOISE_OUT	: bit;
+signal AUDIO_A		: bit;
+signal AUDIO_B		: bit;
+signal AUDIO_C		: bit;
+signal VOL_ENV		: std_logic_vector(4 downto 0);
+signal AMPLITUDE_A	: std_logic_vector(4 downto 0);
+signal AMPLITUDE_B	: std_logic_vector(4 downto 0);
+signal AMPLITUDE_C	: std_logic_vector(4 downto 0);
+signal VOLUME_A		: std_logic_vector(7 downto 0);
+signal VOLUME_B		: std_logic_vector(7 downto 0);
+signal VOLUME_C		: std_logic_vector(7 downto 0);
+signal PWM_RAMP		: std_logic_vector(7 downto 0);
+begin
+	REGISTERS: process(RESETn, SYS_CLK)
+	-- This process is responsible for initialisation
+	-- and write access to the configuration registers.
+	begin
+		if RESETn = '0' then
+			FREQUENCY_A <= x"000";
+			FREQUENCY_B <= x"000";
+			FREQUENCY_C <= x"000";
+			NOISE_FREQ <= "00000";
+			LEVEL_A <= "00000";
+			LEVEL_B <= "00000";
+			LEVEL_C <= "00000";
+			ENV_FREQ <= (others => '0');
+			ENV_SHAPE <= "0000";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			ENV_RESET <= false; -- Initialize signal.
+			if BUSCYCLE = R_WRITE then
+				case ADR is
+					when x"0" => FREQUENCY_A(7 downto 0) <= DATA_IN;
+					when x"1" => FREQUENCY_A(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"2" => FREQUENCY_B(7 downto 0) <= DATA_IN;
+					when x"3" => FREQUENCY_B(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"4" => FREQUENCY_C(7 downto 0) <= DATA_IN;
+					when x"5" => FREQUENCY_C(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"6" => NOISE_FREQ <= DATA_IN(4 downto 0);
+					when x"8" => LEVEL_A <= DATA_IN(4 downto 0);
+					when x"9" => LEVEL_B <= DATA_IN(4 downto 0);
+					when x"A" => LEVEL_C <= DATA_IN(4 downto 0);
+					when x"B" => ENV_FREQ(7 downto 0) <= DATA_IN;
+					when x"C" => ENV_FREQ(15 downto 8) <= DATA_IN;	
+								 ENV_RESET <= true; -- Initialize the envelope generator.
+					when x"D" => ENV_SHAPE <= DATA_IN(3 downto 0);
+					when others => null;
+				end case;
+			end if;
+		end if;
+	end process REGISTERS;
+
+	-- Read back the configuration registers:
+	DATA_OUT <=	FREQUENCY_A(7 downto 0) when BUSCYCLE = R_READ and ADR = x"0" else
+				"0000" & FREQUENCY_A(11 downto 8) when BUSCYCLE = R_READ and ADR = x"1" else
+				FREQUENCY_B(7 downto 0) when BUSCYCLE = R_READ and ADR = x"2" else
+				"0000" & FREQUENCY_B(11 downto 8) when BUSCYCLE = R_READ and ADR = x"3" else
+				FREQUENCY_C(7 downto 0) when BUSCYCLE = R_READ and ADR = x"4" else
+				"0000" & FREQUENCY_C(11 downto 8) when BUSCYCLE = R_READ and ADR = x"5" else
+				"000" & NOISE_FREQ when BUSCYCLE = R_READ and ADR = x"6" else
+				"000" & LEVEL_A when BUSCYCLE = R_READ and ADR = x"8" else
+				"000" & LEVEL_B when BUSCYCLE = R_READ and ADR = x"9" else
+				"000" & LEVEL_C when BUSCYCLE = R_READ and ADR = x"A" else
+				ENV_FREQ(7 downto 0) when BUSCYCLE = R_READ and ADR = x"B" else
+				ENV_FREQ(15 downto 8) when BUSCYCLE = R_READ and ADR = x"C" else
+				x"0" & ENV_SHAPE when BUSCYCLE = R_READ and ADR = x"D" else (others => '0');
+	DATA_EN <=	'1' when BUSCYCLE = R_READ and ADR >= x"0" and ADR <= x"6" else
+				'1' when BUSCYCLE = R_READ and ADR >= x"8" and ADR <= x"D" else '0';
+
+	MUSICGENERATOR: process(RESETn, SYS_CLK)
+	variable CLK_DIV	: std_logic_vector(2 downto 0);
+	variable CNT_CH_A 	: std_logic_vector(11 downto 0);
+	variable CNT_CH_B 	: std_logic_vector(11 downto 0);
+	variable CNT_CH_C 	: std_logic_vector(11 downto 0);
+	begin
+		if RESETn = '0' then
+			CLK_DIV := "000";
+			CNT_CH_A := (others => '0');
+			CNT_CH_B := (others => '0');
+			CNT_CH_C := (others => '0');
+			OSC_A_OUT <= '0';
+			OSC_B_OUT <= '0';
+			OSC_C_OUT <= '0';
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_STRB = '1' then
+				-- Divider by 8 for the oscillators brings in connection 
+				-- with the toggle flip flops CH_x_OUT the required divider
+				-- ratio of 16.
+				CLK_DIV := CLK_DIV + '1';
+
+				if CLK_DIV = "000" then
+					if FREQUENCY_A = x"000" then
+						CNT_CH_A := (others => '0');
+						OSC_A_OUT <= '0';
+					elsif CNT_CH_A = x"000" then
+						CNT_CH_A := FREQUENCY_A - '1' ;
+						OSC_A_OUT <= not OSC_A_OUT;
+					else
+						CNT_CH_A := CNT_CH_A - '1';
+					end if;
+
+					if FREQUENCY_B = x"000" then
+						CNT_CH_B := (others => '0');
+						OSC_B_OUT <= '0';
+					elsif CNT_CH_B = x"000" then
+						CNT_CH_B := FREQUENCY_B - '1' ;
+						OSC_B_OUT <= not OSC_B_OUT;
+					else
+						CNT_CH_B := CNT_CH_B - '1';
+					end if;
+
+					if FREQUENCY_C = x"000" then
+						CNT_CH_C := (others => '0');
+						OSC_C_OUT <= '0';
+					elsif CNT_CH_C = x"000" then
+						CNT_CH_C := FREQUENCY_C - '1' ;
+						OSC_C_OUT <= not OSC_C_OUT;
+					else
+						CNT_CH_C := CNT_CH_C - '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process MUSICGENERATOR;
+
+	NOISEGENERATOR: process
+	-- The noise shift polynomial is taken from a template of Kazuhiro TSUJIKAWA's 
+	-- (ESE Artists' factory) approach for a 2149 equivalent. But the implementation
+	-- is done in another way.
+	-- LFSR (linear feedback shift register polynomial: f(x) = x^17 + x^14 + 1.
+	variable CLK_DIV	: std_logic_vector(3 downto 0);
+	variable CNT_NOISE 	: std_logic_vector(4 downto 0);
+	variable N_SHFT 	: std_logic_vector(16 downto 0);
+	begin
+		wait until SYS_CLK = '1' and SYS_CLK' event;
+		if RESETn = '0' then
+			CLK_DIV := x"0";
+			CNT_NOISE := (others => '1'); -- Preset the polynomial shift register.
+			NOISE_OUT <= '1';
+		elsif WAV_STRB = '1' then
+			-- Divider by 16 for the noise generator.
+			CLK_DIV := CLK_DIV + '1';
+			if CLK_DIV = x"0" then
+				-- Noise frequency counter.
+				if NOISE_FREQ = "00000" then
+					CNT_NOISE := (others => '0');
+				elsif CNT_NOISE = "00000" then
+					CNT_NOISE := NOISE_FREQ - '1' ;
+					N_SHFT := N_SHFT(15 downto 14) & not(N_SHFT(16) xor N_SHFT(13)) & 
+													N_SHFT(12 downto 0) & not N_SHFT(16);
+				else
+					CNT_NOISE := CNT_NOISE - '1';
+				end if;
+			end if;
+		end if;
+		NOISE_OUT <= To_Bit(N_SHFT(16));
+	end process NOISEGENERATOR;
+
+	ENVELOPE_PERIOD: process(RESETn, SYS_CLK)
+	-- The envelope period is controlled by the Envelope Frequency and the divider ratio which is
+	-- 256/32 = 8. For further information see the original data sheet.
+	variable ENV_CLK : std_logic_vector(18 downto 0);
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			ENV_STRB <= '0';
+			ENV_CLK := (others => '0');
+			LOCK := false;
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_STRB = '1' and LOCK = false then
+				LOCK := true;
+				if ENV_FREQ = x"0000" then
+					ENV_STRB <= '0';
+				elsif ENV_CLK = x"0000" & "000" then
+					ENV_CLK := (ENV_FREQ & "111") - '1' ;
+					ENV_STRB <= '1';
+				else
+					ENV_CLK := ENV_CLK - '1';
+					ENV_STRB <= '0';
+				end if;
+			elsif WAV_STRB = '0' then
+				LOCK := false;
+				ENV_STRB <= '0';
+			else
+				ENV_STRB <= '0';
+			end if;
+		end if;
+	end process ENVELOPE_PERIOD;
+	
+	ENVELOPE: process(RESETn, SYS_CLK)
+	-- Envelope shapes:
+	-- case ENV_SHAPE:
+	--
+	-- 0 0 x x  \___
+	--
+	-- 0 1 x x  /|___
+	--
+	-- 1 0 0 0  _|\|\|\|\|
+	--
+	-- 1 0 0 1  \___
+	--
+	-- 1 0 1 0  \/\/
+	--            ___
+	-- 1 0 1 1  \|
+	--
+	-- 1 1 0 0  /|/|/|/|
+	--           ___
+	-- 1 1 0 1  /
+	--
+	-- 1 1 1 0  /\/\
+	--
+	-- 1 1 1 1  /|___
+	--
+	variable ENV_STOP	: boolean;
+	variable ENV_UP_DNn	: bit;
+	begin
+		if RESETn = '0' then
+			VOL_ENV <= (others => '0');
+			ENV_UP_DNn := '0';
+			ENV_STOP := false;
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if ENV_RESET = true then
+				ENV_STOP := false;
+				case ENV_SHAPE is
+					when "1011" | "1010" | "1001" | "1000" | "0011" | "0010" | "0001" | "0000" =>
+						VOL_ENV <= "11111"; -- Start on top.
+						ENV_UP_DNn := '0';
+					when others =>
+						VOL_ENV <= "00000"; -- Start at bottom.
+						ENV_UP_DNn := '1';
+				end case;
+			elsif ENV_STRB = '1' then
+				case ENV_SHAPE is
+					when "1001" | "0011" | "0010" | "0001" | "0000"  =>
+						if VOL_ENV > "00000" then
+							VOL_ENV <= VOL_ENV - '1';
+						end if;
+					when "1111" | "0111" | "0110" | "0101" | "0100"  =>
+						if VOL_ENV < "11111" and ENV_STOP = false then
+							VOL_ENV <= VOL_ENV + '1';
+						else
+							VOL_ENV <= "00000";
+							ENV_STOP := true;
+						end if;
+					when "1000" =>
+						VOL_ENV <= VOL_ENV - '1';
+					when "1110" | "1010" =>
+						if ENV_UP_DNn = '0' then
+							VOL_ENV <= VOL_ENV - '1';
+						else
+							VOL_ENV <= VOL_ENV + '1';
+						end if;
+						--
+                        if VOL_ENV = "00001" then
+							ENV_UP_DNn := '1';
+                        elsif VOL_ENV = "11110" then
+							ENV_UP_DNn := '0';
+						end if;
+					when "1011" =>
+						if VOL_ENV > "00000" and ENV_STOP = false then
+							VOL_ENV <= VOL_ENV - '1';
+						else
+							VOL_ENV <= "11111";
+							ENV_STOP := true;
+						end if;
+					when "1100" =>
+						VOL_ENV <= VOL_ENV + '1';
+					when "1101" =>
+						if VOL_ENV < "11111" then
+							VOL_ENV <= VOL_ENV + '1';
+						end if;
+					when others => null; -- Covers U, X, Z, W, H, L, -.
+				end case;
+			end if;
+		end if;
+	end process ENVELOPE;
+
+	--MIXER:
+	-- The mixer controls are dependant on the mixer settings and the output of the
+	-- audio data for all three channels. The noise generator and the square wave
+	-- generators A, B and C are mixed together by a simple boolean OR.
+	AUDIO_A <= (OSC_A_OUT and not CTRL_REG(0)) or (NOISE_OUT and not CTRL_REG(3));
+	AUDIO_B <= (OSC_B_OUT and not CTRL_REG(1)) or (NOISE_OUT and not CTRL_REG(4));
+	AUDIO_C <= (OSC_C_OUT and not CTRL_REG(2)) or (NOISE_OUT and not CTRL_REG(5));
+
+	--LEVEL (e.g. volume control):
+	-- The linear amplitude for the DA converters of channel A, B or C are fixed
+	-- (LEVEL(3 downto 0)) or delivered by the envelope generator.
+	-- The following behavior is taken from the 2149 IP core of Mike J (www.fpgaarcade.com):
+	-- "make sure level 31 (env) = level 15 (tone)"
+	-- Thus there is a resulting & '1' modeling if LEVEL amplitudes are selected.
+	AMPLITUDE_A <= 	LEVEL_A(3 downto 0) & '1' 	when LEVEL_A(4) = '0' and AUDIO_A = '1' else
+					VOL_ENV 					when LEVEL_A(4) = '1' and AUDIO_A = '1' else "00000";
+	AMPLITUDE_B <= 	LEVEL_B(3 downto 0) & '1' 	when LEVEL_B(4) = '0' and AUDIO_B = '1' else
+					VOL_ENV 					when LEVEL_B(4) = '1' and AUDIO_B = '1' else "00000";
+	AMPLITUDE_C <= 	LEVEL_C(3 downto 0) & '1' 	when LEVEL_C(4) = '0' and AUDIO_C = '1' else
+					VOL_ENV 					when LEVEL_C(4) = '1' and AUDIO_C = '1' else "00000";
+
+	-- The values for the logarithmic DA converter volume controls are taken from the linear 
+	-- mixer of Mike J's 2149 IP core (www.fpgaarcade.com).
+	with AMPLITUDE_A select
+						VOLUME_A <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	with AMPLITUDE_B select 
+						VOLUME_B <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	with AMPLITUDE_C select
+						VOLUME_C <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	DA_CONVERSION: process
+	-- The DA conversion for the three analog outputs is originally performed by a built in DA converter.
+	-- For this is not possible in current FPGA designs, the converter is replaced by three PWM units
+	-- operating at a frequency which is 100 times higher than the highest noise or music frequency which
+	-- is 2MHz/16 = 125kHz. So the PWM frequency requires about 12.5MHz or more. The design is done for
+	-- a PWM frequency of 16MHz).
+	begin
+		wait until SYS_CLK = '1' and SYS_CLK' event;
+		PWM_RAMP <= PWM_RAMP + '1';
+	end process DA_CONVERSION;
+	OUT_A <= '0' when VOLUME_A = x"00" else '1' when PWM_RAMP < VOLUME_A else '0';
+	OUT_B <= '0' when VOLUME_B = x"00" else '1' when PWM_RAMP < VOLUME_B else '0';
+	OUT_C <= '0' when VOLUME_C = x"00" else '1' when PWM_RAMP < VOLUME_C else '0';
+	--
+	-- To obtain proper analog output it is necessary to install analog RC filters to the pulse width
+	-- outputs. An example is given for the direct wiring of the three analog outputs and for a system
+	-- clock frequency of 16MHz. The output circuitry looks in this case as follows:
+	--
+	-- OUT_A ---------|1kOhm|-----------|                      |\ e.g. LM741
+	--                                  |----------------------|+\       ||
+	-- OUT_B ---------|1kOhm|-----------|                      | OP------||--- Analog Signal
+	--                                  |                |-----|-/	|    ||
+	-- OUT_C ---------|1kOhm|-----------|                |     |/   |   4u7
+	--                                  |                |__________|
+	--                                  |
+	--                                 --- 10nF.
+	--                                 ---
+	--                                  |
+	--                                  |
+	--                                 ---
+	--  WF.
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
new file mode 100644
index 0000000..e60cc43
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
@@ -0,0 +1,244 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CTRL_REG has now synchronous reset to meet preset requirements.
+--   Process P_DCD has now synchronous reset to meet preset requirements.
+--   IRQ_In has now synchronous reset to meet preset requirement.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_CTRL_STATUS is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+        CS			: in bit_vector(2 downto 0); -- Active if "011".
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);   
+		DATA_EN		: out bit;
+		
+		-- Status register stuff:
+		RDRF		: in bit;	-- Receive data register full.
+		TDRE		: in bit;	-- Transmit data register empty.
+		DCDn		: in bit;	-- Data carrier detect.
+		CTSn		: in bit;	-- Clear to send.
+		FE			: in bit;	-- Framing error.
+		OVR			: in bit;	-- Overrun error.
+		PE			: in bit;	-- Parity error.
+
+		-- Control register stuff:
+		MCLR		: buffer bit; -- Master clear (high active).
+		RTSn		: out bit; -- Request to send.
+		CDS			: out bit_vector(1 downto 0); -- Clock control.
+		WS			: out bit_vector(2 downto 0); -- Word select.
+		TC			: out bit_vector(1 downto 0); -- Transmit control.
+		IRQn		: out bit -- Interrupt request.
+       );                                              
+end entity WF6850IP_CTRL_STATUS;
+
+architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal RIE			: bit;
+signal IRQ_I		: bit;
+signal CTS_In		: bit;
+signal DCD_In		: bit;
+signal DCD_FLAGn	: bit;
+begin
+	P_SAMPLE: process
+	begin
+		wait until CLK = '0' and CLK' event;
+		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
+		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
+	end process P_SAMPLE;
+
+	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(6) <= PE;
+	STATUS_REG(5) <= OVR;
+	STATUS_REG(4) <= FE;
+	STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin.
+	STATUS_REG(2) <= DCD_FLAGn;
+	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
+	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
+
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	
+	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
+	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
+
+	CDS <= CTRL_REG(1 downto 0);
+	WS <= CTRL_REG(4 downto 2);
+	TC <= CTRL_REG(6 downto 5);
+	RIE <= CTRL_REG(7);
+	
+	P_IRQ: process
+	variable DCD_OVR_LOCK	: boolean;
+	variable DCD_LOCK	    : boolean;
+	variable DCD_TRANS	    : boolean;	
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_OVR_LOCK := false;
+			IRQn <= '1';
+			IRQ_I <= '0';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+		end if;
+
+        -- Clear interrupts when disabled.
+        if CTRL_REG(7) = '0' then
+            IRQn <= '1';
+            IRQ_I <= '0';
+        elsif CTRL_REG(6 downto 5) /= "01" then
+            IRQn <= '1';
+            IRQ_I <= '0';
+        end if;
+
+		-- Transmitter interrupt:
+        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by writing to the transmit data register.
+		end if;
+					
+		-- Receiver interrupts:
+		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by reading the receive data register.
+		end if;
+
+		if OVR = '1' and RIE = '1' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		end if;
+					
+		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			-- DCD_TRANS is used to detect a low to high transition of DCDn.
+			DCD_TRANS := true;
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		elsif DCD_In = '0' then
+			DCD_TRANS := false;
+		end if;
+
+		-- The reset of the IRQ status flag:
+		-- Clear by writing to the transmit data register.
+		-- Clear by reading the receive data register.
+		if  CS = "011" and RS = '1' and E = '1' then
+			IRQ_I <= '0'; 
+		end if;
+	end process P_IRQ;
+	
+	CONTROL: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CTRL_REG <= "01000000";
+		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
+			CTRL_REG <= DATA_IN;
+		end if;
+	end process CONTROL;	
+
+	P_DCD: process
+	-- This process is some kind of tricky. Refer to the MC6850 data
+	-- sheet for more information.
+	variable READ_LOCK		: boolean;
+	variable DCD_RELEASE	: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+			READ_LOCK := true;
+			DCD_RELEASE := false;
+		elsif MCLR = '1' then
+			DCD_FLAGn <= DCD_In;
+			READ_LOCK := true;
+		elsif DCD_In = '1' then
+			DCD_FLAGn <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
+			-- Clear if receiver status register read access.
+			-- After data register has ben read and READ_LOCK again.
+			DCD_RELEASE := true;
+			READ_LOCK := true;
+			DCD_FLAGn <= DCD_In;
+		elsif DCD_In = '0' and DCD_RELEASE = true then
+			DCD_FLAGn <= '0';
+			DCD_RELEASE := false;
+		end if;
+	end process P_DCD;	
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
new file mode 100644
index 0000000..a0ea9e4
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
@@ -0,0 +1,244 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CTRL_REG has now synchronous reset to meet preset requirements.
+--   Process P_DCD has now synchronous reset to meet preset requirements.
+--   IRQ_In has now synchronous reset to meet preset requirement.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_CTRL_STATUS is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+        CS			: in bit_vector(2 downto 0); -- Active if "011".
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);   
+		DATA_EN		: out bit;
+		
+		-- Status register stuff:
+		RDRF		: in bit;	-- Receive data register full.
+		TDRE		: in bit;	-- Transmit data register empty.
+		DCDn		: in bit;	-- Data carrier detect.
+		CTSn		: in bit;	-- Clear to send.
+		FE			: in bit;	-- Framing error.
+		OVR			: in bit;	-- Overrun error.
+		PE			: in bit;	-- Parity error.
+
+		-- Control register stuff:
+		MCLR		: buffer bit; -- Master clear (high active).
+		RTSn		: out bit; -- Request to send.
+		CDS			: out bit_vector(1 downto 0); -- Clock control.
+		WS			: out bit_vector(2 downto 0); -- Word select.
+		TC			: out bit_vector(1 downto 0); -- Transmit control.
+		IRQn		: out bit -- Interrupt request.
+       );                                              
+end entity WF6850IP_CTRL_STATUS;
+
+architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal RIE			: bit;
+signal IRQ_I		: bit;
+signal CTS_In		: bit;
+signal DCD_In		: bit;
+signal DCD_FLAGn	: bit;
+begin
+	P_SAMPLE: process
+	begin
+		wait until CLK = '0' and CLK' event;
+		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
+		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
+	end process P_SAMPLE;
+
+	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(6) <= PE;
+	STATUS_REG(5) <= OVR;
+	STATUS_REG(4) <= FE;
+	STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin.
+	STATUS_REG(2) <= DCD_FLAGn;
+	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
+	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
+
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	
+	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
+	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
+
+	CDS <= CTRL_REG(1 downto 0);
+	WS <= CTRL_REG(4 downto 2);
+	TC <= CTRL_REG(6 downto 5);
+	RIE <= CTRL_REG(7);
+	
+	P_IRQ: process
+	variable DCD_OVR_LOCK	: boolean;
+	variable DCD_LOCK	    : boolean;
+	variable DCD_TRANS	    : boolean;	
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_OVR_LOCK := false;
+			IRQn <= '1';
+			IRQ_I <= '0';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+		end if;
+
+-- Clear interrupts when disabled.
+if CTRL_REG(7) = '0' then
+    IRQn <= '1';
+    IRQ_I <= '0';
+elsif CTRL_REG(6 downto 5) /= "01" then
+    IRQn <= '1';
+    IRQ_I <= '0';
+end if;
+
+		-- Transmitter interrupt:
+        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by writing to the transmit data register.
+		end if;
+					
+		-- Receiver interrupts:
+		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by reading the receive data register.
+		end if;
+
+		if OVR = '1' and RIE = '1' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		end if;
+					
+		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			-- DCD_TRANS is used to detect a low to high transition of DCDn.
+			DCD_TRANS := true;
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		elsif DCD_In = '0' then
+			DCD_TRANS := false;
+		end if;
+
+		-- The reset of the IRQ status flag:
+		-- Clear by writing to the transmit data register.
+		-- Clear by reading the receive data register.
+		if  CS = "011" and RS = '1' and E = '1' then
+			IRQ_I <= '0'; 
+		end if;
+	end process P_IRQ;
+	
+	CONTROL: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CTRL_REG <= "01000000";
+		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
+			CTRL_REG <= DATA_IN;
+		end if;
+	end process CONTROL;	
+
+	P_DCD: process
+	-- This process is some kind of tricky. Refer to the MC6850 data
+	-- sheet for more information.
+	variable READ_LOCK		: boolean;
+	variable DCD_RELEASE	: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+			READ_LOCK := true;
+			DCD_RELEASE := false;
+		elsif MCLR = '1' then
+			DCD_FLAGn <= DCD_In;
+			READ_LOCK := true;
+		elsif DCD_In = '1' then
+			DCD_FLAGn <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
+			-- Clear if receiver status register read access.
+			-- After data register has ben read and READ_LOCK again.
+			DCD_RELEASE := true;
+			READ_LOCK := true;
+			DCD_FLAGn <= DCD_In;
+		elsif DCD_In = '0' and DCD_RELEASE = true then
+			DCD_FLAGn <= '0';
+			DCD_RELEASE := false;
+		end if;
+	end process P_DCD;	
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
new file mode 100644
index 0000000..755e018
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
@@ -0,0 +1,415 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's receiver unit.                                        ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_RECEIVE is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+
+		RDRF				: buffer bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end entity WF6850IP_RECEIVE;
+
+architecture BEHAVIOR of WF6850IP_RECEIVE is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal RXDATA_I		: bit;
+signal RXDATA_S		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal CLK_STRB		: bit;
+signal BITCNT		: std_logic_vector(2 downto 0);
+begin
+	P_SAMPLE: process
+	-- This filter provides a synchronisation to the system
+	-- clock, even for random baud rates of the received data
+	-- stream.
+	variable FLT_TMP	: integer range 0 to 2;
+	begin
+		wait until CLK = '1' and CLK' event;
+		--
+		RXDATA_I <= RXDATA;
+		--
+		if RXDATA_I = '1' and FLT_TMP < 2 then
+			FLT_TMP := FLT_TMP + 1;
+		elsif RXDATA_I = '1' then
+			RXDATA_S <= '1';
+		elsif RXDATA_I = '0' and FLT_TMP > 0 then
+			FLT_TMP := FLT_TMP - 1;
+		elsif RXDATA_I = '0' then
+			RXDATA_S <= '0';
+		end if;
+	end process P_SAMPLE;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif RCV_STATE = IDLE then
+			-- Preset the CLKDIV with the start delays.
+			if CDS = "01" then
+				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+			elsif CDS = "10" then
+				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
+			end if;
+	 		CLK_STRB <= '0';
+		else
+			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				--
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= SHIFT_REG;
+			end if;
+		end if;
+	end process DATAREG;	
+    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
+    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	OVERRUN: process(RESETn, CLK)
+	variable OVR_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OVR_I := '0';
+			OVR <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				OVR_I := '0';
+				OVR <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+				OVR_I := RDRF;
+			end if;
+			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+				-- If an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OVR_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OVR <= '1';
+					FIRST_READ := true;
+				else
+					OVR <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable PE_I		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				PE <= '0';
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				PE_I := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				    	PE_I := PAR_TMP xor RXDATA_S;
+					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+						PE_I := not PAR_TMP xor RXDATA_S;
+					else -- No parity for WS = "100" and WS = "101".
+						PE_I := '0';		
+					end if;
+				end if;
+			end if;
+			-- Transmit the parity flag together with the data
+			-- In other words: no parity to the status register
+			-- when RDRF inhibits the data transfer to the
+			-- receiver data register.
+			if RCV_STATE = SYNC and RDRF = '0' then
+				PE <= PE_I;
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				PE <= '0'; -- Clear when reading the data register.
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	P_RDRF: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RDRF <= '0';
+			elsif RCV_STATE = SYNC then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process P_RDRF;
+	
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if RXDATA_S = '0' and CDS = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif RXDATA_S = '0' and CDS = "01" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				elsif RXDATA_S = '0' and CDS = "10" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
+					else
+						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
+					end if;
+				else
+					RCV_NEXT_STATE <= WAIT_START; -- Stay.
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= STOP1;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif WS = "000" or WS = "001" or WS = "100" then
+						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC;
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
new file mode 100644
index 0000000..e8c82b2
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
@@ -0,0 +1,415 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's receiver unit.                                        ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_RECEIVE is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+
+		RDRF				: buffer bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end entity WF6850IP_RECEIVE;
+
+architecture BEHAVIOR of WF6850IP_RECEIVE is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal RXDATA_I		: bit;
+signal RXDATA_S		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal CLK_STRB		: bit;
+signal BITCNT		: std_logic_vector(2 downto 0);
+begin
+	P_SAMPLE: process
+	-- This filter provides a synchronisation to the system
+	-- clock, even for random baud rates of the received data
+	-- stream.
+	variable FLT_TMP	: integer range 0 to 2;
+	begin
+		wait until CLK = '1' and CLK' event;
+		--
+		RXDATA_I <= RXDATA;
+		--
+		if RXDATA_I = '1' and FLT_TMP < 2 then
+			FLT_TMP := FLT_TMP + 1;
+		elsif RXDATA_I = '1' then
+			RXDATA_S <= '1';
+		elsif RXDATA_I = '0' and FLT_TMP > 0 then
+			FLT_TMP := FLT_TMP - 1;
+		elsif RXDATA_I = '0' then
+			RXDATA_S <= '0';
+		end if;
+	end process P_SAMPLE;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif RCV_STATE = IDLE then
+			-- Preset the CLKDIV with the start delays.
+			if CDS = "01" then
+				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+			elsif CDS = "10" then
+				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
+			end if;
+	 		CLK_STRB <= '0';
+		else
+			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				--
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= SHIFT_REG;
+			end if;
+		end if;
+	end process DATAREG;	
+--DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
+--DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
+DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	OVERRUN: process(RESETn, CLK)
+	variable OVR_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OVR_I := '0';
+			OVR <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				OVR_I := '0';
+				OVR <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+				OVR_I := RDRF;
+			end if;
+			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+				-- If an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OVR_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OVR <= '1';
+					FIRST_READ := true;
+				else
+					OVR <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable PE_I		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				PE <= '0';
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				PE_I := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				    	PE_I := PAR_TMP xor RXDATA_S;
+					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+						PE_I := not PAR_TMP xor RXDATA_S;
+					else -- No parity for WS = "100" and WS = "101".
+						PE_I := '0';		
+					end if;
+				end if;
+			end if;
+			-- Transmit the parity flag together with the data
+			-- In other words: no parity to the status register
+			-- when RDRF inhibits the data transfer to the
+			-- receiver data register.
+			if RCV_STATE = SYNC and RDRF = '0' then
+				PE <= PE_I;
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				PE <= '0'; -- Clear when reading the data register.
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	P_RDRF: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RDRF <= '0';
+			elsif RCV_STATE = SYNC then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process P_RDRF;
+	
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if RXDATA_S = '0' and CDS = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif RXDATA_S = '0' and CDS = "01" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				elsif RXDATA_S = '0' and CDS = "10" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
+					else
+						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
+					end if;
+				else
+					RCV_NEXT_STATE <= WAIT_START; -- Stay.
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= STOP1;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif WS = "000" or WS = "001" or WS = "100" then
+						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC;
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
new file mode 100644
index 0000000..60a7885
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
@@ -0,0 +1,135 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA		        : inout std_logic_vector(7 downto 0);   
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out std_logic;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP;
+
+architecture STRUCTURE of WF6850IP_TOP is
+component WF6850IP_TOP_SOC
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end component;
+signal DATA_OUT     : std_logic_vector(7 downto 0);
+signal DATA_EN      : bit;
+signal IRQ_In       : bit;
+begin
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+    IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
+
+    I_UART: WF6850IP_TOP_SOC
+      port map(CLK          => CLK,
+               RESETn       => RESETn,
+               CS2n         => CS2n,
+               CS1          => CS1,
+               CS0          => CS0,
+               E            => E,
+               RWn          => RWn,
+               RS           => RS,
+               DATA_IN      => DATA,
+               DATA_OUT     => DATA_OUT,
+               DATA_EN      => DATA_EN,
+               TXCLK        => TXCLK,
+               RXCLK        => RXCLK,
+               RXDATA       => RXDATA,
+               CTSn         => CTSn,
+               DCDn         => DCDn,
+               IRQn         => IRQ_In,
+               TXDATA       => TXDATA,
+               RTSn         => RTSn
+           );                                              
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
new file mode 100644
index 0000000..cbca6bd
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
@@ -0,0 +1,255 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP_SOC is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP_SOC;
+
+architecture STRUCTURE of WF6850IP_TOP_SOC is
+component WF6850IP_CTRL_STATUS
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+        CS			: in bit_vector(2 downto 0);
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);  
+		DATA_EN		: out bit;
+		RDRF		: in bit;
+		TDRE		: in bit;
+		DCDn		: in bit;
+		CTSn		: in bit;
+		FE			: in bit;
+		OVR			: in bit;
+		PE			: in bit;
+		MCLR		: out bit;
+		RTSn		: out bit;
+		CDS			: out bit_vector(1 downto 0);
+		WS			: out bit_vector(2 downto 0);
+		TC			: out bit_vector(1 downto 0);
+		IRQn		: out bit
+       );                                              
+end component;
+
+component WF6850IP_RECEIVE
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+		RDRF				: out bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end component;
+
+component WF6850IP_TRANSMIT
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in bit_vector(7 downto 0);   
+		CTSn				: in bit;
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        TXCLK				: in bit;
+		TDRE				: out bit;        
+        TXDATA				: out bit
+       );                                              
+end component;
+signal DATA_IN_I	: bit_vector(7 downto 0);
+signal DATA_RX		: bit_vector(7 downto 0);
+signal DATA_RX_EN	: bit;
+signal DATA_CTRL	: bit_vector(7 downto 0);
+signal DATA_CTRL_EN	: bit;
+signal RDRF_I		: bit;
+signal TDRE_I		: bit;
+signal FE_I			: bit;
+signal OVR_I		: bit;
+signal PE_I			: bit;
+signal MCLR_I		: bit;
+signal CDS_I		: bit_vector(1 downto 0);
+signal WS_I			: bit_vector(2 downto 0);
+signal TC_I			: bit_vector(1 downto 0);
+signal IRQ_In		: bit;
+begin
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
+	DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
+				To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
+				
+	IRQn <= '0' when IRQ_In = '0' else '1';
+
+	I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
+	port map(
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			DATA_OUT	=> DATA_CTRL,
+			DATA_EN		=> DATA_CTRL_EN,
+			RDRF		=> RDRF_I,
+			TDRE		=> TDRE_I,
+			DCDn		=> DCDn,
+			CTSn		=> CTSn,
+			FE			=> FE_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			MCLR		=> MCLR_I,
+			RTSn		=> RTSn,
+			CDS			=> CDS_I,
+			WS			=> WS_I,
+			TC			=> TC_I,
+			IRQn		=> IRQ_In
+	);                                              
+
+	I_UART_RECEIVE: WF6850IP_RECEIVE
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_OUT	=> DATA_RX,
+			DATA_EN		=> DATA_RX_EN,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			RXCLK		=> RXCLK,
+			RXDATA		=> RXDATA,
+			RDRF		=> RDRF_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			FE			=> FE_I
+	);                                              
+
+	I_UART_TRANSMIT: WF6850IP_TRANSMIT
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			CTSn		=> CTSn,
+			TC			=> TC_I,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			TDRE		=> TDRE_I,
+			TXCLK		=> TXCLK,
+			TXDATA		=> TXDATA
+	);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
new file mode 100644
index 0000000..6f80a67
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
@@ -0,0 +1,252 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP_SOC is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP_SOC;
+
+architecture STRUCTURE of WF6850IP_TOP_SOC is
+component WF6850IP_CTRL_STATUS
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+        CS			: in bit_vector(2 downto 0);
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);  
+		DATA_EN		: out bit;
+		RDRF		: in bit;
+		TDRE		: in bit;
+		DCDn		: in bit;
+		CTSn		: in bit;
+		FE			: in bit;
+		OVR			: in bit;
+		PE			: in bit;
+		MCLR		: out bit;
+		RTSn		: out bit;
+		CDS			: out bit_vector(1 downto 0);
+		WS			: out bit_vector(2 downto 0);
+		TC			: out bit_vector(1 downto 0);
+		IRQn		: out bit
+       );                                              
+end component;
+
+component WF6850IP_RECEIVE
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+		RDRF				: out bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end component;
+
+component WF6850IP_TRANSMIT
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in bit_vector(7 downto 0);   
+		CTSn				: in bit;
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        TXCLK				: in bit;
+		TDRE				: out bit;        
+        TXDATA				: out bit
+       );                                              
+end component;
+signal DATA_IN_I	: bit_vector(7 downto 0);
+signal DATA_RX		: bit_vector(7 downto 0);
+signal DATA_RX_EN	: bit;
+signal DATA_CTRL	: bit_vector(7 downto 0);
+signal DATA_CTRL_EN	: bit;
+signal RDRF_I		: bit;
+signal TDRE_I		: bit;
+signal FE_I			: bit;
+signal OVR_I		: bit;
+signal PE_I			: bit;
+signal MCLR_I		: bit;
+signal CDS_I		: bit_vector(1 downto 0);
+signal WS_I			: bit_vector(2 downto 0);
+signal TC_I			: bit_vector(1 downto 0);
+signal IRQ_In		: bit;
+begin
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
+	DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
+				To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
+				
+	IRQn <= '0' when IRQ_In = '0' else '1';
+
+	I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
+	port map(
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			DATA_OUT	=> DATA_CTRL,
+			DATA_EN		=> DATA_CTRL_EN,
+			RDRF		=> RDRF_I,
+			TDRE		=> TDRE_I,
+			DCDn		=> DCDn,
+			CTSn		=> CTSn,
+			FE			=> FE_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			MCLR		=> MCLR_I,
+			RTSn		=> RTSn,
+			CDS			=> CDS_I,
+			WS			=> WS_I,
+			TC			=> TC_I,
+			IRQn		=> IRQ_In
+	);                                              
+
+	I_UART_RECEIVE: WF6850IP_RECEIVE
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_OUT	=> DATA_RX,
+			DATA_EN		=> DATA_RX_EN,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			RXCLK		=> RXCLK,
+			RXDATA		=> RXDATA,
+			RDRF		=> RDRF_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			FE			=> FE_I
+	);                                              
+
+	I_UART_TRANSMIT: WF6850IP_TRANSMIT
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			CTSn		=> CTSn,
+			TC			=> TC_I,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			TDRE		=> TDRE_I,
+			TXCLK		=> TXCLK,
+			TXDATA		=> TXDATA
+	);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
new file mode 100644
index 0000000..c8ae6fc
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
@@ -0,0 +1,339 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's transmitter unit.                                     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/11/01 WF
+--   Fixed the T_DRE process concerning the TDRE <= '1' setting.
+--   Thanks to Lyndon Amsdon finding the bug.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TRANSMIT is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in bit_vector(7 downto 0);   
+
+		CTSn				: in bit;
+
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        TXCLK				: in bit;
+
+		TDRE				: buffer bit;
+        TXDATA				: out bit
+       );                                              
+end entity WF6850IP_TRANSMIT;
+
+architecture BEHAVIOR of WF6850IP_TRANSMIT is
+type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+begin
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	TXDATA <= 	'1' 			when TR_STATE = IDLE 		else
+				'1' 			when TR_STATE = LOAD_SHFT 	else
+				'0' 			when TR_STATE = START 		else
+				SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+				PARITY_I		when TR_STATE = PARITY 		else
+				'1'				when TR_STATE = STOP1 		else
+				'1'				when TR_STATE = STOP2 		else '1';
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- divider off
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif TR_STATE = IDLE then
+			-- preset the CLKDIV with the start delays
+			if CDS = "01" then
+				CLK_DIVCNT := "0010000"; -- div by 16 mode
+			elsif CDS = "10" then
+				CLK_DIVCNT := "1000000"; -- div by 64 mode
+			end if;
+			CLK_STRB <= '0';
+		else
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
+			elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= DATA_IN; -- 8 bit data mode.
+			end if;
+		end if;
+	end process DATAREG;	
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
+				-- If during LOAD_SHIFT the transmitter data register
+				-- is empty (TDRE = '1') the shift register will not
+				-- be loaded. When additionally TC = "11", the break
+				-- character (zero data and no stop bits) is sent.
+				SHIFT_REG <= DATA_REG;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	P_TDRE: process(RESETn, CLK)
+	-- Transmit data register empty flag.
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			TDRE <= '1';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TDRE <= '1';
+            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+				-- Data has been loaded to shift register, thus data register is free again.
+				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
+				-- entering the state now.
+				TDRE <= '1';
+			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
+				LOCK := true;
+			elsif E = '0' and LOCK = true then
+				-- This construction clears TDRE after the falling edge of E
+				-- and after the transmit data register has been written to.
+				TDRE <= '0';
+				LOCK := false;
+			end if;
+		end if;
+	end process P_TDRE;
+
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity for WS = "100" and WS = "101".
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TR_STATE <= IDLE;
+			else
+				TR_STATE <= TR_NEXT_STATE;
+			end if;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				if TDRE = '1' and TC = "11" then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty.
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE;
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						if TDRE = '1' and TC = "11" then
+							-- Break condition, do not send a stop bit.
+							TR_NEXT_STATE <= IDLE;
+						else
+							TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+						end if;
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if TDRE = '1' and TC = "11" then
+						-- Break condition, do not send a stop bit.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
+					TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE;
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
new file mode 100644
index 0000000..bcff094
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
@@ -0,0 +1,339 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's transmitter unit.                                     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/11/01 WF
+--   Fixed the T_DRE process concerning the TDRE <= '1' setting.
+--   Thanks to Lyndon Amsdon finding the bug.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TRANSMIT is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in bit_vector(7 downto 0);   
+
+		CTSn				: in bit;
+
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        TXCLK				: in bit;
+
+		TDRE				: buffer bit;
+        TXDATA				: out bit
+       );                                              
+end entity WF6850IP_TRANSMIT;
+
+architecture BEHAVIOR of WF6850IP_TRANSMIT is
+type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+begin
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	TXDATA <= 	'1' 			when TR_STATE = IDLE 		else
+				'1' 			when TR_STATE = LOAD_SHFT 	else
+				'0' 			when TR_STATE = START 		else
+				SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+				PARITY_I		when TR_STATE = PARITY 		else
+				'1'				when TR_STATE = STOP1 		else
+				'1'				when TR_STATE = STOP2 		else '1';
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- divider off
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif TR_STATE = IDLE then
+			-- preset the CLKDIV with the start delays
+			if CDS = "01" then
+				CLK_DIVCNT := "0010000"; -- div by 16 mode
+			elsif CDS = "10" then
+				CLK_DIVCNT := "1000000"; -- div by 64 mode
+			end if;
+			CLK_STRB <= '0';
+		else
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
+			elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= DATA_IN; -- 8 bit data mode.
+			end if;
+		end if;
+	end process DATAREG;	
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
+				-- If during LOAD_SHIFT the transmitter data register
+				-- is empty (TDRE = '1') the shift register will not
+				-- be loaded. When additionally TC = "11", the break
+				-- character (zero data and no stop bits) is sent.
+				SHIFT_REG <= DATA_REG;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	P_TDRE: process(RESETn, CLK)
+	-- Transmit data register empty flag.
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			TDRE <= '1';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TDRE <= '1';
+            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+				-- Data has been loaded to shift register, thus data register is free again.
+				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
+				-- entering the state now.
+				TDRE <= '1';
+			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
+				LOCK := true;
+			elsif E = '0' and LOCK = true and CS /= "011" then
+				-- This construction clears TDRE after the falling edge of E
+				-- and after the transmit data register has been written to.
+				TDRE <= '0';
+				LOCK := false;
+			end if;
+		end if;
+	end process P_TDRE;
+
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity for WS = "100" and WS = "101".
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TR_STATE <= IDLE;
+			else
+				TR_STATE <= TR_NEXT_STATE;
+			end if;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				if TDRE = '1' and TC = "11" then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty.
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE;
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						if TDRE = '1' and TC = "11" then
+							-- Break condition, do not send a stop bit.
+							TR_NEXT_STATE <= IDLE;
+						else
+							TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+						end if;
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if TDRE = '1' and TC = "11" then
+						-- Break condition, do not send a stop bit.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
+					TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE;
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.bsf b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
new file mode 100644
index 0000000..f4d66a5
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
@@ -0,0 +1,95 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
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+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
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+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
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+	(port
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+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
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+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
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+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
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+		(line (pt 0 144)(pt 16 144)(line_width 1))
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+	(port
+		(pt 160 72)
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+		(text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
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+		(pt 160 96)
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+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
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+		(line (pt 160 96)(pt 144 96)(line_width 3))
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+		(text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
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+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.cmp b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.cmp
new file mode 100644
index 0000000..1f8ad52
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.cmp
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component dcfifo0
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.qip b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.qip
new file mode 100644
index 0000000..a22ffe4
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"]
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd
new file mode 100644
index 0000000..9db22fa
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+END dcfifo0;
+
+
+ARCHITECTURE SYN OF dcfifo0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (9 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(9 DOWNTO 0);
+	q    <= sub_wire1(31 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 1024,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 8,
+		lpm_widthu => 10,
+		lpm_widthu_r => 8,
+		lpm_width_r => 32,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "32"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
new file mode 100644
index 0000000..c3ca670
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END dcfifo0;
+
+
+ARCHITECTURE SYN OF dcfifo0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(4 DOWNTO 0);
+	q    <= sub_wire1(15 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 32,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 8,
+		lpm_widthu => 5,
+		lpm_widthu_r => 4,
+		lpm_width_r => 16,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "32"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "16"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.bsf b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
new file mode 100644
index 0000000..7a4a386
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
@@ -0,0 +1,95 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(port
+		(pt 160 120)
+		(output)
+		(text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8)))
+		(text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8)))
+		(line (pt 160 120)(pt 144 120)(line_width 3))
+	)
+	(drawing
+		(text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.cmp b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.cmp
new file mode 100644
index 0000000..a1b8d55
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.cmp
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component dcfifo1
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.qip b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.qip
new file mode 100644
index 0000000..bf1428c
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"]
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd
new file mode 100644
index 0000000..d05dd0a
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo1.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+END dcfifo1;
+
+
+ARCHITECTURE SYN OF dcfifo1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (9 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdusedw	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+	rdusedw    <= sub_wire1(9 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 256,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 32,
+		lpm_widthu => 8,
+		lpm_widthu_r => 10,
+		lpm_width_r => 8,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		q => sub_wire0,
+		rdusedw => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "32"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
new file mode 100644
index 0000000..e7c6ae6
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo1.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END dcfifo1;
+
+
+ARCHITECTURE SYN OF dcfifo1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(3 DOWNTO 0);
+	q    <= sub_wire1(7 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 16,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 16,
+		lpm_widthu => 4,
+		lpm_widthu_r => 5,
+		lpm_width_r => 8,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "16"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "16"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
new file mode 100644
index 0000000..a455469
--- /dev/null
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
@@ -0,0 +1,478 @@
+TITLE "INTERRUPT HANDLER UND C1287";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_LONG.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN interrupt_handler
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	MAIN_CLK : INPUT;
+	nFB_WR : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	FB_ADR[31..0] : INPUT;
+	PIC_INT : INPUT;
+	E0_INT : INPUT;
+	DVI_INT : INPUT;
+	nPCI_INTA : INPUT;
+	nPCI_INTB : INPUT;
+	nPCI_INTC : INPUT;
+	nPCI_INTD : INPUT;
+	nMFP_INT : INPUT;
+	nFB_OE : INPUT;
+	DSP_INT : INPUT;
+	VSYNC : INPUT;
+	HSYNC : INPUT;
+	DMA_DRQ : INPUT;
+	nIRQ[7..2] : OUTPUT;
+	INT_HANDLER_TA : OUTPUT;
+	ACP_CONF[31..0] : OUTPUT;
+	TIN0 : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]				:NODE;
+	INT_CTR[31..0]			:DFFE;
+	INT_CTR_CS				:NODE;
+	INT_LATCH[31..0]		:DFF;
+	INT_LATCH_CS			:NODE;
+	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR_CS			:NODE;
+	INT_IN[31..0]			:NODE;
+	INT_ENA[31..0]			:DFFE;
+	INT_ENA_CS				:NODE;
+	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF_CS				:NODE;
+	PSEUDO_BUS_ERROR		:NODE;
+	UHR_AS					:NODE;
+	UHR_DS					:NODE;
+	RTC_ADR[5..0]			:DFFE;
+	ACHTELSEKUNDEN[2..0]	:DFFE;
+	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		:DFF;
+	INC_SEC					:NODE;
+	INC_MIN					:NODE;
+	INC_STD					:NODE;
+	INC_TAG					:NODE;
+	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
+	WINTERZEIT				:NODE;
+	SOMMERZEIT				:NODE;
+	INC_MONAT				:NODE;
+	INC_JAHR				:NODE;
+	UPDATE_ON				:NODE;
+	
+BEGIN
+-- BYT SELECT
+	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+	INT_CTR[].CLK = MAIN_CLK;
+	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
+	INT_CTR[] = FB_AD[];
+	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
+	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
+	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
+	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
+	INT_ENA[] = FB_AD[];
+	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
+	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
+	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
+	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+	INT_CLEAR[].CLK = MAIN_CLK;
+	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
+	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
+	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
+	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
+	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT LATCH REGISTER READ ONLY
+	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+-- INTERRUPT
+	!nIRQ2 = HSYNC 						& INT_ENA[26];
+	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
+	!nIRQ4 = VSYNC 						& INT_ENA[28];
+	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
+	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
+	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
+
+PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
+							#  FB_ADR[19..4]==H"F8E0"			-- VME
+							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
+							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
+							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
+							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
+							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+-- IF VIDEO ADR CHANGE
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+
+-- INTERRUPT LATCH
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
+	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
+	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
+	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
+	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
+	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
+	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
+	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
+	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
+	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	
+-- INTERRUPT CLEAR
+	INT_LATCH[].CLRN = !INT_CLEAR[];
+	
+-- INT_IN
+	INT_IN0 = PIC_INT;
+	INT_IN1 = E0_INT;
+	INT_IN2 = DVI_INT;
+	INT_IN3 = !nPCI_INTA;
+	INT_IN4 = !nPCI_INTB;
+	INT_IN5 = !nPCI_INTC;
+	INT_IN6 = !nPCI_INTD;
+	INT_IN7 = DSP_INT;
+	INT_IN8 = VSYNC;
+	INT_IN9 = HSYNC;
+	INT_IN[25..10] = H"0";
+	INT_IN26 = HSYNC; 
+	INT_IN27 = INT_CTR0; 
+	INT_IN28 = VSYNC; 
+	INT_IN29 = INT_LATCH[]!=H"00000000";
+	INT_IN30 = !nMFP_INT; 
+	INT_IN31 = DMA_DRQ; 
+--***************************************************************************************
+-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
+	ACP_CONF[].CLK = MAIN_CLK;
+	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
+	ACP_CONF[] = FB_AD[];
+	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
+	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
+	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
+	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
+--***************************************************************************************
+	
+--------------------------------------------------------------	
+-- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+----------------------------------------------------------
+	RTC_ADR[].CLK = MAIN_CLK;
+	RTC_ADR[] = FB_AD[21..16];
+	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
+	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
+	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
+	WERTE[][].CLK = MAIN_CLK;
+	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[7..0][1] = FB_AD[23..16];
+	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[7..0][3] = FB_AD[23..16];
+	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[7..0][5] = FB_AD[23..16];
+	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[7..0][10] = FB_AD[23..16];
+	WERTE[7..0][11] = FB_AD[23..16];
+	WERTE[7..0][12] = FB_AD[23..16];
+	WERTE[7..0][13] = FB_AD[23..16];
+	WERTE[7..0][14] = FB_AD[23..16];
+	WERTE[7..0][15] = FB_AD[23..16];
+	WERTE[7..0][16] = FB_AD[23..16];
+	WERTE[7..0][17] = FB_AD[23..16];
+	WERTE[7..0][18] = FB_AD[23..16];
+	WERTE[7..0][19] = FB_AD[23..16];
+	WERTE[7..0][20] = FB_AD[23..16];
+	WERTE[7..0][21] = FB_AD[23..16];
+	WERTE[7..0][22] = FB_AD[23..16];
+	WERTE[7..0][23] = FB_AD[23..16];
+	WERTE[7..0][24] = FB_AD[23..16];
+	WERTE[7..0][25] = FB_AD[23..16];
+	WERTE[7..0][26] = FB_AD[23..16];
+	WERTE[7..0][27] = FB_AD[23..16];
+	WERTE[7..0][28] = FB_AD[23..16];
+	WERTE[7..0][29] = FB_AD[23..16];
+	WERTE[7..0][30] = FB_AD[23..16];
+	WERTE[7..0][31] = FB_AD[23..16];
+	WERTE[7..0][32] = FB_AD[23..16];
+	WERTE[7..0][33] = FB_AD[23..16];
+	WERTE[7..0][34] = FB_AD[23..16];
+	WERTE[7..0][35] = FB_AD[23..16];
+	WERTE[7..0][36] = FB_AD[23..16];
+	WERTE[7..0][37] = FB_AD[23..16];
+	WERTE[7..0][38] = FB_AD[23..16];
+	WERTE[7..0][39] = FB_AD[23..16];
+	WERTE[7..0][40] = FB_AD[23..16];
+	WERTE[7..0][41] = FB_AD[23..16];
+	WERTE[7..0][42] = FB_AD[23..16];
+	WERTE[7..0][43] = FB_AD[23..16];
+	WERTE[7..0][44] = FB_AD[23..16];
+	WERTE[7..0][45] = FB_AD[23..16];
+	WERTE[7..0][46] = FB_AD[23..16];
+	WERTE[7..0][47] = FB_AD[23..16];
+	WERTE[7..0][48] = FB_AD[23..16];
+	WERTE[7..0][49] = FB_AD[23..16];
+	WERTE[7..0][50] = FB_AD[23..16];
+	WERTE[7..0][51] = FB_AD[23..16];
+	WERTE[7..0][52] = FB_AD[23..16];
+	WERTE[7..0][53] = FB_AD[23..16];
+	WERTE[7..0][54] = FB_AD[23..16];
+	WERTE[7..0][55] = FB_AD[23..16];
+	WERTE[7..0][56] = FB_AD[23..16];
+	WERTE[7..0][57] = FB_AD[23..16];
+	WERTE[7..0][58] = FB_AD[23..16];
+	WERTE[7..0][59] = FB_AD[23..16];
+	WERTE[7..0][60] = FB_AD[23..16];
+	WERTE[7..0][61] = FB_AD[23..16];
+	WERTE[7..0][62] = FB_AD[23..16];
+	WERTE[7..0][63] = FB_AD[23..16];
+	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
+	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
+	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
+	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
+	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
+	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
+	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
+	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
+	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
+	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
+	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
+	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
+	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
+	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
+	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
+	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
+	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
+	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
+	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
+	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
+	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
+	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
+	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
+	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
+	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
+	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
+	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
+	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
+	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
+	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
+	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
+	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
+	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
+	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
+	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
+	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
+	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
+	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
+	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
+	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
+	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
+	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
+	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
+	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
+	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
+	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
+	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
+	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
+	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
+	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
+	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
+	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
+	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
+	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
+	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
+	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
+	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
+	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+	UPDATE_ON = !WERTE[7][11];		
+	WERTE[6][10].CLRN = GND;	-- KEIN UIP
+	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
+	WERTE[2][11] = VCC;	-- IMMER BINARY
+	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
+	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
+	WERTE[7][13] = VCC;	-- IMMER RICHTIG
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
+	WERTE[0][13] = SOMMERZEIT;
+	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
+	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+-- ACHTELSEKUNDEN
+	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
+	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
+	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+-- SEKUNDEN
+	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
+	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+-- MINUTEN
+	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
+	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+-- STUNDEN
+	INC_STD = INC_MIN & WERTE[][2]==59;							  
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
+	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
+-- WOCHENTAG UND TAG 
+	INC_TAG = INC_STD & WERTE[][2]==23;						
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
+			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
+	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
+	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
+							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
+							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
+							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
+			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
+	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+-- MONATE
+	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
+			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
+	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+-- JAHR		   
+	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
+	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+-- TRISTATE OUTPUT
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[31..24] 
+				  #	INT_ENA_CS   & INT_ENA[31..24]
+				  #	INT_LATCH_CS & INT_LATCH[31..24]
+				  # INT_CLEAR_CS & INT_IN[31..24]
+				  # ACP_CONF_CS  & ACP_CONF[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[23..16] = lpm_bustri_BYT(
+				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
+				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
+				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
+				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
+				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
+				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
+				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
+				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
+				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
+				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
+				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
+				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
+				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
+				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
+				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
+				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
+				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
+				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
+				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
+				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
+				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
+				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
+				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
+				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
+				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
+				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
+				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
+				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
+				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
+				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
+				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
+				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
+				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
+				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
+				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
+				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
+				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
+				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
+				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
+				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
+				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
+				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
+				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
+				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
+				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
+				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
+				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
+				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
+				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
+				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
+				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
+				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
+				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
+				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
+				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
+				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
+				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
+				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
+				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
+				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
+				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
+				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
+				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
+				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
+				 # (0,RTC_ADR[])			   & UHR_AS
+				 # INT_CTR_CS   & INT_CTR[23..16] 
+				 # INT_ENA_CS   & INT_ENA[23..16]
+				 # INT_LATCH_CS & INT_LATCH[23..16]
+				 # INT_CLEAR_CS & INT_IN[23..16]
+				 # ACP_CONF_CS  & ACP_CONF[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[15..8] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[15..8] 
+				  #	INT_ENA_CS   & INT_ENA[15..8]
+				  #	INT_LATCH_CS & INT_LATCH[15..8]
+				  # INT_CLEAR_CS & INT_IN[15..8]
+				  # ACP_CONF_CS  & ACP_CONF[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[7..0] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[7..0] 
+				  #	INT_ENA_CS   & INT_ENA[7..0]
+				  #	INT_LATCH_CS & INT_LATCH[7..0]
+				  # INT_CLEAR_CS & INT_IN[7..0]
+				  # ACP_CONF_CS  & ACP_CONF[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+
+	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
+END;
+
+
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
new file mode 100644
index 0000000..e3e49eb
--- /dev/null
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
@@ -0,0 +1,478 @@
+TITLE "INTERRUPT HANDLER UND C1287";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_LONG.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN interrupt_handler
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	MAIN_CLK : INPUT;
+	nFB_WR : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	FB_ADR[31..0] : INPUT;
+	PIC_INT : INPUT;
+	E0_INT : INPUT;
+	DVI_INT : INPUT;
+	nPCI_INTA : INPUT;
+	nPCI_INTB : INPUT;
+	nPCI_INTC : INPUT;
+	nPCI_INTD : INPUT;
+	nMFP_INT : INPUT;
+	nFB_OE : INPUT;
+	DSP_INT : INPUT;
+	VSYNC : INPUT;
+	HSYNC : INPUT;
+	DMA_DRQ : INPUT;
+	nIRQ[7..2] : OUTPUT;
+	INT_HANDLER_TA : OUTPUT;
+	ACP_CONF[31..0] : OUTPUT;
+	TIN0 : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]				:NODE;
+	INT_CTR[31..0]			:DFFE;
+	INT_CTR_CS				:NODE;
+	INT_LATCH[31..0]		:DFF;
+	INT_LATCH_CS			:NODE;
+	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR_CS			:NODE;
+	INT_IN[31..0]			:NODE;
+	INT_ENA[31..0]			:DFFE;
+	INT_ENA_CS				:NODE;
+	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF_CS				:NODE;
+	PSEUDO_BUS_ERROR		:NODE;
+	UHR_AS					:NODE;
+	UHR_DS					:NODE;
+	RTC_ADR[5..0]			:DFFE;
+	ACHTELSEKUNDEN[2..0]	:DFFE;
+	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		:DFF;
+	INC_SEC					:NODE;
+	INC_MIN					:NODE;
+	INC_STD					:NODE;
+	INC_TAG					:NODE;
+	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
+	WINTERZEIT				:NODE;
+	SOMMERZEIT				:NODE;
+	INC_MONAT				:NODE;
+	INC_JAHR				:NODE;
+	UPDATE_ON				:NODE;
+	
+BEGIN
+-- BYT SELECT
+	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+	INT_CTR[].CLK = MAIN_CLK;
+	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
+	INT_CTR[] = FB_AD[];
+	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
+	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
+	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
+	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
+	INT_ENA[] = FB_AD[];
+	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
+	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
+	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
+	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+	INT_CLEAR[].CLK = MAIN_CLK;
+	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
+	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
+	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
+	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
+	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT LATCH REGISTER READ ONLY
+	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+-- INTERRUPT
+	!nIRQ2 = HSYNC 						& INT_ENA[26];
+	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
+	!nIRQ4 = VSYNC 						& INT_ENA[28];
+	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
+	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
+	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
+
+PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
+							#  FB_ADR[19..4]==H"F8E0"			-- VME
+							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
+							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
+							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
+							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
+							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+-- IF VIDEO ADR CHANGE
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			-- VIDEO BASE ADR HIGH 0xFFFF8201/2
+
+-- INTERRUPT LATCH
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
+	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
+	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
+	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
+	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
+	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
+	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
+	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
+	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
+	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	
+-- INTERRUPT CLEAR
+	INT_LATCH[].CLRN = !INT_CLEAR[];
+	
+-- INT_IN
+	INT_IN0 = PIC_INT;
+	INT_IN1 = E0_INT;
+	INT_IN2 = DVI_INT;
+	INT_IN3 = !nPCI_INTA;
+	INT_IN4 = !nPCI_INTB;
+	INT_IN5 = !nPCI_INTC;
+	INT_IN6 = !nPCI_INTD;
+	INT_IN7 = DSP_INT;
+	INT_IN8 = VSYNC;
+	INT_IN9 = HSYNC;
+	INT_IN[25..10] = H"0";
+	INT_IN26 = HSYNC; 
+	INT_IN27 = INT_CTR0; 
+	INT_IN28 = VSYNC; 
+	INT_IN29 = INT_LATCH[]!=H"00000000";
+	INT_IN30 = !nMFP_INT; 
+	INT_IN31 = DMA_DRQ; 
+--***************************************************************************************
+-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
+	ACP_CONF[].CLK = MAIN_CLK;
+	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
+	ACP_CONF[] = FB_AD[];
+	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
+	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
+	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
+	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
+--***************************************************************************************
+	
+--------------------------------------------------------------	
+-- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+----------------------------------------------------------
+	RTC_ADR[].CLK = MAIN_CLK;
+	RTC_ADR[] = FB_AD[21..16];
+	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
+	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
+	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
+	WERTE[][].CLK = MAIN_CLK;
+	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[7..0][1] = FB_AD[23..16];
+	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[7..0][3] = FB_AD[23..16];
+	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[7..0][5] = FB_AD[23..16];
+	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[7..0][10] = FB_AD[23..16];
+	WERTE[7..0][11] = FB_AD[23..16];
+	WERTE[7..0][12] = FB_AD[23..16];
+	WERTE[7..0][13] = FB_AD[23..16];
+	WERTE[7..0][14] = FB_AD[23..16];
+	WERTE[7..0][15] = FB_AD[23..16];
+	WERTE[7..0][16] = FB_AD[23..16];
+	WERTE[7..0][17] = FB_AD[23..16];
+	WERTE[7..0][18] = FB_AD[23..16];
+	WERTE[7..0][19] = FB_AD[23..16];
+	WERTE[7..0][20] = FB_AD[23..16];
+	WERTE[7..0][21] = FB_AD[23..16];
+	WERTE[7..0][22] = FB_AD[23..16];
+	WERTE[7..0][23] = FB_AD[23..16];
+	WERTE[7..0][24] = FB_AD[23..16];
+	WERTE[7..0][25] = FB_AD[23..16];
+	WERTE[7..0][26] = FB_AD[23..16];
+	WERTE[7..0][27] = FB_AD[23..16];
+	WERTE[7..0][28] = FB_AD[23..16];
+	WERTE[7..0][29] = FB_AD[23..16];
+	WERTE[7..0][30] = FB_AD[23..16];
+	WERTE[7..0][31] = FB_AD[23..16];
+	WERTE[7..0][32] = FB_AD[23..16];
+	WERTE[7..0][33] = FB_AD[23..16];
+	WERTE[7..0][34] = FB_AD[23..16];
+	WERTE[7..0][35] = FB_AD[23..16];
+	WERTE[7..0][36] = FB_AD[23..16];
+	WERTE[7..0][37] = FB_AD[23..16];
+	WERTE[7..0][38] = FB_AD[23..16];
+	WERTE[7..0][39] = FB_AD[23..16];
+	WERTE[7..0][40] = FB_AD[23..16];
+	WERTE[7..0][41] = FB_AD[23..16];
+	WERTE[7..0][42] = FB_AD[23..16];
+	WERTE[7..0][43] = FB_AD[23..16];
+	WERTE[7..0][44] = FB_AD[23..16];
+	WERTE[7..0][45] = FB_AD[23..16];
+	WERTE[7..0][46] = FB_AD[23..16];
+	WERTE[7..0][47] = FB_AD[23..16];
+	WERTE[7..0][48] = FB_AD[23..16];
+	WERTE[7..0][49] = FB_AD[23..16];
+	WERTE[7..0][50] = FB_AD[23..16];
+	WERTE[7..0][51] = FB_AD[23..16];
+	WERTE[7..0][52] = FB_AD[23..16];
+	WERTE[7..0][53] = FB_AD[23..16];
+	WERTE[7..0][54] = FB_AD[23..16];
+	WERTE[7..0][55] = FB_AD[23..16];
+	WERTE[7..0][56] = FB_AD[23..16];
+	WERTE[7..0][57] = FB_AD[23..16];
+	WERTE[7..0][58] = FB_AD[23..16];
+	WERTE[7..0][59] = FB_AD[23..16];
+	WERTE[7..0][60] = FB_AD[23..16];
+	WERTE[7..0][61] = FB_AD[23..16];
+	WERTE[7..0][62] = FB_AD[23..16];
+	WERTE[7..0][63] = FB_AD[23..16];
+	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
+	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
+	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
+	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
+	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
+	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
+	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
+	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
+	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
+	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
+	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
+	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
+	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
+	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
+	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
+	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
+	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
+	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
+	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
+	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
+	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
+	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
+	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
+	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
+	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
+	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
+	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
+	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
+	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
+	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
+	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
+	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
+	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
+	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
+	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
+	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
+	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
+	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
+	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
+	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
+	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
+	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
+	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
+	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
+	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
+	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
+	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
+	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
+	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
+	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
+	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
+	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
+	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
+	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
+	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
+	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
+	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
+	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+	UPDATE_ON = !WERTE[7][11];		
+	WERTE[6][10].CLRN = GND;	-- KEIN UIP
+	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
+	WERTE[2][11] = VCC;	-- IMMER BINARY
+	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
+	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
+	WERTE[7][13] = VCC;	-- IMMER RICHTIG
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
+	WERTE[0][13] = SOMMERZEIT;
+	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
+	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+-- ACHTELSEKUNDEN
+	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
+	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
+	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+-- SEKUNDEN
+	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
+	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+-- MINUTEN
+	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
+	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+-- STUNDEN
+	INC_STD = INC_MIN & WERTE[][2]==59;							  
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
+	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
+-- WOCHENTAG UND TAG 
+	INC_TAG = INC_STD & WERTE[][2]==23;						
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
+			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
+	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
+	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
+							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
+							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
+							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
+			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
+	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+-- MONATE
+	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
+			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
+	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+-- JAHR		   
+	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
+	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+-- TRISTATE OUTPUT
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[31..24] 
+				  #	INT_ENA_CS   & INT_ENA[31..24]
+				  #	INT_LATCH_CS & INT_LATCH[31..24]
+				  # INT_CLEAR_CS & INT_IN[31..24]
+				  # ACP_CONF_CS  & ACP_CONF[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[23..16] = lpm_bustri_BYT(
+				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
+				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
+				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
+				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
+				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
+				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
+				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
+				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
+				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
+				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
+				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
+				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
+				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
+				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
+				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
+				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
+				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
+				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
+				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
+				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
+				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
+				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
+				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
+				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
+				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
+				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
+				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
+				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
+				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
+				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
+				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
+				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
+				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
+				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
+				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
+				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
+				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
+				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
+				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
+				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
+				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
+				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
+				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
+				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
+				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
+				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
+				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
+				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
+				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
+				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
+				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
+				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
+				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
+				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
+				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
+				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
+				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
+				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
+				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
+				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
+				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
+				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
+				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
+				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
+				 # (0,RTC_ADR[])			   & UHR_AS
+				 # INT_CTR_CS   & INT_CTR[23..16] 
+				 # INT_ENA_CS   & INT_ENA[23..16]
+				 # INT_LATCH_CS & INT_LATCH[23..16]
+				 # INT_CLEAR_CS & INT_IN[23..16]
+				 # ACP_CONF_CS  & ACP_CONF[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[15..8] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[15..8] 
+				  #	INT_ENA_CS   & INT_ENA[15..8]
+				  #	INT_LATCH_CS & INT_LATCH[15..8]
+				  # INT_CLEAR_CS & INT_IN[15..8]
+				  # ACP_CONF_CS  & ACP_CONF[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[7..0] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[7..0] 
+				  #	INT_ENA_CS   & INT_ENA[7..0]
+				  #	INT_LATCH_CS & INT_LATCH[7..0]
+				  # INT_CLEAR_CS & INT_IN[7..0]
+				  # ACP_CONF_CS  & ACP_CONF[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+
+	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
+END;
+
+
diff --git a/FPGA_by_Fredi/UNUSED b/FPGA_by_Fredi/UNUSED
new file mode 100644
index 0000000..3a7d9e6
--- /dev/null
+++ b/FPGA_by_Fredi/UNUSED
@@ -0,0 +1,27 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=3;
+DEPTH=16;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	00  :   7;
+	01  :   6;
+	02  :   5;
+	03  :   4;
+	04  :   3;
+	05  :   2;
+	06  :   1;
+	07  :   0;
+	08  :   7;
+	09  :   6;
+	0a  :   5;
+	0b  :   4;
+	0c  :   3;
+	0d  :   2;
+	0e  :   1;
+	0f  :   0;
+END;
diff --git a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
new file mode 100644
index 0000000..e09ed0b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
@@ -0,0 +1,75 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Fri Oct 16 15:40:59 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY BLITTER IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		nRSTO : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
+		BLITTER_ON : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		DDRCLK0 : IN STD_LOGIC;
+		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
+		BLITTER_RUN : OUT STD_LOGIC;
+		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
+		BLITTER_SIG : OUT STD_LOGIC;
+		BLITTER_WR : OUT STD_LOGIC;
+		BLITTER_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END BLITTER;
+
+
+--  Architecture Body
+
+ARCHITECTURE BLITTER_architecture OF BLITTER IS
+
+	
+BEGIN
+	BLITTER_RUN <= '0';
+	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
+	BLITTER_ADR <=  x"76543210";
+	BLITTER_SIG <= '0';
+	BLITTER_WR <= '0';
+	BLITTER_TA <= '0';
+
+END BLITTER_architecture;
diff --git a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
new file mode 100644
index 0000000..f674080
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
@@ -0,0 +1,75 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Fri Oct 16 15:40:59 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY BLITTER IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		nRSTO : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
+		BLITTER_ON : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		DDRCLK0 : IN STD_LOGIC;
+		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
+		BLITTER_RUN : OUT STD_LOGIC;
+		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
+		BLITTER_SIG : OUT STD_LOGIC;
+		BLITTER_WR : OUT STD_LOGIC;
+		BLITTER_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END BLITTER;
+
+
+--  Architecture Body
+
+ARCHITECTURE BLITTER_architecture OF BLITTER IS
+
+	
+BEGIN
+	BLITTER_RUN <= '0';
+	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
+	BLITTER_ADR <=  x"FEDCBA9876543210";
+	BLITTER_SIG <= '0';
+	BLITTER_WR <= '0';
+	BLITTER_TA <= '0';
+
+END BLITTER_architecture;
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf b/FPGA_by_Fredi/Video/DDR_CTR.tdf
new file mode 100644
index 0000000..d5b5ec2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf
@@ -0,0 +1,659 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 200;
+CONSTANT FIFO_HWM = 500;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[8..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
+			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
new file mode 100644
index 0000000..ead66e8
--- /dev/null
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
@@ -0,0 +1,660 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 200;
+CONSTANT FIFO_HWM = 500;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[8..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	CLEAR_FIFO_CNT : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
+			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
new file mode 100644
index 0000000..03052b4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
@@ -0,0 +1,352 @@
+TITLE "DDR_CTR_BLITTER";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR_BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FIFO_FULL : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	VSYNC : INPUT;
+	BLITTER_ON : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	VDVZ[127..0] : INPUT;
+	DDRCLK[3..0] : INPUT;
+	BA0 : OUTPUT;
+	BA1 : OUTPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FIFO_WRE : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	START_CYC_RDWR : OUTPUT;
+	DDR_WR : OUTPUT;
+	CLEAR_FIFO_CNT : OUTPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_LE[3..0] : OUTPUT;
+	BLITTER_RDE : OUTPUT;
+	DDRWR_D_SEL[1..0] : OUTPUT;
+	VDMP[7..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA[12..0]				:NODE;
+	BA0						:NODE;
+	BA1						:NODE;
+	DDR_WR					:DFF;
+	DDR_SEL					:NODE;
+	DDR_CONFIG				:NODE;
+	DDRWR_D_SEL[1..0]		:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA0					:NODE;
+	CPU_BA1					:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	BLITTER_SIG				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_RUN				:DFF;
+	BLITTER_WR				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA0				:NODE;
+	BLITTER_BA1				:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_SIG				:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA0				:NODE;
+	FIFO_BA1				:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_WRE				:DFF;
+	FIFO_ACTIVE				:NODE;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	DDR_REFRESH_ON			:NODE;
+	VIDEO_BASE_L_D[3..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[7..0]	:DFFE;
+	VIDEO_ADR_CNT[27..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[27..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			IF DDR_SEL THEN
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+			FB_LE0   = !nFB_WR;
+			IF LINE THEN							
+				FB_REGDDR = FR_S1;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S1 => 
+			FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+			FB_LE1   = !nFB_WR;
+			FB_REGDDR = FR_S2;
+		WHEN FR_S2 => 
+			FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+			FB_LE2   = !nFB_WR;
+			FB_REGDDR = FR_S3;
+		WHEN FR_S3 => 
+			FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
+			FB_LE3   = !nFB_WR;
+			FB_REGDDR = FR_WAIT;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	FIFO_ACTIVE = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	DDR_REFRESH_ON = VIDEO_RAM_CTR4;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA1 = FB_ADR13;
+	CPU_BA0 = FB_ADR12;
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	DDR_WR.CLK = DDRCLK0;
+-- SELECT LOGIC
+	DDR_SEL  =  FB_ALE & FB_AD[31..29]==B"011";
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL &  nFB_WR & !DDR_CONFIG						-- READ SOFORT LOS
+			# FR_S0   & !nFB_WR 		   							-- WRITE SPÄTER AUCH CONFIG
+			# FR_S3   & !nFB_WR &  LINE  & !DDR_CONFIG;				-- LINE WRITE
+	CPU_REQ = CPU_SIG;
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	DDR_D_SEL[].CLK = DDRCLK3;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF MAIN_CLK THEN
+				DDR_WR = DDR_WR;									-- WRITE HALTEN (VON T4)
+				DDR_SM = DS_T2;
+			ELSE
+				DDR_SM = DS_LS;										-- SYNCHRONISIEREN
+			END IF;
+		WHEN DS_T2 =>
+			IF !DDR_CONFIG THEN
+				VRAS  = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
+				VA[]  = CPU_SIG 	& CPU_ROW_ADR[]
+					#  BLITTER_SIG & BLITTER_ROW_ADR[]
+					#  FIFO_SIG 	& FIFO_ROW_ADR[];
+				BA0   = CPU_SIG 	& CPU_BA0
+					#  BLITTER_SIG & BLITTER_BA0
+					#  FIFO_SIG 	& FIFO_BA0;
+				BA1   = CPU_SIG 	& CPU_BA1
+					#  BLITTER_SIG & BLITTER_BA1
+					#  FIFO_SIG 	& FIFO_BA1;
+				VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON;		-- AUTO REFRESH WENN SONST NICHTS
+				BLITTER_REQ = BLITTER_SIG;
+				FIFO_REQ = FIFO_SIG;	
+			END IF;
+			IF MAIN_CLK THEN
+				DDR_SM = DS_T3;
+			ELSE
+				DDR_SM = DS_LS;
+			END IF;
+		WHEN DS_T3 =>
+			IF DDR_CONFIG & CPU_REQ THEN
+				VRAS = FB_AD18;
+				VCAS = FB_AD17;
+				VWE	 = FB_AD16;
+				BA1  = FB_AD14;
+				BA0  = FB_AD13;
+				VA[] = FB_AD[12..0];
+			END IF;
+			IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
+				DDR_SM = DS_LS;
+			ELSE
+				BLITTER_REQ = BLITTER_SIG;
+				FIFO_REQ = FIFO_SIG;						
+				DDR_SM = DS_T4;
+			END IF;
+		WHEN DS_T4 =>
+			FIFO_REQ = FIFO_SIG;	
+			VCAS = VCC;															
+			VWE  = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
+			VA[9..0] = CPU_REQ     & CPU_COL_ADR[]
+					# BLITTER_REQ & BLITTER_COL_ADR[]
+					# FIFO_REQ    & FIFO_COL_ADR[];
+			VA10 = VCC;															-- AUTO PRECHARGE
+			BA0 = CPU_REQ     & CPU_BA0
+				# BLITTER_REQ & BLITTER_BA0
+				# FIFO_REQ    & FIFO_BA0;
+			BA1 = CPU_REQ     & CPU_BA1
+				# BLITTER_REQ & BLITTER_BA1
+				# FIFO_REQ    & FIFO_BA1;
+			DDR_WR         = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
+			FIFO_REQ = FIFO_SIG;						
+			IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
+				DDR_SM = DS_T5;													-- JA->
+			ELSE
+				DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
+			END IF;
+		WHEN DS_T5 =>
+			FIFO_REQ = FIFO_SIG;	
+			DDR_SM = DS_T6;
+		WHEN DS_T6 =>								 
+			IF CPU_SIG THEN															-- SOFORT UMSCHALTEN WENN CPU REQ
+				VRAS = VCC;
+				VA[] = CPU_ROW_ADR[];
+				BA1  = CPU_BA1;
+				BA0  = CPU_BA0;
+				DDR_SM = DS_T3;
+			ELSE
+				FIFO_REQ = FIFO_SIG;	
+				VCAS = VCC;															
+				VA[9..0] = FIFO_COL_ADR[];
+				VA10 = VCC;															-- AUTO PRECHARGE
+				BA0 = FIFO_BA0;
+				BA1 = FIFO_BA1;
+				FIFO_WRE 	   =  FIFO_REQ;											-- ODER FIFO LATCH IN 5 CYC 133
+				IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
+					DDR_SM = DS_T5;													-- JA->
+				ELSE
+					DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
+				END IF;
+			END IF;
+		WHEN DS_LS =>
+			IF !MAIN_CLK THEN														-- LEERSTATE UND SYNC
+				DDR_SM = DS_T1;	
+			ELSE
+				DDR_SM = DS_LS;	
+			END IF;
+	END CASE;
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+	FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
+	FIFO_REQ.CLK = DDR_SYNC_66M;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
+	FIFO_BA1 	   = VIDEO_ADR_CNT11;
+	FIFO_BA0 	   = VIDEO_ADR_CNT10;
+	FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
+	-- ZÄHLER RÜCKSETZEN WENN VSYNC ----------------
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = VSYNC # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[] =   CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]			-- SET 
+					 # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1);		-- NEXT 16 BYTS
+	VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
+	FIFO_WRE.CLK = DDRCLK0;
+---------------------------------------------------------------
+-- BLITTER BUS IST 128 BIT BREIT ------
+	BLITTER_SIG = GND & !CPU_SIG;
+	BLITTER_REQ.CLK = DDR_SYNC_66M;
+	BLITTER_RUN.CLK = DDRCLK0;
+	BLITTER_RUN = GND;
+	BLITTER_WR.CLK = DDRCLK0;
+	BLITTER_WR = GND;
+	DDRWR_D_SEL1 = BLITTER_WR;
+	BLITTER_ROW_ADR[] = H"0";
+	BLITTER_BA1 = GND;
+	BLITTER_BA0 = GND;
+	BLITTER_COL_ADR[] = H"0";
+	BLITTER_DOUT[] = H"0";
+	BLITTER_LE[] = H"0";
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..20];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[31..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; 								-- 8205/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H     & VIDEO_BASE_X_D[] 
+					  # VIDEO_CNT_H		 & VIDEO_ADR_CNT[27..20]
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & (VIDEO_BASE_L_D[],B"0000")
+					  # VIDEO_BASE_M  &  VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  &  VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & (VIDEO_ADR_CNT[3..0],B"0000")
+					  # VIDEO_CNT_M	  &  VIDEO_ADR_CNT[11..4]
+					  # VIDEO_CNT_H	  &  VIDEO_ADR_CNT[19..12]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+						
+	VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[];
+END;
+
diff --git a/FPGA_by_Fredi/Video/UNUSED b/FPGA_by_Fredi/Video/UNUSED
new file mode 100644
index 0000000..12f424b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/UNUSED
@@ -0,0 +1,267 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=6;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	000  :   0F;
+	001  :   0E;
+	002  :   0D;
+	003  :   0C;
+	004  :   0B;
+	005  :   0A;
+	006  :   09;
+	007  :   08;
+	008  :   07;
+	009  :   06;
+	00a  :   05;
+	00b  :   04;
+	00c  :   03;
+	00d  :   02;
+	00e  :   01;
+	00f  :   00;
+	010  :   0F;
+	011  :   0E;
+	012  :   0D;
+	013  :   0C;
+	014  :   0B;
+	015  :   0A;
+	016  :   09;
+	017  :   08;
+	018  :   07;
+	019  :   06;
+	01a  :   05;
+	01b  :   04;
+	01c  :   03;
+	01d  :   02;
+	01e  :   01;
+	01f  :   00;
+	020  :   0F;
+	021  :   0E;
+	022  :   0D;
+	023  :   0C;
+	024  :   0B;
+	025  :   0A;
+	026  :   09;
+	027  :   08;
+	028  :   07;
+	029  :   06;
+	02a  :   05;
+	02b  :   04;
+	02c  :   03;
+	02d  :   02;
+	02e  :   01;
+	02f  :   00;
+	030  :   0F;
+	031  :   0E;
+	032  :   0D;
+	033  :   0C;
+	034  :   0B;
+	035  :   0A;
+	036  :   09;
+	037  :   08;
+	038  :   07;
+	039  :   06;
+	03a  :   05;
+	03b  :   04;
+	03c  :   03;
+	03d  :   02;
+	03e  :   01;
+	03f  :   00;
+	040  :   0F;
+	041  :   0E;
+	042  :   0D;
+	043  :   0C;
+	044  :   0B;
+	045  :   0A;
+	046  :   09;
+	047  :   08;
+	048  :   07;
+	049  :   06;
+	04a  :   05;
+	04b  :   04;
+	04c  :   03;
+	04d  :   02;
+	04e  :   01;
+	04f  :   00;
+	050  :   0F;
+	051  :   0E;
+	052  :   0D;
+	053  :   0C;
+	054  :   0B;
+	055  :   0A;
+	056  :   09;
+	057  :   08;
+	058  :   07;
+	059  :   06;
+	05a  :   05;
+	05b  :   04;
+	05c  :   03;
+	05d  :   02;
+	05e  :   01;
+	05f  :   00;
+	060  :   0F;
+	061  :   0E;
+	062  :   0D;
+	063  :   0C;
+	064  :   0B;
+	065  :   0A;
+	066  :   09;
+	067  :   08;
+	068  :   07;
+	069  :   06;
+	06a  :   05;
+	06b  :   04;
+	06c  :   03;
+	06d  :   02;
+	06e  :   01;
+	06f  :   00;
+	070  :   0F;
+	071  :   0E;
+	072  :   0D;
+	073  :   0C;
+	074  :   0B;
+	075  :   0A;
+	076  :   09;
+	077  :   08;
+	078  :   07;
+	079  :   06;
+	07a  :   05;
+	07b  :   04;
+	07c  :   03;
+	07d  :   02;
+	07e  :   01;
+	07f  :   00;
+	080  :   0F;
+	081  :   0E;
+	082  :   0D;
+	083  :   0C;
+	084  :   0B;
+	085  :   0A;
+	086  :   09;
+	087  :   08;
+	088  :   07;
+	089  :   06;
+	08a  :   05;
+	08b  :   04;
+	08c  :   03;
+	08d  :   02;
+	08e  :   01;
+	08f  :   00;
+	090  :   0F;
+	091  :   0E;
+	092  :   0D;
+	093  :   0C;
+	094  :   0B;
+	095  :   0A;
+	096  :   09;
+	097  :   08;
+	098  :   07;
+	099  :   06;
+	09a  :   05;
+	09b  :   04;
+	09c  :   03;
+	09d  :   02;
+	09e  :   01;
+	09f  :   00;
+	0a0  :   0F;
+	0a1  :   0E;
+	0a2  :   0D;
+	0a3  :   0C;
+	0a4  :   0B;
+	0a5  :   0A;
+	0a6  :   09;
+	0a7  :   08;
+	0a8  :   07;
+	0a9  :   06;
+	0aa  :   05;
+	0ab  :   04;
+	0ac  :   03;
+	0ad  :   02;
+	0ae  :   01;
+	0af  :   00;
+	0b0  :   0F;
+	0b1  :   0E;
+	0b2  :   0D;
+	0b3  :   0C;
+	0b4  :   0B;
+	0b5  :   0A;
+	0b6  :   09;
+	0b7  :   08;
+	0b8  :   07;
+	0b9  :   06;
+	0ba  :   05;
+	0bb  :   04;
+	0bc  :   03;
+	0bd  :   02;
+	0be  :   01;
+	0bf  :   00;
+	0c0  :   0F;
+	0c1  :   0E;
+	0c2  :   0D;
+	0c3  :   0C;
+	0c4  :   0B;
+	0c5  :   0A;
+	0c6  :   09;
+	0c7  :   08;
+	0c8  :   07;
+	0c9  :   06;
+	0ca  :   05;
+	0cb  :   04;
+	0cc  :   03;
+	0cd  :   02;
+	0ce  :   01;
+	0cf  :   00;
+	0d0  :   0F;
+	0d1  :   0E;
+	0d2  :   0D;
+	0d3  :   0C;
+	0d4  :   0B;
+	0d5  :   0A;
+	0d6  :   09;
+	0d7  :   08;
+	0d8  :   07;
+	0d9  :   06;
+	0da  :   05;
+	0db  :   04;
+	0dc  :   03;
+	0dd  :   02;
+	0de  :   01;
+	0df  :   00;
+	0e0  :   0F;
+	0e1  :   0E;
+	0e2  :   0D;
+	0e3  :   0C;
+	0e4  :   0B;
+	0e5  :   0A;
+	0e6  :   09;
+	0e7  :   08;
+	0e8  :   07;
+	0e9  :   06;
+	0ea  :   05;
+	0eb  :   04;
+	0ec  :   03;
+	0ed  :   02;
+	0ee  :   01;
+	0ef  :   00;
+	0f0  :   0F;
+	0f1  :   0E;
+	0f2  :   0D;
+	0f3  :   0C;
+	0f4  :   0B;
+	0f5  :   0A;
+	0f6  :   09;
+	0f7  :   08;
+	0f8  :   07;
+	0f9  :   06;
+	0fa  :   05;
+	0fb  :   04;
+	0fc  :   03;
+	0fd  :   02;
+	0fe  :   01;
+	0ff  :   00;
+END;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
new file mode 100644
index 0000000..2c9adcc
--- /dev/null
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -0,0 +1,675 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	H_TOTAL[11..0]				:NODE;
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
new file mode 100644
index 0000000..fda03c9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
@@ -0,0 +1,675 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	H_TOTAL[11..0]				:NODE;
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==1 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_by_Fredi/Video/Video.bdf b/FPGA_by_Fredi/Video/Video.bdf
new file mode 100644
index 0000000..6210cb7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/Video.bdf
@@ -0,0 +1,10651 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.3"))
+(properties
+	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n2\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
+)
+(pin
+	(input)
+	(rect 184 1192 352 1208)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_ADR[31..0]" (rect 9 0 103 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1248 352 1264)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "MAIN_CLK" (rect 9 0 78 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1352 352 1368)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 9 0 71 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1384 352 1400)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS2" (rect 9 0 71 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1416 352 1432)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS3" (rect 9 0 71 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1448 352 1464)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_WR" (rect 9 0 66 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1480 352 1496)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_SIZE0" (rect 9 0 73 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1512 352 1528)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_SIZE1" (rect 9 0 73 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1544 352 1560)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nRSTO" (rect 9 0 56 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1608 352 1624)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_OE" (rect 9 0 63 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1736 352 1752)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_ALE" (rect 9 0 60 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1312 352 1328)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "DDRCLK[3..0]" (rect 9 0 99 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 176 1280 344 1296)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "DDR_SYNC_66M" (rect 9 0 123 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 1344 2176 1512 2192)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "CLK33M" (rect 9 0 64 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
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+	(text "CLUT_OFF[3..0]" (rect 2026 2072 2129 2087)(font "Arial" ))
+	(pt 2016 2088)
+	(pt 2112 2088)
+	(bus)
+)
+(connector
+	(text "BLITTER_ON" (rect 2026 2488 2113 2503)(font "Arial" ))
+	(pt 2096 2504)
+	(pt 2016 2504)
+)
+(connector
+	(text "VIDEO_RAM_CTR[15..0]" (rect 2026 2368 2182 2383)(font "Arial" ))
+	(pt 2144 2384)
+	(pt 2016 2384)
+	(bus)
+)
+(connector
+	(text "CCR[23..0]" (rect 2026 2176 2096 2191)(font "Arial" ))
+	(pt 2096 2192)
+	(pt 2016 2192)
+	(bus)
+)
+(connector
+	(text "CCSEL[2..0]" (rect 2026 2200 2105 2215)(font "Arial" ))
+	(pt 2016 2216)
+	(pt 2096 2216)
+	(bus)
+)
+(connector
+	(text "ACP_CLUT_WR[3..0]" (rect 2026 1944 2162 1959)(font "Arial" ))
+	(pt 2136 1960)
+	(pt 2016 1960)
+	(bus)
+)
+(connector
+	(text "FALCON_CLUT_WR[3..0]" (rect 2026 2048 2191 2063)(font "Arial" ))
+	(pt 2144 2064)
+	(pt 2016 2064)
+	(bus)
+)
+(connector
+	(text "INTER_ZEI" (rect 2026 2400 2097 2415)(font "Arial" ))
+	(pt 2016 2416)
+	(pt 2136 2416)
+)
+(connector
+	(text "DOP_FIFO_CLR" (rect 2026 2424 2133 2439)(font "Arial" ))
+	(pt 2016 2440)
+	(pt 2128 2440)
+)
+(connector
+	(text "VIDEO_MOD_TA" (rect 2026 2520 2133 2535)(font "Arial" ))
+	(pt 2088 2536)
+	(pt 2016 2536)
+)
+(connector
+	(text "BLITTER_RUN" (rect 1546 2528 1643 2543)(font "Arial" ))
+	(pt 1664 2544)
+	(pt 1536 2544)
+)
+(connector
+	(pt 1888 1120)
+	(pt 1888 1160)
+	(bus)
+)
+(connector
+	(text "VDM_SEL[3..0]" (rect 1810 1144 1905 1159)(font "Arial" ))
+	(pt 1888 1160)
+	(pt 1800 1160)
+	(bus)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1608 1232)
+)
+(connector
+	(pt 1600 1432)
+	(pt 1608 1432)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1712 1432)
+)
+(connector
+	(pt 1608 1232)
+	(pt 2072 1232)
+)
+(connector
+	(pt 2072 1248)
+	(pt 1944 1248)
+)
+(connector
+	(pt 1944 1248)
+	(pt 1944 1296)
+)
+(connector
+	(pt 1944 1296)
+	(pt 1920 1296)
+)
+(connector
+	(text "FIFO_RDE" (rect 1770 1272 1839 1287)(font "Arial" ))
+	(pt 1760 1288)
+	(pt 1856 1288)
+)
+(connector
+	(text "INTER_ZEI" (rect 1762 1288 1833 1303)(font "Arial" ))
+	(pt 1752 1304)
+	(pt 1856 1304)
+)
+(connector
+	(text "CLK33M" (rect 1586 2168 1641 2183)(font "Arial" ))
+	(pt 1512 2184)
+	(pt 1664 2184)
+)
+(connector
+	(text "CLK25M" (rect 1586 2192 1641 2207)(font "Arial" ))
+	(pt 1512 2208)
+	(pt 1664 2208)
+)
+(connector
+	(text "CLK_VIDEO" (rect 1570 2144 1649 2159)(font "Arial" ))
+	(pt 1512 2160)
+	(pt 1664 2160)
+)
+(connector
+	(text "VIDEO_MOD_TA" (rect 258 1816 365 1831)(font "Arial" ))
+	(pt 264 1832)
+	(pt 360 1832)
+)
+(connector
+	(text "COLOR8" (rect 2026 1912 2085 1927)(font "Arial" ))
+	(pt 2016 1928)
+	(pt 2120 1928)
+)
+(connector
+	(text "COLOR4" (rect 2026 1896 2085 1911)(font "Arial" ))
+	(pt 2016 1912)
+	(pt 2120 1912)
+)
+(connector
+	(text "COLOR2" (rect 2026 1880 2085 1895)(font "Arial" ))
+	(pt 2016 1896)
+	(pt 2120 1896)
+)
+(connector
+	(text "COLOR1" (rect 2026 1864 2085 1879)(font "Arial" ))
+	(pt 2016 1880)
+	(pt 2120 1880)
+)
+(connector
+	(text "FIFO_RDE" (rect 2026 1736 2095 1751)(font "Arial" ))
+	(pt 2104 1752)
+	(pt 2016 1752)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 2026 1688 2151 1703)(font "Arial" ))
+	(pt 2144 1704)
+	(pt 2016 1704)
+)
+(connector
+	(text "VR_WR" (rect 2026 1784 2076 1799)(font "Arial" ))
+	(pt 2016 1800)
+	(pt 2112 1800)
+)
+(connector
+	(text "VR_RD" (rect 2026 1800 2074 1815)(font "Arial" ))
+	(pt 2016 1816)
+	(pt 2112 1816)
+)
+(connector
+	(text "VR_D[8..0]" (rect 1570 2120 1638 2135)(font "Arial" ))
+	(pt 1512 2136)
+	(pt 1664 2136)
+	(bus)
+)
+(connector
+	(text "VR_BUSY" (rect 1578 2104 1642 2119)(font "Arial" ))
+	(pt 1512 2120)
+	(pt 1664 2120)
+)
+(connector
+	(text "CLR_FIFO" (rect 202 2216 270 2231)(font "Arial" ))
+	(pt 296 2232)
+	(pt 192 2232)
+)
+(connector
+	(text "CLR_FIFO" (rect 2026 1752 2094 1767)(font "Arial" ))
+	(pt 2016 1768)
+	(pt 2112 1768)
+)
+(connector
+	(text "CLR_FIFO" (rect 1634 1456 1702 1471)(font "Arial" ))
+	(pt 1712 1472)
+	(pt 1632 1472)
+)
+(junction (pt 2984 1688))
+(junction (pt 792 1192))
+(junction (pt 792 1312))
+(junction (pt 792 1432))
+(junction (pt 792 1792))
+(junction (pt 792 1928))
+(junction (pt 792 1552))
+(junction (pt 792 1648))
+(junction (pt 2512 1728))
+(junction (pt 2512 1888))
+(junction (pt 2512 2048))
+(junction (pt 2512 1408))
+(junction (pt 2512 1568))
+(junction (pt 2512 1552))
+(junction (pt 2512 2208))
+(junction (pt 1344 2880))
+(junction (pt 1344 2824))
+(junction (pt 1344 2928))
+(junction (pt 1328 2904))
+(junction (pt 1328 2952))
+(junction (pt 4240 2800))
+(junction (pt 3232 3024))
+(junction (pt 1968 1424))
+(junction (pt 1608 1432))
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.bsf b/FPGA_by_Fredi/Video/altddio_bidir0.bsf
new file mode 100644
index 0000000..bcf7f28
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.bsf
@@ -0,0 +1,99 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 240 136)
+	(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 120 25 132)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 88 72)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 88 88)(line_width 1))
+	)
+	(port
+		(pt 240 24)
+		(output)
+		(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
+		(line (pt 240 24)(pt 144 24)(line_width 3))
+	)
+	(port
+		(pt 240 40)
+		(output)
+		(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
+		(line (pt 240 40)(pt 144 40)(line_width 3))
+	)
+	(port
+		(pt 240 72)
+		(output)
+		(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
+		(line (pt 240 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 240 56)
+		(bidir)
+		(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
+		(line (pt 240 56)(pt 144 56)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
+		(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 90 129 102)(font "Arial" ))
+		(text "low" (rect 92 100 105 112)(font "Arial" ))
+		(line (pt 88 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 112)(line_width 1))
+		(line (pt 144 112)(pt 88 112)(line_width 1))
+		(line (pt 88 112)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.cmp b/FPGA_by_Fredi/Video/altddio_bidir0.cmp
new file mode 100644
index 0000000..3fb55ed
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.cmp
@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_bidir0
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		inclock		: IN STD_LOGIC ;
+		oe		: IN STD_LOGIC  := '1';
+		outclock		: IN STD_LOGIC ;
+		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.inc b/FPGA_by_Fredi/Video/altddio_bidir0.inc
new file mode 100644
index 0000000..5969513
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_bidir0 
+(
+	datain_h[31..0],
+	datain_l[31..0],
+	inclock,
+	oe,
+	outclock
+)
+
+RETURNS (
+	combout[31..0],
+	dataout_h[31..0],
+	dataout_l[31..0],
+	padio[31..0]
+);
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.ppf b/FPGA_by_Fredi/Video/altddio_bidir0.ppf
new file mode 100644
index 0000000..5601bba
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.ppf
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
+<global>
+<pin name="datain_h[31..0]" direction="input" scope="external"  />
+<pin name="datain_l[31..0]" direction="input" scope="external"  />
+<pin name="inclock" direction="input" scope="external" source="clock"  />
+<pin name="oe" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="combout[31..0]" direction="output" scope="external"  />
+<pin name="dataout_h[31..0]" direction="output" scope="external"  />
+<pin name="dataout_l[31..0]" direction="output" scope="external"  />
+<pin name="padio[31..0]" direction="bidir" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.qip b/FPGA_by_Fredi/Video/altddio_bidir0.qip
new file mode 100644
index 0000000..3339057
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]
diff --git a/FPGA_by_Fredi/Video/altddio_bidir0.vhd b/FPGA_by_Fredi/Video/altddio_bidir0.vhd
new file mode 100644
index 0000000..a0ae0e0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_bidir0.vhd
@@ -0,0 +1,172 @@
+-- megafunction wizard: %ALTDDIO_BIDIR%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_bidir 
+
+-- ============================================================
+-- File Name: altddio_bidir0.vhd
+-- Megafunction Name(s):
+-- 			altddio_bidir
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_bidir0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		inclock		: IN STD_LOGIC ;
+		oe		: IN STD_LOGIC  := '1';
+		outclock		: IN STD_LOGIC ;
+		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END altddio_bidir0;
+
+
+ARCHITECTURE SYN OF altddio_bidir0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altddio_bidir
+	GENERIC (
+		extend_oe_disable		: STRING;
+		implement_input_in_lcell		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			outclock	: IN STD_LOGIC ;
+			padio	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			inclock	: IN STD_LOGIC ;
+			dataout_h	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			oe	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			combout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			dataout_l	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout_h    <= sub_wire0(31 DOWNTO 0);
+	combout    <= sub_wire1(31 DOWNTO 0);
+	dataout_l    <= sub_wire2(31 DOWNTO 0);
+
+	altddio_bidir_component : altddio_bidir
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		implement_input_in_lcell => "ON",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_bidir",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 32
+	)
+	PORT MAP (
+		outclock => outclock,
+		inclock => inclock,
+		oe => oe,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout_h => sub_wire0,
+		combout => sub_wire1,
+		dataout_l => sub_wire2,
+		padio => padio
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "1"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
+-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
+-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
+-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
+-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
+-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
+-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
+-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
+-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
+-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
+-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altddio_out0.bsf b/FPGA_by_Fredi/Video/altddio_out0.bsf
new file mode 100644
index 0000000..6554c2f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "high" (rect 92 84 109 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altddio_out0.cmp b/FPGA_by_Fredi/Video/altddio_out0.cmp
new file mode 100644
index 0000000..df70a5a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_out0
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altddio_out0.inc b/FPGA_by_Fredi/Video/altddio_out0.inc
new file mode 100644
index 0000000..f534925
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out0 
+(
+	datain_h[3..0],
+	datain_l[3..0],
+	outclock
+)
+
+RETURNS (
+	dataout[3..0]
+);
diff --git a/FPGA_by_Fredi/Video/altddio_out0.ppf b/FPGA_by_Fredi/Video/altddio_out0.ppf
new file mode 100644
index 0000000..3f3cfb5
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h[3..0]" direction="input" scope="external"  />
+<pin name="datain_l[3..0]" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout[3..0]" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/Video/altddio_out0.qip b/FPGA_by_Fredi/Video/altddio_out0.qip
new file mode 100644
index 0000000..8193856
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
diff --git a/FPGA_by_Fredi/Video/altddio_out0.vhd b/FPGA_by_Fredi/Video/altddio_out0.vhd
new file mode 100644
index 0000000..f129798
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out0.vhd
@@ -0,0 +1,136 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out0.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END altddio_out0;
+
+
+ARCHITECTURE SYN OF altddio_out0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(3 DOWNTO 0);
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "ON",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "ON",
+		width => 4
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
+-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
+-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altddio_out1.bsf b/FPGA_by_Fredi/Video/altddio_out1.bsf
new file mode 100644
index 0000000..8289852
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altddio_out1.cmp b/FPGA_by_Fredi/Video/altddio_out1.cmp
new file mode 100644
index 0000000..cdb7766
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_out1
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altddio_out1.inc b/FPGA_by_Fredi/Video/altddio_out1.inc
new file mode 100644
index 0000000..4d50b26
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out1 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_by_Fredi/Video/altddio_out1.ppf b/FPGA_by_Fredi/Video/altddio_out1.ppf
new file mode 100644
index 0000000..9772cd3
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/Video/altddio_out1.qip b/FPGA_by_Fredi/Video/altddio_out1.qip
new file mode 100644
index 0000000..606e0b7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
diff --git a/FPGA_by_Fredi/Video/altddio_out1.vhd b/FPGA_by_Fredi/Video/altddio_out1.vhd
new file mode 100644
index 0000000..cb76474
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out1.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out1.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out1 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out1;
+
+
+ARCHITECTURE SYN OF altddio_out1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altddio_out2.bsf b/FPGA_by_Fredi/Video/altddio_out2.bsf
new file mode 100644
index 0000000..ff039ee
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altddio_out2.cmp b/FPGA_by_Fredi/Video/altddio_out2.cmp
new file mode 100644
index 0000000..ad8aa55
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_out2
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altddio_out2.inc b/FPGA_by_Fredi/Video/altddio_out2.inc
new file mode 100644
index 0000000..2257c30
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out2 
+(
+	datain_h[23..0],
+	datain_l[23..0],
+	outclock
+)
+
+RETURNS (
+	dataout[23..0]
+);
diff --git a/FPGA_by_Fredi/Video/altddio_out2.ppf b/FPGA_by_Fredi/Video/altddio_out2.ppf
new file mode 100644
index 0000000..93df472
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h[23..0]" direction="input" scope="external"  />
+<pin name="datain_l[23..0]" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout[23..0]" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/Video/altddio_out2.qip b/FPGA_by_Fredi/Video/altddio_out2.qip
new file mode 100644
index 0000000..d72d5ce
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]
diff --git a/FPGA_by_Fredi/Video/altddio_out2.vhd b/FPGA_by_Fredi/Video/altddio_out2.vhd
new file mode 100644
index 0000000..30a8586
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altddio_out2.vhd
@@ -0,0 +1,136 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out2.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out2 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END altddio_out2;
+
+
+ARCHITECTURE SYN OF altddio_out2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(23 DOWNTO 0);
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 24
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
+-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
+-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
+-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altdpram0.bsf b/FPGA_by_Fredi/Video/altdpram0.bsf
new file mode 100644
index 0000000..e0d3ce3
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
+		(line (pt 128 144)(pt 128 24)(line_width 1))
+		(line (pt 112 27)(pt 120 27)(line_width 1))
+		(line (pt 120 27)(pt 120 39)(line_width 1))
+		(line (pt 120 39)(pt 112 39)(line_width 1))
+		(line (pt 112 39)(pt 112 27)(line_width 1))
+		(line (pt 112 34)(pt 114 36)(line_width 1))
+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 92 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
+		(line (pt 120 43)(pt 120 55)(line_width 1))
+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
+		(line (pt 112 50)(pt 114 52)(line_width 1))
+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 92 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 92 68)(pt 112 68)(line_width 1))
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+		(line (pt 176 36)(pt 184 36)(line_width 1))
+		(line (pt 168 32)(pt 184 32)(line_width 3))
+		(line (pt 184 91)(pt 192 91)(line_width 1))
+		(line (pt 192 91)(pt 192 103)(line_width 1))
+		(line (pt 192 103)(pt 184 103)(line_width 1))
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+		(line (pt 186 100)(pt 184 102)(line_width 1))
+		(line (pt 181 100)(pt 184 100)(line_width 1))
+		(line (pt 168 96)(pt 184 96)(line_width 3))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altdpram0.cmp b/FPGA_by_Fredi/Video/altdpram0.cmp
new file mode 100644
index 0000000..566f5cd
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0.cmp
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altdpram0
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altdpram0.inc b/FPGA_by_Fredi/Video/altdpram0.inc
new file mode 100644
index 0000000..828067d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram0 
+(
+	address_a[3..0],
+	address_b[3..0],
+	clock_a,
+	clock_b,
+	data_a[2..0],
+	data_b[2..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[2..0],
+	q_b[2..0]
+);
diff --git a/FPGA_by_Fredi/Video/altdpram0.qip b/FPGA_by_Fredi/Video/altdpram0.qip
new file mode 100644
index 0000000..e4d02ab
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"]
diff --git a/FPGA_by_Fredi/Video/altdpram0.vhd b/FPGA_by_Fredi/Video/altdpram0.vhd
new file mode 100644
index 0000000..c883f02
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram0.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram0 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+END altdpram0;
+
+
+ARCHITECTURE SYN OF altdpram0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(2 DOWNTO 0);
+	q_b    <= sub_wire1(2 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 16,
+		numwords_b => 16,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 4,
+		widthad_b => 4,
+		width_a => 3,
+		width_b => 3,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
+-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0]
+-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0]
+-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0]
+-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
+-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
+-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
+-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
+-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altdpram0_wave0.jpg b/FPGA_by_Fredi/Video/altdpram0_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/altdpram0_waveforms.html b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
new file mode 100644
index 0000000..e0236fd
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram0.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/altdpram1.bsf b/FPGA_by_Fredi/Video/altdpram1.bsf
new file mode 100644
index 0000000..d75db28
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
+		(line (pt 128 144)(pt 128 24)(line_width 1))
+		(line (pt 112 27)(pt 120 27)(line_width 1))
+		(line (pt 120 27)(pt 120 39)(line_width 1))
+		(line (pt 120 39)(pt 112 39)(line_width 1))
+		(line (pt 112 39)(pt 112 27)(line_width 1))
+		(line (pt 112 34)(pt 114 36)(line_width 1))
+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 92 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
+		(line (pt 120 43)(pt 120 55)(line_width 1))
+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
+		(line (pt 112 50)(pt 114 52)(line_width 1))
+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 92 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 92 68)(pt 112 68)(line_width 1))
+		(line (pt 120 64)(pt 128 64)(line_width 1))
+		(line (pt 112 91)(pt 120 91)(line_width 1))
+		(line (pt 120 91)(pt 120 103)(line_width 1))
+		(line (pt 120 103)(pt 112 103)(line_width 1))
+		(line (pt 112 103)(pt 112 91)(line_width 1))
+		(line (pt 112 98)(pt 114 100)(line_width 1))
+		(line (pt 114 100)(pt 112 102)(line_width 1))
+		(line (pt 104 100)(pt 112 100)(line_width 1))
+		(line (pt 120 96)(pt 128 96)(line_width 3))
+		(line (pt 112 107)(pt 120 107)(line_width 1))
+		(line (pt 120 107)(pt 120 119)(line_width 1))
+		(line (pt 120 119)(pt 112 119)(line_width 1))
+		(line (pt 112 119)(pt 112 107)(line_width 1))
+		(line (pt 112 114)(pt 114 116)(line_width 1))
+		(line (pt 114 116)(pt 112 118)(line_width 1))
+		(line (pt 104 116)(pt 112 116)(line_width 1))
+		(line (pt 120 112)(pt 128 112)(line_width 3))
+		(line (pt 112 123)(pt 120 123)(line_width 1))
+		(line (pt 120 123)(pt 120 135)(line_width 1))
+		(line (pt 120 135)(pt 112 135)(line_width 1))
+		(line (pt 112 135)(pt 112 123)(line_width 1))
+		(line (pt 112 130)(pt 114 132)(line_width 1))
+		(line (pt 114 132)(pt 112 134)(line_width 1))
+		(line (pt 104 132)(pt 112 132)(line_width 1))
+		(line (pt 120 128)(pt 128 128)(line_width 1))
+		(line (pt 92 36)(pt 92 161)(line_width 1))
+		(line (pt 176 36)(pt 176 161)(line_width 1))
+		(line (pt 104 100)(pt 104 177)(line_width 1))
+		(line (pt 181 100)(pt 181 177)(line_width 1))
+		(line (pt 184 27)(pt 192 27)(line_width 1))
+		(line (pt 192 27)(pt 192 39)(line_width 1))
+		(line (pt 192 39)(pt 184 39)(line_width 1))
+		(line (pt 184 39)(pt 184 27)(line_width 1))
+		(line (pt 184 34)(pt 186 36)(line_width 1))
+		(line (pt 186 36)(pt 184 38)(line_width 1))
+		(line (pt 176 36)(pt 184 36)(line_width 1))
+		(line (pt 168 32)(pt 184 32)(line_width 3))
+		(line (pt 184 91)(pt 192 91)(line_width 1))
+		(line (pt 192 91)(pt 192 103)(line_width 1))
+		(line (pt 192 103)(pt 184 103)(line_width 1))
+		(line (pt 184 103)(pt 184 91)(line_width 1))
+		(line (pt 184 98)(pt 186 100)(line_width 1))
+		(line (pt 186 100)(pt 184 102)(line_width 1))
+		(line (pt 181 100)(pt 184 100)(line_width 1))
+		(line (pt 168 96)(pt 184 96)(line_width 3))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/altdpram1.cmp b/FPGA_by_Fredi/Video/altdpram1.cmp
new file mode 100644
index 0000000..a482250
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1.cmp
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altdpram1
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altdpram1.inc b/FPGA_by_Fredi/Video/altdpram1.inc
new file mode 100644
index 0000000..4a7924e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram1 
+(
+	address_a[7..0],
+	address_b[7..0],
+	clock_a,
+	clock_b,
+	data_a[5..0],
+	data_b[5..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[5..0],
+	q_b[5..0]
+);
diff --git a/FPGA_by_Fredi/Video/altdpram1.qip b/FPGA_by_Fredi/Video/altdpram1.qip
new file mode 100644
index 0000000..cdd178f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"]
diff --git a/FPGA_by_Fredi/Video/altdpram1.vhd b/FPGA_by_Fredi/Video/altdpram1.vhd
new file mode 100644
index 0000000..b2e0435
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram1.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram1 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+END altdpram1;
+
+
+ARCHITECTURE SYN OF altdpram1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(5 DOWNTO 0);
+	q_b    <= sub_wire1(5 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		numwords_b => 256,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 8,
+		widthad_b => 8,
+		width_a => 6,
+		width_b => 6,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0]
+-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0]
+-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0]
+-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
+-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
+-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altdpram1_wave0.jpg b/FPGA_by_Fredi/Video/altdpram1_wave0.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..3ab5c5fe19f01eb340d6df91c2896dfc076fd396
GIT binary patch
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diff --git a/FPGA_by_Fredi/Video/altdpram1_waveforms.html b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
new file mode 100644
index 0000000..85b4369
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram1.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/altdpram2.bsf b/FPGA_by_Fredi/Video/altdpram2.bsf
new file mode 100644
index 0000000..75c64aa
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
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+)
diff --git a/FPGA_by_Fredi/Video/altdpram2.cmp b/FPGA_by_Fredi/Video/altdpram2.cmp
new file mode 100644
index 0000000..4895f04
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2.cmp
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altdpram2
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/altdpram2.inc b/FPGA_by_Fredi/Video/altdpram2.inc
new file mode 100644
index 0000000..1909de8
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram2 
+(
+	address_a[7..0],
+	address_b[7..0],
+	clock_a,
+	clock_b,
+	data_a[7..0],
+	data_b[7..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[7..0],
+	q_b[7..0]
+);
diff --git a/FPGA_by_Fredi/Video/altdpram2.qip b/FPGA_by_Fredi/Video/altdpram2.qip
new file mode 100644
index 0000000..f84925c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"]
diff --git a/FPGA_by_Fredi/Video/altdpram2.vhd b/FPGA_by_Fredi/Video/altdpram2.vhd
new file mode 100644
index 0000000..238e6f3
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram2.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram2 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END altdpram2;
+
+
+ARCHITECTURE SYN OF altdpram2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		numwords_b => 256,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 8,
+		widthad_b => 8,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/altdpram2_wave0.jpg b/FPGA_by_Fredi/Video/altdpram2_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/altdpram2_waveforms.html b/FPGA_by_Fredi/Video/altdpram2_waveforms.html
new file mode 100644
index 0000000..a856bf6
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram2_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram2.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_bustri0.bsf b/FPGA_by_Fredi/Video/lpm_bustri0.bsf
new file mode 100644
index 0000000..f65e217
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri0.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "32" (rect 61 25 71 37)(font "Arial" ))
+		(text "32" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri0.cmp b/FPGA_by_Fredi/Video/lpm_bustri0.cmp
new file mode 100644
index 0000000..9426443
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri0
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri0.inc b/FPGA_by_Fredi/Video/lpm_bustri0.inc
new file mode 100644
index 0000000..1b15c22
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri0.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri0 
+(
+	data[31..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[31..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_bustri0.qip b/FPGA_by_Fredi/Video/lpm_bustri0.qip
new file mode 100644
index 0000000..c70041d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri0.vhd b/FPGA_by_Fredi/Video/lpm_bustri0.vhd
new file mode 100644
index 0000000..494b3c2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri0.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri0.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri0 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_bustri0;
+
+
+ARCHITECTURE SYN OF lpm_bustri0 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
+-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri1.bsf b/FPGA_by_Fredi/Video/lpm_bustri1.bsf
new file mode 100644
index 0000000..058fffb
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "3" (rect 63 25 68 37)(font "Arial" ))
+		(text "3" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri1.cmp b/FPGA_by_Fredi/Video/lpm_bustri1.cmp
new file mode 100644
index 0000000..48a33f0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri1
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri1.qip b/FPGA_by_Fredi/Video/lpm_bustri1.qip
new file mode 100644
index 0000000..fd76bb2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri1.vhd b/FPGA_by_Fredi/Video/lpm_bustri1.vhd
new file mode 100644
index 0000000..47db597
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri1.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri1.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri1 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+END lpm_bustri1;
+
+
+ARCHITECTURE SYN OF lpm_bustri1 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 3
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
+-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0]
+-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0
+-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri2.bsf b/FPGA_by_Fredi/Video/lpm_bustri2.bsf
new file mode 100644
index 0000000..36a4813
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "18" (rect 61 25 71 37)(font "Arial" ))
+		(text "18" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri2.cmp b/FPGA_by_Fredi/Video/lpm_bustri2.cmp
new file mode 100644
index 0000000..e45fbdd
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri2.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri2
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri2.qip b/FPGA_by_Fredi/Video/lpm_bustri2.qip
new file mode 100644
index 0000000..676e430
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri2.vhd b/FPGA_by_Fredi/Video/lpm_bustri2.vhd
new file mode 100644
index 0000000..0966743
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri2.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri2.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri2 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+END lpm_bustri2;
+
+
+ARCHITECTURE SYN OF lpm_bustri2 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 18
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "18"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0]
+-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0
+-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri3.bsf b/FPGA_by_Fredi/Video/lpm_bustri3.bsf
new file mode 100644
index 0000000..2dde401
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "6" (rect 63 25 68 37)(font "Arial" ))
+		(text "6" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri3.cmp b/FPGA_by_Fredi/Video/lpm_bustri3.cmp
new file mode 100644
index 0000000..f3836e3
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri3.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri3
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri3.qip b/FPGA_by_Fredi/Video/lpm_bustri3.qip
new file mode 100644
index 0000000..8c41556
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri3.vhd b/FPGA_by_Fredi/Video/lpm_bustri3.vhd
new file mode 100644
index 0000000..2344712
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri3.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri3.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri3 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+END lpm_bustri3;
+
+
+ARCHITECTURE SYN OF lpm_bustri3 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 6
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "6"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
+-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0]
+-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0
+-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri4.bsf b/FPGA_by_Fredi/Video/lpm_bustri4.bsf
new file mode 100644
index 0000000..cd9edcc
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "5" (rect 63 25 68 37)(font "Arial" ))
+		(text "5" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri4.cmp b/FPGA_by_Fredi/Video/lpm_bustri4.cmp
new file mode 100644
index 0000000..37bee59
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri4.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri4
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri4.qip b/FPGA_by_Fredi/Video/lpm_bustri4.qip
new file mode 100644
index 0000000..39eb21d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri4.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri4.vhd b/FPGA_by_Fredi/Video/lpm_bustri4.vhd
new file mode 100644
index 0000000..5bb209b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri4.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri4.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri4 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_bustri4;
+
+
+ARCHITECTURE SYN OF lpm_bustri4 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 5
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0]
+-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0
+-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri5.bsf b/FPGA_by_Fredi/Video/lpm_bustri5.bsf
new file mode 100644
index 0000000..1d9b178
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "8" (rect 63 25 68 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri5.cmp b/FPGA_by_Fredi/Video/lpm_bustri5.cmp
new file mode 100644
index 0000000..5c719c7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri5.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri5
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri5.inc b/FPGA_by_Fredi/Video/lpm_bustri5.inc
new file mode 100644
index 0000000..fdb4877
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri5 
+(
+	data[7..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[7..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_bustri5.qip b/FPGA_by_Fredi/Video/lpm_bustri5.qip
new file mode 100644
index 0000000..daa3efa
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri5.vhd b/FPGA_by_Fredi/Video/lpm_bustri5.vhd
new file mode 100644
index 0000000..e1973b4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri5.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri5.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri5 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_bustri5;
+
+
+ARCHITECTURE SYN OF lpm_bustri5 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 8
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
+-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri6.bsf b/FPGA_by_Fredi/Video/lpm_bustri6.bsf
new file mode 100644
index 0000000..4c9344e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri6.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "24" (rect 61 25 71 37)(font "Arial" ))
+		(text "24" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri6.cmp b/FPGA_by_Fredi/Video/lpm_bustri6.cmp
new file mode 100644
index 0000000..67529c9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri6.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri6
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri6.qip b/FPGA_by_Fredi/Video/lpm_bustri6.qip
new file mode 100644
index 0000000..6b9f1df
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri6.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri6.vhd b/FPGA_by_Fredi/Video/lpm_bustri6.vhd
new file mode 100644
index 0000000..45f409f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri6.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri6.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri6 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_bustri6;
+
+
+ARCHITECTURE SYN OF lpm_bustri6 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 24
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0]
+-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0
+-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_bustri7.bsf b/FPGA_by_Fredi/Video/lpm_bustri7.bsf
new file mode 100644
index 0000000..399a828
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri7.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "4" (rect 63 25 68 37)(font "Arial" ))
+		(text "4" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_bustri7.cmp b/FPGA_by_Fredi/Video/lpm_bustri7.cmp
new file mode 100644
index 0000000..2d5983d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri7.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri7
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_bustri7.qip b/FPGA_by_Fredi/Video/lpm_bustri7.qip
new file mode 100644
index 0000000..f32324c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri7.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_bustri7.vhd b/FPGA_by_Fredi/Video/lpm_bustri7.vhd
new file mode 100644
index 0000000..4bf883d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_bustri7.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri7.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri7 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END lpm_bustri7;
+
+
+ARCHITECTURE SYN OF lpm_bustri7 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 4
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0]
+-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0
+-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_compare1.bsf b/FPGA_by_Fredi/Video/lpm_compare1.bsf
new file mode 100644
index 0000000..9ec3796
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1.bsf
@@ -0,0 +1,54 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 128 96)
+	(text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 128 56)
+		(output)
+		(text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8)))
+		(line (pt 128 56)(pt 112 56)(line_width 1))
+	)
+	(drawing
+		(text "unsigned compare" (rect 36 17 112 29)(font "Arial" ))
+		(line (pt 16 16)(pt 112 16)(line_width 1))
+		(line (pt 112 16)(pt 112 80)(line_width 1))
+		(line (pt 112 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_compare1.cmp b/FPGA_by_Fredi/Video/lpm_compare1.cmp
new file mode 100644
index 0000000..9bab50e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_compare1
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		AgB		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_compare1.inc b/FPGA_by_Fredi/Video/lpm_compare1.inc
new file mode 100644
index 0000000..bde0ab9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_compare1 
+(
+	dataa[10..0],
+	datab[10..0]
+)
+
+RETURNS (
+	AgB
+);
diff --git a/FPGA_by_Fredi/Video/lpm_compare1.qip b/FPGA_by_Fredi/Video/lpm_compare1.qip
new file mode 100644
index 0000000..ea93f3c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_compare1.vhd b/FPGA_by_Fredi/Video/lpm_compare1.vhd
new file mode 100644
index 0000000..a85e3b2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_COMPARE%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_compare 
+
+-- ============================================================
+-- File Name: lpm_compare1.vhd
+-- Megafunction Name(s):
+-- 			lpm_compare
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_compare1 IS
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		AgB		: OUT STD_LOGIC 
+	);
+END lpm_compare1;
+
+
+ARCHITECTURE SYN OF lpm_compare1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_compare
+	GENERIC (
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			AgB	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	AgB    <= sub_wire0;
+
+	lpm_compare_component : lpm_compare
+	GENERIC MAP (
+		lpm_representation => "UNSIGNED",
+		lpm_type => "LPM_COMPARE",
+		lpm_width => 11
+	)
+	PORT MAP (
+		dataa => dataa,
+		datab => datab,
+		AgB => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
+-- Retrieval info: PRIVATE: AleB NUMERIC "0"
+-- Retrieval info: PRIVATE: AltB NUMERIC "0"
+-- Retrieval info: PRIVATE: AneB NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "11"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
+-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
+-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0]
+-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0]
+-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
+-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
+-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg b/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
new file mode 100644
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literal 0
HcmV?d00001

diff --git a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
new file mode 100644
index 0000000..e8242d9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for lpm_compare1.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
+<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_constant0.bsf b/FPGA_by_Fredi/Video/lpm_constant0.bsf
new file mode 100644
index 0000000..684bbae
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant0.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_constant0.cmp b/FPGA_by_Fredi/Video/lpm_constant0.cmp
new file mode 100644
index 0000000..7143429
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant0.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant0
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_constant0.qip b/FPGA_by_Fredi/Video/lpm_constant0.qip
new file mode 100644
index 0000000..bb19c49
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_constant0.vhd b/FPGA_by_Fredi/Video/lpm_constant0.vhd
new file mode 100644
index 0000000..63631cc
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant0.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant0.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant0 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_constant0;
+
+
+ARCHITECTURE SYN OF lpm_constant0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 5
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
+-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_constant1.bsf b/FPGA_by_Fredi/Video/lpm_constant1.bsf
new file mode 100644
index 0000000..01fdb2b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant1.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_constant1.cmp b/FPGA_by_Fredi/Video/lpm_constant1.cmp
new file mode 100644
index 0000000..a7e275c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant1.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant1
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_constant1.inc b/FPGA_by_Fredi/Video/lpm_constant1.inc
new file mode 100644
index 0000000..9b556e7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant1.inc
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_constant1 
+(
+
+)
+
+RETURNS (
+	result[1..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_constant1.qip b/FPGA_by_Fredi/Video/lpm_constant1.qip
new file mode 100644
index 0000000..2bc12e7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_constant1.vhd b/FPGA_by_Fredi/Video/lpm_constant1.vhd
new file mode 100644
index 0000000..afa67ba
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant1.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant1.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant1 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+END lpm_constant1;
+
+
+ARCHITECTURE SYN OF lpm_constant1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(1 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 2
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
+-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_constant2.bsf b/FPGA_by_Fredi/Video/lpm_constant2.bsf
new file mode 100644
index 0000000..a4b7697
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant2.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "8" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_constant2.cmp b/FPGA_by_Fredi/Video/lpm_constant2.cmp
new file mode 100644
index 0000000..63cc406
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant2.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant2
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_constant2.qip b/FPGA_by_Fredi/Video/lpm_constant2.qip
new file mode 100644
index 0000000..ad38485
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_constant2.vhd b/FPGA_by_Fredi/Video/lpm_constant2.vhd
new file mode 100644
index 0000000..f25e68f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant2.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant2.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant2 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_constant2;
+
+
+ARCHITECTURE SYN OF lpm_constant2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(7 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 8
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_constant3.bsf b/FPGA_by_Fredi/Video/lpm_constant3.bsf
new file mode 100644
index 0000000..7616869
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant3.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "7" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_constant3.cmp b/FPGA_by_Fredi/Video/lpm_constant3.cmp
new file mode 100644
index 0000000..0e2f877
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant3.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant3
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_constant3.qip b/FPGA_by_Fredi/Video/lpm_constant3.qip
new file mode 100644
index 0000000..615a781
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_constant3.vhd b/FPGA_by_Fredi/Video/lpm_constant3.vhd
new file mode 100644
index 0000000..5d47d8e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant3.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant3.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant3 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+END lpm_constant3;
+
+
+ARCHITECTURE SYN OF lpm_constant3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(6 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 7
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_constant4.bsf b/FPGA_by_Fredi/Video/lpm_constant4.bsf
new file mode 100644
index 0000000..181c667
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant4.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "2040" (rect 60 18 80 30)(font "Arial" ))
+		(text "11" (rect 85 25 95 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 80 28)(pt 88 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_constant4.cmp b/FPGA_by_Fredi/Video/lpm_constant4.cmp
new file mode 100644
index 0000000..fd7f4cd
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant4.cmp
@@ -0,0 +1,21 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_constant4
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_constant4.inc b/FPGA_by_Fredi/Video/lpm_constant4.inc
new file mode 100644
index 0000000..a913739
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant4.inc
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_constant4 
+(
+
+)
+
+RETURNS (
+	result[10..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_constant4.qip b/FPGA_by_Fredi/Video/lpm_constant4.qip
new file mode 100644
index 0000000..44fa63f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_constant4.vhd b/FPGA_by_Fredi/Video/lpm_constant4.vhd
new file mode 100644
index 0000000..e0fc73d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_constant4.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant4.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant4 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+	);
+END lpm_constant4;
+
+
+ARCHITECTURE SYN OF lpm_constant4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (10 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(10 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 2040,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 11
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "2040"
+-- Retrieval info: PRIVATE: nBit NUMERIC "11"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2040"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
+-- Retrieval info: USED_PORT: result 0 0 11 0 OUTPUT NODEFVAL result[10..0]
+-- Retrieval info: CONNECT: result 0 0 11 0 @result 0 0 11 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff0.bsf b/FPGA_by_Fredi/Video/lpm_ff0.bsf
new file mode 100644
index 0000000..6675606
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff0.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff0.cmp b/FPGA_by_Fredi/Video/lpm_ff0.cmp
new file mode 100644
index 0000000..0d8e769
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff0.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff0
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff0.qip b/FPGA_by_Fredi/Video/lpm_ff0.qip
new file mode 100644
index 0000000..d33c680
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff0.vhd b/FPGA_by_Fredi/Video/lpm_ff0.vhd
new file mode 100644
index 0000000..4c17d8f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff0.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff0.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_ff0;
+
+
+ARCHITECTURE SYN OF lpm_ff0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enable	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enable => enable,
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff1.bsf b/FPGA_by_Fredi/Video/lpm_ff1.bsf
new file mode 100644
index 0000000..947a023
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff1.cmp b/FPGA_by_Fredi/Video/lpm_ff1.cmp
new file mode 100644
index 0000000..4b25f14
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff1.qip b/FPGA_by_Fredi/Video/lpm_ff1.qip
new file mode 100644
index 0000000..94b30af
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff1.vhd b/FPGA_by_Fredi/Video/lpm_ff1.vhd
new file mode 100644
index 0000000..da02a15
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff1.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff1.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_ff1;
+
+
+ARCHITECTURE SYN OF lpm_ff1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 32
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff2.bsf b/FPGA_by_Fredi/Video/lpm_ff2.bsf
new file mode 100644
index 0000000..b52c75b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff2.cmp b/FPGA_by_Fredi/Video/lpm_ff2.cmp
new file mode 100644
index 0000000..6b5b979
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff2.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff2
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff2.qip b/FPGA_by_Fredi/Video/lpm_ff2.qip
new file mode 100644
index 0000000..9c46273
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff2.vhd b/FPGA_by_Fredi/Video/lpm_ff2.vhd
new file mode 100644
index 0000000..27b4c3a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff2.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff2.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_ff2;
+
+
+ARCHITECTURE SYN OF lpm_ff2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 128
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff3.bsf b/FPGA_by_Fredi/Video/lpm_ff3.bsf
new file mode 100644
index 0000000..51248ea
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff3.cmp b/FPGA_by_Fredi/Video/lpm_ff3.cmp
new file mode 100644
index 0000000..b3b5513
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff3.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff3
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff3.qip b/FPGA_by_Fredi/Video/lpm_ff3.qip
new file mode 100644
index 0000000..98d1312
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff3.vhd b/FPGA_by_Fredi/Video/lpm_ff3.vhd
new file mode 100644
index 0000000..a86b4ee
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff3.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff3.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff3 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_ff3;
+
+
+ARCHITECTURE SYN OF lpm_ff3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(23 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 24
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
+-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL q[23..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
+-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff4.bsf b/FPGA_by_Fredi/Video/lpm_ff4.bsf
new file mode 100644
index 0000000..be432cb
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff4.cmp b/FPGA_by_Fredi/Video/lpm_ff4.cmp
new file mode 100644
index 0000000..f3a15e2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff4.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff4
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff4.inc b/FPGA_by_Fredi/Video/lpm_ff4.inc
new file mode 100644
index 0000000..ea243d6
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff4.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff4 
+(
+	clock,
+	data[15..0]
+)
+
+RETURNS (
+	q[15..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_ff4.qip b/FPGA_by_Fredi/Video/lpm_ff4.qip
new file mode 100644
index 0000000..f5a0a35
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff4.vhd b/FPGA_by_Fredi/Video/lpm_ff4.vhd
new file mode 100644
index 0000000..a738a64
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff4.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff4.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff4 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_ff4;
+
+
+ARCHITECTURE SYN OF lpm_ff4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(15 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 16
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff5.bsf b/FPGA_by_Fredi/Video/lpm_ff5.bsf
new file mode 100644
index 0000000..a69af6e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff5.cmp b/FPGA_by_Fredi/Video/lpm_ff5.cmp
new file mode 100644
index 0000000..6ad77c9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff5.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff5
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff5.inc b/FPGA_by_Fredi/Video/lpm_ff5.inc
new file mode 100644
index 0000000..f65f941
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff5 
+(
+	clock,
+	data[7..0]
+)
+
+RETURNS (
+	q[7..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_ff5.qip b/FPGA_by_Fredi/Video/lpm_ff5.qip
new file mode 100644
index 0000000..0d13267
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff5.vhd b/FPGA_by_Fredi/Video/lpm_ff5.vhd
new file mode 100644
index 0000000..96063a2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff5.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff5.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff5 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_ff5;
+
+
+ARCHITECTURE SYN OF lpm_ff5 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 8
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_ff6.bsf b/FPGA_by_Fredi/Video/lpm_ff6.bsf
new file mode 100644
index 0000000..73a2df0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff6.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_ff6.cmp b/FPGA_by_Fredi/Video/lpm_ff6.cmp
new file mode 100644
index 0000000..50df3ad
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff6.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_ff6
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_ff6.inc b/FPGA_by_Fredi/Video/lpm_ff6.inc
new file mode 100644
index 0000000..c8a5a36
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff6.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff6 
+(
+	clock,
+	data[127..0],
+	enable
+)
+
+RETURNS (
+	q[127..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_ff6.qip b/FPGA_by_Fredi/Video/lpm_ff6.qip
new file mode 100644
index 0000000..08e02f0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_ff6.vhd b/FPGA_by_Fredi/Video/lpm_ff6.vhd
new file mode 100644
index 0000000..5cc384d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_ff6.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff6.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_ff6;
+
+
+ARCHITECTURE SYN OF lpm_ff6 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enable	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 128
+	)
+	PORT MAP (
+		enable => enable,
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf b/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
new file mode 100644
index 0000000..1e24640
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
@@ -0,0 +1,79 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 144)
+	(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 125 31 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(text "(ack)" (rect 51 67 76 81)(font "Arial" ))
+		(text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 128)(line_width 1))
+		(line (pt 144 128)(pt 16 128)(line_width 1))
+		(line (pt 16 128)(pt 16 16)(line_width 1))
+		(line (pt 16 108)(pt 144 108)(line_width 1))
+		(line (pt 16 90)(pt 22 96)(line_width 1))
+		(line (pt 22 96)(pt 16 102)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.cmp b/FPGA_by_Fredi/Video/lpm_fifoDZ.cmp
new file mode 100644
index 0000000..153e7c2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_fifoDZ
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.qip b/FPGA_by_Fredi/Video/lpm_fifoDZ.qip
new file mode 100644
index 0000000..5444627
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd b/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
new file mode 100644
index 0000000..95486bb
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
@@ -0,0 +1,178 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo 
+
+-- ============================================================
+-- File Name: lpm_fifoDZ.vhd
+-- Megafunction Name(s):
+-- 			scfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY lpm_fifoDZ IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_fifoDZ;
+
+
+ARCHITECTURE SYN OF lpm_fifodz IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT scfifo
+	GENERIC (
+		add_ram_output_register		: STRING;
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		underflow_checking		: STRING;
+		use_eab		: STRING
+	);
+	PORT (
+			rdreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	scfifo_component : scfifo
+	GENERIC MAP (
+		add_ram_output_register => "OFF",
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 128,
+		lpm_showahead => "ON",
+		lpm_type => "scfifo",
+		lpm_width => 128,
+		lpm_widthu => 7,
+		overflow_checking => "OFF",
+		underflow_checking => "OFF",
+		use_eab => "ON"
+	)
+	PORT MAP (
+		rdreq => rdreq,
+		aclr => aclr,
+		clock => clock,
+		wrreq => wrreq,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "128"
+-- Retrieval info: PRIVATE: Empty NUMERIC "0"
+-- Retrieval info: PRIVATE: Full NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: Width NUMERIC "128"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "128"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
new file mode 100644
index 0000000..467441f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
+<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd".  The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
+<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf b/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
new file mode 100644
index 0000000..61b485b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
@@ -0,0 +1,102 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(port
+		(pt 160 120)
+		(output)
+		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
+		(line (pt 160 120)(pt 144 120)(line_width 1))
+	)
+	(drawing
+		(text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp b/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
new file mode 100644
index 0000000..08f6114
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
@@ -0,0 +1,29 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_fifo_dc0
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc b/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
new file mode 100644
index 0000000..d29fb88
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_fifo_dc0 
+(
+	aclr,
+	data[127..0],
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq
+)
+
+RETURNS (
+	q[127..0],
+	rdempty,
+	wrusedw[8..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip b/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
new file mode 100644
index 0000000..e883724
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd b/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
new file mode 100644
index 0000000..8646d9c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
@@ -0,0 +1,203 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo 
+
+-- ============================================================
+-- File Name: lpm_fifo_dc0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY lpm_fifo_dc0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
+	);
+END lpm_fifo_dc0;
+
+
+ARCHITECTURE SYN OF lpm_fifo_dc0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (8 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdempty	: OUT STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	rdempty    <= sub_wire0;
+	wrusedw    <= sub_wire1(8 DOWNTO 0);
+	q    <= sub_wire2(127 DOWNTO 0);
+
+	dcfifo_component : dcfifo
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 512,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 128,
+		lpm_widthu => 9,
+		overflow_checking => "OFF",
+		rdsync_delaypipe => 6,
+		underflow_checking => "OFF",
+		use_eab => "ON",
+		write_aclr_synch => "ON",
+		wrsync_delaypipe => 6
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		rdempty => sub_wire0,
+		wrusedw => sub_wire1,
+		q => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "512"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "128"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "128"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "6"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
new file mode 100644
index 0000000..3f52c1c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for lpm_fifo_dc0.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file lpm_fifo_dc0.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd.  The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
+<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_latch1.bsf b/FPGA_by_Fredi/Video/lpm_latch1.bsf
new file mode 100644
index 0000000..7197b2f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_latch1.bsf
@@ -0,0 +1,53 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 80)
+	(text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 64)(line_width 1))
+		(line (pt 144 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_latch1.cmp b/FPGA_by_Fredi/Video/lpm_latch1.cmp
new file mode 100644
index 0000000..ac4b322
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_latch1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_latch1
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_latch1.qip b/FPGA_by_Fredi/Video/lpm_latch1.qip
new file mode 100644
index 0000000..bc53d50
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_latch1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_LATCH"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_latch1.vhd b/FPGA_by_Fredi/Video/lpm_latch1.vhd
new file mode 100644
index 0000000..0afc209
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_latch1.vhd
@@ -0,0 +1,110 @@
+-- megafunction wizard: %LPM_LATCH%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_latch 
+
+-- ============================================================
+-- File Name: lpm_latch1.vhd
+-- Megafunction Name(s):
+-- 			lpm_latch
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_latch1 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_latch1;
+
+
+ARCHITECTURE SYN OF lpm_latch1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_latch
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			gate	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_latch_component : lpm_latch
+	GENERIC MAP (
+		lpm_type => "LPM_LATCH",
+		lpm_width => 32
+	)
+	PORT MAP (
+		data => data,
+		gate => gate,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: aset NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux0.bsf b/FPGA_by_Fredi/Video/lpm_mux0.bsf
new file mode 100644
index 0000000..ce1e27e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux0.bsf
@@ -0,0 +1,83 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 128)
+	(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 1))
+	)
+	(port
+		(pt 80 128)
+		(input)
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8)))
+		(line (pt 80 128)(pt 80 116)(line_width 3))
+	)
+	(port
+		(pt 152 72)
+		(output)
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
+		(line (pt 152 72)(pt 88 72)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 120)(line_width 1))
+		(line (pt 88 32)(pt 88 112)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 120)(pt 88 112)(line_width 1))
+		(line (pt 72 98)(pt 78 104)(line_width 1))
+		(line (pt 78 104)(pt 72 110)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux0.cmp b/FPGA_by_Fredi/Video/lpm_mux0.cmp
new file mode 100644
index 0000000..7b6c18f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux0.cmp
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux0
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux0.inc b/FPGA_by_Fredi/Video/lpm_mux0.inc
new file mode 100644
index 0000000..b0bc2be
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux0.inc
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux0 
+(
+	clock,
+	data0x[31..0],
+	data1x[31..0],
+	data2x[31..0],
+	data3x[31..0],
+	sel[1..0]
+)
+
+RETURNS (
+	result[31..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_mux0.qip b/FPGA_by_Fredi/Video/lpm_mux0.qip
new file mode 100644
index 0000000..5e8e2b6
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux0.vhd b/FPGA_by_Fredi/Video/lpm_mux0.vhd
new file mode 100644
index 0000000..9d641a4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux0.vhd
@@ -0,0 +1,251 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux0.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_mux0;
+
+
+ARCHITECTURE SYN OF lpm_mux0 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(31 DOWNTO 0);
+	sub_wire4    <= data1x(31 DOWNTO 0);
+	sub_wire3    <= data2x(31 DOWNTO 0);
+	result    <= sub_wire0(31 DOWNTO 0);
+	sub_wire1    <= data3x(31 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 31)    <= sub_wire5(31);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 4,
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 32,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
+-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
+-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
+-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0]
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux1.bsf b/FPGA_by_Fredi/Video/lpm_mux1.bsf
new file mode 100644
index 0000000..24ee953
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux1.bsf
@@ -0,0 +1,111 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 192)
+	(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
+	)
+	(port
+		(pt 80 192)
+		(input)
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
+	)
+	(port
+		(pt 152 104)
+		(output)
+		(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux1.cmp b/FPGA_by_Fredi/Video/lpm_mux1.cmp
new file mode 100644
index 0000000..cfc222a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux1.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux1.inc b/FPGA_by_Fredi/Video/lpm_mux1.inc
new file mode 100644
index 0000000..e2f94a4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux1.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux1 
+(
+	clock,
+	data0x[15..0],
+	data1x[15..0],
+	data2x[15..0],
+	data3x[15..0],
+	data4x[15..0],
+	data5x[15..0],
+	data6x[15..0],
+	data7x[15..0],
+	sel[2..0]
+)
+
+RETURNS (
+	result[15..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_mux1.qip b/FPGA_by_Fredi/Video/lpm_mux1.qip
new file mode 100644
index 0000000..8a445b2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux1.vhd b/FPGA_by_Fredi/Video/lpm_mux1.vhd
new file mode 100644
index 0000000..a9ad991
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux1.vhd
@@ -0,0 +1,271 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux1.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_mux1;
+
+
+ARCHITECTURE SYN OF lpm_mux1 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+BEGIN
+	sub_wire9    <= data0x(15 DOWNTO 0);
+	sub_wire8    <= data1x(15 DOWNTO 0);
+	sub_wire7    <= data2x(15 DOWNTO 0);
+	sub_wire6    <= data3x(15 DOWNTO 0);
+	sub_wire5    <= data4x(15 DOWNTO 0);
+	sub_wire4    <= data5x(15 DOWNTO 0);
+	sub_wire3    <= data6x(15 DOWNTO 0);
+	result    <= sub_wire0(15 DOWNTO 0);
+	sub_wire1    <= data7x(15 DOWNTO 0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 15)    <= sub_wire9(15);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 4,
+		lpm_size => 8,
+		lpm_type => "LPM_MUX",
+		lpm_width => 16,
+		lpm_widths => 3
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
+-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
+-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
+-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
+-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
+-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
+-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
+-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
+-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux2.bsf b/FPGA_by_Fredi/Video/lpm_mux2.bsf
new file mode 100644
index 0000000..b37c425
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux2.bsf
@@ -0,0 +1,167 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 320)
+	(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 304 25 316)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 3))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 72 184)(line_width 3))
+	)
+	(port
+		(pt 0 200)
+		(input)
+		(text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8)))
+		(line (pt 0 200)(pt 72 200)(line_width 3))
+	)
+	(port
+		(pt 0 216)
+		(input)
+		(text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8)))
+		(line (pt 0 216)(pt 72 216)(line_width 3))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 72 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 72 248)(line_width 3))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 72 264)(line_width 3))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 72 280)(line_width 3))
+	)
+	(port
+		(pt 0 296)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8)))
+		(line (pt 0 296)(pt 72 296)(line_width 1))
+	)
+	(port
+		(pt 80 320)
+		(input)
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
+		(line (pt 80 320)(pt 80 308)(line_width 3))
+	)
+	(port
+		(pt 144 168)
+		(output)
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8)))
+		(line (pt 144 168)(pt 88 168)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 312)(line_width 1))
+		(line (pt 88 32)(pt 88 304)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 312)(pt 88 304)(line_width 1))
+		(line (pt 72 290)(pt 78 296)(line_width 1))
+		(line (pt 78 296)(pt 72 302)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux2.cmp b/FPGA_by_Fredi/Video/lpm_mux2.cmp
new file mode 100644
index 0000000..d94260c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux2.cmp
@@ -0,0 +1,39 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux2
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux2.inc b/FPGA_by_Fredi/Video/lpm_mux2.inc
new file mode 100644
index 0000000..2334c7e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux2.inc
@@ -0,0 +1,40 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux2 
+(
+	clock,
+	data0x[7..0],
+	data10x[7..0],
+	data11x[7..0],
+	data12x[7..0],
+	data13x[7..0],
+	data14x[7..0],
+	data15x[7..0],
+	data1x[7..0],
+	data2x[7..0],
+	data3x[7..0],
+	data4x[7..0],
+	data5x[7..0],
+	data6x[7..0],
+	data7x[7..0],
+	data8x[7..0],
+	data9x[7..0],
+	sel[3..0]
+)
+
+RETURNS (
+	result[7..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_mux2.qip b/FPGA_by_Fredi/Video/lpm_mux2.qip
new file mode 100644
index 0000000..7b5db74
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux2.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux2.vhd b/FPGA_by_Fredi/Video/lpm_mux2.vhd
new file mode 100644
index 0000000..cfece2e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux2.vhd
@@ -0,0 +1,311 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux2.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_mux2;
+
+
+ARCHITECTURE SYN OF lpm_mux2 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	sub_wire17    <= data0x(7 DOWNTO 0);
+	sub_wire16    <= data1x(7 DOWNTO 0);
+	sub_wire15    <= data2x(7 DOWNTO 0);
+	sub_wire14    <= data3x(7 DOWNTO 0);
+	sub_wire13    <= data4x(7 DOWNTO 0);
+	sub_wire12    <= data5x(7 DOWNTO 0);
+	sub_wire11    <= data6x(7 DOWNTO 0);
+	sub_wire10    <= data7x(7 DOWNTO 0);
+	sub_wire9    <= data8x(7 DOWNTO 0);
+	sub_wire8    <= data9x(7 DOWNTO 0);
+	sub_wire7    <= data10x(7 DOWNTO 0);
+	sub_wire6    <= data11x(7 DOWNTO 0);
+	sub_wire5    <= data12x(7 DOWNTO 0);
+	sub_wire4    <= data13x(7 DOWNTO 0);
+	sub_wire3    <= data14x(7 DOWNTO 0);
+	result    <= sub_wire0(7 DOWNTO 0);
+	sub_wire1    <= data15x(7 DOWNTO 0);
+	sub_wire2(15, 0)    <= sub_wire1(0);
+	sub_wire2(15, 1)    <= sub_wire1(1);
+	sub_wire2(15, 2)    <= sub_wire1(2);
+	sub_wire2(15, 3)    <= sub_wire1(3);
+	sub_wire2(15, 4)    <= sub_wire1(4);
+	sub_wire2(15, 5)    <= sub_wire1(5);
+	sub_wire2(15, 6)    <= sub_wire1(6);
+	sub_wire2(15, 7)    <= sub_wire1(7);
+	sub_wire2(14, 0)    <= sub_wire3(0);
+	sub_wire2(14, 1)    <= sub_wire3(1);
+	sub_wire2(14, 2)    <= sub_wire3(2);
+	sub_wire2(14, 3)    <= sub_wire3(3);
+	sub_wire2(14, 4)    <= sub_wire3(4);
+	sub_wire2(14, 5)    <= sub_wire3(5);
+	sub_wire2(14, 6)    <= sub_wire3(6);
+	sub_wire2(14, 7)    <= sub_wire3(7);
+	sub_wire2(13, 0)    <= sub_wire4(0);
+	sub_wire2(13, 1)    <= sub_wire4(1);
+	sub_wire2(13, 2)    <= sub_wire4(2);
+	sub_wire2(13, 3)    <= sub_wire4(3);
+	sub_wire2(13, 4)    <= sub_wire4(4);
+	sub_wire2(13, 5)    <= sub_wire4(5);
+	sub_wire2(13, 6)    <= sub_wire4(6);
+	sub_wire2(13, 7)    <= sub_wire4(7);
+	sub_wire2(12, 0)    <= sub_wire5(0);
+	sub_wire2(12, 1)    <= sub_wire5(1);
+	sub_wire2(12, 2)    <= sub_wire5(2);
+	sub_wire2(12, 3)    <= sub_wire5(3);
+	sub_wire2(12, 4)    <= sub_wire5(4);
+	sub_wire2(12, 5)    <= sub_wire5(5);
+	sub_wire2(12, 6)    <= sub_wire5(6);
+	sub_wire2(12, 7)    <= sub_wire5(7);
+	sub_wire2(11, 0)    <= sub_wire6(0);
+	sub_wire2(11, 1)    <= sub_wire6(1);
+	sub_wire2(11, 2)    <= sub_wire6(2);
+	sub_wire2(11, 3)    <= sub_wire6(3);
+	sub_wire2(11, 4)    <= sub_wire6(4);
+	sub_wire2(11, 5)    <= sub_wire6(5);
+	sub_wire2(11, 6)    <= sub_wire6(6);
+	sub_wire2(11, 7)    <= sub_wire6(7);
+	sub_wire2(10, 0)    <= sub_wire7(0);
+	sub_wire2(10, 1)    <= sub_wire7(1);
+	sub_wire2(10, 2)    <= sub_wire7(2);
+	sub_wire2(10, 3)    <= sub_wire7(3);
+	sub_wire2(10, 4)    <= sub_wire7(4);
+	sub_wire2(10, 5)    <= sub_wire7(5);
+	sub_wire2(10, 6)    <= sub_wire7(6);
+	sub_wire2(10, 7)    <= sub_wire7(7);
+	sub_wire2(9, 0)    <= sub_wire8(0);
+	sub_wire2(9, 1)    <= sub_wire8(1);
+	sub_wire2(9, 2)    <= sub_wire8(2);
+	sub_wire2(9, 3)    <= sub_wire8(3);
+	sub_wire2(9, 4)    <= sub_wire8(4);
+	sub_wire2(9, 5)    <= sub_wire8(5);
+	sub_wire2(9, 6)    <= sub_wire8(6);
+	sub_wire2(9, 7)    <= sub_wire8(7);
+	sub_wire2(8, 0)    <= sub_wire9(0);
+	sub_wire2(8, 1)    <= sub_wire9(1);
+	sub_wire2(8, 2)    <= sub_wire9(2);
+	sub_wire2(8, 3)    <= sub_wire9(3);
+	sub_wire2(8, 4)    <= sub_wire9(4);
+	sub_wire2(8, 5)    <= sub_wire9(5);
+	sub_wire2(8, 6)    <= sub_wire9(6);
+	sub_wire2(8, 7)    <= sub_wire9(7);
+	sub_wire2(7, 0)    <= sub_wire10(0);
+	sub_wire2(7, 1)    <= sub_wire10(1);
+	sub_wire2(7, 2)    <= sub_wire10(2);
+	sub_wire2(7, 3)    <= sub_wire10(3);
+	sub_wire2(7, 4)    <= sub_wire10(4);
+	sub_wire2(7, 5)    <= sub_wire10(5);
+	sub_wire2(7, 6)    <= sub_wire10(6);
+	sub_wire2(7, 7)    <= sub_wire10(7);
+	sub_wire2(6, 0)    <= sub_wire11(0);
+	sub_wire2(6, 1)    <= sub_wire11(1);
+	sub_wire2(6, 2)    <= sub_wire11(2);
+	sub_wire2(6, 3)    <= sub_wire11(3);
+	sub_wire2(6, 4)    <= sub_wire11(4);
+	sub_wire2(6, 5)    <= sub_wire11(5);
+	sub_wire2(6, 6)    <= sub_wire11(6);
+	sub_wire2(6, 7)    <= sub_wire11(7);
+	sub_wire2(5, 0)    <= sub_wire12(0);
+	sub_wire2(5, 1)    <= sub_wire12(1);
+	sub_wire2(5, 2)    <= sub_wire12(2);
+	sub_wire2(5, 3)    <= sub_wire12(3);
+	sub_wire2(5, 4)    <= sub_wire12(4);
+	sub_wire2(5, 5)    <= sub_wire12(5);
+	sub_wire2(5, 6)    <= sub_wire12(6);
+	sub_wire2(5, 7)    <= sub_wire12(7);
+	sub_wire2(4, 0)    <= sub_wire13(0);
+	sub_wire2(4, 1)    <= sub_wire13(1);
+	sub_wire2(4, 2)    <= sub_wire13(2);
+	sub_wire2(4, 3)    <= sub_wire13(3);
+	sub_wire2(4, 4)    <= sub_wire13(4);
+	sub_wire2(4, 5)    <= sub_wire13(5);
+	sub_wire2(4, 6)    <= sub_wire13(6);
+	sub_wire2(4, 7)    <= sub_wire13(7);
+	sub_wire2(3, 0)    <= sub_wire14(0);
+	sub_wire2(3, 1)    <= sub_wire14(1);
+	sub_wire2(3, 2)    <= sub_wire14(2);
+	sub_wire2(3, 3)    <= sub_wire14(3);
+	sub_wire2(3, 4)    <= sub_wire14(4);
+	sub_wire2(3, 5)    <= sub_wire14(5);
+	sub_wire2(3, 6)    <= sub_wire14(6);
+	sub_wire2(3, 7)    <= sub_wire14(7);
+	sub_wire2(2, 0)    <= sub_wire15(0);
+	sub_wire2(2, 1)    <= sub_wire15(1);
+	sub_wire2(2, 2)    <= sub_wire15(2);
+	sub_wire2(2, 3)    <= sub_wire15(3);
+	sub_wire2(2, 4)    <= sub_wire15(4);
+	sub_wire2(2, 5)    <= sub_wire15(5);
+	sub_wire2(2, 6)    <= sub_wire15(6);
+	sub_wire2(2, 7)    <= sub_wire15(7);
+	sub_wire2(1, 0)    <= sub_wire16(0);
+	sub_wire2(1, 1)    <= sub_wire16(1);
+	sub_wire2(1, 2)    <= sub_wire16(2);
+	sub_wire2(1, 3)    <= sub_wire16(3);
+	sub_wire2(1, 4)    <= sub_wire16(4);
+	sub_wire2(1, 5)    <= sub_wire16(5);
+	sub_wire2(1, 6)    <= sub_wire16(6);
+	sub_wire2(1, 7)    <= sub_wire16(7);
+	sub_wire2(0, 0)    <= sub_wire17(0);
+	sub_wire2(0, 1)    <= sub_wire17(1);
+	sub_wire2(0, 2)    <= sub_wire17(2);
+	sub_wire2(0, 3)    <= sub_wire17(3);
+	sub_wire2(0, 4)    <= sub_wire17(4);
+	sub_wire2(0, 5)    <= sub_wire17(5);
+	sub_wire2(0, 6)    <= sub_wire17(6);
+	sub_wire2(0, 7)    <= sub_wire17(7);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 2,
+		lpm_size => 16,
+		lpm_type => "LPM_MUX",
+		lpm_width => 8,
+		lpm_widths => 4
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
+-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0]
+-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0]
+-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0]
+-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0]
+-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0]
+-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0]
+-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
+-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
+-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
+-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0]
+-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0]
+-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0]
+-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0]
+-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0]
+-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0]
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux3.bsf b/FPGA_by_Fredi/Video/lpm_mux3.bsf
new file mode 100644
index 0000000..c389543
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux3.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 80)
+	(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 32 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 32 56)(line_width 1))
+	)
+	(port
+		(pt 40 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
+		(line (pt 40 80)(pt 40 68)(line_width 1))
+	)
+	(port
+		(pt 80 48)
+		(output)
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 80 48)(pt 48 48)(line_width 1))
+	)
+	(drawing
+		(line (pt 32 24)(pt 32 72)(line_width 1))
+		(line (pt 48 32)(pt 48 64)(line_width 1))
+		(line (pt 32 24)(pt 48 32)(line_width 1))
+		(line (pt 32 72)(pt 48 64)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux3.cmp b/FPGA_by_Fredi/Video/lpm_mux3.cmp
new file mode 100644
index 0000000..48f730d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux3.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux3
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux3.qip b/FPGA_by_Fredi/Video/lpm_mux3.qip
new file mode 100644
index 0000000..ca1e672
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux3.vhd b/FPGA_by_Fredi/Video/lpm_mux3.vhd
new file mode 100644
index 0000000..b975686
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux3.vhd
@@ -0,0 +1,115 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux3.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux3 IS
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+END lpm_mux3;
+
+
+ARCHITECTURE SYN OF lpm_mux3 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+
+BEGIN
+	sub_wire6    <= data0;
+	sub_wire1    <= sub_wire0(0);
+	result    <= sub_wire1;
+	sub_wire2    <= sel;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= data1;
+	sub_wire5(1, 0)    <= sub_wire4;
+	sub_wire5(0, 0)    <= sub_wire6;
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 1,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire3,
+		data => sub_wire5,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux4.bsf b/FPGA_by_Fredi/Video/lpm_mux4.bsf
new file mode 100644
index 0000000..a1c9ca0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux4.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 136 80)
+	(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 72 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8)))
+		(line (pt 72 80)(pt 72 68)(line_width 1))
+	)
+	(port
+		(pt 136 48)
+		(output)
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8)))
+		(line (pt 136 48)(pt 80 48)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 72)(line_width 1))
+		(line (pt 80 32)(pt 80 64)(line_width 1))
+		(line (pt 64 24)(pt 80 32)(line_width 1))
+		(line (pt 64 72)(pt 80 64)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux4.cmp b/FPGA_by_Fredi/Video/lpm_mux4.cmp
new file mode 100644
index 0000000..05e7a07
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux4.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux4
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux4.qip b/FPGA_by_Fredi/Video/lpm_mux4.qip
new file mode 100644
index 0000000..7712e39
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux4.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux4.vhd b/FPGA_by_Fredi/Video/lpm_mux4.vhd
new file mode 100644
index 0000000..854a491
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux4.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux4.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux4 IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+END lpm_mux4;
+
+
+ARCHITECTURE SYN OF lpm_mux4 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(6 DOWNTO 0);
+	result    <= sub_wire0(6 DOWNTO 0);
+	sub_wire1    <= sel;
+	sub_wire2(0)    <= sub_wire1;
+	sub_wire3    <= data1x(6 DOWNTO 0);
+	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire4(0, 6)    <= sub_wire5(6);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 7,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire2,
+		data => sub_wire4,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0]
+-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0]
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux5.bsf b/FPGA_by_Fredi/Video/lpm_mux5.bsf
new file mode 100644
index 0000000..e63ce50
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux5.bsf
@@ -0,0 +1,74 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 112)
+	(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 80 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8)))
+		(line (pt 80 112)(pt 80 100)(line_width 3))
+	)
+	(port
+		(pt 152 64)
+		(output)
+		(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8)))
+		(line (pt 152 64)(pt 88 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 104)(line_width 1))
+		(line (pt 88 32)(pt 88 96)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 104)(pt 88 96)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux5.cmp b/FPGA_by_Fredi/Video/lpm_mux5.cmp
new file mode 100644
index 0000000..efc712a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux5.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux5
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux5.inc b/FPGA_by_Fredi/Video/lpm_mux5.inc
new file mode 100644
index 0000000..a063f55
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux5.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux5 
+(
+	data0x[63..0],
+	data1x[63..0],
+	data2x[63..0],
+	data3x[63..0],
+	sel[1..0]
+)
+
+RETURNS (
+	result[63..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_mux5.qip b/FPGA_by_Fredi/Video/lpm_mux5.qip
new file mode 100644
index 0000000..08b2e74
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux5.vhd b/FPGA_by_Fredi/Video/lpm_mux5.vhd
new file mode 100644
index 0000000..1d35347
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux5.vhd
@@ -0,0 +1,373 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux5.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux5 IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+	);
+END lpm_mux5;
+
+
+ARCHITECTURE SYN OF lpm_mux5 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(63 DOWNTO 0);
+	sub_wire4    <= data1x(63 DOWNTO 0);
+	sub_wire3    <= data2x(63 DOWNTO 0);
+	result    <= sub_wire0(63 DOWNTO 0);
+	sub_wire1    <= data3x(63 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(3, 32)    <= sub_wire1(32);
+	sub_wire2(3, 33)    <= sub_wire1(33);
+	sub_wire2(3, 34)    <= sub_wire1(34);
+	sub_wire2(3, 35)    <= sub_wire1(35);
+	sub_wire2(3, 36)    <= sub_wire1(36);
+	sub_wire2(3, 37)    <= sub_wire1(37);
+	sub_wire2(3, 38)    <= sub_wire1(38);
+	sub_wire2(3, 39)    <= sub_wire1(39);
+	sub_wire2(3, 40)    <= sub_wire1(40);
+	sub_wire2(3, 41)    <= sub_wire1(41);
+	sub_wire2(3, 42)    <= sub_wire1(42);
+	sub_wire2(3, 43)    <= sub_wire1(43);
+	sub_wire2(3, 44)    <= sub_wire1(44);
+	sub_wire2(3, 45)    <= sub_wire1(45);
+	sub_wire2(3, 46)    <= sub_wire1(46);
+	sub_wire2(3, 47)    <= sub_wire1(47);
+	sub_wire2(3, 48)    <= sub_wire1(48);
+	sub_wire2(3, 49)    <= sub_wire1(49);
+	sub_wire2(3, 50)    <= sub_wire1(50);
+	sub_wire2(3, 51)    <= sub_wire1(51);
+	sub_wire2(3, 52)    <= sub_wire1(52);
+	sub_wire2(3, 53)    <= sub_wire1(53);
+	sub_wire2(3, 54)    <= sub_wire1(54);
+	sub_wire2(3, 55)    <= sub_wire1(55);
+	sub_wire2(3, 56)    <= sub_wire1(56);
+	sub_wire2(3, 57)    <= sub_wire1(57);
+	sub_wire2(3, 58)    <= sub_wire1(58);
+	sub_wire2(3, 59)    <= sub_wire1(59);
+	sub_wire2(3, 60)    <= sub_wire1(60);
+	sub_wire2(3, 61)    <= sub_wire1(61);
+	sub_wire2(3, 62)    <= sub_wire1(62);
+	sub_wire2(3, 63)    <= sub_wire1(63);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(2, 32)    <= sub_wire3(32);
+	sub_wire2(2, 33)    <= sub_wire3(33);
+	sub_wire2(2, 34)    <= sub_wire3(34);
+	sub_wire2(2, 35)    <= sub_wire3(35);
+	sub_wire2(2, 36)    <= sub_wire3(36);
+	sub_wire2(2, 37)    <= sub_wire3(37);
+	sub_wire2(2, 38)    <= sub_wire3(38);
+	sub_wire2(2, 39)    <= sub_wire3(39);
+	sub_wire2(2, 40)    <= sub_wire3(40);
+	sub_wire2(2, 41)    <= sub_wire3(41);
+	sub_wire2(2, 42)    <= sub_wire3(42);
+	sub_wire2(2, 43)    <= sub_wire3(43);
+	sub_wire2(2, 44)    <= sub_wire3(44);
+	sub_wire2(2, 45)    <= sub_wire3(45);
+	sub_wire2(2, 46)    <= sub_wire3(46);
+	sub_wire2(2, 47)    <= sub_wire3(47);
+	sub_wire2(2, 48)    <= sub_wire3(48);
+	sub_wire2(2, 49)    <= sub_wire3(49);
+	sub_wire2(2, 50)    <= sub_wire3(50);
+	sub_wire2(2, 51)    <= sub_wire3(51);
+	sub_wire2(2, 52)    <= sub_wire3(52);
+	sub_wire2(2, 53)    <= sub_wire3(53);
+	sub_wire2(2, 54)    <= sub_wire3(54);
+	sub_wire2(2, 55)    <= sub_wire3(55);
+	sub_wire2(2, 56)    <= sub_wire3(56);
+	sub_wire2(2, 57)    <= sub_wire3(57);
+	sub_wire2(2, 58)    <= sub_wire3(58);
+	sub_wire2(2, 59)    <= sub_wire3(59);
+	sub_wire2(2, 60)    <= sub_wire3(60);
+	sub_wire2(2, 61)    <= sub_wire3(61);
+	sub_wire2(2, 62)    <= sub_wire3(62);
+	sub_wire2(2, 63)    <= sub_wire3(63);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(1, 32)    <= sub_wire4(32);
+	sub_wire2(1, 33)    <= sub_wire4(33);
+	sub_wire2(1, 34)    <= sub_wire4(34);
+	sub_wire2(1, 35)    <= sub_wire4(35);
+	sub_wire2(1, 36)    <= sub_wire4(36);
+	sub_wire2(1, 37)    <= sub_wire4(37);
+	sub_wire2(1, 38)    <= sub_wire4(38);
+	sub_wire2(1, 39)    <= sub_wire4(39);
+	sub_wire2(1, 40)    <= sub_wire4(40);
+	sub_wire2(1, 41)    <= sub_wire4(41);
+	sub_wire2(1, 42)    <= sub_wire4(42);
+	sub_wire2(1, 43)    <= sub_wire4(43);
+	sub_wire2(1, 44)    <= sub_wire4(44);
+	sub_wire2(1, 45)    <= sub_wire4(45);
+	sub_wire2(1, 46)    <= sub_wire4(46);
+	sub_wire2(1, 47)    <= sub_wire4(47);
+	sub_wire2(1, 48)    <= sub_wire4(48);
+	sub_wire2(1, 49)    <= sub_wire4(49);
+	sub_wire2(1, 50)    <= sub_wire4(50);
+	sub_wire2(1, 51)    <= sub_wire4(51);
+	sub_wire2(1, 52)    <= sub_wire4(52);
+	sub_wire2(1, 53)    <= sub_wire4(53);
+	sub_wire2(1, 54)    <= sub_wire4(54);
+	sub_wire2(1, 55)    <= sub_wire4(55);
+	sub_wire2(1, 56)    <= sub_wire4(56);
+	sub_wire2(1, 57)    <= sub_wire4(57);
+	sub_wire2(1, 58)    <= sub_wire4(58);
+	sub_wire2(1, 59)    <= sub_wire4(59);
+	sub_wire2(1, 60)    <= sub_wire4(60);
+	sub_wire2(1, 61)    <= sub_wire4(61);
+	sub_wire2(1, 62)    <= sub_wire4(62);
+	sub_wire2(1, 63)    <= sub_wire4(63);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 31)    <= sub_wire5(31);
+	sub_wire2(0, 32)    <= sub_wire5(32);
+	sub_wire2(0, 33)    <= sub_wire5(33);
+	sub_wire2(0, 34)    <= sub_wire5(34);
+	sub_wire2(0, 35)    <= sub_wire5(35);
+	sub_wire2(0, 36)    <= sub_wire5(36);
+	sub_wire2(0, 37)    <= sub_wire5(37);
+	sub_wire2(0, 38)    <= sub_wire5(38);
+	sub_wire2(0, 39)    <= sub_wire5(39);
+	sub_wire2(0, 40)    <= sub_wire5(40);
+	sub_wire2(0, 41)    <= sub_wire5(41);
+	sub_wire2(0, 42)    <= sub_wire5(42);
+	sub_wire2(0, 43)    <= sub_wire5(43);
+	sub_wire2(0, 44)    <= sub_wire5(44);
+	sub_wire2(0, 45)    <= sub_wire5(45);
+	sub_wire2(0, 46)    <= sub_wire5(46);
+	sub_wire2(0, 47)    <= sub_wire5(47);
+	sub_wire2(0, 48)    <= sub_wire5(48);
+	sub_wire2(0, 49)    <= sub_wire5(49);
+	sub_wire2(0, 50)    <= sub_wire5(50);
+	sub_wire2(0, 51)    <= sub_wire5(51);
+	sub_wire2(0, 52)    <= sub_wire5(52);
+	sub_wire2(0, 53)    <= sub_wire5(53);
+	sub_wire2(0, 54)    <= sub_wire5(54);
+	sub_wire2(0, 55)    <= sub_wire5(55);
+	sub_wire2(0, 56)    <= sub_wire5(56);
+	sub_wire2(0, 57)    <= sub_wire5(57);
+	sub_wire2(0, 58)    <= sub_wire5(58);
+	sub_wire2(0, 59)    <= sub_wire5(59);
+	sub_wire2(0, 60)    <= sub_wire5(60);
+	sub_wire2(0, 61)    <= sub_wire5(61);
+	sub_wire2(0, 62)    <= sub_wire5(62);
+	sub_wire2(0, 63)    <= sub_wire5(63);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 64,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		sel => sel,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0]
+-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0]
+-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0]
+-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0]
+-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_mux6.bsf b/FPGA_by_Fredi/Video/lpm_mux6.bsf
new file mode 100644
index 0000000..2196842
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux6.bsf
@@ -0,0 +1,111 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 192)
+	(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
+	)
+	(port
+		(pt 80 192)
+		(input)
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
+	)
+	(port
+		(pt 152 104)
+		(output)
+		(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_mux6.cmp b/FPGA_by_Fredi/Video/lpm_mux6.cmp
new file mode 100644
index 0000000..543da1f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux6.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux6
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_mux6.inc b/FPGA_by_Fredi/Video/lpm_mux6.inc
new file mode 100644
index 0000000..3cf223d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux6.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux6 
+(
+	clock,
+	data0x[23..0],
+	data1x[23..0],
+	data2x[23..0],
+	data3x[23..0],
+	data4x[23..0],
+	data5x[23..0],
+	data6x[23..0],
+	data7x[23..0],
+	sel[2..0]
+)
+
+RETURNS (
+	result[23..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_mux6.qip b/FPGA_by_Fredi/Video/lpm_mux6.qip
new file mode 100644
index 0000000..051a945
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_mux6.vhd b/FPGA_by_Fredi/Video/lpm_mux6.vhd
new file mode 100644
index 0000000..42d5aae
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_mux6.vhd
@@ -0,0 +1,335 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux6.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_mux6;
+
+
+ARCHITECTURE SYN OF lpm_mux6 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+BEGIN
+	sub_wire9    <= data0x(23 DOWNTO 0);
+	sub_wire8    <= data1x(23 DOWNTO 0);
+	sub_wire7    <= data2x(23 DOWNTO 0);
+	sub_wire6    <= data3x(23 DOWNTO 0);
+	sub_wire5    <= data4x(23 DOWNTO 0);
+	sub_wire4    <= data5x(23 DOWNTO 0);
+	sub_wire3    <= data6x(23 DOWNTO 0);
+	result    <= sub_wire0(23 DOWNTO 0);
+	sub_wire1    <= data7x(23 DOWNTO 0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(7, 16)    <= sub_wire1(16);
+	sub_wire2(7, 17)    <= sub_wire1(17);
+	sub_wire2(7, 18)    <= sub_wire1(18);
+	sub_wire2(7, 19)    <= sub_wire1(19);
+	sub_wire2(7, 20)    <= sub_wire1(20);
+	sub_wire2(7, 21)    <= sub_wire1(21);
+	sub_wire2(7, 22)    <= sub_wire1(22);
+	sub_wire2(7, 23)    <= sub_wire1(23);
+	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(6, 16)    <= sub_wire3(16);
+	sub_wire2(6, 17)    <= sub_wire3(17);
+	sub_wire2(6, 18)    <= sub_wire3(18);
+	sub_wire2(6, 19)    <= sub_wire3(19);
+	sub_wire2(6, 20)    <= sub_wire3(20);
+	sub_wire2(6, 21)    <= sub_wire3(21);
+	sub_wire2(6, 22)    <= sub_wire3(22);
+	sub_wire2(6, 23)    <= sub_wire3(23);
+	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(5, 16)    <= sub_wire4(16);
+	sub_wire2(5, 17)    <= sub_wire4(17);
+	sub_wire2(5, 18)    <= sub_wire4(18);
+	sub_wire2(5, 19)    <= sub_wire4(19);
+	sub_wire2(5, 20)    <= sub_wire4(20);
+	sub_wire2(5, 21)    <= sub_wire4(21);
+	sub_wire2(5, 22)    <= sub_wire4(22);
+	sub_wire2(5, 23)    <= sub_wire4(23);
+	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(4, 16)    <= sub_wire5(16);
+	sub_wire2(4, 17)    <= sub_wire5(17);
+	sub_wire2(4, 18)    <= sub_wire5(18);
+	sub_wire2(4, 19)    <= sub_wire5(19);
+	sub_wire2(4, 20)    <= sub_wire5(20);
+	sub_wire2(4, 21)    <= sub_wire5(21);
+	sub_wire2(4, 22)    <= sub_wire5(22);
+	sub_wire2(4, 23)    <= sub_wire5(23);
+	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(3, 16)    <= sub_wire6(16);
+	sub_wire2(3, 17)    <= sub_wire6(17);
+	sub_wire2(3, 18)    <= sub_wire6(18);
+	sub_wire2(3, 19)    <= sub_wire6(19);
+	sub_wire2(3, 20)    <= sub_wire6(20);
+	sub_wire2(3, 21)    <= sub_wire6(21);
+	sub_wire2(3, 22)    <= sub_wire6(22);
+	sub_wire2(3, 23)    <= sub_wire6(23);
+	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(2, 16)    <= sub_wire7(16);
+	sub_wire2(2, 17)    <= sub_wire7(17);
+	sub_wire2(2, 18)    <= sub_wire7(18);
+	sub_wire2(2, 19)    <= sub_wire7(19);
+	sub_wire2(2, 20)    <= sub_wire7(20);
+	sub_wire2(2, 21)    <= sub_wire7(21);
+	sub_wire2(2, 22)    <= sub_wire7(22);
+	sub_wire2(2, 23)    <= sub_wire7(23);
+	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(1, 16)    <= sub_wire8(16);
+	sub_wire2(1, 17)    <= sub_wire8(17);
+	sub_wire2(1, 18)    <= sub_wire8(18);
+	sub_wire2(1, 19)    <= sub_wire8(19);
+	sub_wire2(1, 20)    <= sub_wire8(20);
+	sub_wire2(1, 21)    <= sub_wire8(21);
+	sub_wire2(1, 22)    <= sub_wire8(22);
+	sub_wire2(1, 23)    <= sub_wire8(23);
+	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 15)    <= sub_wire9(15);
+	sub_wire2(0, 16)    <= sub_wire9(16);
+	sub_wire2(0, 17)    <= sub_wire9(17);
+	sub_wire2(0, 18)    <= sub_wire9(18);
+	sub_wire2(0, 19)    <= sub_wire9(19);
+	sub_wire2(0, 20)    <= sub_wire9(20);
+	sub_wire2(0, 21)    <= sub_wire9(21);
+	sub_wire2(0, 22)    <= sub_wire9(22);
+	sub_wire2(0, 23)    <= sub_wire9(23);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 2,
+		lpm_size => 8,
+		lpm_type => "LPM_MUX",
+		lpm_width => 24,
+		lpm_widths => 3
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0]
+-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0]
+-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0]
+-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0]
+-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0]
+-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0]
+-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0]
+-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0]
+-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0]
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ.bsf b/FPGA_by_Fredi/Video/lpm_muxDZ.bsf
new file mode 100644
index 0000000..f4f1c7d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ.bsf
@@ -0,0 +1,76 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 168 112)
+	(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 80 72)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 80 88)(line_width 1))
+	)
+	(port
+		(pt 88 112)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
+		(line (pt 88 112)(pt 88 100)(line_width 1))
+	)
+	(port
+		(pt 168 64)
+		(output)
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
+		(line (pt 168 64)(pt 96 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 104)(line_width 1))
+		(line (pt 96 32)(pt 96 96)(line_width 1))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 80 104)(pt 96 96)(line_width 1))
+		(line (pt 80 66)(pt 86 72)(line_width 1))
+		(line (pt 86 72)(pt 80 78)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ.cmp b/FPGA_by_Fredi/Video/lpm_muxDZ.cmp
new file mode 100644
index 0000000..f177216
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_muxDZ
+	PORT
+	(
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ.qip b/FPGA_by_Fredi/Video/lpm_muxDZ.qip
new file mode 100644
index 0000000..34ffc75
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ.vhd b/FPGA_by_Fredi/Video/lpm_muxDZ.vhd
new file mode 100644
index 0000000..e9bd32e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ.vhd
@@ -0,0 +1,377 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxDZ.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxDZ IS
+	PORT
+	(
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_muxDZ;
+
+
+ARCHITECTURE SYN OF lpm_muxdz IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(127 DOWNTO 0);
+	result    <= sub_wire0(127 DOWNTO 0);
+	sub_wire1    <= sel;
+	sub_wire2(0)    <= sub_wire1;
+	sub_wire3    <= data1x(127 DOWNTO 0);
+	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire4(1, 7)    <= sub_wire3(7);
+	sub_wire4(1, 8)    <= sub_wire3(8);
+	sub_wire4(1, 9)    <= sub_wire3(9);
+	sub_wire4(1, 10)    <= sub_wire3(10);
+	sub_wire4(1, 11)    <= sub_wire3(11);
+	sub_wire4(1, 12)    <= sub_wire3(12);
+	sub_wire4(1, 13)    <= sub_wire3(13);
+	sub_wire4(1, 14)    <= sub_wire3(14);
+	sub_wire4(1, 15)    <= sub_wire3(15);
+	sub_wire4(1, 16)    <= sub_wire3(16);
+	sub_wire4(1, 17)    <= sub_wire3(17);
+	sub_wire4(1, 18)    <= sub_wire3(18);
+	sub_wire4(1, 19)    <= sub_wire3(19);
+	sub_wire4(1, 20)    <= sub_wire3(20);
+	sub_wire4(1, 21)    <= sub_wire3(21);
+	sub_wire4(1, 22)    <= sub_wire3(22);
+	sub_wire4(1, 23)    <= sub_wire3(23);
+	sub_wire4(1, 24)    <= sub_wire3(24);
+	sub_wire4(1, 25)    <= sub_wire3(25);
+	sub_wire4(1, 26)    <= sub_wire3(26);
+	sub_wire4(1, 27)    <= sub_wire3(27);
+	sub_wire4(1, 28)    <= sub_wire3(28);
+	sub_wire4(1, 29)    <= sub_wire3(29);
+	sub_wire4(1, 30)    <= sub_wire3(30);
+	sub_wire4(1, 31)    <= sub_wire3(31);
+	sub_wire4(1, 32)    <= sub_wire3(32);
+	sub_wire4(1, 33)    <= sub_wire3(33);
+	sub_wire4(1, 34)    <= sub_wire3(34);
+	sub_wire4(1, 35)    <= sub_wire3(35);
+	sub_wire4(1, 36)    <= sub_wire3(36);
+	sub_wire4(1, 37)    <= sub_wire3(37);
+	sub_wire4(1, 38)    <= sub_wire3(38);
+	sub_wire4(1, 39)    <= sub_wire3(39);
+	sub_wire4(1, 40)    <= sub_wire3(40);
+	sub_wire4(1, 41)    <= sub_wire3(41);
+	sub_wire4(1, 42)    <= sub_wire3(42);
+	sub_wire4(1, 43)    <= sub_wire3(43);
+	sub_wire4(1, 44)    <= sub_wire3(44);
+	sub_wire4(1, 45)    <= sub_wire3(45);
+	sub_wire4(1, 46)    <= sub_wire3(46);
+	sub_wire4(1, 47)    <= sub_wire3(47);
+	sub_wire4(1, 48)    <= sub_wire3(48);
+	sub_wire4(1, 49)    <= sub_wire3(49);
+	sub_wire4(1, 50)    <= sub_wire3(50);
+	sub_wire4(1, 51)    <= sub_wire3(51);
+	sub_wire4(1, 52)    <= sub_wire3(52);
+	sub_wire4(1, 53)    <= sub_wire3(53);
+	sub_wire4(1, 54)    <= sub_wire3(54);
+	sub_wire4(1, 55)    <= sub_wire3(55);
+	sub_wire4(1, 56)    <= sub_wire3(56);
+	sub_wire4(1, 57)    <= sub_wire3(57);
+	sub_wire4(1, 58)    <= sub_wire3(58);
+	sub_wire4(1, 59)    <= sub_wire3(59);
+	sub_wire4(1, 60)    <= sub_wire3(60);
+	sub_wire4(1, 61)    <= sub_wire3(61);
+	sub_wire4(1, 62)    <= sub_wire3(62);
+	sub_wire4(1, 63)    <= sub_wire3(63);
+	sub_wire4(1, 64)    <= sub_wire3(64);
+	sub_wire4(1, 65)    <= sub_wire3(65);
+	sub_wire4(1, 66)    <= sub_wire3(66);
+	sub_wire4(1, 67)    <= sub_wire3(67);
+	sub_wire4(1, 68)    <= sub_wire3(68);
+	sub_wire4(1, 69)    <= sub_wire3(69);
+	sub_wire4(1, 70)    <= sub_wire3(70);
+	sub_wire4(1, 71)    <= sub_wire3(71);
+	sub_wire4(1, 72)    <= sub_wire3(72);
+	sub_wire4(1, 73)    <= sub_wire3(73);
+	sub_wire4(1, 74)    <= sub_wire3(74);
+	sub_wire4(1, 75)    <= sub_wire3(75);
+	sub_wire4(1, 76)    <= sub_wire3(76);
+	sub_wire4(1, 77)    <= sub_wire3(77);
+	sub_wire4(1, 78)    <= sub_wire3(78);
+	sub_wire4(1, 79)    <= sub_wire3(79);
+	sub_wire4(1, 80)    <= sub_wire3(80);
+	sub_wire4(1, 81)    <= sub_wire3(81);
+	sub_wire4(1, 82)    <= sub_wire3(82);
+	sub_wire4(1, 83)    <= sub_wire3(83);
+	sub_wire4(1, 84)    <= sub_wire3(84);
+	sub_wire4(1, 85)    <= sub_wire3(85);
+	sub_wire4(1, 86)    <= sub_wire3(86);
+	sub_wire4(1, 87)    <= sub_wire3(87);
+	sub_wire4(1, 88)    <= sub_wire3(88);
+	sub_wire4(1, 89)    <= sub_wire3(89);
+	sub_wire4(1, 90)    <= sub_wire3(90);
+	sub_wire4(1, 91)    <= sub_wire3(91);
+	sub_wire4(1, 92)    <= sub_wire3(92);
+	sub_wire4(1, 93)    <= sub_wire3(93);
+	sub_wire4(1, 94)    <= sub_wire3(94);
+	sub_wire4(1, 95)    <= sub_wire3(95);
+	sub_wire4(1, 96)    <= sub_wire3(96);
+	sub_wire4(1, 97)    <= sub_wire3(97);
+	sub_wire4(1, 98)    <= sub_wire3(98);
+	sub_wire4(1, 99)    <= sub_wire3(99);
+	sub_wire4(1, 100)    <= sub_wire3(100);
+	sub_wire4(1, 101)    <= sub_wire3(101);
+	sub_wire4(1, 102)    <= sub_wire3(102);
+	sub_wire4(1, 103)    <= sub_wire3(103);
+	sub_wire4(1, 104)    <= sub_wire3(104);
+	sub_wire4(1, 105)    <= sub_wire3(105);
+	sub_wire4(1, 106)    <= sub_wire3(106);
+	sub_wire4(1, 107)    <= sub_wire3(107);
+	sub_wire4(1, 108)    <= sub_wire3(108);
+	sub_wire4(1, 109)    <= sub_wire3(109);
+	sub_wire4(1, 110)    <= sub_wire3(110);
+	sub_wire4(1, 111)    <= sub_wire3(111);
+	sub_wire4(1, 112)    <= sub_wire3(112);
+	sub_wire4(1, 113)    <= sub_wire3(113);
+	sub_wire4(1, 114)    <= sub_wire3(114);
+	sub_wire4(1, 115)    <= sub_wire3(115);
+	sub_wire4(1, 116)    <= sub_wire3(116);
+	sub_wire4(1, 117)    <= sub_wire3(117);
+	sub_wire4(1, 118)    <= sub_wire3(118);
+	sub_wire4(1, 119)    <= sub_wire3(119);
+	sub_wire4(1, 120)    <= sub_wire3(120);
+	sub_wire4(1, 121)    <= sub_wire3(121);
+	sub_wire4(1, 122)    <= sub_wire3(122);
+	sub_wire4(1, 123)    <= sub_wire3(123);
+	sub_wire4(1, 124)    <= sub_wire3(124);
+	sub_wire4(1, 125)    <= sub_wire3(125);
+	sub_wire4(1, 126)    <= sub_wire3(126);
+	sub_wire4(1, 127)    <= sub_wire3(127);
+	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire4(0, 6)    <= sub_wire5(6);
+	sub_wire4(0, 7)    <= sub_wire5(7);
+	sub_wire4(0, 8)    <= sub_wire5(8);
+	sub_wire4(0, 9)    <= sub_wire5(9);
+	sub_wire4(0, 10)    <= sub_wire5(10);
+	sub_wire4(0, 11)    <= sub_wire5(11);
+	sub_wire4(0, 12)    <= sub_wire5(12);
+	sub_wire4(0, 13)    <= sub_wire5(13);
+	sub_wire4(0, 14)    <= sub_wire5(14);
+	sub_wire4(0, 15)    <= sub_wire5(15);
+	sub_wire4(0, 16)    <= sub_wire5(16);
+	sub_wire4(0, 17)    <= sub_wire5(17);
+	sub_wire4(0, 18)    <= sub_wire5(18);
+	sub_wire4(0, 19)    <= sub_wire5(19);
+	sub_wire4(0, 20)    <= sub_wire5(20);
+	sub_wire4(0, 21)    <= sub_wire5(21);
+	sub_wire4(0, 22)    <= sub_wire5(22);
+	sub_wire4(0, 23)    <= sub_wire5(23);
+	sub_wire4(0, 24)    <= sub_wire5(24);
+	sub_wire4(0, 25)    <= sub_wire5(25);
+	sub_wire4(0, 26)    <= sub_wire5(26);
+	sub_wire4(0, 27)    <= sub_wire5(27);
+	sub_wire4(0, 28)    <= sub_wire5(28);
+	sub_wire4(0, 29)    <= sub_wire5(29);
+	sub_wire4(0, 30)    <= sub_wire5(30);
+	sub_wire4(0, 31)    <= sub_wire5(31);
+	sub_wire4(0, 32)    <= sub_wire5(32);
+	sub_wire4(0, 33)    <= sub_wire5(33);
+	sub_wire4(0, 34)    <= sub_wire5(34);
+	sub_wire4(0, 35)    <= sub_wire5(35);
+	sub_wire4(0, 36)    <= sub_wire5(36);
+	sub_wire4(0, 37)    <= sub_wire5(37);
+	sub_wire4(0, 38)    <= sub_wire5(38);
+	sub_wire4(0, 39)    <= sub_wire5(39);
+	sub_wire4(0, 40)    <= sub_wire5(40);
+	sub_wire4(0, 41)    <= sub_wire5(41);
+	sub_wire4(0, 42)    <= sub_wire5(42);
+	sub_wire4(0, 43)    <= sub_wire5(43);
+	sub_wire4(0, 44)    <= sub_wire5(44);
+	sub_wire4(0, 45)    <= sub_wire5(45);
+	sub_wire4(0, 46)    <= sub_wire5(46);
+	sub_wire4(0, 47)    <= sub_wire5(47);
+	sub_wire4(0, 48)    <= sub_wire5(48);
+	sub_wire4(0, 49)    <= sub_wire5(49);
+	sub_wire4(0, 50)    <= sub_wire5(50);
+	sub_wire4(0, 51)    <= sub_wire5(51);
+	sub_wire4(0, 52)    <= sub_wire5(52);
+	sub_wire4(0, 53)    <= sub_wire5(53);
+	sub_wire4(0, 54)    <= sub_wire5(54);
+	sub_wire4(0, 55)    <= sub_wire5(55);
+	sub_wire4(0, 56)    <= sub_wire5(56);
+	sub_wire4(0, 57)    <= sub_wire5(57);
+	sub_wire4(0, 58)    <= sub_wire5(58);
+	sub_wire4(0, 59)    <= sub_wire5(59);
+	sub_wire4(0, 60)    <= sub_wire5(60);
+	sub_wire4(0, 61)    <= sub_wire5(61);
+	sub_wire4(0, 62)    <= sub_wire5(62);
+	sub_wire4(0, 63)    <= sub_wire5(63);
+	sub_wire4(0, 64)    <= sub_wire5(64);
+	sub_wire4(0, 65)    <= sub_wire5(65);
+	sub_wire4(0, 66)    <= sub_wire5(66);
+	sub_wire4(0, 67)    <= sub_wire5(67);
+	sub_wire4(0, 68)    <= sub_wire5(68);
+	sub_wire4(0, 69)    <= sub_wire5(69);
+	sub_wire4(0, 70)    <= sub_wire5(70);
+	sub_wire4(0, 71)    <= sub_wire5(71);
+	sub_wire4(0, 72)    <= sub_wire5(72);
+	sub_wire4(0, 73)    <= sub_wire5(73);
+	sub_wire4(0, 74)    <= sub_wire5(74);
+	sub_wire4(0, 75)    <= sub_wire5(75);
+	sub_wire4(0, 76)    <= sub_wire5(76);
+	sub_wire4(0, 77)    <= sub_wire5(77);
+	sub_wire4(0, 78)    <= sub_wire5(78);
+	sub_wire4(0, 79)    <= sub_wire5(79);
+	sub_wire4(0, 80)    <= sub_wire5(80);
+	sub_wire4(0, 81)    <= sub_wire5(81);
+	sub_wire4(0, 82)    <= sub_wire5(82);
+	sub_wire4(0, 83)    <= sub_wire5(83);
+	sub_wire4(0, 84)    <= sub_wire5(84);
+	sub_wire4(0, 85)    <= sub_wire5(85);
+	sub_wire4(0, 86)    <= sub_wire5(86);
+	sub_wire4(0, 87)    <= sub_wire5(87);
+	sub_wire4(0, 88)    <= sub_wire5(88);
+	sub_wire4(0, 89)    <= sub_wire5(89);
+	sub_wire4(0, 90)    <= sub_wire5(90);
+	sub_wire4(0, 91)    <= sub_wire5(91);
+	sub_wire4(0, 92)    <= sub_wire5(92);
+	sub_wire4(0, 93)    <= sub_wire5(93);
+	sub_wire4(0, 94)    <= sub_wire5(94);
+	sub_wire4(0, 95)    <= sub_wire5(95);
+	sub_wire4(0, 96)    <= sub_wire5(96);
+	sub_wire4(0, 97)    <= sub_wire5(97);
+	sub_wire4(0, 98)    <= sub_wire5(98);
+	sub_wire4(0, 99)    <= sub_wire5(99);
+	sub_wire4(0, 100)    <= sub_wire5(100);
+	sub_wire4(0, 101)    <= sub_wire5(101);
+	sub_wire4(0, 102)    <= sub_wire5(102);
+	sub_wire4(0, 103)    <= sub_wire5(103);
+	sub_wire4(0, 104)    <= sub_wire5(104);
+	sub_wire4(0, 105)    <= sub_wire5(105);
+	sub_wire4(0, 106)    <= sub_wire5(106);
+	sub_wire4(0, 107)    <= sub_wire5(107);
+	sub_wire4(0, 108)    <= sub_wire5(108);
+	sub_wire4(0, 109)    <= sub_wire5(109);
+	sub_wire4(0, 110)    <= sub_wire5(110);
+	sub_wire4(0, 111)    <= sub_wire5(111);
+	sub_wire4(0, 112)    <= sub_wire5(112);
+	sub_wire4(0, 113)    <= sub_wire5(113);
+	sub_wire4(0, 114)    <= sub_wire5(114);
+	sub_wire4(0, 115)    <= sub_wire5(115);
+	sub_wire4(0, 116)    <= sub_wire5(116);
+	sub_wire4(0, 117)    <= sub_wire5(117);
+	sub_wire4(0, 118)    <= sub_wire5(118);
+	sub_wire4(0, 119)    <= sub_wire5(119);
+	sub_wire4(0, 120)    <= sub_wire5(120);
+	sub_wire4(0, 121)    <= sub_wire5(121);
+	sub_wire4(0, 122)    <= sub_wire5(122);
+	sub_wire4(0, 123)    <= sub_wire5(123);
+	sub_wire4(0, 124)    <= sub_wire5(124);
+	sub_wire4(0, 125)    <= sub_wire5(125);
+	sub_wire4(0, 126)    <= sub_wire5(126);
+	sub_wire4(0, 127)    <= sub_wire5(127);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 1,
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 128,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire2,
+		clken => clken,
+		clock => clock,
+		data => sub_wire4,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ2.bsf b/FPGA_by_Fredi/Video/lpm_muxDZ2.bsf
new file mode 100644
index 0000000..b7e3184
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ2.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 80)
+	(text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 40 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 40 56)(line_width 1))
+	)
+	(port
+		(pt 48 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8)))
+		(line (pt 48 80)(pt 48 68)(line_width 1))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 66 35 91 48)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 56 48)(line_width 1))
+	)
+	(drawing
+		(line (pt 40 24)(pt 40 72)(line_width 1))
+		(line (pt 56 32)(pt 56 64)(line_width 1))
+		(line (pt 40 24)(pt 56 32)(line_width 1))
+		(line (pt 40 72)(pt 56 64)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ2.cmp b/FPGA_by_Fredi/Video/lpm_muxDZ2.cmp
new file mode 100644
index 0000000..725acf4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ2.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_muxDZ2
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ2.qip b/FPGA_by_Fredi/Video/lpm_muxDZ2.qip
new file mode 100644
index 0000000..8203bc6
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_muxDZ2.vhd b/FPGA_by_Fredi/Video/lpm_muxDZ2.vhd
new file mode 100644
index 0000000..42e0c81
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxDZ2.vhd
@@ -0,0 +1,115 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxDZ2.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxDZ2 IS
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+END lpm_muxDZ2;
+
+
+ARCHITECTURE SYN OF lpm_muxdz2 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+
+BEGIN
+	sub_wire6    <= data0;
+	sub_wire1    <= sub_wire0(0);
+	result    <= sub_wire1;
+	sub_wire2    <= sel;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= data1;
+	sub_wire5(1, 0)    <= sub_wire4;
+	sub_wire5(0, 0)    <= sub_wire6;
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 1,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire3,
+		data => sub_wire5,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_muxVDM.bsf b/FPGA_by_Fredi/Video/lpm_muxVDM.bsf
new file mode 100644
index 0000000..42d235c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxVDM.bsf
@@ -0,0 +1,158 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 168 304)
+	(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 288 25 300)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 80 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 80 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 80 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 80 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 80 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 80 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 80 168)(line_width 3))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 80 184)(line_width 3))
+	)
+	(port
+		(pt 0 200)
+		(input)
+		(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8)))
+		(line (pt 0 200)(pt 80 200)(line_width 3))
+	)
+	(port
+		(pt 0 216)
+		(input)
+		(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8)))
+		(line (pt 0 216)(pt 80 216)(line_width 3))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 80 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 80 248)(line_width 3))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 80 264)(line_width 3))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 80 280)(line_width 3))
+	)
+	(port
+		(pt 88 304)
+		(input)
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8)))
+		(line (pt 88 304)(pt 88 292)(line_width 3))
+	)
+	(port
+		(pt 168 160)
+		(output)
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
+		(line (pt 168 160)(pt 96 160)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 296)(line_width 1))
+		(line (pt 96 32)(pt 96 288)(line_width 1))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 80 296)(pt 96 288)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_muxVDM.cmp b/FPGA_by_Fredi/Video/lpm_muxVDM.cmp
new file mode 100644
index 0000000..867776d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxVDM.cmp
@@ -0,0 +1,38 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_muxVDM
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_muxVDM.qip b/FPGA_by_Fredi/Video/lpm_muxVDM.qip
new file mode 100644
index 0000000..08a824e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxVDM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_muxVDM.vhd b/FPGA_by_Fredi/Video/lpm_muxVDM.vhd
new file mode 100644
index 0000000..662c8be
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_muxVDM.vhd
@@ -0,0 +1,2225 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxVDM.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxVDM IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_muxVDM;
+
+
+ARCHITECTURE SYN OF lpm_muxvdm IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+BEGIN
+	sub_wire17    <= data0x(127 DOWNTO 0);
+	sub_wire16    <= data1x(127 DOWNTO 0);
+	sub_wire15    <= data2x(127 DOWNTO 0);
+	sub_wire14    <= data3x(127 DOWNTO 0);
+	sub_wire13    <= data4x(127 DOWNTO 0);
+	sub_wire12    <= data5x(127 DOWNTO 0);
+	sub_wire11    <= data6x(127 DOWNTO 0);
+	sub_wire10    <= data7x(127 DOWNTO 0);
+	sub_wire9    <= data8x(127 DOWNTO 0);
+	sub_wire8    <= data9x(127 DOWNTO 0);
+	sub_wire7    <= data10x(127 DOWNTO 0);
+	sub_wire6    <= data11x(127 DOWNTO 0);
+	sub_wire5    <= data12x(127 DOWNTO 0);
+	sub_wire4    <= data13x(127 DOWNTO 0);
+	sub_wire3    <= data14x(127 DOWNTO 0);
+	result    <= sub_wire0(127 DOWNTO 0);
+	sub_wire1    <= data15x(127 DOWNTO 0);
+	sub_wire2(15, 0)    <= sub_wire1(0);
+	sub_wire2(15, 1)    <= sub_wire1(1);
+	sub_wire2(15, 2)    <= sub_wire1(2);
+	sub_wire2(15, 3)    <= sub_wire1(3);
+	sub_wire2(15, 4)    <= sub_wire1(4);
+	sub_wire2(15, 5)    <= sub_wire1(5);
+	sub_wire2(15, 6)    <= sub_wire1(6);
+	sub_wire2(15, 7)    <= sub_wire1(7);
+	sub_wire2(15, 8)    <= sub_wire1(8);
+	sub_wire2(15, 9)    <= sub_wire1(9);
+	sub_wire2(15, 10)    <= sub_wire1(10);
+	sub_wire2(15, 11)    <= sub_wire1(11);
+	sub_wire2(15, 12)    <= sub_wire1(12);
+	sub_wire2(15, 13)    <= sub_wire1(13);
+	sub_wire2(15, 14)    <= sub_wire1(14);
+	sub_wire2(15, 15)    <= sub_wire1(15);
+	sub_wire2(15, 16)    <= sub_wire1(16);
+	sub_wire2(15, 17)    <= sub_wire1(17);
+	sub_wire2(15, 18)    <= sub_wire1(18);
+	sub_wire2(15, 19)    <= sub_wire1(19);
+	sub_wire2(15, 20)    <= sub_wire1(20);
+	sub_wire2(15, 21)    <= sub_wire1(21);
+	sub_wire2(15, 22)    <= sub_wire1(22);
+	sub_wire2(15, 23)    <= sub_wire1(23);
+	sub_wire2(15, 24)    <= sub_wire1(24);
+	sub_wire2(15, 25)    <= sub_wire1(25);
+	sub_wire2(15, 26)    <= sub_wire1(26);
+	sub_wire2(15, 27)    <= sub_wire1(27);
+	sub_wire2(15, 28)    <= sub_wire1(28);
+	sub_wire2(15, 29)    <= sub_wire1(29);
+	sub_wire2(15, 30)    <= sub_wire1(30);
+	sub_wire2(15, 31)    <= sub_wire1(31);
+	sub_wire2(15, 32)    <= sub_wire1(32);
+	sub_wire2(15, 33)    <= sub_wire1(33);
+	sub_wire2(15, 34)    <= sub_wire1(34);
+	sub_wire2(15, 35)    <= sub_wire1(35);
+	sub_wire2(15, 36)    <= sub_wire1(36);
+	sub_wire2(15, 37)    <= sub_wire1(37);
+	sub_wire2(15, 38)    <= sub_wire1(38);
+	sub_wire2(15, 39)    <= sub_wire1(39);
+	sub_wire2(15, 40)    <= sub_wire1(40);
+	sub_wire2(15, 41)    <= sub_wire1(41);
+	sub_wire2(15, 42)    <= sub_wire1(42);
+	sub_wire2(15, 43)    <= sub_wire1(43);
+	sub_wire2(15, 44)    <= sub_wire1(44);
+	sub_wire2(15, 45)    <= sub_wire1(45);
+	sub_wire2(15, 46)    <= sub_wire1(46);
+	sub_wire2(15, 47)    <= sub_wire1(47);
+	sub_wire2(15, 48)    <= sub_wire1(48);
+	sub_wire2(15, 49)    <= sub_wire1(49);
+	sub_wire2(15, 50)    <= sub_wire1(50);
+	sub_wire2(15, 51)    <= sub_wire1(51);
+	sub_wire2(15, 52)    <= sub_wire1(52);
+	sub_wire2(15, 53)    <= sub_wire1(53);
+	sub_wire2(15, 54)    <= sub_wire1(54);
+	sub_wire2(15, 55)    <= sub_wire1(55);
+	sub_wire2(15, 56)    <= sub_wire1(56);
+	sub_wire2(15, 57)    <= sub_wire1(57);
+	sub_wire2(15, 58)    <= sub_wire1(58);
+	sub_wire2(15, 59)    <= sub_wire1(59);
+	sub_wire2(15, 60)    <= sub_wire1(60);
+	sub_wire2(15, 61)    <= sub_wire1(61);
+	sub_wire2(15, 62)    <= sub_wire1(62);
+	sub_wire2(15, 63)    <= sub_wire1(63);
+	sub_wire2(15, 64)    <= sub_wire1(64);
+	sub_wire2(15, 65)    <= sub_wire1(65);
+	sub_wire2(15, 66)    <= sub_wire1(66);
+	sub_wire2(15, 67)    <= sub_wire1(67);
+	sub_wire2(15, 68)    <= sub_wire1(68);
+	sub_wire2(15, 69)    <= sub_wire1(69);
+	sub_wire2(15, 70)    <= sub_wire1(70);
+	sub_wire2(15, 71)    <= sub_wire1(71);
+	sub_wire2(15, 72)    <= sub_wire1(72);
+	sub_wire2(15, 73)    <= sub_wire1(73);
+	sub_wire2(15, 74)    <= sub_wire1(74);
+	sub_wire2(15, 75)    <= sub_wire1(75);
+	sub_wire2(15, 76)    <= sub_wire1(76);
+	sub_wire2(15, 77)    <= sub_wire1(77);
+	sub_wire2(15, 78)    <= sub_wire1(78);
+	sub_wire2(15, 79)    <= sub_wire1(79);
+	sub_wire2(15, 80)    <= sub_wire1(80);
+	sub_wire2(15, 81)    <= sub_wire1(81);
+	sub_wire2(15, 82)    <= sub_wire1(82);
+	sub_wire2(15, 83)    <= sub_wire1(83);
+	sub_wire2(15, 84)    <= sub_wire1(84);
+	sub_wire2(15, 85)    <= sub_wire1(85);
+	sub_wire2(15, 86)    <= sub_wire1(86);
+	sub_wire2(15, 87)    <= sub_wire1(87);
+	sub_wire2(15, 88)    <= sub_wire1(88);
+	sub_wire2(15, 89)    <= sub_wire1(89);
+	sub_wire2(15, 90)    <= sub_wire1(90);
+	sub_wire2(15, 91)    <= sub_wire1(91);
+	sub_wire2(15, 92)    <= sub_wire1(92);
+	sub_wire2(15, 93)    <= sub_wire1(93);
+	sub_wire2(15, 94)    <= sub_wire1(94);
+	sub_wire2(15, 95)    <= sub_wire1(95);
+	sub_wire2(15, 96)    <= sub_wire1(96);
+	sub_wire2(15, 97)    <= sub_wire1(97);
+	sub_wire2(15, 98)    <= sub_wire1(98);
+	sub_wire2(15, 99)    <= sub_wire1(99);
+	sub_wire2(15, 100)    <= sub_wire1(100);
+	sub_wire2(15, 101)    <= sub_wire1(101);
+	sub_wire2(15, 102)    <= sub_wire1(102);
+	sub_wire2(15, 103)    <= sub_wire1(103);
+	sub_wire2(15, 104)    <= sub_wire1(104);
+	sub_wire2(15, 105)    <= sub_wire1(105);
+	sub_wire2(15, 106)    <= sub_wire1(106);
+	sub_wire2(15, 107)    <= sub_wire1(107);
+	sub_wire2(15, 108)    <= sub_wire1(108);
+	sub_wire2(15, 109)    <= sub_wire1(109);
+	sub_wire2(15, 110)    <= sub_wire1(110);
+	sub_wire2(15, 111)    <= sub_wire1(111);
+	sub_wire2(15, 112)    <= sub_wire1(112);
+	sub_wire2(15, 113)    <= sub_wire1(113);
+	sub_wire2(15, 114)    <= sub_wire1(114);
+	sub_wire2(15, 115)    <= sub_wire1(115);
+	sub_wire2(15, 116)    <= sub_wire1(116);
+	sub_wire2(15, 117)    <= sub_wire1(117);
+	sub_wire2(15, 118)    <= sub_wire1(118);
+	sub_wire2(15, 119)    <= sub_wire1(119);
+	sub_wire2(15, 120)    <= sub_wire1(120);
+	sub_wire2(15, 121)    <= sub_wire1(121);
+	sub_wire2(15, 122)    <= sub_wire1(122);
+	sub_wire2(15, 123)    <= sub_wire1(123);
+	sub_wire2(15, 124)    <= sub_wire1(124);
+	sub_wire2(15, 125)    <= sub_wire1(125);
+	sub_wire2(15, 126)    <= sub_wire1(126);
+	sub_wire2(15, 127)    <= sub_wire1(127);
+	sub_wire2(14, 0)    <= sub_wire3(0);
+	sub_wire2(14, 1)    <= sub_wire3(1);
+	sub_wire2(14, 2)    <= sub_wire3(2);
+	sub_wire2(14, 3)    <= sub_wire3(3);
+	sub_wire2(14, 4)    <= sub_wire3(4);
+	sub_wire2(14, 5)    <= sub_wire3(5);
+	sub_wire2(14, 6)    <= sub_wire3(6);
+	sub_wire2(14, 7)    <= sub_wire3(7);
+	sub_wire2(14, 8)    <= sub_wire3(8);
+	sub_wire2(14, 9)    <= sub_wire3(9);
+	sub_wire2(14, 10)    <= sub_wire3(10);
+	sub_wire2(14, 11)    <= sub_wire3(11);
+	sub_wire2(14, 12)    <= sub_wire3(12);
+	sub_wire2(14, 13)    <= sub_wire3(13);
+	sub_wire2(14, 14)    <= sub_wire3(14);
+	sub_wire2(14, 15)    <= sub_wire3(15);
+	sub_wire2(14, 16)    <= sub_wire3(16);
+	sub_wire2(14, 17)    <= sub_wire3(17);
+	sub_wire2(14, 18)    <= sub_wire3(18);
+	sub_wire2(14, 19)    <= sub_wire3(19);
+	sub_wire2(14, 20)    <= sub_wire3(20);
+	sub_wire2(14, 21)    <= sub_wire3(21);
+	sub_wire2(14, 22)    <= sub_wire3(22);
+	sub_wire2(14, 23)    <= sub_wire3(23);
+	sub_wire2(14, 24)    <= sub_wire3(24);
+	sub_wire2(14, 25)    <= sub_wire3(25);
+	sub_wire2(14, 26)    <= sub_wire3(26);
+	sub_wire2(14, 27)    <= sub_wire3(27);
+	sub_wire2(14, 28)    <= sub_wire3(28);
+	sub_wire2(14, 29)    <= sub_wire3(29);
+	sub_wire2(14, 30)    <= sub_wire3(30);
+	sub_wire2(14, 31)    <= sub_wire3(31);
+	sub_wire2(14, 32)    <= sub_wire3(32);
+	sub_wire2(14, 33)    <= sub_wire3(33);
+	sub_wire2(14, 34)    <= sub_wire3(34);
+	sub_wire2(14, 35)    <= sub_wire3(35);
+	sub_wire2(14, 36)    <= sub_wire3(36);
+	sub_wire2(14, 37)    <= sub_wire3(37);
+	sub_wire2(14, 38)    <= sub_wire3(38);
+	sub_wire2(14, 39)    <= sub_wire3(39);
+	sub_wire2(14, 40)    <= sub_wire3(40);
+	sub_wire2(14, 41)    <= sub_wire3(41);
+	sub_wire2(14, 42)    <= sub_wire3(42);
+	sub_wire2(14, 43)    <= sub_wire3(43);
+	sub_wire2(14, 44)    <= sub_wire3(44);
+	sub_wire2(14, 45)    <= sub_wire3(45);
+	sub_wire2(14, 46)    <= sub_wire3(46);
+	sub_wire2(14, 47)    <= sub_wire3(47);
+	sub_wire2(14, 48)    <= sub_wire3(48);
+	sub_wire2(14, 49)    <= sub_wire3(49);
+	sub_wire2(14, 50)    <= sub_wire3(50);
+	sub_wire2(14, 51)    <= sub_wire3(51);
+	sub_wire2(14, 52)    <= sub_wire3(52);
+	sub_wire2(14, 53)    <= sub_wire3(53);
+	sub_wire2(14, 54)    <= sub_wire3(54);
+	sub_wire2(14, 55)    <= sub_wire3(55);
+	sub_wire2(14, 56)    <= sub_wire3(56);
+	sub_wire2(14, 57)    <= sub_wire3(57);
+	sub_wire2(14, 58)    <= sub_wire3(58);
+	sub_wire2(14, 59)    <= sub_wire3(59);
+	sub_wire2(14, 60)    <= sub_wire3(60);
+	sub_wire2(14, 61)    <= sub_wire3(61);
+	sub_wire2(14, 62)    <= sub_wire3(62);
+	sub_wire2(14, 63)    <= sub_wire3(63);
+	sub_wire2(14, 64)    <= sub_wire3(64);
+	sub_wire2(14, 65)    <= sub_wire3(65);
+	sub_wire2(14, 66)    <= sub_wire3(66);
+	sub_wire2(14, 67)    <= sub_wire3(67);
+	sub_wire2(14, 68)    <= sub_wire3(68);
+	sub_wire2(14, 69)    <= sub_wire3(69);
+	sub_wire2(14, 70)    <= sub_wire3(70);
+	sub_wire2(14, 71)    <= sub_wire3(71);
+	sub_wire2(14, 72)    <= sub_wire3(72);
+	sub_wire2(14, 73)    <= sub_wire3(73);
+	sub_wire2(14, 74)    <= sub_wire3(74);
+	sub_wire2(14, 75)    <= sub_wire3(75);
+	sub_wire2(14, 76)    <= sub_wire3(76);
+	sub_wire2(14, 77)    <= sub_wire3(77);
+	sub_wire2(14, 78)    <= sub_wire3(78);
+	sub_wire2(14, 79)    <= sub_wire3(79);
+	sub_wire2(14, 80)    <= sub_wire3(80);
+	sub_wire2(14, 81)    <= sub_wire3(81);
+	sub_wire2(14, 82)    <= sub_wire3(82);
+	sub_wire2(14, 83)    <= sub_wire3(83);
+	sub_wire2(14, 84)    <= sub_wire3(84);
+	sub_wire2(14, 85)    <= sub_wire3(85);
+	sub_wire2(14, 86)    <= sub_wire3(86);
+	sub_wire2(14, 87)    <= sub_wire3(87);
+	sub_wire2(14, 88)    <= sub_wire3(88);
+	sub_wire2(14, 89)    <= sub_wire3(89);
+	sub_wire2(14, 90)    <= sub_wire3(90);
+	sub_wire2(14, 91)    <= sub_wire3(91);
+	sub_wire2(14, 92)    <= sub_wire3(92);
+	sub_wire2(14, 93)    <= sub_wire3(93);
+	sub_wire2(14, 94)    <= sub_wire3(94);
+	sub_wire2(14, 95)    <= sub_wire3(95);
+	sub_wire2(14, 96)    <= sub_wire3(96);
+	sub_wire2(14, 97)    <= sub_wire3(97);
+	sub_wire2(14, 98)    <= sub_wire3(98);
+	sub_wire2(14, 99)    <= sub_wire3(99);
+	sub_wire2(14, 100)    <= sub_wire3(100);
+	sub_wire2(14, 101)    <= sub_wire3(101);
+	sub_wire2(14, 102)    <= sub_wire3(102);
+	sub_wire2(14, 103)    <= sub_wire3(103);
+	sub_wire2(14, 104)    <= sub_wire3(104);
+	sub_wire2(14, 105)    <= sub_wire3(105);
+	sub_wire2(14, 106)    <= sub_wire3(106);
+	sub_wire2(14, 107)    <= sub_wire3(107);
+	sub_wire2(14, 108)    <= sub_wire3(108);
+	sub_wire2(14, 109)    <= sub_wire3(109);
+	sub_wire2(14, 110)    <= sub_wire3(110);
+	sub_wire2(14, 111)    <= sub_wire3(111);
+	sub_wire2(14, 112)    <= sub_wire3(112);
+	sub_wire2(14, 113)    <= sub_wire3(113);
+	sub_wire2(14, 114)    <= sub_wire3(114);
+	sub_wire2(14, 115)    <= sub_wire3(115);
+	sub_wire2(14, 116)    <= sub_wire3(116);
+	sub_wire2(14, 117)    <= sub_wire3(117);
+	sub_wire2(14, 118)    <= sub_wire3(118);
+	sub_wire2(14, 119)    <= sub_wire3(119);
+	sub_wire2(14, 120)    <= sub_wire3(120);
+	sub_wire2(14, 121)    <= sub_wire3(121);
+	sub_wire2(14, 122)    <= sub_wire3(122);
+	sub_wire2(14, 123)    <= sub_wire3(123);
+	sub_wire2(14, 124)    <= sub_wire3(124);
+	sub_wire2(14, 125)    <= sub_wire3(125);
+	sub_wire2(14, 126)    <= sub_wire3(126);
+	sub_wire2(14, 127)    <= sub_wire3(127);
+	sub_wire2(13, 0)    <= sub_wire4(0);
+	sub_wire2(13, 1)    <= sub_wire4(1);
+	sub_wire2(13, 2)    <= sub_wire4(2);
+	sub_wire2(13, 3)    <= sub_wire4(3);
+	sub_wire2(13, 4)    <= sub_wire4(4);
+	sub_wire2(13, 5)    <= sub_wire4(5);
+	sub_wire2(13, 6)    <= sub_wire4(6);
+	sub_wire2(13, 7)    <= sub_wire4(7);
+	sub_wire2(13, 8)    <= sub_wire4(8);
+	sub_wire2(13, 9)    <= sub_wire4(9);
+	sub_wire2(13, 10)    <= sub_wire4(10);
+	sub_wire2(13, 11)    <= sub_wire4(11);
+	sub_wire2(13, 12)    <= sub_wire4(12);
+	sub_wire2(13, 13)    <= sub_wire4(13);
+	sub_wire2(13, 14)    <= sub_wire4(14);
+	sub_wire2(13, 15)    <= sub_wire4(15);
+	sub_wire2(13, 16)    <= sub_wire4(16);
+	sub_wire2(13, 17)    <= sub_wire4(17);
+	sub_wire2(13, 18)    <= sub_wire4(18);
+	sub_wire2(13, 19)    <= sub_wire4(19);
+	sub_wire2(13, 20)    <= sub_wire4(20);
+	sub_wire2(13, 21)    <= sub_wire4(21);
+	sub_wire2(13, 22)    <= sub_wire4(22);
+	sub_wire2(13, 23)    <= sub_wire4(23);
+	sub_wire2(13, 24)    <= sub_wire4(24);
+	sub_wire2(13, 25)    <= sub_wire4(25);
+	sub_wire2(13, 26)    <= sub_wire4(26);
+	sub_wire2(13, 27)    <= sub_wire4(27);
+	sub_wire2(13, 28)    <= sub_wire4(28);
+	sub_wire2(13, 29)    <= sub_wire4(29);
+	sub_wire2(13, 30)    <= sub_wire4(30);
+	sub_wire2(13, 31)    <= sub_wire4(31);
+	sub_wire2(13, 32)    <= sub_wire4(32);
+	sub_wire2(13, 33)    <= sub_wire4(33);
+	sub_wire2(13, 34)    <= sub_wire4(34);
+	sub_wire2(13, 35)    <= sub_wire4(35);
+	sub_wire2(13, 36)    <= sub_wire4(36);
+	sub_wire2(13, 37)    <= sub_wire4(37);
+	sub_wire2(13, 38)    <= sub_wire4(38);
+	sub_wire2(13, 39)    <= sub_wire4(39);
+	sub_wire2(13, 40)    <= sub_wire4(40);
+	sub_wire2(13, 41)    <= sub_wire4(41);
+	sub_wire2(13, 42)    <= sub_wire4(42);
+	sub_wire2(13, 43)    <= sub_wire4(43);
+	sub_wire2(13, 44)    <= sub_wire4(44);
+	sub_wire2(13, 45)    <= sub_wire4(45);
+	sub_wire2(13, 46)    <= sub_wire4(46);
+	sub_wire2(13, 47)    <= sub_wire4(47);
+	sub_wire2(13, 48)    <= sub_wire4(48);
+	sub_wire2(13, 49)    <= sub_wire4(49);
+	sub_wire2(13, 50)    <= sub_wire4(50);
+	sub_wire2(13, 51)    <= sub_wire4(51);
+	sub_wire2(13, 52)    <= sub_wire4(52);
+	sub_wire2(13, 53)    <= sub_wire4(53);
+	sub_wire2(13, 54)    <= sub_wire4(54);
+	sub_wire2(13, 55)    <= sub_wire4(55);
+	sub_wire2(13, 56)    <= sub_wire4(56);
+	sub_wire2(13, 57)    <= sub_wire4(57);
+	sub_wire2(13, 58)    <= sub_wire4(58);
+	sub_wire2(13, 59)    <= sub_wire4(59);
+	sub_wire2(13, 60)    <= sub_wire4(60);
+	sub_wire2(13, 61)    <= sub_wire4(61);
+	sub_wire2(13, 62)    <= sub_wire4(62);
+	sub_wire2(13, 63)    <= sub_wire4(63);
+	sub_wire2(13, 64)    <= sub_wire4(64);
+	sub_wire2(13, 65)    <= sub_wire4(65);
+	sub_wire2(13, 66)    <= sub_wire4(66);
+	sub_wire2(13, 67)    <= sub_wire4(67);
+	sub_wire2(13, 68)    <= sub_wire4(68);
+	sub_wire2(13, 69)    <= sub_wire4(69);
+	sub_wire2(13, 70)    <= sub_wire4(70);
+	sub_wire2(13, 71)    <= sub_wire4(71);
+	sub_wire2(13, 72)    <= sub_wire4(72);
+	sub_wire2(13, 73)    <= sub_wire4(73);
+	sub_wire2(13, 74)    <= sub_wire4(74);
+	sub_wire2(13, 75)    <= sub_wire4(75);
+	sub_wire2(13, 76)    <= sub_wire4(76);
+	sub_wire2(13, 77)    <= sub_wire4(77);
+	sub_wire2(13, 78)    <= sub_wire4(78);
+	sub_wire2(13, 79)    <= sub_wire4(79);
+	sub_wire2(13, 80)    <= sub_wire4(80);
+	sub_wire2(13, 81)    <= sub_wire4(81);
+	sub_wire2(13, 82)    <= sub_wire4(82);
+	sub_wire2(13, 83)    <= sub_wire4(83);
+	sub_wire2(13, 84)    <= sub_wire4(84);
+	sub_wire2(13, 85)    <= sub_wire4(85);
+	sub_wire2(13, 86)    <= sub_wire4(86);
+	sub_wire2(13, 87)    <= sub_wire4(87);
+	sub_wire2(13, 88)    <= sub_wire4(88);
+	sub_wire2(13, 89)    <= sub_wire4(89);
+	sub_wire2(13, 90)    <= sub_wire4(90);
+	sub_wire2(13, 91)    <= sub_wire4(91);
+	sub_wire2(13, 92)    <= sub_wire4(92);
+	sub_wire2(13, 93)    <= sub_wire4(93);
+	sub_wire2(13, 94)    <= sub_wire4(94);
+	sub_wire2(13, 95)    <= sub_wire4(95);
+	sub_wire2(13, 96)    <= sub_wire4(96);
+	sub_wire2(13, 97)    <= sub_wire4(97);
+	sub_wire2(13, 98)    <= sub_wire4(98);
+	sub_wire2(13, 99)    <= sub_wire4(99);
+	sub_wire2(13, 100)    <= sub_wire4(100);
+	sub_wire2(13, 101)    <= sub_wire4(101);
+	sub_wire2(13, 102)    <= sub_wire4(102);
+	sub_wire2(13, 103)    <= sub_wire4(103);
+	sub_wire2(13, 104)    <= sub_wire4(104);
+	sub_wire2(13, 105)    <= sub_wire4(105);
+	sub_wire2(13, 106)    <= sub_wire4(106);
+	sub_wire2(13, 107)    <= sub_wire4(107);
+	sub_wire2(13, 108)    <= sub_wire4(108);
+	sub_wire2(13, 109)    <= sub_wire4(109);
+	sub_wire2(13, 110)    <= sub_wire4(110);
+	sub_wire2(13, 111)    <= sub_wire4(111);
+	sub_wire2(13, 112)    <= sub_wire4(112);
+	sub_wire2(13, 113)    <= sub_wire4(113);
+	sub_wire2(13, 114)    <= sub_wire4(114);
+	sub_wire2(13, 115)    <= sub_wire4(115);
+	sub_wire2(13, 116)    <= sub_wire4(116);
+	sub_wire2(13, 117)    <= sub_wire4(117);
+	sub_wire2(13, 118)    <= sub_wire4(118);
+	sub_wire2(13, 119)    <= sub_wire4(119);
+	sub_wire2(13, 120)    <= sub_wire4(120);
+	sub_wire2(13, 121)    <= sub_wire4(121);
+	sub_wire2(13, 122)    <= sub_wire4(122);
+	sub_wire2(13, 123)    <= sub_wire4(123);
+	sub_wire2(13, 124)    <= sub_wire4(124);
+	sub_wire2(13, 125)    <= sub_wire4(125);
+	sub_wire2(13, 126)    <= sub_wire4(126);
+	sub_wire2(13, 127)    <= sub_wire4(127);
+	sub_wire2(12, 0)    <= sub_wire5(0);
+	sub_wire2(12, 1)    <= sub_wire5(1);
+	sub_wire2(12, 2)    <= sub_wire5(2);
+	sub_wire2(12, 3)    <= sub_wire5(3);
+	sub_wire2(12, 4)    <= sub_wire5(4);
+	sub_wire2(12, 5)    <= sub_wire5(5);
+	sub_wire2(12, 6)    <= sub_wire5(6);
+	sub_wire2(12, 7)    <= sub_wire5(7);
+	sub_wire2(12, 8)    <= sub_wire5(8);
+	sub_wire2(12, 9)    <= sub_wire5(9);
+	sub_wire2(12, 10)    <= sub_wire5(10);
+	sub_wire2(12, 11)    <= sub_wire5(11);
+	sub_wire2(12, 12)    <= sub_wire5(12);
+	sub_wire2(12, 13)    <= sub_wire5(13);
+	sub_wire2(12, 14)    <= sub_wire5(14);
+	sub_wire2(12, 15)    <= sub_wire5(15);
+	sub_wire2(12, 16)    <= sub_wire5(16);
+	sub_wire2(12, 17)    <= sub_wire5(17);
+	sub_wire2(12, 18)    <= sub_wire5(18);
+	sub_wire2(12, 19)    <= sub_wire5(19);
+	sub_wire2(12, 20)    <= sub_wire5(20);
+	sub_wire2(12, 21)    <= sub_wire5(21);
+	sub_wire2(12, 22)    <= sub_wire5(22);
+	sub_wire2(12, 23)    <= sub_wire5(23);
+	sub_wire2(12, 24)    <= sub_wire5(24);
+	sub_wire2(12, 25)    <= sub_wire5(25);
+	sub_wire2(12, 26)    <= sub_wire5(26);
+	sub_wire2(12, 27)    <= sub_wire5(27);
+	sub_wire2(12, 28)    <= sub_wire5(28);
+	sub_wire2(12, 29)    <= sub_wire5(29);
+	sub_wire2(12, 30)    <= sub_wire5(30);
+	sub_wire2(12, 31)    <= sub_wire5(31);
+	sub_wire2(12, 32)    <= sub_wire5(32);
+	sub_wire2(12, 33)    <= sub_wire5(33);
+	sub_wire2(12, 34)    <= sub_wire5(34);
+	sub_wire2(12, 35)    <= sub_wire5(35);
+	sub_wire2(12, 36)    <= sub_wire5(36);
+	sub_wire2(12, 37)    <= sub_wire5(37);
+	sub_wire2(12, 38)    <= sub_wire5(38);
+	sub_wire2(12, 39)    <= sub_wire5(39);
+	sub_wire2(12, 40)    <= sub_wire5(40);
+	sub_wire2(12, 41)    <= sub_wire5(41);
+	sub_wire2(12, 42)    <= sub_wire5(42);
+	sub_wire2(12, 43)    <= sub_wire5(43);
+	sub_wire2(12, 44)    <= sub_wire5(44);
+	sub_wire2(12, 45)    <= sub_wire5(45);
+	sub_wire2(12, 46)    <= sub_wire5(46);
+	sub_wire2(12, 47)    <= sub_wire5(47);
+	sub_wire2(12, 48)    <= sub_wire5(48);
+	sub_wire2(12, 49)    <= sub_wire5(49);
+	sub_wire2(12, 50)    <= sub_wire5(50);
+	sub_wire2(12, 51)    <= sub_wire5(51);
+	sub_wire2(12, 52)    <= sub_wire5(52);
+	sub_wire2(12, 53)    <= sub_wire5(53);
+	sub_wire2(12, 54)    <= sub_wire5(54);
+	sub_wire2(12, 55)    <= sub_wire5(55);
+	sub_wire2(12, 56)    <= sub_wire5(56);
+	sub_wire2(12, 57)    <= sub_wire5(57);
+	sub_wire2(12, 58)    <= sub_wire5(58);
+	sub_wire2(12, 59)    <= sub_wire5(59);
+	sub_wire2(12, 60)    <= sub_wire5(60);
+	sub_wire2(12, 61)    <= sub_wire5(61);
+	sub_wire2(12, 62)    <= sub_wire5(62);
+	sub_wire2(12, 63)    <= sub_wire5(63);
+	sub_wire2(12, 64)    <= sub_wire5(64);
+	sub_wire2(12, 65)    <= sub_wire5(65);
+	sub_wire2(12, 66)    <= sub_wire5(66);
+	sub_wire2(12, 67)    <= sub_wire5(67);
+	sub_wire2(12, 68)    <= sub_wire5(68);
+	sub_wire2(12, 69)    <= sub_wire5(69);
+	sub_wire2(12, 70)    <= sub_wire5(70);
+	sub_wire2(12, 71)    <= sub_wire5(71);
+	sub_wire2(12, 72)    <= sub_wire5(72);
+	sub_wire2(12, 73)    <= sub_wire5(73);
+	sub_wire2(12, 74)    <= sub_wire5(74);
+	sub_wire2(12, 75)    <= sub_wire5(75);
+	sub_wire2(12, 76)    <= sub_wire5(76);
+	sub_wire2(12, 77)    <= sub_wire5(77);
+	sub_wire2(12, 78)    <= sub_wire5(78);
+	sub_wire2(12, 79)    <= sub_wire5(79);
+	sub_wire2(12, 80)    <= sub_wire5(80);
+	sub_wire2(12, 81)    <= sub_wire5(81);
+	sub_wire2(12, 82)    <= sub_wire5(82);
+	sub_wire2(12, 83)    <= sub_wire5(83);
+	sub_wire2(12, 84)    <= sub_wire5(84);
+	sub_wire2(12, 85)    <= sub_wire5(85);
+	sub_wire2(12, 86)    <= sub_wire5(86);
+	sub_wire2(12, 87)    <= sub_wire5(87);
+	sub_wire2(12, 88)    <= sub_wire5(88);
+	sub_wire2(12, 89)    <= sub_wire5(89);
+	sub_wire2(12, 90)    <= sub_wire5(90);
+	sub_wire2(12, 91)    <= sub_wire5(91);
+	sub_wire2(12, 92)    <= sub_wire5(92);
+	sub_wire2(12, 93)    <= sub_wire5(93);
+	sub_wire2(12, 94)    <= sub_wire5(94);
+	sub_wire2(12, 95)    <= sub_wire5(95);
+	sub_wire2(12, 96)    <= sub_wire5(96);
+	sub_wire2(12, 97)    <= sub_wire5(97);
+	sub_wire2(12, 98)    <= sub_wire5(98);
+	sub_wire2(12, 99)    <= sub_wire5(99);
+	sub_wire2(12, 100)    <= sub_wire5(100);
+	sub_wire2(12, 101)    <= sub_wire5(101);
+	sub_wire2(12, 102)    <= sub_wire5(102);
+	sub_wire2(12, 103)    <= sub_wire5(103);
+	sub_wire2(12, 104)    <= sub_wire5(104);
+	sub_wire2(12, 105)    <= sub_wire5(105);
+	sub_wire2(12, 106)    <= sub_wire5(106);
+	sub_wire2(12, 107)    <= sub_wire5(107);
+	sub_wire2(12, 108)    <= sub_wire5(108);
+	sub_wire2(12, 109)    <= sub_wire5(109);
+	sub_wire2(12, 110)    <= sub_wire5(110);
+	sub_wire2(12, 111)    <= sub_wire5(111);
+	sub_wire2(12, 112)    <= sub_wire5(112);
+	sub_wire2(12, 113)    <= sub_wire5(113);
+	sub_wire2(12, 114)    <= sub_wire5(114);
+	sub_wire2(12, 115)    <= sub_wire5(115);
+	sub_wire2(12, 116)    <= sub_wire5(116);
+	sub_wire2(12, 117)    <= sub_wire5(117);
+	sub_wire2(12, 118)    <= sub_wire5(118);
+	sub_wire2(12, 119)    <= sub_wire5(119);
+	sub_wire2(12, 120)    <= sub_wire5(120);
+	sub_wire2(12, 121)    <= sub_wire5(121);
+	sub_wire2(12, 122)    <= sub_wire5(122);
+	sub_wire2(12, 123)    <= sub_wire5(123);
+	sub_wire2(12, 124)    <= sub_wire5(124);
+	sub_wire2(12, 125)    <= sub_wire5(125);
+	sub_wire2(12, 126)    <= sub_wire5(126);
+	sub_wire2(12, 127)    <= sub_wire5(127);
+	sub_wire2(11, 0)    <= sub_wire6(0);
+	sub_wire2(11, 1)    <= sub_wire6(1);
+	sub_wire2(11, 2)    <= sub_wire6(2);
+	sub_wire2(11, 3)    <= sub_wire6(3);
+	sub_wire2(11, 4)    <= sub_wire6(4);
+	sub_wire2(11, 5)    <= sub_wire6(5);
+	sub_wire2(11, 6)    <= sub_wire6(6);
+	sub_wire2(11, 7)    <= sub_wire6(7);
+	sub_wire2(11, 8)    <= sub_wire6(8);
+	sub_wire2(11, 9)    <= sub_wire6(9);
+	sub_wire2(11, 10)    <= sub_wire6(10);
+	sub_wire2(11, 11)    <= sub_wire6(11);
+	sub_wire2(11, 12)    <= sub_wire6(12);
+	sub_wire2(11, 13)    <= sub_wire6(13);
+	sub_wire2(11, 14)    <= sub_wire6(14);
+	sub_wire2(11, 15)    <= sub_wire6(15);
+	sub_wire2(11, 16)    <= sub_wire6(16);
+	sub_wire2(11, 17)    <= sub_wire6(17);
+	sub_wire2(11, 18)    <= sub_wire6(18);
+	sub_wire2(11, 19)    <= sub_wire6(19);
+	sub_wire2(11, 20)    <= sub_wire6(20);
+	sub_wire2(11, 21)    <= sub_wire6(21);
+	sub_wire2(11, 22)    <= sub_wire6(22);
+	sub_wire2(11, 23)    <= sub_wire6(23);
+	sub_wire2(11, 24)    <= sub_wire6(24);
+	sub_wire2(11, 25)    <= sub_wire6(25);
+	sub_wire2(11, 26)    <= sub_wire6(26);
+	sub_wire2(11, 27)    <= sub_wire6(27);
+	sub_wire2(11, 28)    <= sub_wire6(28);
+	sub_wire2(11, 29)    <= sub_wire6(29);
+	sub_wire2(11, 30)    <= sub_wire6(30);
+	sub_wire2(11, 31)    <= sub_wire6(31);
+	sub_wire2(11, 32)    <= sub_wire6(32);
+	sub_wire2(11, 33)    <= sub_wire6(33);
+	sub_wire2(11, 34)    <= sub_wire6(34);
+	sub_wire2(11, 35)    <= sub_wire6(35);
+	sub_wire2(11, 36)    <= sub_wire6(36);
+	sub_wire2(11, 37)    <= sub_wire6(37);
+	sub_wire2(11, 38)    <= sub_wire6(38);
+	sub_wire2(11, 39)    <= sub_wire6(39);
+	sub_wire2(11, 40)    <= sub_wire6(40);
+	sub_wire2(11, 41)    <= sub_wire6(41);
+	sub_wire2(11, 42)    <= sub_wire6(42);
+	sub_wire2(11, 43)    <= sub_wire6(43);
+	sub_wire2(11, 44)    <= sub_wire6(44);
+	sub_wire2(11, 45)    <= sub_wire6(45);
+	sub_wire2(11, 46)    <= sub_wire6(46);
+	sub_wire2(11, 47)    <= sub_wire6(47);
+	sub_wire2(11, 48)    <= sub_wire6(48);
+	sub_wire2(11, 49)    <= sub_wire6(49);
+	sub_wire2(11, 50)    <= sub_wire6(50);
+	sub_wire2(11, 51)    <= sub_wire6(51);
+	sub_wire2(11, 52)    <= sub_wire6(52);
+	sub_wire2(11, 53)    <= sub_wire6(53);
+	sub_wire2(11, 54)    <= sub_wire6(54);
+	sub_wire2(11, 55)    <= sub_wire6(55);
+	sub_wire2(11, 56)    <= sub_wire6(56);
+	sub_wire2(11, 57)    <= sub_wire6(57);
+	sub_wire2(11, 58)    <= sub_wire6(58);
+	sub_wire2(11, 59)    <= sub_wire6(59);
+	sub_wire2(11, 60)    <= sub_wire6(60);
+	sub_wire2(11, 61)    <= sub_wire6(61);
+	sub_wire2(11, 62)    <= sub_wire6(62);
+	sub_wire2(11, 63)    <= sub_wire6(63);
+	sub_wire2(11, 64)    <= sub_wire6(64);
+	sub_wire2(11, 65)    <= sub_wire6(65);
+	sub_wire2(11, 66)    <= sub_wire6(66);
+	sub_wire2(11, 67)    <= sub_wire6(67);
+	sub_wire2(11, 68)    <= sub_wire6(68);
+	sub_wire2(11, 69)    <= sub_wire6(69);
+	sub_wire2(11, 70)    <= sub_wire6(70);
+	sub_wire2(11, 71)    <= sub_wire6(71);
+	sub_wire2(11, 72)    <= sub_wire6(72);
+	sub_wire2(11, 73)    <= sub_wire6(73);
+	sub_wire2(11, 74)    <= sub_wire6(74);
+	sub_wire2(11, 75)    <= sub_wire6(75);
+	sub_wire2(11, 76)    <= sub_wire6(76);
+	sub_wire2(11, 77)    <= sub_wire6(77);
+	sub_wire2(11, 78)    <= sub_wire6(78);
+	sub_wire2(11, 79)    <= sub_wire6(79);
+	sub_wire2(11, 80)    <= sub_wire6(80);
+	sub_wire2(11, 81)    <= sub_wire6(81);
+	sub_wire2(11, 82)    <= sub_wire6(82);
+	sub_wire2(11, 83)    <= sub_wire6(83);
+	sub_wire2(11, 84)    <= sub_wire6(84);
+	sub_wire2(11, 85)    <= sub_wire6(85);
+	sub_wire2(11, 86)    <= sub_wire6(86);
+	sub_wire2(11, 87)    <= sub_wire6(87);
+	sub_wire2(11, 88)    <= sub_wire6(88);
+	sub_wire2(11, 89)    <= sub_wire6(89);
+	sub_wire2(11, 90)    <= sub_wire6(90);
+	sub_wire2(11, 91)    <= sub_wire6(91);
+	sub_wire2(11, 92)    <= sub_wire6(92);
+	sub_wire2(11, 93)    <= sub_wire6(93);
+	sub_wire2(11, 94)    <= sub_wire6(94);
+	sub_wire2(11, 95)    <= sub_wire6(95);
+	sub_wire2(11, 96)    <= sub_wire6(96);
+	sub_wire2(11, 97)    <= sub_wire6(97);
+	sub_wire2(11, 98)    <= sub_wire6(98);
+	sub_wire2(11, 99)    <= sub_wire6(99);
+	sub_wire2(11, 100)    <= sub_wire6(100);
+	sub_wire2(11, 101)    <= sub_wire6(101);
+	sub_wire2(11, 102)    <= sub_wire6(102);
+	sub_wire2(11, 103)    <= sub_wire6(103);
+	sub_wire2(11, 104)    <= sub_wire6(104);
+	sub_wire2(11, 105)    <= sub_wire6(105);
+	sub_wire2(11, 106)    <= sub_wire6(106);
+	sub_wire2(11, 107)    <= sub_wire6(107);
+	sub_wire2(11, 108)    <= sub_wire6(108);
+	sub_wire2(11, 109)    <= sub_wire6(109);
+	sub_wire2(11, 110)    <= sub_wire6(110);
+	sub_wire2(11, 111)    <= sub_wire6(111);
+	sub_wire2(11, 112)    <= sub_wire6(112);
+	sub_wire2(11, 113)    <= sub_wire6(113);
+	sub_wire2(11, 114)    <= sub_wire6(114);
+	sub_wire2(11, 115)    <= sub_wire6(115);
+	sub_wire2(11, 116)    <= sub_wire6(116);
+	sub_wire2(11, 117)    <= sub_wire6(117);
+	sub_wire2(11, 118)    <= sub_wire6(118);
+	sub_wire2(11, 119)    <= sub_wire6(119);
+	sub_wire2(11, 120)    <= sub_wire6(120);
+	sub_wire2(11, 121)    <= sub_wire6(121);
+	sub_wire2(11, 122)    <= sub_wire6(122);
+	sub_wire2(11, 123)    <= sub_wire6(123);
+	sub_wire2(11, 124)    <= sub_wire6(124);
+	sub_wire2(11, 125)    <= sub_wire6(125);
+	sub_wire2(11, 126)    <= sub_wire6(126);
+	sub_wire2(11, 127)    <= sub_wire6(127);
+	sub_wire2(10, 0)    <= sub_wire7(0);
+	sub_wire2(10, 1)    <= sub_wire7(1);
+	sub_wire2(10, 2)    <= sub_wire7(2);
+	sub_wire2(10, 3)    <= sub_wire7(3);
+	sub_wire2(10, 4)    <= sub_wire7(4);
+	sub_wire2(10, 5)    <= sub_wire7(5);
+	sub_wire2(10, 6)    <= sub_wire7(6);
+	sub_wire2(10, 7)    <= sub_wire7(7);
+	sub_wire2(10, 8)    <= sub_wire7(8);
+	sub_wire2(10, 9)    <= sub_wire7(9);
+	sub_wire2(10, 10)    <= sub_wire7(10);
+	sub_wire2(10, 11)    <= sub_wire7(11);
+	sub_wire2(10, 12)    <= sub_wire7(12);
+	sub_wire2(10, 13)    <= sub_wire7(13);
+	sub_wire2(10, 14)    <= sub_wire7(14);
+	sub_wire2(10, 15)    <= sub_wire7(15);
+	sub_wire2(10, 16)    <= sub_wire7(16);
+	sub_wire2(10, 17)    <= sub_wire7(17);
+	sub_wire2(10, 18)    <= sub_wire7(18);
+	sub_wire2(10, 19)    <= sub_wire7(19);
+	sub_wire2(10, 20)    <= sub_wire7(20);
+	sub_wire2(10, 21)    <= sub_wire7(21);
+	sub_wire2(10, 22)    <= sub_wire7(22);
+	sub_wire2(10, 23)    <= sub_wire7(23);
+	sub_wire2(10, 24)    <= sub_wire7(24);
+	sub_wire2(10, 25)    <= sub_wire7(25);
+	sub_wire2(10, 26)    <= sub_wire7(26);
+	sub_wire2(10, 27)    <= sub_wire7(27);
+	sub_wire2(10, 28)    <= sub_wire7(28);
+	sub_wire2(10, 29)    <= sub_wire7(29);
+	sub_wire2(10, 30)    <= sub_wire7(30);
+	sub_wire2(10, 31)    <= sub_wire7(31);
+	sub_wire2(10, 32)    <= sub_wire7(32);
+	sub_wire2(10, 33)    <= sub_wire7(33);
+	sub_wire2(10, 34)    <= sub_wire7(34);
+	sub_wire2(10, 35)    <= sub_wire7(35);
+	sub_wire2(10, 36)    <= sub_wire7(36);
+	sub_wire2(10, 37)    <= sub_wire7(37);
+	sub_wire2(10, 38)    <= sub_wire7(38);
+	sub_wire2(10, 39)    <= sub_wire7(39);
+	sub_wire2(10, 40)    <= sub_wire7(40);
+	sub_wire2(10, 41)    <= sub_wire7(41);
+	sub_wire2(10, 42)    <= sub_wire7(42);
+	sub_wire2(10, 43)    <= sub_wire7(43);
+	sub_wire2(10, 44)    <= sub_wire7(44);
+	sub_wire2(10, 45)    <= sub_wire7(45);
+	sub_wire2(10, 46)    <= sub_wire7(46);
+	sub_wire2(10, 47)    <= sub_wire7(47);
+	sub_wire2(10, 48)    <= sub_wire7(48);
+	sub_wire2(10, 49)    <= sub_wire7(49);
+	sub_wire2(10, 50)    <= sub_wire7(50);
+	sub_wire2(10, 51)    <= sub_wire7(51);
+	sub_wire2(10, 52)    <= sub_wire7(52);
+	sub_wire2(10, 53)    <= sub_wire7(53);
+	sub_wire2(10, 54)    <= sub_wire7(54);
+	sub_wire2(10, 55)    <= sub_wire7(55);
+	sub_wire2(10, 56)    <= sub_wire7(56);
+	sub_wire2(10, 57)    <= sub_wire7(57);
+	sub_wire2(10, 58)    <= sub_wire7(58);
+	sub_wire2(10, 59)    <= sub_wire7(59);
+	sub_wire2(10, 60)    <= sub_wire7(60);
+	sub_wire2(10, 61)    <= sub_wire7(61);
+	sub_wire2(10, 62)    <= sub_wire7(62);
+	sub_wire2(10, 63)    <= sub_wire7(63);
+	sub_wire2(10, 64)    <= sub_wire7(64);
+	sub_wire2(10, 65)    <= sub_wire7(65);
+	sub_wire2(10, 66)    <= sub_wire7(66);
+	sub_wire2(10, 67)    <= sub_wire7(67);
+	sub_wire2(10, 68)    <= sub_wire7(68);
+	sub_wire2(10, 69)    <= sub_wire7(69);
+	sub_wire2(10, 70)    <= sub_wire7(70);
+	sub_wire2(10, 71)    <= sub_wire7(71);
+	sub_wire2(10, 72)    <= sub_wire7(72);
+	sub_wire2(10, 73)    <= sub_wire7(73);
+	sub_wire2(10, 74)    <= sub_wire7(74);
+	sub_wire2(10, 75)    <= sub_wire7(75);
+	sub_wire2(10, 76)    <= sub_wire7(76);
+	sub_wire2(10, 77)    <= sub_wire7(77);
+	sub_wire2(10, 78)    <= sub_wire7(78);
+	sub_wire2(10, 79)    <= sub_wire7(79);
+	sub_wire2(10, 80)    <= sub_wire7(80);
+	sub_wire2(10, 81)    <= sub_wire7(81);
+	sub_wire2(10, 82)    <= sub_wire7(82);
+	sub_wire2(10, 83)    <= sub_wire7(83);
+	sub_wire2(10, 84)    <= sub_wire7(84);
+	sub_wire2(10, 85)    <= sub_wire7(85);
+	sub_wire2(10, 86)    <= sub_wire7(86);
+	sub_wire2(10, 87)    <= sub_wire7(87);
+	sub_wire2(10, 88)    <= sub_wire7(88);
+	sub_wire2(10, 89)    <= sub_wire7(89);
+	sub_wire2(10, 90)    <= sub_wire7(90);
+	sub_wire2(10, 91)    <= sub_wire7(91);
+	sub_wire2(10, 92)    <= sub_wire7(92);
+	sub_wire2(10, 93)    <= sub_wire7(93);
+	sub_wire2(10, 94)    <= sub_wire7(94);
+	sub_wire2(10, 95)    <= sub_wire7(95);
+	sub_wire2(10, 96)    <= sub_wire7(96);
+	sub_wire2(10, 97)    <= sub_wire7(97);
+	sub_wire2(10, 98)    <= sub_wire7(98);
+	sub_wire2(10, 99)    <= sub_wire7(99);
+	sub_wire2(10, 100)    <= sub_wire7(100);
+	sub_wire2(10, 101)    <= sub_wire7(101);
+	sub_wire2(10, 102)    <= sub_wire7(102);
+	sub_wire2(10, 103)    <= sub_wire7(103);
+	sub_wire2(10, 104)    <= sub_wire7(104);
+	sub_wire2(10, 105)    <= sub_wire7(105);
+	sub_wire2(10, 106)    <= sub_wire7(106);
+	sub_wire2(10, 107)    <= sub_wire7(107);
+	sub_wire2(10, 108)    <= sub_wire7(108);
+	sub_wire2(10, 109)    <= sub_wire7(109);
+	sub_wire2(10, 110)    <= sub_wire7(110);
+	sub_wire2(10, 111)    <= sub_wire7(111);
+	sub_wire2(10, 112)    <= sub_wire7(112);
+	sub_wire2(10, 113)    <= sub_wire7(113);
+	sub_wire2(10, 114)    <= sub_wire7(114);
+	sub_wire2(10, 115)    <= sub_wire7(115);
+	sub_wire2(10, 116)    <= sub_wire7(116);
+	sub_wire2(10, 117)    <= sub_wire7(117);
+	sub_wire2(10, 118)    <= sub_wire7(118);
+	sub_wire2(10, 119)    <= sub_wire7(119);
+	sub_wire2(10, 120)    <= sub_wire7(120);
+	sub_wire2(10, 121)    <= sub_wire7(121);
+	sub_wire2(10, 122)    <= sub_wire7(122);
+	sub_wire2(10, 123)    <= sub_wire7(123);
+	sub_wire2(10, 124)    <= sub_wire7(124);
+	sub_wire2(10, 125)    <= sub_wire7(125);
+	sub_wire2(10, 126)    <= sub_wire7(126);
+	sub_wire2(10, 127)    <= sub_wire7(127);
+	sub_wire2(9, 0)    <= sub_wire8(0);
+	sub_wire2(9, 1)    <= sub_wire8(1);
+	sub_wire2(9, 2)    <= sub_wire8(2);
+	sub_wire2(9, 3)    <= sub_wire8(3);
+	sub_wire2(9, 4)    <= sub_wire8(4);
+	sub_wire2(9, 5)    <= sub_wire8(5);
+	sub_wire2(9, 6)    <= sub_wire8(6);
+	sub_wire2(9, 7)    <= sub_wire8(7);
+	sub_wire2(9, 8)    <= sub_wire8(8);
+	sub_wire2(9, 9)    <= sub_wire8(9);
+	sub_wire2(9, 10)    <= sub_wire8(10);
+	sub_wire2(9, 11)    <= sub_wire8(11);
+	sub_wire2(9, 12)    <= sub_wire8(12);
+	sub_wire2(9, 13)    <= sub_wire8(13);
+	sub_wire2(9, 14)    <= sub_wire8(14);
+	sub_wire2(9, 15)    <= sub_wire8(15);
+	sub_wire2(9, 16)    <= sub_wire8(16);
+	sub_wire2(9, 17)    <= sub_wire8(17);
+	sub_wire2(9, 18)    <= sub_wire8(18);
+	sub_wire2(9, 19)    <= sub_wire8(19);
+	sub_wire2(9, 20)    <= sub_wire8(20);
+	sub_wire2(9, 21)    <= sub_wire8(21);
+	sub_wire2(9, 22)    <= sub_wire8(22);
+	sub_wire2(9, 23)    <= sub_wire8(23);
+	sub_wire2(9, 24)    <= sub_wire8(24);
+	sub_wire2(9, 25)    <= sub_wire8(25);
+	sub_wire2(9, 26)    <= sub_wire8(26);
+	sub_wire2(9, 27)    <= sub_wire8(27);
+	sub_wire2(9, 28)    <= sub_wire8(28);
+	sub_wire2(9, 29)    <= sub_wire8(29);
+	sub_wire2(9, 30)    <= sub_wire8(30);
+	sub_wire2(9, 31)    <= sub_wire8(31);
+	sub_wire2(9, 32)    <= sub_wire8(32);
+	sub_wire2(9, 33)    <= sub_wire8(33);
+	sub_wire2(9, 34)    <= sub_wire8(34);
+	sub_wire2(9, 35)    <= sub_wire8(35);
+	sub_wire2(9, 36)    <= sub_wire8(36);
+	sub_wire2(9, 37)    <= sub_wire8(37);
+	sub_wire2(9, 38)    <= sub_wire8(38);
+	sub_wire2(9, 39)    <= sub_wire8(39);
+	sub_wire2(9, 40)    <= sub_wire8(40);
+	sub_wire2(9, 41)    <= sub_wire8(41);
+	sub_wire2(9, 42)    <= sub_wire8(42);
+	sub_wire2(9, 43)    <= sub_wire8(43);
+	sub_wire2(9, 44)    <= sub_wire8(44);
+	sub_wire2(9, 45)    <= sub_wire8(45);
+	sub_wire2(9, 46)    <= sub_wire8(46);
+	sub_wire2(9, 47)    <= sub_wire8(47);
+	sub_wire2(9, 48)    <= sub_wire8(48);
+	sub_wire2(9, 49)    <= sub_wire8(49);
+	sub_wire2(9, 50)    <= sub_wire8(50);
+	sub_wire2(9, 51)    <= sub_wire8(51);
+	sub_wire2(9, 52)    <= sub_wire8(52);
+	sub_wire2(9, 53)    <= sub_wire8(53);
+	sub_wire2(9, 54)    <= sub_wire8(54);
+	sub_wire2(9, 55)    <= sub_wire8(55);
+	sub_wire2(9, 56)    <= sub_wire8(56);
+	sub_wire2(9, 57)    <= sub_wire8(57);
+	sub_wire2(9, 58)    <= sub_wire8(58);
+	sub_wire2(9, 59)    <= sub_wire8(59);
+	sub_wire2(9, 60)    <= sub_wire8(60);
+	sub_wire2(9, 61)    <= sub_wire8(61);
+	sub_wire2(9, 62)    <= sub_wire8(62);
+	sub_wire2(9, 63)    <= sub_wire8(63);
+	sub_wire2(9, 64)    <= sub_wire8(64);
+	sub_wire2(9, 65)    <= sub_wire8(65);
+	sub_wire2(9, 66)    <= sub_wire8(66);
+	sub_wire2(9, 67)    <= sub_wire8(67);
+	sub_wire2(9, 68)    <= sub_wire8(68);
+	sub_wire2(9, 69)    <= sub_wire8(69);
+	sub_wire2(9, 70)    <= sub_wire8(70);
+	sub_wire2(9, 71)    <= sub_wire8(71);
+	sub_wire2(9, 72)    <= sub_wire8(72);
+	sub_wire2(9, 73)    <= sub_wire8(73);
+	sub_wire2(9, 74)    <= sub_wire8(74);
+	sub_wire2(9, 75)    <= sub_wire8(75);
+	sub_wire2(9, 76)    <= sub_wire8(76);
+	sub_wire2(9, 77)    <= sub_wire8(77);
+	sub_wire2(9, 78)    <= sub_wire8(78);
+	sub_wire2(9, 79)    <= sub_wire8(79);
+	sub_wire2(9, 80)    <= sub_wire8(80);
+	sub_wire2(9, 81)    <= sub_wire8(81);
+	sub_wire2(9, 82)    <= sub_wire8(82);
+	sub_wire2(9, 83)    <= sub_wire8(83);
+	sub_wire2(9, 84)    <= sub_wire8(84);
+	sub_wire2(9, 85)    <= sub_wire8(85);
+	sub_wire2(9, 86)    <= sub_wire8(86);
+	sub_wire2(9, 87)    <= sub_wire8(87);
+	sub_wire2(9, 88)    <= sub_wire8(88);
+	sub_wire2(9, 89)    <= sub_wire8(89);
+	sub_wire2(9, 90)    <= sub_wire8(90);
+	sub_wire2(9, 91)    <= sub_wire8(91);
+	sub_wire2(9, 92)    <= sub_wire8(92);
+	sub_wire2(9, 93)    <= sub_wire8(93);
+	sub_wire2(9, 94)    <= sub_wire8(94);
+	sub_wire2(9, 95)    <= sub_wire8(95);
+	sub_wire2(9, 96)    <= sub_wire8(96);
+	sub_wire2(9, 97)    <= sub_wire8(97);
+	sub_wire2(9, 98)    <= sub_wire8(98);
+	sub_wire2(9, 99)    <= sub_wire8(99);
+	sub_wire2(9, 100)    <= sub_wire8(100);
+	sub_wire2(9, 101)    <= sub_wire8(101);
+	sub_wire2(9, 102)    <= sub_wire8(102);
+	sub_wire2(9, 103)    <= sub_wire8(103);
+	sub_wire2(9, 104)    <= sub_wire8(104);
+	sub_wire2(9, 105)    <= sub_wire8(105);
+	sub_wire2(9, 106)    <= sub_wire8(106);
+	sub_wire2(9, 107)    <= sub_wire8(107);
+	sub_wire2(9, 108)    <= sub_wire8(108);
+	sub_wire2(9, 109)    <= sub_wire8(109);
+	sub_wire2(9, 110)    <= sub_wire8(110);
+	sub_wire2(9, 111)    <= sub_wire8(111);
+	sub_wire2(9, 112)    <= sub_wire8(112);
+	sub_wire2(9, 113)    <= sub_wire8(113);
+	sub_wire2(9, 114)    <= sub_wire8(114);
+	sub_wire2(9, 115)    <= sub_wire8(115);
+	sub_wire2(9, 116)    <= sub_wire8(116);
+	sub_wire2(9, 117)    <= sub_wire8(117);
+	sub_wire2(9, 118)    <= sub_wire8(118);
+	sub_wire2(9, 119)    <= sub_wire8(119);
+	sub_wire2(9, 120)    <= sub_wire8(120);
+	sub_wire2(9, 121)    <= sub_wire8(121);
+	sub_wire2(9, 122)    <= sub_wire8(122);
+	sub_wire2(9, 123)    <= sub_wire8(123);
+	sub_wire2(9, 124)    <= sub_wire8(124);
+	sub_wire2(9, 125)    <= sub_wire8(125);
+	sub_wire2(9, 126)    <= sub_wire8(126);
+	sub_wire2(9, 127)    <= sub_wire8(127);
+	sub_wire2(8, 0)    <= sub_wire9(0);
+	sub_wire2(8, 1)    <= sub_wire9(1);
+	sub_wire2(8, 2)    <= sub_wire9(2);
+	sub_wire2(8, 3)    <= sub_wire9(3);
+	sub_wire2(8, 4)    <= sub_wire9(4);
+	sub_wire2(8, 5)    <= sub_wire9(5);
+	sub_wire2(8, 6)    <= sub_wire9(6);
+	sub_wire2(8, 7)    <= sub_wire9(7);
+	sub_wire2(8, 8)    <= sub_wire9(8);
+	sub_wire2(8, 9)    <= sub_wire9(9);
+	sub_wire2(8, 10)    <= sub_wire9(10);
+	sub_wire2(8, 11)    <= sub_wire9(11);
+	sub_wire2(8, 12)    <= sub_wire9(12);
+	sub_wire2(8, 13)    <= sub_wire9(13);
+	sub_wire2(8, 14)    <= sub_wire9(14);
+	sub_wire2(8, 15)    <= sub_wire9(15);
+	sub_wire2(8, 16)    <= sub_wire9(16);
+	sub_wire2(8, 17)    <= sub_wire9(17);
+	sub_wire2(8, 18)    <= sub_wire9(18);
+	sub_wire2(8, 19)    <= sub_wire9(19);
+	sub_wire2(8, 20)    <= sub_wire9(20);
+	sub_wire2(8, 21)    <= sub_wire9(21);
+	sub_wire2(8, 22)    <= sub_wire9(22);
+	sub_wire2(8, 23)    <= sub_wire9(23);
+	sub_wire2(8, 24)    <= sub_wire9(24);
+	sub_wire2(8, 25)    <= sub_wire9(25);
+	sub_wire2(8, 26)    <= sub_wire9(26);
+	sub_wire2(8, 27)    <= sub_wire9(27);
+	sub_wire2(8, 28)    <= sub_wire9(28);
+	sub_wire2(8, 29)    <= sub_wire9(29);
+	sub_wire2(8, 30)    <= sub_wire9(30);
+	sub_wire2(8, 31)    <= sub_wire9(31);
+	sub_wire2(8, 32)    <= sub_wire9(32);
+	sub_wire2(8, 33)    <= sub_wire9(33);
+	sub_wire2(8, 34)    <= sub_wire9(34);
+	sub_wire2(8, 35)    <= sub_wire9(35);
+	sub_wire2(8, 36)    <= sub_wire9(36);
+	sub_wire2(8, 37)    <= sub_wire9(37);
+	sub_wire2(8, 38)    <= sub_wire9(38);
+	sub_wire2(8, 39)    <= sub_wire9(39);
+	sub_wire2(8, 40)    <= sub_wire9(40);
+	sub_wire2(8, 41)    <= sub_wire9(41);
+	sub_wire2(8, 42)    <= sub_wire9(42);
+	sub_wire2(8, 43)    <= sub_wire9(43);
+	sub_wire2(8, 44)    <= sub_wire9(44);
+	sub_wire2(8, 45)    <= sub_wire9(45);
+	sub_wire2(8, 46)    <= sub_wire9(46);
+	sub_wire2(8, 47)    <= sub_wire9(47);
+	sub_wire2(8, 48)    <= sub_wire9(48);
+	sub_wire2(8, 49)    <= sub_wire9(49);
+	sub_wire2(8, 50)    <= sub_wire9(50);
+	sub_wire2(8, 51)    <= sub_wire9(51);
+	sub_wire2(8, 52)    <= sub_wire9(52);
+	sub_wire2(8, 53)    <= sub_wire9(53);
+	sub_wire2(8, 54)    <= sub_wire9(54);
+	sub_wire2(8, 55)    <= sub_wire9(55);
+	sub_wire2(8, 56)    <= sub_wire9(56);
+	sub_wire2(8, 57)    <= sub_wire9(57);
+	sub_wire2(8, 58)    <= sub_wire9(58);
+	sub_wire2(8, 59)    <= sub_wire9(59);
+	sub_wire2(8, 60)    <= sub_wire9(60);
+	sub_wire2(8, 61)    <= sub_wire9(61);
+	sub_wire2(8, 62)    <= sub_wire9(62);
+	sub_wire2(8, 63)    <= sub_wire9(63);
+	sub_wire2(8, 64)    <= sub_wire9(64);
+	sub_wire2(8, 65)    <= sub_wire9(65);
+	sub_wire2(8, 66)    <= sub_wire9(66);
+	sub_wire2(8, 67)    <= sub_wire9(67);
+	sub_wire2(8, 68)    <= sub_wire9(68);
+	sub_wire2(8, 69)    <= sub_wire9(69);
+	sub_wire2(8, 70)    <= sub_wire9(70);
+	sub_wire2(8, 71)    <= sub_wire9(71);
+	sub_wire2(8, 72)    <= sub_wire9(72);
+	sub_wire2(8, 73)    <= sub_wire9(73);
+	sub_wire2(8, 74)    <= sub_wire9(74);
+	sub_wire2(8, 75)    <= sub_wire9(75);
+	sub_wire2(8, 76)    <= sub_wire9(76);
+	sub_wire2(8, 77)    <= sub_wire9(77);
+	sub_wire2(8, 78)    <= sub_wire9(78);
+	sub_wire2(8, 79)    <= sub_wire9(79);
+	sub_wire2(8, 80)    <= sub_wire9(80);
+	sub_wire2(8, 81)    <= sub_wire9(81);
+	sub_wire2(8, 82)    <= sub_wire9(82);
+	sub_wire2(8, 83)    <= sub_wire9(83);
+	sub_wire2(8, 84)    <= sub_wire9(84);
+	sub_wire2(8, 85)    <= sub_wire9(85);
+	sub_wire2(8, 86)    <= sub_wire9(86);
+	sub_wire2(8, 87)    <= sub_wire9(87);
+	sub_wire2(8, 88)    <= sub_wire9(88);
+	sub_wire2(8, 89)    <= sub_wire9(89);
+	sub_wire2(8, 90)    <= sub_wire9(90);
+	sub_wire2(8, 91)    <= sub_wire9(91);
+	sub_wire2(8, 92)    <= sub_wire9(92);
+	sub_wire2(8, 93)    <= sub_wire9(93);
+	sub_wire2(8, 94)    <= sub_wire9(94);
+	sub_wire2(8, 95)    <= sub_wire9(95);
+	sub_wire2(8, 96)    <= sub_wire9(96);
+	sub_wire2(8, 97)    <= sub_wire9(97);
+	sub_wire2(8, 98)    <= sub_wire9(98);
+	sub_wire2(8, 99)    <= sub_wire9(99);
+	sub_wire2(8, 100)    <= sub_wire9(100);
+	sub_wire2(8, 101)    <= sub_wire9(101);
+	sub_wire2(8, 102)    <= sub_wire9(102);
+	sub_wire2(8, 103)    <= sub_wire9(103);
+	sub_wire2(8, 104)    <= sub_wire9(104);
+	sub_wire2(8, 105)    <= sub_wire9(105);
+	sub_wire2(8, 106)    <= sub_wire9(106);
+	sub_wire2(8, 107)    <= sub_wire9(107);
+	sub_wire2(8, 108)    <= sub_wire9(108);
+	sub_wire2(8, 109)    <= sub_wire9(109);
+	sub_wire2(8, 110)    <= sub_wire9(110);
+	sub_wire2(8, 111)    <= sub_wire9(111);
+	sub_wire2(8, 112)    <= sub_wire9(112);
+	sub_wire2(8, 113)    <= sub_wire9(113);
+	sub_wire2(8, 114)    <= sub_wire9(114);
+	sub_wire2(8, 115)    <= sub_wire9(115);
+	sub_wire2(8, 116)    <= sub_wire9(116);
+	sub_wire2(8, 117)    <= sub_wire9(117);
+	sub_wire2(8, 118)    <= sub_wire9(118);
+	sub_wire2(8, 119)    <= sub_wire9(119);
+	sub_wire2(8, 120)    <= sub_wire9(120);
+	sub_wire2(8, 121)    <= sub_wire9(121);
+	sub_wire2(8, 122)    <= sub_wire9(122);
+	sub_wire2(8, 123)    <= sub_wire9(123);
+	sub_wire2(8, 124)    <= sub_wire9(124);
+	sub_wire2(8, 125)    <= sub_wire9(125);
+	sub_wire2(8, 126)    <= sub_wire9(126);
+	sub_wire2(8, 127)    <= sub_wire9(127);
+	sub_wire2(7, 0)    <= sub_wire10(0);
+	sub_wire2(7, 1)    <= sub_wire10(1);
+	sub_wire2(7, 2)    <= sub_wire10(2);
+	sub_wire2(7, 3)    <= sub_wire10(3);
+	sub_wire2(7, 4)    <= sub_wire10(4);
+	sub_wire2(7, 5)    <= sub_wire10(5);
+	sub_wire2(7, 6)    <= sub_wire10(6);
+	sub_wire2(7, 7)    <= sub_wire10(7);
+	sub_wire2(7, 8)    <= sub_wire10(8);
+	sub_wire2(7, 9)    <= sub_wire10(9);
+	sub_wire2(7, 10)    <= sub_wire10(10);
+	sub_wire2(7, 11)    <= sub_wire10(11);
+	sub_wire2(7, 12)    <= sub_wire10(12);
+	sub_wire2(7, 13)    <= sub_wire10(13);
+	sub_wire2(7, 14)    <= sub_wire10(14);
+	sub_wire2(7, 15)    <= sub_wire10(15);
+	sub_wire2(7, 16)    <= sub_wire10(16);
+	sub_wire2(7, 17)    <= sub_wire10(17);
+	sub_wire2(7, 18)    <= sub_wire10(18);
+	sub_wire2(7, 19)    <= sub_wire10(19);
+	sub_wire2(7, 20)    <= sub_wire10(20);
+	sub_wire2(7, 21)    <= sub_wire10(21);
+	sub_wire2(7, 22)    <= sub_wire10(22);
+	sub_wire2(7, 23)    <= sub_wire10(23);
+	sub_wire2(7, 24)    <= sub_wire10(24);
+	sub_wire2(7, 25)    <= sub_wire10(25);
+	sub_wire2(7, 26)    <= sub_wire10(26);
+	sub_wire2(7, 27)    <= sub_wire10(27);
+	sub_wire2(7, 28)    <= sub_wire10(28);
+	sub_wire2(7, 29)    <= sub_wire10(29);
+	sub_wire2(7, 30)    <= sub_wire10(30);
+	sub_wire2(7, 31)    <= sub_wire10(31);
+	sub_wire2(7, 32)    <= sub_wire10(32);
+	sub_wire2(7, 33)    <= sub_wire10(33);
+	sub_wire2(7, 34)    <= sub_wire10(34);
+	sub_wire2(7, 35)    <= sub_wire10(35);
+	sub_wire2(7, 36)    <= sub_wire10(36);
+	sub_wire2(7, 37)    <= sub_wire10(37);
+	sub_wire2(7, 38)    <= sub_wire10(38);
+	sub_wire2(7, 39)    <= sub_wire10(39);
+	sub_wire2(7, 40)    <= sub_wire10(40);
+	sub_wire2(7, 41)    <= sub_wire10(41);
+	sub_wire2(7, 42)    <= sub_wire10(42);
+	sub_wire2(7, 43)    <= sub_wire10(43);
+	sub_wire2(7, 44)    <= sub_wire10(44);
+	sub_wire2(7, 45)    <= sub_wire10(45);
+	sub_wire2(7, 46)    <= sub_wire10(46);
+	sub_wire2(7, 47)    <= sub_wire10(47);
+	sub_wire2(7, 48)    <= sub_wire10(48);
+	sub_wire2(7, 49)    <= sub_wire10(49);
+	sub_wire2(7, 50)    <= sub_wire10(50);
+	sub_wire2(7, 51)    <= sub_wire10(51);
+	sub_wire2(7, 52)    <= sub_wire10(52);
+	sub_wire2(7, 53)    <= sub_wire10(53);
+	sub_wire2(7, 54)    <= sub_wire10(54);
+	sub_wire2(7, 55)    <= sub_wire10(55);
+	sub_wire2(7, 56)    <= sub_wire10(56);
+	sub_wire2(7, 57)    <= sub_wire10(57);
+	sub_wire2(7, 58)    <= sub_wire10(58);
+	sub_wire2(7, 59)    <= sub_wire10(59);
+	sub_wire2(7, 60)    <= sub_wire10(60);
+	sub_wire2(7, 61)    <= sub_wire10(61);
+	sub_wire2(7, 62)    <= sub_wire10(62);
+	sub_wire2(7, 63)    <= sub_wire10(63);
+	sub_wire2(7, 64)    <= sub_wire10(64);
+	sub_wire2(7, 65)    <= sub_wire10(65);
+	sub_wire2(7, 66)    <= sub_wire10(66);
+	sub_wire2(7, 67)    <= sub_wire10(67);
+	sub_wire2(7, 68)    <= sub_wire10(68);
+	sub_wire2(7, 69)    <= sub_wire10(69);
+	sub_wire2(7, 70)    <= sub_wire10(70);
+	sub_wire2(7, 71)    <= sub_wire10(71);
+	sub_wire2(7, 72)    <= sub_wire10(72);
+	sub_wire2(7, 73)    <= sub_wire10(73);
+	sub_wire2(7, 74)    <= sub_wire10(74);
+	sub_wire2(7, 75)    <= sub_wire10(75);
+	sub_wire2(7, 76)    <= sub_wire10(76);
+	sub_wire2(7, 77)    <= sub_wire10(77);
+	sub_wire2(7, 78)    <= sub_wire10(78);
+	sub_wire2(7, 79)    <= sub_wire10(79);
+	sub_wire2(7, 80)    <= sub_wire10(80);
+	sub_wire2(7, 81)    <= sub_wire10(81);
+	sub_wire2(7, 82)    <= sub_wire10(82);
+	sub_wire2(7, 83)    <= sub_wire10(83);
+	sub_wire2(7, 84)    <= sub_wire10(84);
+	sub_wire2(7, 85)    <= sub_wire10(85);
+	sub_wire2(7, 86)    <= sub_wire10(86);
+	sub_wire2(7, 87)    <= sub_wire10(87);
+	sub_wire2(7, 88)    <= sub_wire10(88);
+	sub_wire2(7, 89)    <= sub_wire10(89);
+	sub_wire2(7, 90)    <= sub_wire10(90);
+	sub_wire2(7, 91)    <= sub_wire10(91);
+	sub_wire2(7, 92)    <= sub_wire10(92);
+	sub_wire2(7, 93)    <= sub_wire10(93);
+	sub_wire2(7, 94)    <= sub_wire10(94);
+	sub_wire2(7, 95)    <= sub_wire10(95);
+	sub_wire2(7, 96)    <= sub_wire10(96);
+	sub_wire2(7, 97)    <= sub_wire10(97);
+	sub_wire2(7, 98)    <= sub_wire10(98);
+	sub_wire2(7, 99)    <= sub_wire10(99);
+	sub_wire2(7, 100)    <= sub_wire10(100);
+	sub_wire2(7, 101)    <= sub_wire10(101);
+	sub_wire2(7, 102)    <= sub_wire10(102);
+	sub_wire2(7, 103)    <= sub_wire10(103);
+	sub_wire2(7, 104)    <= sub_wire10(104);
+	sub_wire2(7, 105)    <= sub_wire10(105);
+	sub_wire2(7, 106)    <= sub_wire10(106);
+	sub_wire2(7, 107)    <= sub_wire10(107);
+	sub_wire2(7, 108)    <= sub_wire10(108);
+	sub_wire2(7, 109)    <= sub_wire10(109);
+	sub_wire2(7, 110)    <= sub_wire10(110);
+	sub_wire2(7, 111)    <= sub_wire10(111);
+	sub_wire2(7, 112)    <= sub_wire10(112);
+	sub_wire2(7, 113)    <= sub_wire10(113);
+	sub_wire2(7, 114)    <= sub_wire10(114);
+	sub_wire2(7, 115)    <= sub_wire10(115);
+	sub_wire2(7, 116)    <= sub_wire10(116);
+	sub_wire2(7, 117)    <= sub_wire10(117);
+	sub_wire2(7, 118)    <= sub_wire10(118);
+	sub_wire2(7, 119)    <= sub_wire10(119);
+	sub_wire2(7, 120)    <= sub_wire10(120);
+	sub_wire2(7, 121)    <= sub_wire10(121);
+	sub_wire2(7, 122)    <= sub_wire10(122);
+	sub_wire2(7, 123)    <= sub_wire10(123);
+	sub_wire2(7, 124)    <= sub_wire10(124);
+	sub_wire2(7, 125)    <= sub_wire10(125);
+	sub_wire2(7, 126)    <= sub_wire10(126);
+	sub_wire2(7, 127)    <= sub_wire10(127);
+	sub_wire2(6, 0)    <= sub_wire11(0);
+	sub_wire2(6, 1)    <= sub_wire11(1);
+	sub_wire2(6, 2)    <= sub_wire11(2);
+	sub_wire2(6, 3)    <= sub_wire11(3);
+	sub_wire2(6, 4)    <= sub_wire11(4);
+	sub_wire2(6, 5)    <= sub_wire11(5);
+	sub_wire2(6, 6)    <= sub_wire11(6);
+	sub_wire2(6, 7)    <= sub_wire11(7);
+	sub_wire2(6, 8)    <= sub_wire11(8);
+	sub_wire2(6, 9)    <= sub_wire11(9);
+	sub_wire2(6, 10)    <= sub_wire11(10);
+	sub_wire2(6, 11)    <= sub_wire11(11);
+	sub_wire2(6, 12)    <= sub_wire11(12);
+	sub_wire2(6, 13)    <= sub_wire11(13);
+	sub_wire2(6, 14)    <= sub_wire11(14);
+	sub_wire2(6, 15)    <= sub_wire11(15);
+	sub_wire2(6, 16)    <= sub_wire11(16);
+	sub_wire2(6, 17)    <= sub_wire11(17);
+	sub_wire2(6, 18)    <= sub_wire11(18);
+	sub_wire2(6, 19)    <= sub_wire11(19);
+	sub_wire2(6, 20)    <= sub_wire11(20);
+	sub_wire2(6, 21)    <= sub_wire11(21);
+	sub_wire2(6, 22)    <= sub_wire11(22);
+	sub_wire2(6, 23)    <= sub_wire11(23);
+	sub_wire2(6, 24)    <= sub_wire11(24);
+	sub_wire2(6, 25)    <= sub_wire11(25);
+	sub_wire2(6, 26)    <= sub_wire11(26);
+	sub_wire2(6, 27)    <= sub_wire11(27);
+	sub_wire2(6, 28)    <= sub_wire11(28);
+	sub_wire2(6, 29)    <= sub_wire11(29);
+	sub_wire2(6, 30)    <= sub_wire11(30);
+	sub_wire2(6, 31)    <= sub_wire11(31);
+	sub_wire2(6, 32)    <= sub_wire11(32);
+	sub_wire2(6, 33)    <= sub_wire11(33);
+	sub_wire2(6, 34)    <= sub_wire11(34);
+	sub_wire2(6, 35)    <= sub_wire11(35);
+	sub_wire2(6, 36)    <= sub_wire11(36);
+	sub_wire2(6, 37)    <= sub_wire11(37);
+	sub_wire2(6, 38)    <= sub_wire11(38);
+	sub_wire2(6, 39)    <= sub_wire11(39);
+	sub_wire2(6, 40)    <= sub_wire11(40);
+	sub_wire2(6, 41)    <= sub_wire11(41);
+	sub_wire2(6, 42)    <= sub_wire11(42);
+	sub_wire2(6, 43)    <= sub_wire11(43);
+	sub_wire2(6, 44)    <= sub_wire11(44);
+	sub_wire2(6, 45)    <= sub_wire11(45);
+	sub_wire2(6, 46)    <= sub_wire11(46);
+	sub_wire2(6, 47)    <= sub_wire11(47);
+	sub_wire2(6, 48)    <= sub_wire11(48);
+	sub_wire2(6, 49)    <= sub_wire11(49);
+	sub_wire2(6, 50)    <= sub_wire11(50);
+	sub_wire2(6, 51)    <= sub_wire11(51);
+	sub_wire2(6, 52)    <= sub_wire11(52);
+	sub_wire2(6, 53)    <= sub_wire11(53);
+	sub_wire2(6, 54)    <= sub_wire11(54);
+	sub_wire2(6, 55)    <= sub_wire11(55);
+	sub_wire2(6, 56)    <= sub_wire11(56);
+	sub_wire2(6, 57)    <= sub_wire11(57);
+	sub_wire2(6, 58)    <= sub_wire11(58);
+	sub_wire2(6, 59)    <= sub_wire11(59);
+	sub_wire2(6, 60)    <= sub_wire11(60);
+	sub_wire2(6, 61)    <= sub_wire11(61);
+	sub_wire2(6, 62)    <= sub_wire11(62);
+	sub_wire2(6, 63)    <= sub_wire11(63);
+	sub_wire2(6, 64)    <= sub_wire11(64);
+	sub_wire2(6, 65)    <= sub_wire11(65);
+	sub_wire2(6, 66)    <= sub_wire11(66);
+	sub_wire2(6, 67)    <= sub_wire11(67);
+	sub_wire2(6, 68)    <= sub_wire11(68);
+	sub_wire2(6, 69)    <= sub_wire11(69);
+	sub_wire2(6, 70)    <= sub_wire11(70);
+	sub_wire2(6, 71)    <= sub_wire11(71);
+	sub_wire2(6, 72)    <= sub_wire11(72);
+	sub_wire2(6, 73)    <= sub_wire11(73);
+	sub_wire2(6, 74)    <= sub_wire11(74);
+	sub_wire2(6, 75)    <= sub_wire11(75);
+	sub_wire2(6, 76)    <= sub_wire11(76);
+	sub_wire2(6, 77)    <= sub_wire11(77);
+	sub_wire2(6, 78)    <= sub_wire11(78);
+	sub_wire2(6, 79)    <= sub_wire11(79);
+	sub_wire2(6, 80)    <= sub_wire11(80);
+	sub_wire2(6, 81)    <= sub_wire11(81);
+	sub_wire2(6, 82)    <= sub_wire11(82);
+	sub_wire2(6, 83)    <= sub_wire11(83);
+	sub_wire2(6, 84)    <= sub_wire11(84);
+	sub_wire2(6, 85)    <= sub_wire11(85);
+	sub_wire2(6, 86)    <= sub_wire11(86);
+	sub_wire2(6, 87)    <= sub_wire11(87);
+	sub_wire2(6, 88)    <= sub_wire11(88);
+	sub_wire2(6, 89)    <= sub_wire11(89);
+	sub_wire2(6, 90)    <= sub_wire11(90);
+	sub_wire2(6, 91)    <= sub_wire11(91);
+	sub_wire2(6, 92)    <= sub_wire11(92);
+	sub_wire2(6, 93)    <= sub_wire11(93);
+	sub_wire2(6, 94)    <= sub_wire11(94);
+	sub_wire2(6, 95)    <= sub_wire11(95);
+	sub_wire2(6, 96)    <= sub_wire11(96);
+	sub_wire2(6, 97)    <= sub_wire11(97);
+	sub_wire2(6, 98)    <= sub_wire11(98);
+	sub_wire2(6, 99)    <= sub_wire11(99);
+	sub_wire2(6, 100)    <= sub_wire11(100);
+	sub_wire2(6, 101)    <= sub_wire11(101);
+	sub_wire2(6, 102)    <= sub_wire11(102);
+	sub_wire2(6, 103)    <= sub_wire11(103);
+	sub_wire2(6, 104)    <= sub_wire11(104);
+	sub_wire2(6, 105)    <= sub_wire11(105);
+	sub_wire2(6, 106)    <= sub_wire11(106);
+	sub_wire2(6, 107)    <= sub_wire11(107);
+	sub_wire2(6, 108)    <= sub_wire11(108);
+	sub_wire2(6, 109)    <= sub_wire11(109);
+	sub_wire2(6, 110)    <= sub_wire11(110);
+	sub_wire2(6, 111)    <= sub_wire11(111);
+	sub_wire2(6, 112)    <= sub_wire11(112);
+	sub_wire2(6, 113)    <= sub_wire11(113);
+	sub_wire2(6, 114)    <= sub_wire11(114);
+	sub_wire2(6, 115)    <= sub_wire11(115);
+	sub_wire2(6, 116)    <= sub_wire11(116);
+	sub_wire2(6, 117)    <= sub_wire11(117);
+	sub_wire2(6, 118)    <= sub_wire11(118);
+	sub_wire2(6, 119)    <= sub_wire11(119);
+	sub_wire2(6, 120)    <= sub_wire11(120);
+	sub_wire2(6, 121)    <= sub_wire11(121);
+	sub_wire2(6, 122)    <= sub_wire11(122);
+	sub_wire2(6, 123)    <= sub_wire11(123);
+	sub_wire2(6, 124)    <= sub_wire11(124);
+	sub_wire2(6, 125)    <= sub_wire11(125);
+	sub_wire2(6, 126)    <= sub_wire11(126);
+	sub_wire2(6, 127)    <= sub_wire11(127);
+	sub_wire2(5, 0)    <= sub_wire12(0);
+	sub_wire2(5, 1)    <= sub_wire12(1);
+	sub_wire2(5, 2)    <= sub_wire12(2);
+	sub_wire2(5, 3)    <= sub_wire12(3);
+	sub_wire2(5, 4)    <= sub_wire12(4);
+	sub_wire2(5, 5)    <= sub_wire12(5);
+	sub_wire2(5, 6)    <= sub_wire12(6);
+	sub_wire2(5, 7)    <= sub_wire12(7);
+	sub_wire2(5, 8)    <= sub_wire12(8);
+	sub_wire2(5, 9)    <= sub_wire12(9);
+	sub_wire2(5, 10)    <= sub_wire12(10);
+	sub_wire2(5, 11)    <= sub_wire12(11);
+	sub_wire2(5, 12)    <= sub_wire12(12);
+	sub_wire2(5, 13)    <= sub_wire12(13);
+	sub_wire2(5, 14)    <= sub_wire12(14);
+	sub_wire2(5, 15)    <= sub_wire12(15);
+	sub_wire2(5, 16)    <= sub_wire12(16);
+	sub_wire2(5, 17)    <= sub_wire12(17);
+	sub_wire2(5, 18)    <= sub_wire12(18);
+	sub_wire2(5, 19)    <= sub_wire12(19);
+	sub_wire2(5, 20)    <= sub_wire12(20);
+	sub_wire2(5, 21)    <= sub_wire12(21);
+	sub_wire2(5, 22)    <= sub_wire12(22);
+	sub_wire2(5, 23)    <= sub_wire12(23);
+	sub_wire2(5, 24)    <= sub_wire12(24);
+	sub_wire2(5, 25)    <= sub_wire12(25);
+	sub_wire2(5, 26)    <= sub_wire12(26);
+	sub_wire2(5, 27)    <= sub_wire12(27);
+	sub_wire2(5, 28)    <= sub_wire12(28);
+	sub_wire2(5, 29)    <= sub_wire12(29);
+	sub_wire2(5, 30)    <= sub_wire12(30);
+	sub_wire2(5, 31)    <= sub_wire12(31);
+	sub_wire2(5, 32)    <= sub_wire12(32);
+	sub_wire2(5, 33)    <= sub_wire12(33);
+	sub_wire2(5, 34)    <= sub_wire12(34);
+	sub_wire2(5, 35)    <= sub_wire12(35);
+	sub_wire2(5, 36)    <= sub_wire12(36);
+	sub_wire2(5, 37)    <= sub_wire12(37);
+	sub_wire2(5, 38)    <= sub_wire12(38);
+	sub_wire2(5, 39)    <= sub_wire12(39);
+	sub_wire2(5, 40)    <= sub_wire12(40);
+	sub_wire2(5, 41)    <= sub_wire12(41);
+	sub_wire2(5, 42)    <= sub_wire12(42);
+	sub_wire2(5, 43)    <= sub_wire12(43);
+	sub_wire2(5, 44)    <= sub_wire12(44);
+	sub_wire2(5, 45)    <= sub_wire12(45);
+	sub_wire2(5, 46)    <= sub_wire12(46);
+	sub_wire2(5, 47)    <= sub_wire12(47);
+	sub_wire2(5, 48)    <= sub_wire12(48);
+	sub_wire2(5, 49)    <= sub_wire12(49);
+	sub_wire2(5, 50)    <= sub_wire12(50);
+	sub_wire2(5, 51)    <= sub_wire12(51);
+	sub_wire2(5, 52)    <= sub_wire12(52);
+	sub_wire2(5, 53)    <= sub_wire12(53);
+	sub_wire2(5, 54)    <= sub_wire12(54);
+	sub_wire2(5, 55)    <= sub_wire12(55);
+	sub_wire2(5, 56)    <= sub_wire12(56);
+	sub_wire2(5, 57)    <= sub_wire12(57);
+	sub_wire2(5, 58)    <= sub_wire12(58);
+	sub_wire2(5, 59)    <= sub_wire12(59);
+	sub_wire2(5, 60)    <= sub_wire12(60);
+	sub_wire2(5, 61)    <= sub_wire12(61);
+	sub_wire2(5, 62)    <= sub_wire12(62);
+	sub_wire2(5, 63)    <= sub_wire12(63);
+	sub_wire2(5, 64)    <= sub_wire12(64);
+	sub_wire2(5, 65)    <= sub_wire12(65);
+	sub_wire2(5, 66)    <= sub_wire12(66);
+	sub_wire2(5, 67)    <= sub_wire12(67);
+	sub_wire2(5, 68)    <= sub_wire12(68);
+	sub_wire2(5, 69)    <= sub_wire12(69);
+	sub_wire2(5, 70)    <= sub_wire12(70);
+	sub_wire2(5, 71)    <= sub_wire12(71);
+	sub_wire2(5, 72)    <= sub_wire12(72);
+	sub_wire2(5, 73)    <= sub_wire12(73);
+	sub_wire2(5, 74)    <= sub_wire12(74);
+	sub_wire2(5, 75)    <= sub_wire12(75);
+	sub_wire2(5, 76)    <= sub_wire12(76);
+	sub_wire2(5, 77)    <= sub_wire12(77);
+	sub_wire2(5, 78)    <= sub_wire12(78);
+	sub_wire2(5, 79)    <= sub_wire12(79);
+	sub_wire2(5, 80)    <= sub_wire12(80);
+	sub_wire2(5, 81)    <= sub_wire12(81);
+	sub_wire2(5, 82)    <= sub_wire12(82);
+	sub_wire2(5, 83)    <= sub_wire12(83);
+	sub_wire2(5, 84)    <= sub_wire12(84);
+	sub_wire2(5, 85)    <= sub_wire12(85);
+	sub_wire2(5, 86)    <= sub_wire12(86);
+	sub_wire2(5, 87)    <= sub_wire12(87);
+	sub_wire2(5, 88)    <= sub_wire12(88);
+	sub_wire2(5, 89)    <= sub_wire12(89);
+	sub_wire2(5, 90)    <= sub_wire12(90);
+	sub_wire2(5, 91)    <= sub_wire12(91);
+	sub_wire2(5, 92)    <= sub_wire12(92);
+	sub_wire2(5, 93)    <= sub_wire12(93);
+	sub_wire2(5, 94)    <= sub_wire12(94);
+	sub_wire2(5, 95)    <= sub_wire12(95);
+	sub_wire2(5, 96)    <= sub_wire12(96);
+	sub_wire2(5, 97)    <= sub_wire12(97);
+	sub_wire2(5, 98)    <= sub_wire12(98);
+	sub_wire2(5, 99)    <= sub_wire12(99);
+	sub_wire2(5, 100)    <= sub_wire12(100);
+	sub_wire2(5, 101)    <= sub_wire12(101);
+	sub_wire2(5, 102)    <= sub_wire12(102);
+	sub_wire2(5, 103)    <= sub_wire12(103);
+	sub_wire2(5, 104)    <= sub_wire12(104);
+	sub_wire2(5, 105)    <= sub_wire12(105);
+	sub_wire2(5, 106)    <= sub_wire12(106);
+	sub_wire2(5, 107)    <= sub_wire12(107);
+	sub_wire2(5, 108)    <= sub_wire12(108);
+	sub_wire2(5, 109)    <= sub_wire12(109);
+	sub_wire2(5, 110)    <= sub_wire12(110);
+	sub_wire2(5, 111)    <= sub_wire12(111);
+	sub_wire2(5, 112)    <= sub_wire12(112);
+	sub_wire2(5, 113)    <= sub_wire12(113);
+	sub_wire2(5, 114)    <= sub_wire12(114);
+	sub_wire2(5, 115)    <= sub_wire12(115);
+	sub_wire2(5, 116)    <= sub_wire12(116);
+	sub_wire2(5, 117)    <= sub_wire12(117);
+	sub_wire2(5, 118)    <= sub_wire12(118);
+	sub_wire2(5, 119)    <= sub_wire12(119);
+	sub_wire2(5, 120)    <= sub_wire12(120);
+	sub_wire2(5, 121)    <= sub_wire12(121);
+	sub_wire2(5, 122)    <= sub_wire12(122);
+	sub_wire2(5, 123)    <= sub_wire12(123);
+	sub_wire2(5, 124)    <= sub_wire12(124);
+	sub_wire2(5, 125)    <= sub_wire12(125);
+	sub_wire2(5, 126)    <= sub_wire12(126);
+	sub_wire2(5, 127)    <= sub_wire12(127);
+	sub_wire2(4, 0)    <= sub_wire13(0);
+	sub_wire2(4, 1)    <= sub_wire13(1);
+	sub_wire2(4, 2)    <= sub_wire13(2);
+	sub_wire2(4, 3)    <= sub_wire13(3);
+	sub_wire2(4, 4)    <= sub_wire13(4);
+	sub_wire2(4, 5)    <= sub_wire13(5);
+	sub_wire2(4, 6)    <= sub_wire13(6);
+	sub_wire2(4, 7)    <= sub_wire13(7);
+	sub_wire2(4, 8)    <= sub_wire13(8);
+	sub_wire2(4, 9)    <= sub_wire13(9);
+	sub_wire2(4, 10)    <= sub_wire13(10);
+	sub_wire2(4, 11)    <= sub_wire13(11);
+	sub_wire2(4, 12)    <= sub_wire13(12);
+	sub_wire2(4, 13)    <= sub_wire13(13);
+	sub_wire2(4, 14)    <= sub_wire13(14);
+	sub_wire2(4, 15)    <= sub_wire13(15);
+	sub_wire2(4, 16)    <= sub_wire13(16);
+	sub_wire2(4, 17)    <= sub_wire13(17);
+	sub_wire2(4, 18)    <= sub_wire13(18);
+	sub_wire2(4, 19)    <= sub_wire13(19);
+	sub_wire2(4, 20)    <= sub_wire13(20);
+	sub_wire2(4, 21)    <= sub_wire13(21);
+	sub_wire2(4, 22)    <= sub_wire13(22);
+	sub_wire2(4, 23)    <= sub_wire13(23);
+	sub_wire2(4, 24)    <= sub_wire13(24);
+	sub_wire2(4, 25)    <= sub_wire13(25);
+	sub_wire2(4, 26)    <= sub_wire13(26);
+	sub_wire2(4, 27)    <= sub_wire13(27);
+	sub_wire2(4, 28)    <= sub_wire13(28);
+	sub_wire2(4, 29)    <= sub_wire13(29);
+	sub_wire2(4, 30)    <= sub_wire13(30);
+	sub_wire2(4, 31)    <= sub_wire13(31);
+	sub_wire2(4, 32)    <= sub_wire13(32);
+	sub_wire2(4, 33)    <= sub_wire13(33);
+	sub_wire2(4, 34)    <= sub_wire13(34);
+	sub_wire2(4, 35)    <= sub_wire13(35);
+	sub_wire2(4, 36)    <= sub_wire13(36);
+	sub_wire2(4, 37)    <= sub_wire13(37);
+	sub_wire2(4, 38)    <= sub_wire13(38);
+	sub_wire2(4, 39)    <= sub_wire13(39);
+	sub_wire2(4, 40)    <= sub_wire13(40);
+	sub_wire2(4, 41)    <= sub_wire13(41);
+	sub_wire2(4, 42)    <= sub_wire13(42);
+	sub_wire2(4, 43)    <= sub_wire13(43);
+	sub_wire2(4, 44)    <= sub_wire13(44);
+	sub_wire2(4, 45)    <= sub_wire13(45);
+	sub_wire2(4, 46)    <= sub_wire13(46);
+	sub_wire2(4, 47)    <= sub_wire13(47);
+	sub_wire2(4, 48)    <= sub_wire13(48);
+	sub_wire2(4, 49)    <= sub_wire13(49);
+	sub_wire2(4, 50)    <= sub_wire13(50);
+	sub_wire2(4, 51)    <= sub_wire13(51);
+	sub_wire2(4, 52)    <= sub_wire13(52);
+	sub_wire2(4, 53)    <= sub_wire13(53);
+	sub_wire2(4, 54)    <= sub_wire13(54);
+	sub_wire2(4, 55)    <= sub_wire13(55);
+	sub_wire2(4, 56)    <= sub_wire13(56);
+	sub_wire2(4, 57)    <= sub_wire13(57);
+	sub_wire2(4, 58)    <= sub_wire13(58);
+	sub_wire2(4, 59)    <= sub_wire13(59);
+	sub_wire2(4, 60)    <= sub_wire13(60);
+	sub_wire2(4, 61)    <= sub_wire13(61);
+	sub_wire2(4, 62)    <= sub_wire13(62);
+	sub_wire2(4, 63)    <= sub_wire13(63);
+	sub_wire2(4, 64)    <= sub_wire13(64);
+	sub_wire2(4, 65)    <= sub_wire13(65);
+	sub_wire2(4, 66)    <= sub_wire13(66);
+	sub_wire2(4, 67)    <= sub_wire13(67);
+	sub_wire2(4, 68)    <= sub_wire13(68);
+	sub_wire2(4, 69)    <= sub_wire13(69);
+	sub_wire2(4, 70)    <= sub_wire13(70);
+	sub_wire2(4, 71)    <= sub_wire13(71);
+	sub_wire2(4, 72)    <= sub_wire13(72);
+	sub_wire2(4, 73)    <= sub_wire13(73);
+	sub_wire2(4, 74)    <= sub_wire13(74);
+	sub_wire2(4, 75)    <= sub_wire13(75);
+	sub_wire2(4, 76)    <= sub_wire13(76);
+	sub_wire2(4, 77)    <= sub_wire13(77);
+	sub_wire2(4, 78)    <= sub_wire13(78);
+	sub_wire2(4, 79)    <= sub_wire13(79);
+	sub_wire2(4, 80)    <= sub_wire13(80);
+	sub_wire2(4, 81)    <= sub_wire13(81);
+	sub_wire2(4, 82)    <= sub_wire13(82);
+	sub_wire2(4, 83)    <= sub_wire13(83);
+	sub_wire2(4, 84)    <= sub_wire13(84);
+	sub_wire2(4, 85)    <= sub_wire13(85);
+	sub_wire2(4, 86)    <= sub_wire13(86);
+	sub_wire2(4, 87)    <= sub_wire13(87);
+	sub_wire2(4, 88)    <= sub_wire13(88);
+	sub_wire2(4, 89)    <= sub_wire13(89);
+	sub_wire2(4, 90)    <= sub_wire13(90);
+	sub_wire2(4, 91)    <= sub_wire13(91);
+	sub_wire2(4, 92)    <= sub_wire13(92);
+	sub_wire2(4, 93)    <= sub_wire13(93);
+	sub_wire2(4, 94)    <= sub_wire13(94);
+	sub_wire2(4, 95)    <= sub_wire13(95);
+	sub_wire2(4, 96)    <= sub_wire13(96);
+	sub_wire2(4, 97)    <= sub_wire13(97);
+	sub_wire2(4, 98)    <= sub_wire13(98);
+	sub_wire2(4, 99)    <= sub_wire13(99);
+	sub_wire2(4, 100)    <= sub_wire13(100);
+	sub_wire2(4, 101)    <= sub_wire13(101);
+	sub_wire2(4, 102)    <= sub_wire13(102);
+	sub_wire2(4, 103)    <= sub_wire13(103);
+	sub_wire2(4, 104)    <= sub_wire13(104);
+	sub_wire2(4, 105)    <= sub_wire13(105);
+	sub_wire2(4, 106)    <= sub_wire13(106);
+	sub_wire2(4, 107)    <= sub_wire13(107);
+	sub_wire2(4, 108)    <= sub_wire13(108);
+	sub_wire2(4, 109)    <= sub_wire13(109);
+	sub_wire2(4, 110)    <= sub_wire13(110);
+	sub_wire2(4, 111)    <= sub_wire13(111);
+	sub_wire2(4, 112)    <= sub_wire13(112);
+	sub_wire2(4, 113)    <= sub_wire13(113);
+	sub_wire2(4, 114)    <= sub_wire13(114);
+	sub_wire2(4, 115)    <= sub_wire13(115);
+	sub_wire2(4, 116)    <= sub_wire13(116);
+	sub_wire2(4, 117)    <= sub_wire13(117);
+	sub_wire2(4, 118)    <= sub_wire13(118);
+	sub_wire2(4, 119)    <= sub_wire13(119);
+	sub_wire2(4, 120)    <= sub_wire13(120);
+	sub_wire2(4, 121)    <= sub_wire13(121);
+	sub_wire2(4, 122)    <= sub_wire13(122);
+	sub_wire2(4, 123)    <= sub_wire13(123);
+	sub_wire2(4, 124)    <= sub_wire13(124);
+	sub_wire2(4, 125)    <= sub_wire13(125);
+	sub_wire2(4, 126)    <= sub_wire13(126);
+	sub_wire2(4, 127)    <= sub_wire13(127);
+	sub_wire2(3, 0)    <= sub_wire14(0);
+	sub_wire2(3, 1)    <= sub_wire14(1);
+	sub_wire2(3, 2)    <= sub_wire14(2);
+	sub_wire2(3, 3)    <= sub_wire14(3);
+	sub_wire2(3, 4)    <= sub_wire14(4);
+	sub_wire2(3, 5)    <= sub_wire14(5);
+	sub_wire2(3, 6)    <= sub_wire14(6);
+	sub_wire2(3, 7)    <= sub_wire14(7);
+	sub_wire2(3, 8)    <= sub_wire14(8);
+	sub_wire2(3, 9)    <= sub_wire14(9);
+	sub_wire2(3, 10)    <= sub_wire14(10);
+	sub_wire2(3, 11)    <= sub_wire14(11);
+	sub_wire2(3, 12)    <= sub_wire14(12);
+	sub_wire2(3, 13)    <= sub_wire14(13);
+	sub_wire2(3, 14)    <= sub_wire14(14);
+	sub_wire2(3, 15)    <= sub_wire14(15);
+	sub_wire2(3, 16)    <= sub_wire14(16);
+	sub_wire2(3, 17)    <= sub_wire14(17);
+	sub_wire2(3, 18)    <= sub_wire14(18);
+	sub_wire2(3, 19)    <= sub_wire14(19);
+	sub_wire2(3, 20)    <= sub_wire14(20);
+	sub_wire2(3, 21)    <= sub_wire14(21);
+	sub_wire2(3, 22)    <= sub_wire14(22);
+	sub_wire2(3, 23)    <= sub_wire14(23);
+	sub_wire2(3, 24)    <= sub_wire14(24);
+	sub_wire2(3, 25)    <= sub_wire14(25);
+	sub_wire2(3, 26)    <= sub_wire14(26);
+	sub_wire2(3, 27)    <= sub_wire14(27);
+	sub_wire2(3, 28)    <= sub_wire14(28);
+	sub_wire2(3, 29)    <= sub_wire14(29);
+	sub_wire2(3, 30)    <= sub_wire14(30);
+	sub_wire2(3, 31)    <= sub_wire14(31);
+	sub_wire2(3, 32)    <= sub_wire14(32);
+	sub_wire2(3, 33)    <= sub_wire14(33);
+	sub_wire2(3, 34)    <= sub_wire14(34);
+	sub_wire2(3, 35)    <= sub_wire14(35);
+	sub_wire2(3, 36)    <= sub_wire14(36);
+	sub_wire2(3, 37)    <= sub_wire14(37);
+	sub_wire2(3, 38)    <= sub_wire14(38);
+	sub_wire2(3, 39)    <= sub_wire14(39);
+	sub_wire2(3, 40)    <= sub_wire14(40);
+	sub_wire2(3, 41)    <= sub_wire14(41);
+	sub_wire2(3, 42)    <= sub_wire14(42);
+	sub_wire2(3, 43)    <= sub_wire14(43);
+	sub_wire2(3, 44)    <= sub_wire14(44);
+	sub_wire2(3, 45)    <= sub_wire14(45);
+	sub_wire2(3, 46)    <= sub_wire14(46);
+	sub_wire2(3, 47)    <= sub_wire14(47);
+	sub_wire2(3, 48)    <= sub_wire14(48);
+	sub_wire2(3, 49)    <= sub_wire14(49);
+	sub_wire2(3, 50)    <= sub_wire14(50);
+	sub_wire2(3, 51)    <= sub_wire14(51);
+	sub_wire2(3, 52)    <= sub_wire14(52);
+	sub_wire2(3, 53)    <= sub_wire14(53);
+	sub_wire2(3, 54)    <= sub_wire14(54);
+	sub_wire2(3, 55)    <= sub_wire14(55);
+	sub_wire2(3, 56)    <= sub_wire14(56);
+	sub_wire2(3, 57)    <= sub_wire14(57);
+	sub_wire2(3, 58)    <= sub_wire14(58);
+	sub_wire2(3, 59)    <= sub_wire14(59);
+	sub_wire2(3, 60)    <= sub_wire14(60);
+	sub_wire2(3, 61)    <= sub_wire14(61);
+	sub_wire2(3, 62)    <= sub_wire14(62);
+	sub_wire2(3, 63)    <= sub_wire14(63);
+	sub_wire2(3, 64)    <= sub_wire14(64);
+	sub_wire2(3, 65)    <= sub_wire14(65);
+	sub_wire2(3, 66)    <= sub_wire14(66);
+	sub_wire2(3, 67)    <= sub_wire14(67);
+	sub_wire2(3, 68)    <= sub_wire14(68);
+	sub_wire2(3, 69)    <= sub_wire14(69);
+	sub_wire2(3, 70)    <= sub_wire14(70);
+	sub_wire2(3, 71)    <= sub_wire14(71);
+	sub_wire2(3, 72)    <= sub_wire14(72);
+	sub_wire2(3, 73)    <= sub_wire14(73);
+	sub_wire2(3, 74)    <= sub_wire14(74);
+	sub_wire2(3, 75)    <= sub_wire14(75);
+	sub_wire2(3, 76)    <= sub_wire14(76);
+	sub_wire2(3, 77)    <= sub_wire14(77);
+	sub_wire2(3, 78)    <= sub_wire14(78);
+	sub_wire2(3, 79)    <= sub_wire14(79);
+	sub_wire2(3, 80)    <= sub_wire14(80);
+	sub_wire2(3, 81)    <= sub_wire14(81);
+	sub_wire2(3, 82)    <= sub_wire14(82);
+	sub_wire2(3, 83)    <= sub_wire14(83);
+	sub_wire2(3, 84)    <= sub_wire14(84);
+	sub_wire2(3, 85)    <= sub_wire14(85);
+	sub_wire2(3, 86)    <= sub_wire14(86);
+	sub_wire2(3, 87)    <= sub_wire14(87);
+	sub_wire2(3, 88)    <= sub_wire14(88);
+	sub_wire2(3, 89)    <= sub_wire14(89);
+	sub_wire2(3, 90)    <= sub_wire14(90);
+	sub_wire2(3, 91)    <= sub_wire14(91);
+	sub_wire2(3, 92)    <= sub_wire14(92);
+	sub_wire2(3, 93)    <= sub_wire14(93);
+	sub_wire2(3, 94)    <= sub_wire14(94);
+	sub_wire2(3, 95)    <= sub_wire14(95);
+	sub_wire2(3, 96)    <= sub_wire14(96);
+	sub_wire2(3, 97)    <= sub_wire14(97);
+	sub_wire2(3, 98)    <= sub_wire14(98);
+	sub_wire2(3, 99)    <= sub_wire14(99);
+	sub_wire2(3, 100)    <= sub_wire14(100);
+	sub_wire2(3, 101)    <= sub_wire14(101);
+	sub_wire2(3, 102)    <= sub_wire14(102);
+	sub_wire2(3, 103)    <= sub_wire14(103);
+	sub_wire2(3, 104)    <= sub_wire14(104);
+	sub_wire2(3, 105)    <= sub_wire14(105);
+	sub_wire2(3, 106)    <= sub_wire14(106);
+	sub_wire2(3, 107)    <= sub_wire14(107);
+	sub_wire2(3, 108)    <= sub_wire14(108);
+	sub_wire2(3, 109)    <= sub_wire14(109);
+	sub_wire2(3, 110)    <= sub_wire14(110);
+	sub_wire2(3, 111)    <= sub_wire14(111);
+	sub_wire2(3, 112)    <= sub_wire14(112);
+	sub_wire2(3, 113)    <= sub_wire14(113);
+	sub_wire2(3, 114)    <= sub_wire14(114);
+	sub_wire2(3, 115)    <= sub_wire14(115);
+	sub_wire2(3, 116)    <= sub_wire14(116);
+	sub_wire2(3, 117)    <= sub_wire14(117);
+	sub_wire2(3, 118)    <= sub_wire14(118);
+	sub_wire2(3, 119)    <= sub_wire14(119);
+	sub_wire2(3, 120)    <= sub_wire14(120);
+	sub_wire2(3, 121)    <= sub_wire14(121);
+	sub_wire2(3, 122)    <= sub_wire14(122);
+	sub_wire2(3, 123)    <= sub_wire14(123);
+	sub_wire2(3, 124)    <= sub_wire14(124);
+	sub_wire2(3, 125)    <= sub_wire14(125);
+	sub_wire2(3, 126)    <= sub_wire14(126);
+	sub_wire2(3, 127)    <= sub_wire14(127);
+	sub_wire2(2, 0)    <= sub_wire15(0);
+	sub_wire2(2, 1)    <= sub_wire15(1);
+	sub_wire2(2, 2)    <= sub_wire15(2);
+	sub_wire2(2, 3)    <= sub_wire15(3);
+	sub_wire2(2, 4)    <= sub_wire15(4);
+	sub_wire2(2, 5)    <= sub_wire15(5);
+	sub_wire2(2, 6)    <= sub_wire15(6);
+	sub_wire2(2, 7)    <= sub_wire15(7);
+	sub_wire2(2, 8)    <= sub_wire15(8);
+	sub_wire2(2, 9)    <= sub_wire15(9);
+	sub_wire2(2, 10)    <= sub_wire15(10);
+	sub_wire2(2, 11)    <= sub_wire15(11);
+	sub_wire2(2, 12)    <= sub_wire15(12);
+	sub_wire2(2, 13)    <= sub_wire15(13);
+	sub_wire2(2, 14)    <= sub_wire15(14);
+	sub_wire2(2, 15)    <= sub_wire15(15);
+	sub_wire2(2, 16)    <= sub_wire15(16);
+	sub_wire2(2, 17)    <= sub_wire15(17);
+	sub_wire2(2, 18)    <= sub_wire15(18);
+	sub_wire2(2, 19)    <= sub_wire15(19);
+	sub_wire2(2, 20)    <= sub_wire15(20);
+	sub_wire2(2, 21)    <= sub_wire15(21);
+	sub_wire2(2, 22)    <= sub_wire15(22);
+	sub_wire2(2, 23)    <= sub_wire15(23);
+	sub_wire2(2, 24)    <= sub_wire15(24);
+	sub_wire2(2, 25)    <= sub_wire15(25);
+	sub_wire2(2, 26)    <= sub_wire15(26);
+	sub_wire2(2, 27)    <= sub_wire15(27);
+	sub_wire2(2, 28)    <= sub_wire15(28);
+	sub_wire2(2, 29)    <= sub_wire15(29);
+	sub_wire2(2, 30)    <= sub_wire15(30);
+	sub_wire2(2, 31)    <= sub_wire15(31);
+	sub_wire2(2, 32)    <= sub_wire15(32);
+	sub_wire2(2, 33)    <= sub_wire15(33);
+	sub_wire2(2, 34)    <= sub_wire15(34);
+	sub_wire2(2, 35)    <= sub_wire15(35);
+	sub_wire2(2, 36)    <= sub_wire15(36);
+	sub_wire2(2, 37)    <= sub_wire15(37);
+	sub_wire2(2, 38)    <= sub_wire15(38);
+	sub_wire2(2, 39)    <= sub_wire15(39);
+	sub_wire2(2, 40)    <= sub_wire15(40);
+	sub_wire2(2, 41)    <= sub_wire15(41);
+	sub_wire2(2, 42)    <= sub_wire15(42);
+	sub_wire2(2, 43)    <= sub_wire15(43);
+	sub_wire2(2, 44)    <= sub_wire15(44);
+	sub_wire2(2, 45)    <= sub_wire15(45);
+	sub_wire2(2, 46)    <= sub_wire15(46);
+	sub_wire2(2, 47)    <= sub_wire15(47);
+	sub_wire2(2, 48)    <= sub_wire15(48);
+	sub_wire2(2, 49)    <= sub_wire15(49);
+	sub_wire2(2, 50)    <= sub_wire15(50);
+	sub_wire2(2, 51)    <= sub_wire15(51);
+	sub_wire2(2, 52)    <= sub_wire15(52);
+	sub_wire2(2, 53)    <= sub_wire15(53);
+	sub_wire2(2, 54)    <= sub_wire15(54);
+	sub_wire2(2, 55)    <= sub_wire15(55);
+	sub_wire2(2, 56)    <= sub_wire15(56);
+	sub_wire2(2, 57)    <= sub_wire15(57);
+	sub_wire2(2, 58)    <= sub_wire15(58);
+	sub_wire2(2, 59)    <= sub_wire15(59);
+	sub_wire2(2, 60)    <= sub_wire15(60);
+	sub_wire2(2, 61)    <= sub_wire15(61);
+	sub_wire2(2, 62)    <= sub_wire15(62);
+	sub_wire2(2, 63)    <= sub_wire15(63);
+	sub_wire2(2, 64)    <= sub_wire15(64);
+	sub_wire2(2, 65)    <= sub_wire15(65);
+	sub_wire2(2, 66)    <= sub_wire15(66);
+	sub_wire2(2, 67)    <= sub_wire15(67);
+	sub_wire2(2, 68)    <= sub_wire15(68);
+	sub_wire2(2, 69)    <= sub_wire15(69);
+	sub_wire2(2, 70)    <= sub_wire15(70);
+	sub_wire2(2, 71)    <= sub_wire15(71);
+	sub_wire2(2, 72)    <= sub_wire15(72);
+	sub_wire2(2, 73)    <= sub_wire15(73);
+	sub_wire2(2, 74)    <= sub_wire15(74);
+	sub_wire2(2, 75)    <= sub_wire15(75);
+	sub_wire2(2, 76)    <= sub_wire15(76);
+	sub_wire2(2, 77)    <= sub_wire15(77);
+	sub_wire2(2, 78)    <= sub_wire15(78);
+	sub_wire2(2, 79)    <= sub_wire15(79);
+	sub_wire2(2, 80)    <= sub_wire15(80);
+	sub_wire2(2, 81)    <= sub_wire15(81);
+	sub_wire2(2, 82)    <= sub_wire15(82);
+	sub_wire2(2, 83)    <= sub_wire15(83);
+	sub_wire2(2, 84)    <= sub_wire15(84);
+	sub_wire2(2, 85)    <= sub_wire15(85);
+	sub_wire2(2, 86)    <= sub_wire15(86);
+	sub_wire2(2, 87)    <= sub_wire15(87);
+	sub_wire2(2, 88)    <= sub_wire15(88);
+	sub_wire2(2, 89)    <= sub_wire15(89);
+	sub_wire2(2, 90)    <= sub_wire15(90);
+	sub_wire2(2, 91)    <= sub_wire15(91);
+	sub_wire2(2, 92)    <= sub_wire15(92);
+	sub_wire2(2, 93)    <= sub_wire15(93);
+	sub_wire2(2, 94)    <= sub_wire15(94);
+	sub_wire2(2, 95)    <= sub_wire15(95);
+	sub_wire2(2, 96)    <= sub_wire15(96);
+	sub_wire2(2, 97)    <= sub_wire15(97);
+	sub_wire2(2, 98)    <= sub_wire15(98);
+	sub_wire2(2, 99)    <= sub_wire15(99);
+	sub_wire2(2, 100)    <= sub_wire15(100);
+	sub_wire2(2, 101)    <= sub_wire15(101);
+	sub_wire2(2, 102)    <= sub_wire15(102);
+	sub_wire2(2, 103)    <= sub_wire15(103);
+	sub_wire2(2, 104)    <= sub_wire15(104);
+	sub_wire2(2, 105)    <= sub_wire15(105);
+	sub_wire2(2, 106)    <= sub_wire15(106);
+	sub_wire2(2, 107)    <= sub_wire15(107);
+	sub_wire2(2, 108)    <= sub_wire15(108);
+	sub_wire2(2, 109)    <= sub_wire15(109);
+	sub_wire2(2, 110)    <= sub_wire15(110);
+	sub_wire2(2, 111)    <= sub_wire15(111);
+	sub_wire2(2, 112)    <= sub_wire15(112);
+	sub_wire2(2, 113)    <= sub_wire15(113);
+	sub_wire2(2, 114)    <= sub_wire15(114);
+	sub_wire2(2, 115)    <= sub_wire15(115);
+	sub_wire2(2, 116)    <= sub_wire15(116);
+	sub_wire2(2, 117)    <= sub_wire15(117);
+	sub_wire2(2, 118)    <= sub_wire15(118);
+	sub_wire2(2, 119)    <= sub_wire15(119);
+	sub_wire2(2, 120)    <= sub_wire15(120);
+	sub_wire2(2, 121)    <= sub_wire15(121);
+	sub_wire2(2, 122)    <= sub_wire15(122);
+	sub_wire2(2, 123)    <= sub_wire15(123);
+	sub_wire2(2, 124)    <= sub_wire15(124);
+	sub_wire2(2, 125)    <= sub_wire15(125);
+	sub_wire2(2, 126)    <= sub_wire15(126);
+	sub_wire2(2, 127)    <= sub_wire15(127);
+	sub_wire2(1, 0)    <= sub_wire16(0);
+	sub_wire2(1, 1)    <= sub_wire16(1);
+	sub_wire2(1, 2)    <= sub_wire16(2);
+	sub_wire2(1, 3)    <= sub_wire16(3);
+	sub_wire2(1, 4)    <= sub_wire16(4);
+	sub_wire2(1, 5)    <= sub_wire16(5);
+	sub_wire2(1, 6)    <= sub_wire16(6);
+	sub_wire2(1, 7)    <= sub_wire16(7);
+	sub_wire2(1, 8)    <= sub_wire16(8);
+	sub_wire2(1, 9)    <= sub_wire16(9);
+	sub_wire2(1, 10)    <= sub_wire16(10);
+	sub_wire2(1, 11)    <= sub_wire16(11);
+	sub_wire2(1, 12)    <= sub_wire16(12);
+	sub_wire2(1, 13)    <= sub_wire16(13);
+	sub_wire2(1, 14)    <= sub_wire16(14);
+	sub_wire2(1, 15)    <= sub_wire16(15);
+	sub_wire2(1, 16)    <= sub_wire16(16);
+	sub_wire2(1, 17)    <= sub_wire16(17);
+	sub_wire2(1, 18)    <= sub_wire16(18);
+	sub_wire2(1, 19)    <= sub_wire16(19);
+	sub_wire2(1, 20)    <= sub_wire16(20);
+	sub_wire2(1, 21)    <= sub_wire16(21);
+	sub_wire2(1, 22)    <= sub_wire16(22);
+	sub_wire2(1, 23)    <= sub_wire16(23);
+	sub_wire2(1, 24)    <= sub_wire16(24);
+	sub_wire2(1, 25)    <= sub_wire16(25);
+	sub_wire2(1, 26)    <= sub_wire16(26);
+	sub_wire2(1, 27)    <= sub_wire16(27);
+	sub_wire2(1, 28)    <= sub_wire16(28);
+	sub_wire2(1, 29)    <= sub_wire16(29);
+	sub_wire2(1, 30)    <= sub_wire16(30);
+	sub_wire2(1, 31)    <= sub_wire16(31);
+	sub_wire2(1, 32)    <= sub_wire16(32);
+	sub_wire2(1, 33)    <= sub_wire16(33);
+	sub_wire2(1, 34)    <= sub_wire16(34);
+	sub_wire2(1, 35)    <= sub_wire16(35);
+	sub_wire2(1, 36)    <= sub_wire16(36);
+	sub_wire2(1, 37)    <= sub_wire16(37);
+	sub_wire2(1, 38)    <= sub_wire16(38);
+	sub_wire2(1, 39)    <= sub_wire16(39);
+	sub_wire2(1, 40)    <= sub_wire16(40);
+	sub_wire2(1, 41)    <= sub_wire16(41);
+	sub_wire2(1, 42)    <= sub_wire16(42);
+	sub_wire2(1, 43)    <= sub_wire16(43);
+	sub_wire2(1, 44)    <= sub_wire16(44);
+	sub_wire2(1, 45)    <= sub_wire16(45);
+	sub_wire2(1, 46)    <= sub_wire16(46);
+	sub_wire2(1, 47)    <= sub_wire16(47);
+	sub_wire2(1, 48)    <= sub_wire16(48);
+	sub_wire2(1, 49)    <= sub_wire16(49);
+	sub_wire2(1, 50)    <= sub_wire16(50);
+	sub_wire2(1, 51)    <= sub_wire16(51);
+	sub_wire2(1, 52)    <= sub_wire16(52);
+	sub_wire2(1, 53)    <= sub_wire16(53);
+	sub_wire2(1, 54)    <= sub_wire16(54);
+	sub_wire2(1, 55)    <= sub_wire16(55);
+	sub_wire2(1, 56)    <= sub_wire16(56);
+	sub_wire2(1, 57)    <= sub_wire16(57);
+	sub_wire2(1, 58)    <= sub_wire16(58);
+	sub_wire2(1, 59)    <= sub_wire16(59);
+	sub_wire2(1, 60)    <= sub_wire16(60);
+	sub_wire2(1, 61)    <= sub_wire16(61);
+	sub_wire2(1, 62)    <= sub_wire16(62);
+	sub_wire2(1, 63)    <= sub_wire16(63);
+	sub_wire2(1, 64)    <= sub_wire16(64);
+	sub_wire2(1, 65)    <= sub_wire16(65);
+	sub_wire2(1, 66)    <= sub_wire16(66);
+	sub_wire2(1, 67)    <= sub_wire16(67);
+	sub_wire2(1, 68)    <= sub_wire16(68);
+	sub_wire2(1, 69)    <= sub_wire16(69);
+	sub_wire2(1, 70)    <= sub_wire16(70);
+	sub_wire2(1, 71)    <= sub_wire16(71);
+	sub_wire2(1, 72)    <= sub_wire16(72);
+	sub_wire2(1, 73)    <= sub_wire16(73);
+	sub_wire2(1, 74)    <= sub_wire16(74);
+	sub_wire2(1, 75)    <= sub_wire16(75);
+	sub_wire2(1, 76)    <= sub_wire16(76);
+	sub_wire2(1, 77)    <= sub_wire16(77);
+	sub_wire2(1, 78)    <= sub_wire16(78);
+	sub_wire2(1, 79)    <= sub_wire16(79);
+	sub_wire2(1, 80)    <= sub_wire16(80);
+	sub_wire2(1, 81)    <= sub_wire16(81);
+	sub_wire2(1, 82)    <= sub_wire16(82);
+	sub_wire2(1, 83)    <= sub_wire16(83);
+	sub_wire2(1, 84)    <= sub_wire16(84);
+	sub_wire2(1, 85)    <= sub_wire16(85);
+	sub_wire2(1, 86)    <= sub_wire16(86);
+	sub_wire2(1, 87)    <= sub_wire16(87);
+	sub_wire2(1, 88)    <= sub_wire16(88);
+	sub_wire2(1, 89)    <= sub_wire16(89);
+	sub_wire2(1, 90)    <= sub_wire16(90);
+	sub_wire2(1, 91)    <= sub_wire16(91);
+	sub_wire2(1, 92)    <= sub_wire16(92);
+	sub_wire2(1, 93)    <= sub_wire16(93);
+	sub_wire2(1, 94)    <= sub_wire16(94);
+	sub_wire2(1, 95)    <= sub_wire16(95);
+	sub_wire2(1, 96)    <= sub_wire16(96);
+	sub_wire2(1, 97)    <= sub_wire16(97);
+	sub_wire2(1, 98)    <= sub_wire16(98);
+	sub_wire2(1, 99)    <= sub_wire16(99);
+	sub_wire2(1, 100)    <= sub_wire16(100);
+	sub_wire2(1, 101)    <= sub_wire16(101);
+	sub_wire2(1, 102)    <= sub_wire16(102);
+	sub_wire2(1, 103)    <= sub_wire16(103);
+	sub_wire2(1, 104)    <= sub_wire16(104);
+	sub_wire2(1, 105)    <= sub_wire16(105);
+	sub_wire2(1, 106)    <= sub_wire16(106);
+	sub_wire2(1, 107)    <= sub_wire16(107);
+	sub_wire2(1, 108)    <= sub_wire16(108);
+	sub_wire2(1, 109)    <= sub_wire16(109);
+	sub_wire2(1, 110)    <= sub_wire16(110);
+	sub_wire2(1, 111)    <= sub_wire16(111);
+	sub_wire2(1, 112)    <= sub_wire16(112);
+	sub_wire2(1, 113)    <= sub_wire16(113);
+	sub_wire2(1, 114)    <= sub_wire16(114);
+	sub_wire2(1, 115)    <= sub_wire16(115);
+	sub_wire2(1, 116)    <= sub_wire16(116);
+	sub_wire2(1, 117)    <= sub_wire16(117);
+	sub_wire2(1, 118)    <= sub_wire16(118);
+	sub_wire2(1, 119)    <= sub_wire16(119);
+	sub_wire2(1, 120)    <= sub_wire16(120);
+	sub_wire2(1, 121)    <= sub_wire16(121);
+	sub_wire2(1, 122)    <= sub_wire16(122);
+	sub_wire2(1, 123)    <= sub_wire16(123);
+	sub_wire2(1, 124)    <= sub_wire16(124);
+	sub_wire2(1, 125)    <= sub_wire16(125);
+	sub_wire2(1, 126)    <= sub_wire16(126);
+	sub_wire2(1, 127)    <= sub_wire16(127);
+	sub_wire2(0, 0)    <= sub_wire17(0);
+	sub_wire2(0, 1)    <= sub_wire17(1);
+	sub_wire2(0, 2)    <= sub_wire17(2);
+	sub_wire2(0, 3)    <= sub_wire17(3);
+	sub_wire2(0, 4)    <= sub_wire17(4);
+	sub_wire2(0, 5)    <= sub_wire17(5);
+	sub_wire2(0, 6)    <= sub_wire17(6);
+	sub_wire2(0, 7)    <= sub_wire17(7);
+	sub_wire2(0, 8)    <= sub_wire17(8);
+	sub_wire2(0, 9)    <= sub_wire17(9);
+	sub_wire2(0, 10)    <= sub_wire17(10);
+	sub_wire2(0, 11)    <= sub_wire17(11);
+	sub_wire2(0, 12)    <= sub_wire17(12);
+	sub_wire2(0, 13)    <= sub_wire17(13);
+	sub_wire2(0, 14)    <= sub_wire17(14);
+	sub_wire2(0, 15)    <= sub_wire17(15);
+	sub_wire2(0, 16)    <= sub_wire17(16);
+	sub_wire2(0, 17)    <= sub_wire17(17);
+	sub_wire2(0, 18)    <= sub_wire17(18);
+	sub_wire2(0, 19)    <= sub_wire17(19);
+	sub_wire2(0, 20)    <= sub_wire17(20);
+	sub_wire2(0, 21)    <= sub_wire17(21);
+	sub_wire2(0, 22)    <= sub_wire17(22);
+	sub_wire2(0, 23)    <= sub_wire17(23);
+	sub_wire2(0, 24)    <= sub_wire17(24);
+	sub_wire2(0, 25)    <= sub_wire17(25);
+	sub_wire2(0, 26)    <= sub_wire17(26);
+	sub_wire2(0, 27)    <= sub_wire17(27);
+	sub_wire2(0, 28)    <= sub_wire17(28);
+	sub_wire2(0, 29)    <= sub_wire17(29);
+	sub_wire2(0, 30)    <= sub_wire17(30);
+	sub_wire2(0, 31)    <= sub_wire17(31);
+	sub_wire2(0, 32)    <= sub_wire17(32);
+	sub_wire2(0, 33)    <= sub_wire17(33);
+	sub_wire2(0, 34)    <= sub_wire17(34);
+	sub_wire2(0, 35)    <= sub_wire17(35);
+	sub_wire2(0, 36)    <= sub_wire17(36);
+	sub_wire2(0, 37)    <= sub_wire17(37);
+	sub_wire2(0, 38)    <= sub_wire17(38);
+	sub_wire2(0, 39)    <= sub_wire17(39);
+	sub_wire2(0, 40)    <= sub_wire17(40);
+	sub_wire2(0, 41)    <= sub_wire17(41);
+	sub_wire2(0, 42)    <= sub_wire17(42);
+	sub_wire2(0, 43)    <= sub_wire17(43);
+	sub_wire2(0, 44)    <= sub_wire17(44);
+	sub_wire2(0, 45)    <= sub_wire17(45);
+	sub_wire2(0, 46)    <= sub_wire17(46);
+	sub_wire2(0, 47)    <= sub_wire17(47);
+	sub_wire2(0, 48)    <= sub_wire17(48);
+	sub_wire2(0, 49)    <= sub_wire17(49);
+	sub_wire2(0, 50)    <= sub_wire17(50);
+	sub_wire2(0, 51)    <= sub_wire17(51);
+	sub_wire2(0, 52)    <= sub_wire17(52);
+	sub_wire2(0, 53)    <= sub_wire17(53);
+	sub_wire2(0, 54)    <= sub_wire17(54);
+	sub_wire2(0, 55)    <= sub_wire17(55);
+	sub_wire2(0, 56)    <= sub_wire17(56);
+	sub_wire2(0, 57)    <= sub_wire17(57);
+	sub_wire2(0, 58)    <= sub_wire17(58);
+	sub_wire2(0, 59)    <= sub_wire17(59);
+	sub_wire2(0, 60)    <= sub_wire17(60);
+	sub_wire2(0, 61)    <= sub_wire17(61);
+	sub_wire2(0, 62)    <= sub_wire17(62);
+	sub_wire2(0, 63)    <= sub_wire17(63);
+	sub_wire2(0, 64)    <= sub_wire17(64);
+	sub_wire2(0, 65)    <= sub_wire17(65);
+	sub_wire2(0, 66)    <= sub_wire17(66);
+	sub_wire2(0, 67)    <= sub_wire17(67);
+	sub_wire2(0, 68)    <= sub_wire17(68);
+	sub_wire2(0, 69)    <= sub_wire17(69);
+	sub_wire2(0, 70)    <= sub_wire17(70);
+	sub_wire2(0, 71)    <= sub_wire17(71);
+	sub_wire2(0, 72)    <= sub_wire17(72);
+	sub_wire2(0, 73)    <= sub_wire17(73);
+	sub_wire2(0, 74)    <= sub_wire17(74);
+	sub_wire2(0, 75)    <= sub_wire17(75);
+	sub_wire2(0, 76)    <= sub_wire17(76);
+	sub_wire2(0, 77)    <= sub_wire17(77);
+	sub_wire2(0, 78)    <= sub_wire17(78);
+	sub_wire2(0, 79)    <= sub_wire17(79);
+	sub_wire2(0, 80)    <= sub_wire17(80);
+	sub_wire2(0, 81)    <= sub_wire17(81);
+	sub_wire2(0, 82)    <= sub_wire17(82);
+	sub_wire2(0, 83)    <= sub_wire17(83);
+	sub_wire2(0, 84)    <= sub_wire17(84);
+	sub_wire2(0, 85)    <= sub_wire17(85);
+	sub_wire2(0, 86)    <= sub_wire17(86);
+	sub_wire2(0, 87)    <= sub_wire17(87);
+	sub_wire2(0, 88)    <= sub_wire17(88);
+	sub_wire2(0, 89)    <= sub_wire17(89);
+	sub_wire2(0, 90)    <= sub_wire17(90);
+	sub_wire2(0, 91)    <= sub_wire17(91);
+	sub_wire2(0, 92)    <= sub_wire17(92);
+	sub_wire2(0, 93)    <= sub_wire17(93);
+	sub_wire2(0, 94)    <= sub_wire17(94);
+	sub_wire2(0, 95)    <= sub_wire17(95);
+	sub_wire2(0, 96)    <= sub_wire17(96);
+	sub_wire2(0, 97)    <= sub_wire17(97);
+	sub_wire2(0, 98)    <= sub_wire17(98);
+	sub_wire2(0, 99)    <= sub_wire17(99);
+	sub_wire2(0, 100)    <= sub_wire17(100);
+	sub_wire2(0, 101)    <= sub_wire17(101);
+	sub_wire2(0, 102)    <= sub_wire17(102);
+	sub_wire2(0, 103)    <= sub_wire17(103);
+	sub_wire2(0, 104)    <= sub_wire17(104);
+	sub_wire2(0, 105)    <= sub_wire17(105);
+	sub_wire2(0, 106)    <= sub_wire17(106);
+	sub_wire2(0, 107)    <= sub_wire17(107);
+	sub_wire2(0, 108)    <= sub_wire17(108);
+	sub_wire2(0, 109)    <= sub_wire17(109);
+	sub_wire2(0, 110)    <= sub_wire17(110);
+	sub_wire2(0, 111)    <= sub_wire17(111);
+	sub_wire2(0, 112)    <= sub_wire17(112);
+	sub_wire2(0, 113)    <= sub_wire17(113);
+	sub_wire2(0, 114)    <= sub_wire17(114);
+	sub_wire2(0, 115)    <= sub_wire17(115);
+	sub_wire2(0, 116)    <= sub_wire17(116);
+	sub_wire2(0, 117)    <= sub_wire17(117);
+	sub_wire2(0, 118)    <= sub_wire17(118);
+	sub_wire2(0, 119)    <= sub_wire17(119);
+	sub_wire2(0, 120)    <= sub_wire17(120);
+	sub_wire2(0, 121)    <= sub_wire17(121);
+	sub_wire2(0, 122)    <= sub_wire17(122);
+	sub_wire2(0, 123)    <= sub_wire17(123);
+	sub_wire2(0, 124)    <= sub_wire17(124);
+	sub_wire2(0, 125)    <= sub_wire17(125);
+	sub_wire2(0, 126)    <= sub_wire17(126);
+	sub_wire2(0, 127)    <= sub_wire17(127);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 16,
+		lpm_type => "LPM_MUX",
+		lpm_width => 128,
+		lpm_widths => 4
+	)
+	PORT MAP (
+		sel => sel,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
+-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
+-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
+-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
+-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
+-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
+-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
+-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
+-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
+-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
+-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
+-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
+-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg0.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg0.bsf
new file mode 100644
index 0000000..fb70a4b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg0.bsf
@@ -0,0 +1,70 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 128)
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 144 72)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
+		(line (pt 144 72)(pt 128 72)(line_width 1))
+	)
+	(drawing
+		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 112)(line_width 1))
+		(line (pt 128 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+		(line (pt 16 74)(pt 22 80)(line_width 1))
+		(line (pt 22 80)(pt 16 86)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg0.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg0.cmp
new file mode 100644
index 0000000..c0613d5
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg0.cmp
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg0
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		load		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg0.inc b/FPGA_by_Fredi/Video/lpm_shiftreg0.inc
new file mode 100644
index 0000000..1c0c4a2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg0.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg0 
+(
+	clock,
+	data[15..0],
+	load,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg0.qip b/FPGA_by_Fredi/Video/lpm_shiftreg0.qip
new file mode 100644
index 0000000..a233319
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg0.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg0.vhd
new file mode 100644
index 0000000..6e5d954
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg0.vhd
@@ -0,0 +1,135 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg0.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		load		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg0;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			load	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "LEFT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 16
+	)
+	PORT MAP (
+		load => load,
+		clock => clock,
+		data => data,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg1.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg1.bsf
new file mode 100644
index 0000000..aa20405
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg1.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg1.cmp
new file mode 100644
index 0000000..1a7ae1c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg1.qip b/FPGA_by_Fredi/Video/lpm_shiftreg1.qip
new file mode 100644
index 0000000..8a8e8a5
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg1.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg1.vhd
new file mode 100644
index 0000000..781fe1b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg1.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg1.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+END lpm_shiftreg1;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(1 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "LEFT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 2
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg2.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg2.bsf
new file mode 100644
index 0000000..0caa084
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg2.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg2.cmp
new file mode 100644
index 0000000..e7c1030
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg2.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg2
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg2.qip b/FPGA_by_Fredi/Video/lpm_shiftreg2.qip
new file mode 100644
index 0000000..3c5305b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg2.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg2.vhd
new file mode 100644
index 0000000..ca02c26
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg2.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg2.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg2;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 4
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg3.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg3.bsf
new file mode 100644
index 0000000..d18b388
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg3.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg3.cmp
new file mode 100644
index 0000000..4cc6db7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg3.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg3
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg3.inc b/FPGA_by_Fredi/Video/lpm_shiftreg3.inc
new file mode 100644
index 0000000..4f70ce5
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg3.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg3 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg3.qip b/FPGA_by_Fredi/Video/lpm_shiftreg3.qip
new file mode 100644
index 0000000..783fdea
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg3.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg3.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg3.vhd
new file mode 100644
index 0000000..b87c221
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg3.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg3.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg3 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg3;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 2
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg4.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg4.bsf
new file mode 100644
index 0000000..658958d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg4.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg4.cmp
new file mode 100644
index 0000000..83fb9e5
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg4.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg4
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg4.inc b/FPGA_by_Fredi/Video/lpm_shiftreg4.inc
new file mode 100644
index 0000000..322863a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg4.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg4 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg4.qip b/FPGA_by_Fredi/Video/lpm_shiftreg4.qip
new file mode 100644
index 0000000..363cd59
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg4.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg4.vhd
new file mode 100644
index 0000000..3d8f5d1
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg4.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg4.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg4 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg4;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg5.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg5.bsf
new file mode 100644
index 0000000..a528c96
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg5.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg5.cmp
new file mode 100644
index 0000000..638f12e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg5.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg5
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg5.inc b/FPGA_by_Fredi/Video/lpm_shiftreg5.inc
new file mode 100644
index 0000000..431ed2c
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg5 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	q[4..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg5.qip b/FPGA_by_Fredi/Video/lpm_shiftreg5.qip
new file mode 100644
index 0000000..9b71f4b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg5.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg5.vhd
new file mode 100644
index 0000000..71a1232
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg5.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg5.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg5 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_shiftreg5;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg5 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg6.bsf b/FPGA_by_Fredi/Video/lpm_shiftreg6.bsf
new file mode 100644
index 0000000..aa0296b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg6.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg6.cmp b/FPGA_by_Fredi/Video/lpm_shiftreg6.cmp
new file mode 100644
index 0000000..c9f7a9b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg6.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg6
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg6.inc b/FPGA_by_Fredi/Video/lpm_shiftreg6.inc
new file mode 100644
index 0000000..7767c57
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg6.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg6 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	q[4..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg6.qip b/FPGA_by_Fredi/Video/lpm_shiftreg6.qip
new file mode 100644
index 0000000..adb4909
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_shiftreg6.vhd b/FPGA_by_Fredi/Video/lpm_shiftreg6.vhd
new file mode 100644
index 0000000..773243e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_shiftreg6.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg6.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_shiftreg6;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg6 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/altddio_out0.bsf b/FPGA_by_Fredi/altddio_out0.bsf
new file mode 100644
index 0000000..9889d79
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altddio_out0.cmp b/FPGA_by_Fredi/altddio_out0.cmp
new file mode 100644
index 0000000..6e98c39
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_out0
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altddio_out0.inc b/FPGA_by_Fredi/altddio_out0.inc
new file mode 100644
index 0000000..030b327
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out0 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_by_Fredi/altddio_out0.ppf b/FPGA_by_Fredi/altddio_out0.ppf
new file mode 100644
index 0000000..4379977
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altddio_out0.qip b/FPGA_by_Fredi/altddio_out0.qip
new file mode 100644
index 0000000..8193856
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
diff --git a/FPGA_by_Fredi/altddio_out0.vhd b/FPGA_by_Fredi/altddio_out0.vhd
new file mode 100644
index 0000000..ea6d708
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out0.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out0.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out0;
+
+
+ARCHITECTURE SYN OF altddio_out0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altddio_out3.bsf b/FPGA_by_Fredi/altddio_out3.bsf
new file mode 100644
index 0000000..ba8c153
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altddio_out3.cmp b/FPGA_by_Fredi/altddio_out3.cmp
new file mode 100644
index 0000000..ce5862c
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altddio_out3
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altddio_out3.inc b/FPGA_by_Fredi/altddio_out3.inc
new file mode 100644
index 0000000..f6b4097
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out3 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_by_Fredi/altddio_out3.ppf b/FPGA_by_Fredi/altddio_out3.ppf
new file mode 100644
index 0000000..e914df8
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altddio_out3.qip b/FPGA_by_Fredi/altddio_out3.qip
new file mode 100644
index 0000000..8f94ee3
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]
diff --git a/FPGA_by_Fredi/altddio_out3.vhd b/FPGA_by_Fredi/altddio_out3.vhd
new file mode 100644
index 0000000..e55160f
--- /dev/null
+++ b/FPGA_by_Fredi/altddio_out3.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out3.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out3 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out3;
+
+
+ARCHITECTURE SYN OF altddio_out3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll0.bsf b/FPGA_by_Fredi/altpll0.bsf
new file mode 100644
index 0000000..b9a2853
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.bsf
@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 280 248)
+	(text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 229 31 244)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 280 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8)))
+		(line (pt 280 72)(pt 248 72)(line_width 1))
+	)
+	(port
+		(pt 280 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8)))
+		(line (pt 280 96)(pt 248 96)(line_width 1))
+	)
+	(port
+		(pt 280 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8)))
+		(line (pt 280 120)(pt 248 120)(line_width 1))
+	)
+	(port
+		(pt 280 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8)))
+		(line (pt 280 144)(pt 248 144)(line_width 1))
+	)
+	(port
+		(pt 280 168)
+		(output)
+		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8)))
+		(line (pt 280 168)(pt 248 168)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 205 230 253 244)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
+		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "16/11" (rect 89 129 116 143)(font "Arial" ))
+		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
+		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "50/11" (rect 89 147 116 161)(font "Arial" ))
+		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
+		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "40/11" (rect 89 165 116 179)(font "Arial" ))
+		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
+		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "109/33" (rect 85 183 118 197)(font "Arial" ))
+		(text "0.00" (rect 136 183 157 197)(font "Arial" ))
+		(text "50.00" (rect 178 183 205 197)(font "Arial" ))
+		(text "c4" (rect 63 201 75 215)(font "Arial" ))
+		(text "109/39" (rect 85 201 118 215)(font "Arial" ))
+		(text "0.00" (rect 136 201 157 215)(font "Arial" ))
+		(text "50.00" (rect 178 201 205 215)(font "Arial" ))
+		(line (pt 0 0)(pt 281 0)(line_width 1))
+		(line (pt 281 0)(pt 281 249)(line_width 1))
+		(line (pt 0 249)(pt 281 249)(line_width 1))
+		(line (pt 0 0)(pt 0 249)(line_width 1))
+		(line (pt 56 108)(pt 215 108)(line_width 1))
+		(line (pt 56 125)(pt 215 125)(line_width 1))
+		(line (pt 56 143)(pt 215 143)(line_width 1))
+		(line (pt 56 161)(pt 215 161)(line_width 1))
+		(line (pt 56 179)(pt 215 179)(line_width 1))
+		(line (pt 56 197)(pt 215 197)(line_width 1))
+		(line (pt 56 215)(pt 215 215)(line_width 1))
+		(line (pt 56 108)(pt 56 215)(line_width 1))
+		(line (pt 82 108)(pt 82 215)(line_width 3))
+		(line (pt 125 108)(pt 125 215)(line_width 3))
+		(line (pt 170 108)(pt 170 215)(line_width 3))
+		(line (pt 214 108)(pt 214 215)(line_width 1))
+		(line (pt 48 56)(pt 248 56)(line_width 1))
+		(line (pt 248 56)(pt 248 232)(line_width 1))
+		(line (pt 48 232)(pt 248 232)(line_width 1))
+		(line (pt 48 56)(pt 48 232)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll0.cmp b/FPGA_by_Fredi/altpll0.cmp
new file mode 100644
index 0000000..5097275
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll0
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll0.inc b/FPGA_by_Fredi/altpll0.inc
new file mode 100644
index 0000000..933af49
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll0 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3,
+	c4
+);
diff --git a/FPGA_by_Fredi/altpll0.ppf b/FPGA_by_Fredi/altpll0.ppf
new file mode 100644
index 0000000..521a742
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.ppf
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll0" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll0.qip b/FPGA_by_Fredi/altpll0.qip
new file mode 100644
index 0000000..1b4cd11
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"]
diff --git a/FPGA_by_Fredi/altpll0.vhd b/FPGA_by_Fredi/altpll0.vhd
new file mode 100644
index 0000000..b035bf5
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0.vhd
@@ -0,0 +1,477 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll0.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll0 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+END altpll0;
+
+
+ARCHITECTURE SYN OF altpll0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(4);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	c4    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 16,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 11,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 50,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 11,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 40,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 33,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 109,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 39,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 109,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll0_waveforms.html b/FPGA_by_Fredi/altpll0_waveforms.html
new file mode 100644
index 0000000..80e236a
--- /dev/null
+++ b/FPGA_by_Fredi/altpll0_waveforms.html
@@ -0,0 +1,10 @@
+<html>
+<head>
+<title>Sample Waveforms for "altpll0.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "altpll0.vhd" </CENTER></h2>
+<P></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/altpll1.bsf b/FPGA_by_Fredi/altpll1.bsf
new file mode 100644
index 0000000..d1e4a9e
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.bsf
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 328 216)
+	(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 197 31 212)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 328 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
+		(line (pt 328 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 328 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
+		(line (pt 328 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 328 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
+		(line (pt 328 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 328 144)
+		(output)
+		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+		(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
+		(line (pt 328 144)(pt 272 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
+		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "1/66" (rect 92 129 113 143)(font "Arial" ))
+		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
+		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "67/900" (rect 85 147 118 161)(font "Arial" ))
+		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
+		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "67/90" (rect 89 165 116 179)(font "Arial" ))
+		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
+		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
+		(line (pt 0 0)(pt 329 0)(line_width 1))
+		(line (pt 329 0)(pt 329 217)(line_width 1))
+		(line (pt 0 217)(pt 329 217)(line_width 1))
+		(line (pt 0 0)(pt 0 217)(line_width 1))
+		(line (pt 56 108)(pt 215 108)(line_width 1))
+		(line (pt 56 125)(pt 215 125)(line_width 1))
+		(line (pt 56 143)(pt 215 143)(line_width 1))
+		(line (pt 56 161)(pt 215 161)(line_width 1))
+		(line (pt 56 179)(pt 215 179)(line_width 1))
+		(line (pt 56 108)(pt 56 179)(line_width 1))
+		(line (pt 82 108)(pt 82 179)(line_width 3))
+		(line (pt 125 108)(pt 125 179)(line_width 3))
+		(line (pt 170 108)(pt 170 179)(line_width 3))
+		(line (pt 214 108)(pt 214 179)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 200)(line_width 1))
+		(line (pt 48 200)(pt 272 200)(line_width 1))
+		(line (pt 48 56)(pt 48 200)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll1.cmp b/FPGA_by_Fredi/altpll1.cmp
new file mode 100644
index 0000000..300576d
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.cmp
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll1
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll1.inc b/FPGA_by_Fredi/altpll1.inc
new file mode 100644
index 0000000..0923ad2
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll1 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	locked
+);
diff --git a/FPGA_by_Fredi/altpll1.ppf b/FPGA_by_Fredi/altpll1.ppf
new file mode 100644
index 0000000..0f38a28
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll1.qip b/FPGA_by_Fredi/altpll1.qip
new file mode 100644
index 0000000..ec03f05
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
diff --git a/FPGA_by_Fredi/altpll1.vhd b/FPGA_by_Fredi/altpll1.vhd
new file mode 100644
index 0000000..ab9bfaf
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1.vhd
@@ -0,0 +1,423 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll1.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll1 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END altpll1;
+
+
+ARCHITECTURE SYN OF altpll1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	locked    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 66,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 1,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 900,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 67,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 90,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 67,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire4
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll1_waveforms.html b/FPGA_by_Fredi/altpll1_waveforms.html
new file mode 100644
index 0000000..1382a12
--- /dev/null
+++ b/FPGA_by_Fredi/altpll1_waveforms.html
@@ -0,0 +1,10 @@
+<html>
+<head>
+<title>Sample Waveforms for "altpll1.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "altpll1.vhd" </CENTER></h2>
+<P></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/altpll2.bsf b/FPGA_by_Fredi/altpll2.bsf
new file mode 100644
index 0000000..79679d7
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.bsf
@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 304 248)
+	(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 229 31 244)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 304 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
+		(line (pt 304 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 304 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
+		(line (pt 304 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 304 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
+		(line (pt 304 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 304 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
+		(line (pt 304 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 304 168)
+		(output)
+		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
+		(line (pt 304 168)(pt 272 168)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
+		(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "4/1" (rect 91 129 106 143)(font "Arial" ))
+		(text "240.00" (rect 120 129 153 143)(font "Arial" ))
+		(text "50.00" (rect 169 129 196 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "4/1" (rect 91 147 106 161)(font "Arial" ))
+		(text "0.00" (rect 127 147 148 161)(font "Arial" ))
+		(text "50.00" (rect 169 147 196 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "4/1" (rect 91 165 106 179)(font "Arial" ))
+		(text "180.00" (rect 120 165 153 179)(font "Arial" ))
+		(text "50.00" (rect 169 165 196 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "4/1" (rect 91 183 106 197)(font "Arial" ))
+		(text "105.00" (rect 120 183 153 197)(font "Arial" ))
+		(text "50.00" (rect 169 183 196 197)(font "Arial" ))
+		(text "c4" (rect 63 201 75 215)(font "Arial" ))
+		(text "2/1" (rect 91 201 106 215)(font "Arial" ))
+		(text "270.00" (rect 120 201 153 215)(font "Arial" ))
+		(text "50.00" (rect 169 201 196 215)(font "Arial" ))
+		(line (pt 0 0)(pt 305 0)(line_width 1))
+		(line (pt 305 0)(pt 305 249)(line_width 1))
+		(line (pt 0 249)(pt 305 249)(line_width 1))
+		(line (pt 0 0)(pt 0 249)(line_width 1))
+		(line (pt 56 108)(pt 206 108)(line_width 1))
+		(line (pt 56 125)(pt 206 125)(line_width 1))
+		(line (pt 56 143)(pt 206 143)(line_width 1))
+		(line (pt 56 161)(pt 206 161)(line_width 1))
+		(line (pt 56 179)(pt 206 179)(line_width 1))
+		(line (pt 56 197)(pt 206 197)(line_width 1))
+		(line (pt 56 215)(pt 206 215)(line_width 1))
+		(line (pt 56 108)(pt 56 215)(line_width 1))
+		(line (pt 82 108)(pt 82 215)(line_width 3))
+		(line (pt 116 108)(pt 116 215)(line_width 3))
+		(line (pt 161 108)(pt 161 215)(line_width 3))
+		(line (pt 205 108)(pt 205 215)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 232)(line_width 1))
+		(line (pt 48 232)(pt 272 232)(line_width 1))
+		(line (pt 48 56)(pt 48 232)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll2.cmp b/FPGA_by_Fredi/altpll2.cmp
new file mode 100644
index 0000000..c6fe758
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll2
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll2.inc b/FPGA_by_Fredi/altpll2.inc
new file mode 100644
index 0000000..e75913b
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll2 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3,
+	c4
+);
diff --git a/FPGA_by_Fredi/altpll2.ppf b/FPGA_by_Fredi/altpll2.ppf
new file mode 100644
index 0000000..b1c71cc
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.ppf
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll2.qip b/FPGA_by_Fredi/altpll2.qip
new file mode 100644
index 0000000..74cc641
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
diff --git a/FPGA_by_Fredi/altpll2.vhd b/FPGA_by_Fredi/altpll2.vhd
new file mode 100644
index 0000000..2c55f08
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2.vhd
@@ -0,0 +1,477 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll2.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll2 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+END altpll2;
+
+
+ARCHITECTURE SYN OF altpll2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(4);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	c4    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 4,
+		clk0_phase_shift => "5051",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 4,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 4,
+		clk2_phase_shift => "3788",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "2210",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "11364",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll2_waveforms.html b/FPGA_by_Fredi/altpll2_waveforms.html
new file mode 100644
index 0000000..1932527
--- /dev/null
+++ b/FPGA_by_Fredi/altpll2_waveforms.html
@@ -0,0 +1,10 @@
+<html>
+<head>
+<title>Sample Waveforms for "altpll2.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "altpll2.vhd" </CENTER></h2>
+<P></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/altpll3.bsf b/FPGA_by_Fredi/altpll3.bsf
new file mode 100644
index 0000000..da30b0c
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.bsf
@@ -0,0 +1,105 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 304 232)
+	(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 304 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
+		(line (pt 304 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 304 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
+		(line (pt 304 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 304 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
+		(line (pt 304 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 304 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
+		(line (pt 304 144)(pt 272 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
+		(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "2/33" (rect 88 129 109 143)(font "Arial" ))
+		(text "0.00" (rect 129 129 150 143)(font "Arial" ))
+		(text "50.00" (rect 171 129 198 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "16/33" (rect 85 147 112 161)(font "Arial" ))
+		(text "0.00" (rect 129 147 150 161)(font "Arial" ))
+		(text "50.00" (rect 171 147 198 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "25/33" (rect 85 165 112 179)(font "Arial" ))
+		(text "0.00" (rect 129 165 150 179)(font "Arial" ))
+		(text "50.00" (rect 171 165 198 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "16/11" (rect 85 183 112 197)(font "Arial" ))
+		(text "0.00" (rect 129 183 150 197)(font "Arial" ))
+		(text "50.00" (rect 171 183 198 197)(font "Arial" ))
+		(line (pt 0 0)(pt 305 0)(line_width 1))
+		(line (pt 305 0)(pt 305 233)(line_width 1))
+		(line (pt 0 233)(pt 305 233)(line_width 1))
+		(line (pt 0 0)(pt 0 233)(line_width 1))
+		(line (pt 56 108)(pt 208 108)(line_width 1))
+		(line (pt 56 125)(pt 208 125)(line_width 1))
+		(line (pt 56 143)(pt 208 143)(line_width 1))
+		(line (pt 56 161)(pt 208 161)(line_width 1))
+		(line (pt 56 179)(pt 208 179)(line_width 1))
+		(line (pt 56 197)(pt 208 197)(line_width 1))
+		(line (pt 56 108)(pt 56 197)(line_width 1))
+		(line (pt 82 108)(pt 82 197)(line_width 3))
+		(line (pt 118 108)(pt 118 197)(line_width 3))
+		(line (pt 163 108)(pt 163 197)(line_width 3))
+		(line (pt 207 108)(pt 207 197)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 216)(line_width 1))
+		(line (pt 48 216)(pt 272 216)(line_width 1))
+		(line (pt 48 56)(pt 48 216)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll3.cmp b/FPGA_by_Fredi/altpll3.cmp
new file mode 100644
index 0000000..44b3f2e
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.cmp
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll3
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll3.inc b/FPGA_by_Fredi/altpll3.inc
new file mode 100644
index 0000000..160ecad
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll3 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3
+);
diff --git a/FPGA_by_Fredi/altpll3.ppf b/FPGA_by_Fredi/altpll3.ppf
new file mode 100644
index 0000000..2a7b695
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll3.qip b/FPGA_by_Fredi/altpll3.qip
new file mode 100644
index 0000000..8dd2955
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]
diff --git a/FPGA_by_Fredi/altpll3.vhd b/FPGA_by_Fredi/altpll3.vhd
new file mode 100644
index 0000000..6ead1f5
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3.vhd
@@ -0,0 +1,445 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll3.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll3 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END altpll3;
+
+
+ARCHITECTURE SYN OF altpll3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 33,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 2,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 33,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 16,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 33,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 25,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 11,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 16,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK1",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll3_waveforms.html b/FPGA_by_Fredi/altpll3_waveforms.html
new file mode 100644
index 0000000..3f6367c
--- /dev/null
+++ b/FPGA_by_Fredi/altpll3_waveforms.html
@@ -0,0 +1,10 @@
+<html>
+<head>
+<title>Sample Waveforms for "altpll3.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "altpll3.vhd" </CENTER></h2>
+<P></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/altpll4.bsf b/FPGA_by_Fredi/altpll4.bsf
new file mode 100644
index 0000000..e071d43
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.bsf
@@ -0,0 +1,125 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 376 232)
+	(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 88 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 88 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 88 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 88 144)(line_width 1))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 88 168)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 88 192)(line_width 1))
+	)
+	(port
+		(pt 376 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
+		(line (pt 376 72)(pt 288 72)(line_width 1))
+	)
+	(port
+		(pt 376 96)
+		(output)
+		(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
+		(line (pt 376 96)(pt 288 96)(line_width 1))
+	)
+	(port
+		(pt 376 120)
+		(output)
+		(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
+		(line (pt 376 120)(pt 288 120)(line_width 1))
+	)
+	(port
+		(pt 376 144)
+		(output)
+		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+		(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
+		(line (pt 376 144)(pt 288 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
+		(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
+		(text "Clk " (rect 99 167 116 181)(font "Arial" ))
+		(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
+		(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
+		(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
+		(text "c0" (rect 103 185 115 199)(font "Arial" ))
+		(text "2/1" (rect 131 185 146 199)(font "Arial" ))
+		(text "0.00" (rect 167 185 188 199)(font "Arial" ))
+		(text "50.00" (rect 209 185 236 199)(font "Arial" ))
+		(line (pt 0 0)(pt 377 0)(line_width 1))
+		(line (pt 377 0)(pt 377 233)(line_width 1))
+		(line (pt 0 233)(pt 377 233)(line_width 1))
+		(line (pt 0 0)(pt 0 233)(line_width 1))
+		(line (pt 96 164)(pt 246 164)(line_width 1))
+		(line (pt 96 181)(pt 246 181)(line_width 1))
+		(line (pt 96 199)(pt 246 199)(line_width 1))
+		(line (pt 96 164)(pt 96 199)(line_width 1))
+		(line (pt 122 164)(pt 122 199)(line_width 3))
+		(line (pt 156 164)(pt 156 199)(line_width 3))
+		(line (pt 201 164)(pt 201 199)(line_width 3))
+		(line (pt 245 164)(pt 245 199)(line_width 1))
+		(line (pt 88 56)(pt 288 56)(line_width 1))
+		(line (pt 288 56)(pt 288 216)(line_width 1))
+		(line (pt 88 216)(pt 288 216)(line_width 1))
+		(line (pt 88 56)(pt 88 216)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll4.cmp b/FPGA_by_Fredi/altpll4.cmp
new file mode 100644
index 0000000..83b3c1e
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.cmp
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll4
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		configupdate		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		scanclk		: IN STD_LOGIC  := '1';
+		scanclkena		: IN STD_LOGIC  := '0';
+		scandata		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC ;
+		scandataout		: OUT STD_LOGIC ;
+		scandone		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll4.inc b/FPGA_by_Fredi/altpll4.inc
new file mode 100644
index 0000000..39f54c9
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll4 
+(
+	areset,
+	configupdate,
+	inclk0,
+	scanclk,
+	scanclkena,
+	scandata
+)
+
+RETURNS (
+	c0,
+	locked,
+	scandataout,
+	scandone
+);
diff --git a/FPGA_by_Fredi/altpll4.mif b/FPGA_by_Fredi/altpll4.mif
new file mode 100644
index 0000000..e50eda2
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: C:\FireBee\FPGA\altpll4.mif
+--    Generated: Mon Dec 06 01:47:24 2010
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 6 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   0;
+	42   :   1;
+	43   :   1;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 6 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   0;
+	51   :   1;
+	52   :   1;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 3 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   0;
+	61   :   1;
+	62   :   1;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 3 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   0;
+	70   :   1;
+	71   :   1;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/FPGA_by_Fredi/altpll4.ppf b/FPGA_by_Fredi/altpll4.ppf
new file mode 100644
index 0000000..541ce91
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.ppf
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_by_Fredi/altpll4.qip b/FPGA_by_Fredi/altpll4.qip
new file mode 100644
index 0000000..f44acdc
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]
diff --git a/FPGA_by_Fredi/altpll4.tdf b/FPGA_by_Fredi/altpll4.tdf
new file mode 100644
index 0000000..3ec77d4
--- /dev/null
+++ b/FPGA_by_Fredi/altpll4.tdf
@@ -0,0 +1,298 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll4.tdf
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "altpll.inc";
+
+
+
+SUBDESIGN altpll4
+(
+	areset	 : INPUT = GND;
+	configupdate	 : INPUT = GND;
+	inclk0	 : INPUT = GND;
+	scanclk	 : INPUT = VCC;
+	scanclkena	 : INPUT = GND;
+	scandata	 : INPUT = GND;
+	c0	 : OUTPUT;
+	locked	 : OUTPUT;
+	scandataout	 : OUTPUT;
+	scandone	 : OUTPUT;
+)
+
+VARIABLE
+
+	altpll_component : altpll WITH (
+			BANDWIDTH_TYPE = "AUTO",
+			CLK0_DIVIDE_BY = 1,
+			CLK0_DUTY_CYCLE = 50,
+			CLK0_MULTIPLY_BY = 2,
+			CLK0_PHASE_SHIFT = "0",
+			COMPENSATE_CLOCK = "CLK0",
+			INCLK0_INPUT_FREQUENCY = 20833,
+			INTENDED_DEVICE_FAMILY = "Cyclone III",
+			LPM_TYPE = "altpll",
+			OPERATION_MODE = "NORMAL",
+			PLL_TYPE = "AUTO",
+			PORT_ACTIVECLOCK = "PORT_UNUSED",
+			PORT_ARESET = "PORT_USED",
+			PORT_CLKBAD0 = "PORT_UNUSED",
+			PORT_CLKBAD1 = "PORT_UNUSED",
+			PORT_CLKLOSS = "PORT_UNUSED",
+			PORT_CLKSWITCH = "PORT_UNUSED",
+			PORT_CONFIGUPDATE = "PORT_USED",
+			PORT_FBIN = "PORT_UNUSED",
+			PORT_INCLK0 = "PORT_USED",
+			PORT_INCLK1 = "PORT_UNUSED",
+			PORT_LOCKED = "PORT_USED",
+			PORT_PFDENA = "PORT_UNUSED",
+			PORT_PHASECOUNTERSELECT = "PORT_UNUSED",
+			PORT_PHASEDONE = "PORT_UNUSED",
+			PORT_PHASESTEP = "PORT_UNUSED",
+			PORT_PHASEUPDOWN = "PORT_UNUSED",
+			PORT_PLLENA = "PORT_UNUSED",
+			PORT_SCANACLR = "PORT_UNUSED",
+			PORT_SCANCLK = "PORT_USED",
+			PORT_SCANCLKENA = "PORT_USED",
+			PORT_SCANDATA = "PORT_USED",
+			PORT_SCANDATAOUT = "PORT_USED",
+			PORT_SCANDONE = "PORT_USED",
+			PORT_SCANREAD = "PORT_UNUSED",
+			PORT_SCANWRITE = "PORT_UNUSED",
+			PORT_clk0 = "PORT_USED",
+			PORT_clk1 = "PORT_UNUSED",
+			PORT_clk2 = "PORT_UNUSED",
+			PORT_clk3 = "PORT_UNUSED",
+			PORT_clk4 = "PORT_UNUSED",
+			PORT_clk5 = "PORT_UNUSED",
+			PORT_clkena0 = "PORT_UNUSED",
+			PORT_clkena1 = "PORT_UNUSED",
+			PORT_clkena2 = "PORT_UNUSED",
+			PORT_clkena3 = "PORT_UNUSED",
+			PORT_clkena4 = "PORT_UNUSED",
+			PORT_clkena5 = "PORT_UNUSED",
+			PORT_extclk0 = "PORT_UNUSED",
+			PORT_extclk1 = "PORT_UNUSED",
+			PORT_extclk2 = "PORT_UNUSED",
+			PORT_extclk3 = "PORT_UNUSED",
+			SELF_RESET_ON_LOSS_LOCK = "OFF",
+			WIDTH_CLOCK = 5,
+			scan_chain_mif_file = "altpll4.mif"
+			);
+
+BEGIN
+
+	c0 = altpll_component.clk[0..0];
+	scandone = altpll_component.scandone;
+	scandataout = altpll_component.scandataout;
+	locked = altpll_component.locked;
+	altpll_component.scanclkena = scanclkena;
+	altpll_component.inclk[0..0] = inclk0;
+	altpll_component.inclk[1..1] = GND;
+	altpll_component.scandata = scandata;
+	altpll_component.areset = areset;
+	altpll_component.scanclk = scanclk;
+	altpll_component.configupdate = configupdate;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
+-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/altpll_reconfig0.bsf b/FPGA_by_Fredi/altpll_reconfig0.bsf
new file mode 100644
index 0000000..452f320
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig0.bsf
@@ -0,0 +1,162 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 216 296)
+	(text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 277 31 292)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 16 168)(line_width 1))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 16 184)(line_width 1))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208)(line_width 1))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224)(line_width 1))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 16 248)(line_width 1))
+	)
+	(port
+		(pt 216 40)
+		(output)
+		(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
+		(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
+		(line (pt 216 40)(pt 200 40)(line_width 1))
+	)
+	(port
+		(pt 216 96)
+		(output)
+		(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
+		(line (pt 216 96)(pt 200 96)(line_width 3))
+	)
+	(port
+		(pt 216 152)
+		(output)
+		(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
+		(line (pt 216 152)(pt 200 152)(line_width 1))
+	)
+	(port
+		(pt 216 168)
+		(output)
+		(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
+		(line (pt 216 168)(pt 200 168)(line_width 1))
+	)
+	(port
+		(pt 216 200)
+		(output)
+		(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
+		(line (pt 216 200)(pt 200 200)(line_width 1))
+	)
+	(port
+		(pt 216 216)
+		(output)
+		(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
+		(line (pt 216 216)(pt 200 216)(line_width 1))
+	)
+	(port
+		(pt 216 248)
+		(output)
+		(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
+		(line (pt 216 248)(pt 200 248)(line_width 1))
+	)
+	(drawing
+		(line (pt 0 0)(pt 217 0)(line_width 1))
+		(line (pt 217 0)(pt 217 297)(line_width 1))
+		(line (pt 0 297)(pt 217 297)(line_width 1))
+		(line (pt 0 0)(pt 0 297)(line_width 1))
+		(line (pt 16 24)(pt 201 24)(line_width 1))
+		(line (pt 201 24)(pt 201 273)(line_width 1))
+		(line (pt 16 273)(pt 201 273)(line_width 1))
+		(line (pt 16 24)(pt 16 273)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll_reconfig0.qip b/FPGA_by_Fredi/altpll_reconfig0.qip
new file mode 100644
index 0000000..3194459
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"]
diff --git a/FPGA_by_Fredi/altpll_reconfig1.bsf b/FPGA_by_Fredi/altpll_reconfig1.bsf
new file mode 100644
index 0000000..f896607
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1.bsf
@@ -0,0 +1,162 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 216 296)
+	(text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 277 31 292)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 16 168)(line_width 1))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 16 184)(line_width 1))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208)(line_width 1))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224)(line_width 1))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 16 248)(line_width 1))
+	)
+	(port
+		(pt 216 40)
+		(output)
+		(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
+		(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
+		(line (pt 216 40)(pt 200 40)(line_width 1))
+	)
+	(port
+		(pt 216 96)
+		(output)
+		(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
+		(line (pt 216 96)(pt 200 96)(line_width 3))
+	)
+	(port
+		(pt 216 152)
+		(output)
+		(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
+		(line (pt 216 152)(pt 200 152)(line_width 1))
+	)
+	(port
+		(pt 216 168)
+		(output)
+		(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
+		(line (pt 216 168)(pt 200 168)(line_width 1))
+	)
+	(port
+		(pt 216 200)
+		(output)
+		(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
+		(line (pt 216 200)(pt 200 200)(line_width 1))
+	)
+	(port
+		(pt 216 216)
+		(output)
+		(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
+		(line (pt 216 216)(pt 200 216)(line_width 1))
+	)
+	(port
+		(pt 216 248)
+		(output)
+		(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
+		(line (pt 216 248)(pt 200 248)(line_width 1))
+	)
+	(drawing
+		(line (pt 0 0)(pt 217 0)(line_width 1))
+		(line (pt 217 0)(pt 217 297)(line_width 1))
+		(line (pt 0 297)(pt 217 297)(line_width 1))
+		(line (pt 0 0)(pt 0 297)(line_width 1))
+		(line (pt 16 24)(pt 201 24)(line_width 1))
+		(line (pt 201 24)(pt 201 273)(line_width 1))
+		(line (pt 16 273)(pt 201 273)(line_width 1))
+		(line (pt 16 24)(pt 16 273)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altpll_reconfig1.cmp b/FPGA_by_Fredi/altpll_reconfig1.cmp
new file mode 100644
index 0000000..7d409d0
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1.cmp
@@ -0,0 +1,38 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altpll_reconfig1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		counter_param		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		counter_type		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		data_in		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset_in		: IN STD_LOGIC  := '0';
+		pll_scandataout		: IN STD_LOGIC ;
+		pll_scandone		: IN STD_LOGIC ;
+		read_param		: IN STD_LOGIC ;
+		reconfig		: IN STD_LOGIC ;
+		reset		: IN STD_LOGIC ;
+		write_param		: IN STD_LOGIC ;
+		busy		: OUT STD_LOGIC ;
+		data_out		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset		: OUT STD_LOGIC ;
+		pll_configupdate		: OUT STD_LOGIC ;
+		pll_scanclk		: OUT STD_LOGIC ;
+		pll_scanclkena		: OUT STD_LOGIC ;
+		pll_scandata		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/altpll_reconfig1.inc b/FPGA_by_Fredi/altpll_reconfig1.inc
new file mode 100644
index 0000000..c1a6e65
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1.inc
@@ -0,0 +1,39 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll_reconfig1 
+(
+	clock,
+	counter_param[2..0],
+	counter_type[3..0],
+	data_in[8..0],
+	pll_areset_in,
+	pll_scandataout,
+	pll_scandone,
+	read_param,
+	reconfig,
+	reset,
+	write_param
+)
+
+RETURNS (
+	busy,
+	data_out[8..0],
+	pll_areset,
+	pll_configupdate,
+	pll_scanclk,
+	pll_scanclkena,
+	pll_scandata
+);
diff --git a/FPGA_by_Fredi/altpll_reconfig1.qip b/FPGA_by_Fredi/altpll_reconfig1.qip
new file mode 100644
index 0000000..713a3c3
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"]
diff --git a/FPGA_by_Fredi/altpll_reconfig1.tdf b/FPGA_by_Fredi/altpll_reconfig1.tdf
new file mode 100644
index 0000000..82ad4ff
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1.tdf
@@ -0,0 +1,144 @@
+-- megafunction wizard: %ALTPLL_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll_reconfig 
+
+-- ============================================================
+-- File Name: altpll_reconfig1.tdf
+-- Megafunction Name(s):
+-- 			altpll_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;cycloneiii;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+-- Clearbox generated function header
+FUNCTION altpll_reconfig1_pllrcfg_t4q (clock, counter_param[2..0], counter_type[3..0], data_in[8..0], pll_areset_in, pll_scandataout, pll_scandone, read_param, reconfig, reset, write_param)
+RETURNS ( busy, data_out[8..0], pll_areset, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata);
+
+
+
+
+SUBDESIGN altpll_reconfig1
+(
+	clock	 : INPUT;
+	counter_param[2..0]	 : INPUT;
+	counter_type[3..0]	 : INPUT;
+	data_in[8..0]	 : INPUT;
+	pll_areset_in	 : INPUT = GND;
+	pll_scandataout	 : INPUT;
+	pll_scandone	 : INPUT;
+	read_param	 : INPUT;
+	reconfig	 : INPUT;
+	reset	 : INPUT;
+	write_param	 : INPUT;
+	busy	 : OUTPUT;
+	data_out[8..0]	 : OUTPUT;
+	pll_areset	 : OUTPUT;
+	pll_configupdate	 : OUTPUT;
+	pll_scanclk	 : OUTPUT;
+	pll_scanclkena	 : OUTPUT;
+	pll_scandata	 : OUTPUT;
+)
+
+VARIABLE
+
+	altpll_reconfig1_pllrcfg_t4q_component : altpll_reconfig1_pllrcfg_t4q;
+
+BEGIN
+
+	pll_areset = altpll_reconfig1_pllrcfg_t4q_component.pll_areset;
+	pll_scanclkena = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclkena;
+	pll_scanclk = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclk;
+	busy = altpll_reconfig1_pllrcfg_t4q_component.busy;
+	data_out[8..0] = altpll_reconfig1_pllrcfg_t4q_component.data_out[8..0];
+	pll_scandata = altpll_reconfig1_pllrcfg_t4q_component.pll_scandata;
+	pll_configupdate = altpll_reconfig1_pllrcfg_t4q_component.pll_configupdate;
+	altpll_reconfig1_pllrcfg_t4q_component.reconfig = reconfig;
+	altpll_reconfig1_pllrcfg_t4q_component.counter_type[3..0] = counter_type[3..0];
+	altpll_reconfig1_pllrcfg_t4q_component.pll_scandone = pll_scandone;
+	altpll_reconfig1_pllrcfg_t4q_component.pll_scandataout = pll_scandataout;
+	altpll_reconfig1_pllrcfg_t4q_component.pll_areset_in = pll_areset_in;
+	altpll_reconfig1_pllrcfg_t4q_component.read_param = read_param;
+	altpll_reconfig1_pllrcfg_t4q_component.reset = reset;
+	altpll_reconfig1_pllrcfg_t4q_component.data_in[8..0] = data_in[8..0];
+	altpll_reconfig1_pllrcfg_t4q_component.clock = clock;
+	altpll_reconfig1_pllrcfg_t4q_component.counter_param[2..0] = counter_param[2..0];
+	altpll_reconfig1_pllrcfg_t4q_component.write_param = write_param;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
+-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
+-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
+-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
+-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
+-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
+-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
+-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
+-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
+-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
+-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
+-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
+-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
+-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
+-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
+-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
+-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
+-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
+-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
+-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
+-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
+-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
+-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
+-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
+-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: cycloneiii
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_bju.tdf b/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_bju.tdf
new file mode 100644
index 0000000..81695ae
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_bju.tdf
@@ -0,0 +1,583 @@
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./altpll4.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
+--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+include "altsyncram.inc";
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS)
+RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]);
+FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT)
+RETURNS ( aeb, agb, ageb, alb, aleb, aneb);
+FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
+WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width)
+RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);
+FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable)
+WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH)
+RETURNS ( eq[LPM_DECODES-1..0]);
+
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 
+OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW";
+
+SUBDESIGN altpll_reconfig1_pllrcfg_bju
+( 
+	busy	:	output;
+	clock	:	input;
+	counter_param[2..0]	:	input;
+	counter_type[3..0]	:	input;
+	data_in[8..0]	:	input;
+	data_out[8..0]	:	output;
+	pll_areset	:	output;
+	pll_areset_in	:	input;
+	pll_configupdate	:	output;
+	pll_scanclk	:	output;
+	pll_scanclkena	:	output;
+	pll_scandata	:	output;
+	pll_scandataout	:	input;
+	pll_scandone	:	input;
+	read_param	:	input;
+	reconfig	:	input;
+	reset	:	input;
+	write_param	:	input;
+) 
+VARIABLE 
+	altsyncram4 : altsyncram
+		WITH (
+			INIT_FILE = "./altpll4.mif",
+			NUMWORDS_A = 144,
+			OPERATION_MODE = "SINGLE_PORT",
+			WIDTH_A = 1,
+			WIDTH_BYTEENA_A = 1,
+			WIDTHAD_A = 8
+		);
+	le_comb10 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "F0F0",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb8 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "AAAA",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb9 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "CCCC",
+			SUM_LUTC_INPUT = "datac"
+		);
+	areset_init_state_1 : dffe;
+	areset_state : dffe;
+	C0_data_state : dffe;
+	C0_ena_state : dffe;
+	C1_data_state : dffe;
+	C1_ena_state : dffe;
+	C2_data_state : dffe;
+	C2_ena_state : dffe;
+	C3_data_state : dffe;
+	C3_ena_state : dffe;
+	C4_data_state : dffe;
+	C4_ena_state : dffe;
+	configupdate2_state : dffe;
+	configupdate3_state : dffe;
+	configupdate_state : dffe;
+	counter_param_latch_reg[2..0] : dffe;
+	counter_type_latch_reg[3..0] : dffe;
+	idle_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	nominal_data[17..0] : dffe;
+	read_data_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_counter_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_post_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_ena_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_wait_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reset_state : dffe
+		WITH (
+			power_up = "high"
+		);
+	shift_reg[17..0] : dffeas;
+	tmp_nominal_data_out_state : dffe;
+	tmp_seq_ena_state : dffe;
+	write_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	add_sub5 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 9
+		);
+	add_sub6 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cmpr7 : lpm_compare
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cntr1 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr12 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr13 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 6
+		);
+	cntr14 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	cntr15 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr2 : lpm_counter
+		WITH (
+			lpm_direction = "UP",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr3 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	decode11 : lpm_decode
+		WITH (
+			LPM_DECODES = 5,
+			LPM_WIDTH = 3
+		);
+	addr_counter_enable	: WIRE;
+	addr_counter_out[7..0]	: WIRE;
+	addr_counter_sload	: WIRE;
+	addr_counter_sload_value[7..0]	: WIRE;
+	addr_decoder_out[7..0]	: WIRE;
+	c0_wire[7..0]	: WIRE;
+	c1_wire[7..0]	: WIRE;
+	c2_wire[7..0]	: WIRE;
+	c3_wire[7..0]	: WIRE;
+	c4_wire[7..0]	: WIRE;
+	counter_param_latch[2..0]	: WIRE;
+	counter_type_latch[3..0]	: WIRE;
+	cuda_combout_wire[2..0]	: WIRE;
+	dummy_scandataout	: WIRE;
+	encode_out[2..0]	: WIRE;
+	input_latch_enable	: WIRE;
+	power_up	: WIRE;
+	read_addr_counter_enable	: WIRE;
+	read_addr_counter_out[7..0]	: WIRE;
+	read_addr_counter_sload	: WIRE;
+	read_addr_counter_sload_value[7..0]	: WIRE;
+	read_addr_decoder_out[7..0]	: WIRE;
+	read_nominal_out	: WIRE;
+	reconfig_addr_counter_enable	: WIRE;
+	reconfig_addr_counter_out[7..0]	: WIRE;
+	reconfig_addr_counter_sload	: WIRE;
+	reconfig_addr_counter_sload_value[7..0]	: WIRE;
+	reconfig_done	: WIRE;
+	reconfig_post_done	: WIRE;
+	reconfig_width_counter_done	: WIRE;
+	reconfig_width_counter_enable	: WIRE;
+	reconfig_width_counter_sload	: WIRE;
+	reconfig_width_counter_sload_value[5..0]	: WIRE;
+	rotate_addr_counter_enable	: WIRE;
+	rotate_addr_counter_out[7..0]	: WIRE;
+	rotate_addr_counter_sload	: WIRE;
+	rotate_addr_counter_sload_value[7..0]	: WIRE;
+	rotate_decoder_wires[4..0]	: WIRE;
+	rotate_width_counter_done	: WIRE;
+	rotate_width_counter_enable	: WIRE;
+	rotate_width_counter_sload	: WIRE;
+	rotate_width_counter_sload_value[4..0]	: WIRE;
+	scan_cache_address[7..0]	: WIRE;
+	scan_cache_in	: WIRE;
+	scan_cache_out	: WIRE;
+	scan_cache_write_enable	: WIRE;
+	sel_param_bypass_LF_unused	: WIRE;
+	sel_param_c	: WIRE;
+	sel_param_high_i_postscale	: WIRE;
+	sel_param_low_r	: WIRE;
+	sel_param_nominal_count	: WIRE;
+	sel_param_odd_CP_unused	: WIRE;
+	sel_type_c0	: WIRE;
+	sel_type_c1	: WIRE;
+	sel_type_c2	: WIRE;
+	sel_type_c3	: WIRE;
+	sel_type_c4	: WIRE;
+	sel_type_cplf	: WIRE;
+	sel_type_m	: WIRE;
+	sel_type_n	: WIRE;
+	sel_type_vco	: WIRE;
+	seq_addr_wire[7..0]	: WIRE;
+	seq_sload_value[5..0]	: WIRE;
+	shift_reg_clear	: WIRE;
+	shift_reg_load_enable	: WIRE;
+	shift_reg_load_nominal_enable	: WIRE;
+	shift_reg_serial_in	: WIRE;
+	shift_reg_serial_out	: WIRE;
+	shift_reg_shift_enable	: WIRE;
+	shift_reg_shift_nominal_enable	: WIRE;
+	shift_reg_width_select[7..0]	: WIRE;
+	w1565w	: WIRE;
+	w1592w	: WIRE;
+	w64w	: WIRE;
+	width_counter_done	: WIRE;
+	width_counter_enable	: WIRE;
+	width_counter_sload	: WIRE;
+	width_counter_sload_value[4..0]	: WIRE;
+	width_decoder_out[4..0]	: WIRE;
+	width_decoder_select[7..0]	: WIRE;
+	write_from_rom	: NODE;
+
+BEGIN 
+	altsyncram4.address_a[] = scan_cache_address[];
+	altsyncram4.clock0 = clock;
+	altsyncram4.data_a[] = ( scan_cache_in);
+	altsyncram4.wren_a = scan_cache_write_enable;
+	le_comb10.dataa = encode_out[0..0];
+	le_comb10.datab = encode_out[1..1];
+	le_comb10.datac = encode_out[2..2];
+	le_comb8.dataa = encode_out[0..0];
+	le_comb8.datab = encode_out[1..1];
+	le_comb8.datac = encode_out[2..2];
+	le_comb9.dataa = encode_out[0..0];
+	le_comb9.datab = encode_out[1..1];
+	le_comb9.datac = encode_out[2..2];
+	areset_init_state_1.clk = clock;
+	areset_init_state_1.d = pll_scandone;
+	areset_state.clk = clock;
+	areset_state.d = (areset_init_state_1.q & (! reset));
+	C0_data_state.clk = clock;
+	C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done)));
+	C0_ena_state.clk = clock;
+	C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done);
+	C1_data_state.clk = clock;
+	C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done)));
+	C1_ena_state.clk = clock;
+	C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done);
+	C2_data_state.clk = clock;
+	C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done)));
+	C2_ena_state.clk = clock;
+	C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done);
+	C3_data_state.clk = clock;
+	C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done)));
+	C3_ena_state.clk = clock;
+	C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done);
+	C4_data_state.clk = clock;
+	C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done)));
+	C4_ena_state.clk = clock;
+	C4_ena_state.d = reconfig_init_state.q;
+	configupdate2_state.clk = clock;
+	configupdate2_state.d = configupdate_state.q;
+	configupdate3_state.clk = (! clock);
+	configupdate3_state.d = configupdate2_state.q;
+	configupdate_state.clk = clock;
+	configupdate_state.d = reconfig_post_state.q;
+	counter_param_latch_reg[].clk = clock;
+	counter_param_latch_reg[].clrn = (! reset);
+	counter_param_latch_reg[].d = counter_param[];
+	counter_param_latch_reg[].ena = input_latch_enable;
+	counter_type_latch_reg[].clk = clock;
+	counter_type_latch_reg[].clrn = (! reset);
+	counter_type_latch_reg[].d = counter_type[];
+	counter_type_latch_reg[].ena = input_latch_enable;
+	idle_state.clk = clock;
+	idle_state.clrn = (! reset);
+	idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q);
+	nominal_data[].clk = clock;
+	nominal_data[].clrn = (! reset);
+	nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]);
+	read_data_nominal_state.clk = clock;
+	read_data_nominal_state.clrn = (! reset);
+	read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done)));
+	read_data_state.clk = clock;
+	read_data_state.clrn = (! reset);
+	read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done)));
+	read_first_nominal_state.clk = clock;
+	read_first_nominal_state.clrn = (! reset);
+	read_first_nominal_state.d = read_init_nominal_state.q;
+	read_first_state.clk = clock;
+	read_first_state.clrn = (! reset);
+	read_first_state.d = read_init_state.q;
+	read_init_nominal_state.clk = clock;
+	read_init_nominal_state.clrn = (! reset);
+	read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	read_init_state.clk = clock;
+	read_init_state.clrn = (! reset);
+	read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	read_last_nominal_state.clk = clock;
+	read_last_nominal_state.clrn = (! reset);
+	read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done));
+	read_last_state.clk = clock;
+	read_last_state.clrn = (! reset);
+	read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done));
+	reconfig_counter_state.clk = clock;
+	reconfig_counter_state.clrn = (! reset);
+	reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	reconfig_init_state.clk = clock;
+	reconfig_init_state.clrn = (! reset);
+	reconfig_init_state.d = (idle_state.q & reconfig);
+	reconfig_post_state.clk = clock;
+	reconfig_post_state.clrn = (! reset);
+	reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done)));
+	reconfig_seq_data_state.clk = clock;
+	reconfig_seq_data_state.clrn = (! reset);
+	reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done)));
+	reconfig_seq_ena_state.clk = clock;
+	reconfig_seq_ena_state.clrn = (! reset);
+	reconfig_seq_ena_state.d = tmp_seq_ena_state.q;
+	reconfig_wait_state.clk = clock;
+	reconfig_wait_state.clrn = (! reset);
+	reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done)));
+	reset_state.clk = clock;
+	reset_state.d = power_up;
+	reset_state.prn = (! reset);
+	shift_reg[].clk = clock;
+	shift_reg[].clrn = (! reset);
+	shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in)));
+	shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear);
+	shift_reg[].sclr = shift_reg_clear;
+	tmp_nominal_data_out_state.clk = clock;
+	tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q));
+	tmp_seq_ena_state.clk = clock;
+	tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done));
+	write_data_state.clk = clock;
+	write_data_state.clrn = (! reset);
+	write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done)));
+	write_init_nominal_state.clk = clock;
+	write_init_nominal_state.clrn = (! reset);
+	write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	write_init_state.clk = clock;
+	write_init_state.clrn = (! reset);
+	write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	write_nominal_state.clk = clock;
+	write_nominal_state.clrn = (! reset);
+	write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done)));
+	add_sub5.cin = B"0";
+	add_sub5.dataa[] = ( B"0", shift_reg[8..1].q);
+	add_sub5.datab[] = ( B"0", shift_reg[17..10].q);
+	add_sub6.cin = data_in[0..0];
+	add_sub6.dataa[] = ( data_in[8..1]);
+	cmpr7.dataa[] = ( data_in[7..0]);
+	cmpr7.datab[] = B"00000001";
+	cntr1.clock = clock;
+	cntr1.cnt_en = addr_counter_enable;
+	cntr1.data[] = addr_counter_sload_value[];
+	cntr1.sload = addr_counter_sload;
+	cntr12.clock = clock;
+	cntr12.cnt_en = reconfig_addr_counter_enable;
+	cntr12.data[] = reconfig_addr_counter_sload_value[];
+	cntr12.sload = reconfig_addr_counter_sload;
+	cntr13.clock = clock;
+	cntr13.cnt_en = reconfig_width_counter_enable;
+	cntr13.data[] = reconfig_width_counter_sload_value[];
+	cntr13.sload = reconfig_width_counter_sload;
+	cntr14.clock = clock;
+	cntr14.cnt_en = rotate_width_counter_enable;
+	cntr14.data[] = rotate_width_counter_sload_value[];
+	cntr14.sload = rotate_width_counter_sload;
+	cntr15.clock = clock;
+	cntr15.cnt_en = rotate_addr_counter_enable;
+	cntr15.data[] = rotate_addr_counter_sload_value[];
+	cntr15.sload = rotate_addr_counter_sload;
+	cntr2.clock = clock;
+	cntr2.cnt_en = read_addr_counter_enable;
+	cntr2.data[] = read_addr_counter_sload_value[];
+	cntr2.sload = read_addr_counter_sload;
+	cntr3.clock = clock;
+	cntr3.cnt_en = width_counter_enable;
+	cntr3.data[] = width_counter_sload_value[];
+	cntr3.sload = width_counter_sload;
+	decode11.data[] = cuda_combout_wire[];
+	addr_counter_enable = (write_data_state.q # write_nominal_state.q);
+	addr_counter_out[] = cntr1.q[];
+	addr_counter_sload = (write_init_state.q # write_init_nominal_state.q);
+	addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q));
+	addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r)));
+	busy = ((! idle_state.q) # areset_state.q);
+	c0_wire[] = B"01000111";
+	c1_wire[] = B"01011001";
+	c2_wire[] = B"01101011";
+	c3_wire[] = B"01111101";
+	c4_wire[] = B"10001111";
+	counter_param_latch[] = counter_param_latch_reg[].q;
+	counter_type_latch[] = counter_type_latch_reg[].q;
+	cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout);
+	data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out)));
+	dummy_scandataout = pll_scandataout;
+	encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q));
+	input_latch_enable = (idle_state.q & (write_param # read_param));
+	pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q));
+	pll_configupdate = (configupdate_state.q & (! configupdate3_state.q));
+	pll_scanclk = clock;
+	pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q);
+	pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q));
+	power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q));
+	read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q);
+	read_addr_counter_out[] = cntr2.q[];
+	read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q);
+	read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q));
+	read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0"));
+	read_nominal_out = tmp_nominal_data_out_state.q;
+	reconfig_addr_counter_enable = reconfig_seq_data_state.q;
+	reconfig_addr_counter_out[] = cntr12.q[];
+	reconfig_addr_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]);
+	reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout)));
+	reconfig_post_done = pll_scandone;
+	reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5]));
+	reconfig_width_counter_enable = reconfig_seq_data_state.q;
+	reconfig_width_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]);
+	rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_addr_counter_out[] = cntr15.q[];
+	rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4]));
+	rotate_decoder_wires[] = decode11.eq[];
+	rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4]));
+	rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_width_counter_sload_value[] = B"10010";
+	scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable));
+	scan_cache_in = shift_reg_serial_out;
+	scan_cache_out = altsyncram4.q_a[0..0];
+	scan_cache_write_enable = (write_data_state.q # write_nominal_state.q);
+	sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2]));
+	sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]);
+	sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]);
+	sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	seq_addr_wire[] = B"00110101";
+	seq_sload_value[] = B"110110";
+	shift_reg_clear = (read_init_state.q # read_init_nominal_state.q);
+	shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	shift_reg_serial_in = scan_cache_out;
+	shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7]));
+	shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q);
+	shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q);
+	shift_reg_width_select[] = width_decoder_select[];
+	w1565w = B"0";
+	w1592w = B"0";
+	w64w = B"0";
+	width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4]));
+	width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q);
+	width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q);
+	width_counter_sload_value[] = width_decoder_out[];
+	width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0"));
+	width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused)));
+	write_from_rom = GND;
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_t4q.tdf b/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_t4q.tdf
new file mode 100644
index 0000000..fae939f
--- /dev/null
+++ b/FPGA_by_Fredi/altpll_reconfig1_pllrcfg_t4q.tdf
@@ -0,0 +1,582 @@
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
+--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+include "altsyncram.inc";
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS)
+RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]);
+FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT)
+RETURNS ( aeb, agb, ageb, alb, aleb, aneb);
+FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
+WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width)
+RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);
+FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable)
+WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH)
+RETURNS ( eq[LPM_DECODES-1..0]);
+
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 
+OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW";
+
+SUBDESIGN altpll_reconfig1_pllrcfg_t4q
+( 
+	busy	:	output;
+	clock	:	input;
+	counter_param[2..0]	:	input;
+	counter_type[3..0]	:	input;
+	data_in[8..0]	:	input;
+	data_out[8..0]	:	output;
+	pll_areset	:	output;
+	pll_areset_in	:	input;
+	pll_configupdate	:	output;
+	pll_scanclk	:	output;
+	pll_scanclkena	:	output;
+	pll_scandata	:	output;
+	pll_scandataout	:	input;
+	pll_scandone	:	input;
+	read_param	:	input;
+	reconfig	:	input;
+	reset	:	input;
+	write_param	:	input;
+) 
+VARIABLE 
+	altsyncram4 : altsyncram
+		WITH (
+			NUMWORDS_A = 144,
+			OPERATION_MODE = "SINGLE_PORT",
+			WIDTH_A = 1,
+			WIDTH_BYTEENA_A = 1,
+			WIDTHAD_A = 8
+		);
+	le_comb10 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "F0F0",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb8 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "AAAA",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb9 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "CCCC",
+			SUM_LUTC_INPUT = "datac"
+		);
+	areset_init_state_1 : dffe;
+	areset_state : dffe;
+	C0_data_state : dffe;
+	C0_ena_state : dffe;
+	C1_data_state : dffe;
+	C1_ena_state : dffe;
+	C2_data_state : dffe;
+	C2_ena_state : dffe;
+	C3_data_state : dffe;
+	C3_ena_state : dffe;
+	C4_data_state : dffe;
+	C4_ena_state : dffe;
+	configupdate2_state : dffe;
+	configupdate3_state : dffe;
+	configupdate_state : dffe;
+	counter_param_latch_reg[2..0] : dffe;
+	counter_type_latch_reg[3..0] : dffe;
+	idle_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	nominal_data[17..0] : dffe;
+	read_data_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_counter_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_post_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_ena_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_wait_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reset_state : dffe
+		WITH (
+			power_up = "high"
+		);
+	shift_reg[17..0] : dffeas;
+	tmp_nominal_data_out_state : dffe;
+	tmp_seq_ena_state : dffe;
+	write_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	add_sub5 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 9
+		);
+	add_sub6 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cmpr7 : lpm_compare
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cntr1 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr12 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr13 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 6
+		);
+	cntr14 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	cntr15 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr2 : lpm_counter
+		WITH (
+			lpm_direction = "UP",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr3 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	decode11 : lpm_decode
+		WITH (
+			LPM_DECODES = 5,
+			LPM_WIDTH = 3
+		);
+	addr_counter_enable	: WIRE;
+	addr_counter_out[7..0]	: WIRE;
+	addr_counter_sload	: WIRE;
+	addr_counter_sload_value[7..0]	: WIRE;
+	addr_decoder_out[7..0]	: WIRE;
+	c0_wire[7..0]	: WIRE;
+	c1_wire[7..0]	: WIRE;
+	c2_wire[7..0]	: WIRE;
+	c3_wire[7..0]	: WIRE;
+	c4_wire[7..0]	: WIRE;
+	counter_param_latch[2..0]	: WIRE;
+	counter_type_latch[3..0]	: WIRE;
+	cuda_combout_wire[2..0]	: WIRE;
+	dummy_scandataout	: WIRE;
+	encode_out[2..0]	: WIRE;
+	input_latch_enable	: WIRE;
+	power_up	: WIRE;
+	read_addr_counter_enable	: WIRE;
+	read_addr_counter_out[7..0]	: WIRE;
+	read_addr_counter_sload	: WIRE;
+	read_addr_counter_sload_value[7..0]	: WIRE;
+	read_addr_decoder_out[7..0]	: WIRE;
+	read_nominal_out	: WIRE;
+	reconfig_addr_counter_enable	: WIRE;
+	reconfig_addr_counter_out[7..0]	: WIRE;
+	reconfig_addr_counter_sload	: WIRE;
+	reconfig_addr_counter_sload_value[7..0]	: WIRE;
+	reconfig_done	: WIRE;
+	reconfig_post_done	: WIRE;
+	reconfig_width_counter_done	: WIRE;
+	reconfig_width_counter_enable	: WIRE;
+	reconfig_width_counter_sload	: WIRE;
+	reconfig_width_counter_sload_value[5..0]	: WIRE;
+	rotate_addr_counter_enable	: WIRE;
+	rotate_addr_counter_out[7..0]	: WIRE;
+	rotate_addr_counter_sload	: WIRE;
+	rotate_addr_counter_sload_value[7..0]	: WIRE;
+	rotate_decoder_wires[4..0]	: WIRE;
+	rotate_width_counter_done	: WIRE;
+	rotate_width_counter_enable	: WIRE;
+	rotate_width_counter_sload	: WIRE;
+	rotate_width_counter_sload_value[4..0]	: WIRE;
+	scan_cache_address[7..0]	: WIRE;
+	scan_cache_in	: WIRE;
+	scan_cache_out	: WIRE;
+	scan_cache_write_enable	: WIRE;
+	sel_param_bypass_LF_unused	: WIRE;
+	sel_param_c	: WIRE;
+	sel_param_high_i_postscale	: WIRE;
+	sel_param_low_r	: WIRE;
+	sel_param_nominal_count	: WIRE;
+	sel_param_odd_CP_unused	: WIRE;
+	sel_type_c0	: WIRE;
+	sel_type_c1	: WIRE;
+	sel_type_c2	: WIRE;
+	sel_type_c3	: WIRE;
+	sel_type_c4	: WIRE;
+	sel_type_cplf	: WIRE;
+	sel_type_m	: WIRE;
+	sel_type_n	: WIRE;
+	sel_type_vco	: WIRE;
+	seq_addr_wire[7..0]	: WIRE;
+	seq_sload_value[5..0]	: WIRE;
+	shift_reg_clear	: WIRE;
+	shift_reg_load_enable	: WIRE;
+	shift_reg_load_nominal_enable	: WIRE;
+	shift_reg_serial_in	: WIRE;
+	shift_reg_serial_out	: WIRE;
+	shift_reg_shift_enable	: WIRE;
+	shift_reg_shift_nominal_enable	: WIRE;
+	shift_reg_width_select[7..0]	: WIRE;
+	w1565w	: WIRE;
+	w1592w	: WIRE;
+	w64w	: WIRE;
+	width_counter_done	: WIRE;
+	width_counter_enable	: WIRE;
+	width_counter_sload	: WIRE;
+	width_counter_sload_value[4..0]	: WIRE;
+	width_decoder_out[4..0]	: WIRE;
+	width_decoder_select[7..0]	: WIRE;
+	write_from_rom	: NODE;
+
+BEGIN 
+	altsyncram4.address_a[] = scan_cache_address[];
+	altsyncram4.clock0 = clock;
+	altsyncram4.data_a[] = ( scan_cache_in);
+	altsyncram4.wren_a = scan_cache_write_enable;
+	le_comb10.dataa = encode_out[0..0];
+	le_comb10.datab = encode_out[1..1];
+	le_comb10.datac = encode_out[2..2];
+	le_comb8.dataa = encode_out[0..0];
+	le_comb8.datab = encode_out[1..1];
+	le_comb8.datac = encode_out[2..2];
+	le_comb9.dataa = encode_out[0..0];
+	le_comb9.datab = encode_out[1..1];
+	le_comb9.datac = encode_out[2..2];
+	areset_init_state_1.clk = clock;
+	areset_init_state_1.d = pll_scandone;
+	areset_state.clk = clock;
+	areset_state.d = (areset_init_state_1.q & (! reset));
+	C0_data_state.clk = clock;
+	C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done)));
+	C0_ena_state.clk = clock;
+	C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done);
+	C1_data_state.clk = clock;
+	C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done)));
+	C1_ena_state.clk = clock;
+	C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done);
+	C2_data_state.clk = clock;
+	C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done)));
+	C2_ena_state.clk = clock;
+	C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done);
+	C3_data_state.clk = clock;
+	C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done)));
+	C3_ena_state.clk = clock;
+	C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done);
+	C4_data_state.clk = clock;
+	C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done)));
+	C4_ena_state.clk = clock;
+	C4_ena_state.d = reconfig_init_state.q;
+	configupdate2_state.clk = clock;
+	configupdate2_state.d = configupdate_state.q;
+	configupdate3_state.clk = (! clock);
+	configupdate3_state.d = configupdate2_state.q;
+	configupdate_state.clk = clock;
+	configupdate_state.d = reconfig_post_state.q;
+	counter_param_latch_reg[].clk = clock;
+	counter_param_latch_reg[].clrn = (! reset);
+	counter_param_latch_reg[].d = counter_param[];
+	counter_param_latch_reg[].ena = input_latch_enable;
+	counter_type_latch_reg[].clk = clock;
+	counter_type_latch_reg[].clrn = (! reset);
+	counter_type_latch_reg[].d = counter_type[];
+	counter_type_latch_reg[].ena = input_latch_enable;
+	idle_state.clk = clock;
+	idle_state.clrn = (! reset);
+	idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q);
+	nominal_data[].clk = clock;
+	nominal_data[].clrn = (! reset);
+	nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]);
+	read_data_nominal_state.clk = clock;
+	read_data_nominal_state.clrn = (! reset);
+	read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done)));
+	read_data_state.clk = clock;
+	read_data_state.clrn = (! reset);
+	read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done)));
+	read_first_nominal_state.clk = clock;
+	read_first_nominal_state.clrn = (! reset);
+	read_first_nominal_state.d = read_init_nominal_state.q;
+	read_first_state.clk = clock;
+	read_first_state.clrn = (! reset);
+	read_first_state.d = read_init_state.q;
+	read_init_nominal_state.clk = clock;
+	read_init_nominal_state.clrn = (! reset);
+	read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	read_init_state.clk = clock;
+	read_init_state.clrn = (! reset);
+	read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	read_last_nominal_state.clk = clock;
+	read_last_nominal_state.clrn = (! reset);
+	read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done));
+	read_last_state.clk = clock;
+	read_last_state.clrn = (! reset);
+	read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done));
+	reconfig_counter_state.clk = clock;
+	reconfig_counter_state.clrn = (! reset);
+	reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	reconfig_init_state.clk = clock;
+	reconfig_init_state.clrn = (! reset);
+	reconfig_init_state.d = (idle_state.q & reconfig);
+	reconfig_post_state.clk = clock;
+	reconfig_post_state.clrn = (! reset);
+	reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done)));
+	reconfig_seq_data_state.clk = clock;
+	reconfig_seq_data_state.clrn = (! reset);
+	reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done)));
+	reconfig_seq_ena_state.clk = clock;
+	reconfig_seq_ena_state.clrn = (! reset);
+	reconfig_seq_ena_state.d = tmp_seq_ena_state.q;
+	reconfig_wait_state.clk = clock;
+	reconfig_wait_state.clrn = (! reset);
+	reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done)));
+	reset_state.clk = clock;
+	reset_state.d = power_up;
+	reset_state.prn = (! reset);
+	shift_reg[].clk = clock;
+	shift_reg[].clrn = (! reset);
+	shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in)));
+	shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear);
+	shift_reg[].sclr = shift_reg_clear;
+	tmp_nominal_data_out_state.clk = clock;
+	tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q));
+	tmp_seq_ena_state.clk = clock;
+	tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done));
+	write_data_state.clk = clock;
+	write_data_state.clrn = (! reset);
+	write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done)));
+	write_init_nominal_state.clk = clock;
+	write_init_nominal_state.clrn = (! reset);
+	write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	write_init_state.clk = clock;
+	write_init_state.clrn = (! reset);
+	write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	write_nominal_state.clk = clock;
+	write_nominal_state.clrn = (! reset);
+	write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done)));
+	add_sub5.cin = B"0";
+	add_sub5.dataa[] = ( B"0", shift_reg[8..1].q);
+	add_sub5.datab[] = ( B"0", shift_reg[17..10].q);
+	add_sub6.cin = data_in[0..0];
+	add_sub6.dataa[] = ( data_in[8..1]);
+	cmpr7.dataa[] = ( data_in[7..0]);
+	cmpr7.datab[] = B"00000001";
+	cntr1.clock = clock;
+	cntr1.cnt_en = addr_counter_enable;
+	cntr1.data[] = addr_counter_sload_value[];
+	cntr1.sload = addr_counter_sload;
+	cntr12.clock = clock;
+	cntr12.cnt_en = reconfig_addr_counter_enable;
+	cntr12.data[] = reconfig_addr_counter_sload_value[];
+	cntr12.sload = reconfig_addr_counter_sload;
+	cntr13.clock = clock;
+	cntr13.cnt_en = reconfig_width_counter_enable;
+	cntr13.data[] = reconfig_width_counter_sload_value[];
+	cntr13.sload = reconfig_width_counter_sload;
+	cntr14.clock = clock;
+	cntr14.cnt_en = rotate_width_counter_enable;
+	cntr14.data[] = rotate_width_counter_sload_value[];
+	cntr14.sload = rotate_width_counter_sload;
+	cntr15.clock = clock;
+	cntr15.cnt_en = rotate_addr_counter_enable;
+	cntr15.data[] = rotate_addr_counter_sload_value[];
+	cntr15.sload = rotate_addr_counter_sload;
+	cntr2.clock = clock;
+	cntr2.cnt_en = read_addr_counter_enable;
+	cntr2.data[] = read_addr_counter_sload_value[];
+	cntr2.sload = read_addr_counter_sload;
+	cntr3.clock = clock;
+	cntr3.cnt_en = width_counter_enable;
+	cntr3.data[] = width_counter_sload_value[];
+	cntr3.sload = width_counter_sload;
+	decode11.data[] = cuda_combout_wire[];
+	addr_counter_enable = (write_data_state.q # write_nominal_state.q);
+	addr_counter_out[] = cntr1.q[];
+	addr_counter_sload = (write_init_state.q # write_init_nominal_state.q);
+	addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q));
+	addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r)));
+	busy = ((! idle_state.q) # areset_state.q);
+	c0_wire[] = B"01000111";
+	c1_wire[] = B"01011001";
+	c2_wire[] = B"01101011";
+	c3_wire[] = B"01111101";
+	c4_wire[] = B"10001111";
+	counter_param_latch[] = counter_param_latch_reg[].q;
+	counter_type_latch[] = counter_type_latch_reg[].q;
+	cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout);
+	data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out)));
+	dummy_scandataout = pll_scandataout;
+	encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q));
+	input_latch_enable = (idle_state.q & (write_param # read_param));
+	pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q));
+	pll_configupdate = (configupdate_state.q & (! configupdate3_state.q));
+	pll_scanclk = clock;
+	pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q);
+	pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q));
+	power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q));
+	read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q);
+	read_addr_counter_out[] = cntr2.q[];
+	read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q);
+	read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q));
+	read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0"));
+	read_nominal_out = tmp_nominal_data_out_state.q;
+	reconfig_addr_counter_enable = reconfig_seq_data_state.q;
+	reconfig_addr_counter_out[] = cntr12.q[];
+	reconfig_addr_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]);
+	reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout)));
+	reconfig_post_done = pll_scandone;
+	reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5]));
+	reconfig_width_counter_enable = reconfig_seq_data_state.q;
+	reconfig_width_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]);
+	rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_addr_counter_out[] = cntr15.q[];
+	rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4]));
+	rotate_decoder_wires[] = decode11.eq[];
+	rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4]));
+	rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_width_counter_sload_value[] = B"10010";
+	scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable));
+	scan_cache_in = shift_reg_serial_out;
+	scan_cache_out = altsyncram4.q_a[0..0];
+	scan_cache_write_enable = (write_data_state.q # write_nominal_state.q);
+	sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2]));
+	sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]);
+	sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]);
+	sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	seq_addr_wire[] = B"00110101";
+	seq_sload_value[] = B"110110";
+	shift_reg_clear = (read_init_state.q # read_init_nominal_state.q);
+	shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	shift_reg_serial_in = scan_cache_out;
+	shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7]));
+	shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q);
+	shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q);
+	shift_reg_width_select[] = width_decoder_select[];
+	w1565w = B"0";
+	w1592w = B"0";
+	w64w = B"0";
+	width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4]));
+	width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q);
+	width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q);
+	width_counter_sload_value[] = width_decoder_out[];
+	width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0"));
+	width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused)));
+	write_from_rom = GND;
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/firebee1.asm.rpt b/FPGA_by_Fredi/firebee1.asm.rpt
new file mode 100644
index 0000000..7ffb13e
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.asm.rpt
@@ -0,0 +1,128 @@
+Assembler report for firebee1
+Wed Dec 15 02:25:13 2010
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
+  6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Wed Dec 15 02:25:13 2010 ;
+; Revision Name         ; firebee1                              ;
+; Top-level Entity Name ; firebee1                              ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C40F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                       ;
++-----------------------------------------------------------------------------+------------+---------------+
+; Option                                                                      ; Setting    ; Default Value ;
++-----------------------------------------------------------------------------+------------+---------------+
+; Generate Raw Binary File (.rbf) For Target Device                           ; On         ; Off           ;
+; Hexadecimal Output File start address                                       ; 0XE0700000 ; 0             ;
+; Use smart compilation                                                       ; Off        ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On         ; On            ;
+; Enable compact report table                                                 ; Off        ; Off           ;
+; Generate compressed bitstreams                                              ; On         ; On            ;
+; Compression mode                                                            ; Off        ; Off           ;
+; Clock source for configuration device                                       ; Internal   ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ     ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1          ; 1             ;
+; Auto user code                                                              ; Off        ; Off           ;
+; Use configuration device                                                    ; Off        ; Off           ;
+; Configuration device                                                        ; Auto       ; Auto          ;
+; Configuration device auto user code                                         ; Off        ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off        ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off        ; Off           ;
+; Hexadecimal Output File count direction                                     ; Up         ; Up            ;
+; Release clears before tri-states                                            ; Off        ; Off           ;
+; Auto-restart configuration after error                                      ; On         ; On            ;
+; Enable OCT_DONE                                                             ; Off        ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off        ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off        ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off        ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On         ; On            ;
++-----------------------------------------------------------------------------+------------+---------------+
+
+
++------------------------------+
+; Assembler Generated Files    ;
++------------------------------+
+; File Name                    ;
++------------------------------+
+; C:/FireBee/FPGA/firebee1.sof ;
+; C:/FireBee/FPGA/firebee1.rbf ;
++------------------------------+
+
+
++--------------------------------------------------------+
+; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
++----------------+---------------------------------------+
+; Option         ; Setting                               ;
++----------------+---------------------------------------+
+; Device         ; EP3C40F484C6                          ;
+; JTAG usercode  ; 0xFFFFFFFF                            ;
+; Checksum       ; 0x0085E8C6                            ;
++----------------+---------------------------------------+
+
+
++--------------------------------------------------------+
+; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
++---------------------+----------------------------------+
+; Option              ; Setting                          ;
++---------------------+----------------------------------+
+; Raw Binary File     ;                                  ;
+;  Compression Ratio  ; 2                                ;
++---------------------+----------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Wed Dec 15 02:25:08 2010
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 291 megabytes
+    Info: Processing ended: Wed Dec 15 02:25:13 2010
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
new file mode 100644
index 0000000..46507a2
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -0,0 +1,5837 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
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+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DMA_DRQ" (input))
+	(block_io "nIRQ[7..2]" (output))
+	(block_io "INT_HANDLER_TA" (output))
+	(block_io "ACP_CONF[31..0]" (output))
+	(block_io "TIN0" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 0 136)
+		(bidir)
+		)
+	(mapper
+		(pt 0 160)
+		(bidir)
+		)
+	(mapper
+		(pt 0 184)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 112)
+		(bidir)
+		)
+	(mapper
+		(pt 0 40)
+		(bidir)
+		)
+	(mapper
+		(pt 408 56)
+		(bidir)
+		)
+	(mapper
+		(pt 408 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 280)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 208)
+		(bidir)
+		)
+	(mapper
+		(pt 0 64)
+		(bidir)
+		)
+	(mapper
+		(pt 0 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 400)
+		(bidir)
+		)
+	(mapper
+		(pt 0 328)
+		(bidir)
+		)
+	(mapper
+		(pt 0 352)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 0 480)
+		(bidir)
+		)
+	(mapper
+		(pt 0 504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 504)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 744 1672 2264)
+	(text "FalconIO_SDCard_IDE_CF" (rect 5 5 189 21)(font "Arial" (font_size 8)))	(text "Wolfgang_Foerster_and_Fredi_Aschwanden" (rect 5 1506 295 1521)(font "Arial" ))	(block_io "CLK33M" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "CLK2M" (input))
+	(block_io "CLK500k" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "LP_BUSY" (input))
+	(block_io "nACSI_DRQ" (input))
+	(block_io "nACSI_INT" (input))
+	(block_io "nSCSI_DRQ" (input))
+	(block_io "nSCSI_MSG" (input))
+	(block_io "MIDI_IN" (input))
+	(block_io "RxD" (input))
+	(block_io "CTS" (input))
+	(block_io "RI" (input))
+	(block_io "DCD" (input))
+	(block_io "AMKB_RX" (input))
+	(block_io "PIC_AMKB_RX" (input))
+	(block_io "IDE_RDY" (input))
+	(block_io "IDE_INT" (input))
+	(block_io "WP_CS_CARD" (input))
+	(block_io "nINDEX" (input))
+	(block_io "TRACK00" (input))
+	(block_io "nRD_DATA" (input))
+	(block_io "nDCHG" (input))
+	(block_io "SD_DATA0" (input))
+	(block_io "SD_DATA1" (input))
+	(block_io "SD_DATA2" (input))
+	(block_io "SD_CARD_DEDECT" (input))
+	(block_io "SD_WP" (input))
+	(block_io "nDACK0" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "WP_CF_CARD" (input))
+	(block_io "nWP" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nSCSI_C_D" (input))
+	(block_io "nSCSI_I_O" (input))
+	(block_io "CLK2M4576" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "nBLANK" (input))
+	(block_io "FDC_CLK" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "ACP_CONF[31..24]" (input))
+	(block_io "HD_DD" (input))
+	(block_io "nIDE_CS1" (output))
+	(block_io "nIDE_CS0" (output))
+	(block_io "LP_STR" (output))
+	(block_io "LP_DIR" (output))
+	(block_io "nACSI_ACK" (output))
+	(block_io "nACSI_RESET" (output))
+	(block_io "nACSI_CS" (output))
+	(block_io "ACSI_DIR" (output))
+	(block_io "ACSI_A1" (output))
+	(block_io "nSCSI_ACK" (output))
+	(block_io "nSCSI_ATN" (output))
+	(block_io "SCSI_DIR" (output))
+	(block_io "SD_CLK" (output))
+	(block_io "YM_QA" (output))
+	(block_io "YM_QC" (output))
+	(block_io "YM_QB" (output))
+	(block_io "nSDSEL" (output))
+	(block_io "STEP" (output))
+	(block_io "MOT_ON" (output))
+	(block_io "nRP_LDS" (output))
+	(block_io "nRP_UDS" (output))
+	(block_io "nROM4" (output))
+	(block_io "nROM3" (output))
+	(block_io "nCF_CS1" (output))
+	(block_io "nCF_CS0" (output))
+	(block_io "nIDE_RD" (output))
+	(block_io "nIDE_WR" (output))
+	(block_io "AMKB_TX" (output))
+	(block_io "IDE_RES" (output))
+	(block_io "DTR" (output))
+	(block_io "RTS" (output))
+	(block_io "TxD" (output))
+	(block_io "MIDI_OLR" (output))
+	(block_io "MIDI_TLR" (output))
+	(block_io "nDREQ0" (output))
+	(block_io "DSA_D" (output))
+	(block_io "nMFP_INT" (output))
+	(block_io "FALCON_IO_TA" (output))
+	(block_io "STEP_DIR" (output))
+	(block_io "WR_DATA" (output))
+	(block_io "WR_GATE" (output))
+	(block_io "DMA_DRQ" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "LP_D[7..0]" (bidir))
+	(block_io "ACSI_D[7..0]" (bidir))
+	(block_io "SCSI_D[7..0]" (bidir))
+	(block_io "SCSI_PAR" (bidir))
+	(block_io "nSCSI_SEL" (bidir))
+	(block_io "nSCSI_BUSY" (bidir))
+	(block_io "nSCSI_RST" (bidir))
+	(block_io "SD_CD_DATA3" (bidir))
+	(block_io "SD_CDM_D1" (bidir))
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+		(bidir)
+		)
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+		)
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+		(bidir)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 608)
+		(bidir)
+		)
+	(mapper
+		(pt 408 632)
+		(bidir)
+		)
+	(mapper
+		(pt 408 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 552)
+		(bidir)
+		)
+	(mapper
+		(pt 408 584)
+		(bidir)
+		)
+	(mapper
+		(pt 0 624)
+		(bidir)
+		)
+	(mapper
+		(pt 0 656)
+		(bidir)
+		)
+	(mapper
+		(pt 0 680)
+		(bidir)
+		)
+	(mapper
+		(pt 0 704)
+		(bidir)
+		)
+	(mapper
+		(pt 0 728)
+		(bidir)
+		)
+	(mapper
+		(pt 0 752)
+		(bidir)
+		)
+	(mapper
+		(pt 0 776)
+		(bidir)
+		)
+	(mapper
+		(pt 408 664)
+		(bidir)
+		)
+	(mapper
+		(pt 0 808)
+		(bidir)
+		)
+	(mapper
+		(pt 0 832)
+		(bidir)
+		)
+	(mapper
+		(pt 408 696)
+		(bidir)
+		)
+	(mapper
+		(pt 408 720)
+		(bidir)
+		)
+	(mapper
+		(pt 408 744)
+		(bidir)
+		)
+	(mapper
+		(pt 408 768)
+		(bidir)
+		)
+	(mapper
+		(pt 408 792)
+		(bidir)
+		)
+	(mapper
+		(pt 408 816)
+		(bidir)
+		)
+	(mapper
+		(pt 408 840)
+		(bidir)
+		)
+	(mapper
+		(pt 0 856)
+		(bidir)
+		)
+	(mapper
+		(pt 408 872)
+		(bidir)
+		)
+	(mapper
+		(pt 408 896)
+		(bidir)
+		)
+	(mapper
+		(pt 408 920)
+		(bidir)
+		)
+	(mapper
+		(pt 408 944)
+		(bidir)
+		)
+	(mapper
+		(pt 0 912)
+		(bidir)
+		)
+	(mapper
+		(pt 0 936)
+		(bidir)
+		)
+	(mapper
+		(pt 0 960)
+		(bidir)
+		)
+	(mapper
+		(pt 0 984)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1008)
+		(bidir)
+		)
+	(mapper
+		(pt 408 976)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1000)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1072)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1096)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1040)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1064)
+		(bidir)
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+	(mapper
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(pt 0 1136)
+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 568)
+		(bidir)
+		)
+	(mapper
+		(pt 0 592)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1168)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1192)
+		(bidir)
+		)
+	(mapper
+		(pt 0 368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1216)
+		(bidir)
+		)
+	(mapper
+		(pt 408 48)
+		(bidir)
+		)
+	(mapper
+		(pt 408 16)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1304)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1280)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1048)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1024)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1264)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1336)
+		(bidir)
+		)
+	(mapper
+		(pt 0 888)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 -48 1672 728)
+	(text "Video" (rect 5 5 43 21)(font "Arial" (font_size 8)))	(text "Fredi_Aschwanden" (rect 5 762 130 777)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "DDRCLK[3..0]" (input))
+	(block_io "DDR_SYNC_66M" (input))
+	(block_io "CLK33M" (input))
+	(block_io "CLK25M" (input))
+	(block_io "CLK_VIDEO" (input))
+	(block_io "VR_D[8..0]" (input))
+	(block_io "VR_BUSY" (input))
+	(block_io "VR_RD" (output))
+	(block_io "VG[7..0]" (output))
+	(block_io "VB[7..0]" (output))
+	(block_io "VR[7..0]" (output))
+	(block_io "nBLANK" (output))
+	(block_io "VA[12..0]" (output))
+	(block_io "nVWE" (output))
+	(block_io "nVCAS" (output))
+	(block_io "nVRAS" (output))
+	(block_io "nVCS" (output))
+	(block_io "VDM[3..0]" (output))
+	(block_io "nPD_VGA" (output))
+	(block_io "VCKE" (output))
+	(block_io "VSYNC" (output))
+	(block_io "HSYNC" (output))
+	(block_io "nSYNC" (output))
+	(block_io "VIDEO_TA" (output))
+	(block_io "PIXEL_CLK" (output))
+	(block_io "BA[1..0]" (output))
+	(block_io "VIDEO_RECONFIG" (output))
+	(block_io "VR_WR" (output))
+	(block_io "VDQS[3..0]" (bidir))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "VD[31..0]" (bidir))
+	(mapper
+		(pt 408 448)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 592)
+		(bidir)
+		)
+	(mapper
+		(pt 408 352)
+		(bidir)
+		)
+	(mapper
+		(pt 408 760)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 128)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 416)
+		(bidir)
+		)
+	(mapper
+		(pt 408 320)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 568)
+		(bidir)
+		)
+	(mapper
+		(pt 408 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 648)
+		(bidir)
+		)
+	(mapper
+		(pt 0 672)
+		(bidir)
+		)
+	(mapper
+		(pt 0 616)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 656)
+		(bidir)
+		)
+	(mapper
+		(pt 408 640)
+		(bidir)
+		)
+	(mapper
+		(pt 408 624)
+		(bidir)
+		)
+	(mapper
+		(pt 0 512)
+		(bidir)
+		)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 776 1765 791)(font "Arial" ))
+	(pt 1832 792)
+	(pt 1672 792)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 1072 1240 1087)(font "Arial" ))
+	(pt 1112 1088)
+	(pt 1264 1088)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 784 1231 799)(font "Arial" ))
+	(pt 1152 800)
+	(pt 1264 800)
+)
+(connector
+	(text "CLK33M" (rect 1210 760 1265 775)(font "Arial" ))
+	(pt 1200 776)
+	(pt 1264 776)
+)
+(connector
+	(text "CLK2M" (rect 1202 808 1249 823)(font "Arial" ))
+	(pt 1192 824)
+	(pt 1264 824)
+)
+(connector
+	(text "CLK500k" (rect 1202 832 1262 847)(font "Arial" ))
+	(pt 1192 848)
+	(pt 1264 848)
+)
+(connector
+	(text "LP_DIR" (rect 1682 848 1732 863)(font "Arial" ))
+	(pt 1672 864)
+	(pt 1832 864)
+)
+(connector
+	(text "LP_STR" (rect 1682 824 1736 839)(font "Arial" ))
+	(pt 1672 840)
+	(pt 1832 840)
+)
+(connector
+	(text "nACSI_ACK" (rect 1682 928 1758 943)(font "Arial" ))
+	(pt 1672 944)
+	(pt 1832 944)
+)
+(connector
+	(text "nACSI_RESET" (rect 1682 952 1777 967)(font "Arial" ))
+	(pt 1672 968)
+	(pt 1832 968)
+)
+(connector
+	(text "nACSI_CS" (rect 1682 976 1750 991)(font "Arial" ))
+	(pt 1672 992)
+	(pt 1832 992)
+)
+(connector
+	(text "ACSI_DIR" (rect 1682 1000 1746 1015)(font "Arial" ))
+	(pt 1672 1016)
+	(pt 1832 1016)
+)
+(connector
+	(text "ACSI_A1" (rect 1682 1024 1738 1039)(font "Arial" ))
+	(pt 1672 1040)
+	(pt 1832 1040)
+)
+(connector
+	(text "nSCSI_ATN" (rect 1682 1128 1758 1143)(font "Arial" ))
+	(pt 1672 1144)
+	(pt 1840 1144)
+)
+(connector
+	(text "SCSI_DIR" (rect 1682 1152 1748 1167)(font "Arial" ))
+	(pt 1672 1168)
+	(pt 1840 1168)
+)
+(connector
+	(text "nSCSI_DRQ" (rect 1114 1248 1195 1263)(font "Arial" ))
+	(pt 1264 1264)
+	(pt 1104 1264)
+)
+(connector
+	(text "nSCSI_MSG" (rect 1114 1320 1194 1335)(font "Arial" ))
+	(pt 1104 1336)
+	(pt 1264 1336)
+)
+(connector
+	(text "nSCSI_RST" (rect 1682 1176 1759 1191)(font "Arial" ))
+	(pt 1672 1192)
+	(pt 1840 1192)
+)
+(connector
+	(text "nSCSI_SEL" (rect 1680 1200 1756 1215)(font "Arial" ))
+	(pt 1672 1216)
+	(pt 1840 1216)
+)
+(connector
+	(text "nSCSI_BUSY" (rect 1682 1224 1769 1239)(font "Arial" ))
+	(pt 1672 1240)
+	(pt 1840 1240)
+)
+(connector
+	(text "TxD" (rect 1682 1312 1706 1327)(font "Arial" ))
+	(pt 1672 1328)
+	(pt 1840 1328)
+)
+(connector
+	(text "RTS" (rect 1682 1336 1710 1351)(font "Arial" ))
+	(pt 1672 1352)
+	(pt 1840 1352)
+)
+(connector
+	(text "DTR" (rect 1680 1360 1709 1375)(font "Arial" ))
+	(pt 1672 1376)
+	(pt 1848 1376)
+)
+(connector
+	(text "CTS" (rect 1114 1408 1142 1423)(font "Arial" ))
+	(pt 1104 1424)
+	(pt 1264 1424)
+)
+(connector
+	(text "RI" (rect 1114 1432 1128 1447)(font "Arial" ))
+	(pt 1104 1448)
+	(pt 1264 1448)
+)
+(connector
+	(text "DCD" (rect 1114 1456 1145 1471)(font "Arial" ))
+	(pt 1104 1472)
+	(pt 1264 1472)
+)
+(connector
+	(text "IDE_RDY" (rect 1114 1536 1175 1551)(font "Arial" ))
+	(pt 1264 1552)
+	(pt 1104 1552)
+)
+(connector
+	(text "IDE_INT" (rect 1114 1560 1168 1575)(font "Arial" ))
+	(pt 1104 1576)
+	(pt 1264 1576)
+)
+(connector
+	(text "IDE_RES" (rect 1682 1424 1743 1439)(font "Arial" ))
+	(pt 1672 1440)
+	(pt 1848 1440)
+)
+(connector
+	(text "nIDE_CS0" (rect 1682 1448 1750 1463)(font "Arial" ))
+	(pt 1672 1464)
+	(pt 1848 1464)
+)
+(connector
+	(text "nIDE_CS1" (rect 1682 1472 1750 1487)(font "Arial" ))
+	(pt 1672 1488)
+	(pt 1856 1488)
+)
+(connector
+	(text "nIDE_WR" (rect 1682 1496 1745 1511)(font "Arial" ))
+	(pt 1672 1512)
+	(pt 1848 1512)
+)
+(connector
+	(text "nIDE_RD" (rect 1682 1520 1743 1535)(font "Arial" ))
+	(pt 1672 1536)
+	(pt 1848 1536)
+)
+(connector
+	(text "nCF_CS0" (rect 1682 1544 1745 1559)(font "Arial" ))
+	(pt 1672 1560)
+	(pt 1848 1560)
+)
+(connector
+	(text "nCF_CS1" (rect 1682 1568 1745 1583)(font "Arial" ))
+	(pt 1672 1584)
+	(pt 1848 1584)
+)
+(connector
+	(text "WP_CF_CARD" (rect 1112 1584 1209 1599)(font "Arial" ))
+	(pt 1104 1600)
+	(pt 1264 1600)
+)
+(connector
+	(text "nSDSEL" (rect 1682 1848 1737 1863)(font "Arial" ))
+	(pt 1672 1864)
+	(pt 1856 1864)
+)
+(connector
+	(text "nDREQ0" (rect 1682 2152 1739 2167)(font "Arial" ))
+	(pt 1672 2168)
+	(pt 1856 2168)
+)
+(connector
+	(text "SD_CLK" (rect 1682 2032 1738 2047)(font "Arial" ))
+	(pt 1856 2048)
+	(pt 1672 2048)
+)
+(connector
+	(text "SD_DATA0" (rect 1114 1768 1185 1783)(font "Arial" ))
+	(pt 1104 1784)
+	(pt 1264 1784)
+)
+(connector
+	(text "SD_DATA1" (rect 1114 1792 1185 1807)(font "Arial" ))
+	(pt 1104 1808)
+	(pt 1264 1808)
+)
+(connector
+	(text "SD_DATA2" (rect 1114 1816 1185 1831)(font "Arial" ))
+	(pt 1104 1832)
+	(pt 1264 1832)
+)
+(connector
+	(text "SD_WP" (rect 1114 1864 1164 1879)(font "Arial" ))
+	(pt 1104 1880)
+	(pt 1264 1880)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 2536 1240 2551)(font "Arial" ))
+	(pt 1112 2552)
+	(pt 1264 2552)
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+)
+(connector
+	(text "nFB_WR" (rect 1162 2416 1219 2431)(font "Arial" ))
+	(pt 1152 2432)
+	(pt 1264 2432)
+)
+(connector
+	(text "nFB_CS1" (rect 1154 2440 1216 2455)(font "Arial" ))
+	(pt 1152 2456)
+	(pt 1264 2456)
+)
+(connector
+	(text "FB_SIZE0" (rect 1154 2488 1218 2503)(font "Arial" ))
+	(pt 1152 2504)
+	(pt 1264 2504)
+)
+(connector
+	(text "FB_SIZE1" (rect 1154 2512 1218 2527)(font "Arial" ))
+	(pt 1152 2528)
+	(pt 1264 2528)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 2368 1231 2383)(font "Arial" ))
+	(pt 1152 2384)
+	(pt 1264 2384)
+)
+(connector
+	(text "nFB_CS2" (rect 1162 2464 1224 2479)(font "Arial" ))
+	(pt 1152 2480)
+	(pt 1264 2480)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 2384 1765 2399)(font "Arial" ))
+	(pt 1832 2400)
+	(pt 1672 2400)
+	(bus)
+)
+(connector
+	(text "nSCSI_ACK" (rect 1682 1104 1759 1119)(font "Arial" ))
+	(pt 1672 1120)
+	(pt 1840 1120)
+)
+(connector
+	(text "SCSI_PAR" (rect 1682 1080 1751 1095)(font "Arial" ))
+	(pt 1672 1096)
+	(pt 1840 1096)
+)
+(connector
+	(text "MIDI_OLR" (rect 1762 1256 1828 1271)(font "Arial" ))
+	(pt 1672 1272)
+	(pt 1920 1272)
+)
+(connector
+	(text "MIDI_TLR" (rect 1770 1280 1833 1295)(font "Arial" ))
+	(pt 1672 1296)
+	(pt 1920 1296)
+)
+(connector
+	(text "nROM3" (rect 1754 1600 1802 1615)(font "Arial" ))
+	(pt 1672 1616)
+	(pt 1920 1616)
+)
+(connector
+	(text "nROM4" (rect 1754 1624 1802 1639)(font "Arial" ))
+	(pt 1672 1640)
+	(pt 1920 1640)
+)
+(connector
+	(text "nRP_UDS" (rect 1744 1648 1811 1663)(font "Arial" ))
+	(pt 1672 1664)
+	(pt 1920 1664)
+)
+(connector
+	(text "nRP_LDS" (rect 1746 1672 1810 1687)(font "Arial" ))
+	(pt 1672 1688)
+	(pt 1920 1688)
+)
+(connector
+	(text "YM_QA" (rect 1762 1904 1808 1919)(font "Arial" ))
+	(pt 1672 1920)
+	(pt 1928 1920)
+)
+(connector
+	(text "YM_QB" (rect 1762 1928 1809 1943)(font "Arial" ))
+	(pt 1672 1944)
+	(pt 1928 1944)
+)
+(connector
+	(text "YM_QC" (rect 1762 1952 1810 1967)(font "Arial" ))
+	(pt 1672 1968)
+	(pt 1928 1968)
+)
+(connector
+	(text "LP_BUSY" (rect 1114 1160 1177 1175)(font "Arial" ))
+	(pt 1264 1176)
+	(pt 1104 1176)
+)
+(connector
+	(text "nACSI_DRQ" (rect 1034 1192 1114 1207)(font "Arial" ))
+	(pt 1024 1208)
+	(pt 1264 1208)
+)
+(connector
+	(text "nACSI_INT" (rect 1034 1216 1104 1231)(font "Arial" ))
+	(pt 1024 1232)
+	(pt 1264 1232)
+)
+(connector
+	(text "MIDI_IN" (rect 1050 1352 1100 1367)(font "Arial" ))
+	(pt 1040 1368)
+	(pt 1264 1368)
+)
+(connector
+	(text "RxD" (rect 1114 1384 1141 1399)(font "Arial" ))
+	(pt 1264 1400)
+	(pt 1104 1400)
+)
+(connector
+	(text "nINDEX" (rect 1050 1640 1100 1655)(font "Arial" ))
+	(pt 1040 1656)
+	(pt 1264 1656)
+)
+(connector
+	(text "TRACK00" (rect 1050 1664 1113 1679)(font "Arial" ))
+	(pt 1040 1680)
+	(pt 1264 1680)
+)
+(connector
+	(text "nWP" (rect 1050 1688 1080 1703)(font "Arial" ))
+	(pt 1040 1704)
+	(pt 1264 1704)
+)
+(connector
+	(text "nRD_DATA" (rect 1050 1712 1123 1727)(font "Arial" ))
+	(pt 1040 1728)
+	(pt 1264 1728)
+)
+(connector
+	(text "nDCHG" (rect 1050 1736 1100 1751)(font "Arial" ))
+	(pt 1040 1752)
+	(pt 1264 1752)
+)
+(connector
+	(text "SD_CARD_DEDECT" (rect 1138 1840 1273 1855)(font "Arial" ))
+	(pt 1264 1856)
+	(pt 1128 1856)
+)
+(connector
+	(text "SD_CD_DATA3" (rect 1682 1984 1783 1999)(font "Arial" ))
+	(pt 1672 2000)
+	(pt 1856 2000)
+)
+(connector
+	(text "SD_CDM_D1" (rect 1682 2008 1769 2023)(font "Arial" ))
+	(pt 1672 2024)
+	(pt 1856 2024)
+)
+(connector
+	(text "nSCSI_C_D" (rect 1114 1272 1193 1287)(font "Arial" ))
+	(pt 1104 1288)
+	(pt 1264 1288)
+)
+(connector
+	(text "nSCSI_I_O" (rect 1114 1296 1185 1311)(font "Arial" ))
+	(pt 1104 1312)
+	(pt 1264 1312)
+)
+(connector
+	(text "DSA_D" (rect 1682 1704 1729 1719)(font "Arial" ))
+	(pt 1672 1720)
+	(pt 1856 1720)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 8 1765 23)(font "Arial" ))
+	(pt 1832 24)
+	(pt 1672 24)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 328 1240 343)(font "Arial" ))
+	(pt 1112 344)
+	(pt 1264 344)
+	(bus)
+)
+(connector
+	(text "nFB_WR" (rect 1162 184 1219 199)(font "Arial" ))
+	(pt 1152 200)
+	(pt 1264 200)
+)
+(connector
+	(text "nFB_CS1" (rect 1154 208 1216 223)(font "Arial" ))
+	(pt 1152 224)
+	(pt 1264 224)
+)
+(connector
+	(text "FB_SIZE0" (rect 1154 256 1218 271)(font "Arial" ))
+	(pt 1152 272)
+	(pt 1264 272)
+)
+(connector
+	(text "FB_SIZE1" (rect 1154 280 1218 295)(font "Arial" ))
+	(pt 1152 296)
+	(pt 1264 296)
+)
+(connector
+	(text "nFB_CS2" (rect 1162 232 1224 247)(font "Arial" ))
+	(pt 1152 248)
+	(pt 1264 248)
+)
+(connector
+	(text "nBLANK" (rect 1682 184 1736 199)(font "Arial" ))
+	(pt 1672 200)
+	(pt 1832 200)
+)
+(connector
+	(text "nSYNC" (rect 1682 208 1729 223)(font "Arial" ))
+	(pt 1672 224)
+	(pt 1832 224)
+)
+(connector
+	(text "nFB_CS3" (rect 1186 352 1248 367)(font "Arial" ))
+	(pt 1264 368)
+	(pt 1176 368)
+)
+(connector
+	(text "nFB_WR" (rect 1170 928 1227 943)(font "Arial" ))
+	(pt 1264 944)
+	(pt 1160 944)
+)
+(connector
+	(text "nFB_CS1" (rect 1162 952 1224 967)(font "Arial" ))
+	(pt 1264 968)
+	(pt 1160 968)
+)
+(connector
+	(text "nFB_CS2" (rect 1170 976 1232 991)(font "Arial" ))
+	(pt 1264 992)
+	(pt 1160 992)
+)
+(connector
+	(text "FB_SIZE0" (rect 1162 1000 1226 1015)(font "Arial" ))
+	(pt 1264 1016)
+	(pt 1160 1016)
+)
+(connector
+	(text "FB_SIZE1" (rect 1162 1024 1226 1039)(font "Arial" ))
+	(pt 1264 1040)
+	(pt 1160 1040)
+)
+(connector
+	(text "nFB_BURST" (rect 1162 1048 1244 1063)(font "Arial" ))
+	(pt 1264 1064)
+	(pt 1160 1064)
+)
+(connector
+	(text "nDACK0" (rect 1250 1096 1305 1111)(font "Arial" ))
+	(pt 1264 1112)
+	(pt 1160 1112)
+)
+(connector
+	(text "nRSTO" (rect 1170 1120 1217 1135)(font "Arial" ))
+	(pt 1264 1136)
+	(pt 1160 1136)
+)
+(connector
+	(text "nPD_VGA" (rect 1682 256 1745 271)(font "Arial" ))
+	(pt 1672 272)
+	(pt 1832 272)
+)
+(connector
+	(text "PIC_INT" (rect 1162 2584 1216 2599)(font "Arial" ))
+	(pt 1152 2600)
+	(pt 1264 2600)
+)
+(connector
+	(text "nIRQ[7..2]" (rect 1682 2408 1745 2423)(font "Arial" ))
+	(pt 1672 2424)
+	(pt 1832 2424)
+	(bus)
+)
+(connector
+	(text "CLK2M4576" (rect 1202 856 1282 871)(font "Arial" ))
+	(pt 1192 872)
+	(pt 1264 872)
+)
+(connector
+	(text "nFB_OE" (rect 1170 904 1224 919)(font "Arial" ))
+	(pt 1264 920)
+	(pt 1160 920)
+)
+(connector
+	(text "nFB_OE" (rect 1170 160 1224 175)(font "Arial" ))
+	(pt 1264 176)
+	(pt 1160 176)
+)
+(connector
+	(text "nFB_OE" (rect 1170 2392 1224 2407)(font "Arial" ))
+	(pt 1264 2408)
+	(pt 1160 2408)
+)
+(connector
+	(text "DVI_INT" (rect 1162 2632 1215 2647)(font "Arial" ))
+	(pt 1152 2648)
+	(pt 1264 2648)
+)
+(connector
+	(text "nPCI_INTA" (rect 1162 2728 1232 2743)(font "Arial" ))
+	(pt 1152 2744)
+	(pt 1264 2744)
+)
+(connector
+	(text "nPCI_INTB" (rect 1162 2704 1233 2719)(font "Arial" ))
+	(pt 1152 2720)
+	(pt 1264 2720)
+)
+(connector
+	(text "nPCI_INTC" (rect 1162 2680 1235 2695)(font "Arial" ))
+	(pt 1152 2696)
+	(pt 1264 2696)
+)
+(connector
+	(text "nPCI_INTD" (rect 1162 2656 1235 2671)(font "Arial" ))
+	(pt 1152 2672)
+	(pt 1264 2672)
+)
+(connector
+	(text "nMFP_INT" (rect 1162 2760 1229 2775)(font "Arial" ))
+	(pt 1152 2776)
+	(pt 1264 2776)
+)
+(connector
+	(text "nMFP_INT" (rect 1682 2072 1749 2087)(font "Arial" ))
+	(pt 1672 2088)
+	(pt 1784 2088)
+)
+(connector
+	(text "E0_INT" (rect 1162 2608 1210 2623)(font "Arial" ))
+	(pt 1152 2624)
+	(pt 1264 2624)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 2968 1765 2983)(font "Arial" ))
+	(pt 1832 2984)
+	(pt 1672 2984)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 3224 1240 3239)(font "Arial" ))
+	(pt 1112 3240)
+	(pt 1264 3240)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 3008 1231 3023)(font "Arial" ))
+	(pt 1152 3024)
+	(pt 1264 3024)
+)
+(connector
+	(text "CLK33M" (rect 1210 2984 1265 2999)(font "Arial" ))
+	(pt 1200 3000)
+	(pt 1264 3000)
+)
+(connector
+	(text "nFB_WR" (rect 1170 3056 1227 3071)(font "Arial" ))
+	(pt 1264 3072)
+	(pt 1160 3072)
+)
+(connector
+	(text "nFB_CS1" (rect 1162 3080 1224 3095)(font "Arial" ))
+	(pt 1264 3096)
+	(pt 1160 3096)
+)
+(connector
+	(text "nFB_CS2" (rect 1170 3104 1232 3119)(font "Arial" ))
+	(pt 1264 3120)
+	(pt 1160 3120)
+)
+(connector
+	(text "FB_SIZE0" (rect 1162 3152 1226 3167)(font "Arial" ))
+	(pt 1264 3168)
+	(pt 1160 3168)
+)
+(connector
+	(text "FB_SIZE1" (rect 1162 3176 1226 3191)(font "Arial" ))
+	(pt 1264 3192)
+	(pt 1160 3192)
+)
+(connector
+	(text "nFB_BURST" (rect 1162 3200 1244 3215)(font "Arial" ))
+	(pt 1264 3216)
+	(pt 1160 3216)
+)
+(connector
+	(text "nRSTO" (rect 1170 3248 1217 3263)(font "Arial" ))
+	(pt 1264 3264)
+	(pt 1160 3264)
+)
+(connector
+	(text "nFB_OE" (rect 1170 3032 1224 3047)(font "Arial" ))
+	(pt 1264 3048)
+	(pt 1160 3048)
+)
+(connector
+	(text "nSRCS" (rect 1682 3272 1730 3287)(font "Arial" ))
+	(pt 1824 3288)
+	(pt 1672 3288)
+)
+(connector
+	(text "nSRBLE" (rect 1682 3296 1737 3311)(font "Arial" ))
+	(pt 1824 3312)
+	(pt 1672 3312)
+)
+(connector
+	(text "nSRBHE" (rect 1682 3320 1739 3335)(font "Arial" ))
+	(pt 1824 3336)
+	(pt 1672 3336)
+)
+(connector
+	(text "nSRWE" (rect 1682 3344 1732 3359)(font "Arial" ))
+	(pt 1824 3360)
+	(pt 1672 3360)
+)
+(connector
+	(text "nSROE" (rect 1682 3368 1730 3383)(font "Arial" ))
+	(pt 1824 3384)
+	(pt 1672 3384)
+)
+(connector
+	(text "DSP_INT" (rect 1130 2832 1190 2847)(font "Arial" ))
+	(pt 1264 2848)
+	(pt 1120 2848)
+)
+(connector
+	(text "DSP_INT" (rect 1682 3000 1742 3015)(font "Arial" ))
+	(pt 1816 3016)
+	(pt 1672 3016)
+)
+(connector
+	(text "CLK500k" (rect 482 2040 542 2055)(font "Arial" ))
+	(pt 472 2056)
+	(pt 544 2056)
+)
+(connector
+	(pt 528 2416)
+	(pt 616 2416)
+)
+(connector
+	(text "FB_ALE" (rect 1194 304 1245 319)(font "Arial" ))
+	(pt 1264 320)
+	(pt 1184 320)
+)
+(connector
+	(text "DDRCLK[3..0]" (rect 1162 136 1252 151)(font "Arial" ))
+	(pt 1152 152)
+	(pt 1264 152)
+	(bus)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 1178 112 1292 127)(font "Arial" ))
+	(pt 1168 128)
+	(pt 1264 128)
+)
+(connector
+	(text "VD[31..0]" (rect 1682 288 1739 303)(font "Arial" ))
+	(pt 1672 304)
+	(pt 2648 304)
+	(bus)
+)
+(connector
+	(text "VA[12..0]" (rect 1682 312 1737 327)(font "Arial" ))
+	(pt 1672 328)
+	(pt 2528 328)
+	(bus)
+)
+(connector
+	(text "nVWE" (rect 1682 336 1720 351)(font "Arial" ))
+	(pt 1672 352)
+	(pt 2400 352)
+)
+(connector
+	(text "nVCAS" (rect 1690 360 1734 375)(font "Arial" ))
+	(pt 1672 376)
+	(pt 2304 376)
+)
+(connector
+	(text "nVRAS" (rect 1690 384 1734 399)(font "Arial" ))
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+)
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+	(text "nVCS" (rect 1690 408 1726 423)(font "Arial" ))
+	(pt 1672 424)
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+)
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+	(text "VCKE" (rect 1690 432 1727 447)(font "Arial" ))
+	(pt 1672 448)
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+(connector
+	(text "VSYNC" (rect 1682 136 1729 151)(font "Arial" ))
+	(pt 1672 152)
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+)
+(connector
+	(text "HSYNC" (rect 1682 160 1731 175)(font "Arial" ))
+	(pt 1672 176)
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+(connector
+	(text "VB[7..0]" (rect 1754 112 1802 127)(font "Arial" ))
+	(pt 1672 128)
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+	(text "VG[7..0]" (rect 1842 88 1891 103)(font "Arial" ))
+	(pt 1672 104)
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+	(text "VR[7..0]" (rect 1922 64 1971 79)(font "Arial" ))
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+	(text "IO[17..0]" (rect 1962 3224 2015 3239)(font "Arial" ))
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+(connector
+	(text "SRD[15..0]" (rect 1802 3248 1871 3263)(font "Arial" ))
+	(pt 1672 3264)
+	(pt 1944 3264)
+	(bus)
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+(connector
+	(text "SCSI_D[7..0]" (rect 1786 1056 1868 1071)(font "Arial" ))
+	(pt 1672 1072)
+	(pt 1936 1072)
+	(bus)
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+(connector
+	(text "ACSI_D[7..0]" (rect 1754 880 1835 895)(font "Arial" ))
+	(pt 1672 896)
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+(connector
+	(text "LP_D[7..0]" (rect 1810 800 1877 815)(font "Arial" ))
+	(pt 1672 816)
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+	(text "AMKB_RX" (rect 786 1480 850 1495)(font "Arial" ))
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+	(pt 1264 1496)
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+	(pt 336 304)
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+	(text "CLK25M" (rect 1202 608 1257 623)(font "Arial" ))
+	(pt 1192 624)
+	(pt 1264 624)
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+(connector
+	(text "TIMEBASE[17]" (rect 354 2120 446 2135)(font "Arial" ))
+	(pt 440 2136)
+	(pt 344 2136)
+)
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+	(text "TIMEBASE[17..0]" (rect 706 2048 813 2063)(font "Arial" ))
+	(pt 688 2064)
+	(pt 808 2064)
+	(bus)
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+	(pt 1672 2848)
+	(pt 1808 2848)
+)
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+	(text "DSP_TA" (rect 1682 3504 1736 3519)(font "Arial" ))
+	(pt 1672 3520)
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+	(pt 1672 712)
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+	(pt 2464 72)
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+	(pt 2712 40)
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+	(pt 2136 -64)
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+	(pt 2440 160)
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+	(pt 1160 3144)
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+	(pt 1144 1984)
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+	(pt 1264 1960)
+	(pt 1144 1960)
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+	(pt 1672 1768)
+	(pt 1856 1768)
+)
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+	(pt 2136 1768)
+)
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+	(pt 1904 1816)
+	(pt 2136 1816)
+)
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+	(text "WR_DATA" (rect 1682 1800 1749 1815)(font "Arial" ))
+	(pt 1672 1816)
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+)
+(connector
+	(text "DMA_DRQ" (rect 1130 2856 1199 2871)(font "Arial" ))
+	(pt 1264 2872)
+	(pt 1120 2872)
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+	(pt 1784 2112)
+	(pt 1672 2112)
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+	(text "FDC_CLK" (rect 1202 880 1268 895)(font "Arial" ))
+	(pt 1192 896)
+	(pt 1264 896)
+)
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+	(text "MOT_ON" (rect 1626 1728 1685 1743)(font "Arial" ))
+	(pt 1672 1744)
+	(pt 1800 1744)
+)
+(connector
+	(pt 1848 1744)
+	(pt 2136 1744)
+)
+(connector
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+	(pt 1672 1792)
+	(pt 1800 1792)
+)
+(connector
+	(pt 1848 1792)
+	(pt 2136 1792)
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+	(pt 1672 1840)
+	(pt 1800 1840)
+)
+(connector
+	(pt 1848 1840)
+	(pt 2136 1840)
+)
+(connector
+	(text "FB_ALE" (rect 1186 1992 1237 2007)(font "Arial" ))
+	(pt 1144 2008)
+	(pt 1264 2008)
+)
+(connector
+	(text "AMKB_TX" (rect 1946 1392 2008 1407)(font "Arial" ))
+	(pt 1672 1408)
+	(pt 2112 1408)
+)
+(connector
+	(text "PIC_AMKB_RX" (rect 786 1504 882 1519)(font "Arial" ))
+	(pt 776 1520)
+	(pt 1264 1520)
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+	(pt 440 -16)
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+	(text "CLK2M" (rect 754 -32 801 -17)(font "Arial" ))
+	(pt 744 -16)
+	(pt 816 -16)
+)
+(connector
+	(text "FDC_CLK" (rect 754 -8 820 7)(font "Arial" ))
+	(pt 744 8)
+	(pt 816 8)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 370 1352 453 1367)(font "Arial" ))
+	(pt 352 1368)
+	(pt 464 1368)
+	(bus)
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+(connector
+	(text "FB_ADR[31..0]" (rect 642 1376 736 1391)(font "Arial" ))
+	(pt 608 1392)
+	(pt 760 1392)
+	(bus)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 378 1368 492 1383)(font "Arial" ))
+	(pt 368 1384)
+	(pt 464 1384)
+)
+(connector
+	(text "FB_ALE" (rect 386 1384 437 1399)(font "Arial" ))
+	(pt 376 1400)
+	(pt 464 1400)
+)
+(connector
+	(text "ACP_CONF[31..0]" (rect 1682 2568 1797 2583)(font "Arial" ))
+	(pt 1672 2584)
+	(pt 1832 2584)
+	(bus)
+)
+(connector
+	(text "ACP_CONF[31..24]" (rect 1146 2064 1269 2079)(font "Arial" ))
+	(pt 1136 2080)
+	(pt 1264 2080)
+	(bus)
+)
+(connector
+	(text "TIN0" (rect 1682 2624 1712 2639)(font "Arial" ))
+	(pt 1832 2640)
+	(pt 1672 2640)
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+	(pt 1856 -48)
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+	(pt 1896 -64)
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+	(pt 2424 -64)
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+	(pt 2424 -80)
+	(pt 2424 -64)
+)
+(connector
+	(text "HD_DD" (rect 1050 1616 1100 1631)(font "Arial" ))
+	(pt 1040 1632)
+	(pt 1264 1632)
+)
+(connector
+	(text "CLK48M" (rect 754 40 809 55)(font "Arial" ))
+	(pt 744 56)
+	(pt 840 56)
+)
+(connector
+	(text "CLK25M" (rect 754 16 809 31)(font "Arial" ))
+	(pt 744 32)
+	(pt 864 32)
+)
+(connector
+	(text "DDRCLK[0]" (rect 762 -296 837 -281)(font "Arial" ))
+	(pt 752 -280)
+	(pt 848 -280)
+)
+(connector
+	(text "DDRCLK[1]" (rect 762 -272 837 -257)(font "Arial" ))
+	(pt 752 -256)
+	(pt 848 -256)
+)
+(connector
+	(text "DDRCLK[2]" (rect 762 -248 837 -233)(font "Arial" ))
+	(pt 752 -232)
+	(pt 848 -232)
+)
+(connector
+	(text "DDRCLK[3]" (rect 762 -224 837 -209)(font "Arial" ))
+	(pt 752 -208)
+	(pt 848 -208)
+)
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+	(text "DDR_SYNC_66M" (rect 762 -200 876 -185)(font "Arial" ))
+	(pt 752 -184)
+	(pt 848 -184)
+)
+(connector
+	(pt 408 672)
+	(pt 472 672)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 74 496 199 511)(font "Arial" ))
+	(pt 192 512)
+	(pt 64 512)
+)
+(connector
+	(text "MAIN_CLK" (rect 330 -296 399 -281)(font "Arial" ))
+	(pt 264 -280)
+	(pt 448 -280)
+)
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+	(pt 408 640)
+	(pt 472 640)
+)
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+	(pt 408 624)
+	(pt 512 624)
+)
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+	(text "VR_D[8..0]" (rect 418 552 486 567)(font "Arial" ))
+	(pt 496 568)
+	(pt 408 568)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 122 664 191 679)(font "Arial" ))
+	(pt 112 680)
+	(pt 192 680)
+)
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+	(pt 408 720)
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+	(text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" ))
+	(pt 192 584)
+	(pt 72 584)
+	(bus)
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+	(pt 192 600)
+	(pt 72 600)
+	(bus)
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+	(text "VR_RD" (rect 98 512 146 527)(font "Arial" ))
+	(pt 64 528)
+	(pt 192 528)
+)
+(connector
+	(text "VR_WR" (rect 98 528 148 543)(font "Arial" ))
+	(pt 64 544)
+	(pt 192 544)
+)
+(connector
+	(text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" ))
+	(pt 1144 480)
+	(pt 1264 480)
+	(bus)
+)
+(connector
+	(text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" ))
+	(pt 2040 544)
+	(pt 1960 544)
+	(bus)
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+	(pt 1672 544)
+	(pt 1888 544)
+	(bus)
+)
+(connector
+	(pt 1888 544)
+	(pt 1888 568)
+	(bus)
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+	(text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" ))
+	(pt 1944 568)
+	(pt 1888 568)
+	(bus)
+)
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+	(pt 1672 520)
+	(pt 1960 520)
+	(bus)
+)
+(connector
+	(pt 1960 544)
+	(pt 1960 520)
+	(bus)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" ))
+	(pt 1672 576)
+	(pt 1792 576)
+)
+(connector
+	(text "VR_WR" (rect 1698 592 1748 607)(font "Arial" ))
+	(pt 1672 608)
+	(pt 1792 608)
+)
+(connector
+	(text "VR_BUSY" (rect 418 496 482 511)(font "Arial" ))
+	(pt 408 512)
+	(pt 480 512)
+)
+(connector
+	(text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" ))
+	(pt 1144 464)
+	(pt 1264 464)
+)
+(connector
+	(text "VR_RD" (rect 1698 576 1746 591)(font "Arial" ))
+	(pt 1792 592)
+	(pt 1672 592)
+)
+(connector
+	(text "nRSTO" (rect -86 680 -39 695)(font "Arial" ))
+	(pt -96 696)
+	(pt -16 696)
+)
+(connector
+	(pt 32 696)
+	(pt 192 696)
+)
+(connector
+	(text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" ))
+	(pt 72 568)
+	(pt 192 568)
+	(bus)
+)
+(connector
+	(text "CLK48M" (rect 538 552 593 567)(font "Arial" ))
+	(pt 528 568)
+	(pt 608 568)
+)
+(connector
+	(text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" ))
+	(pt 984 568)
+	(pt 1264 568)
+)
+(connector
+	(text "CLK33M" (rect 1202 584 1257 599)(font "Arial" ))
+	(pt 1264 600)
+	(pt 1192 600)
+)
+(connector
+	(text "CLK500k" (rect 802 232 862 247)(font "Arial" ))
+	(pt 768 248)
+	(pt 864 248)
+)
+(connector
+	(text "CLK2M4576" (rect 802 256 882 271)(font "Arial" ))
+	(pt 768 272)
+	(pt 864 272)
+)
+(connector
+	(text "CLK24M576" (rect 802 280 882 295)(font "Arial" ))
+	(pt 768 296)
+	(pt 864 296)
+)
+(connector
+	(text "nRSTO" (rect 1018 424 1065 439)(font "Arial" ))
+	(pt 1008 440)
+	(pt 1096 440)
+)
+(connector
+	(pt 768 320)
+	(pt 872 320)
+)
+(connector
+	(pt 872 432)
+	(pt 944 432)
+)
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+	(pt 840 448)
+	(pt 944 448)
+)
+(connector
+	(pt 872 320)
+	(pt 872 432)
+)
+(connector
+	(text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" ))
+	(pt 2304 -80)
+	(pt 2424 -80)
+)
+(connector
+	(pt 2424 -80)
+	(pt 2464 -80)
+)
+(connector
+	(text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" ))
+	(pt 1736 -64)
+	(pt 1856 -64)
+)
+(junction (pt 2504 760))
+(junction (pt 400 248))
+(junction (pt 1856 -64))
+(junction (pt 2424 -80))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
new file mode 100644
index 0000000..1674c93
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.done
@@ -0,0 +1 @@
+Wed Dec 15 02:25:24 2010
diff --git a/FPGA_by_Fredi/firebee1.dpf b/FPGA_by_Fredi/firebee1.dpf
new file mode 100644
index 0000000..f0b3ecc
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.dpf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<pin_planner>
+	<pin_info>
+	</pin_info>
+	<buses>
+	</buses>
+	<group_file_association>
+	</group_file_association>
+	<pin_planner_file_specifies>
+	</pin_planner_file_specifies>
+</pin_planner>
diff --git a/FPGA_by_Fredi/firebee1.fit.rpt b/FPGA_by_Fredi/firebee1.fit.rpt
new file mode 100644
index 0000000..e3df129
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.fit.rpt
@@ -0,0 +1,6866 @@
+Fitter report for firebee1
+Wed Dec 15 02:25:03 2010
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Fitter Netlist Optimizations
+  7. Ignored Assignments
+  8. Incremental Compilation Preservation Summary
+  9. Incremental Compilation Partition Settings
+ 10. Incremental Compilation Placement Preservation
+ 11. Pin-Out File
+ 12. Fitter Resource Usage Summary
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Output Pin Default Load For Reported TCO
+ 22. Fitter Resource Utilization by Entity
+ 23. Delay Chain Summary
+ 24. Pad To Core Delay Chain Fanout
+ 25. Control Signals
+ 26. Global & Other Fast Signals
+ 27. Non-Global High Fan-Out Signals
+ 28. Fitter RAM Summary
+ 29. Fitter DSP Block Usage Summary
+ 30. DSP Block Details
+ 31. Interconnect Usage Summary
+ 32. LAB Logic Elements
+ 33. LAB-wide Signals
+ 34. LAB Signals Sourced
+ 35. LAB Signals Sourced Out
+ 36. LAB Distinct Inputs
+ 37. I/O Rules Summary
+ 38. I/O Rules Details
+ 39. I/O Rules Matrix
+ 40. Fitter Device Options
+ 41. Operating Settings and Conditions
+ 42. Estimated Delay Added for Hold Timing
+ 43. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Fitter Summary                                                                    ;
++------------------------------------+----------------------------------------------+
+; Fitter Status                      ; Successful - Wed Dec 15 02:25:02 2010        ;
+; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name                      ; firebee1                                     ;
+; Top-level Entity Name              ; firebee1                                     ;
+; Family                             ; Cyclone III                                  ;
+; Device                             ; EP3C40F484C6                                 ;
+; Timing Models                      ; Final                                        ;
+; Total logic elements               ; 9,526 / 39,600 ( 24 % )                      ;
+;     Total combinational functions  ; 8,061 / 39,600 ( 20 % )                      ;
+;     Dedicated logic registers      ; 4,563 / 39,600 ( 12 % )                      ;
+; Total registers                    ; 4749                                         ;
+; Total pins                         ; 295 / 332 ( 89 % )                           ;
+; Total virtual pins                 ; 0                                            ;
+; Total memory bits                  ; 109,344 / 1,161,216 ( 9 % )                  ;
+; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % )                              ;
+; Total PLLs                         ; 4 / 4 ( 100 % )                              ;
++------------------------------------+----------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C40F484C6                          ;                                       ;
+; Use TimeQuest Timing Analyzer                                              ; Off                                   ; On                                    ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; On                                    ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; On                                    ; Off                                   ;
+; Perform Register Duplication for Performance                               ; On                                    ; Off                                   ;
+; Physical Synthesis Effort Level                                            ; Fast                                  ; Normal                                ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; Off                                   ; Off                                   ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; On                                    ; On                                    ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Stop After Congestion Map Generation                                       ; Off                                   ; Off                                   ;
+; Save Intermediate Fitting Results                                          ; Off                                   ; Off                                   ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; Use Best Effort Settings for Compilation                                   ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++------------------------------------------------------+
+; I/O Assignment Warnings                              ;
++---------------+--------------------------------------+
+; Pin Name      ; Reason                               ;
++---------------+--------------------------------------+
+; LP_STR        ; Missing drive strength               ;
+; nACSI_ACK     ; Missing drive strength               ;
+; nACSI_RESET   ; Missing drive strength               ;
+; nACSI_CS      ; Missing drive strength               ;
+; ACSI_DIR      ; Missing drive strength               ;
+; ACSI_A1       ; Missing drive strength               ;
+; nSCSI_ACK     ; Missing drive strength               ;
+; nSCSI_ATN     ; Missing drive strength               ;
+; SCSI_DIR      ; Missing drive strength               ;
+; MIDI_OLR      ; Missing drive strength               ;
+; MIDI_TLR      ; Missing drive strength               ;
+; TxD           ; Missing drive strength               ;
+; RTS           ; Missing drive strength               ;
+; DTR           ; Missing drive strength               ;
+; IDE_RES       ; Missing drive strength               ;
+; nIDE_CS0      ; Missing drive strength               ;
+; nIDE_CS1      ; Missing drive strength               ;
+; nIDE_WR       ; Missing drive strength               ;
+; nIDE_RD       ; Missing drive strength               ;
+; nCF_CS0       ; Missing drive strength               ;
+; nCF_CS1       ; Missing drive strength               ;
+; nROM3         ; Missing drive strength               ;
+; nROM4         ; Missing drive strength               ;
+; nRP_UDS       ; Missing drive strength               ;
+; nRP_LDS       ; Missing drive strength               ;
+; nSDSEL        ; Missing drive strength               ;
+; nWR_GATE      ; Missing drive strength               ;
+; nWR           ; Missing drive strength               ;
+; YM_QA         ; Missing drive strength               ;
+; YM_QB         ; Missing drive strength               ;
+; YM_QC         ; Missing drive strength               ;
+; SD_CLK        ; Missing drive strength               ;
+; DSA_D         ; Missing drive strength               ;
+; nVWE          ; Missing slew rate                    ;
+; nVCAS         ; Missing slew rate                    ;
+; nVRAS         ; Missing slew rate                    ;
+; nVCS          ; Missing slew rate                    ;
+; TIN0          ; Missing drive strength               ;
+; nDREQ1        ; Missing drive strength               ;
+; LED_FPGA_OK   ; Missing slew rate                    ;
+; VCKE          ; Missing slew rate                    ;
+; nFB_TA        ; Missing drive strength               ;
+; nDDR_CLK      ; Missing slew rate                    ;
+; DDR_CLK       ; Missing slew rate                    ;
+; VSYNC_PAD     ; Missing slew rate                    ;
+; HSYNC_PAD     ; Missing slew rate                    ;
+; nBLANK_PAD    ; Missing slew rate                    ;
+; PIXEL_CLK_PAD ; Missing slew rate                    ;
+; nSYNC         ; Missing slew rate                    ;
+; nMOT_ON       ; Missing drive strength               ;
+; nSTEP_DIR     ; Missing drive strength               ;
+; nSTEP         ; Missing drive strength               ;
+; LPDIR         ; Missing drive strength               ;
+; BA[1]         ; Missing slew rate                    ;
+; BA[0]         ; Missing slew rate                    ;
+; nIRQ[7]       ; Missing drive strength               ;
+; nIRQ[6]       ; Missing drive strength               ;
+; nIRQ[5]       ; Missing drive strength               ;
+; nIRQ[4]       ; Missing drive strength and slew rate ;
+; nIRQ[3]       ; Missing drive strength and slew rate ;
+; nIRQ[2]       ; Missing drive strength and slew rate ;
+; VA[12]        ; Missing slew rate                    ;
+; VA[11]        ; Missing slew rate                    ;
+; VA[10]        ; Missing slew rate                    ;
+; VA[9]         ; Missing slew rate                    ;
+; VA[8]         ; Missing slew rate                    ;
+; VA[7]         ; Missing slew rate                    ;
+; VA[6]         ; Missing slew rate                    ;
+; VA[5]         ; Missing slew rate                    ;
+; VA[4]         ; Missing slew rate                    ;
+; VA[3]         ; Missing slew rate                    ;
+; VA[2]         ; Missing slew rate                    ;
+; VA[1]         ; Missing slew rate                    ;
+; VA[0]         ; Missing slew rate                    ;
+; VB[7]         ; Missing slew rate                    ;
+; VB[6]         ; Missing slew rate                    ;
+; VB[5]         ; Missing slew rate                    ;
+; VB[4]         ; Missing slew rate                    ;
+; VB[3]         ; Missing slew rate                    ;
+; VB[2]         ; Missing slew rate                    ;
+; VB[1]         ; Missing slew rate                    ;
+; VB[0]         ; Missing slew rate                    ;
+; VDM[3]        ; Missing slew rate                    ;
+; VDM[2]        ; Missing slew rate                    ;
+; VDM[1]        ; Missing slew rate                    ;
+; VDM[0]        ; Missing slew rate                    ;
+; VG[7]         ; Missing slew rate                    ;
+; VG[6]         ; Missing slew rate                    ;
+; VG[5]         ; Missing slew rate                    ;
+; VG[4]         ; Missing slew rate                    ;
+; VG[3]         ; Missing slew rate                    ;
+; VG[2]         ; Missing slew rate                    ;
+; VG[1]         ; Missing slew rate                    ;
+; VG[0]         ; Missing slew rate                    ;
+; VR[7]         ; Missing slew rate                    ;
+; VR[6]         ; Missing slew rate                    ;
+; VR[5]         ; Missing slew rate                    ;
+; VR[4]         ; Missing slew rate                    ;
+; VR[3]         ; Missing slew rate                    ;
+; VR[2]         ; Missing slew rate                    ;
+; VR[1]         ; Missing slew rate                    ;
+; VR[0]         ; Missing slew rate                    ;
+; VD[31]        ; Missing slew rate                    ;
+; VD[30]        ; Missing slew rate                    ;
+; VD[29]        ; Missing slew rate                    ;
+; VD[28]        ; Missing slew rate                    ;
+; VD[27]        ; Missing slew rate                    ;
+; VD[26]        ; Missing slew rate                    ;
+; VD[25]        ; Missing slew rate                    ;
+; VD[24]        ; Missing slew rate                    ;
+; VD[23]        ; Missing slew rate                    ;
+; VD[22]        ; Missing slew rate                    ;
+; VD[21]        ; Missing slew rate                    ;
+; VD[20]        ; Missing slew rate                    ;
+; VD[19]        ; Missing slew rate                    ;
+; VD[18]        ; Missing slew rate                    ;
+; VD[17]        ; Missing slew rate                    ;
+; VD[16]        ; Missing slew rate                    ;
+; VD[15]        ; Missing slew rate                    ;
+; VD[14]        ; Missing slew rate                    ;
+; VD[13]        ; Missing slew rate                    ;
+; VD[12]        ; Missing slew rate                    ;
+; VD[11]        ; Missing slew rate                    ;
+; VD[10]        ; Missing slew rate                    ;
+; VD[9]         ; Missing slew rate                    ;
+; VD[8]         ; Missing slew rate                    ;
+; VD[7]         ; Missing slew rate                    ;
+; VD[6]         ; Missing slew rate                    ;
+; VD[5]         ; Missing slew rate                    ;
+; VD[4]         ; Missing slew rate                    ;
+; VD[3]         ; Missing slew rate                    ;
+; VD[2]         ; Missing slew rate                    ;
+; VD[1]         ; Missing slew rate                    ;
+; VD[0]         ; Missing slew rate                    ;
+; VDQS[3]       ; Missing slew rate                    ;
+; VDQS[2]       ; Missing slew rate                    ;
+; VDQS[1]       ; Missing slew rate                    ;
+; VDQS[0]       ; Missing slew rate                    ;
+; SCSI_PAR      ; Missing drive strength               ;
+; nSCSI_SEL     ; Missing drive strength               ;
+; nSCSI_BUSY    ; Missing drive strength               ;
+; nSCSI_RST     ; Missing drive strength               ;
+; SD_CD_DATA3   ; Missing drive strength               ;
+; SD_CMD_D1     ; Missing drive strength               ;
+; ACSI_D[7]     ; Missing drive strength               ;
+; ACSI_D[6]     ; Missing drive strength               ;
+; ACSI_D[5]     ; Missing drive strength               ;
+; ACSI_D[4]     ; Missing drive strength               ;
+; ACSI_D[3]     ; Missing drive strength               ;
+; ACSI_D[2]     ; Missing drive strength               ;
+; ACSI_D[1]     ; Missing drive strength               ;
+; ACSI_D[0]     ; Missing drive strength               ;
+; LP_D[7]       ; Missing drive strength               ;
+; LP_D[6]       ; Missing drive strength               ;
+; LP_D[5]       ; Missing drive strength               ;
+; LP_D[4]       ; Missing drive strength               ;
+; LP_D[3]       ; Missing drive strength               ;
+; LP_D[2]       ; Missing drive strength               ;
+; LP_D[1]       ; Missing drive strength               ;
+; LP_D[0]       ; Missing drive strength               ;
+; SCSI_D[7]     ; Missing drive strength               ;
+; SCSI_D[6]     ; Missing drive strength               ;
+; SCSI_D[5]     ; Missing drive strength               ;
+; SCSI_D[4]     ; Missing drive strength               ;
+; SCSI_D[3]     ; Missing drive strength               ;
+; SCSI_D[2]     ; Missing drive strength               ;
+; SCSI_D[1]     ; Missing drive strength               ;
+; SCSI_D[0]     ; Missing drive strength               ;
++---------------+--------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+; Node                                                                                                                                                                      ; Action          ; Operation          ; Reason                            ; Node Port ; Node Port Name ; Destination Node                                                                                                                 ; Destination Port ; Destination Port Name ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR~_Duplicate_1 ; Q                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSTEP_DIR~output                                                                                                                 ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1  ; Q                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nMOT_ON~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP                                                      ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSTEP~output                                                                                                                     ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP                                                      ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1  ; Q                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nWR_GATE~output                                                                                                                  ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In                                             ; Packed Register ; Register Packing   ; PLL Source Synchronous assignment ; Q         ;                ; nRD_DATA~input                                                                                                                   ; O                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nWR~output                                                                                                                       ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSDSEL~output                                                                                                                    ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; DSA_D~output                                                                                                                     ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; RTS~output                                                                                                                       ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; DTR~output                                                                                                                       ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_STR~output                                                                                                                    ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                          ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1                    ; Q                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LPDIR~output                                                                                                                     ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[0]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[1]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[2]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[3]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[4]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[5]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[6]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[7]~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_OUTn                                                     ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSCSI_BUSY~output                                                                                                                ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0_Duplicate_1                                           ; Q                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nIDE_RD~output                                                                                                                   ; I                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0SLOAD_MUX                                                                                       ; Created         ; Register Packing   ; Timing optimization               ; COMBOUT   ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                       ; Q                ;                       ;
+; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[3]~output                                                                                                                   ; OE               ;                       ;
+; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                       ; Q                ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[2]~output                                                                                                                   ; OE               ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                       ; Q                ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[1]~output                                                                                                                   ; OE               ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                       ; Q                ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[0]~output                                                                                                                   ; OE               ;                       ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[28]~input                                                                                                                  ; O                ;                       ;
+; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[29]~input                                                                                                                  ; O                ;                       ;
+; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[30]~input                                                                                                                  ; O                ;                       ;
+; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[31]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[0]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[1]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[2]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[3]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[4]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[5]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[6]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[7]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[8]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[9]~input                                                                                                                   ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[10]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[11]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[12]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[13]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[14]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[15]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[16]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[17]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[18]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[19]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[20]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[21]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[22]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[23]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[24]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[25]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[26]~input                                                                                                                  ; O                ;                       ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[27]~input                                                                                                                  ; O                ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0                                                                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0_RESYN24_BDD25                                                                                ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~53                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54_RESYN0_BDD1                                                                                    ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~168                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~177                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~178                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN2_BDD3                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN6_BDD7                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~368                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369_RESYN18_BDD19                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~358                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN10_BDD11                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN12_BDD13                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_RESYN50_BDD51                                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN16_BDD17                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~0                                                                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~1                                                                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2                                                                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20_BDD21                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22_BDD23                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS                                                                                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS_RESYN56_BDD57                                                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add7~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add8~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT~1                                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~54                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~55                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector96~0                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add2~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~30                                           ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~31                                           ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add0~1                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~2                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]~0                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~0                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~16                                           ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_01_STRB~1                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_10_STRB~2                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add1~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add3~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add5~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~4                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~17                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~18                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add10~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add11~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_CLK~16                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan6~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan7~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan8~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux84~1                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux92~1                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux100~1                                                  ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]~3                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_A[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~16                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15                                  ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1                                         ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~12                                        ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15                                      ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~162                                                                     ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163                                                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163_RESYN8_BDD9                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~2                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~2                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~2                                                    ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~2                                                    ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~0                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~0                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~0                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~1                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~2                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~3                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~1                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~3                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~4                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~1                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~3                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~4                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]~0                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]~2                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|STRB_LOCK~0          ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:STRB_LOCK~0  ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[6]~1      ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG~13        ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|STRB_LOCK~0         ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:STRB_LOCK~0 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                          ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0_RESYN30_BDD31                                                                                                            ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5                                                                                                                         ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN26_BDD27                                                                                                           ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28_BDD29                                                                                                           ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2                                                                                                                             ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN52_BDD53                                                                                                               ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN54_BDD55                                                                                                               ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START~5                                                                                          ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_END[10]                                                                                           ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[1]~19                                                                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[10]~1                                                                                       ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28                                                                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28_RESYN32_BDD33                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~29                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~32                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~17                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~29                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~32                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_15~1                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~15                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~43                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_26~22                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_27~22                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_28~20                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_30~20                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_31~1                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|_~472                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|_~478                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|_~479                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|_~481                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|_~482                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~10                                                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~11                                                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42_BDD43                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN44_BDD45                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN46_BDD47                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN48_BDD49                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34_BDD35                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN36_BDD37                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN38_BDD39                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
+; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN40_BDD41                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                                                            ;
++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
+; Name                        ; Ignored Entity ; Ignored From ; Ignored To                 ; Ignored Value          ; Ignored Source             ;
++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
+; DDIO_INPUT_REGISTER         ; altddio_bidir  ;              ; input_cell_H               ; HIGH                   ; Compiler or HDL Assignment ;
+; DDIO_INPUT_REGISTER         ; altddio_bidir  ;              ; input_cell_L               ; LOW                    ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_0hh1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_3fh1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
+; Synchronizer Identification ; dcfifo_8fi1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
+
+
++------------------------------------------------+
+; Incremental Compilation Preservation Summary   ;
++-------------------------+----------------------+
+; Type                    ; Value                ;
++-------------------------+----------------------+
+; Netlist                 ;                      ;
+;     -- Requested        ; 0 / 0 ( 0.00 % )     ;
+;     -- Achieved         ; 0 / 0 ( 0.00 % )     ;
+;                         ;                      ;
+; Placement               ;                      ;
+;     -- Requested        ; 0 / 13829 ( 0.00 % ) ;
+;     -- Achieved         ; 0 / 13829 ( 0.00 % ) ;
+;                         ;                      ;
+; Routing (by Connection) ;                      ;
+;     -- Requested        ; 0 / 0 ( 0.00 % )     ;
+;     -- Achieved         ; 0 / 0 ( 0.00 % )     ;
++-------------------------+----------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                       ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                             ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top            ; 13829   ; 0                 ; N/A                     ; Source File       ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/FireBee/FPGA/firebee1.pin.
+
+
++----------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                              ;
++---------------------------------------------+------------------------------+
+; Resource                                    ; Usage                        ;
++---------------------------------------------+------------------------------+
+; Total logic elements                        ; 9,526 / 39,600 ( 24 % )      ;
+;     -- Combinational with no register       ; 4963                         ;
+;     -- Register only                        ; 1465                         ;
+;     -- Combinational with a register        ; 3098                         ;
+;                                             ;                              ;
+; Logic element usage by number of LUT inputs ;                              ;
+;     -- 4 input functions                    ; 4959                         ;
+;     -- 3 input functions                    ; 1861                         ;
+;     -- <=2 input functions                  ; 1241                         ;
+;     -- Register only                        ; 1465                         ;
+;                                             ;                              ;
+; Logic elements by mode                      ;                              ;
+;     -- normal mode                          ; 7262                         ;
+;     -- arithmetic mode                      ; 799                          ;
+;                                             ;                              ;
+; Total registers*                            ; 4,749 / 41,185 ( 12 % )      ;
+;     -- Dedicated logic registers            ; 4,563 / 39,600 ( 12 % )      ;
+;     -- I/O registers                        ; 186 / 1,585 ( 12 % )         ;
+;                                             ;                              ;
+; Total LABs:  partially or completely used   ; 756 / 2,475 ( 31 % )         ;
+; User inserted logic elements                ; 0                            ;
+; Virtual pins                                ; 0                            ;
+; I/O pins                                    ; 295 / 332 ( 89 % )           ;
+;     -- Clock pins                           ; 7 / 8 ( 88 % )               ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )                ;
+; Global signals                              ; 20                           ;
+; M9Ks                                        ; 23 / 126 ( 18 % )            ;
+; Total block memory bits                     ; 109,344 / 1,161,216 ( 9 % )  ;
+; Total block memory implementation bits      ; 211,968 / 1,161,216 ( 18 % ) ;
+; Embedded Multiplier 9-bit elements          ; 6 / 252 ( 2 % )              ;
+; PLLs                                        ; 4 / 4 ( 100 % )              ;
+; Global clocks                               ; 20 / 20 ( 100 % )            ;
+; JTAGs                                       ; 0 / 1 ( 0 % )                ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )                ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )                ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )                ;
+; Average interconnect usage (total/H/V)      ; 15% / 14% / 16%              ;
+; Peak interconnect usage (total/H/V)         ; 59% / 54% / 65%              ;
+; Maximum fan-out node                        ; MAIN_CLK~input               ;
+; Maximum fan-out                             ; 2272                         ;
+; Highest non-global fan-out signal           ; MAIN_CLK~input               ;
+; Highest non-global fan-out                  ; 2272                         ;
+; Total fan-out                               ; 44654                        ;
+; Average fan-out                             ; 3.02                         ;
++---------------------------------------------+------------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                          ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; AMKB_RX        ; Y2    ; 2        ; 0            ; 10           ; 21           ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CLK33M         ; AB12  ; 4        ; 36           ; 0            ; 0            ; 16                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CTS            ; H14   ; 7        ; 61           ; 43           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; DCD            ; A19   ; 7        ; 56           ; 43           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; DVI_INT        ; A11   ; 8        ; 34           ; 43           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; E0_INT         ; G21   ; 6        ; 67           ; 22           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; FB_ALE         ; R7    ; 2        ; 0            ; 2            ; 0            ; 33                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; FB_SIZE0       ; U8    ; 3        ; 3            ; 0            ; 21           ; 24                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; FB_SIZE1       ; Y4    ; 3        ; 3            ; 0            ; 14           ; 24                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; HD_DD          ; F16   ; 7        ; 65           ; 43           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; IDE_INT        ; G22   ; 6        ; 67           ; 22           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; IDE_RDY        ; Y1    ; 2        ; 0            ; 9            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; LP_BUSY        ; G7    ; 8        ; 3            ; 43           ; 28           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; MAIN_CLK       ; G2    ; 1        ; 0            ; 21           ; 0            ; 2272                  ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; MIDI_IN        ; E12   ; 7        ; 36           ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PIC_AMKB_RX    ; L7    ; 2        ; 0            ; 18           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PIC_INT        ; AA2   ; 2        ; 0            ; 7            ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; RI             ; B19   ; 7        ; 56           ; 43           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; RxD            ; H15   ; 7        ; 61           ; 43           ; 0            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SD_CARD_DEDECT ; M20   ; 5        ; 67           ; 19           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SD_DATA0       ; B16   ; 7        ; 50           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SD_DATA1       ; A16   ; 7        ; 50           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SD_DATA2       ; B17   ; 7        ; 50           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SD_WP          ; M19   ; 5        ; 67           ; 19           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; TOUT0          ; T22   ; 5        ; 67           ; 22           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; TRACK00        ; C19   ; 7        ; 61           ; 43           ; 28           ; 11                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; WP_CF_CARD     ; T1    ; 2        ; 0            ; 21           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nACSI_DRQ      ; K7    ; 1        ; 0            ; 30           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nACSI_INT      ; J4    ; 1        ; 0            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nDACK0         ; B12   ; 7        ; 34           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nDACK1         ; A12   ; 7        ; 34           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nDCHG          ; C17   ; 7        ; 56           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_BURST      ; T3    ; 2        ; 0            ; 7            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_CS1        ; T8    ; 3        ; 14           ; 0            ; 28           ; 59                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_CS2        ; T9    ; 3        ; 14           ; 0            ; 21           ; 95                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_CS3        ; V6    ; 3        ; 1            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_OE         ; R6    ; 2        ; 0            ; 3            ; 0            ; 101                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nFB_WR         ; T5    ; 2        ; 0            ; 4            ; 0            ; 235                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nINDEX         ; E16   ; 7        ; 65           ; 43           ; 28           ; 14                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nMASTER        ; T21   ; 5        ; 67           ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nPCI_INTA      ; AA1   ; 2        ; 0            ; 6            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nPCI_INTB      ; V4    ; 2        ; 0            ; 5            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nPCI_INTC      ; V3    ; 2        ; 0            ; 5            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nPCI_INTD      ; P6    ; 2        ; 0            ; 5            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nRD_DATA       ; A20   ; 7        ; 59           ; 43           ; 7            ; 0                     ; 2                  ; no     ; yes            ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nRSTO_MCF      ; B11   ; 8        ; 34           ; 43           ; 21           ; 27                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nSCSI_C_D      ; H1    ; 1        ; 0            ; 28           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nSCSI_DRQ      ; U1    ; 2        ; 0            ; 15           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nSCSI_I_O      ; J3    ; 1        ; 0            ; 28           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nSCSI_MSG      ; H2    ; 1        ; 0            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; nWP            ; D19   ; 7        ; 59           ; 43           ; 0            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
+; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
+; ACSI_A1       ; M6    ; 2        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; ACSI_DIR      ; L6    ; 2        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; AMKB_TX       ; N1    ; 2        ; 0            ; 19           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; BA[0]         ; W19   ; 5        ; 67           ; 5            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; BA[1]         ; AA19  ; 4        ; 56           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; CLK24M576     ; AB10  ; 3        ; 34           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; CLK25M        ; T4    ; 2        ; 0            ; 4            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; CLKUSB        ; J1    ; 1        ; 0            ; 28           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; DDR_CLK       ; AB17  ; 4        ; 54           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; DSA_D         ; F15   ; 7        ; 63           ; 43           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; DTR           ; D15   ; 7        ; 54           ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; HSYNC_PAD     ; K21   ; 6        ; 67           ; 27           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; IDE_RES       ; M5    ; 2        ; 0            ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; LED_FPGA_OK   ; N19   ; 5        ; 67           ; 15           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 4mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; LPDIR         ; E5    ; 8        ; 1            ; 43           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; LP_STR        ; E6    ; 8        ; 1            ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; MIDI_OLR      ; H5    ; 1        ; 0            ; 31           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; MIDI_TLR      ; B2    ; 1        ; 0            ; 41           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; PIXEL_CLK_PAD ; F19   ; 6        ; 67           ; 37           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; RTS           ; B18   ; 7        ; 54           ; 43           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; SCSI_DIR      ; J7    ; 1        ; 0            ; 30           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; SD_CLK        ; C15   ; 7        ; 50           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; TIN0          ; R5    ; 2        ; 0            ; 4            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; TxD           ; A18   ; 7        ; 54           ; 43           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[0]         ; W20   ; 5        ; 67           ; 3            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[10]        ; V21   ; 5        ; 67           ; 10           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[11]        ; U19   ; 5        ; 67           ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[12]        ; AA18  ; 4        ; 54           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[1]         ; W22   ; 5        ; 67           ; 7            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[2]         ; W21   ; 5        ; 67           ; 8            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[3]         ; Y22   ; 5        ; 67           ; 6            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[4]         ; AA22  ; 5        ; 67           ; 2            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[5]         ; Y21   ; 5        ; 67           ; 7            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[6]         ; AA21  ; 5        ; 67           ; 2            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[7]         ; AA20  ; 4        ; 61           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[8]         ; AB20  ; 4        ; 61           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VA[9]         ; AB19  ; 4        ; 59           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[0]         ; G18   ; 6        ; 67           ; 37           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[1]         ; H17   ; 6        ; 67           ; 38           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[2]         ; C22   ; 6        ; 67           ; 38           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[3]         ; C21   ; 6        ; 67           ; 38           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[4]         ; B22   ; 6        ; 67           ; 39           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[5]         ; B21   ; 6        ; 67           ; 39           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[6]         ; C20   ; 6        ; 67           ; 39           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VB[7]         ; D20   ; 6        ; 67           ; 40           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VCKE          ; U15   ; 4        ; 50           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VDM[0]        ; AA16  ; 4        ; 45           ; 0            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VDM[1]        ; V16   ; 4        ; 61           ; 0            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VDM[2]        ; U20   ; 5        ; 67           ; 7            ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VDM[3]        ; T17   ; 5        ; 67           ; 3            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[0]         ; H19   ; 6        ; 67           ; 34           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[1]         ; E22   ; 6        ; 67           ; 34           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[2]         ; E21   ; 6        ; 67           ; 34           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[3]         ; H18   ; 6        ; 67           ; 35           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[4]         ; J17   ; 6        ; 67           ; 36           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[5]         ; H16   ; 6        ; 67           ; 36           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[6]         ; D22   ; 6        ; 67           ; 36           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VG[7]         ; D21   ; 6        ; 67           ; 36           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[0]         ; J22   ; 6        ; 67           ; 28           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[1]         ; J21   ; 6        ; 67           ; 28           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[2]         ; H22   ; 6        ; 67           ; 28           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[3]         ; H21   ; 6        ; 67           ; 28           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[4]         ; K17   ; 6        ; 67           ; 29           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[5]         ; K18   ; 6        ; 67           ; 30           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[6]         ; J18   ; 6        ; 67           ; 31           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VR[7]         ; F22   ; 6        ; 67           ; 31           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; VSYNC_PAD     ; K19   ; 6        ; 67           ; 26           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; YM_QA         ; A17   ; 7        ; 52           ; 43           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; YM_QB         ; G13   ; 7        ; 52           ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; YM_QC         ; E15   ; 7        ; 54           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nACSI_ACK     ; M4    ; 2        ; 0            ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nACSI_CS      ; M2    ; 2        ; 0            ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nACSI_RESET   ; M1    ; 2        ; 0            ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nBLANK_PAD    ; G17   ; 6        ; 67           ; 41           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nCF_CS0       ; W2    ; 2        ; 0            ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nCF_CS1       ; W1    ; 2        ; 0            ; 10           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nDDR_CLK      ; AA17  ; 4        ; 54           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nDREQ1        ; E11   ; 7        ; 36           ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nFB_TA        ; T7    ; 2        ; 0            ; 2            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIDE_CS0      ; R2    ; 2        ; 0            ; 16           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIDE_CS1      ; R1    ; 2        ; 0            ; 16           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIDE_RD       ; P1    ; 2        ; 0            ; 17           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIDE_WR       ; P2    ; 2        ; 0            ; 17           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[2]       ; F21   ; 6        ; 67           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[3]       ; H20   ; 6        ; 67           ; 34           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[4]       ; F20   ; 6        ; 67           ; 37           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[5]       ; P5    ; 2        ; 0            ; 12           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[6]       ; P7    ; 2        ; 0            ; 7            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nIRQ[7]       ; N7    ; 2        ; 0            ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nMOT_ON       ; G16   ; 7        ; 63           ; 43           ; 7            ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nPD_VGA       ; V1    ; 2        ; 0            ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nROM3         ; P3    ; 2        ; 0            ; 15           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nROM4         ; U2    ; 2        ; 0            ; 15           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nRP_LDS       ; N5    ; 2        ; 0            ; 16           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nRP_UDS       ; P4    ; 2        ; 0            ; 16           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSCSI_ACK     ; N2    ; 2        ; 0            ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSCSI_ATN     ; M3    ; 2        ; 0            ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSDSEL        ; B20   ; 7        ; 59           ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSRBHE        ; B4    ; 8        ; 7            ; 43           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSRBLE        ; A4    ; 8        ; 9            ; 43           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSRCS         ; B8    ; 8        ; 25           ; 43           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSROE         ; F11   ; 7        ; 36           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSRWE         ; F8    ; 8        ; 7            ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSTEP         ; F14   ; 7        ; 63           ; 43           ; 28           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSTEP_DIR     ; G15   ; 7        ; 63           ; 43           ; 21           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nSYNC         ; F17   ; 6        ; 67           ; 41           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nVCAS         ; AB18  ; 4        ; 52           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nVCS          ; T18   ; 5        ; 67           ; 3            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nVRAS         ; W17   ; 4        ; 59           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nVWE          ; Y17   ; 4        ; 61           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nWR           ; G14   ; 7        ; 54           ; 43           ; 28           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
+; nWR_GATE      ; D17   ; 7        ; 61           ; 43           ; 14           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                                                                          ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
+; ACSI_D[0]   ; B1    ; 1        ; 0            ; 40           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[1]   ; G5    ; 1        ; 0            ; 40           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[2]   ; E3    ; 1        ; 0            ; 39           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[3]   ; C2    ; 1        ; 0            ; 38           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[4]   ; C1    ; 1        ; 0            ; 38           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[5]   ; D2    ; 1        ; 0            ; 37           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[6]   ; H7    ; 1        ; 0            ; 37           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; ACSI_D[7]   ; H6    ; 1        ; 0            ; 37           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; FB_AD[0]    ; Y3    ; 3        ; 3            ; 0            ; 7            ; 21                    ; 25                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[10]   ; W7    ; 3        ; 14           ; 0            ; 14           ; 19                    ; 27                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[11]   ; Y7    ; 3        ; 14           ; 0            ; 7            ; 19                    ; 14                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[12]   ; U9    ; 3        ; 16           ; 0            ; 21           ; 21                    ; 8                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[13]   ; V8    ; 3        ; 16           ; 0            ; 14           ; 21                    ; 13                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[14]   ; W8    ; 3        ; 16           ; 0            ; 7            ; 20                    ; 13                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[15]   ; AA7   ; 3        ; 16           ; 0            ; 0            ; 19                    ; 11                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[16]   ; AB7   ; 3        ; 18           ; 0            ; 21           ; 142                   ; 10                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted)                         ; -                   ;
+; FB_AD[17]   ; Y8    ; 3        ; 18           ; 0            ; 14           ; 144                   ; 9                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted)                         ; -                   ;
+; FB_AD[18]   ; V9    ; 3        ; 20           ; 0            ; 21           ; 144                   ; 9                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
+; FB_AD[19]   ; V10   ; 3        ; 20           ; 0            ; 14           ; 142                   ; 5                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted)                        ; -                   ;
+; FB_AD[1]    ; Y6    ; 3        ; 5            ; 0            ; 14           ; 20                    ; 158                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[20]   ; T10   ; 3        ; 18           ; 0            ; 7            ; 143                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
+; FB_AD[21]   ; U10   ; 3        ; 22           ; 0            ; 14           ; 142                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
+; FB_AD[22]   ; AA8   ; 3        ; 22           ; 0            ; 7            ; 139                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
+; FB_AD[23]   ; AB8   ; 3        ; 22           ; 0            ; 0            ; 136                   ; 2                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted)                        ; -                   ;
+; FB_AD[24]   ; T11   ; 3        ; 18           ; 0            ; 0            ; 62                    ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted)                        ; -                   ;
+; FB_AD[25]   ; AA9   ; 3        ; 27           ; 0            ; 7            ; 58                    ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted)                        ; -                   ;
+; FB_AD[26]   ; AB9   ; 3        ; 27           ; 0            ; 0            ; 56                    ; 11                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 (inverted)                        ; -                   ;
+; FB_AD[27]   ; U11   ; 3        ; 29           ; 0            ; 28           ; 47                    ; 5                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
+; FB_AD[28]   ; V11   ; 3        ; 34           ; 0            ; 28           ; 36                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
+; FB_AD[29]   ; W10   ; 3        ; 34           ; 0            ; 21           ; 32                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
+; FB_AD[2]    ; AA3   ; 3        ; 7            ; 0            ; 28           ; 20                    ; 120                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[30]   ; Y10   ; 3        ; 34           ; 0            ; 14           ; 36                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
+; FB_AD[31]   ; AA10  ; 3        ; 34           ; 0            ; 7            ; 35                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
+; FB_AD[3]    ; AB3   ; 3        ; 7            ; 0            ; 21           ; 20                    ; 97                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[4]    ; W6    ; 3        ; 7            ; 0            ; 14           ; 20                    ; 83                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[5]    ; V7    ; 3        ; 7            ; 0            ; 7            ; 20                    ; 161                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[6]    ; AA4   ; 3        ; 9            ; 0            ; 28           ; 19                    ; 27                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[7]    ; AB4   ; 3        ; 9            ; 0            ; 21           ; 18                    ; 26                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[8]    ; AA5   ; 3        ; 9            ; 0            ; 14           ; 20                    ; 34                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; FB_AD[9]    ; AB5   ; 3        ; 9            ; 0            ; 7            ; 20                    ; 22                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
+; IO[0]       ; A8    ; 8        ; 25           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[10]      ; B15   ; 7        ; 45           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[11]      ; C13   ; 7        ; 45           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[12]      ; D13   ; 7        ; 45           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[13]      ; E13   ; 7        ; 41           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[14]      ; A14   ; 7        ; 41           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[15]      ; B14   ; 7        ; 38           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[16]      ; A13   ; 7        ; 38           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[17]      ; B13   ; 7        ; 38           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[1]       ; A7    ; 8        ; 25           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[2]       ; B7    ; 8        ; 25           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[3]       ; A6    ; 8        ; 25           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[4]       ; B6    ; 8        ; 22           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[5]       ; E9    ; 8        ; 22           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[6]       ; C8    ; 8        ; 20           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[7]       ; C7    ; 8        ; 20           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[8]       ; G10   ; 8        ; 11           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; IO[9]       ; A15   ; 7        ; 45           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; LP_D[0]     ; F7    ; 8        ; 3            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[1]     ; C4    ; 8        ; 3            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[2]     ; C3    ; 8        ; 5            ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[3]     ; E7    ; 8        ; 5            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[4]     ; D6    ; 8        ; 5            ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[5]     ; B3    ; 8        ; 5            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[6]     ; A3    ; 8        ; 5            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; LP_D[7]     ; G8    ; 8        ; 7            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
+; SCSI_D[0]   ; J6    ; 1        ; 0            ; 36           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[1]   ; E1    ; 1        ; 0            ; 36           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[2]   ; F2    ; 1        ; 0            ; 35           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[3]   ; F1    ; 1        ; 0            ; 35           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[4]   ; G4    ; 1        ; 0            ; 41           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[5]   ; G3    ; 1        ; 0            ; 41           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[6]   ; L8    ; 1        ; 0            ; 31           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_D[7]   ; K8    ; 1        ; 0            ; 30           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SCSI_PAR    ; M7    ; 2        ; 0            ; 11           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SD_CD_DATA3 ; F13   ; 7        ; 45           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SD_CMD_D1   ; E14   ; 7        ; 48           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; SRD[0]      ; B5    ; 8        ; 11           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[10]     ; A9    ; 8        ; 32           ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[11]     ; B10   ; 8        ; 32           ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[12]     ; D10   ; 8        ; 32           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[13]     ; F10   ; 8        ; 9            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[14]     ; G9    ; 8        ; 1            ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[15]     ; H10   ; 8        ; 18           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[1]      ; A5    ; 8        ; 14           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[2]      ; C6    ; 8        ; 9            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[3]      ; G11   ; 8        ; 27           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[4]      ; C10   ; 8        ; 29           ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[5]      ; F9    ; 8        ; 1            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[6]      ; E10   ; 8        ; 32           ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[7]      ; H11   ; 8        ; 20           ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[8]      ; B9    ; 8        ; 29           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; SRD[9]      ; A10   ; 8        ; 32           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
+; VDQS[0]     ; AA15  ; 4        ; 43           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                    ; -                   ;
+; VDQS[1]     ; W15   ; 4        ; 52           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                    ; -                   ;
+; VDQS[2]     ; U22   ; 5        ; 67           ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                    ; -                   ;
+; VDQS[3]     ; T16   ; 4        ; 63           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90                                                                                 ; -                   ;
+; VD[0]       ; M22   ; 5        ; 67           ; 18           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[10]      ; P17   ; 5        ; 67           ; 10           ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[11]      ; R21   ; 5        ; 67           ; 13           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[12]      ; N17   ; 5        ; 67           ; 17           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[13]      ; P20   ; 5        ; 67           ; 14           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[14]      ; R22   ; 5        ; 67           ; 13           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[15]      ; N20   ; 5        ; 67           ; 15           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[16]      ; T12   ; 4        ; 45           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[17]      ; Y13   ; 4        ; 43           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[18]      ; AA13  ; 4        ; 38           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[19]      ; V14   ; 4        ; 50           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[1]       ; M21   ; 5        ; 67           ; 18           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[20]      ; U13   ; 4        ; 50           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[21]      ; V15   ; 4        ; 50           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[22]      ; W14   ; 4        ; 48           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[23]      ; AB16  ; 4        ; 45           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[24]      ; AB15  ; 4        ; 43           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[25]      ; AA14  ; 4        ; 38           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[26]      ; AB14  ; 4        ; 38           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[27]      ; V13   ; 4        ; 48           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[28]      ; W13   ; 4        ; 43           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[29]      ; AB13  ; 4        ; 38           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[2]       ; P22   ; 5        ; 67           ; 14           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[30]      ; V12   ; 4        ; 41           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[31]      ; U12   ; 4        ; 43           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[3]       ; R20   ; 5        ; 67           ; 11           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[4]       ; P21   ; 5        ; 67           ; 14           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[5]       ; R17   ; 5        ; 67           ; 10           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[6]       ; R19   ; 5        ; 67           ; 12           ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[7]       ; U21   ; 5        ; 67           ; 11           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[8]       ; V22   ; 5        ; 67           ; 10           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; VD[9]       ; R18   ; 5        ; 67           ; 12           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
+; nSCSI_BUSY  ; N8    ; 2        ; 0            ; 11           ; 14           ; 0                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; nSCSI_RST   ; N6    ; 2        ; 0            ; 12           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
+; nSCSI_SEL   ; M8    ; 2        ; 0            ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                            ;
++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As                    ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
+; D1       ; DIFFIO_L8n, DATA1, ASDO                  ; As input tri-stated            ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L10p, FLASH_nCE, nCSO             ; As input tri-stated            ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                              ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As input tri-stated            ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated            ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                              ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                              ; -                       ; Dedicated Programming Pin ;
+; N22      ; DIFFIO_R32n, DEV_OE                      ; Reserved as secondary function ; ~ALTERA_DEV_OE~         ; Dual Purpose Pin          ;
+; N21      ; DIFFIO_R32p, DEV_CLRn                    ; Reserved as secondary function ; ~ALTERA_DEV_CLRn~       ; Dual Purpose Pin          ;
+; M18      ; CONF_DONE                                ; -                              ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                              ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                              ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                              ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                              ; -                       ; Dedicated Programming Pin ;
+; K22      ; DIFFIO_R24n, nCEO                        ; Use as programming pin         ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R24p, CLKUSR                      ; Use as general purpose IO      ; HSYNC_PAD               ; Dual Purpose Pin          ;
+; E22      ; DIFFIO_R12n, nWE                         ; Use as regular IO              ; VG[1]                   ; Dual Purpose Pin          ;
+; E21      ; DIFFIO_R12p, nOE                         ; Use as regular IO              ; VG[2]                   ; Dual Purpose Pin          ;
+; F20      ; DIFFIO_R8n, nAVD                         ; Use as regular IO              ; nIRQ[4]                 ; Dual Purpose Pin          ;
+; F19      ; DIFFIO_R8n, nAVD                         ; -                              ; PIXEL_CLK_PAD           ; Dual Purpose Pin          ;
+; G18      ; DIFFIO_R7n, PADD23                       ; Use as regular IO              ; VB[0]                   ; Dual Purpose Pin          ;
+; B22      ; DIFFIO_R5n, PADD22                       ; Use as regular IO              ; VB[4]                   ; Dual Purpose Pin          ;
+; B21      ; DIFFIO_R5p, PADD21                       ; Use as regular IO              ; VB[5]                   ; Dual Purpose Pin          ;
+; C20      ; DIFFIO_R4n, PADD20, DQS2R/CQ3R,CDPCLK5   ; Use as regular IO              ; VB[6]                   ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T45p, PADD0                       ; Use as regular IO              ; RTS                     ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T41n, PADD1                       ; Use as regular IO              ; YM_QA                   ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T41p, PADD2                       ; Use as regular IO              ; SD_DATA2                ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T38n, PADD3                       ; Use as regular IO              ; SD_CMD_D1               ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T37p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO              ; SD_CD_DATA3             ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T36n, PADD5                       ; Use as regular IO              ; IO[9]                   ; Dual Purpose Pin          ;
+; B15      ; DIFFIO_T36p, PADD6                       ; Use as regular IO              ; IO[10]                  ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T35n, PADD7                       ; Use as regular IO              ; IO[11]                  ; Dual Purpose Pin          ;
+; D13      ; DIFFIO_T35p, PADD8                       ; Use as regular IO              ; IO[12]                  ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T31n, PADD9                       ; Use as regular IO              ; IO[14]                  ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T31p, PADD10                      ; Use as regular IO              ; IO[15]                  ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T29n, PADD11                      ; Use as regular IO              ; IO[16]                  ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T29p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO              ; IO[17]                  ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T27n, PADD13                      ; Use as regular IO              ; nDREQ1                  ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T27p, PADD14                      ; Use as regular IO              ; nSROE                   ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T25p, PADD15                      ; Use as regular IO              ; SRD[11]                 ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T24n, PADD16                      ; Use as regular IO              ; SRD[10]                 ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T24p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO              ; SRD[8]                  ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T20n, DATA2                       ; Use as regular IO              ; IO[0]                   ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T20p, DATA3                       ; Use as regular IO              ; nSRCS                   ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T19n, PADD18                      ; Use as regular IO              ; IO[1]                   ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T19p, DATA4                       ; Use as regular IO              ; IO[2]                   ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T18n, PADD19                      ; Use as regular IO              ; IO[3]                   ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T18p, DATA15                      ; Use as regular IO              ; IO[4]                   ; Dual Purpose Pin          ;
+; C8       ; DIFFIO_T16n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO              ; IO[6]                   ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T16p, DATA13                      ; Use as regular IO              ; IO[7]                   ; Dual Purpose Pin          ;
+; A5       ; DIFFIO_T11p, DATA5                       ; Use as regular IO              ; SRD[1]                  ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T8p, DATA6                        ; Use as regular IO              ; SRD[13]                 ; Dual Purpose Pin          ;
+; C6       ; DIFFIO_T7n, DATA7                        ; Use as regular IO              ; SRD[2]                  ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T6p, DATA8                        ; Use as regular IO              ; nSRBHE                  ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T5n, DATA9                        ; Use as regular IO              ; nSRWE                   ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T4n, DATA10                       ; Use as regular IO              ; LP_D[6]                 ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T4p, DATA11                       ; Use as regular IO              ; LP_D[5]                 ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T3p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO              ; LP_D[1]                 ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage                                              ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1        ; 30 / 36 ( 83 % )  ; 3.3V          ; --           ;
+; 2        ; 44 / 46 ( 96 % )  ; 3.3V          ; --           ;
+; 3        ; 38 / 42 ( 90 % )  ; 3.3V          ; --           ;
+; 4        ; 33 / 43 ( 77 % )  ; 2.5V          ; --           ;
+; 5        ; 37 / 42 ( 88 % )  ; 2.5V          ; --           ;
+; 6        ; 35 / 37 ( 95 % )  ; 3.0V          ; --           ;
+; 7        ; 43 / 43 ( 100 % ) ; 3.3V          ; --           ;
+; 8        ; 42 / 43 ( 98 % )  ; 3.3V          ; --           ;
++----------+-------------------+---------------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                         ;
++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                             ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 534        ; 8        ; LP_D[6]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 529        ; 8        ; nSRBLE                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 518        ; 8        ; SRD[1]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 501        ; 8        ; IO[3]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 499        ; 8        ; IO[1]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 497        ; 8        ; IO[0]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 487        ; 8        ; SRD[10]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 485        ; 8        ; SRD[9]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 481        ; 8        ; DVI_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A12      ; 479        ; 7        ; nDACK1                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A13      ; 473        ; 7        ; IO[16]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 469        ; 7        ; IO[14]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 458        ; 7        ; IO[9]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 448        ; 7        ; SD_DATA1                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 446        ; 7        ; YM_QA                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 437        ; 7        ; TxD                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A19      ; 435        ; 7        ; DCD                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 430        ; 7        ; nRD_DATA                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A21      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 125        ; 2        ; nPCI_INTA                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; AA2      ; 124        ; 2        ; PIC_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; AA3      ; 154        ; 3        ; FB_AD[2]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA4      ; 158        ; 3        ; FB_AD[6]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA5      ; 160        ; 3        ; FB_AD[8]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA6      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 173        ; 3        ; FB_AD[15]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 183        ; 3        ; FB_AD[22]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA9      ; 189        ; 3        ; FB_AD[25]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 202        ; 3        ; FB_AD[31]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA11     ; 204        ; 3        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 206        ; 4        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 208        ; 4        ; VD[18]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA14     ; 210        ; 4        ; VD[25]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA15     ; 220        ; 4        ; VDQS[0]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA16     ; 224        ; 4        ; VDM[0]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA17     ; 243        ; 4        ; nDDR_CLK                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 245        ; 4        ; VA[12]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 252        ; 4        ; BA[1]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 259        ; 4        ; VA[7]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 274        ; 5        ; VA[6]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; AA22     ; 273        ; 5        ; VA[4]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; AB1      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 155        ; 3        ; FB_AD[3]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB4      ; 159        ; 3        ; FB_AD[7]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB5      ; 161        ; 3        ; FB_AD[9]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB6      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 174        ; 3        ; FB_AD[16]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 184        ; 3        ; FB_AD[23]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB9      ; 190        ; 3        ; FB_AD[26]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 203        ; 3        ; CLK24M576                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB11     ; 205        ; 3        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 207        ; 4        ; CLK33M                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB13     ; 209        ; 4        ; VD[29]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB14     ; 211        ; 4        ; VD[26]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB15     ; 221        ; 4        ; VD[24]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB16     ; 225        ; 4        ; VD[23]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB17     ; 244        ; 4        ; DDR_CLK                                    ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 242        ; 4        ; nVCAS                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 253        ; 4        ; VA[9]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 260        ; 4        ; VA[8]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 4          ; 1        ; ACSI_D[0]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 3          ; 1        ; MIDI_TLR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 535        ; 8        ; LP_D[5]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 530        ; 8        ; nSRBHE                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 523        ; 8        ; SRD[0]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 502        ; 8        ; IO[4]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 500        ; 8        ; IO[2]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 498        ; 8        ; nSRCS                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 488        ; 8        ; SRD[8]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 486        ; 8        ; SRD[11]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 482        ; 8        ; nRSTO_MCF                                  ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B12      ; 480        ; 7        ; nDACK0                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B13      ; 474        ; 7        ; IO[17]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 470        ; 7        ; IO[15]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 459        ; 7        ; IO[10]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B16      ; 449        ; 7        ; SD_DATA0                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 447        ; 7        ; SD_DATA2                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 438        ; 7        ; RTS                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 434        ; 7        ; RI                                         ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 431        ; 7        ; nSDSEL                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B21      ; 404        ; 6        ; VB[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B22      ; 403        ; 6        ; VB[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C1       ; 15         ; 1        ; ACSI_D[4]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 14         ; 1        ; ACSI_D[3]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 538        ; 8        ; LP_D[2]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 539        ; 8        ; LP_D[1]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 526        ; 8        ; SRD[2]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 508        ; 8        ; IO[7]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 507        ; 8        ; IO[6]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 491        ; 8        ; SRD[4]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 460        ; 7        ; IO[11]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 450        ; 7        ; SD_CLK                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 433        ; 7        ; nDCHG                                      ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C18      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 428        ; 7        ; TRACK00                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 405        ; 6        ; VB[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C21      ; 401        ; 6        ; VB[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C22      ; 400        ; 6        ; VB[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D1       ; 17         ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; D2       ; 16         ; 1        ; ACSI_D[5]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 536        ; 8        ; LP_D[4]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ; 527        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D8       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 483        ; 8        ; SRD[12]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 461        ; 7        ; IO[12]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D14      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 439        ; 7        ; DTR                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 426        ; 7        ; nWR_GATE                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D18      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 429        ; 7        ; nWP                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 407        ; 6        ; VB[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D21      ; 395        ; 6        ; VG[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D22      ; 394        ; 6        ; VG[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E1       ; 22         ; 1        ; SCSI_D[1]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 21         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; E3       ; 9          ; 1        ; ACSI_D[2]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E5       ; 546        ; 8        ; LPDIR                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 545        ; 8        ; LP_STR                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 537        ; 8        ; LP_D[3]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 506        ; 8        ; IO[5]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 484        ; 8        ; SRD[6]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 477        ; 7        ; nDREQ1                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 476        ; 7        ; MIDI_IN                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E13      ; 468        ; 7        ; IO[13]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E14      ; 453        ; 7        ; SD_CMD_D1                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 440        ; 7        ; YM_QC                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 418        ; 7        ; nINDEX                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E17      ;            ;          ; VCCD_PLL2                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 388        ; 6        ; VG[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E22      ; 387        ; 6        ; VG[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F1       ; 26         ; 1        ; SCSI_D[3]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 25         ; 1        ; SCSI_D[2]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 542        ; 8        ; LP_D[0]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 531        ; 8        ; nSRWE                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 544        ; 8        ; SRD[5]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 525        ; 8        ; SRD[13]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 478        ; 7        ; nSROE                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F13      ; 457        ; 7        ; SD_CD_DATA3                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 423        ; 7        ; nSTEP                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 419        ; 7        ; DSA_D                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 417        ; 7        ; HD_DD                                      ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F17      ; 410        ; 6        ; nSYNC                                      ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F18      ;            ; --       ; VCCA2                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 397        ; 6        ; PIXEL_CLK_PAD                              ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F20      ; 396        ; 6        ; nIRQ[4]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F21      ; 376        ; 6        ; nIRQ[2]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F22      ; 375        ; 6        ; VR[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G1       ; 67         ; 1        ; GND+                                       ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 66         ; 1        ; MAIN_CLK                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G3       ; 1          ; 1        ; SCSI_D[5]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 0          ; 1        ; SCSI_D[4]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 5          ; 1        ; ACSI_D[1]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 543        ; 8        ; LP_BUSY                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 532        ; 8        ; LP_D[7]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 547        ; 8        ; SRD[14]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 524        ; 8        ; IO[8]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 492        ; 8        ; SRD[3]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; G13      ; 444        ; 7        ; YM_QB                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G14      ; 441        ; 7        ; nWR                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G15      ; 422        ; 7        ; nSTEP_DIR                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 420        ; 7        ; nMOT_ON                                    ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G17      ; 411        ; 6        ; nBLANK_PAD                                 ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G18      ; 398        ; 6        ; VB[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 345        ; 6        ; E0_INT                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 344        ; 6        ; IDE_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H1       ; 52         ; 1        ; nSCSI_C_D                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 51         ; 1        ; nSCSI_MSG                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 42         ; 1        ; MIDI_OLR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 19         ; 1        ; ACSI_D[7]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 18         ; 1        ; ACSI_D[6]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; H10      ; 512        ; 8        ; SRD[15]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 511        ; 8        ; SRD[7]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H14      ; 425        ; 7        ; CTS                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H15      ; 424        ; 7        ; RxD                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H16      ; 393        ; 6        ; VG[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H17      ; 399        ; 6        ; VB[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 391        ; 6        ; VG[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H19      ; 386        ; 6        ; VG[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 385        ; 6        ; nIRQ[3]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 365        ; 6        ; VR[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 364        ; 6        ; VR[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 55         ; 1        ; CLKUSB                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 54         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J3       ; 53         ; 1        ; nSCSI_I_O                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 50         ; 1        ; nACSI_INT                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J5       ; 38         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J6       ; 20         ; 1        ; SCSI_D[0]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 45         ; 1        ; SCSI_DIR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ; 30         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J16      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J17      ; 392        ; 6        ; VG[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 374        ; 6        ; VR[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J19      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
+; J21      ; 363        ; 6        ; VR[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 362        ; 6        ; VR[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 59         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT            ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K2       ; 58         ; 1        ; ~ALTERA_DCLK~ / RESERVED_INPUT             ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; K3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 60         ; 1        ; ^nCONFIG                                   ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 41         ; 1        ; ^nSTATUS                                   ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 46         ; 1        ; nACSI_DRQ                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K8       ; 44         ; 1        ; SCSI_D[7]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K17      ; 369        ; 6        ; VR[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 370        ; 6        ; VR[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 357        ; 6        ; VSYNC_PAD                                  ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K20      ; 350        ; 6        ; ^MSEL3                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 361        ; 6        ; HSYNC_PAD                                  ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 360        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
+; L1       ; 63         ; 1        ; #TMS                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 62         ; 1        ; #TCK                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 65         ; 1        ; ^nCE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 64         ; 1        ; #TDO                                       ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 61         ; 1        ; #TDI                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 70         ; 2        ; ACSI_DIR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L7       ; 79         ; 2        ; PIC_AMKB_RX                                ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L8       ; 43         ; 1        ; SCSI_D[6]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L16      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L17      ; 349        ; 6        ; ^MSEL2                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 348        ; 6        ; ^MSEL1                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 354        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L22      ; 353        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M1       ; 73         ; 2        ; nACSI_RESET                                ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M2       ; 72         ; 2        ; nACSI_CS                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M3       ; 75         ; 2        ; nSCSI_ATN                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M4       ; 74         ; 2        ; nACSI_ACK                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M5       ; 80         ; 2        ; IDE_RES                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M6       ; 71         ; 2        ; ACSI_A1                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M7       ; 105        ; 2        ; SCSI_PAR                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M8       ; 106        ; 2        ; nSCSI_SEL                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M16      ; 337        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 347        ; 6        ; ^MSEL0                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 346        ; 6        ; ^CONF_DONE                                 ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 336        ; 5        ; SD_WP                                      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M20      ; 335        ; 5        ; SD_CARD_DEDECT                             ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M21      ; 334        ; 5        ; VD[1]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M22      ; 333        ; 5        ; VD[0]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N1       ; 77         ; 2        ; AMKB_TX                                    ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N2       ; 76         ; 2        ; nSCSI_ACK                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 87         ; 2        ; nRP_LDS                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N6       ; 104        ; 2        ; nSCSI_RST                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N7       ; 122        ; 2        ; nIRQ[7]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N8       ; 107        ; 2        ; nSCSI_BUSY                                 ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N16      ; 314        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 329        ; 5        ; VD[12]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N18      ; 330        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 324        ; 5        ; LED_FPGA_OK                                ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N20      ; 323        ; 5        ; VD[15]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; N21      ; 332        ; 5        ; ~ALTERA_DEV_CLRn~ / RESERVED_INPUT         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; N22      ; 331        ; 5        ; ~ALTERA_DEV_OE~ / RESERVED_INPUT           ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
+; P1       ; 84         ; 2        ; nIDE_RD                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P2       ; 83         ; 2        ; nIDE_WR                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P3       ; 89         ; 2        ; nROM3                                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P4       ; 88         ; 2        ; nRP_UDS                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P5       ; 103        ; 2        ; nIRQ[5]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P6       ; 131        ; 2        ; nPCI_INTD                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P7       ; 123        ; 2        ; nIRQ[6]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P8       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P15      ; 298        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 299        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 302        ; 5        ; VD[10]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P18      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 317        ; 5        ; VD[13]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P21      ; 320        ; 5        ; VD[4]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P22      ; 319        ; 5        ; VD[2]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 86         ; 2        ; nIDE_CS1                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R2       ; 85         ; 2        ; nIDE_CS0                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 135        ; 2        ; TIN0                                       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R6       ; 136        ; 2        ; nFB_OE                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R7       ; 137        ; 2        ; FB_ALE                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R8       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; R9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; R11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; R13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R14      ; 268        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 269        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 267        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 301        ; 5        ; VD[5]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R18      ; 309        ; 5        ; VD[9]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R19      ; 310        ; 5        ; VD[6]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R20      ; 305        ; 5        ; VD[3]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R21      ; 316        ; 5        ; VD[11]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R22      ; 315        ; 5        ; VD[14]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T1       ; 69         ; 2        ; WP_CF_CARD                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T2       ; 68         ; 2        ; GND+                                       ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 121        ; 2        ; nFB_BURST                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T4       ; 134        ; 2        ; CLK25M                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T5       ; 133        ; 2        ; nFB_WR                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T6       ;            ; --       ; VCCA1                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 138        ; 2        ; nFB_TA                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T8       ; 166        ; 3        ; nFB_CS1                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T9       ; 167        ; 3        ; nFB_CS2                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 176        ; 3        ; FB_AD[20]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 177        ; 3        ; FB_AD[24]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T12      ; 226        ; 4        ; VD[16]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ; 227        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T14      ; 240        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 241        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 266        ; 4        ; VDQS[3]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 277        ; 5        ; VDM[3]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T18      ; 278        ; 5        ; nVCS                                       ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 343        ; 5        ; nMASTER                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T22      ; 342        ; 5        ; TOUT0                                      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U1       ; 92         ; 2        ; nSCSI_DRQ                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U2       ; 91         ; 2        ; nROM4                                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 145        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 146        ; 3        ; FB_SIZE0                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 170        ; 3        ; FB_AD[12]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 182        ; 3        ; FB_AD[21]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 191        ; 3        ; FB_AD[27]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U12      ; 222        ; 4        ; VD[31]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 233        ; 4        ; VD[20]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U14      ; 235        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 236        ; 4        ; VCKE                                       ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ; 262        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U17      ; 263        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U18      ;            ; --       ; VCCA4                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 291        ; 5        ; VA[11]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U20      ; 290        ; 5        ; VDM[2]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U21      ; 308        ; 5        ; VD[7]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; U22      ; 307        ; 5        ; VDQS[2]                                    ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; V1       ; 98         ; 2        ; nPD_VGA                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; V2       ; 97         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 130        ; 2        ; nPCI_INTC                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; V4       ; 129        ; 2        ; nPCI_INTB                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; V5       ; 142        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 141        ; 3        ; nFB_CS3                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 157        ; 3        ; FB_AD[5]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 171        ; 3        ; FB_AD[13]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V9       ; 178        ; 3        ; FB_AD[18]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V10      ; 179        ; 3        ; FB_AD[19]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V11      ; 199        ; 3        ; FB_AD[28]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V12      ; 213        ; 4        ; VD[30]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V13      ; 228        ; 4        ; VD[27]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V14      ; 234        ; 4        ; VD[19]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V15      ; 237        ; 4        ; VD[21]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 261        ; 4        ; VDM[1]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V17      ;            ;          ; VCCD_PLL4                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 304        ; 5        ; VA[10]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; V22      ; 303        ; 5        ; VD[8]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W1       ; 111        ; 2        ; nCF_CS1                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W2       ; 110        ; 2        ; nCF_CS0                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 156        ; 3        ; FB_AD[4]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W7       ; 168        ; 3        ; FB_AD[10]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W8       ; 172        ; 3        ; FB_AD[14]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W9       ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 200        ; 3        ; FB_AD[29]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W11      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 218        ; 4        ; VD[28]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W14      ; 229        ; 4        ; VD[22]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W15      ; 239        ; 4        ; VDQS[1]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 257        ; 4        ; nVRAS                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 285        ; 5        ; BA[0]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W20      ; 280        ; 5        ; VA[0]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W21      ; 293        ; 5        ; VA[2]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; W22      ; 292        ; 5        ; VA[1]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; Y1       ; 113        ; 2        ; IDE_RDY                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; Y2       ; 112        ; 2        ; AMKB_RX                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; Y3       ; 148        ; 3        ; FB_AD[0]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y4       ; 147        ; 3        ; FB_SIZE1                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y5       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 152        ; 3        ; FB_AD[1]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y7       ; 169        ; 3        ; FB_AD[11]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 175        ; 3        ; FB_AD[17]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 201        ; 3        ; FB_AD[30]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 219        ; 4        ; VD[17]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y14      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 258        ; 4        ; nVWE                                       ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 289        ; 5        ; VA[5]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; Y22      ; 288        ; 5        ; VA[3]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                                                                                                                                                                                                                                       ;
++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
+; Name                          ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1   ;
++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
+; SDC pin name                  ; inst|altpll_component|auto_generated|pll1                            ; inst13|altpll_component|auto_generated|pll1                            ; inst12|altpll_component|auto_generated|pll1                            ; inst22|altpll_component|auto_generated|pll1                              ;
+; PLL mode                      ; Source Synchronous                                                   ; Source Synchronous                                                     ; Source Synchronous                                                     ; Normal                                                                   ;
+; Compensate clock              ; clock0                                                               ; clock1                                                                 ; clock0                                                                 ; clock0                                                                   ;
+; Compensated input/output pins ; --                                                                   ; nRD_DATA                                                               ; MAIN_CLK                                                               ; --                                                                       ;
+; Switchover type               ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
+; Input frequency 0             ; 33.0 MHz                                                             ; 33.0 MHz                                                               ; 33.0 MHz                                                               ; 48.0 MHz                                                                 ;
+; Input frequency 1             ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
+; Nominal PFD frequency         ; 5.5 MHz                                                              ; 11.0 MHz                                                               ; 33.0 MHz                                                               ; 48.0 MHz                                                                 ;
+; Nominal VCO frequency         ; 368.5 MHz                                                            ; 1199.0 MHz                                                             ; 396.0 MHz                                                              ; 576.0 MHz                                                                ;
+; VCO post scale                ; 2                                                                    ; --                                                                     ; 2                                                                      ; 2                                                                        ;
+; VCO frequency control         ; Auto                                                                 ; Auto                                                                   ; Auto                                                                   ; Auto                                                                     ;
+; VCO phase shift step          ; 339 ps                                                               ; 104 ps                                                                 ; 315 ps                                                                 ; 217 ps                                                                   ;
+; VCO multiply                  ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
+; VCO divide                    ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
+; Freq min lock                 ; 32.4 MHz                                                             ; 16.8 MHz                                                               ; 25.0 MHz                                                               ; 25.0 MHz                                                                 ;
+; Freq max lock                 ; 58.23 MHz                                                            ; 35.79 MHz                                                              ; 54.18 MHz                                                              ; 54.18 MHz                                                                ;
+; M VCO Tap                     ; 0                                                                    ; 0                                                                      ; 0                                                                      ; 0                                                                        ;
+; M Initial                     ; 1                                                                    ; 1                                                                      ; 1                                                                      ; 1                                                                        ;
+; M value                       ; 67                                                                   ; 109                                                                    ; 12                                                                     ; 12                                                                       ;
+; N value                       ; 6                                                                    ; 3                                                                      ; 1                                                                      ; 1                                                                        ;
+; Charge pump current           ; setting 1                                                            ; setting 1                                                              ; setting 1                                                              ; setting 1                                                                ;
+; Loop filter resistance        ; setting 16                                                           ; setting 19                                                             ; setting 27                                                             ; setting 27                                                               ;
+; Loop filter capacitance       ; setting 0                                                            ; setting 0                                                              ; setting 0                                                              ; setting 0                                                                ;
+; Bandwidth                     ; 340 kHz to 540 kHz                                                   ; 450 kHz to 560 kHz                                                     ; 680 kHz to 980 kHz                                                     ; 680 kHz to 980 kHz                                                       ;
+; Real time reconfigurable      ; Off                                                                  ; Off                                                                    ; Off                                                                    ; On                                                                       ;
+; Scan chain MIF file           ; --                                                                   ; --                                                                     ; --                                                                     ; altpll4.mif                                                              ;
+; Preserve PLL counter order    ; Off                                                                  ; Off                                                                    ; Off                                                                    ; Off                                                                      ;
+; PLL location                  ; PLL_3                                                                ; PLL_4                                                                  ; PLL_1                                                                  ; PLL_2                                                                    ;
+; Inclk0 signal                 ; CLK33M                                                               ; CLK33M                                                                 ; MAIN_CLK                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ;
+; Inclk1 signal                 ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
+; Inclk0 signal type            ; Global Clock                                                         ; Dedicated Pin                                                          ; Dedicated Pin                                                          ; Global Clock                                                             ;
+; Inclk1 signal type            ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                              ;
++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div  ; Output Frequency ; Phase Shift    ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low   ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                       ;
++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]              ; clock0       ; 1    ; 66   ; 0.5 MHz          ; 0 (0 ps)       ; 0.67 (339 ps)    ; 50/50      ; C1      ; 67            ; 34/33 Odd    ; C0            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[0]   ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]              ; clock1       ; 67   ; 900  ; 2.46 MHz         ; 0 (0 ps)       ; 0.30 (339 ps)    ; 50/50      ; C2      ; 150           ; 75/75 Even   ; --            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[1]   ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]              ; clock2       ; 67   ; 90   ; 24.57 MHz        ; 0 (0 ps)       ; 3.00 (339 ps)    ; 50/50      ; C3      ; 15            ; 8/7 Odd      ; --            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[2]   ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~cascade_in   ; --           ; --   ; --   ; --               ; --             ; --               ; --         ; C0      ; 11            ; 5/6 Odd      ; --            ; 1       ; 0       ;                                                    ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]            ; clock0       ; 109  ; 1800 ; 2.0 MHz          ; 0 (0 ps)       ; 0.15 (104 ps)    ; 50/50      ; C1      ; 300           ; 150/150 Even ; C0            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[0] ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]            ; clock1       ; 109  ; 225  ; 15.99 MHz        ; 0 (0 ps)       ; 0.60 (104 ps)    ; 50/50      ; C2      ; 75            ; 38/37 Odd    ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[1] ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]            ; clock2       ; 109  ; 144  ; 24.98 MHz        ; 0 (0 ps)       ; 0.94 (104 ps)    ; 50/50      ; C3      ; 48            ; 24/24 Even   ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[2] ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]            ; clock3       ; 109  ; 75   ; 47.96 MHz        ; 0 (0 ps)       ; 1.80 (104 ps)    ; 50/50      ; C4      ; 25            ; 13/12 Odd    ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[3] ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~cascade_in ; --           ; --   ; --   ; --               ; --             ; --               ; --         ; C0      ; 2             ; 1/1 Even     ; --            ; 1       ; 0       ;                                                    ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]            ; clock0       ; 4    ; 1    ; 132.0 MHz        ; 240 (5051 ps)  ; 15.00 (315 ps)   ; 50/50      ; C0      ; 3             ; 2/1 Odd      ; --            ; 3       ; 0       ; inst12|altpll_component|auto_generated|pll1|clk[0] ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]            ; clock1       ; 4    ; 1    ; 132.0 MHz        ; 0 (0 ps)       ; 15.00 (315 ps)   ; 50/50      ; C3      ; 3             ; 2/1 Odd      ; --            ; 1       ; 0       ; inst12|altpll_component|auto_generated|pll1|clk[1] ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]            ; clock2       ; 4    ; 1    ; 132.0 MHz        ; 180 (3788 ps)  ; 15.00 (315 ps)   ; 50/50      ; C2      ; 3             ; 2/1 Odd      ; --            ; 2       ; 4       ; inst12|altpll_component|auto_generated|pll1|clk[2] ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]            ; clock3       ; 4    ; 1    ; 132.0 MHz        ; 105 (2210 ps)  ; 15.00 (315 ps)   ; 50/50      ; C4      ; 3             ; 2/1 Odd      ; --            ; 1       ; 7       ; inst12|altpll_component|auto_generated|pll1|clk[3] ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]            ; clock4       ; 2    ; 1    ; 66.0 MHz         ; 270 (11364 ps) ; 7.50 (315 ps)    ; 50/50      ; C1      ; 6             ; 3/3 Even     ; --            ; 5       ; 4       ; inst12|altpll_component|auto_generated|pll1|clk[4] ;
+; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]            ; clock0       ; 2    ; 1    ; 96.0 MHz         ; 0 (0 ps)       ; 7.50 (217 ps)    ; 50/50      ; C0      ; 6             ; 3/3 Even     ; --            ; 1       ; 0       ; inst22|altpll_component|auto_generated|pll1|clk[0] ;
++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO                                      ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard                     ; Load  ; Termination Resistance             ;
++----------------------------------+-------+------------------------------------+
+; 3.0-V LVTTL                      ; 0 pF  ; Not Available                      ;
+; 3.3-V LVTTL                      ; 0 pF  ; Not Available                      ;
+; 3.0-V LVCMOS                     ; 0 pF  ; Not Available                      ;
+; 3.3-V LVCMOS                     ; 0 pF  ; Not Available                      ;
+; 3.0-V PCI                        ; 10 pF ; Not Available                      ;
+; 3.0-V PCI-X                      ; 10 pF ; Not Available                      ;
+; 2.5 V                            ; 0 pF  ; Not Available                      ;
+; 1.8 V                            ; 0 pF  ; Not Available                      ;
+; 1.5 V                            ; 0 pF  ; Not Available                      ;
+; 1.2 V                            ; 0 pF  ; Not Available                      ;
+; SSTL-2 Class I                   ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; Differential 2.5-V SSTL Class I  ; 0 pF  ; (See SSTL-2)                       ;
+; SSTL-2 Class II                  ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; Differential 2.5-V SSTL Class II ; 0 pF  ; (See SSTL-2 Class II)              ;
+; SSTL-18 Class I                  ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; Differential 1.8-V SSTL Class I  ; 0 pF  ; (See 1.8-V SSTL Class I)           ;
+; SSTL-18 Class II                 ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; Differential 1.8-V SSTL Class II ; 0 pF  ; (See 1.8-V SSTL Class II)          ;
+; 1.8-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
+; Differential 1.8-V HSTL Class I  ; 0 pF  ; (See 1.8-V HSTL Class I)           ;
+; 1.8-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
+; Differential 1.8-V HSTL Class II ; 0 pF  ; (See 1.8-V HSTL Class II)          ;
+; 1.5-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
+; Differential 1.5-V HSTL Class I  ; 0 pF  ; (See 1.5-V HSTL Class I)           ;
+; 1.5-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
+; Differential 1.5-V HSTL Class II ; 0 pF  ; (See 1.5-V HSTL Class II)          ;
+; 1.2-V HSTL Class I               ; 0 pF  ; Not Available                      ;
+; Differential 1.2-V HSTL Class I  ; 0 pF  ; Not Available                      ;
+; 1.2-V HSTL Class II              ; 0 pF  ; Not Available                      ;
+; Differential 1.2-V HSTL Class II ; 0 pF  ; Not Available                      ;
+; Differential LVPECL              ; 0 pF  ; 100 Ohm (Differential)             ;
+; LVDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
+; LVDS_E_3R                        ; 0 pF  ; Not Available                      ;
+; RSDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
+; RSDS_E_1R                        ; 0 pF  ; Not Available                      ;
+; RSDS_E_3R                        ; 0 pF  ; Not Available                      ;
+; mini-LVDS                        ; 0 pF  ; 100 Ohm (Differential)             ;
+; mini-LVDS_E_3R                   ; 0 pF  ; Not Available                      ;
+; PPDS                             ; 0 pF  ; Not Available                      ;
+; PPDS_E_3R                        ; 0 pF  ; Not Available                      ;
+; Bus LVDS                         ; 0 pF  ; Not Available                      ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                                                  ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                                               ; Library Name ;
++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |firebee1                                                                   ; 9526 (10)   ; 4563 (0)                  ; 186 (186)     ; 109344      ; 23   ; 6            ; 0       ; 3         ; 295  ; 0            ; 4963 (10)    ; 1465 (0)          ; 3098 (0)         ; |firebee1                                                                                                                                                                                                         ; work         ;
+;    |DSP:Mathias_Alles|                                                      ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; |firebee1|DSP:Mathias_Alles                                                                                                                                                                                       ;              ;
+;    |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|          ; 4093 (640)  ; 1616 (114)                ; 0 (0)         ; 16384       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2414 (465)   ; 291 (10)          ; 1388 (177)       ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden                                                                                                                                           ;              ;
+;       |WF1772IP_TOP_SOC:I_FDC|                                              ; 976 (17)    ; 403 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 565 (9)      ; 33 (0)            ; 378 (15)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC                                                                                                                    ;              ;
+;          |WF1772IP_AM_DETECTOR:I_AM_DETECTOR|                               ; 40 (40)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (13)      ; 1 (1)             ; 26 (26)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR                                                                                 ;              ;
+;          |WF1772IP_CONTROL:I_CONTROL|                                       ; 545 (545)   ; 196 (196)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 344 (344)    ; 12 (12)           ; 189 (189)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL                                                                                         ;              ;
+;          |WF1772IP_CRC_LOGIC:I_CRC_LOGIC|                                   ; 51 (51)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 11 (11)           ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC                                                                                     ;              ;
+;          |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|                               ; 103 (103)   ; 37 (37)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 66 (66)      ; 0 (0)             ; 37 (37)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL                                                                                 ;              ;
+;          |WF1772IP_REGISTERS:I_REGISTERS|                                   ; 105 (105)   ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 57 (57)      ; 7 (7)             ; 41 (41)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS                                                                                     ;              ;
+;          |WF1772IP_TRANSCEIVER:I_TRANSCEIVER|                               ; 120 (120)   ; 79 (79)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 2 (2)             ; 77 (77)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER                                                                                 ;              ;
+;       |WF2149IP_TOP_SOC:I_SOUND|                                            ; 490 (36)    ; 197 (16)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 293 (20)     ; 37 (2)            ; 160 (18)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND                                                                                                                  ;              ;
+;          |WF2149IP_WAVE:I_PSG_WAVE|                                         ; 461 (461)   ; 181 (181)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 273 (273)    ; 35 (35)           ; 153 (153)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE                                                                                         ;              ;
+;       |WF5380_TOP_SOC:I_SCSI|                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI                                                                                                                     ;              ;
+;          |WF5380_CONTROL:I_CONTROL|                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL                                                                                            ;              ;
+;       |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|                                    ; 208 (1)     ; 97 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 106 (1)      ; 1 (0)             ; 101 (1)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD                                                                                                          ;              ;
+;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 21 (21)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 1 (1)             ; 10 (10)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                  ;              ;
+;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 101 (101)   ; 47 (47)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 54 (54)      ; 0 (0)             ; 47 (47)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                          ;              ;
+;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)     ; 39 (39)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 0 (0)             ; 46 (46)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                        ;              ;
+;       |WF6850IP_TOP_SOC:I_ACIA_MIDI|                                        ; 218 (2)     ; 97 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 116 (2)      ; 10 (0)            ; 92 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI                                                                                                              ;              ;
+;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 27 (27)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 6 (6)             ; 9 (9)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                      ;              ;
+;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 101 (101)   ; 47 (47)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 53 (53)      ; 3 (3)             ; 45 (45)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                              ;              ;
+;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 88 (88)     ; 39 (39)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 49 (49)      ; 1 (1)             ; 38 (38)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                            ;              ;
+;       |WF68901IP_TOP_SOC:I_MFP|                                             ; 1261 (110)  ; 460 (2)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 797 (107)    ; 70 (0)            ; 394 (71)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP                                                                                                                   ;              ;
+;          |WF68901IP_GPIO:I_GPIO|                                            ; 49 (49)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (23)      ; 9 (9)             ; 17 (17)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO                                                                                             ;              ;
+;          |WF68901IP_INTERRUPTS:I_INTERRUPTS|                                ; 290 (290)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 159 (159)    ; 5 (5)             ; 126 (126)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS                                                                                 ;              ;
+;          |WF68901IP_TIMERS:I_TIMERS|                                        ; 501 (501)   ; 166 (166)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 332 (332)    ; 44 (44)           ; 125 (125)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS                                                                                         ;              ;
+;          |WF68901IP_USART_TOP:I_USART|                                      ; 316 (3)     ; 140 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 176 (3)      ; 12 (0)            ; 128 (1)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART                                                                                       ;              ;
+;             |WF68901IP_USART_CTRL:I_USART_CTRL|                             ; 77 (77)     ; 49 (49)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (28)      ; 9 (9)             ; 40 (40)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL                                                     ;              ;
+;             |WF68901IP_USART_RX:I_USART_RECEIVE|                            ; 160 (160)   ; 56 (56)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 100 (100)    ; 2 (2)             ; 58 (58)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE                                                    ;              ;
+;             |WF68901IP_USART_TX:I_USART_TRANSMIT|                           ; 87 (87)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 45 (45)      ; 1 (1)             ; 41 (41)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT                                                   ;              ;
+;       |dcfifo0:RDF|                                                         ; 156 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 60 (0)            ; 66 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF                                                                                                                               ;              ;
+;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 156 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 60 (0)            ; 66 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
+;             |dcfifo_0hh1:auto_generated|                                    ; 156 (55)    ; 124 (42)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (4)       ; 60 (27)           ; 66 (13)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated                                                  ;              ;
+;                |a_gray2bin_lfb:wrptr_g_gray2bin|                            ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin                  ;              ;
+;                |a_gray2bin_lfb:ws_dgrp_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin                  ;              ;
+;                |a_graycounter_fic:wrptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 1 (1)             ; 13 (13)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p                      ;              ;
+;                |a_graycounter_k47:rdptr_g1p|                                ; 18 (18)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p                      ;              ;
+;                |alt_synch_pipe_ikd:rs_dgwp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 4 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp                       ;              ;
+;                   |dffpipe_hd9:dffpipe12|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;              ;
+;                |alt_synch_pipe_jkd:ws_dgrp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (0)            ; 1 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp                       ;              ;
+;                   |dffpipe_id9:dffpipe17|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (17)           ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;              ;
+;                |altsyncram_bi31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram                         ;              ;
+;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
+;                |cmpr_156:wrfull_eq_comp1_msb|                               ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb                     ;              ;
+;                |cntr_t2e:cntr_b|                                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
+;                |dffpipe_gd9:ws_brp|                                         ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp                               ;              ;
+;                |dffpipe_pe9:ws_bwp|                                         ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (10)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp                               ;              ;
+;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
+;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
+;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
+;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
+;       |dcfifo1:WRF|                                                         ; 166 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (0)       ; 70 (0)            ; 54 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF                                                                                                                               ;              ;
+;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 166 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (0)       ; 70 (0)            ; 54 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
+;             |dcfifo_3fh1:auto_generated|                                    ; 166 (58)    ; 124 (42)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (6)       ; 70 (34)           ; 54 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated                                                  ;              ;
+;                |a_gray2bin_lfb:rdptr_g_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin                  ;              ;
+;                |a_gray2bin_lfb:rs_dgwp_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin                  ;              ;
+;                |a_graycounter_gic:wrptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p                      ;              ;
+;                |a_graycounter_j47:rdptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p                      ;              ;
+;                |alt_synch_pipe_kkd:rs_dgwp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 3 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp                       ;              ;
+;                   |dffpipe_jd9:dffpipe12|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 3 (3)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;              ;
+;                |alt_synch_pipe_lkd:ws_dgrp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 2 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp                       ;              ;
+;                   |dffpipe_kd9:dffpipe15|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;              ;
+;                |altsyncram_ci31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram                         ;              ;
+;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
+;                |cntr_t2e:cntr_b|                                            ; 4 (4)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
+;                |dffpipe_gd9:rs_bwp|                                         ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 6 (6)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp                               ;              ;
+;                |dffpipe_pe9:rs_brp|                                         ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 9 (9)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp                               ;              ;
+;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
+;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 3 (3)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
+;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
+;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
+;    |Video:Fredi_Aschwanden|                                                 ; 4088 (14)   ; 2168 (4)                  ; 0 (0)         ; 92816       ; 20   ; 6            ; 0       ; 3         ; 0    ; 0            ; 1920 (10)    ; 916 (4)           ; 1252 (0)         ; |firebee1|Video:Fredi_Aschwanden                                                                                                                                                                                  ;              ;
+;       |DDR_CTR:DDR_CTR|                                                     ; 374 (342)   ; 158 (158)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 211 (180)    ; 20 (20)           ; 143 (140)        ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR                                                                                                                                                                  ;              ;
+;          |lpm_bustri_BYT:$00002|                                            ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002                                                                                                                                            ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
+;          |lpm_bustri_BYT:$00004|                                            ; 31 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 3 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004                                                                                                                                            ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 31 (31)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 3 (3)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
+;       |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|                         ; 1420 (1292) ; 529 (529)                 ; 0 (0)         ; 0           ; 0    ; 6            ; 0       ; 3         ; 0    ; 0            ; 891 (763)    ; 158 (158)         ; 371 (252)        ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR                                                                                                                                      ;              ;
+;          |lpm_bustri_WORD:$00000|                                           ; 187 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 112 (0)      ; 0 (0)             ; 75 (0)           ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000                                                                                                               ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 187 (187)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 112 (112)    ; 0 (0)             ; 75 (75)          ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component                                                                               ;              ;
+;          |lpm_bustri_WORD:$00002|                                           ; 60 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 44 (0)           ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002                                                                                                               ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 60 (60)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 44 (44)          ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component                                                                               ;              ;
+;          |lpm_mult:op_12|                                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12                                                                                                                       ;              ;
+;             |mult_aat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated                                                                                               ;              ;
+;          |lpm_mult:op_14|                                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14                                                                                                                       ;              ;
+;             |mult_cat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated                                                                                               ;              ;
+;          |lpm_mult:op_6|                                                    ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6                                                                                                                        ;              ;
+;             |mult_aat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated                                                                                                ;              ;
+;       |altddio_bidir0:inst1|                                                ; 96 (0)      ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1                                                                                                                                                             ;              ;
+;          |altddio_bidir:altddio_bidir_component|                            ; 96 (0)      ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component                                                                                                                       ;              ;
+;             |ddio_bidir_3jl:auto_generated|                                 ; 96 (96)     ; 96 (96)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (96)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated                                                                                         ;              ;
+;       |altddio_out0:inst2|                                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2                                                                                                                                                               ;              ;
+;          |altddio_out:altddio_out_component|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component                                                                                                                             ;              ;
+;             |ddio_out_are:auto_generated|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated                                                                                                 ;              ;
+;       |altddio_out2:inst5|                                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5                                                                                                                                                               ;              ;
+;          |altddio_out:altddio_out_component|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component                                                                                                                             ;              ;
+;             |ddio_out_o2f:auto_generated|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated                                                                                                 ;              ;
+;       |altdpram0:ST_CLUT_BLUE|                                              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE                                                                                                                                                           ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                           ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                            ;              ;
+;       |altdpram0:ST_CLUT_GREEN|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN                                                                                                                                                          ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                          ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                           ;              ;
+;       |altdpram0:ST_CLUT_RED|                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED                                                                                                                                                            ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                                                                                                            ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                             ;              ;
+;       |altdpram1:FALCON_CLUT_BLUE|                                          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE                                                                                                                                                       ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                       ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                        ;              ;
+;       |altdpram1:FALCON_CLUT_GREEN|                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN                                                                                                                                                      ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                      ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                       ;              ;
+;       |altdpram1:FALCON_CLUT_RED|                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED                                                                                                                                                        ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                                                                                                        ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                         ;              ;
+;       |altdpram2:ACP_CLUT_RAM54|                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54                                                                                                                                                         ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                                                                                                         ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
+;       |altdpram2:ACP_CLUT_RAM55|                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55                                                                                                                                                         ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                                                                                                         ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
+;       |altdpram2:ACP_CLUT_RAM|                                              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM                                                                                                                                                           ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                                                                                                           ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                            ;              ;
+;       |lpm_bustri_LONG:inst119|                                             ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_ff0:inst13|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 23 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 23 (23)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst14|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 31 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 31 (31)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst15|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 25 (0)            ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 25 (25)           ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst16|                                                      ; 28 (0)      ; 28 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (0)            ; 2 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 28 (28)     ; 28 (28)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (26)           ; 2 (2)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst17|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 31 (0)            ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 31 (31)           ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst18|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 30 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 30 (30)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst19|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst12|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (0)            ; 2 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (30)           ; 2 (2)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst20|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 28 (0)            ; 4 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 28 (28)           ; 4 (4)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst3|                                                       ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 32 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff1:inst4|                                                       ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (0)            ; 6 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (26)           ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff1:inst9|                                                       ; 24 (0)      ; 24 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 12 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 24 (24)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 12 (12)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff3:inst46|                                                      ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst47|                                                      ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst49|                                                      ; 9 (0)       ; 9 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst52|                                                      ; 9 (0)       ; 9 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff4:inst10|                                                      ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 4 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 4 (4)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff5:inst11|                                                      ; 8 (0)       ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff5:inst97|                                                      ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff6:inst71|                                                      ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 87 (0)            ; 41 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 87 (87)           ; 41 (41)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff6:inst94|                                                      ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 85 (0)            ; 43 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 85 (85)           ; 43 (43)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_fifoDZ:inst63|                                                   ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63                                                                                                                                                                ;              ;
+;          |scfifo:scfifo_component|                                          ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component                                                                                                                                        ;              ;
+;             |scfifo_lk21:auto_generated|                                    ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated                                                                                                             ;              ;
+;                |a_dpfifo_oq21:dpfifo|                                       ; 22 (9)      ; 21 (8)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 21 (8)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo                                                                                        ;              ;
+;                   |altsyncram_gj81:FIFOram|                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram                                                                ;              ;
+;                   |cntr_omb:rd_ptr_msb|                                     ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb                                                                    ;              ;
+;                   |cntr_pmb:wr_ptr|                                         ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr                                                                        ;              ;
+;       |lpm_fifo_dc0:inst|                                                   ; 118 (0)     ; 98 (0)                    ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 51 (0)            ; 47 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst                                                                                                                                                                ;              ;
+;          |dcfifo:dcfifo_component|                                          ; 118 (0)     ; 98 (0)                    ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 51 (0)            ; 47 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component                                                                                                                                        ;              ;
+;             |dcfifo_8fi1:auto_generated|                                    ; 118 (31)    ; 98 (20)                   ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (2)       ; 51 (16)           ; 47 (10)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                                                                             ;              ;
+;                |a_gray2bin_tgb:wrptr_g_gray2bin|                            ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 3 (3)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                                                                             ;              ;
+;                |a_gray2bin_tgb:ws_dgrp_gray2bin|                            ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                                                                             ;              ;
+;                |a_graycounter_njc:wrptr_gp|                                 ; 18 (18)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 13 (13)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp                                                                                  ;              ;
+;                |a_graycounter_s57:rdptr_g1p|                                ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p                                                                                 ;              ;
+;                |alt_synch_pipe_sld:ws_dgrp|                                 ; 30 (0)      ; 30 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp                                                                                  ;              ;
+;                   |dffpipe_re9:dffpipe22|                                   ; 30 (30)     ; 30 (30)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (30)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22                                                            ;              ;
+;                |altsyncram_tl31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram                                                                                    ;              ;
+;                |dffpipe_9d9:wraclr|                                         ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr                                                                                          ;              ;
+;                |dffpipe_oe9:ws_brp|                                         ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp                                                                                          ;              ;
+;                |dffpipe_oe9:ws_bwp|                                         ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp                                                                                          ;              ;
+;       |lpm_latch0:inst27|                                                   ; 32 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (0)       ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27                                                                                                                                                                ;              ;
+;          |lpm_latch:lpm_latch_component|                                    ; 32 (32)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 0 (0)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component                                                                                                                                  ;              ;
+;       |lpm_mux0:inst21|                                                     ; 120 (0)     ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (0)       ; 71 (0)            ; 27 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 120 (0)     ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (0)       ; 71 (0)            ; 27 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_gpe:auto_generated|                                        ; 120 (120)   ; 96 (96)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (22)      ; 71 (71)           ; 27 (27)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux1:inst24|                                                     ; 113 (0)     ; 81 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (0)       ; 33 (0)            ; 48 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 113 (0)     ; 81 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (0)       ; 33 (0)            ; 48 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_npe:auto_generated|                                        ; 113 (113)   ; 81 (81)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (32)      ; 33 (33)           ; 48 (48)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux2:inst25|                                                     ; 81 (0)      ; 41 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (0)       ; 1 (0)             ; 40 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 81 (0)      ; 41 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (0)       ; 1 (0)             ; 40 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_mpe:auto_generated|                                        ; 81 (81)     ; 41 (41)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (40)      ; 1 (1)             ; 40 (40)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux3:inst102|                                                    ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102                                                                                                                                                                 ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
+;             |mux_96e:auto_generated|                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated                                                                                                                ;              ;
+;       |lpm_mux4:inst81|                                                     ; 7 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 7 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_f6e:auto_generated|                                        ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux5:inst22|                                                     ; 64 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 60 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 64 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 60 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_58e:auto_generated|                                        ; 64 (64)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 60 (60)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux6:inst7|                                                      ; 91 (0)      ; 67 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (0)        ; 1 (0)             ; 82 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7                                                                                                                                                                   ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 91 (0)      ; 67 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (0)        ; 1 (0)             ; 82 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component                                                                                                                                         ;              ;
+;             |mux_kpe:auto_generated|                                        ; 91 (91)     ; 67 (67)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (8)        ; 1 (1)             ; 82 (82)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated                                                                                                                  ;              ;
+;       |lpm_muxDZ:inst62|                                                    ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (0)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62                                                                                                                                                                 ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (0)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
+;             |mux_dcf:auto_generated|                                        ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (128)        ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated                                                                                                                ;              ;
+;       |lpm_muxVDM:inst100|                                                  ; 736 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (0)      ; 0 (0)             ; 96 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100                                                                                                                                                               ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 736 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (0)      ; 0 (0)             ; 96 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component                                                                                                                                     ;              ;
+;             |mux_bbe:auto_generated|                                        ; 736 (736)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (640)    ; 0 (0)             ; 96 (96)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated                                                                                                              ;              ;
+;       |lpm_shiftreg0:sr0|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr1|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr2|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr3|                                                   ; 17 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 17 (17)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr4|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr5|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr6|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr7|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg4:inst26|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26                                                                                                                                                             ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
+;       |lpm_shiftreg6:inst92|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92                                                                                                                                                             ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
+;       |mux41:inst40|                                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40                                                                                                                                                                     ;              ;
+;       |mux41:inst41|                                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41                                                                                                                                                                     ;              ;
+;       |mux41:inst42|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42                                                                                                                                                                     ;              ;
+;       |mux41:inst43|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43                                                                                                                                                                     ;              ;
+;       |mux41:inst44|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44                                                                                                                                                                     ;              ;
+;       |mux41:inst45|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45                                                                                                                                                                     ;              ;
+;    |altddio_out3:inst5|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst6|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst8|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst9|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9                                                                                                                                                                                      ; work         ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component                                                                                                                                                    ; work         ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ; work         ;
+;    |altpll1:inst|                                                           ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst                                                                                                                                                                                            ;              ;
+;       |altpll:altpll_component|                                             ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst|altpll:altpll_component                                                                                                                                                                    ;              ;
+;          |altpll_pul2:auto_generated|                                       ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated                                                                                                                                         ;              ;
+;    |altpll2:inst12|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_isv2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated                                                                                                                                       ;              ;
+;    |altpll3:inst13|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_41p2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated                                                                                                                                       ;              ;
+;    |altpll4:inst22|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_c6j2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated                                                                                                                                       ;              ;
+;    |altpll_reconfig1:inst7|                                                 ; 334 (0)     ; 128 (0)                   ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 206 (0)      ; 22 (0)            ; 106 (0)          ; |firebee1|altpll_reconfig1:inst7                                                                                                                                                                                  ;              ;
+;       |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 334 (237)   ; 128 (80)                  ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 206 (157)    ; 22 (22)           ; 106 (57)         ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component                                                                                                              ;              ;
+;          |altsyncram:altsyncram4|                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4                                                                                       ;              ;
+;             |altsyncram_46r:auto_generated|                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated                                                         ;              ;
+;          |lpm_compare:cmpr7|                                                ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7                                                                                            ;              ;
+;             |cmpr_tnd:auto_generated|                                       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr12|                                               ; 10 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12                                                                                           ;              ;
+;             |cntr_30l:auto_generated|                                       ; 10 (10)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr13|                                               ; 7 (0)       ; 6 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 6 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13                                                                                           ;              ;
+;             |cntr_qij:auto_generated|                                       ; 7 (7)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 6 (6)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr14|                                               ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14                                                                                           ;              ;
+;             |cntr_pij:auto_generated|                                       ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr15|                                               ; 18 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15                                                                                           ;              ;
+;             |cntr_30l:auto_generated|                                       ; 18 (18)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr1|                                                ; 41 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1                                                                                            ;              ;
+;             |cntr_30l:auto_generated|                                       ; 41 (41)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (33)      ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr2|                                                ; 9 (0)       ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2                                                                                            ;              ;
+;             |cntr_9cj:auto_generated|                                       ; 9 (9)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr3|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3                                                                                            ;              ;
+;             |cntr_pij:auto_generated|                                       ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated                                                                    ;              ;
+;    |interrupt_handler:nobody|                                               ; 1037 (999)  ; 633 (633)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 401 (363)    ; 235 (235)         ; 401 (355)        ; |firebee1|interrupt_handler:nobody                                                                                                                                                                                ;              ;
+;       |lpm_bustri_BYT:$00000|                                               ; 14 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 9 (0)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 9 (9)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00002|                                               ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 8 (8)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00004|                                               ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 0 (0)             ; 14 (0)           ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 14 (14)          ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00006|                                               ; 22 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (0)        ; 0 (0)             ; 15 (0)           ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 22 (22)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 15 (15)          ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;    |lpm_counter0:inst18|                                                    ; 19 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 1 (0)             ; 17 (0)           ; |firebee1|lpm_counter0:inst18                                                                                                                                                                                     ;              ;
+;       |lpm_counter:lpm_counter_component|                                   ; 19 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 1 (0)             ; 17 (0)           ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component                                                                                                                                                   ;              ;
+;          |cntr_mph:auto_generated|                                          ; 19 (19)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 17 (17)          ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated                                                                                                                           ;              ;
+;    |lpm_ff0:inst1|                                                          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|lpm_ff0:inst1                                                                                                                                                                                           ;              ;
+;       |lpm_ff:lpm_ff_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component                                                                                                                                                                   ;              ;
++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                                     ;
++----------------+----------+---------------+---------------+-----------------------+----------+----------+
+; Name           ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO      ; TCOE     ;
++----------------+----------+---------------+---------------+-----------------------+----------+----------+
+; CLK24M576      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; LP_STR         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nFB_BURST      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nACSI_DRQ      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nACSI_INT      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_DRQ      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_MSG      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nDCHG          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_DATA0       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_DATA1       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_DATA2       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_CARD_DEDECT ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_WP          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nDACK0         ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; WP_CF_CARD     ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_C_D      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_I_O      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nFB_CS3        ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; CLK25M         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nACSI_ACK      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nACSI_RESET    ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nACSI_CS       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_DIR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_A1        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_ACK      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_ATN      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_DIR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; MIDI_OLR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; MIDI_TLR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; TxD            ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; RTS            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; DTR            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; AMKB_TX        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; IDE_RES        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIDE_CS0       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIDE_CS1       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIDE_WR        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIDE_RD        ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nCF_CS0        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nCF_CS1        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nROM3          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nROM4          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nRP_UDS        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nRP_LDS        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSDSEL         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nWR_GATE       ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nWR            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; YM_QA          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; YM_QB          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; YM_QC          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; SD_CLK         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; DSA_D          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nVWE           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nVCAS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nVRAS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nVCS           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nPD_VGA        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; TIN0           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSRCS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSRBLE         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSRBHE         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSRWE          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nDREQ1         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; LED_FPGA_OK    ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nSROE          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VCKE           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nFB_TA         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nDDR_CLK       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; DDR_CLK        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VSYNC_PAD      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; HSYNC_PAD      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nBLANK_PAD     ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; PIXEL_CLK_PAD  ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nSYNC          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nMOT_ON        ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nSTEP_DIR      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nSTEP          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; CLKUSB         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; LPDIR          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; BA[1]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; BA[0]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[7]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[6]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[5]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[4]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[3]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; nIRQ[2]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[12]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[11]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[10]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[9]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[8]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[7]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[6]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[5]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[4]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[3]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[2]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[1]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VA[0]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
+; VB[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VB[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VDM[3]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VDM[2]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VDM[1]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VDM[0]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VG[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; VR[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; TOUT0          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; nMASTER        ; Input    ; --            ; --            ; --                    ; --       ; --       ;
+; FB_AD[31]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[30]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[29]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[28]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[27]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[26]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[25]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[24]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[23]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[22]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[21]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[20]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[19]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[18]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[17]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[16]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[15]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[14]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[13]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[12]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[11]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[10]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[9]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[8]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[7]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[6]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[5]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[4]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[3]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[2]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[1]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; FB_AD[0]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
+; VD[31]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[30]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[29]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[28]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[27]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[26]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[25]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[24]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[23]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[22]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[21]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[20]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[19]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[18]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[17]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[16]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[15]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[14]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[13]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[12]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[11]         ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[10]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[9]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[8]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[7]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[6]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[5]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[4]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; VD[3]          ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[2]          ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
+; VD[1]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VD[0]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; VDQS[3]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
+; VDQS[2]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
+; VDQS[1]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
+; VDQS[0]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
+; IO[17]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[16]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[15]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[14]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[13]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[12]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[11]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[10]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[9]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[8]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[7]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[6]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[5]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[4]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[3]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[2]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[1]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; IO[0]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SRD[15]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[14]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[13]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[12]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[11]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[10]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[9]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[8]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[7]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[6]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[5]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[4]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[3]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[2]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SRD[1]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; SRD[0]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; SCSI_PAR       ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_SEL      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; nSCSI_BUSY     ; Bidir    ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
+; nSCSI_RST      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_CD_DATA3    ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SD_CMD_D1      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[7]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[6]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[5]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[4]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; ACSI_D[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; LP_D[7]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; LP_D[6]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; LP_D[5]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; LP_D[4]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; LP_D[3]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; LP_D[2]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
+; LP_D[1]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; LP_D[0]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
+; SCSI_D[7]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[6]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[5]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[4]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; SCSI_D[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
+; nRSTO_MCF      ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; nFB_WR         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nFB_CS1        ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; FB_SIZE1       ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; FB_SIZE0       ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; FB_ALE         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nFB_CS2        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; MAIN_CLK       ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; nDACK1         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; nFB_OE         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; IDE_RDY        ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; CLK33M         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; HD_DD          ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nINDEX         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; RxD            ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; nWP            ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; LP_BUSY        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; DCD            ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; CTS            ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; TRACK00        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; IDE_INT        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; RI             ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nPCI_INTD      ; Input    ; (6) 2223 ps   ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nPCI_INTC      ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
+; nPCI_INTB      ; Input    ; (6) 2223 ps   ; (0) 0 ps      ; --                    ; --       ; --       ;
+; nPCI_INTA      ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
+; DVI_INT        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; E0_INT         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
+; PIC_INT        ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
+; PIC_AMKB_RX    ; Input    ; (1) 663 ps    ; --            ; --                    ; --       ; --       ;
+; MIDI_IN        ; Input    ; --            ; (1) 634 ps    ; --                    ; --       ; --       ;
+; nRD_DATA       ; Input    ; --            ; --            ; (0) 0 ps              ; --       ; --       ;
+; AMKB_RX        ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
++----------------+----------+---------------+---------------+-----------------------+----------+----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                                                                                  ; Pad To Core Index ; Setting ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; nFB_BURST                                                                                                                                                                                            ;                   ;         ;
+; nACSI_DRQ                                                                                                                                                                                            ;                   ;         ;
+; nACSI_INT                                                                                                                                                                                            ;                   ;         ;
+; nSCSI_DRQ                                                                                                                                                                                            ;                   ;         ;
+; nSCSI_MSG                                                                                                                                                                                            ;                   ;         ;
+; nDCHG                                                                                                                                                                                                ;                   ;         ;
+; SD_DATA0                                                                                                                                                                                             ;                   ;         ;
+; SD_DATA1                                                                                                                                                                                             ;                   ;         ;
+; SD_DATA2                                                                                                                                                                                             ;                   ;         ;
+; SD_CARD_DEDECT                                                                                                                                                                                       ;                   ;         ;
+; SD_WP                                                                                                                                                                                                ;                   ;         ;
+; nDACK0                                                                                                                                                                                               ;                   ;         ;
+; WP_CF_CARD                                                                                                                                                                                           ;                   ;         ;
+; nSCSI_C_D                                                                                                                                                                                            ;                   ;         ;
+; nSCSI_I_O                                                                                                                                                                                            ;                   ;         ;
+; nFB_CS3                                                                                                                                                                                              ;                   ;         ;
+; TOUT0                                                                                                                                                                                                ;                   ;         ;
+; nMASTER                                                                                                                                                                                              ;                   ;         ;
+; FB_AD[31]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[15]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~32                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[31]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[7]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[15]                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~1                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28                                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[31]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~feeder                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[30]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[14]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[30]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[6]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[30]~0                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[14]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[6]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[14]                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[30]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[30]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[14]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[30]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[30]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~7                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28                                                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1feeder                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[14]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[30]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[6]~feeder                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[6]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[29]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[13]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                                            ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[29]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[29]~2                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[5]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[13]                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[29]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[13]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[29]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~6                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]~feeder                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[29]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[13]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[29]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[28]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[12]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[28]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[4]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[28]~3                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~4                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[12]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[4]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[12]                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[28]                                                                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[28]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[28]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[28]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[12]                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[28]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]~feeder                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[4]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[12]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[28]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[28]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[27]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[11]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[3]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[3]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[3]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[27]~4                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~5                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[3]                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[3]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[11]                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[11]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[27]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[27]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[11]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]~feeder                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]~feeder                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[27]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~feeder                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[11]~feeder                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[26]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
+;      - SRD[10]~output                                                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[2]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[2]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                                            ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[26]                                                                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[12]~53                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[26]~5                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~3                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[2]                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[26]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[26]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[2]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[10]                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[26]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[26]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]~feeder                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[10]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]~feeder                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[2]~feeder                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~feeder                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
+; FB_AD[25]                                                                                                                                                                                            ;                   ;         ;
+;      - SRD[9]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[1]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[1]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[1]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[11]~55                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[1]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[9]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[1]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[25]~6                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~2                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[1]                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[1]                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[25]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[25]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[9]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[25]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[9]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[9]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]~feeder                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[25]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[9]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[9]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
+; FB_AD[24]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]~22                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - SRD[8]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[0]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[0]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[0]                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[10]~58                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[0]                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0]                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[24]~7                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~0                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[0]                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[24]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[24]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[24]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[8]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0]                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                        ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]~29                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]~feeder                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]~feeder                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[8]~feeder                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[24]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~feeder                                                                                                               ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]~feeder                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[24]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[8]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[8]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[24]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[24]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]~feeder                                                                                                                 ; 1                 ; 0       ;
+; FB_AD[23]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]~20                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[7]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[7]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[7]~0                                                            ; 1                 ; 0       ;
+;      - SRD[7]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[7]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[7]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[9]~60                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~4                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[7]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~10                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[23]~8                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~1                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~1                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[7]                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]                                                                                                                 ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[23]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[23]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][10]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][20]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][21]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][23]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][26]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][34]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][35]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][37]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][42]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][46]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][45]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][50]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][54]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][58]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][57]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][61]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[7]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[7]                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[7]                                                                            ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][0]~73                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][2]~74                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][4]~75                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~10                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[7]                                                                       ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]~5                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[7]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[7]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~24                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~24                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[7]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~feeder                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][19]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[23]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]~feeder                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[7]~feeder                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[22]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]~18                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[6]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[6]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[6]~0                                                             ; 1                 ; 0       ;
+;      - SRD[6]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[6]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[6]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[8]~62                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~2                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[6]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~8                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]~9                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[6]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~2                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~2                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[6]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[22]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[6]                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[22]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[22]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][7]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][11]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][17]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][21]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][23]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][25]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][33]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][38]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][41]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][46]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][47]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][50]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][53]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][55]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][58]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][57]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][61]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][62]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[6]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[6]                                                                           ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][0]~78                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][2]~79                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][4]~80                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[6]~12                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[6]                                                                       ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]~9                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[6]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~30                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~30                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[6]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][63]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][32]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][56]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[6][18]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]~feeder                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[6]~feeder                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[6]~feeder                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[6]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[22]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]~feeder                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[6]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[5]~feeder                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[6]~feeder                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[6]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[6]~feeder                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[21]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]~16                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[5]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[5]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[5]~1                                                             ; 1                 ; 0       ;
+;      - SRD[5]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[5]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[7]~64                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[5]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[5]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~6                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~14                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]~10                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[5]                                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[5]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~3                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~3                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[5]                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[21]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5]                                                                                                                 ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[21]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[21]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[21]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][17]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][40]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][43]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][35]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][47]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][7]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][15]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][58]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][55]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][51]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][60]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[5]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[5]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[5]                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[5]                                                                            ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][2]~82                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][4]~83                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][0]~85                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[5]~15                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[5]                                                                       ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]~12                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[5]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~36                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~36                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[5]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[5]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[5]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[5]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]~feeder                                                                            ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][9]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[5]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[5]~feeder                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5]~feeder                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]~feeder                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]~feeder                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[5]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[5][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[20]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]~14                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[4]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[4]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]~2                                                             ; 1                 ; 0       ;
+;      - SRD[4]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[4]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[6]~66                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[4]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[4]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[4]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[4]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~8                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~12                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]~11                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[4]                                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[4]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~4                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~4                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[4]                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[20]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4]                                                                                                                 ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[20]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[20]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[20]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][40]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][43]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][35]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][47]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][17]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][7]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][15]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][55]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][51]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][60]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[4]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[4]                                                                           ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][2]~86                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][4]~87                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][0]~89                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[4]~18                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[4]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[4]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~42                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[4]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~42                                                                    ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12]                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]~27                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[4]                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[4]~feeder                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[4]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4]~feeder                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[4]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[3]~feeder                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[20]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[4]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[20]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[4]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[4]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]~feeder                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[4][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[4]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[19]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]~12                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[3]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[3]~3                                                             ; 1                 ; 0       ;
+;      - SRD[3]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[3]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[5]~68                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[3]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[3]                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~10                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[3]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~16                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]~12                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[3]                                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[3]                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~7                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~5                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[3]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[3]                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[3]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[3]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3]                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[3]                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[19]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[19]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][17]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][40]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][43]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][35]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][47]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][10]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][8]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][7]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][15]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][55]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][51]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][60]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[3]                                                                                                                     ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[3]~21                                 ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][2]~90                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][4]~91                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][0]~93                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[3]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~47                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[3]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~47                                                                    ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]~24                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3]                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]~feeder                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[3]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[19]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[3]~feeder                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[19]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[3]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][9]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[3][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[3]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[3]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[3]~feeder                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[3]~feeder                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[18]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]~10                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[2]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[2]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[2]~4                                                             ; 1                 ; 0       ;
+;      - SRD[2]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~4                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[2]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[2]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[4]~70                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[2]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[18]                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~4                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[2]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~12                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]~13                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[2]                                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[2]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[2]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[18]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[18]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][21]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][24]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][26]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][27]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][33]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][35]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][37]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][39]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][41]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][46]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][50]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][49]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][51]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][54]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][57]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][59]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][61]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[2]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[2]                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[2]                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[2]                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~8                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~6                                                                ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][0]~69                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][2]~70                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][4]~71                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[2]~9                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[2]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[2]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~18                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[2]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~18                                                                    ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]~21                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[2]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[2]~feeder                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][6]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][36]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][52]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[2][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[2]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]~feeder                                                        ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]~feeder                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]~feeder                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]~feeder                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[2]~feeder                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[17]                                                                                                                                                                                            ;                   ;         ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[1]~5                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[1]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[1]                                                                    ; 1                 ; 0       ;
+;      - SRD[1]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~0                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[1]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[1]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[3]~72                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[1]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[1]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~2                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~14                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]~14                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[1]                                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[1]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[17]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[17]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[1]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[1]                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[17]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[17]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[17]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][15]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][19]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][21]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][23]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][26]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][27]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][29]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][31]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][34]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][37]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][40]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][42]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][43]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][46]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][47]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][49]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][51]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][53]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][55]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][58]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][60]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][61]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][62]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[1]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[1]                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~6                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~7                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][0]~65                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][2]~66                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][4]~67                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[1]~6                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[1]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~12                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[1]                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~12                                                                    ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]~18                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[1]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[1]~feeder                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][59]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][48]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[1]~feeder                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[1]~feeder                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[1]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[1]~feeder                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[1]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][56]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][63]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][44]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][52]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][32]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][39]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[1][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[17]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[1]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[17]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]~feeder                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]~feeder                                                                                                           ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]~feeder                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]~feeder                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[16]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[0]~6                                                             ; 1                 ; 0       ;
+;      - SRD[0]~output                                                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VWE                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[16]                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[2]~74                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~6                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~16                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[0]                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[0]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[0]                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[16]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[0]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][10]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][16]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][18]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][20]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][22]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][24]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][26]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][27]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][28]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][30]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][32]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][34]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][36]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][38]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][40]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][42]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][44]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][46]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][48]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][50]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][52]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][54]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][56]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][58]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][60]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][61]                                                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][63]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[0]                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[0]                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0]                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[0]                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~5                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~8                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]~2                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][0]~0                                                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][2]~3                                                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][4]~6                                                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][13]~12                                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~6                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~6                                                                     ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~15                                                                                   ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8]                                                                                    ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][59]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][29]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[16]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][31]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][39]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~feeder                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[16]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]~feeder                                                                                                          ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]~feeder                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][19]~feeder                                                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~feeder                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~feeder                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~feeder                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[0]~feeder                                                                                                          ; 1                 ; 0       ;
+; FB_AD[15]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[1]~76                                                                                                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[15]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[15]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[15]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[14]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[0]~78                                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]~0                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[14]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[14]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[14]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[14]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[13]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[1]~9                                                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~5                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[13]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[13]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[13]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[13]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[13]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[13]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[13]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[13]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[12]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[0]~11                                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]~1                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[12]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[12]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[12]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[12]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[12]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[12]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[12]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[11]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]~2                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[11]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[11]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[11]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[11]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[11]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[11]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[11]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[11]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[10]                                                                                                                                                                                            ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~4                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[10]                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10]                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[10]                                                                                                                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[10]                                                                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]~feeder                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]~feeder                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[10]~feeder                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]~feeder                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[9]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]~8                                                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[9]~0                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[9]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[9]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[9]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[9]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[9]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+; FB_AD[8]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]~13                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]~23                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[8]~1                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[8]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[8]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[8]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[8]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[8]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+; FB_AD[7]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~16                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]~24                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[7]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[7]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[7]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[6]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]~23                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[6]~25                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[6]~2                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[6]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[6]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[6]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[6]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[6]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[5]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]~26                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[5]~26                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[5]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[5]~3                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[5]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[5]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[5]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[5]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[5]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[4]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]~29                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[4]~27                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[4]~4                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[4]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[4]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4]                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[4]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[4]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[4]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[3]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]~32                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[3]~28                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[3]~5                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[3]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[3]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[3]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[2]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]~35                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[2]~29                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[2]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[2]~6                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[2]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[2]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[2]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[2]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[1]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]~41                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]~30                                                                                                               ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[1]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[1]~7                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[1]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[1]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[1]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[1]                                                                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[1]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]~feeder                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+; FB_AD[0]                                                                                                                                                                                             ;                   ;         ;
+;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]~43                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[0]~31                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[0]~8                                                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[0]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0]                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[0]                                                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~5                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                         ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[0]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[0]~feeder                                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]~feeder                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]~feeder                                                                                                                  ; 1                 ; 0       ;
+; VD[31]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]~feeder                                                       ; 0                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]~feeder                                                       ; 0                 ; 1       ;
+; VD[30]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]~feeder                                                       ; 1                 ; 1       ;
+; VD[29]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]~feeder                                                       ; 1                 ; 1       ;
+; VD[28]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]~feeder                                                       ; 1                 ; 1       ;
+; VD[27]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]~feeder                                                       ; 1                 ; 1       ;
+; VD[26]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]~feeder                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]~feeder                                                       ; 1                 ; 0       ;
+; VD[25]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]~feeder                                                       ; 0                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]~feeder                                                       ; 0                 ; 1       ;
+; VD[24]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]~feeder                                                       ; 1                 ; 1       ;
+; VD[23]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]~feeder                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]~feeder                                                       ; 0                 ; 0       ;
+; VD[22]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]~feeder                                                       ; 1                 ; 1       ;
+; VD[21]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]~feeder                                                       ; 1                 ; 1       ;
+; VD[20]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]~feeder                                                       ; 1                 ; 1       ;
+; VD[19]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]~feeder                                                       ; 0                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]~feeder                                                       ; 0                 ; 1       ;
+; VD[18]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]~feeder                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]~feeder                                                       ; 0                 ; 0       ;
+; VD[17]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]~feeder                                                       ; 1                 ; 1       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]~feeder                                                       ; 1                 ; 1       ;
+; VD[16]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]~feeder                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]~feeder                                                       ; 0                 ; 0       ;
+; VD[15]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]~feeder                                                       ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]~feeder                                                       ; 0                 ; 2       ;
+; VD[14]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]~feeder                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]~feeder                                                       ; 1                 ; 0       ;
+; VD[13]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]~feeder                                                       ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]~feeder                                                       ; 0                 ; 2       ;
+; VD[12]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]~feeder                                                       ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]~feeder                                                       ; 0                 ; 2       ;
+; VD[11]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]~feeder                                                       ; 1                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]~feeder                                                       ; 1                 ; 2       ;
+; VD[10]                                                                                                                                                                                               ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]~feeder                                                       ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]~feeder                                                       ; 0                 ; 2       ;
+; VD[9]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]~feeder                                                        ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]~feeder                                                        ; 0                 ; 2       ;
+; VD[8]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]~feeder                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]~feeder                                                        ; 0                 ; 0       ;
+; VD[7]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]~feeder                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]~feeder                                                        ; 0                 ; 0       ;
+; VD[6]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]~feeder                                                        ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]~feeder                                                        ; 0                 ; 2       ;
+; VD[5]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]~feeder                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]~feeder                                                        ; 0                 ; 0       ;
+; VD[4]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]~feeder                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]~feeder                                                        ; 0                 ; 0       ;
+; VD[3]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]~feeder                                                        ; 1                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]~feeder                                                        ; 1                 ; 2       ;
+; VD[2]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]~feeder                                                        ; 1                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]~feeder                                                        ; 1                 ; 2       ;
+; VD[1]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]~feeder                                                        ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]~feeder                                                        ; 0                 ; 2       ;
+; VD[0]                                                                                                                                                                                                ;                   ;         ;
+;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]~feeder                                                        ; 0                 ; 2       ;
+;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]~feeder                                                        ; 0                 ; 2       ;
+; VDQS[3]                                                                                                                                                                                              ;                   ;         ;
+; VDQS[2]                                                                                                                                                                                              ;                   ;         ;
+; VDQS[1]                                                                                                                                                                                              ;                   ;         ;
+; VDQS[0]                                                                                                                                                                                              ;                   ;         ;
+; IO[17]                                                                                                                                                                                               ;                   ;         ;
+; IO[16]                                                                                                                                                                                               ;                   ;         ;
+; IO[15]                                                                                                                                                                                               ;                   ;         ;
+; IO[14]                                                                                                                                                                                               ;                   ;         ;
+; IO[13]                                                                                                                                                                                               ;                   ;         ;
+; IO[12]                                                                                                                                                                                               ;                   ;         ;
+; IO[11]                                                                                                                                                                                               ;                   ;         ;
+; IO[10]                                                                                                                                                                                               ;                   ;         ;
+; IO[9]                                                                                                                                                                                                ;                   ;         ;
+; IO[8]                                                                                                                                                                                                ;                   ;         ;
+; IO[7]                                                                                                                                                                                                ;                   ;         ;
+; IO[6]                                                                                                                                                                                                ;                   ;         ;
+; IO[5]                                                                                                                                                                                                ;                   ;         ;
+; IO[4]                                                                                                                                                                                                ;                   ;         ;
+; IO[3]                                                                                                                                                                                                ;                   ;         ;
+; IO[2]                                                                                                                                                                                                ;                   ;         ;
+; IO[1]                                                                                                                                                                                                ;                   ;         ;
+; IO[0]                                                                                                                                                                                                ;                   ;         ;
+; SRD[15]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~156                                                                                                                   ; 1                 ; 0       ;
+; SRD[14]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~131                                                                                                                   ; 1                 ; 0       ;
+; SRD[13]                                                                                                                                                                                              ;                   ;         ;
+;      - DSP:Mathias_Alles|FB_AD[29]~3                                                                                                                                                                 ; 0                 ; 0       ;
+; SRD[12]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369                                                                                                                   ; 0                 ; 0       ;
+; SRD[11]                                                                                                                                                                                              ;                   ;         ;
+;      - DSP:Mathias_Alles|FB_AD[27]~4                                                                                                                                                                 ; 0                 ; 0       ;
+; SRD[10]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~197                                                                                                                   ; 1                 ; 0       ;
+; SRD[9]                                                                                                                                                                                               ;                   ;         ;
+;      - DSP:Mathias_Alles|FB_AD[25]~0                                                                                                                                                                 ; 1                 ; 0       ;
+; SRD[8]                                                                                                                                                                                               ;                   ;         ;
+;      - DSP:Mathias_Alles|FB_AD[24]~1                                                                                                                                                                 ; 1                 ; 0       ;
+; SRD[7]                                                                                                                                                                                               ;                   ;         ;
+;      - DSP:Mathias_Alles|FB_AD[23]~2                                                                                                                                                                 ; 0                 ; 0       ;
+; SRD[6]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~269                                                                                                                   ; 1                 ; 0       ;
+; SRD[5]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~285                                                                                                                   ; 0                 ; 0       ;
+; SRD[4]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~301                                                                                                                   ; 1                 ; 0       ;
+; SRD[3]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~319                                                                                                                   ; 1                 ; 0       ;
+; SRD[2]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~172                                                                                                                   ; 0                 ; 0       ;
+; SRD[1]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~86                                                                                                                    ; 1                 ; 0       ;
+; SRD[0]                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54                                                                                                                    ; 0                 ; 0       ;
+; SCSI_PAR                                                                                                                                                                                             ;                   ;         ;
+; nSCSI_SEL                                                                                                                                                                                            ;                   ;         ;
+; nSCSI_BUSY                                                                                                                                                                                           ;                   ;         ;
+; nSCSI_RST                                                                                                                                                                                            ;                   ;         ;
+; SD_CD_DATA3                                                                                                                                                                                          ;                   ;         ;
+; SD_CMD_D1                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[7]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[6]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[5]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[4]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[3]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[2]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[1]                                                                                                                                                                                            ;                   ;         ;
+; ACSI_D[0]                                                                                                                                                                                            ;                   ;         ;
+; LP_D[7]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~142                                                                                                                   ; 1                 ; 0       ;
+; LP_D[6]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~112                                                                                                                   ; 0                 ; 0       ;
+; LP_D[5]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~339                                                                                                                   ; 0                 ; 0       ;
+; LP_D[4]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~378                                                                                                                   ; 0                 ; 0       ;
+; LP_D[3]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~383                                                                                                                   ; 1                 ; 0       ;
+; LP_D[2]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~186                                                                                                                   ; 1                 ; 0       ;
+; LP_D[1]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~206                                                                                                                   ; 0                 ; 0       ;
+; LP_D[0]                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~227                                                                                                                   ; 0                 ; 0       ;
+; SCSI_D[7]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[6]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[5]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[4]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[3]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[2]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[1]                                                                                                                                                                                            ;                   ;         ;
+; SCSI_D[0]                                                                                                                                                                                            ;                   ;         ;
+; nRSTO_MCF                                                                                                                                                                                            ;                   ;         ;
+; nFB_WR                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS                                                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SUB_BUS~0                                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|TIN0~0                                                                                                                                                               ; 1                 ; 0       ;
+;      - DSP:Mathias_Alles|nSRWE~0                                                                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPIO_REGISTERS~0                                                                  ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~1                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector0~0                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0                                                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~11                                                                                                                                                   ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~0                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~0                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~1                                                                                                                                              ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[31]~0                                                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|Selector1~4                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~1                                                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0                                                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~1                                                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[7]~0                                                                                                                                                         ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~19                                                                                                                                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~1                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1                                                                                                               ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CONTROL~0                                              ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE~1                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0                                                               ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0                                                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1                                                              ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0                                                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~0                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~0                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~1                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~5                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~11                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~15                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT_EN~1                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~0                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR_READ~0                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~1                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR_READ~0                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~1                                                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~0                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_EN~1                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|Mux1~0                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~2                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~3                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DATA_EN~0                                              ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0                                                          ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~1                                                                                                              ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~0                                                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~0                                                                ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0                                                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[9]~0                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[8]~1                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[6]~2                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[5]~3                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[4]~4                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[3]~5                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[2]~6                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[1]~7                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR[0]~8                                                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~4                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~5                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~6                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT~5                                                                                               ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~9                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~10                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~14                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~15                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~17                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~218                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~42                                                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~238                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~1                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~35                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~37                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~40                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~350                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[3]~1                                                                                      ; 0                 ; 0       ;
+;      - DSP:Mathias_Alles|nSRWE~1                                                                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]~1                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~0                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nFDC_WR~0                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[23]~1                                                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[23]~1                                                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|RTC_ADR[5]~0                                                                                                                                                         ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~491                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[0][0]~1                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][1]~2                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~492                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][3]~5                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~496                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][5]~9                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~503                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~504                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|_~505                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|_~506                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][10]~10                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][12]~11                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][13]~13                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][14]~15                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][15]~16                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][16]~17                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][17]~18                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][18]~19                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][19]~20                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][20]~21                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][21]~22                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][22]~23                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][23]~24                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][24]~25                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][25]~26                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][26]~27                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][27]~28                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][28]~29                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][29]~30                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][30]~31                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][31]~32                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][32]~33                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][33]~34                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][34]~35                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][35]~36                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][36]~37                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][37]~38                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][38]~39                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][39]~40                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][40]~41                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][41]~42                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][42]~43                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][43]~44                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][44]~45                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][45]~46                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][46]~47                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][47]~48                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][48]~49                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][49]~50                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][50]~51                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][51]~52                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][52]~53                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][53]~54                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][54]~55                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][55]~56                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][56]~57                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][57]~58                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][58]~59                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][59]~60                                                                                                                                                      ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][60]~61                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][61]~62                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][62]~63                                                                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][63]~64                                                                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0                                                                         ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0                                                                          ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~2                                                                                                    ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[15]~2                                                                                                                                                       ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0                                                                                                                    ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0]                                                                                                          ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1                                                                                                              ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[31]~3                                                                                                                                                        ; 0                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~0                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~4                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7                                                                                                              ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[7]~3                                                                                                                                                         ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]~0                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_WR~0                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                                         ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_RECONFIG~0                                                                                                           ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|WERTE[7][11]~77                                                                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3                                                                                                              ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0                                                                                            ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_2~0                                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3]                                                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2                                                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3                                                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4                                                                                                                                             ; 0                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state~2                                                                          ; 1                 ; 0       ;
+;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state~0                                                                                  ; 1                 ; 0       ;
+; nFB_CS1                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS                                                                                                                          ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_CS                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|TIN0~0                                                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE_CS                                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~2                                                                                                             ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT_CS~2                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF_CS                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW_CS~0                                                                                                                    ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|UHR_DS~3                                                                                                                                                             ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|MFP_CS~1                                                                                                                        ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|_~3                                                                                                                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|NEXT_CMD_STATE.T1~0                                                                                                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector2~0                                                                                                                     ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~28                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~32                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~7                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_M                                                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_H                                                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~6                                                                                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~8                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~36                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~37                                                                                                                                                   ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~38                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~39                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~27                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~40                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~41                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[9]~81                                                          ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~43                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~38                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~44                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~45                                                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|TIN0~1                                                                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_L                                                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~46                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~47                                                                                                                                                   ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~48                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~49                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~50                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~51                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~52                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~53                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~54                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~55                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1                                                                                                     ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7                                                                                                              ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                                         ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~34                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~35                                                                                       ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59                                                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[2]~36                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0                                                                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS                                                                                                                           ; 1                 ; 0       ;
+; FB_SIZE1                                                                                                                                                                                             ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1                                                                                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|FB_B[0]~0                                                                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1                                                                                                                  ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|_~22                                                                                                                                                                 ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20                                                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|UHR_AS~0                                                                                                                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|UHR_DS~6                                                                                                                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~194                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|FB_B[2]~1                                                                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2]                                                                                                                    ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0]                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0                                                                                                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                                              ; 1                 ; 0       ;
+; FB_SIZE0                                                                                                                                                                                             ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1                                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|FB_B[0]~0                                                                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1                                                                                                                  ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~22                                                                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20                                                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|UHR_AS~0                                                                                                                                                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|UHR_DS~6                                                                                                                                                             ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|_~194                                                                                                                                                                ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|FB_B[2]~1                                                                                                                                                            ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2]                                                                                                                    ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0]                                                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0                                                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                                              ; 0                 ; 0       ;
+; FB_ALE                                                                                                                                                                                               ;                   ;         ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                                                 ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                                                 ; 1                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                                                ; 0                 ; 0       ;
+;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5                                                                                                                                             ; 1                 ; 0       ;
+; nFB_CS2                                                                                                                                                                                              ;                   ;         ;
+;      - DSP:Mathias_Alles|nSRCS~0                                                                                                                                                                     ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~4                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_RECONFIG_CS~0                                                                                                    ; 0                 ; 0       ;
+;      - inst2~3                                                                                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0                                                                                                             ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1                                                                                                              ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_CONFIG_CS~0                                                                                                      ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA_CS                                                                                                                                                           ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR_CS                                                                                                                                                           ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~23                                                                                                                                                                 ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF_CS                                                                                                                                                          ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~25                                                                                                                                                                 ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH_CS                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH_CS                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL_CS                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL_CS                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~2                                                                                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~3                                                                                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR_CS                                                                                                                     ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~13                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~14                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~147                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~148                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR_CS                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CLEAR_CS                                                                                                                                                         ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~195                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~196                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~198                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~199                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2                                                                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~200                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~201                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~24                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~25                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~246                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~247                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~35                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~41                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~42                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~248                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~46                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~47                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~295                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~53                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~54                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~338                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~339                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~60                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~61                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~382                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~383                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~67                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~68                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~426                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~427                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~470                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~471                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~473                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~474                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~71                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~475                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~476                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~73                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~74                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~477                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~75                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~76                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~480                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~77                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~78                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~79                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~80                                                                                                                       ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~483                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~484                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~485                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~486                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~487                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~488                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~489                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~490                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0                                                                                                                  ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1                                                                                                                  ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3                                                                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_CTR[15]~2                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|INT_ENA[15]~2                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~508                                                                                                                                                                ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34                                                                                             ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42                                                                                             ; 0                 ; 0       ;
+; MAIN_CLK                                                                                                                                                                                             ;                   ;         ;
+; nDACK1                                                                                                                                                                                               ;                   ;         ;
+; nFB_OE                                                                                                                                                                                               ;                   ;         ;
+;      - DSP:Mathias_Alles|nSROE~0                                                                                                                                                                     ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31                                                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~39                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~40                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~43                                                                                                                        ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[0]~0                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~45                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~47                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~48                                                                                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_RD                                                                                                                 ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_RD                                                                                                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~51                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[3]~2                                                                                                                                           ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[0]~3                                                                                                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~55                                                                                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~56                                                                                                                        ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[1]~4                                                                                                                                           ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[2]~5                                                                                                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~59                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~60                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~61                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~65                                                                                                                    ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~10                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~67                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~70                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~72                                                                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~77                                                                                                                    ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[3]~28                                                          ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[1]~3                                                                                                      ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~85                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~89                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~94                                                                                                                        ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19                                                                                                                       ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~111                                                                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~124                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~127                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~129                                                                                                                   ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDH                                                                                                            ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[14]~34                                                         ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[15]~40                                                         ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~154                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~160                                                                                                                   ; 1                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[2]~6                                                                                                      ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDL~0                                                                                                          ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~170                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~175                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~176                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~179                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~181                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~182                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~193                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~195                                                                                                                   ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~211                                                                                                                   ; 0                 ; 0       ;
+;      - DSP:Mathias_Alles|FB_AD[25]~0                                                                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~215                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~220                                                                                                                   ; 0                 ; 0       ;
+;      - DSP:Mathias_Alles|FB_AD[24]~1                                                                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~235                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~240                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[7]~9                                                                                                      ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~250                                                                                                                   ; 0                 ; 0       ;
+;      - DSP:Mathias_Alles|FB_AD[23]~2                                                                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~255                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[6]~12                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~267                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~272                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[5]~15                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~283                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~288                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[4]~18                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~299                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~304                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~308                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~312                                                                                                                   ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[3]~21                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~317                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[15]~327                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~352                                                                                                                   ; 0                 ; 0       ;
+;      - DSP:Mathias_Alles|FB_AD[29]~3                                                                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~356                                                                                                                   ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[13]~173                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~366                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~375                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~388                                                                                                                   ; 1                 ; 0       ;
+;      - DSP:Mathias_Alles|FB_AD[27]~4                                                                                                                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~392                                                                                                                   ; 1                 ; 0       ;
+;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[11]~186                                                        ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~411                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~415                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~420                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~424                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[7]~432                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[6]~437                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[5]~445                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[4]~453                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[3]~461                                                                                                                    ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[2]~469                                                                                                                    ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|_~508                                                                                                                                                                ; 0                 ; 0       ;
+;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59                                                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~490                                                                                                                   ; 1                 ; 0       ;
+; IDE_RDY                                                                                                                                                                                              ;                   ;         ;
+;      - inst2~1                                                                                                                                                                                       ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~0                                                                                                                     ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_TA~0                                                                                                                     ; 1                 ; 0       ;
+; CLK33M                                                                                                                                                                                               ;                   ;         ;
+; HD_DD                                                                                                                                                                                                ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|HD_DD_OUT~0                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~62                                                                                                                    ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PHASE_DECODER~0                                                       ; 1                 ; 0       ;
+; nINDEX                                                                                                                                                                                               ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~1                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~2                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~78                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOCK~0                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK~1                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~113                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~173                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_COUNTER~2                                                               ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ~4                                                                       ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~205                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK~0                                                         ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DRQ_IPn~0                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_INDEX_MARK:LOCK~0                                                          ; 0                 ; 0       ;
+;      - nINDEX~_wirecell                                                                                                                                                                              ; 0                 ; 0       ;
+; RxD                                                                                                                                                                                                  ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|SDATA_IN_I~1                                                                ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SDATA_IN_I~2                             ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_SAMPLE~6                               ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_START_BIT~0                            ; 0                 ; 0       ;
+; nWP                                                                                                                                                                                                  ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~85                                                                  ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~168                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~176                                                                 ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR~0                                                                       ; 1                 ; 0       ;
+; LP_BUSY                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[0]~20                                                                                          ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~15                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~15                                                               ; 0                 ; 0       ;
+; DCD                                                                                                                                                                                                  ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[1]~43                                                                                          ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~10                                                           ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~10                                                               ; 0                 ; 0       ;
+; CTS                                                                                                                                                                                                  ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[2]~63                                                                                          ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~9                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~9                                                                ; 1                 ; 0       ;
+; TRACK00                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TR_CLR                                                                        ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~18                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~20                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~22                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~24                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~26                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~28                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~103                                                                 ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~2                                                              ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~3                                                              ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30                                                                   ; 0                 ; 0       ;
+; IDE_INT                                                                                                                                                                                              ;                   ;         ;
+; RI                                                                                                                                                                                                   ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~11                                                           ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT~104                                                                                            ; 1                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~11                                                               ; 1                 ; 0       ;
+; nPCI_INTD                                                                                                                                                                                            ;                   ;         ;
+;      - interrupt_handler:nobody|INT_LATCH[6]~11                                                                                                                                                      ; 0                 ; 6       ;
+;      - interrupt_handler:nobody|_~484                                                                                                                                                                ; 1                 ; 0       ;
+; nPCI_INTC                                                                                                                                                                                            ;                   ;         ;
+;      - interrupt_handler:nobody|INT_LATCH[5]~12                                                                                                                                                      ; 1                 ; 6       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[5]~5                                                                                                      ; 0                 ; 0       ;
+; nPCI_INTB                                                                                                                                                                                            ;                   ;         ;
+;      - interrupt_handler:nobody|INT_LATCH[4]~13                                                                                                                                                      ; 0                 ; 6       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[4]~8                                                                                                      ; 1                 ; 0       ;
+; nPCI_INTA                                                                                                                                                                                            ;                   ;         ;
+;      - interrupt_handler:nobody|INT_LATCH[3]~14                                                                                                                                                      ; 1                 ; 6       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[3]~11                                                                                                     ; 0                 ; 0       ;
+; DVI_INT                                                                                                                                                                                              ;                   ;         ;
+; E0_INT                                                                                                                                                                                               ;                   ;         ;
+; PIC_INT                                                                                                                                                                                              ;                   ;         ;
+;      - interrupt_handler:nobody|INT_LATCH[0]~17                                                                                                                                                      ; 1                 ; 6       ;
+;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[0]~20                                                                                                     ; 0                 ; 0       ;
+;      - interrupt_handler:nobody|PIC_INT_SYNC[0]                                                                                                                                                      ; 0                 ; 0       ;
+; PIC_AMKB_RX                                                                                                                                                                                          ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|KEYB_RxD                                                                                                                        ; 0                 ; 1       ;
+; MIDI_IN                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_I~feeder                                                    ; 1                 ; 1       ;
+; nRD_DATA                                                                                                                                                                                             ;                   ;         ;
+; AMKB_RX                                                                                                                                                                                              ;                   ;         ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~11                                                                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14                                                                                                                  ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]~9                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]~7                                                                                                                   ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]                                                                                                                     ; 0                 ; 0       ;
+;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13                                                                                                                  ; 1                 ; 0       ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                                                                        ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                                                         ; Location               ; Fan-Out ; Usage                                 ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+; CLK33M                                                                                                                                                                       ; PIN_AB12               ; 12      ; Clock                                 ; yes    ; Global Clock         ; GCLK15           ; --                        ;
+; CLK33M                                                                                                                                                                       ; PIN_AB12               ; 5       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; DSP:Mathias_Alles|nSRWE~1                                                                                                                                                    ; LCCOMB_X23_Y8_N20      ; 16      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FB_ALE                                                                                                                                                                       ; PIN_R7                 ; 33      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13                                                                                                 ; LCCOMB_X1_Y10_N14      ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO                                                                                                       ; LCCOMB_X26_Y22_N16     ; 250     ; Async. clear                          ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1                                                                                              ; LCCOMB_X18_Y17_N18     ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1                                                                                                   ; LCCOMB_X22_Y14_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1                                                                                                   ; LCCOMB_X22_Y14_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~0                                                                                                 ; LCCOMB_X16_Y14_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]~1                                                                                                 ; LCCOMB_X16_Y14_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104                                                                                                  ; LCCOMB_X21_Y12_N8      ; 16      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78                                                                                                   ; LCCOMB_X22_Y13_N12     ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183                                                                                                  ; LCCOMB_X22_Y13_N30     ; 4       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259                                                                                                  ; LCCOMB_X22_Y13_N4      ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203                                                                                                  ; LCCOMB_X22_Y13_N16     ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224                                                                                                  ; LCCOMB_X22_Y13_N10     ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141                                                                                                  ; LCCOMB_X33_Y1_N4       ; 5       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector4~1                                                                                                    ; LCCOMB_X23_Y18_N0      ; 20      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~1                                                                                                   ; LCCOMB_X22_Y13_N2      ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|Equal0~4                                             ; LCCOMB_X22_Y28_N30     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]~1                                           ; LCCOMB_X21_Y28_N6      ; 16      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]~3                               ; LCCOMB_X21_Y28_N12     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SHFT                                       ; FF_X34_Y29_N7          ; 26      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SHFT_LOAD_ND~0                                               ; LCCOMB_X28_Y27_N8      ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47                                                ; LCCOMB_X35_Y25_N2      ; 88      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector78~0                                                 ; LCCOMB_X32_Y25_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor2~5                                                   ; LCCOMB_X36_Y28_N0      ; 33      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor8                                                     ; LCCOMB_X28_Y27_N6      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]~1                                  ; LCCOMB_X32_Y27_N4      ; 8       ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]~37                                          ; LCCOMB_X27_Y26_N22     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT~27                                           ; LCCOMB_X30_Y30_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE                                             ; FF_X30_Y32_N13         ; 18      ; Clock enable, Sync. load              ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]~1                     ; LCCOMB_X27_Y32_N24     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]                                           ; FF_X32_Y25_N31         ; 20      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]~1                                         ; LCCOMB_X32_Y25_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Equal3~2                                                 ; LCCOMB_X27_Y25_N14     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~1                                              ; LCCOMB_X29_Y25_N2      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]~9                                           ; LCCOMB_X28_Y27_N26     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG~8                                              ; LCCOMB_X30_Y28_N22     ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~1                                               ; LCCOMB_X30_Y26_N20     ; 9       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]~3                                           ; LCCOMB_X30_Y26_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT~1                                            ; LCCOMB_X28_Y30_N28     ; 31      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT~12                                            ; LCCOMB_X36_Y29_N10     ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK~0                                     ; LCCOMB_X25_Y29_N26     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]~0                             ; LCCOMB_X25_Y27_N6      ; 23      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1                                                                        ; LCCOMB_X18_Y19_N22     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0                                                                           ; LCCOMB_X15_Y14_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1                                                                ; FF_X4_Y41_N5           ; 8       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0                                                                           ; LCCOMB_X7_Y39_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0                                                                          ; LCCOMB_X19_Y23_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WAV_STRB                                                                              ; FF_X9_Y21_N23          ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0                                                ; LCCOMB_X17_Y22_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET                                                    ; FF_X18_Y22_N21         ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0                                                  ; LCCOMB_X18_Y22_N20     ; 9       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0                                               ; LCCOMB_X18_Y24_N0      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB~1                                                   ; LCCOMB_X18_Y23_N8      ; 19      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal14~3                                                    ; LCCOMB_X20_Y21_N28     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal16~3                                                    ; LCCOMB_X19_Y24_N20     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal18~3                                                    ; LCCOMB_X18_Y20_N28     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0                                            ; LCCOMB_X15_Y14_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1                                             ; LCCOMB_X20_Y23_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0                                            ; LCCOMB_X19_Y24_N30     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1                                             ; LCCOMB_X20_Y20_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0                                            ; LCCOMB_X18_Y20_N2      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1                                             ; LCCOMB_X17_Y18_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0                                                 ; LCCOMB_X17_Y25_N18     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0                                                 ; LCCOMB_X20_Y22_N6      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0                                                 ; LCCOMB_X21_Y27_N0      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0                                              ; LCCOMB_X17_Y19_N26     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT~1                                                  ; LCCOMB_X17_Y25_N24     ; 39      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]~12                                                ; LCCOMB_X18_Y25_N10     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]~0                                 ; LCCOMB_X16_Y24_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]~0                               ; LCCOMB_X16_Y24_N6      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]~2                                 ; LCCOMB_X16_Y24_N24     ; 17      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]~0                         ; LCCOMB_X6_Y18_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1                                      ; LCCOMB_X4_Y19_N12      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]~1                                 ; LCCOMB_X5_Y18_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0                              ; LCCOMB_X2_Y21_N28      ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]~1                                ; LCCOMB_X5_Y17_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]~1                       ; LCCOMB_X1_Y18_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1                                    ; LCCOMB_X1_Y19_N30      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]~1                               ; LCCOMB_X3_Y19_N4       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]~1                              ; LCCOMB_X2_Y19_N2       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE                               ; FF_X1_Y20_N15          ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]~3                     ; LCCOMB_X1_Y20_N26      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]~1                             ; LCCOMB_X7_Y18_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1                                          ; LCCOMB_X4_Y19_N18      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]~1                                     ; LCCOMB_X5_Y16_N14      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0                                  ; LCCOMB_X3_Y17_N26      ; 6       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]~1                                    ; LCCOMB_X4_Y17_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]~1                           ; LCCOMB_X3_Y17_N22      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1                                        ; LCCOMB_X5_Y20_N0       ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]~1                                   ; LCCOMB_X4_Y21_N6       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]~1                                  ; LCCOMB_X5_Y21_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE                                   ; FF_X6_Y19_N27          ; 12      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]~1                         ; LCCOMB_X6_Y19_N28      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0                                                         ; LCCOMB_X14_Y18_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0                                                         ; LCCOMB_X14_Y14_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0                                                        ; LCCOMB_X14_Y15_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0                                            ; LCCOMB_X14_Y16_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0                                            ; LCCOMB_X14_Y16_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0                                            ; LCCOMB_X16_Y19_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0                                            ; LCCOMB_X16_Y19_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[9]~5                                        ; LCCOMB_X17_Y21_N4      ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST                                    ; FF_X16_Y17_N3          ; 23      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[0]~7                                     ; LCCOMB_X17_Y17_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]~0                                              ; LCCOMB_X16_Y16_N4      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_A~0                                                 ; LCCOMB_X6_Y20_N18      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_B~0                                                 ; LCCOMB_X6_Y20_N8       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_C~0                                                 ; LCCOMB_X3_Y20_N0       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_D~0                                                 ; LCCOMB_X9_Y17_N6       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0                                                    ; LCCOMB_X12_Y16_N22     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~0                                                    ; LCCOMB_X8_Y20_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0                                                    ; LCCOMB_X10_Y18_N30     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~0                                                    ; LCCOMB_X7_Y17_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0                                                   ; LCCOMB_X12_Y18_N10     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~0                                                    ; LCCOMB_X10_Y15_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]~0                                                    ; LCCOMB_X4_Y15_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERC~1                                                     ; LCCOMB_X10_Y15_N2      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERD~1                                                     ; LCCOMB_X3_Y15_N4       ; 9       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[0]~0                                               ; LCCOMB_X10_Y18_N16     ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[0]~3                                               ; LCCOMB_X12_Y17_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[0]~1                                               ; LCCOMB_X11_Y18_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[0]~1                                               ; LCCOMB_X11_Y18_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL_STRB                                                    ; FF_X3_Y20_N7           ; 44      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]~0                 ; LCCOMB_X14_Y19_N26     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]~0                 ; LCCOMB_X14_Y22_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]~1                 ; LCCOMB_X14_Y19_N24     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]~0                 ; LCCOMB_X12_Y16_N8      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7]                   ; FF_X14_Y20_N1          ; 19      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~3                 ; LCCOMB_X11_Y19_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]~2             ; LCCOMB_X10_Y24_N14     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]~1          ; LCCOMB_X10_Y22_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[0]~0 ; LCCOMB_X3_Y27_N20      ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT~1               ; LCCOMB_X14_Y23_N6      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|CLK_STRB               ; FF_X2_Y27_N7           ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFTREG~0             ; LCCOMB_X12_Y21_N12     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]~8         ; LCCOMB_X12_Y23_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TX_END                 ; FF_X12_Y23_N17         ; 17      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|_~0                   ; LCCOMB_X21_Y9_N28      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1         ; LCCOMB_X23_Y7_N18      ; 20      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_wrreq~1         ; LCCOMB_X18_Y18_N20     ; 18      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|_~0                   ; LCCOMB_X22_Y22_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_rdreq~1         ; LCCOMB_X22_Y22_N4      ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_wrreq~0         ; LCCOMB_X26_Y24_N4      ; 22      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0                                                                                                   ; LCCOMB_X20_Y16_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0                                                                                                   ; LCCOMB_X20_Y16_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2                                                                                                    ; LCCOMB_X26_Y22_N14     ; 32      ; Async. clear                          ; yes    ; Global Clock         ; GCLK5            ; --                        ;
+; MAIN_CLK                                                                                                                                                                     ; PIN_G2                 ; 2272    ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT                                                                                                                        ; FF_X23_Y12_N17         ; 26      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]~1                                                                                                                  ; LCCOMB_X27_Y6_N0       ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4                                                                                                                            ; LCCOMB_X22_Y2_N22      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2                                                                                                                            ; LCCOMB_X34_Y2_N8       ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3                                                                                                                            ; LCCOMB_X21_Y4_N10      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3]                                                                                                                              ; LCCOMB_X34_Y2_N24      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]~40                                                                                                                  ; LCCOMB_X26_Y8_N24      ; 23      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0                                                                                                                   ; LCCOMB_X26_Y11_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0                                                                                                                   ; LCCOMB_X26_Y11_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                   ; LCCOMB_X25_Y11_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0                                                                                                                   ; LCCOMB_X23_Y11_N24     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[1]                                                                                            ; LCCOMB_X25_Y16_N22     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[2]                                                                                            ; LCCOMB_X25_Y14_N26     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[3]                                                                                            ; LCCOMB_X25_Y16_N0      ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3                                                                                            ; LCCOMB_X22_Y19_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0                                                                                            ; LCCOMB_X23_Y12_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2                                                                                            ; LCCOMB_X27_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1                                                                                             ; LCCOMB_X23_Y18_N22     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6                                                                                             ; LCCOMB_X28_Y18_N22     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1                                                                                            ; LCCOMB_X21_Y19_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0                                                                                            ; LCCOMB_X29_Y14_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2                                                                                            ; LCCOMB_X23_Y14_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3                                                                                             ; LCCOMB_X23_Y14_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1                                                                                            ; LCCOMB_X23_Y19_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0                                                                                            ; LCCOMB_X28_Y15_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2                                                                                            ; LCCOMB_X25_Y17_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3                                                                                             ; LCCOMB_X22_Y17_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1                                                                                            ; LCCOMB_X21_Y19_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0                                                                                            ; LCCOMB_X28_Y15_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2                                                                                            ; LCCOMB_X28_Y17_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3                                                                                             ; LCCOMB_X28_Y17_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1                                                                                            ; LCCOMB_X23_Y19_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0                                                                                            ; LCCOMB_X29_Y12_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2                                                                                            ; LCCOMB_X25_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3                                                                                             ; LCCOMB_X25_Y17_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1                                                                                                 ; LCCOMB_X22_Y18_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0                                                                                                 ; LCCOMB_X29_Y18_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2                                                                                                  ; LCCOMB_X23_Y18_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                                  ; FF_X33_Y18_N13         ; 54      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                                  ; FF_X33_Y18_N15         ; 54      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                                                                                  ; FF_X29_Y21_N3          ; 34      ; Async. clear                          ; yes    ; Global Clock         ; GCLK11           ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_FIFO_CLR                                                                                              ; FF_X36_Y17_N25         ; 21      ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0]                                                                                         ; LCCOMB_X23_Y16_N24     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[1]                                                                                         ; LCCOMB_X23_Y16_N8      ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[3]                                                                                         ; LCCOMB_X23_Y16_N18     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3                                                                                   ; LCCOMB_X28_Y16_N22     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1                                                                                    ; LCCOMB_X28_Y16_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                                  ; FF_X37_Y20_N27         ; 141     ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                      ; FF_X33_Y12_N25         ; 30      ; Clock enable, Sync. clear             ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                                                                                 ; LCCOMB_X26_Y18_N4      ; 3       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                                                                                 ; LCCOMB_X26_Y18_N4      ; 850     ; Clock                                 ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]                                                                                             ; LCCOMB_X26_Y13_N18     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[1]                                                                                             ; LCCOMB_X21_Y13_N14     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                        ; LCCOMB_X29_Y17_N18     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[6]~7                                                                                        ; LCCOMB_X35_Y17_N16     ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX                                                                                                  ; FF_X34_Y14_N13         ; 10      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0                                                                                              ; LCCOMB_X26_Y16_N6      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]~1                                                                                             ; LCCOMB_X30_Y13_N14     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]~0                                                                                              ; LCCOMB_X30_Y13_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~1                                                                                             ; LCCOMB_X30_Y10_N2      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]~0                                                                                              ; LCCOMB_X29_Y10_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]~1                                                                                             ; LCCOMB_X30_Y10_N12     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]~0                                                                                              ; LCCOMB_X29_Y10_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]~1                                                                                             ; LCCOMB_X33_Y13_N12     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]~0                                                                                              ; LCCOMB_X33_Y13_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]~1                                                                                             ; LCCOMB_X30_Y12_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]~0                                                                                              ; LCCOMB_X30_Y12_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]~1                                                                                             ; LCCOMB_X29_Y14_N22     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]~0                                                                                              ; LCCOMB_X26_Y12_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1                                                                                             ; LCCOMB_X26_Y17_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0                                                                                              ; LCCOMB_X27_Y15_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3                                                                                             ; LCCOMB_X26_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2                                                                                              ; LCCOMB_X26_Y15_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]~1                                                                                             ; LCCOMB_X30_Y15_N4      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~0                                                                                              ; LCCOMB_X29_Y15_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]~1                                                                                             ; LCCOMB_X25_Y13_N18     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~0                                                                                              ; LCCOMB_X30_Y13_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0                                                                                              ; LCCOMB_X26_Y18_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1                                                                                              ; LCCOMB_X26_Y13_N20     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]~1                                                                                             ; LCCOMB_X29_Y14_N20     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]~0                                                                                              ; LCCOMB_X29_Y13_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]~1                                                                                             ; LCCOMB_X30_Y15_N30     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]~0                                                                                              ; LCCOMB_X29_Y16_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]~1                                                                                             ; LCCOMB_X26_Y14_N6      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]~0                                                                                              ; LCCOMB_X27_Y16_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0                                                                                              ; LCCOMB_X25_Y18_N26     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1                                                                                             ; LCCOMB_X27_Y18_N20     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0                                                                                              ; LCCOMB_X26_Y16_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~3                                                                                               ; LCCOMB_X27_Y18_N6      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~92                                                                                                      ; LCCOMB_X28_Y20_N4      ; 10      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst37                                                                                                                                                ; LCCOMB_X66_Y4_N2       ; 32      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst65~0                                                                                                                                              ; LCCOMB_X37_Y20_N28     ; 34      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst67                                                                                                                                                ; LCCOMB_X37_Y17_N12     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst90                                                                                                                                                ; DDIOOECELL_X63_Y0_N12  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                   ; DDIOOECELL_X67_Y11_N12 ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                   ; DDIOOECELL_X52_Y0_N26  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                   ; DDIOOECELL_X43_Y0_N19  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|inst95                                                                                                                                                ; FF_X39_Y18_N21         ; 128     ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|_~0                                                         ; LCCOMB_X36_Y20_N2      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0]                                                    ; FF_X57_Y17_N21         ; 72      ; Async. clear                          ; yes    ; Global Clock         ; GCLK9            ; --                        ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0                                                                    ; LCCOMB_X57_Y17_N14     ; 14      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                                      ; FF_X45_Y15_N1          ; 258     ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                                      ; FF_X18_Y13_N29         ; 64      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                      ; FF_X18_Y13_N3          ; 33      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]                                                                                                       ; PLL_3                  ; 52      ; Clock                                 ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]                                                                                                     ; PLL_1                  ; 691     ; Clock                                 ; yes    ; Global Clock         ; GCLK3            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]                                                                                                     ; PLL_1                  ; 96      ; Clock                                 ; yes    ; Global Clock         ; GCLK1            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]                                                                                                     ; PLL_1                  ; 5       ; Clock                                 ; yes    ; Global Clock         ; GCLK0            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]                                                                                                     ; PLL_1                  ; 41      ; Clock                                 ; yes    ; Global Clock         ; GCLK2            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]                                                                                                     ; PLL_1                  ; 189     ; Clock, Latch enable                   ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]                                                                                                     ; PLL_4                  ; 7       ; Clock                                 ; yes    ; Global Clock         ; GCLK16           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]                                                                                                     ; PLL_4                  ; 585     ; Clock                                 ; yes    ; Global Clock         ; GCLK17           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]                                                                                                     ; PLL_4                  ; 4       ; Clock                                 ; yes    ; Global Clock         ; GCLK18           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]                                                                                                     ; PLL_4                  ; 2       ; Clock                                 ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~1                                                                               ; LCCOMB_X23_Y26_N8      ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|busy                                                                              ; LCCOMB_X22_Y25_N2      ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|input_latch_enable~0                                                              ; LCCOMB_X22_Y26_N10     ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7]~0                   ; LCCOMB_X14_Y25_N0      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|_~0                                    ; LCCOMB_X19_Y28_N4      ; 14      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7]~0                   ; LCCOMB_X21_Y29_N18     ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|_~9                                     ; LCCOMB_X21_Y27_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]~0                    ; LCCOMB_X18_Y29_N18     ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|_~0                                     ; LCCOMB_X21_Y26_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~4                                                                        ; LCCOMB_X21_Y26_N10     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~5                                                                        ; LCCOMB_X21_Y27_N12     ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~0                                                          ; LCCOMB_X21_Y29_N6      ; 16      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~1                                                          ; LCCOMB_X18_Y29_N24     ; 13      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state                                                            ; FF_X22_Y29_N31         ; 13      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|scan_cache_write_enable~0                                                         ; LCCOMB_X20_Y26_N4      ; 3       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~3                                                                   ; LCCOMB_X22_Y23_N2      ; 18      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg_clear~0                                                                 ; LCCOMB_X22_Y27_N28     ; 35      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ; --                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state                                                        ; FF_X21_Y25_N29         ; 10      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
+; inst25                                                                                                                                                                       ; LCCOMB_X15_Y23_N20     ; 1027    ; Async. clear, Async. load             ; yes    ; Global Clock         ; GCLK10           ; --                        ;
+; inst25                                                                                                                                                                       ; LCCOMB_X15_Y23_N20     ; 119     ; Clock enable, Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|ACHTELSEKUNDEN[2]~0                                                                                                                                 ; LCCOMB_X1_Y13_N6       ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                      ; LCCOMB_X16_Y11_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                      ; LCCOMB_X11_Y13_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                      ; LCCOMB_X16_Y11_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                       ; LCCOMB_X15_Y11_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[0]                                                                                                                                        ; FF_X17_Y10_N9          ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[1]                                                                                                                                        ; FF_X17_Y10_N31         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[2]                                                                                                                                        ; FF_X17_Y10_N1          ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[3]                                                                                                                                        ; FF_X17_Y10_N23         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[4]                                                                                                                                        ; FF_X17_Y10_N21         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[5]                                                                                                                                        ; FF_X17_Y10_N11         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[6]                                                                                                                                        ; FF_X17_Y10_N25         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[8]                                                                                                                                        ; FF_X17_Y10_N15         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CLEAR[9]                                                                                                                                        ; FF_X17_Y10_N29         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CTR[15]~2                                                                                                                                       ; LCCOMB_X15_Y15_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CTR[23]~1                                                                                                                                       ; LCCOMB_X12_Y11_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CTR[31]~3                                                                                                                                       ; LCCOMB_X18_Y12_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_CTR[7]~0                                                                                                                                        ; LCCOMB_X15_Y13_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_ENA[15]~2                                                                                                                                       ; LCCOMB_X15_Y15_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_ENA[23]~1                                                                                                                                       ; LCCOMB_X12_Y13_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_ENA[31]~0                                                                                                                                       ; LCCOMB_X16_Y13_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_ENA[7]~3                                                                                                                                        ; LCCOMB_X15_Y13_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[0]~26                                                                                                                                     ; LCCOMB_X14_Y13_N30     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[1]~25                                                                                                                                     ; LCCOMB_X15_Y11_N22     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[2]~24                                                                                                                                     ; LCCOMB_X15_Y11_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[3]~23                                                                                                                                     ; LCCOMB_X15_Y10_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[4]~22                                                                                                                                     ; LCCOMB_X14_Y13_N20     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[5]~21                                                                                                                                     ; LCCOMB_X15_Y11_N0      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[6]~20                                                                                                                                     ; LCCOMB_X15_Y12_N26     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[8]~19                                                                                                                                     ; LCCOMB_X15_Y15_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|INT_LATCH[9]~18                                                                                                                                     ; LCCOMB_X15_Y15_N16     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|RTC_ADR[5]~0                                                                                                                                        ; LCCOMB_X8_Y12_N24      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[0][0]~1                                                                                                                                       ; LCCOMB_X6_Y15_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[0][13]~14                                                                                                                                     ; LCCOMB_X4_Y14_N22      ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[0][2]~4                                                                                                                                       ; LCCOMB_X7_Y15_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][10]~10                                                                                                                                     ; LCCOMB_X7_Y14_N4       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][11]~77                                                                                                                                     ; LCCOMB_X1_Y13_N26      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][12]~11                                                                                                                                     ; LCCOMB_X8_Y13_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][13]~13                                                                                                                                     ; LCCOMB_X6_Y14_N18      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][14]~15                                                                                                                                     ; LCCOMB_X7_Y14_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][15]~16                                                                                                                                     ; LCCOMB_X11_Y13_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][16]~17                                                                                                                                     ; LCCOMB_X4_Y13_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][17]~18                                                                                                                                     ; LCCOMB_X3_Y11_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][18]~19                                                                                                                                     ; LCCOMB_X2_Y14_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][19]~20                                                                                                                                     ; LCCOMB_X2_Y13_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][1]~2                                                                                                                                       ; LCCOMB_X7_Y13_N28      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][20]~21                                                                                                                                     ; LCCOMB_X2_Y13_N16      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][21]~22                                                                                                                                     ; LCCOMB_X3_Y14_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][22]~23                                                                                                                                     ; LCCOMB_X2_Y14_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][23]~24                                                                                                                                     ; LCCOMB_X3_Y10_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][24]~25                                                                                                                                     ; LCCOMB_X3_Y10_N14      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][25]~26                                                                                                                                     ; LCCOMB_X2_Y12_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][26]~27                                                                                                                                     ; LCCOMB_X2_Y12_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][27]~28                                                                                                                                     ; LCCOMB_X4_Y9_N24       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][28]~29                                                                                                                                     ; LCCOMB_X4_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][29]~30                                                                                                                                     ; LCCOMB_X3_Y11_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][30]~31                                                                                                                                     ; LCCOMB_X3_Y12_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][31]~32                                                                                                                                     ; LCCOMB_X5_Y12_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][32]~33                                                                                                                                     ; LCCOMB_X4_Y10_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][33]~34                                                                                                                                     ; LCCOMB_X8_Y10_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][34]~35                                                                                                                                     ; LCCOMB_X8_Y10_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][35]~36                                                                                                                                     ; LCCOMB_X4_Y10_N0       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][36]~37                                                                                                                                     ; LCCOMB_X2_Y10_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][37]~38                                                                                                                                     ; LCCOMB_X2_Y10_N24      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][38]~39                                                                                                                                     ; LCCOMB_X7_Y10_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][39]~40                                                                                                                                     ; LCCOMB_X4_Y10_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][3]~5                                                                                                                                       ; LCCOMB_X6_Y13_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][40]~41                                                                                                                                     ; LCCOMB_X6_Y9_N24       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][41]~42                                                                                                                                     ; LCCOMB_X5_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][42]~43                                                                                                                                     ; LCCOMB_X6_Y9_N6        ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][43]~44                                                                                                                                     ; LCCOMB_X9_Y11_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][44]~45                                                                                                                                     ; LCCOMB_X10_Y11_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][45]~46                                                                                                                                     ; LCCOMB_X10_Y10_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][46]~47                                                                                                                                     ; LCCOMB_X10_Y10_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][47]~48                                                                                                                                     ; LCCOMB_X9_Y13_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][48]~49                                                                                                                                     ; LCCOMB_X9_Y13_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][49]~50                                                                                                                                     ; LCCOMB_X9_Y10_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][50]~51                                                                                                                                     ; LCCOMB_X9_Y10_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][51]~52                                                                                                                                     ; LCCOMB_X8_Y9_N10       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][52]~53                                                                                                                                     ; LCCOMB_X7_Y9_N26       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][53]~54                                                                                                                                     ; LCCOMB_X11_Y9_N14      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][54]~55                                                                                                                                     ; LCCOMB_X10_Y9_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][55]~56                                                                                                                                     ; LCCOMB_X10_Y11_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][56]~57                                                                                                                                     ; LCCOMB_X10_Y9_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][57]~58                                                                                                                                     ; LCCOMB_X8_Y12_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][58]~59                                                                                                                                     ; LCCOMB_X8_Y12_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][59]~60                                                                                                                                     ; LCCOMB_X9_Y12_N24      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][5]~9                                                                                                                                       ; LCCOMB_X6_Y14_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][60]~61                                                                                                                                     ; LCCOMB_X5_Y12_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][61]~62                                                                                                                                     ; LCCOMB_X5_Y12_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][62]~63                                                                                                                                     ; LCCOMB_X12_Y12_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|WERTE[7][63]~64                                                                                                                                     ; LCCOMB_X11_Y12_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|_~503                                                                                                                                               ; LCCOMB_X6_Y11_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|_~504                                                                                                                                               ; LCCOMB_X5_Y11_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|_~505                                                                                                                                               ; LCCOMB_X4_Y14_N28      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
+; interrupt_handler:nobody|_~506                                                                                                                                               ; LCCOMB_X7_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                                                      ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLK33M                                                                                                                    ; PIN_AB12           ; 12      ; 0                                    ; Global Clock         ; GCLK15           ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO                                                    ; LCCOMB_X26_Y22_N16 ; 250     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2                                                 ; LCCOMB_X26_Y22_N14 ; 32      ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                               ; FF_X29_Y21_N3      ; 34      ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                              ; LCCOMB_X26_Y18_N4  ; 850     ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21     ; 72      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]                                                    ; PLL_3              ; 52      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]                                                    ; PLL_3              ; 1       ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]                                                    ; PLL_3              ; 1       ; 0                                    ; Global Clock         ; GCLK13           ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]                                                  ; PLL_1              ; 691     ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]                                                  ; PLL_1              ; 96      ; 0                                    ; Global Clock         ; GCLK1            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]                                                  ; PLL_1              ; 5       ; 0                                    ; Global Clock         ; GCLK0            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]                                                  ; PLL_1              ; 41      ; 0                                    ; Global Clock         ; GCLK2            ; --                        ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]                                                  ; PLL_1              ; 189     ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]                                                  ; PLL_4              ; 7       ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]                                                  ; PLL_4              ; 585     ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]                                                  ; PLL_4              ; 4       ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]                                                  ; PLL_4              ; 2       ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
+; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]                                                  ; PLL_2              ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
+; inst25                                                                                                                    ; LCCOMB_X15_Y23_N20 ; 1027    ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                             ;
++-----------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                              ; Fan-Out ;
++-----------------------------------------------------------------------------------------------------------------------------------+---------+
+; MAIN_CLK~input                                                                                                                    ; 2272    ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; 385     ;
+; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                           ; 258     ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; 257     ;
+; nFB_WR~input                                                                                                                      ; 235     ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; 225     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                    ; 208     ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; 161     ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; 158     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                   ; 156     ;
+; FB_AD[17]~input                                                                                                                   ; 145     ;
+; FB_AD[18]~input                                                                                                                   ; 145     ;
+; FB_AD[20]~input                                                                                                                   ; 144     ;
+; FB_AD[16]~input                                                                                                                   ; 143     ;
+; FB_AD[19]~input                                                                                                                   ; 143     ;
+; FB_AD[21]~input                                                                                                                   ; 143     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                       ; 141     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                      ; 141     ;
+; FB_AD[22]~input                                                                                                                   ; 140     ;
+; FB_AD[23]~input                                                                                                                   ; 137     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                ; 132     ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                ; 132     ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; 129     ;
+; Video:Fredi_Aschwanden|inst95                                                                                                     ; 128     ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; 120     ;
+; inst25                                                                                                                            ; 118     ;
+; nFB_OE~input                                                                                                                      ; 101     ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; 97      ;
+; nFB_CS2~input                                                                                                                     ; 95      ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47     ; 88      ;
+; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; 83      ;
+; interrupt_handler:nobody|RTC_ADR[4]                                                                                               ; 80      ;
+; interrupt_handler:nobody|RTC_ADR[5]                                                                                               ; 79      ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ROLL_OVER ; 78      ;
+; interrupt_handler:nobody|UHR_DS~5                                                                                                 ; 71      ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1                                                   ; 68      ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                     ; 66      ;
+; interrupt_handler:nobody|UHR_DS~6                                                                                                 ; 66      ;
+; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                        ; 65      ;
+; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                           ; 64      ;
+; FB_AD[24]~input                                                                                                                   ; 63      ;
+; interrupt_handler:nobody|RTC_ADR[3]                                                                                               ; 62      ;
+; interrupt_handler:nobody|RTC_ADR[2]                                                                                               ; 62      ;
+; interrupt_handler:nobody|RTC_ADR[1]                                                                                               ; 62      ;
+; interrupt_handler:nobody|RTC_ADR[0]                                                                                               ; 62      ;
+; ~GND                                                                                                                              ; 61      ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; 60      ;
+; nFB_CS1~input                                                                                                                     ; 59      ;
+; FB_AD[25]~input                                                                                                                   ; 59      ;
+; FB_AD[26]~input                                                                                                                   ; 57      ;
++-----------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
+; Name                                                                                                                                                                                       ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                       ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 1024         ; 8            ; 256          ; 32           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 1024                        ; 8                           ; 256                         ; 32                          ; 8192                ; 1    ; None ; M9K_X24_Y11_N0                                                                                                                 ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 256          ; 32           ; 1024         ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 256                         ; 32                          ; 1024                        ; 8                           ; 8192                ; 1    ; None ; M9K_X24_Y21_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y15_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                   ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y15_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                     ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y13_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y20_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                               ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y19_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                 ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y17_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y14_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y16_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y18_N0                                                                                                                 ;
+; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM                                        ; AUTO ; Simple Dual Port ; Dual Clocks  ; 128          ; 128          ; 128          ; 128          ; yes                    ; no                      ; yes                    ; no                      ; 16384 ; 128                         ; 128                         ; 128                         ; 128                         ; 16384               ; 4    ; None ; M9K_X40_Y19_N0, M9K_X40_Y20_N0, M9K_X40_Y21_N0, M9K_X40_Y22_N0                                                                 ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM                                                            ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 128          ; 512          ; 128          ; yes                    ; no                      ; yes                    ; yes                     ; 65536 ; 512                         ; 128                         ; 512                         ; 128                         ; 65536               ; 8    ; None ; M9K_X40_Y16_N0, M9K_X40_Y15_N0, M9K_X58_Y16_N0, M9K_X58_Y17_N0, M9K_X40_Y17_N0, M9K_X40_Y14_N0, M9K_X40_Y13_N0, M9K_X40_Y18_N0 ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM                                 ; AUTO ; Single Port      ; Single Clock ; 144          ; 1            ; --           ; --           ; yes                    ; no                      ; --                     ; --                      ; 144   ; 144                         ; 1                           ; --                          ; --                          ; 144                 ; 1    ; None ; M9K_X24_Y25_N0                                                                                                                 ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter DSP Block Usage Summary                                                                ;
++---------------------------------------+-------------+---------------------+-------------------+
+; Statistic                             ; Number Used ; Available per Block ; Maximum Available ;
++---------------------------------------+-------------+---------------------+-------------------+
+; Simple Multipliers (9-bit)            ; 0           ; 2                   ; 252               ;
+; Simple Multipliers (18-bit)           ; 3           ; 1                   ; 126               ;
+; Embedded Multiplier Blocks            ; 3           ; --                  ; 126               ;
+; Embedded Multiplier 9-bit elements    ; 6           ; 2                   ; 252               ;
+; Signed Embedded Multipliers           ; 0           ; --                  ; --                ;
+; Unsigned Embedded Multipliers         ; 3           ; --                  ; --                ;
+; Mixed Sign Embedded Multipliers       ; 0           ; --                  ; --                ;
+; Variable Sign Embedded Multipliers    ; 0           ; --                  ; --                ;
+; Dedicated Input Shift Register Chains ; 0           ; --                  ; --                ;
++---------------------------------------+-------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; DSP Block Details                                                                                                                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+; Name                                                                                                                   ; Mode                       ; Location           ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;
++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2     ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y14_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1 ;                            ; DSPMULT_X31_Y14_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2      ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y10_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_mult1  ;                            ; DSPMULT_X31_Y10_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2     ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y12_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
+;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_mult1 ;                            ; DSPMULT_X31_Y12_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
+
+
++--------------------------------------------------------+
+; Interconnect Usage Summary                             ;
++----------------------------+---------------------------+
+; Interconnect Resource Type ; Usage                     ;
++----------------------------+---------------------------+
+; Block interconnects        ; 16,358 / 116,715 ( 14 % ) ;
+; C16 interconnects          ; 749 / 3,886 ( 19 % )      ;
+; C4 interconnects           ; 10,626 / 73,752 ( 14 % )  ;
+; Direct links               ; 2,046 / 116,715 ( 2 % )   ;
+; Global clocks              ; 20 / 20 ( 100 % )         ;
+; Local interconnects        ; 4,734 / 39,600 ( 12 % )   ;
+; R24 interconnects          ; 882 / 3,777 ( 23 % )      ;
+; R4 interconnects           ; 11,442 / 99,858 ( 11 % )  ;
++----------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 12.60) ; Number of LABs  (Total = 756) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 41                            ;
+; 2                                           ; 20                            ;
+; 3                                           ; 22                            ;
+; 4                                           ; 11                            ;
+; 5                                           ; 13                            ;
+; 6                                           ; 12                            ;
+; 7                                           ; 15                            ;
+; 8                                           ; 13                            ;
+; 9                                           ; 13                            ;
+; 10                                          ; 30                            ;
+; 11                                          ; 23                            ;
+; 12                                          ; 32                            ;
+; 13                                          ; 29                            ;
+; 14                                          ; 47                            ;
+; 15                                          ; 59                            ;
+; 16                                          ; 376                           ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.78) ; Number of LABs  (Total = 756) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 239                           ;
+; 1 Clock                            ; 631                           ;
+; 1 Clock enable                     ; 289                           ;
+; 1 Sync. clear                      ; 20                            ;
+; 1 Sync. load                       ; 26                            ;
+; 2 Async. clears                    ; 12                            ;
+; 2 Clock enables                    ; 84                            ;
+; 2 Clocks                           ; 41                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 18.19) ; Number of LABs  (Total = 756) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 19                            ;
+; 2                                            ; 26                            ;
+; 3                                            ; 12                            ;
+; 4                                            ; 16                            ;
+; 5                                            ; 8                             ;
+; 6                                            ; 14                            ;
+; 7                                            ; 5                             ;
+; 8                                            ; 11                            ;
+; 9                                            ; 8                             ;
+; 10                                           ; 14                            ;
+; 11                                           ; 9                             ;
+; 12                                           ; 20                            ;
+; 13                                           ; 17                            ;
+; 14                                           ; 15                            ;
+; 15                                           ; 30                            ;
+; 16                                           ; 49                            ;
+; 17                                           ; 41                            ;
+; 18                                           ; 43                            ;
+; 19                                           ; 30                            ;
+; 20                                           ; 42                            ;
+; 21                                           ; 35                            ;
+; 22                                           ; 49                            ;
+; 23                                           ; 45                            ;
+; 24                                           ; 31                            ;
+; 25                                           ; 31                            ;
+; 26                                           ; 27                            ;
+; 27                                           ; 28                            ;
+; 28                                           ; 20                            ;
+; 29                                           ; 17                            ;
+; 30                                           ; 18                            ;
+; 31                                           ; 10                            ;
+; 32                                           ; 16                            ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 8.27) ; Number of LABs  (Total = 756) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 1                             ;
+; 1                                               ; 61                            ;
+; 2                                               ; 48                            ;
+; 3                                               ; 47                            ;
+; 4                                               ; 43                            ;
+; 5                                               ; 40                            ;
+; 6                                               ; 51                            ;
+; 7                                               ; 50                            ;
+; 8                                               ; 53                            ;
+; 9                                               ; 71                            ;
+; 10                                              ; 46                            ;
+; 11                                              ; 45                            ;
+; 12                                              ; 51                            ;
+; 13                                              ; 46                            ;
+; 14                                              ; 26                            ;
+; 15                                              ; 25                            ;
+; 16                                              ; 19                            ;
+; 17                                              ; 5                             ;
+; 18                                              ; 9                             ;
+; 19                                              ; 6                             ;
+; 20                                              ; 4                             ;
+; 21                                              ; 1                             ;
+; 22                                              ; 2                             ;
+; 23                                              ; 0                             ;
+; 24                                              ; 3                             ;
+; 25                                              ; 2                             ;
+; 26                                              ; 0                             ;
+; 27                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 18.51) ; Number of LABs  (Total = 756) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 1                             ;
+; 2                                            ; 22                            ;
+; 3                                            ; 24                            ;
+; 4                                            ; 30                            ;
+; 5                                            ; 15                            ;
+; 6                                            ; 15                            ;
+; 7                                            ; 23                            ;
+; 8                                            ; 16                            ;
+; 9                                            ; 20                            ;
+; 10                                           ; 17                            ;
+; 11                                           ; 19                            ;
+; 12                                           ; 16                            ;
+; 13                                           ; 20                            ;
+; 14                                           ; 18                            ;
+; 15                                           ; 17                            ;
+; 16                                           ; 19                            ;
+; 17                                           ; 34                            ;
+; 18                                           ; 26                            ;
+; 19                                           ; 19                            ;
+; 20                                           ; 27                            ;
+; 21                                           ; 33                            ;
+; 22                                           ; 35                            ;
+; 23                                           ; 33                            ;
+; 24                                           ; 33                            ;
+; 25                                           ; 30                            ;
+; 26                                           ; 30                            ;
+; 27                                           ; 21                            ;
+; 28                                           ; 15                            ;
+; 29                                           ; 16                            ;
+; 30                                           ; 26                            ;
+; 31                                           ; 28                            ;
+; 32                                           ; 29                            ;
+; 33                                           ; 25                            ;
+; 34                                           ; 4                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 17    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 13    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 295       ; 121          ; 295       ; 0            ; 0            ; 295       ; 295       ; 0            ; 295       ; 295       ; 168          ; 3            ; 0            ; 0            ; 183          ; 168          ; 3            ; 183          ; 0            ; 0            ; 11           ; 3            ; 171          ; 0            ; 0            ; 0            ; 0            ; 295       ; 0            ; 0            ;
+; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 0         ; 174          ; 0         ; 295          ; 295          ; 0         ; 0         ; 295          ; 0         ; 0         ; 127          ; 292          ; 295          ; 295          ; 112          ; 127          ; 292          ; 112          ; 295          ; 295          ; 284          ; 292          ; 124          ; 295          ; 295          ; 295          ; 295          ; 0         ; 295          ; 295          ;
+; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; CLK24M576          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_STR             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_BURST          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nACSI_DRQ          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nACSI_INT          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_DRQ          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_MSG          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nDCHG              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_DATA0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_DATA1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_DATA2           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_CARD_DEDECT     ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_WP              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nDACK0             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; WP_CF_CARD         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_C_D          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_I_O          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_CS3            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK25M             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nACSI_ACK          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nACSI_RESET        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nACSI_CS           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_DIR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_A1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_ACK          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_ATN          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_DIR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; MIDI_OLR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; MIDI_TLR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; TxD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; RTS                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DTR                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; AMKB_TX            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IDE_RES            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIDE_CS0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIDE_CS1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIDE_WR            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIDE_RD            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nCF_CS0            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nCF_CS1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nROM3              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nROM4              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nRP_UDS            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nRP_LDS            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSDSEL             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nWR_GATE           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nWR                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; YM_QA              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; YM_QB              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; YM_QC              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_CLK             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DSA_D              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nVWE               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nVCAS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nVRAS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nVCS               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nPD_VGA            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; TIN0               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSRCS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSRBLE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSRBHE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSRWE              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nDREQ1             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LED_FPGA_OK        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSROE              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VCKE               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_TA             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nDDR_CLK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DDR_CLK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VSYNC_PAD          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HSYNC_PAD          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nBLANK_PAD         ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PIXEL_CLK_PAD      ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSYNC              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nMOT_ON            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSTEP_DIR          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSTEP              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLKUSB             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LPDIR              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BA[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BA[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nIRQ[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[12]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[11]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[10]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VA[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VB[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDM[3]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDM[2]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDM[1]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDM[0]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VG[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VR[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; TOUT0              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nMASTER            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[31]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[30]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[29]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[28]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[27]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[26]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[25]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[24]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[23]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[22]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[21]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[20]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[19]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[18]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[17]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[16]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[15]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[14]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[13]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[12]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[11]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[10]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[9]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[8]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[7]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[6]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[5]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[4]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[3]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[2]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[1]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_AD[0]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[31]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[30]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[29]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[28]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[27]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[26]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[25]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[24]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[23]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[22]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[21]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[20]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[19]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[18]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[17]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[16]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[15]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[14]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[13]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[12]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[11]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[10]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[9]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[8]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VD[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDQS[3]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDQS[2]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDQS[1]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VDQS[0]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[17]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[16]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[15]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[14]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[13]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[12]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[11]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[10]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IO[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[15]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[14]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[13]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[12]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[11]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[10]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[9]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[8]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[7]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[6]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[5]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[4]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SRD[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_PAR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_SEL          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_BUSY         ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nSCSI_RST          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_CD_DATA3        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SD_CMD_D1          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; ACSI_D[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[7]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[6]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[5]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[4]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[3]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[2]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[1]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_D[0]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SCSI_D[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nRSTO_MCF          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_WR             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_CS1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_SIZE1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_SIZE0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; FB_ALE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_CS2            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; MAIN_CLK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nDACK1             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nFB_OE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IDE_RDY            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLK33M             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HD_DD              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nINDEX             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; RxD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nWP                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LP_BUSY            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DCD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CTS                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; TRACK00            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; IDE_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; RI                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nPCI_INTD          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nPCI_INTC          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nPCI_INTB          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nPCI_INTA          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DVI_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; E0_INT             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PIC_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PIC_AMKB_RX        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; MIDI_IN            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; nRD_DATA           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; AMKB_RX            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options                                                   ;
++----------------------------------------------+--------------------------+
+; Option                                       ; Setting                  ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)          ; On                       ;
+; Enable device-wide output enable (DEV_OE)    ; On                       ;
+; Enable INIT_DONE output                      ; Off                      ;
+; Configuration scheme                         ; Passive Serial           ;
+; Error detection CRC                          ; Off                      ;
+; Enable Open Drain on CRC Error pin           ; Off                      ;
+; Configuration Voltage Level                  ; Auto                     ;
+; Force Configuration Voltage Level            ; On                       ;
+; nCEO                                         ; As output driving ground ;
+; Data[0]                                      ; As input tri-stated      ;
+; Data[1]/ASDO                                 ; As input tri-stated      ;
+; Data[7..2]                                   ; Unreserved               ;
+; FLASH_nCE/nCSO                               ; As input tri-stated      ;
+; Other Active Parallel pins                   ; Unreserved               ;
+; DCLK                                         ; As input tri-stated      ;
+; Base pin-out file on sameframe device        ; Off                      ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing                                                                                                                                                                                                                                                                                                                     ;
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Clock(s)                                                                                                                                                   ; Destination Clock(s)                                                                                                                                              ; Delay Added in ns ;
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; I/O                                                                                                                                                               ; MAIN_CLK                                                                                                                                                          ; 245.886           ;
+; MAIN_CLK                                                                                                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 444.109           ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 1092.93           ;
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Wed Dec 15 02:21:57 2010
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
+Info: Selected device EP3C40F484C6 for design "firebee1"
+Info: Core supply voltage is 1.2V
+Info: Low junction temperature is 0 degrees C
+Info: High junction temperature is 85 degrees C
+Info: Implemented PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" as Cyclone III PLL type
+    Info: Implementing clock multiplication of 1, clock division of 66, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] port
+    Info: Implementing clock multiplication of 67, clock division of 900, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] port
+    Info: Implementing clock multiplication of 67, clock division of 90, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] port
+Info: None of the inputs fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input
+    Info: Input "nRD_DATA" that is fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input
+Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings
+    Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109
+    Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75
+    Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port
+    Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port
+    Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port
+    Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port
+Info: None of the inputs fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input
+    Info: Input "MAIN_CLK" that is fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input
+Info: Implemented PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" as Cyclone III PLL type
+    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 240 degrees (5051 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] port
+    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] port
+    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 180 degrees (3788 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] port
+    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 105 degrees (2210 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] port
+    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 270 degrees (11364 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] port
+Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type
+    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port
+Critical Warning: The input clock frequency specification of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is different from the output clock frequency specification of the source PLLs that are driving it
+    Critical Warning: Input port inclk[0] of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" and its source clk[3] (the output port of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1") have different specified frequencies, 48.0 MHz and 48.0 MHz respectively
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info: Device EP3C16F484C6 is compatible
+    Info: Device EP3C55F484C6 is compatible
+    Info: Device EP3C80F484C6 is compatible
+Info: Fitter converted 7 user pins into dedicated programming pins
+    Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info: Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info: Pin ~ALTERA_DATA0~ is reserved at location K1
+    Info: Pin ~ALTERA_DEV_OE~ is reserved at location N22
+    Info: Pin ~ALTERA_DEV_CLRn~ is reserved at location N21
+    Info: Pin ~ALTERA_nCEO~ is reserved at location K22
+Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Warning: The parameters of the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 and the PLL altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged
+    Info: The values of the parameter "M" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "M" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 67
+        Info: The value of the parameter "M" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 109
+    Info: The values of the parameter "N" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "N" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 6
+        Info: The value of the parameter "N" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 3
+    Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 12000
+        Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 10000
+    Info: The values of the parameter "VCO POST SCALE" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 2
+        Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1
+    Info: The values of the parameter "Min VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Min VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538
+        Info: The value of the parameter "Min VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769
+    Info: The values of the parameter "Max VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Max VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 3333
+        Info: The value of the parameter "Max VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1666
+    Info: The values of the parameter "Center VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Center VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538
+        Info: The value of the parameter "Center VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769
+    Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Min Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 17174
+        Info: The value of the parameter "Min Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 27940
+    Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Max Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 30864
+        Info: The value of the parameter "Max Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 59523
+    Info: The values of the parameter "Compensate Clock" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
+        Info: The value of the parameter "Compensate Clock" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is clock0
+        Info: The value of the parameter "Compensate Clock" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is clock1
+Warning: The input ports of the PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 and the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 are mismatched, preventing the PLLs to be merged
+    Warning: Input clock frequency of PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 differs from input clock frequency of PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1
+Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings
+    Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109
+    Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75
+    Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port
+    Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port
+    Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port
+    Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port
+Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type
+    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port
+Critical Warning: Input pin "CLK33M" feeds inclk port of PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" by global clock - I/O timing will be affected
+Info: Timing-driven compilation is using the Classic Timing Analyzer
+Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
+Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] (placed in counter C1 of PLL_3)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14
+Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] (placed in counter C2 of PLL_3)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12
+Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] (placed in counter C3 of PLL_3)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G13
+Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] (placed in counter C0 of PLL_1)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] (placed in counter C3 of PLL_1)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
+Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] (placed in counter C2 of PLL_1)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0
+Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] (placed in counter C4 of PLL_1)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
+Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] (placed in counter C1 of PLL_1)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
+Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] (placed in counter C1 of PLL_4)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16
+Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] (placed in counter C2 of PLL_4)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17
+Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] (placed in counter C3 of PLL_4)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
+Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] (placed in counter C4 of PLL_4)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info: Automatically promoted node altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info: Automatically promoted node CLK33M~input (placed in PIN AB12 (CLK12, DIFFCLK_7n))
+    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15
+    Info: Following destination nodes may be non-global or may not use global or regional clocks
+        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0
+        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3
+        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M
+Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+    Info: Following destination nodes may be non-global or may not use global or regional clocks
+        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC
+        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC
+Info: Automatically promoted node inst25 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+    Info: Following destination nodes may be non-global or may not use global or regional clocks
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_WR~reg0
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[10]
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[14]
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[15]
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[12]
+        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[13]
+        Info: Non-global destination nodes limited to 10 nodes
+Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+    Info: Following destination nodes may be non-global or may not use global or regional clocks
+        Info: Destination node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
+Info: Automatically promoted node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+    Info: Following destination nodes may be non-global or may not use global or regional clocks
+        Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|_~0
+        Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0
+Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 
+    Info: Automatically promoted destinations to use location or clock signal Global Clock
+Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "VD[31]~input" is constrained to location IOIBUF_X43_Y0_N1 to improve DDIO timing
+    Info: Node "VD[31]" is constrained to location PIN U12 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
+    Info: Node "VD[30]~input" is constrained to location IOIBUF_X41_Y0_N29 to improve DDIO timing
+    Info: Node "VD[30]" is constrained to location PIN V12 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "VD[29]~input" is constrained to location IOIBUF_X38_Y0_N22 to improve DDIO timing
+    Info: Node "VD[29]" is constrained to location PIN AB13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "VD[28]~input" is constrained to location IOIBUF_X43_Y0_N29 to improve DDIO timing
+    Info: Node "VD[28]" is constrained to location PIN W13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "VD[27]~input" is constrained to location IOIBUF_X48_Y0_N29 to improve DDIO timing
+    Info: Node "VD[27]" is constrained to location PIN V13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "VD[26]~input" is constrained to location IOIBUF_X38_Y0_N8 to improve DDIO timing
+    Info: Node "VD[26]" is constrained to location PIN AB14 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "VD[25]~input" is constrained to location IOIBUF_X38_Y0_N15 to improve DDIO timing
+    Info: Node "VD[25]" is constrained to location PIN AA14 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "VD[24]~input" is constrained to location IOIBUF_X43_Y0_N8 to improve DDIO timing
+    Info: Node "VD[24]" is constrained to location PIN AB15 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "VD[23]~input" is constrained to location IOIBUF_X45_Y0_N15 to improve DDIO timing
+    Info: Node "VD[23]" is constrained to location PIN AB16 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
+    Info: Node "VD[22]~input" is constrained to location IOIBUF_X48_Y0_N22 to improve DDIO timing
+    Info: Node "VD[22]" is constrained to location PIN W14 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "VD[21]~input" is constrained to location IOIBUF_X50_Y0_N1 to improve DDIO timing
+    Info: Node "VD[21]" is constrained to location PIN V15 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "VD[20]~input" is constrained to location IOIBUF_X50_Y0_N29 to improve DDIO timing
+    Info: Node "VD[20]" is constrained to location PIN U13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
+    Info: Node "VD[19]~input" is constrained to location IOIBUF_X50_Y0_N22 to improve DDIO timing
+    Info: Node "VD[19]" is constrained to location PIN V14 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
+    Info: Node "VD[18]~input" is constrained to location IOIBUF_X38_Y0_N29 to improve DDIO timing
+    Info: Node "VD[18]" is constrained to location PIN AA13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
+    Info: Node "VD[17]~input" is constrained to location IOIBUF_X43_Y0_N22 to improve DDIO timing
+    Info: Node "VD[17]" is constrained to location PIN Y13 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
+    Info: Node "VD[16]~input" is constrained to location IOIBUF_X45_Y0_N8 to improve DDIO timing
+    Info: Node "VD[16]" is constrained to location PIN T12 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
+    Info: Node "VD[15]~input" is constrained to location IOIBUF_X67_Y15_N8 to improve DDIO timing
+    Info: Node "VD[15]" is constrained to location PIN N20 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "VD[14]~input" is constrained to location IOIBUF_X67_Y13_N8 to improve DDIO timing
+    Info: Node "VD[14]" is constrained to location PIN R22 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "VD[13]~input" is constrained to location IOIBUF_X67_Y14_N22 to improve DDIO timing
+    Info: Node "VD[13]" is constrained to location PIN P20 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
+    Info: Node "VD[12]~input" is constrained to location IOIBUF_X67_Y17_N22 to improve DDIO timing
+    Info: Node "VD[12]" is constrained to location PIN N17 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
+    Info: Node "VD[11]~input" is constrained to location IOIBUF_X67_Y13_N1 to improve DDIO timing
+    Info: Node "VD[11]" is constrained to location PIN R21 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "VD[10]~input" is constrained to location IOIBUF_X67_Y10_N15 to improve DDIO timing
+    Info: Node "VD[10]" is constrained to location PIN P17 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "VD[9]~input" is constrained to location IOIBUF_X67_Y12_N22 to improve DDIO timing
+    Info: Node "VD[9]" is constrained to location PIN R18 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "VD[8]~input" is constrained to location IOIBUF_X67_Y10_N8 to improve DDIO timing
+    Info: Node "VD[8]" is constrained to location PIN V22 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "VD[7]~input" is constrained to location IOIBUF_X67_Y11_N1 to improve DDIO timing
+    Info: Node "VD[7]" is constrained to location PIN U21 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
+    Info: Node "VD[6]~input" is constrained to location IOIBUF_X67_Y12_N15 to improve DDIO timing
+    Info: Node "VD[6]" is constrained to location PIN R19 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
+    Info: Node "VD[5]~input" is constrained to location IOIBUF_X67_Y10_N22 to improve DDIO timing
+    Info: Node "VD[5]" is constrained to location PIN R17 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "VD[4]~input" is constrained to location IOIBUF_X67_Y14_N1 to improve DDIO timing
+    Info: Node "VD[4]" is constrained to location PIN P21 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
+    Info: Node "VD[3]~input" is constrained to location IOIBUF_X67_Y11_N22 to improve DDIO timing
+    Info: Node "VD[3]" is constrained to location PIN R20 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
+    Info: Node "VD[2]~input" is constrained to location IOIBUF_X67_Y14_N8 to improve DDIO timing
+    Info: Node "VD[2]" is constrained to location PIN P22 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "VD[1]~input" is constrained to location IOIBUF_X67_Y18_N1 to improve DDIO timing
+    Info: Node "VD[1]" is constrained to location PIN M21 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
+    Info: Node "VD[0]~input" is constrained to location IOIBUF_X67_Y18_N8 to improve DDIO timing
+    Info: Node "VD[0]" is constrained to location PIN M22 to improve DDIO timing
+Info: Starting register packing
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] to I/O pin
+    Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] and I/O node MAIN_CLK -- I/O node is a dedicated I/O pin
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
+Info: Finished register packing
+    Extra Info: Packed 33 registers into blocks of type I/O Input Buffer
+    Extra Info: Packed 25 registers into blocks of type I/O Output Buffer
+    Extra Info: Created 9 register duplicates
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
+    Info: Input port INCLK[0] of node "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" is driven by CLK33M~inputclkctrl which is OUTCLK output port of Clock control block type node CLK33M~inputclkctrl
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" output port clk[2] feeds output pin "CLK24M576~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[2] feeds output pin "CLK25M~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[3] feeds output pin "CLKUSB~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[3]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[2]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "nDDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "DDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
+    Info: Input port INCLK[0] of node "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is driven by altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl
+Info: Starting physical synthesis optimizations for speed
+Info: Starting physical synthesis algorithm combinational resynthesis using boolean division
+Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2208 ps
+Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:23
+Info: Fitter preparation operations ending: elapsed time is 00:00:47
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:18
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:01:10
+Info: Starting physical synthesis optimizations for speed
+Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:05
+Info: Estimated most critical path is register to pin delay of 5.130 ns
+    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12_N0; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[9]'
+    Info: 2: + IC(0.161 ns) + CELL(0.369 ns) = 0.530 ns; Loc. = LAB_X16_Y12_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15'
+    Info: 3: + IC(0.528 ns) + CELL(0.243 ns) = 1.301 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359'
+    Info: 4: + IC(0.172 ns) + CELL(0.130 ns) = 1.603 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~360'
+    Info: 5: + IC(1.521 ns) + CELL(2.006 ns) = 5.130 ns; Loc. = IOOBUF_X34_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[29]~output'
+    Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 5.130 ns; Loc. = PIN_W10; Fanout = 0; PIN Node = 'FB_AD[29]'
+    Info: Total cell delay = 2.748 ns ( 53.57 % )
+    Info: Total interconnect delay = 2.382 ns ( 46.43 % )
+Info: Fitter routing operations beginning
+Info: 2 (of 32134) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Fitter report for a summary of the relevant clock transfers. Also, check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks.
+Info: Average interconnect usage is 13% of the available device resources
+    Info: Peak interconnect usage is 51% of the available device resources in the region that extends from location X22_Y11 to location X33_Y21
+Info: Fitter routing operations ending: elapsed time is 00:01:18
+Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info: Optimizations that may affect the design's routability were skipped
+Info: Started post-fitting delay annotation
+Info: Delay annotation completed successfully
+Info: Auto delay chain can't change the delay chain setting on I/O pin nRD_DATA since it's a PLL compensated pin
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register
+Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning: Total number of single-ended output or bi-directional pins in bank 4 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
+    Info: There are 32 output pin(s) with I/O standard 2.5 V and current strength 12mA
+        Info: Location AA13 (pad PAD_208): Pin VD[18] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AB13 (pad PAD_209): Pin VD[29] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AA14 (pad PAD_210): Pin VD[25] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AB14 (pad PAD_211): Pin VD[26] of type bi-directional uses 2.5 V I/O standard
+        Info: Location V12 (pad PAD_213): Pin VD[30] of type bi-directional uses 2.5 V I/O standard
+        Info: Location W13 (pad PAD_218): Pin VD[28] of type bi-directional uses 2.5 V I/O standard
+        Info: Location Y13 (pad PAD_219): Pin VD[17] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AA15 (pad PAD_220): Pin VDQS[0] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AB15 (pad PAD_221): Pin VD[24] of type bi-directional uses 2.5 V I/O standard
+        Info: Location U12 (pad PAD_222): Pin VD[31] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AA16 (pad PAD_224): Pin VDM[0] of type output uses 2.5 V I/O standard
+        Info: Location AB16 (pad PAD_225): Pin VD[23] of type bi-directional uses 2.5 V I/O standard
+        Info: Location T12 (pad PAD_226): Pin VD[16] of type bi-directional uses 2.5 V I/O standard
+        Info: Location V13 (pad PAD_228): Pin VD[27] of type bi-directional uses 2.5 V I/O standard
+        Info: Location W14 (pad PAD_229): Pin VD[22] of type bi-directional uses 2.5 V I/O standard
+        Info: Location U13 (pad PAD_233): Pin VD[20] of type bi-directional uses 2.5 V I/O standard
+        Info: Location V14 (pad PAD_234): Pin VD[19] of type bi-directional uses 2.5 V I/O standard
+        Info: Location U15 (pad PAD_236): Pin VCKE of type output uses 2.5 V I/O standard
+        Info: Location V15 (pad PAD_237): Pin VD[21] of type bi-directional uses 2.5 V I/O standard
+        Info: Location W15 (pad PAD_239): Pin VDQS[1] of type bi-directional uses 2.5 V I/O standard
+        Info: Location AB18 (pad PAD_242): Pin nVCAS of type output uses 2.5 V I/O standard
+        Info: Location AA17 (pad PAD_243): Pin nDDR_CLK of type output uses 2.5 V I/O standard
+        Info: Location AB17 (pad PAD_244): Pin DDR_CLK of type output uses 2.5 V I/O standard
+        Info: Location AA18 (pad PAD_245): Pin VA[12] of type output uses 2.5 V I/O standard
+        Info: Location AA19 (pad PAD_252): Pin BA[1] of type output uses 2.5 V I/O standard
+        Info: Location AB19 (pad PAD_253): Pin VA[9] of type output uses 2.5 V I/O standard
+        Info: Location W17 (pad PAD_257): Pin nVRAS of type output uses 2.5 V I/O standard
+        Info: Location Y17 (pad PAD_258): Pin nVWE of type output uses 2.5 V I/O standard
+        Info: Location AA20 (pad PAD_259): Pin VA[7] of type output uses 2.5 V I/O standard
+        Info: Location AB20 (pad PAD_260): Pin VA[8] of type output uses 2.5 V I/O standard
+        Info: Location V16 (pad PAD_261): Pin VDM[1] of type output uses 2.5 V I/O standard
+        Info: Location T16 (pad PAD_266): Pin VDQS[3] of type bi-directional uses 2.5 V I/O standard
+Warning: Total number of single-ended output or bi-directional pins in bank 5 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
+    Info: There are 30 output pin(s) with I/O standard 2.5 V and current strength 12mA
+        Info: Location AA22 (pad PAD_273): Pin VA[4] of type output uses 2.5 V I/O standard
+        Info: Location AA21 (pad PAD_274): Pin VA[6] of type output uses 2.5 V I/O standard
+        Info: Location T17 (pad PAD_277): Pin VDM[3] of type output uses 2.5 V I/O standard
+        Info: Location T18 (pad PAD_278): Pin nVCS of type output uses 2.5 V I/O standard
+        Info: Location W20 (pad PAD_280): Pin VA[0] of type output uses 2.5 V I/O standard
+        Info: Location W19 (pad PAD_285): Pin BA[0] of type output uses 2.5 V I/O standard
+        Info: Location Y22 (pad PAD_288): Pin VA[3] of type output uses 2.5 V I/O standard
+        Info: Location Y21 (pad PAD_289): Pin VA[5] of type output uses 2.5 V I/O standard
+        Info: Location U20 (pad PAD_290): Pin VDM[2] of type output uses 2.5 V I/O standard
+        Info: Location U19 (pad PAD_291): Pin VA[11] of type output uses 2.5 V I/O standard
+        Info: Location W22 (pad PAD_292): Pin VA[1] of type output uses 2.5 V I/O standard
+        Info: Location W21 (pad PAD_293): Pin VA[2] of type output uses 2.5 V I/O standard
+        Info: Location R17 (pad PAD_301): Pin VD[5] of type bi-directional uses 2.5 V I/O standard
+        Info: Location P17 (pad PAD_302): Pin VD[10] of type bi-directional uses 2.5 V I/O standard
+        Info: Location V22 (pad PAD_303): Pin VD[8] of type bi-directional uses 2.5 V I/O standard
+        Info: Location V21 (pad PAD_304): Pin VA[10] of type output uses 2.5 V I/O standard
+        Info: Location R20 (pad PAD_305): Pin VD[3] of type bi-directional uses 2.5 V I/O standard
+        Info: Location U22 (pad PAD_307): Pin VDQS[2] of type bi-directional uses 2.5 V I/O standard
+        Info: Location U21 (pad PAD_308): Pin VD[7] of type bi-directional uses 2.5 V I/O standard
+        Info: Location R18 (pad PAD_309): Pin VD[9] of type bi-directional uses 2.5 V I/O standard
+        Info: Location R19 (pad PAD_310): Pin VD[6] of type bi-directional uses 2.5 V I/O standard
+        Info: Location R22 (pad PAD_315): Pin VD[14] of type bi-directional uses 2.5 V I/O standard
+        Info: Location R21 (pad PAD_316): Pin VD[11] of type bi-directional uses 2.5 V I/O standard
+        Info: Location P20 (pad PAD_317): Pin VD[13] of type bi-directional uses 2.5 V I/O standard
+        Info: Location P22 (pad PAD_319): Pin VD[2] of type bi-directional uses 2.5 V I/O standard
+        Info: Location P21 (pad PAD_320): Pin VD[4] of type bi-directional uses 2.5 V I/O standard
+        Info: Location N20 (pad PAD_323): Pin VD[15] of type bi-directional uses 2.5 V I/O standard
+        Info: Location N17 (pad PAD_329): Pin VD[12] of type bi-directional uses 2.5 V I/O standard
+        Info: Location M22 (pad PAD_333): Pin VD[0] of type bi-directional uses 2.5 V I/O standard
+        Info: Location M21 (pad PAD_334): Pin VD[1] of type bi-directional uses 2.5 V I/O standard
+Warning: 145 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone&nbsp;III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
+    Info: Pin nFB_BURST uses I/O standard 3.3-V LVTTL at T3
+    Info: Pin nACSI_DRQ uses I/O standard 3.3-V LVTTL at K7
+    Info: Pin nACSI_INT uses I/O standard 3.3-V LVTTL at J4
+    Info: Pin nSCSI_DRQ uses I/O standard 3.3-V LVTTL at U1
+    Info: Pin nSCSI_MSG uses I/O standard 3.3-V LVTTL at H2
+    Info: Pin nDCHG uses I/O standard 3.3-V LVTTL at C17
+    Info: Pin SD_DATA0 uses I/O standard 3.3-V LVTTL at B16
+    Info: Pin SD_DATA1 uses I/O standard 3.3-V LVTTL at A16
+    Info: Pin SD_DATA2 uses I/O standard 3.3-V LVTTL at B17
+    Info: Pin SD_CARD_DEDECT uses I/O standard 3.3-V LVTTL at M20
+    Info: Pin SD_WP uses I/O standard 3.3-V LVTTL at M19
+    Info: Pin nDACK0 uses I/O standard 3.3-V LVTTL at B12
+    Info: Pin WP_CF_CARD uses I/O standard 3.3-V LVTTL at T1
+    Info: Pin nSCSI_C_D uses I/O standard 3.3-V LVTTL at H1
+    Info: Pin nSCSI_I_O uses I/O standard 3.3-V LVTTL at J3
+    Info: Pin nFB_CS3 uses I/O standard 3.3-V LVTTL at V6
+    Info: Pin TOUT0 uses I/O standard 3.3-V LVTTL at T22
+    Info: Pin nMASTER uses I/O standard 3.3-V LVTTL at T21
+    Info: Pin FB_AD[31] uses I/O standard 3.3-V LVTTL at AA10
+    Info: Pin FB_AD[30] uses I/O standard 3.3-V LVTTL at Y10
+    Info: Pin FB_AD[29] uses I/O standard 3.3-V LVTTL at W10
+    Info: Pin FB_AD[28] uses I/O standard 3.3-V LVTTL at V11
+    Info: Pin FB_AD[27] uses I/O standard 3.3-V LVTTL at U11
+    Info: Pin FB_AD[26] uses I/O standard 3.3-V LVTTL at AB9
+    Info: Pin FB_AD[25] uses I/O standard 3.3-V LVTTL at AA9
+    Info: Pin FB_AD[24] uses I/O standard 3.3-V LVTTL at T11
+    Info: Pin FB_AD[23] uses I/O standard 3.3-V LVTTL at AB8
+    Info: Pin FB_AD[22] uses I/O standard 3.3-V LVTTL at AA8
+    Info: Pin FB_AD[21] uses I/O standard 3.3-V LVTTL at U10
+    Info: Pin FB_AD[20] uses I/O standard 3.3-V LVTTL at T10
+    Info: Pin FB_AD[19] uses I/O standard 3.3-V LVTTL at V10
+    Info: Pin FB_AD[18] uses I/O standard 3.3-V LVTTL at V9
+    Info: Pin FB_AD[17] uses I/O standard 3.3-V LVTTL at Y8
+    Info: Pin FB_AD[16] uses I/O standard 3.3-V LVTTL at AB7
+    Info: Pin FB_AD[15] uses I/O standard 3.3-V LVTTL at AA7
+    Info: Pin FB_AD[14] uses I/O standard 3.3-V LVTTL at W8
+    Info: Pin FB_AD[13] uses I/O standard 3.3-V LVTTL at V8
+    Info: Pin FB_AD[12] uses I/O standard 3.3-V LVTTL at U9
+    Info: Pin FB_AD[11] uses I/O standard 3.3-V LVTTL at Y7
+    Info: Pin FB_AD[10] uses I/O standard 3.3-V LVTTL at W7
+    Info: Pin FB_AD[9] uses I/O standard 3.3-V LVTTL at AB5
+    Info: Pin FB_AD[8] uses I/O standard 3.3-V LVTTL at AA5
+    Info: Pin FB_AD[7] uses I/O standard 3.3-V LVTTL at AB4
+    Info: Pin FB_AD[6] uses I/O standard 3.3-V LVTTL at AA4
+    Info: Pin FB_AD[5] uses I/O standard 3.3-V LVTTL at V7
+    Info: Pin FB_AD[4] uses I/O standard 3.3-V LVTTL at W6
+    Info: Pin FB_AD[3] uses I/O standard 3.3-V LVTTL at AB3
+    Info: Pin FB_AD[2] uses I/O standard 3.3-V LVTTL at AA3
+    Info: Pin FB_AD[1] uses I/O standard 3.3-V LVTTL at Y6
+    Info: Pin FB_AD[0] uses I/O standard 3.3-V LVTTL at Y3
+    Info: Pin IO[17] uses I/O standard 3.3-V LVTTL at B13
+    Info: Pin IO[16] uses I/O standard 3.3-V LVTTL at A13
+    Info: Pin IO[15] uses I/O standard 3.3-V LVTTL at B14
+    Info: Pin IO[14] uses I/O standard 3.3-V LVTTL at A14
+    Info: Pin IO[13] uses I/O standard 3.3-V LVTTL at E13
+    Info: Pin IO[12] uses I/O standard 3.3-V LVTTL at D13
+    Info: Pin IO[11] uses I/O standard 3.3-V LVTTL at C13
+    Info: Pin IO[10] uses I/O standard 3.3-V LVTTL at B15
+    Info: Pin IO[9] uses I/O standard 3.3-V LVTTL at A15
+    Info: Pin IO[8] uses I/O standard 3.3-V LVTTL at G10
+    Info: Pin IO[7] uses I/O standard 3.3-V LVTTL at C7
+    Info: Pin IO[6] uses I/O standard 3.3-V LVTTL at C8
+    Info: Pin IO[5] uses I/O standard 3.3-V LVTTL at E9
+    Info: Pin IO[4] uses I/O standard 3.3-V LVTTL at B6
+    Info: Pin IO[3] uses I/O standard 3.3-V LVTTL at A6
+    Info: Pin IO[2] uses I/O standard 3.3-V LVTTL at B7
+    Info: Pin IO[1] uses I/O standard 3.3-V LVTTL at A7
+    Info: Pin IO[0] uses I/O standard 3.3-V LVTTL at A8
+    Info: Pin SRD[15] uses I/O standard 3.3-V LVTTL at H10
+    Info: Pin SRD[14] uses I/O standard 3.3-V LVTTL at G9
+    Info: Pin SRD[13] uses I/O standard 3.3-V LVTTL at F10
+    Info: Pin SRD[12] uses I/O standard 3.3-V LVTTL at D10
+    Info: Pin SRD[11] uses I/O standard 3.3-V LVTTL at B10
+    Info: Pin SRD[10] uses I/O standard 3.3-V LVTTL at A9
+    Info: Pin SRD[9] uses I/O standard 3.3-V LVTTL at A10
+    Info: Pin SRD[8] uses I/O standard 3.3-V LVTTL at B9
+    Info: Pin SRD[7] uses I/O standard 3.3-V LVTTL at H11
+    Info: Pin SRD[6] uses I/O standard 3.3-V LVTTL at E10
+    Info: Pin SRD[5] uses I/O standard 3.3-V LVTTL at F9
+    Info: Pin SRD[4] uses I/O standard 3.3-V LVTTL at C10
+    Info: Pin SRD[3] uses I/O standard 3.3-V LVTTL at G11
+    Info: Pin SRD[2] uses I/O standard 3.3-V LVTTL at C6
+    Info: Pin SRD[1] uses I/O standard 3.3-V LVTTL at A5
+    Info: Pin SRD[0] uses I/O standard 3.3-V LVTTL at B5
+    Info: Pin SCSI_PAR uses I/O standard 3.3-V LVTTL at M7
+    Info: Pin nSCSI_SEL uses I/O standard 3.3-V LVTTL at M8
+    Info: Pin nSCSI_BUSY uses I/O standard 3.3-V LVTTL at N8
+    Info: Pin nSCSI_RST uses I/O standard 3.3-V LVTTL at N6
+    Info: Pin SD_CD_DATA3 uses I/O standard 3.3-V LVTTL at F13
+    Info: Pin SD_CMD_D1 uses I/O standard 3.3-V LVTTL at E14
+    Info: Pin ACSI_D[7] uses I/O standard 3.3-V LVTTL at H6
+    Info: Pin ACSI_D[6] uses I/O standard 3.3-V LVTTL at H7
+    Info: Pin ACSI_D[5] uses I/O standard 3.3-V LVTTL at D2
+    Info: Pin ACSI_D[4] uses I/O standard 3.3-V LVTTL at C1
+    Info: Pin ACSI_D[3] uses I/O standard 3.3-V LVTTL at C2
+    Info: Pin ACSI_D[2] uses I/O standard 3.3-V LVTTL at E3
+    Info: Pin ACSI_D[1] uses I/O standard 3.3-V LVTTL at G5
+    Info: Pin ACSI_D[0] uses I/O standard 3.3-V LVTTL at B1
+    Info: Pin LP_D[7] uses I/O standard 3.3-V LVTTL at G8
+    Info: Pin LP_D[6] uses I/O standard 3.3-V LVTTL at A3
+    Info: Pin LP_D[5] uses I/O standard 3.3-V LVTTL at B3
+    Info: Pin LP_D[4] uses I/O standard 3.3-V LVTTL at D6
+    Info: Pin LP_D[3] uses I/O standard 3.3-V LVTTL at E7
+    Info: Pin LP_D[2] uses I/O standard 3.3-V LVTTL at C3
+    Info: Pin LP_D[1] uses I/O standard 3.3-V LVTTL at C4
+    Info: Pin LP_D[0] uses I/O standard 3.3-V LVTTL at F7
+    Info: Pin SCSI_D[7] uses I/O standard 3.3-V LVTTL at K8
+    Info: Pin SCSI_D[6] uses I/O standard 3.3-V LVTTL at L8
+    Info: Pin SCSI_D[5] uses I/O standard 3.3-V LVTTL at G3
+    Info: Pin SCSI_D[4] uses I/O standard 3.3-V LVTTL at G4
+    Info: Pin SCSI_D[3] uses I/O standard 3.3-V LVTTL at F1
+    Info: Pin SCSI_D[2] uses I/O standard 3.3-V LVTTL at F2
+    Info: Pin SCSI_D[1] uses I/O standard 3.3-V LVTTL at E1
+    Info: Pin SCSI_D[0] uses I/O standard 3.3-V LVTTL at J6
+    Info: Pin nRSTO_MCF uses I/O standard 3.3-V LVTTL at B11
+    Info: Pin nFB_WR uses I/O standard 3.3-V LVTTL at T5
+    Info: Pin nFB_CS1 uses I/O standard 3.3-V LVTTL at T8
+    Info: Pin FB_SIZE1 uses I/O standard 3.3-V LVTTL at Y4
+    Info: Pin FB_SIZE0 uses I/O standard 3.3-V LVTTL at U8
+    Info: Pin FB_ALE uses I/O standard 3.3-V LVTTL at R7
+    Info: Pin nFB_CS2 uses I/O standard 3.3-V LVTTL at T9
+    Info: Pin MAIN_CLK uses I/O standard 3.3-V LVTTL at G2
+    Info: Pin nDACK1 uses I/O standard 3.3-V LVTTL at A12
+    Info: Pin nFB_OE uses I/O standard 3.3-V LVTTL at R6
+    Info: Pin IDE_RDY uses I/O standard 3.3-V LVTTL at Y1
+    Info: Pin CLK33M uses I/O standard 3.3-V LVTTL at AB12
+    Info: Pin HD_DD uses I/O standard 3.3-V LVTTL at F16
+    Info: Pin nINDEX uses I/O standard 3.3-V LVTTL at E16
+    Info: Pin RxD uses I/O standard 3.3-V LVTTL at H15
+    Info: Pin nWP uses I/O standard 3.3-V LVTTL at D19
+    Info: Pin LP_BUSY uses I/O standard 3.3-V LVTTL at G7
+    Info: Pin DCD uses I/O standard 3.3-V LVTTL at A19
+    Info: Pin CTS uses I/O standard 3.3-V LVTTL at H14
+    Info: Pin TRACK00 uses I/O standard 3.3-V LVTTL at C19
+    Info: Pin RI uses I/O standard 3.3-V LVTTL at B19
+    Info: Pin nPCI_INTD uses I/O standard 3.3-V LVTTL at P6
+    Info: Pin nPCI_INTC uses I/O standard 3.3-V LVTTL at V3
+    Info: Pin nPCI_INTB uses I/O standard 3.3-V LVTTL at V4
+    Info: Pin nPCI_INTA uses I/O standard 3.3-V LVTTL at AA1
+    Info: Pin DVI_INT uses I/O standard 3.3-V LVTTL at A11
+    Info: Pin PIC_INT uses I/O standard 3.3-V LVTTL at AA2
+    Info: Pin PIC_AMKB_RX uses I/O standard 3.3-V LVTTL at L7
+    Info: Pin MIDI_IN uses I/O standard 3.3-V LVTTL at E12
+    Info: Pin nRD_DATA uses I/O standard 3.3-V LVTTL at A20
+    Info: Pin AMKB_RX uses I/O standard 3.3-V LVTTL at Y2
+Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info: Pin IO[17] has a permanently enabled output enable
+    Info: Pin IO[16] has a permanently enabled output enable
+    Info: Pin IO[15] has a permanently enabled output enable
+    Info: Pin IO[14] has a permanently enabled output enable
+    Info: Pin IO[13] has a permanently enabled output enable
+    Info: Pin IO[12] has a permanently enabled output enable
+    Info: Pin IO[11] has a permanently enabled output enable
+    Info: Pin IO[10] has a permanently enabled output enable
+    Info: Pin IO[9] has a permanently enabled output enable
+    Info: Pin IO[8] has a permanently enabled output enable
+    Info: Pin IO[7] has a permanently enabled output enable
+    Info: Pin IO[6] has a permanently enabled output enable
+    Info: Pin IO[5] has a permanently enabled output enable
+    Info: Pin IO[4] has a permanently enabled output enable
+    Info: Pin IO[3] has a permanently enabled output enable
+    Info: Pin IO[2] has a permanently enabled output enable
+    Info: Pin IO[1] has a permanently enabled output enable
+    Info: Pin IO[0] has a permanently enabled output enable
+    Info: Pin SCSI_PAR has a permanently disabled output enable
+    Info: Pin nSCSI_SEL has a permanently enabled output enable
+    Info: Pin nSCSI_BUSY has a permanently enabled output enable
+    Info: Pin nSCSI_RST has a permanently disabled output enable
+    Info: Pin SD_CD_DATA3 has a permanently disabled output enable
+    Info: Pin SD_CMD_D1 has a permanently disabled output enable
+    Info: Pin ACSI_D[7] has a permanently disabled output enable
+    Info: Pin ACSI_D[6] has a permanently disabled output enable
+    Info: Pin ACSI_D[5] has a permanently disabled output enable
+    Info: Pin ACSI_D[4] has a permanently disabled output enable
+    Info: Pin ACSI_D[3] has a permanently disabled output enable
+    Info: Pin ACSI_D[2] has a permanently disabled output enable
+    Info: Pin ACSI_D[1] has a permanently disabled output enable
+    Info: Pin ACSI_D[0] has a permanently disabled output enable
+    Info: Pin SCSI_D[7] has a permanently disabled output enable
+    Info: Pin SCSI_D[6] has a permanently disabled output enable
+    Info: Pin SCSI_D[5] has a permanently disabled output enable
+    Info: Pin SCSI_D[4] has a permanently disabled output enable
+    Info: Pin SCSI_D[3] has a permanently disabled output enable
+    Info: Pin SCSI_D[2] has a permanently disabled output enable
+    Info: Pin SCSI_D[1] has a permanently disabled output enable
+    Info: Pin SCSI_D[0] has a permanently disabled output enable
+Info: Quartus II Fitter was successful. 0 errors, 34 warnings
+    Info: Peak virtual memory: 334 megabytes
+    Info: Processing ended: Wed Dec 15 02:25:07 2010
+    Info: Elapsed time: 00:03:10
+    Info: Total CPU time (on all processors): 00:03:11
+
+
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
new file mode 100644
index 0000000..f177099
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Wed Dec 15 02:25:02 2010
+Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+Revision Name : firebee1
+Top-level Entity Name : firebee1
+Family : Cyclone III
+Device : EP3C40F484C6
+Timing Models : Final
+Total logic elements : 9,526 / 39,600 ( 24 % )
+    Total combinational functions : 8,061 / 39,600 ( 20 % )
+    Dedicated logic registers : 4,563 / 39,600 ( 12 % )
+Total registers : 4749
+Total pins : 295 / 332 ( 89 % )
+Total virtual pins : 0
+Total memory bits : 109,344 / 1,161,216 ( 9 % )
+Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % )
+Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.flow.rpt b/FPGA_by_Fredi/firebee1.flow.rpt
new file mode 100644
index 0000000..297d7a0
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.flow.rpt
@@ -0,0 +1,380 @@
+Flow report for firebee1
+Wed Dec 15 02:25:22 2010
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++------------------------------------+----------------------------------------------+
+; Flow Status                        ; Successful - Wed Dec 15 02:25:21 2010        ;
+; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name                      ; firebee1                                     ;
+; Top-level Entity Name              ; firebee1                                     ;
+; Family                             ; Cyclone III                                  ;
+; Device                             ; EP3C40F484C6                                 ;
+; Timing Models                      ; Final                                        ;
+; Met timing requirements            ; No                                           ;
+; Total logic elements               ; 9,526 / 39,600 ( 24 % )                      ;
+;     Total combinational functions  ; 8,061 / 39,600 ( 20 % )                      ;
+;     Dedicated logic registers      ; 4,563 / 39,600 ( 12 % )                      ;
+; Total registers                    ; 4749                                         ;
+; Total pins                         ; 295 / 332 ( 89 % )                           ;
+; Total virtual pins                 ; 0                                            ;
+; Total memory bits                  ; 109,344 / 1,161,216 ( 9 % )                  ;
+; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % )                              ;
+; Total PLLs                         ; 4 / 4 ( 100 % )                              ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 12/15/2010 02:20:37 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; firebee1            ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                            ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+; Assignment Name                         ; Value                              ; Default Value ; Entity Name ; Section Id     ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID                   ; 150661768621.129237603704664       ; --            ; --          ; --             ;
+; CYCLONEII_OPTIMIZATION_TECHNIQUE        ; Speed                              ; Balanced      ; --          ; --             ;
+; FMAX_REQUIREMENT                        ; 30 ns                              ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_LATCH                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_COMPARE                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_BIDIR                      ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL_RECONFIG                    ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP                  ; 85                                 ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP                  ; 0                                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; C:/firebee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter0.bsf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter0.cmp                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri1.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri1.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri2.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri2.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri4.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri4.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant0.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant0.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant2.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant2.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri6.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri6.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux3.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux3.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux4.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux4.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant3.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant3.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg1.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg1.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_latch1.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_latch1.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg2.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg2.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.bsf           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.inc           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.cmp           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.ppf           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.bsf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.inc                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.cmp                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.ppf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxDZ.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxDZ.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxVDM.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxVDM.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; C:/FireBee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.tdf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.inc               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.tdf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.ppf                        ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE             ; 1.2V                               ; --            ; --          ; --             ;
+; PARTITION_COLOR                         ; 16764057                           ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE                  ; SOURCE                             ; --            ; --          ; Top            ;
+; PHYSICAL_SYNTHESIS_COMBO_LOGIC          ; On                                 ; Off           ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On                                 ; Off           ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_EFFORT               ; Fast                               ; Normal        ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On                                 ; Off           ; --          ; --             ;
+; STATE_MACHINE_PROCESSING                ; One-Hot                            ; Auto          ; --          ; --             ;
+; TCO_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; TH_REQUIREMENT                          ; 1 ns                               ; --            ; --          ; --             ;
+; TPD_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; TSU_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS      ; Off                                ; --            ; --          ; eda_blast_fpga ;
+; USE_TIMEQUEST_TIMING_ANALYZER           ; Off                                ; On            ; --          ; --             ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                           ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis    ; 00:01:16     ; 1.0                     ; 347 MB              ; 00:01:17                           ;
+; Fitter                  ; 00:03:05     ; 1.0                     ; 334 MB              ; 00:03:07                           ;
+; Assembler               ; 00:00:05     ; 1.0                     ; 291 MB              ; 00:00:04                           ;
+; Classic Timing Analyzer ; 00:00:07     ; 1.0                     ; 227 MB              ; 00:00:09                           ;
+; Total                   ; 00:04:33     ; --                      ; --                  ; 00:04:37                           ;
++-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                          ;
++-------------------------+------------------+---------------+------------+----------------+
+; Module Name             ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
++-------------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis    ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
+; Fitter                  ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
+; Assembler               ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
+; Classic Timing Analyzer ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
++-------------------------+------------------+---------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
+quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
+quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
+quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only
+
+
+
diff --git a/FPGA_by_Fredi/firebee1.map.rpt b/FPGA_by_Fredi/firebee1.map.rpt
new file mode 100644
index 0000000..11a1ac1
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.map.rpt
@@ -0,0 +1,8590 @@
+Analysis & Synthesis report for firebee1
+Wed Dec 15 02:21:56 2010
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis DSP Block Usage Summary
+ 10. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR
+ 11. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM
+ 12. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE
+ 13. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE
+ 14. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE
+ 15. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE
+ 16. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE
+ 17. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE
+ 18. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE
+ 19. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE
+ 20. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE
+ 21. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE
+ 22. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE
+ 23. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP
+ 24. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE
+ 25. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE
+ 26. Registers Protected by Synthesis
+ 27. User-Specified and Inferred Latches
+ 28. Registers Removed During Synthesis
+ 29. Removed Registers Triggering Further Register Optimizations
+ 30. General Register Statistics
+ 31. Inverted Register Statistics
+ 32. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 33. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated
+ 34. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p
+ 35. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p
+ 36. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram
+ 37. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp
+ 38. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12
+ 39. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp
+ 40. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp
+ 41. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp
+ 42. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17
+ 43. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated
+ 44. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p
+ 45. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p
+ 46. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram
+ 47. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp
+ 48. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp
+ 49. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp
+ 50. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12
+ 51. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp
+ 52. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15
+ 53. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component
+ 54. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated
+ 55. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 56. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 57. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp
+ 58. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram
+ 59. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp
+ 60. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15
+ 61. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr
+ 62. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp
+ 63. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp
+ 64. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp
+ 65. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22
+ 66. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component
+ 67. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated
+ 68. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
+ 69. Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram
+ 70. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
+ 71. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
+ 72. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
+ 73. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
+ 74. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
+ 75. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
+ 76. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
+ 77. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
+ 78. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component
+ 79. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated
+ 80. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component
+ 81. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated
+ 82. Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated
+ 83. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component
+ 84. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated
+ 85. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1
+ 86. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12
+ 87. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13
+ 88. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14
+ 89. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15
+ 90. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2
+ 91. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3
+ 92. Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component
+ 93. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component
+ 94. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
+ 95. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component
+ 96. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
+ 97. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component
+ 98. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
+ 99. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component
+100. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
+101. Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component
+102. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component
+103. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component
+104. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL
+105. Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component
+106. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component
+107. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component
+108. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component
+109. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component
+110. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component
+111. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component
+112. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component
+113. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component
+114. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component
+115. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component
+116. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component
+117. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component
+118. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component
+119. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component
+120. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component
+121. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component
+122. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component
+123. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component
+124. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component
+125. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component
+126. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component
+127. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component
+128. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component
+129. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component
+130. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component
+131. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component
+132. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component
+133. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component
+134. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component
+135. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component
+136. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component
+137. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component
+138. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component
+139. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component
+140. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component
+141. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component
+142. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component
+143. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component
+144. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component
+145. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component
+146. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component
+147. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component
+148. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component
+149. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component
+150. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component
+151. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component
+152. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component
+153. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component
+154. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component
+155. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component
+156. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component
+157. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component
+158. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component
+159. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component
+160. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component
+161. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component
+162. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component
+163. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component
+164. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component
+165. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component
+166. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component
+167. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component
+168. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component
+169. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component
+170. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component
+171. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component
+172. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component
+173. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component
+174. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component
+175. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component
+176. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component
+177. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component
+178. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component
+179. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component
+180. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component
+181. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component
+182. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component
+183. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component
+184. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component
+185. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component
+186. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component
+187. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component
+188. Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component
+189. Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component
+190. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component
+191. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4
+192. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5
+193. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6
+194. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7
+195. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1
+196. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12
+197. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13
+198. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14
+199. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15
+200. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2
+201. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3
+202. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11
+203. Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component
+204. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component
+205. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component
+206. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component
+207. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component
+208. Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component
+209. Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component
+210. Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component
+211. Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component
+212. Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component
+213. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14
+214. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6
+215. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12
+216. altpll Parameter Settings by Entity Instance
+217. lpm_shiftreg Parameter Settings by Entity Instance
+218. dcfifo Parameter Settings by Entity Instance
+219. scfifo Parameter Settings by Entity Instance
+220. altsyncram Parameter Settings by Entity Instance
+221. lpm_mult Parameter Settings by Entity Instance
+222. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"
+223. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"
+224. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI"
+225. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD"
+226. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS"
+227. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"
+228. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"
+229. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                      ;
++------------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Wed Dec 15 02:21:55 2010        ;
+; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name                      ; firebee1                                     ;
+; Top-level Entity Name              ; firebee1                                     ;
+; Family                             ; Cyclone III                                  ;
+; Total logic elements               ; 10,706                                       ;
+;     Total combinational functions  ; 8,060                                        ;
+;     Dedicated logic registers      ; 4,612                                        ;
+; Total registers                    ; 4740                                         ;
+; Total pins                         ; 295                                          ;
+; Total virtual pins                 ; 0                                            ;
+; Total memory bits                  ; 109,344                                      ;
+; Embedded Multiplier 9-bit elements ; 6                                            ;
+; Total PLLs                         ; 4                                            ;
++------------------------------------+----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C40F484C6       ;                    ;
+; Top-level entity name                                                      ; firebee1           ; firebee1           ;
+; Family name                                                                ; Cyclone III        ; Stratix II         ;
+; State Machine Processing                                                   ; One-Hot            ; Auto               ;
+; Optimization Technique                                                     ; Speed              ; Balanced           ;
+; Use Generated Physical Constraints File                                    ; Off                ;                    ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Show Parameter Settings Tables in Synthesis Report                         ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                 ;
++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
+; File Name with User-Entered Path                               ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                   ;
++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
+; FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd               ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd               ;
+; FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd                   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd                   ;
+; FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd             ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd             ;
+; FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd               ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd               ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd  ;
+; FalconIO_SDCard_IDE_CF/dcfifo0.vhd                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo0.vhd                             ;
+; Video/DDR_CTR.tdf                                              ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Video/DDR_CTR.tdf                                              ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd      ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd    ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd  ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd          ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd    ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd      ;
+; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd  ;
+; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ;
+; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd     ;
+; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd     ;
+; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd    ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd       ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd       ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd        ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd        ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd     ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd    ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd   ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd  ;
+; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd   ;
+; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd          ;
+; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd      ;
+; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd         ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd         ;
+; lpm_latch0.vhd                                                 ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_latch0.vhd                                                 ;
+; altpll1.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll1.vhd                                                    ;
+; Video/lpm_fifoDZ.vhd                                           ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_fifoDZ.vhd                                           ;
+; altpll2.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll2.vhd                                                    ;
+; altpll3.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll3.vhd                                                    ;
+; Video/altdpram0.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram0.vhd                                            ;
+; Video/lpm_muxDZ.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_muxDZ.vhd                                            ;
+; Video/lpm_bustri3.vhd                                          ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_bustri3.vhd                                          ;
+; Video/lpm_ff0.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff0.vhd                                              ;
+; Video/lpm_ff1.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff1.vhd                                              ;
+; Video/lpm_ff3.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff3.vhd                                              ;
+; Video/VIDEO_MOD_MUX_CLUTCTR.tdf                                ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Video/VIDEO_MOD_MUX_CLUTCTR.tdf                                ;
+; Video/lpm_fifo_dc0.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_fifo_dc0.vhd                                         ;
+; Video/Video.bdf                                                ; yes             ; User Block Diagram/Schematic File  ; C:/FireBee/FPGA/Video/Video.bdf                                                ;
+; firebee1.bdf                                                   ; yes             ; User Block Diagram/Schematic File  ; C:/FireBee/FPGA/firebee1.bdf                                                   ;
+; lpm_counter0.vhd                                               ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_counter0.vhd                                               ;
+; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd              ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd              ;
+; DSP/DSP.vhd                                                    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/DSP/DSP.vhd                                                    ;
+; Video/lpm_shiftreg0.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg0.vhd                                        ;
+; Video/lpm_bustri1.vhd                                          ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_bustri1.vhd                                          ;
+; Video/altdpram1.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram1.vhd                                            ;
+; Video/lpm_constant0.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant0.vhd                                        ;
+; Video/lpm_constant1.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant1.vhd                                        ;
+; Video/lpm_mux0.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux0.vhd                                             ;
+; Video/lpm_mux1.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux1.vhd                                             ;
+; Video/lpm_mux2.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux2.vhd                                             ;
+; Video/lpm_constant2.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant2.vhd                                        ;
+; Video/altdpram2.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram2.vhd                                            ;
+; Video/lpm_mux3.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux3.vhd                                             ;
+; Video/lpm_mux4.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux4.vhd                                             ;
+; Video/lpm_constant3.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant3.vhd                                        ;
+; Interrupt_Handler/interrupt_handler.tdf                        ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Interrupt_Handler/interrupt_handler.tdf                        ;
+; lpm_bustri_LONG.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_LONG.vhd                                            ;
+; lpm_bustri_BYT.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_BYT.vhd                                             ;
+; lpm_bustri_WORD.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_WORD.vhd                                            ;
+; Video/lpm_ff4.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff4.vhd                                              ;
+; Video/lpm_ff5.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff5.vhd                                              ;
+; Video/lpm_ff6.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff6.vhd                                              ;
+; Video/altddio_bidir0.vhd                                       ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_bidir0.vhd                                       ;
+; Video/altddio_out0.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_out0.vhd                                         ;
+; Video/lpm_mux5.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux5.vhd                                             ;
+; Video/BLITTER/BLITTER.vhd                                      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/Video/BLITTER/BLITTER.vhd                                      ;
+; Video/lpm_shiftreg6.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg6.vhd                                        ;
+; Video/lpm_shiftreg4.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg4.vhd                                        ;
+; Video/altddio_out2.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_out2.vhd                                         ;
+; altddio_out3.vhd                                               ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altddio_out3.vhd                                               ;
+; Video/lpm_mux6.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux6.vhd                                             ;
+; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd          ;
+; FalconIO_SDCard_IDE_CF/dcfifo1.vhd                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo1.vhd                             ;
+; Video/lpm_muxVDM.vhd                                           ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_muxVDM.vhd                                           ;
+; lpm_bustri_byt.inc                                             ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_byt.inc                                             ;
+; lpm_bustri_word.inc                                            ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_word.inc                                            ;
+; lpm_bustri_long.inc                                            ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_long.inc                                            ;
+; altpll.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.tdf                     ;
+; db/altpll_pul2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_pul2.tdf                                             ;
+; dcfifo_mixed_widths.tdf                                        ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf        ;
+; db/dcfifo_0hh1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_0hh1.tdf                                             ;
+; db/a_gray2bin_lfb.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_gray2bin_lfb.tdf                                          ;
+; db/a_graycounter_k47.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_k47.tdf                                       ;
+; db/a_graycounter_fic.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_fic.tdf                                       ;
+; db/altsyncram_bi31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_bi31.tdf                                         ;
+; db/alt_synch_pipe_ikd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_ikd.tdf                                      ;
+; db/dffpipe_hd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_hd9.tdf                                             ;
+; db/dffpipe_gd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_gd9.tdf                                             ;
+; db/dffpipe_pe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_pe9.tdf                                             ;
+; db/alt_synch_pipe_jkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_jkd.tdf                                      ;
+; db/dffpipe_id9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_id9.tdf                                             ;
+; db/cmpr_256.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_256.tdf                                                ;
+; db/cmpr_156.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_156.tdf                                                ;
+; db/cntr_t2e.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_t2e.tdf                                                ;
+; db/mux_a18.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_a18.tdf                                                 ;
+; db/dcfifo_3fh1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_3fh1.tdf                                             ;
+; db/a_graycounter_j47.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_j47.tdf                                       ;
+; db/a_graycounter_gic.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_gic.tdf                                       ;
+; db/altsyncram_ci31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_ci31.tdf                                         ;
+; db/alt_synch_pipe_kkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_kkd.tdf                                      ;
+; db/dffpipe_jd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_jd9.tdf                                             ;
+; db/alt_synch_pipe_lkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_lkd.tdf                                      ;
+; db/dffpipe_kd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_kd9.tdf                                             ;
+; db/altpll_41p2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_41p2.tdf                                             ;
+; lpm_bustri.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_bustri.tdf                 ;
+; lpm_shiftreg.tdf                                               ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf               ;
+; dcfifo.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo.tdf                     ;
+; db/dcfifo_8fi1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_8fi1.tdf                                             ;
+; db/a_gray2bin_tgb.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_gray2bin_tgb.tdf                                          ;
+; db/a_graycounter_s57.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_s57.tdf                                       ;
+; db/a_graycounter_ojc.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_ojc.tdf                                       ;
+; db/a_graycounter_njc.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_njc.tdf                                       ;
+; db/altsyncram_tl31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_tl31.tdf                                         ;
+; db/alt_synch_pipe_rld.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_rld.tdf                                      ;
+; db/dffpipe_qe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_qe9.tdf                                             ;
+; db/dffpipe_9d9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_9d9.tdf                                             ;
+; db/dffpipe_oe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_oe9.tdf                                             ;
+; db/alt_synch_pipe_sld.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_sld.tdf                                      ;
+; db/dffpipe_re9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_re9.tdf                                             ;
+; lpm_mux.tdf                                                    ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf                    ;
+; db/mux_bbe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_bbe.tdf                                                 ;
+; lpm_ff.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_ff.tdf                     ;
+; altddio_bidir.tdf                                              ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_bidir.tdf              ;
+; db/ddio_bidir_3jl.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_bidir_3jl.tdf                                          ;
+; db/mux_58e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_58e.tdf                                                 ;
+; lpm_latch.tdf                                                  ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_latch.tdf                  ;
+; altsyncram.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf                 ;
+; db/altsyncram_lf92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_lf92.tdf                                         ;
+; mux41.bdf                                                      ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/others/maxplus2/mux41.bdf                    ;
+; db/mux_dcf.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_dcf.tdf                                                 ;
+; scfifo.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/scfifo.tdf                     ;
+; db/scfifo_lk21.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/scfifo_lk21.tdf                                             ;
+; db/a_dpfifo_oq21.tdf                                           ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_dpfifo_oq21.tdf                                           ;
+; db/altsyncram_gj81.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_gj81.tdf                                         ;
+; db/cmpr_br8.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_br8.tdf                                                ;
+; db/cntr_omb.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_omb.tdf                                                ;
+; db/cntr_5n7.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_5n7.tdf                                                ;
+; db/cntr_pmb.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_pmb.tdf                                                ;
+; db/altsyncram_rb92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_rb92.tdf                                         ;
+; db/altsyncram_pf92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_pf92.tdf                                         ;
+; db/mux_96e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_96e.tdf                                                 ;
+; db/mux_mpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_mpe.tdf                                                 ;
+; db/mux_f6e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_f6e.tdf                                                 ;
+; lpm_constant.tdf                                               ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_constant.tdf               ;
+; altddio_out.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_out.tdf                ;
+; db/ddio_out_o2f.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_o2f.tdf                                            ;
+; db/mux_kpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_kpe.tdf                                                 ;
+; db/mux_npe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_npe.tdf                                                 ;
+; db/mux_gpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_gpe.tdf                                                 ;
+; db/ddio_out_are.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_are.tdf                                            ;
+; db/altpll_isv2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_isv2.tdf                                             ;
+; altpll4.tdf                                                    ; yes             ; Auto-Found Wizard-Generated File   ; C:/FireBee/FPGA/altpll4.tdf                                                    ;
+; altpll.inc                                                     ; yes             ; Auto-Found AHDL File               ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.inc                     ;
+; db/altpll_c6j2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_c6j2.tdf                                             ;
+; altpll_reconfig1.tdf                                           ; yes             ; Auto-Found Wizard-Generated File   ; C:/FireBee/FPGA/altpll_reconfig1.tdf                                           ;
+; altpll_reconfig1_pllrcfg_t4q.tdf                               ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/altpll_reconfig1_pllrcfg_t4q.tdf                               ;
+; altsyncram.inc                                                 ; yes             ; Auto-Found AHDL File               ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.inc                 ;
+; db/altsyncram_46r.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_46r.tdf                                          ;
+; lpm_add_sub.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf                ;
+; db/add_sub_hpa.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/add_sub_hpa.tdf                                             ;
+; db/add_sub_k8a.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/add_sub_k8a.tdf                                             ;
+; lpm_compare.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_compare.tdf                ;
+; db/cmpr_tnd.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_tnd.tdf                                                ;
+; lpm_counter.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf                ;
+; db/cntr_30l.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_30l.tdf                                                ;
+; db/cntr_qij.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_qij.tdf                                                ;
+; db/cntr_pij.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_pij.tdf                                                ;
+; db/cntr_9cj.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_9cj.tdf                                                ;
+; lpm_decode.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf                 ;
+; db/decode_2af.tdf                                              ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/decode_2af.tdf                                              ;
+; db/cntr_mph.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_mph.tdf                                                ;
+; db/ddio_out_31f.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_31f.tdf                                            ;
+; lpm_mult.tdf                                                   ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mult.tdf                   ;
+; db/mult_cat.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mult_cat.tdf                                                ;
+; db/mult_aat.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mult_aat.tdf                                                ;
++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+; Estimated Total logic elements              ; 10,706         ;
+;                                             ;                ;
+; Total combinational functions               ; 8060           ;
+; Logic element usage by number of LUT inputs ;                ;
+;     -- 4 input functions                    ; 4947           ;
+;     -- 3 input functions                    ; 1867           ;
+;     -- <=2 input functions                  ; 1246           ;
+;                                             ;                ;
+; Logic elements by mode                      ;                ;
+;     -- normal mode                          ; 7261           ;
+;     -- arithmetic mode                      ; 799            ;
+;                                             ;                ;
+; Total registers                             ; 4740           ;
+;     -- Dedicated logic registers            ; 4612           ;
+;     -- I/O registers                        ; 256            ;
+;                                             ;                ;
+; I/O pins                                    ; 295            ;
+; Total memory bits                           ; 109344         ;
+; Embedded Multiplier 9-bit elements          ; 6              ;
+; Total PLLs                                  ; 4              ;
+; Maximum fan-out node                        ; MAIN_CLK~input ;
+; Maximum fan-out                             ; 2327           ;
+; Total fan-out                               ; 49317          ;
+; Average fan-out                             ; 3.57           ;
++---------------------------------------------+----------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                        ;
++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                                                  ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                               ; Library Name ;
++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |firebee1                                                                   ; 8060 (10)         ; 4612 (0)     ; 109344      ; 6            ; 0       ; 3         ; 295  ; 0            ; |firebee1                                                                                                                                                                                                         ; work         ;
+;    |DSP:Mathias_Alles|                                                      ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|DSP:Mathias_Alles                                                                                                                                                                                       ;              ;
+;    |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|          ; 3814 (634)        ; 1633 (114)   ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden                                                                                                                                           ;              ;
+;       |WF1772IP_TOP_SOC:I_FDC|                                              ; 944 (24)          ; 406 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC                                                                                                                    ;              ;
+;          |WF1772IP_AM_DETECTOR:I_AM_DETECTOR|                               ; 39 (39)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR                                                                                 ;              ;
+;          |WF1772IP_CONTROL:I_CONTROL|                                       ; 533 (533)         ; 197 (197)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL                                                                                         ;              ;
+;          |WF1772IP_CRC_LOGIC:I_CRC_LOGIC|                                   ; 40 (40)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC                                                                                     ;              ;
+;          |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|                               ; 104 (104)         ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL                                                                                 ;              ;
+;          |WF1772IP_REGISTERS:I_REGISTERS|                                   ; 86 (86)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS                                                                                     ;              ;
+;          |WF1772IP_TRANSCEIVER:I_TRANSCEIVER|                               ; 118 (118)         ; 80 (80)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER                                                                                 ;              ;
+;       |WF2149IP_TOP_SOC:I_SOUND|                                            ; 445 (32)          ; 210 (29)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND                                                                                                                  ;              ;
+;          |WF2149IP_WAVE:I_PSG_WAVE|                                         ; 413 (413)         ; 181 (181)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE                                                                                         ;              ;
+;       |WF5380_TOP_SOC:I_SCSI|                                               ; 0 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI                                                                                                                     ;              ;
+;          |WF5380_CONTROL:I_CONTROL|                                         ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL                                                                                            ;              ;
+;       |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|                                    ; 199 (2)           ; 97 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD                                                                                                          ;              ;
+;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 16 (16)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                  ;              ;
+;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 94 (94)           ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                          ;              ;
+;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)           ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                        ;              ;
+;       |WF6850IP_TOP_SOC:I_ACIA_MIDI|                                        ; 203 (2)           ; 97 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI                                                                                                              ;              ;
+;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 20 (20)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                      ;              ;
+;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 94 (94)           ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                              ;              ;
+;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)           ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                            ;              ;
+;       |WF68901IP_TOP_SOC:I_MFP|                                             ; 1199 (178)        ; 460 (2)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP                                                                                                                   ;              ;
+;          |WF68901IP_GPIO:I_GPIO|                                            ; 25 (25)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO                                                                                             ;              ;
+;          |WF68901IP_INTERRUPTS:I_INTERRUPTS|                                ; 273 (273)         ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS                                                                                 ;              ;
+;          |WF68901IP_TIMERS:I_TIMERS|                                        ; 434 (434)         ; 166 (166)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS                                                                                         ;              ;
+;          |WF68901IP_USART_TOP:I_USART|                                      ; 289 (4)           ; 140 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART                                                                                       ;              ;
+;             |WF68901IP_USART_CTRL:I_USART_CTRL|                             ; 38 (38)           ; 49 (49)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL                                                     ;              ;
+;             |WF68901IP_USART_RX:I_USART_RECEIVE|                            ; 159 (159)         ; 56 (56)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE                                                    ;              ;
+;             |WF68901IP_USART_TX:I_USART_TRANSMIT|                           ; 88 (88)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT                                                   ;              ;
+;       |dcfifo0:RDF|                                                         ; 94 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF                                                                                                                               ;              ;
+;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 94 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
+;             |dcfifo_0hh1:auto_generated|                                    ; 94 (17)           ; 124 (42)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated                                                  ;              ;
+;                |a_gray2bin_lfb:wrptr_g_gray2bin|                            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin                  ;              ;
+;                |a_gray2bin_lfb:ws_dgrp_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin                  ;              ;
+;                |a_graycounter_fic:wrptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p                      ;              ;
+;                |a_graycounter_k47:rdptr_g1p|                                ; 17 (17)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p                      ;              ;
+;                |alt_synch_pipe_ikd:rs_dgwp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp                       ;              ;
+;                   |dffpipe_hd9:dffpipe12|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;              ;
+;                |alt_synch_pipe_jkd:ws_dgrp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp                       ;              ;
+;                   |dffpipe_id9:dffpipe17|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;              ;
+;                |altsyncram_bi31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram                         ;              ;
+;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
+;                |cmpr_156:wrfull_eq_comp1_msb|                               ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb                     ;              ;
+;                |cntr_t2e:cntr_b|                                            ; 3 (3)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
+;                |dffpipe_gd9:ws_brp|                                         ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp                               ;              ;
+;                |dffpipe_pe9:ws_bwp|                                         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp                               ;              ;
+;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
+;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
+;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
+;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
+;       |dcfifo1:WRF|                                                         ; 96 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF                                                                                                                               ;              ;
+;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 96 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
+;             |dcfifo_3fh1:auto_generated|                                    ; 96 (18)           ; 124 (42)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated                                                  ;              ;
+;                |a_gray2bin_lfb:rdptr_g_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin                  ;              ;
+;                |a_gray2bin_lfb:rs_dgwp_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin                  ;              ;
+;                |a_graycounter_gic:wrptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p                      ;              ;
+;                |a_graycounter_j47:rdptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p                      ;              ;
+;                |alt_synch_pipe_kkd:rs_dgwp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp                       ;              ;
+;                   |dffpipe_jd9:dffpipe12|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;              ;
+;                |alt_synch_pipe_lkd:ws_dgrp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp                       ;              ;
+;                   |dffpipe_kd9:dffpipe15|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;              ;
+;                |altsyncram_ci31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram                         ;              ;
+;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
+;                |cntr_t2e:cntr_b|                                            ; 4 (4)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
+;                |dffpipe_gd9:rs_bwp|                                         ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp                               ;              ;
+;                |dffpipe_pe9:rs_brp|                                         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp                               ;              ;
+;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
+;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
+;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
+;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
+;    |Video:Fredi_Aschwanden|                                                 ; 3109 (10)         ; 2172 (4)     ; 92816       ; 6            ; 0       ; 3         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden                                                                                                                                                                                  ;              ;
+;       |DDR_CTR:DDR_CTR|                                                     ; 348 (314)         ; 158 (158)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR                                                                                                                                                                  ;              ;
+;          |lpm_bustri_BYT:$00002|                                            ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002                                                                                                                                            ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
+;          |lpm_bustri_BYT:$00004|                                            ; 31 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004                                                                                                                                            ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 31 (31)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
+;       |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|                         ; 1260 (1013)       ; 529 (529)    ; 0           ; 6            ; 0       ; 3         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR                                                                                                                                      ;              ;
+;          |lpm_bustri_WORD:$00000|                                           ; 187 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000                                                                                                               ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 187 (187)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component                                                                               ;              ;
+;          |lpm_bustri_WORD:$00002|                                           ; 60 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002                                                                                                               ;              ;
+;             |lpm_bustri:lpm_bustri_component|                               ; 60 (60)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component                                                                               ;              ;
+;          |lpm_mult:op_12|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12                                                                                                                       ;              ;
+;             |mult_aat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated                                                                                               ;              ;
+;          |lpm_mult:op_14|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14                                                                                                                       ;              ;
+;             |mult_cat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated                                                                                               ;              ;
+;          |lpm_mult:op_6|                                                    ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6                                                                                                                        ;              ;
+;             |mult_aat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated                                                                                                ;              ;
+;       |altddio_bidir0:inst1|                                                ; 0 (0)             ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1                                                                                                                                                             ;              ;
+;          |altddio_bidir:altddio_bidir_component|                            ; 0 (0)             ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component                                                                                                                       ;              ;
+;             |ddio_bidir_3jl:auto_generated|                                 ; 0 (0)             ; 96 (96)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated                                                                                         ;              ;
+;       |altddio_out0:inst2|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2                                                                                                                                                               ;              ;
+;          |altddio_out:altddio_out_component|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component                                                                                                                             ;              ;
+;             |ddio_out_are:auto_generated|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated                                                                                                 ;              ;
+;       |altddio_out2:inst5|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5                                                                                                                                                               ;              ;
+;          |altddio_out:altddio_out_component|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component                                                                                                                             ;              ;
+;             |ddio_out_o2f:auto_generated|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated                                                                                                 ;              ;
+;       |altdpram0:ST_CLUT_BLUE|                                              ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE                                                                                                                                                           ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                           ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                            ;              ;
+;       |altdpram0:ST_CLUT_GREEN|                                             ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN                                                                                                                                                          ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                          ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                           ;              ;
+;       |altdpram0:ST_CLUT_RED|                                               ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED                                                                                                                                                            ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                                                                                                            ;              ;
+;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                             ;              ;
+;       |altdpram1:FALCON_CLUT_BLUE|                                          ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE                                                                                                                                                       ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                       ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                        ;              ;
+;       |altdpram1:FALCON_CLUT_GREEN|                                         ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN                                                                                                                                                      ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                      ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                       ;              ;
+;       |altdpram1:FALCON_CLUT_RED|                                           ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED                                                                                                                                                        ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                                                                                                        ;              ;
+;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                         ;              ;
+;       |altdpram2:ACP_CLUT_RAM54|                                            ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54                                                                                                                                                         ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                                                                                                         ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
+;       |altdpram2:ACP_CLUT_RAM55|                                            ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55                                                                                                                                                         ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                                                                                                         ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
+;       |altdpram2:ACP_CLUT_RAM|                                              ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM                                                                                                                                                           ;              ;
+;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                                                                                                           ;              ;
+;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                            ;              ;
+;       |lpm_bustri_LONG:inst119|                                             ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_ff0:inst13|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst14|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst15|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst16|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst17|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst18|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff0:inst19|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst12|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst20|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff1:inst3|                                                       ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff1:inst4|                                                       ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff1:inst9|                                                       ; 0 (0)             ; 24 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9                                                                                                                                                                    ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
+;       |lpm_ff3:inst46|                                                      ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst47|                                                      ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst49|                                                      ; 0 (0)             ; 9 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff3:inst52|                                                      ; 0 (0)             ; 9 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff4:inst10|                                                      ; 0 (0)             ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff5:inst11|                                                      ; 0 (0)             ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff5:inst97|                                                      ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff6:inst71|                                                      ; 0 (0)             ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_ff6:inst94|                                                      ; 0 (0)             ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94                                                                                                                                                                   ;              ;
+;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
+;       |lpm_fifoDZ:inst63|                                                   ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63                                                                                                                                                                ;              ;
+;          |scfifo:scfifo_component|                                          ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component                                                                                                                                        ;              ;
+;             |scfifo_lk21:auto_generated|                                    ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated                                                                                                             ;              ;
+;                |a_dpfifo_oq21:dpfifo|                                       ; 22 (9)            ; 21 (8)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo                                                                                        ;              ;
+;                   |altsyncram_gj81:FIFOram|                                 ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram                                                                ;              ;
+;                   |cntr_omb:rd_ptr_msb|                                     ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb                                                                    ;              ;
+;                   |cntr_pmb:wr_ptr|                                         ; 7 (7)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr                                                                        ;              ;
+;       |lpm_fifo_dc0:inst|                                                   ; 66 (0)            ; 98 (0)       ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst                                                                                                                                                                ;              ;
+;          |dcfifo:dcfifo_component|                                          ; 66 (0)            ; 98 (0)       ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component                                                                                                                                        ;              ;
+;             |dcfifo_8fi1:auto_generated|                                    ; 66 (12)           ; 98 (20)      ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                                                                             ;              ;
+;                |a_gray2bin_tgb:wrptr_g_gray2bin|                            ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                                                                             ;              ;
+;                |a_gray2bin_tgb:ws_dgrp_gray2bin|                            ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                                                                             ;              ;
+;                |a_graycounter_njc:wrptr_gp|                                 ; 17 (17)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp                                                                                  ;              ;
+;                |a_graycounter_s57:rdptr_g1p|                                ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p                                                                                 ;              ;
+;                |alt_synch_pipe_sld:ws_dgrp|                                 ; 0 (0)             ; 30 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp                                                                                  ;              ;
+;                   |dffpipe_re9:dffpipe22|                                   ; 0 (0)             ; 30 (30)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22                                                            ;              ;
+;                |altsyncram_tl31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram                                                                                    ;              ;
+;                |dffpipe_9d9:wraclr|                                         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr                                                                                          ;              ;
+;                |dffpipe_oe9:ws_brp|                                         ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp                                                                                          ;              ;
+;                |dffpipe_oe9:ws_bwp|                                         ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp                                                                                          ;              ;
+;       |lpm_latch0:inst27|                                                   ; 32 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27                                                                                                                                                                ;              ;
+;          |lpm_latch:lpm_latch_component|                                    ; 32 (32)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component                                                                                                                                  ;              ;
+;       |lpm_mux0:inst21|                                                     ; 48 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 48 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_gpe:auto_generated|                                        ; 48 (48)           ; 96 (96)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux1:inst24|                                                     ; 80 (0)            ; 81 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 80 (0)            ; 81 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_npe:auto_generated|                                        ; 80 (80)           ; 81 (81)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux2:inst25|                                                     ; 80 (0)            ; 41 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 80 (0)            ; 41 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_mpe:auto_generated|                                        ; 80 (80)           ; 41 (41)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux3:inst102|                                                    ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102                                                                                                                                                                 ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
+;             |mux_96e:auto_generated|                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated                                                                                                                ;              ;
+;       |lpm_mux4:inst81|                                                     ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_f6e:auto_generated|                                        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux5:inst22|                                                     ; 64 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22                                                                                                                                                                  ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 64 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
+;             |mux_58e:auto_generated|                                        ; 64 (64)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated                                                                                                                 ;              ;
+;       |lpm_mux6:inst7|                                                      ; 90 (0)            ; 67 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7                                                                                                                                                                   ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 90 (0)            ; 67 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component                                                                                                                                         ;              ;
+;             |mux_kpe:auto_generated|                                        ; 90 (90)           ; 67 (67)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated                                                                                                                  ;              ;
+;       |lpm_muxDZ:inst62|                                                    ; 128 (0)           ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62                                                                                                                                                                 ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 128 (0)           ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
+;             |mux_dcf:auto_generated|                                        ; 128 (128)         ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated                                                                                                                ;              ;
+;       |lpm_muxVDM:inst100|                                                  ; 736 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100                                                                                                                                                               ;              ;
+;          |lpm_mux:lpm_mux_component|                                        ; 736 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component                                                                                                                                     ;              ;
+;             |mux_bbe:auto_generated|                                        ; 736 (736)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated                                                                                                              ;              ;
+;       |lpm_shiftreg0:sr0|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr1|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr2|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr3|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr4|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr5|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr6|                                                   ; 16 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg0:sr7|                                                   ; 16 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7                                                                                                                                                                ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
+;       |lpm_shiftreg4:inst26|                                                ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26                                                                                                                                                             ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
+;       |lpm_shiftreg6:inst92|                                                ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92                                                                                                                                                             ;              ;
+;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
+;       |mux41:inst40|                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40                                                                                                                                                                     ;              ;
+;       |mux41:inst41|                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41                                                                                                                                                                     ;              ;
+;       |mux41:inst42|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42                                                                                                                                                                     ;              ;
+;       |mux41:inst43|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43                                                                                                                                                                     ;              ;
+;       |mux41:inst44|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44                                                                                                                                                                     ;              ;
+;       |mux41:inst45|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45                                                                                                                                                                     ;              ;
+;    |altddio_out3:inst5|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst6|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst8|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8                                                                                                                                                                                      ;              ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
+;    |altddio_out3:inst9|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9                                                                                                                                                                                      ; work         ;
+;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component                                                                                                                                                    ; work         ;
+;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ; work         ;
+;    |altpll1:inst|                                                           ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst                                                                                                                                                                                            ;              ;
+;       |altpll:altpll_component|                                             ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst|altpll:altpll_component                                                                                                                                                                    ;              ;
+;          |altpll_pul2:auto_generated|                                       ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated                                                                                                                                         ;              ;
+;    |altpll2:inst12|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_isv2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated                                                                                                                                       ;              ;
+;    |altpll3:inst13|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_41p2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated                                                                                                                                       ;              ;
+;    |altpll4:inst22|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22                                                                                                                                                                                          ;              ;
+;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22|altpll:altpll_component                                                                                                                                                                  ;              ;
+;          |altpll_c6j2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated                                                                                                                                       ;              ;
+;    |altpll_reconfig1:inst7|                                                 ; 309 (0)           ; 128 (0)      ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7                                                                                                                                                                                  ;              ;
+;       |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 309 (211)         ; 128 (80)     ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component                                                                                                              ;              ;
+;          |altsyncram:altsyncram4|                                           ; 0 (0)             ; 0 (0)        ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4                                                                                       ;              ;
+;             |altsyncram_46r:auto_generated|                                 ; 0 (0)             ; 0 (0)        ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated                                                         ;              ;
+;          |lpm_compare:cmpr7|                                                ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7                                                                                            ;              ;
+;             |cmpr_tnd:auto_generated|                                       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr12|                                               ; 10 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12                                                                                           ;              ;
+;             |cntr_30l:auto_generated|                                       ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr13|                                               ; 7 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13                                                                                           ;              ;
+;             |cntr_qij:auto_generated|                                       ; 7 (7)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr14|                                               ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14                                                                                           ;              ;
+;             |cntr_pij:auto_generated|                                       ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr15|                                               ; 18 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15                                                                                           ;              ;
+;             |cntr_30l:auto_generated|                                       ; 18 (18)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated                                                                   ;              ;
+;          |lpm_counter:cntr1|                                                ; 41 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1                                                                                            ;              ;
+;             |cntr_30l:auto_generated|                                       ; 41 (41)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr2|                                                ; 9 (0)             ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2                                                                                            ;              ;
+;             |cntr_9cj:auto_generated|                                       ; 9 (9)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated                                                                    ;              ;
+;          |lpm_counter:cntr3|                                                ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3                                                                                            ;              ;
+;             |cntr_pij:auto_generated|                                       ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated                                                                    ;              ;
+;    |interrupt_handler:nobody|                                               ; 789 (711)         ; 633 (633)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody                                                                                                                                                                                ;              ;
+;       |lpm_bustri_BYT:$00000|                                               ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00002|                                               ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00004|                                               ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;       |lpm_bustri_BYT:$00006|                                               ; 22 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006                                                                                                                                                          ;              ;
+;          |lpm_bustri:lpm_bustri_component|                                  ; 22 (22)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
+;    |lpm_counter0:inst18|                                                    ; 18 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18                                                                                                                                                                                     ;              ;
+;       |lpm_counter:lpm_counter_component|                                   ; 18 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component                                                                                                                                                   ;              ;
+;          |cntr_mph:auto_generated|                                          ; 18 (18)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated                                                                                                                           ;              ;
+;    |lpm_ff0:inst1|                                                          ; 0 (0)             ; 28 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_ff0:inst1                                                                                                                                                                                           ;              ;
+;       |lpm_ff:lpm_ff_component|                                             ; 0 (0)             ; 28 (28)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component                                                                                                                                                                   ;              ;
++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                                                                       ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024         ; 8            ; 256          ; 32           ; 8192  ; None ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256          ; 32           ; 1024         ; 8            ; 8192  ; None ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                   ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
+; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                     ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                               ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
+; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                 ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
+; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
+; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM                                        ; AUTO ; Simple Dual Port ; 128          ; 128          ; 128          ; 128          ; 16384 ; None ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM                                                            ; AUTO ; Simple Dual Port ; 512          ; 128          ; 512          ; 128          ; 65536 ; None ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM                                 ; AUTO ; Single Port      ; 144          ; 1            ; --           ; --           ; 144   ; None ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++-----------------------------------------------------+
+; Analysis & Synthesis DSP Block Usage Summary        ;
++---------------------------------------+-------------+
+; Statistic                             ; Number Used ;
++---------------------------------------+-------------+
+; Simple Multipliers (9-bit)            ; 0           ;
+; Simple Multipliers (18-bit)           ; 3           ;
+; Embedded Multiplier Blocks            ; --          ;
+; Embedded Multiplier 9-bit elements    ; 6           ;
+; Signed Embedded Multipliers           ; 0           ;
+; Unsigned Embedded Multipliers         ; 3           ;
+; Mixed Sign Embedded Multipliers       ; 0           ;
+; Variable Sign Embedded Multipliers    ; 0           ;
+; Dedicated Input Shift Register Chains ; 0           ;
++---------------------------------------+-------------+
+Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------------+
+; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR ;
++---------+-------+-------+-------+-------+----------------------------------+
+; Name    ; FR_S3 ; FR_S2 ; FR_S1 ; FR_S0 ; FR_WAIT                          ;
++---------+-------+-------+-------+-------+----------------------------------+
+; FR_WAIT ; 0     ; 0     ; 0     ; 0     ; 0                                ;
+; FR_S0   ; 0     ; 0     ; 0     ; 1     ; 1                                ;
+; FR_S1   ; 0     ; 0     ; 1     ; 0     ; 1                                ;
+; FR_S2   ; 0     ; 1     ; 0     ; 0     ; 1                                ;
+; FR_S3   ; 1     ; 0     ; 0     ; 0     ; 1                                ;
++---------+-------+-------+-------+-------+----------------------------------+
+
+
+Encoding Type:  One-Hot
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM                                                                                                                                                                                                                                                     ;
++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
+; Name    ; DS_R6 ; DS_R5 ; DS_R4 ; DS_R3 ; DS_R2 ; DS_CB8 ; DS_CB6 ; DS_T10F ; DS_T9F ; DS_T8F ; DS_T7F ; DS_T6F ; DS_T5F ; DS_T4F ; DS_T9W ; DS_T8W ; DS_T7W ; DS_T6W ; DS_T5W ; DS_T4W ; DS_T5R ; DS_T4R ; DS_C7 ; DS_C6 ; DS_C5 ; DS_C4 ; DS_C3 ; DS_C2 ; DS_N8 ; DS_N7 ; DS_N6 ; DS_N5 ; DS_T3 ; DS_T2B ; DS_T2A ; DS_T1 ;
++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
+; DS_T1   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0     ;
+; DS_T2A  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 1      ; 1     ;
+; DS_T2B  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1      ; 0      ; 1     ;
+; DS_T3   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0      ; 0      ; 1     ;
+; DS_N5   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0      ; 0      ; 1     ;
+; DS_N6   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_N7   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_N8   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C2   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C3   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C4   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C5   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C6   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_C7   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T4R  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T5R  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T4W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T5W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T6W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T7W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T8W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T9W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T4F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T5F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T6F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T7F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T8F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T9F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_T10F ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_CB6  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 1      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_CB8  ; 0     ; 0     ; 0     ; 0     ; 0     ; 1      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_R2   ; 0     ; 0     ; 0     ; 0     ; 1     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_R3   ; 0     ; 0     ; 0     ; 1     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_R4   ; 0     ; 0     ; 1     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_R5   ; 0     ; 1     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
+; DS_R6   ; 1     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
+
+
+Encoding Type:  One-Hot
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE                                                         ;
++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
+; Name               ; FCF_STATE.FCF_T7 ; FCF_STATE.FCF_T6 ; FCF_STATE.FCF_T3 ; FCF_STATE.FCF_T2 ; FCF_STATE.FCF_T1 ; FCF_STATE.FCF_T0 ; FCF_STATE.FCF_IDLE ;
++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
+; FCF_STATE.FCF_IDLE ; 0                ; 0                ; 0                ; 0                ; 0                ; 0                ; 0                  ;
+; FCF_STATE.FCF_T0   ; 0                ; 0                ; 0                ; 0                ; 0                ; 1                ; 1                  ;
+; FCF_STATE.FCF_T1   ; 0                ; 0                ; 0                ; 0                ; 1                ; 0                ; 1                  ;
+; FCF_STATE.FCF_T2   ; 0                ; 0                ; 0                ; 1                ; 0                ; 0                ; 1                  ;
+; FCF_STATE.FCF_T3   ; 0                ; 0                ; 1                ; 0                ; 0                ; 0                ; 1                  ;
+; FCF_STATE.FCF_T6   ; 0                ; 1                ; 0                ; 0                ; 0                ; 0                ; 1                  ;
+; FCF_STATE.FCF_T7   ; 1                ; 0                ; 0                ; 0                ; 0                ; 0                ; 1                  ;
++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
+
+
+Encoding Type:  One-Hot
++---------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE ;
++----------------+--------------+--------------+--------------+-------------------------------------+
+; Name           ; CMD_STATE.T7 ; CMD_STATE.T6 ; CMD_STATE.T1 ; CMD_STATE.IDLE                      ;
++----------------+--------------+--------------+--------------+-------------------------------------+
+; CMD_STATE.IDLE ; 0            ; 0            ; 0            ; 0                                   ;
+; CMD_STATE.T1   ; 0            ; 0            ; 1            ; 1                                   ;
+; CMD_STATE.T6   ; 0            ; 1            ; 0            ; 1                                   ;
+; CMD_STATE.T7   ; 1            ; 0            ; 0            ; 1                                   ;
++----------------+--------------+--------------+--------------+-------------------------------------+
+
+
+Encoding Type:  One-Hot
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE ;
++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
+; Name                 ; INT_STATE.VECTOR_OUT ; INT_STATE.REQUEST ; INT_STATE.SCAN                                                                            ;
++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
+; INT_STATE.SCAN       ; 0                    ; 0                 ; 0                                                                                         ;
+; INT_STATE.REQUEST    ; 0                    ; 1                 ; 1                                                                                         ;
+; INT_STATE.VECTOR_OUT ; 1                    ; 0                 ; 1                                                                                         ;
++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE ;
++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
+; Name                 ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.CHECK_BREAK ; TR_STATE.IDLE                ;
++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
+; TR_STATE.IDLE        ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 0                            ;
+; TR_STATE.CHECK_BREAK ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                    ; 1                            ;
+; TR_STATE.LOAD_SHFT   ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 0                    ; 1                            ;
+; TR_STATE.START       ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 0                    ; 1                            ;
+; TR_STATE.SHIFTOUT    ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 0                    ; 1                            ;
+; TR_STATE.PARITY      ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
+; TR_STATE.STOP1       ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
+; TR_STATE.STOP2       ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
+; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE                                  ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
+; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                                               ;
+; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                                               ;
+; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                                               ;
+; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                                               ;
+; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                                               ;
+; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                                               ;
+; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                                               ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
+; Name               ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE                ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
+; TR_STATE.IDLE      ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                            ;
+; TR_STATE.LOAD_SHFT ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 1                            ;
+; TR_STATE.START     ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 1                            ;
+; TR_STATE.SHIFTOUT  ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 1                            ;
+; TR_STATE.PARITY    ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 1                            ;
+; TR_STATE.STOP1     ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 1                            ;
+; TR_STATE.STOP2     ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                            ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
+; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE        ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
+; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                     ;
+; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                     ;
+; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                     ;
+; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                     ;
+; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                     ;
+; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                     ;
+; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                     ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
+
+
+Encoding Type:  One-Hot
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
+; Name               ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE                    ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
+; TR_STATE.IDLE      ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                                ;
+; TR_STATE.LOAD_SHFT ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 1                                ;
+; TR_STATE.START     ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 1                                ;
+; TR_STATE.SHIFTOUT  ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 1                                ;
+; TR_STATE.PARITY    ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 1                                ;
+; TR_STATE.STOP1     ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 1                                ;
+; TR_STATE.STOP2     ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                                ;
++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
+; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE            ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
+; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                         ;
+; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                         ;
+; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                         ;
+; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                         ;
+; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                         ;
+; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                         ;
+; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                         ;
++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE ;
++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
+; Name                 ; DMA_STATE.DMA_STEP_4 ; DMA_STATE.DMA_STEP_3 ; DMA_STATE.DMA_STEP_2 ; DMA_STATE.DMA_STEP_1 ; DMA_STATE.IDLE                ;
++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
+; DMA_STATE.IDLE       ; 0                    ; 0                    ; 0                    ; 0                    ; 0                             ;
+; DMA_STATE.DMA_STEP_1 ; 0                    ; 0                    ; 0                    ; 1                    ; 1                             ;
+; DMA_STATE.DMA_STEP_2 ; 0                    ; 0                    ; 1                    ; 0                    ; 1                             ;
+; DMA_STATE.DMA_STEP_3 ; 0                    ; 1                    ; 0                    ; 0                    ; 1                             ;
+; DMA_STATE.DMA_STEP_4 ; 1                    ; 0                    ; 0                    ; 0                    ; 1                             ;
++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE                    ;
++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
+; Name                    ; CTRL_STATE.DMA_INIT_RCV ; CTRL_STATE.DMA_TARG_RCV ; CTRL_STATE.DMA_SEND ; CTRL_STATE.WAIT_2200ns ; CTRL_STATE.WAIT_800ns ; CTRL_STATE.IDLE ;
++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
+; CTRL_STATE.IDLE         ; 0                       ; 0                       ; 0                   ; 0                      ; 0                     ; 0               ;
+; CTRL_STATE.WAIT_800ns   ; 0                       ; 0                       ; 0                   ; 0                      ; 1                     ; 1               ;
+; CTRL_STATE.WAIT_2200ns  ; 0                       ; 0                       ; 0                   ; 1                      ; 0                     ; 1               ;
+; CTRL_STATE.DMA_SEND     ; 0                       ; 0                       ; 1                   ; 0                      ; 0                     ; 1               ;
+; CTRL_STATE.DMA_TARG_RCV ; 0                       ; 1                       ; 0                   ; 0                      ; 0                     ; 1               ;
+; CTRL_STATE.DMA_INIT_RCV ; 1                       ; 0                       ; 0                   ; 0                      ; 0                     ; 1               ;
++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
+
+
+Encoding Type:  One-Hot
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP ;
++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
+; Name            ; PRECOMP.LATE ; PRECOMP.EARLY ; PRECOMP.NOMINAL                                                                                          ;
++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
+; PRECOMP.NOMINAL ; 0            ; 0             ; 0                                                                                                        ;
+; PRECOMP.EARLY   ; 0            ; 1             ; 1                                                                                                        ;
+; PRECOMP.LATE    ; 1            ; 0             ; 1                                                                                                        ;
++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE ;
++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
+; Name           ; MFM_STATE.C_10 ; MFM_STATE.B_01 ; MFM_STATE.A_00                                                                                           ;
++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
+; MFM_STATE.A_00 ; 0              ; 0              ; 0                                                                                                        ;
+; MFM_STATE.B_01 ; 0              ; 1              ; 1                                                                                                        ;
+; MFM_STATE.C_10 ; 1              ; 0              ; 1                                                                                                        ;
++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
+; Name                       ; CMD_STATE.T3_VERIFY_CRC ; CMD_STATE.T3_LOAD_SR ; CMD_STATE.T3_CHECK_RD ; CMD_STATE.T3_SET_DRQ_2 ; CMD_STATE.T3_LOAD_DATA_2 ; CMD_STATE.T3_SHIFT_ADR ; CMD_STATE.T3_VERIFY_AM ; CMD_STATE.T3_RD_ADR ; CMD_STATE.T3_SET_DRQ_1 ; CMD_STATE.T3_LOAD_DATA_1 ; CMD_STATE.T3_CHECK_DR ; CMD_STATE.T3_CHECK_BYTE ; CMD_STATE.T3_DETECT_AM ; CMD_STATE.T3_CHECK_INDEX_3 ; CMD_STATE.T3_SHIFT ; CMD_STATE.T3_RD_TRACK ; CMD_STATE.T3_DATALOST ; CMD_STATE.T3_CHECK_INDEX_2 ; CMD_STATE.T3_WR_DATA ; CMD_STATE.T3_LOAD_SHFT ; CMD_STATE.T3_CHECK_INDEX_1 ; CMD_STATE.T3_VERIFY_DRQ ; CMD_STATE.T3_DELAY_B3 ; CMD_STATE.T3_WR ; CMD_STATE.T2_WR_FF ; CMD_STATE.T2_WR_CRC ; CMD_STATE.T2_WRSTAT ; CMD_STATE.T2_DATALOST ; CMD_STATE.T2_VERIFY_DRQ_3 ; CMD_STATE.T2_WR_BYTE ; CMD_STATE.T2_LOAD_SHFT ; CMD_STATE.T2_WR_AM ; CMD_STATE.T2_WR_LEADIN ; CMD_STATE.T2_DELAY_B11 ; CMD_STATE.T2_CHECK_MODE ; CMD_STATE.T2_DELAY_B1 ; CMD_STATE.T2_VERIFY_DRQ_2 ; CMD_STATE.T2_DELAY_B8 ; CMD_STATE.T2_SET_DRQ ; CMD_STATE.T2_DELAY_B2 ; CMD_STATE.T2_MULTISECT ; CMD_STATE.T2_VERIFY_CRC_2 ; CMD_STATE.T2_RDSTAT ; CMD_STATE.T2_VERIFY_DRQ_1 ; CMD_STATE.T2_NEXTBYTE ; CMD_STATE.T2_LOAD_DATA ; CMD_STATE.T2_FIRSTBYTE ; CMD_STATE.T2_VERIFY_AM ; CMD_STATE.T2_VERIFY_CRC_1 ; CMD_STATE.T2_SCAN_LEN ; CMD_STATE.T2_SCAN_SECT ; CMD_STATE.T2_SCAN_TRACK ; CMD_STATE.T2_INIT ; CMD_STATE.T2_RD_WR_SECT ; CMD_STATE.T1_VERIFY_CRC ; CMD_STATE.T1_VERIFY_DELAY ; CMD_STATE.T1_SCAN_CRC ; CMD_STATE.T1_SCAN_TRACK ; CMD_STATE.T1_SPINDOWN ; CMD_STATE.T1_STEP_DELAY ; CMD_STATE.T1_TRAP ; CMD_STATE.T1_STEP ; CMD_STATE.T1_HEAD_CTRL ; CMD_STATE.T1_CHECK_DIR ; CMD_STATE.T1_COMP_TR_DSR ; CMD_STATE.T1_LOAD_SHFT ; CMD_STATE.T1_STEPPING ; CMD_STATE.T1_SEEK_RESTORE ; CMD_STATE.DECODE ; CMD_STATE.DELAY_15MS ; CMD_STATE.SPINUP ; CMD_STATE.INIT ; CMD_STATE.IDLE ;
++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
+; CMD_STATE.IDLE             ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 0              ;
+; CMD_STATE.INIT             ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 1              ; 1              ;
+; CMD_STATE.SPINUP           ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 1                ; 0              ; 1              ;
+; CMD_STATE.DELAY_15MS       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 1                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.DECODE           ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 1                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_SEEK_RESTORE  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 1                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_STEPPING      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 1                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 1                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_COMP_TR_DSR   ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 1                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_CHECK_DIR     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 1                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_HEAD_CTRL     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 1                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_STEP          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 1                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_TRAP          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 1                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_STEP_DELAY    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 1                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_SPINDOWN      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 1                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_SCAN_TRACK    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 1                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_SCAN_CRC      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 1                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_VERIFY_DELAY  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 1                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T1_VERIFY_CRC    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 1                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_RD_WR_SECT    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 1                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_INIT          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 1                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_SCAN_TRACK    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 1                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_SCAN_SECT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 1                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_SCAN_LEN      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 1                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_CRC_1  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 1                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 1                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_FIRSTBYTE     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 1                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_LOAD_DATA     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 1                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_NEXTBYTE      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 1                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_DRQ_1  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 1                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_RDSTAT        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 1                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_CRC_2  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 1                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_MULTISECT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 1                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_DELAY_B2      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 1                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_SET_DRQ       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 1                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_DELAY_B8      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 1                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_DRQ_2  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 1                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_DELAY_B1      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 1                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_CHECK_MODE    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 1                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_DELAY_B11     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 1                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WR_LEADIN     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 1                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WR_AM         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 1                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 1                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WR_BYTE       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 1                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_VERIFY_DRQ_3  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 1                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_DATALOST      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 1                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WRSTAT        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 1                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WR_CRC        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 1                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T2_WR_FF         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 1                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_WR            ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 1               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_DELAY_B3      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 1                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_VERIFY_DRQ    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 1                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_INDEX_1 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 1                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 1                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_WR_DATA       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 1                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_INDEX_2 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 1                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_DATALOST      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 1                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_RD_TRACK      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 1                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_SHIFT         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 1                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_INDEX_3 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 1                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_DETECT_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 1                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_BYTE    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 1                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_DR      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 1                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_LOAD_DATA_1   ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 1                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_SET_DRQ_1     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 1                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_RD_ADR        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 1                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_VERIFY_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 1                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_SHIFT_ADR     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 1                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_LOAD_DATA_2   ; 0                       ; 0                    ; 0                     ; 0                      ; 1                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_SET_DRQ_2     ; 0                       ; 0                    ; 0                     ; 1                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_CHECK_RD      ; 0                       ; 0                    ; 1                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_LOAD_SR       ; 0                       ; 1                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
+; CMD_STATE.T3_VERIFY_CRC    ; 1                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Protected by Synthesis                                                                                                                                                                                                                                         ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
+; Register Name                                                                                                                                            ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                    ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[1]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[0]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state                                    ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_data_state                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_nominal_state                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_nominal_state                                       ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_state                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state                                                   ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[2]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]                                                 ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[3]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_data_state                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_data_state                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_data_state                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_data_state                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_data_state                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_data_state                                       ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate3_state                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate_state                                            ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[8]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[7]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[6]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[5]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]                                                 ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[4]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]                                                 ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]                         ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_state                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_nominal_state                                       ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state                                       ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[17]                                              ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]                         ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[2]                                    ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[1]                                    ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[0]                                    ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[3]                                     ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[2]                                     ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[1]                                     ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_nominal_state                                      ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_state                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_state                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[0]                                     ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_nominal_state                                      ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state                                        ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_init_state                                           ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state                                        ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]                         ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]                                               ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]                         ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_ena_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_ena_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_ena_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_ena_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_ena_state                                                  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[5]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[5]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[6]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[6]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[6] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[6] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[7]  ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7] ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate2_state                                           ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]                         ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]                                              ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]                                               ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]                         ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]                          ; no                                                               ; yes                                        ;
+; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]                          ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8]                                               ; no                                                               ; yes                                        ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_seq_ena_state                                             ; no                                                               ; yes                                        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; User-Specified and Inferred Latches                                                                                                                                                    ;
++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
+; Latch Name                                                                         ; Latch Enable Signal                                                      ; Free of Timing Hazards ;
++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
+; Number of user-specified and inferred latches = 32                                 ;                                                                          ;                        ;
++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
+Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Register name                                                                                                                                                                         ; Reason for Removal                                                                                                                                                                   ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; interrupt_handler:nobody|INT_LATCH[31]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[31]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[30]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[30]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[29]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[29]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[28]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[28]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[27]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[27]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[26]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[26]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[25]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[25]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[24]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[24]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[23]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[23]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[22]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[22]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[21]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[21]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[20]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[20]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[19]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[19]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[18]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[18]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[17]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[17]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[16]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[16]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[15]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[15]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[14]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[14]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[13]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[13]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[12]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[12]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[11]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[11]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[10]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[10]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|INT_LATCH[7]                                                                                                                                                 ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
+; interrupt_handler:nobody|INT_CLEAR[7]                                                                                                                                                 ; Lost fanout                                                                                                                                                                          ;
+; interrupt_handler:nobody|WERTE[7][13]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
+; interrupt_handler:nobody|WERTE[6][10]                                                                                                                                                 ; Stuck at GND due to stuck port clear                                                                                                                                                 ;
+; interrupt_handler:nobody|WERTE[2][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
+; interrupt_handler:nobody|WERTE[1][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
+; interrupt_handler:nobody|WERTE[0][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20]                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20]                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_REQ                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In                                                         ; Lost fanout                                                                                                                                                                          ;
+; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0..6]                         ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP                                                                                 ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS                                   ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS                               ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP                                                                      ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA                                                                       ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR                                                                  ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]                                                               ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0..5]                                                            ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK                                                         ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0..7]                                         ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[6]                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0,2..5,7]                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[0..2]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[0..7]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SPER                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE                                                                 ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK                                                  ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0..2]                                                     ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6..7]                                                            ; Lost fanout                                                                                                                                                                          ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]                                                             ; Lost fanout                                                                                                                                                                          ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]                                                             ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]  ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10] ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10] ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]  ; Lost fanout                                                                                                                                                                          ;
+; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[2]                                                                                     ; Merged with Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                                        ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_OUT                                                             ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|OE                               ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\OVERRUN:FIRST_READ ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                                        ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ                           ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                                    ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ                       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[6]                                                               ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[7]                                                  ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[0..3]                                                            ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]                                                  ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_DRQ:LOCK                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_ACTIVE_I                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4,7]                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[1]                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe18                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe2                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe20                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe34                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe36                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe4                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|INT                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DRQ                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[0..7]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDRWR_D_SEL                                                                                                                                 ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                                                                                                                         ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[0..2]                                                                                                                                  ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]                                                                                                                        ;
+; Video:Fredi_Aschwanden|inst88                                                                                                                                                         ; Merged with Video:Fredi_Aschwanden|inst90                                                                                                                                            ;
+; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[0..2]                                                                                                              ; Merged with Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]                                                                                                    ;
+; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_AC                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[2]                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE                                                           ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1                                                     ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2                                                     ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3                                                     ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4                                                     ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE                                                          ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND                                                      ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV                                                  ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV                                                  ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns                                                   ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00                                                ; Lost fanout                                                                                                                                                                          ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DELAY_800ns                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[0..3]                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[0]                          ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                   ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]                                         ; Lost fanout                                                                                                                                                                          ;
+; Total Number of Removed Registers = 223                                                                                                                                               ;                                                                                                                                                                                      ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                         ;
++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Register name                                                                                                                                 ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                  ;
++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns            ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN,                                   ;
+;                                                                                                                                               ; due to stuck port data_in ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[2]                          ;
+; interrupt_handler:nobody|INT_LATCH[30]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[30]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[29]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[29]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[28]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[28]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[27]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[27]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[26]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[26]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[25]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[25]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[24]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[24]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[23]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[23]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[22]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[22]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[21]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[21]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[20]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[20]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[19]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[19]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[18]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[18]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[17]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[17]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[16]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[16]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[15]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[15]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[14]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[14]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[13]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[13]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[12]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[12]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[11]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[11]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[10]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[10]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[7]                                                                                                         ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[7]                                                                                                                   ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[17]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[16]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[9]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[8]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[1]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[20]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[20]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[19]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[18]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[17]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[16]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[12]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[11]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[10]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[9]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; interrupt_handler:nobody|INT_LATCH[31]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[31]                                                                                                                  ;
+;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[4]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[3]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[2]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[1]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[8]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In     ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]                                 ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2]                       ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]                                 ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0]                       ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE                                   ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn  ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[2]                                 ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In     ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS     ;
+;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 4612  ;
+; Number of registers using Synchronous Clear  ; 156   ;
+; Number of registers using Synchronous Load   ; 204   ;
+; Number of registers using Asynchronous Clear ; 1431  ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 2735  ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                                                               ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                                                                ; Fan out ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                ; 4       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[2]                                                                ; 5       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[1]                                                                ; 5       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0]                                                                ; 4       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT[7]                                                               ; 7       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE                                                                ; 7       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE                                                            ; 7       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IRQ_ACIAn                                                                                                                          ; 2       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb                     ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb                     ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0    ; 8       ;
+; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state                                                                                           ; 2       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_lsb_aeb                     ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_msb_aeb                     ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6       ; 4       ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                                                            ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|counter8a0    ; 8       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|parity9       ; 4       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; 1       ;
+; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; 1       ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                                               ; 7       ;
+; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                                                  ; 3       ;
+; Total number of inverted registers = 22                                                                                                                                                          ;         ;
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                      ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[7]                                           ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]                                  ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[0]    ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]           ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]                              ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                             ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]                                     ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]                          ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                         ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]                                 ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]                                          ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]                                            ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[4]                                     ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[4]                                     ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[7]                                     ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[6]                                     ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]                  ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]                                   ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                            ;
+; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]                                            ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]                                   ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2]                                      ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT[0]             ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]                               ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[0]                                  ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:CLK_DIVCNT[0] ;
+; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_START_BIT:TMP[0]    ;
+; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:LOW_FLT[0]   ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[3]  ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[0]                                        ;
+; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                    ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]                                    ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]                                ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]                                  ;
+; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]                                      ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]                                                                                                   ;
+; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]              ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[7]                                                 ;
+; 5:1                ; 21 bits   ; 63 LEs        ; 42 LEs               ; 21 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                              ;
+; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[19]                             ;
+; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]          ;
+; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]                                ;
+; 4:1                ; 31 bits   ; 62 LEs        ; 62 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                         ;
+; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:TIMER[1]     ;
+; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]                                             ;
+; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[5]                                     ;
+; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[2]                                     ;
+; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[1]                                     ;
+; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[5]                                     ;
+; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3]                                                  ;
+; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]                                                  ;
+; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]                          ;
+; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]                            ;
+; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]                      ;
+; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]                        ;
+; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]                                            ;
+; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                  ;
+; 7:1                ; 13 bits   ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[10]                                           ;
+; 6:1                ; 20 bits   ; 80 LEs        ; 20 LEs               ; 60 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]                                          ;
+; 11:1               ; 2 bits    ; 14 LEs        ; 10 LEs               ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]                      ;
+; 8:1                ; 5 bits    ; 25 LEs        ; 20 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]                  ;
+; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]                                            ;
+; 14:1               ; 5 bits    ; 45 LEs        ; 10 LEs               ; 35 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]                                                  ;
+; 11:1               ; 8 bits    ; 56 LEs        ; 16 LEs               ; 40 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B[1]                                                  ;
+; 11:1               ; 8 bits    ; 56 LEs        ; 16 LEs               ; 40 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A[1]                                                  ;
+; 17:1               ; 4 bits    ; 44 LEs        ; 40 LEs               ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[2]                                      ;
+; 17:1               ; 4 bits    ; 44 LEs        ; 0 LEs                ; 44 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7]                                      ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]                                                                                                    ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]                                                                                                    ;
+; 3:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]                                                                                                ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                               ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0]                                           ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                   ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_NEXT_STATE         ;
+; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                   ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEXCNT                                                    ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]                                                                                                     ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|DATA_OUT[4]                                                                  ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[1]                                                                      ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT                                                         ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE                                   ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE                               ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|NEXT_CMD_STATE                                              ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_A[1]                                              ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_B[2]                                              ;
+; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_C[1]                                              ;
+; 16:1               ; 8 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|DATA_OUT[2]                                                                            ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ADDER_IN[1]                                         ;
+; 64:1               ; 3 bits    ; 126 LEs       ; 126 LEs              ; 0 LEs                  ; No         ; |firebee1|interrupt_handler:nobody|_                                                                                                                                                  ;
+; 17:1               ; 3 bits    ; 33 LEs        ; 18 LEs               ; 15 LEs                 ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[7]                                                                            ;
+; 18:1               ; 4 bits    ; 48 LEs        ; 44 LEs               ; 4 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[2]                                                                            ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+; Assignment                            ; Value                                                                               ; From            ; To                            ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                             ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                             ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                                                                                   ; -               ; -                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb         ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb         ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb         ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb         ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                   ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg    ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg    ;
+; SUPPRESS_DA_RULE_INTERNAL             ; S102                                                                                ; -               ; wrptr_g                       ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                   ;
+; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe17|dffe18a     ;
+; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*          ; -               ; -                             ;
+; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a     ;
+; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*  ; -               ; -                             ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                                                                        ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                                ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                   ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                                                                                             ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                                                                              ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; sub_parity9a0                                                                                                                                                  ;
+; POWER_UP_LEVEL            ; LOW   ; -    ; parity8                                                                                                                                                        ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                                                                       ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                        ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                              ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                              ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+; Assignment                            ; Value                                                                               ; From            ; To                            ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                             ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                             ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                                                                                   ; -               ; -                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb         ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb         ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb         ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb         ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                   ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg    ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg    ;
+; SUPPRESS_DA_RULE_INTERNAL             ; S102                                                                                ; -               ; wrptr_g                       ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                   ;
+; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe15|dffe16a     ;
+; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*          ; -               ; -                             ;
+; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a     ;
+; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*  ; -               ; -                             ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                                                                        ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity6a0                                                                                                                                                             ;
+; POWER_UP_LEVEL ; LOW   ; -    ; parity5                                                                                                                                                                   ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                                                                                             ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                                                                              ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; counter8a0                                                                                                                                                     ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; parity9                                                                                                                                                        ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                                                                       ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                        ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                              ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                              ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------+
+; Assignment                      ; Value ; From ; To                                     ;
++---------------------------------+-------+------+----------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                      ;
++---------------------------------+-------+------+----------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                         ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
+; Assignment                            ; Value                                                                               ; From            ; To                         ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                          ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                          ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                          ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 4                                                                                   ; -               ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL             ; R105                                                                                ; -               ; -                          ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb      ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb      ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb      ;
+; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb      ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg ;
+; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                ;
+; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe22|dffe23a  ;
+; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe22|dffe23a*          ; -               ; -                          ;
+; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a  ;
+; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe15|dffe16a*  ; -               ; -                          ;
++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                             ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                     ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                        ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                                  ;
++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                   ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; counter8a0                                                                                          ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; parity9                                                                                             ;
++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                                 ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                  ;
+; POWER_UP_LEVEL            ; HIGH  ; -    ; sub_parity12a0                                                                                     ;
+; POWER_UP_LEVEL            ; LOW   ; -    ; parity11                                                                                           ;
++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                            ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                             ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                              ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                               ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                               ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                  ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                              ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                               ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                               ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                  ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ;
++---------------------------+-------------+------+---------------------------------------------------------+
+; Assignment                ; Value       ; From ; To                                                      ;
++---------------------------+-------------+------+---------------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                       ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                           ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                           ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                                     ;
+; DDIO_INPUT_REGISTER       ; LOW         ; -    ; input_cell_L                                            ;
+; DDIO_INPUT_REGISTER       ; HIGH        ; -    ; input_cell_H                                            ;
+; SUPPRESS_DA_RULE_INTERNAL ; D101        ; -    ; -                                                       ;
+; SUPPRESS_DA_RULE_INTERNAL ; D103        ; -    ; -                                                       ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                       ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                       ;
+; SUPPRESS_DA_RULE_INTERNAL ; D102        ; -    ; -                                                       ;
++---------------------------+-------------+------+---------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ;
++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                                                        ;
++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL   ; C106  ; -    ; -                                                                                         ;
+; DDIO_INPUT_REGISTER         ; HIGH  ; -    ; input_cell_h                                                                              ;
+; DDIO_INPUT_REGISTER         ; LOW   ; -    ; input_cell_l                                                                              ;
+; MEGAFUNCTION_GENERATED_TRI  ; ON    ; -    ; tri_buf1a                                                                                 ;
++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                       ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                        ;
++---------------------------------+--------------------+------+--------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                                ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                 ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                         ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                          ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                        ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                         ;
++---------------------------------+--------------------+------+---------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                   ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                    ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                     ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                    ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                      ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                      ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                    ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
++---------------------------------+--------------------+------+-----------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+---------------------------------------------------+
+; Assignment                ; Value       ; From ; To                                                ;
++---------------------------+-------------+------+---------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                 ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                     ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                     ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                               ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                 ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                 ;
++---------------------------+-------------+------+---------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                                                ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                 ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+---------------------------------------------------+
+; Assignment                ; Value       ; From ; To                                                ;
++---------------------------+-------------+------+---------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                 ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                     ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                     ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                               ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                 ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                 ;
++---------------------------+-------------+------+---------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                                                ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                 ;
++-----------------------------+-------+------+-----------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------+
+; Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ;
++---------------------------+-------+------+-----------------------------------------------+
+; Assignment                ; Value ; From ; To                                            ;
++---------------------------+-------+------+-----------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; C104  ; -    ; -                                             ;
++---------------------------+-------+------+-----------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ;
++---------------------------------------+-------------+------+------------------------------------------------------+
+; Assignment                            ; Value       ; From ; To                                                   ;
++---------------------------------------+-------------+------+------------------------------------------------------+
+; ADV_NETLIST_OPT_ALLOWED               ; NEVER_ALLOW ; -    ; -                                                    ;
+; SUPPRESS_DA_RULE_INTERNAL             ; C106        ; -    ; -                                                    ;
+; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 2           ; -    ; le_comb10                                            ;
+; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 0           ; -    ; le_comb8                                             ;
+; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 1           ; -    ; le_comb9                                             ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; idle_state                                           ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_data_nominal_state                              ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_data_state                                      ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_first_nominal_state                             ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_first_state                                     ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_init_nominal_state                              ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_init_state                                      ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_last_nominal_state                              ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; read_last_state                                      ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_counter_state                               ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_init_state                                  ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_post_state                                  ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_seq_data_state                              ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_seq_ena_state                               ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_wait_state                                  ;
+; POWER_UP_LEVEL                        ; HIGH        ; -    ; reset_state                                          ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; write_data_state                                     ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; write_init_nominal_state                             ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; write_init_state                                     ;
+; POWER_UP_LEVEL                        ; LOW         ; -    ; write_nominal_state                                  ;
++---------------------------------------+-------------+------+------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                                       ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                        ;
++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                       ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                        ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                        ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                        ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                        ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
++---------------------------+-------+------+-------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                       ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; Assignment                ; Value ; From ; To                                                                                       ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
++---------------------------+-------+------+------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component ;
++---------------------------+-------+------+-----------------------------------+
+; Assignment                ; Value ; From ; To                                ;
++---------------------------+-------+------+-----------------------------------+
+; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                 ;
+; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                 ;
+; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                 ;
++---------------------------+-------+------+-----------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+----------------------------+
+; Assignment                ; Value       ; From ; To                         ;
++---------------------------+-------------+------+----------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
++---------------------------+-------------+------+----------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                         ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
++-----------------------------+-------+------+------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+----------------------------+
+; Assignment                ; Value       ; From ; To                         ;
++---------------------------+-------------+------+----------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
++---------------------------+-------------+------+----------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                         ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
++-----------------------------+-------+------+------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+----------------------------+
+; Assignment                ; Value       ; From ; To                         ;
++---------------------------+-------------+------+----------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
++---------------------------+-------------+------+----------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                         ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
++-----------------------------+-------+------+------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component ;
++---------------------------+-------------+------+----------------------------+
+; Assignment                ; Value       ; From ; To                         ;
++---------------------------+-------------+------+----------------------------+
+; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
+; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
+; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
+; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
+; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
++---------------------------+-------------+------+----------------------------+
+
+
++---------------------------------------------------------------------------------------------------------+
+; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; Assignment                  ; Value ; From ; To                                                         ;
++-----------------------------+-------+------+------------------------------------------------------------+
+; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
++-----------------------------+-------+------+------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component ;
++-------------------------------+--------------------+------------------------------+
+; Parameter Name                ; Value              ; Type                         ;
++-------------------------------+--------------------+------------------------------+
+; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                      ;
+; PLL_TYPE                      ; AUTO               ; Untyped                      ;
+; QUALIFY_CONF_DONE             ; OFF                ; Untyped                      ;
+; COMPENSATE_CLOCK              ; CLK0               ; Untyped                      ;
+; SCAN_CHAIN                    ; LONG               ; Untyped                      ;
+; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                      ;
+; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer               ;
+; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                      ;
+; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                      ;
+; GATE_LOCK_COUNTER             ; 0                  ; Untyped                      ;
+; LOCK_HIGH                     ; 1                  ; Untyped                      ;
+; LOCK_LOW                      ; 1                  ; Untyped                      ;
+; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                      ;
+; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                      ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                      ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                      ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                      ;
+; SKIP_VCO                      ; OFF                ; Untyped                      ;
+; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                      ;
+; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                      ;
+; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                      ;
+; BANDWIDTH                     ; 0                  ; Untyped                      ;
+; BANDWIDTH_TYPE                ; AUTO               ; Untyped                      ;
+; SPREAD_FREQUENCY              ; 0                  ; Untyped                      ;
+; DOWN_SPREAD                   ; 0                  ; Untyped                      ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                      ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                      ;
+; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                      ;
+; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                      ;
+; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                      ;
+; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                      ;
+; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                      ;
+; CLK4_MULTIPLY_BY              ; 1                  ; Untyped                      ;
+; CLK3_MULTIPLY_BY              ; 1                  ; Untyped                      ;
+; CLK2_MULTIPLY_BY              ; 67                 ; Signed Integer               ;
+; CLK1_MULTIPLY_BY              ; 67                 ; Signed Integer               ;
+; CLK0_MULTIPLY_BY              ; 1                  ; Signed Integer               ;
+; CLK9_DIVIDE_BY                ; 0                  ; Untyped                      ;
+; CLK8_DIVIDE_BY                ; 0                  ; Untyped                      ;
+; CLK7_DIVIDE_BY                ; 0                  ; Untyped                      ;
+; CLK6_DIVIDE_BY                ; 0                  ; Untyped                      ;
+; CLK5_DIVIDE_BY                ; 1                  ; Untyped                      ;
+; CLK4_DIVIDE_BY                ; 1                  ; Untyped                      ;
+; CLK3_DIVIDE_BY                ; 1                  ; Untyped                      ;
+; CLK2_DIVIDE_BY                ; 90                 ; Signed Integer               ;
+; CLK1_DIVIDE_BY                ; 900                ; Signed Integer               ;
+; CLK0_DIVIDE_BY                ; 66                 ; Signed Integer               ;
+; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK4_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK3_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK2_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK0_PHASE_SHIFT              ; 0                  ; Untyped                      ;
+; CLK5_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK4_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK3_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK2_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK1_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK0_TIME_DELAY               ; 0                  ; Untyped                      ;
+; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK4_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK3_DUTY_CYCLE               ; 50                 ; Untyped                      ;
+; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
+; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
+; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
+; LOCK_WINDOW_UI                ;  0.05              ; Untyped                      ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                      ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                      ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                      ;
+; DPA_MULTIPLY_BY               ; 0                  ; Untyped                      ;
+; DPA_DIVIDE_BY                 ; 1                  ; Untyped                      ;
+; DPA_DIVIDER                   ; 0                  ; Untyped                      ;
+; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                      ;
+; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                      ;
+; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                      ;
+; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                      ;
+; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                      ;
+; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                      ;
+; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                      ;
+; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                      ;
+; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                      ;
+; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                      ;
+; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                      ;
+; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                      ;
+; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                      ;
+; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                      ;
+; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                      ;
+; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                      ;
+; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                      ;
+; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                      ;
+; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                      ;
+; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                      ;
+; VCO_MULTIPLY_BY               ; 0                  ; Untyped                      ;
+; VCO_DIVIDE_BY                 ; 0                  ; Untyped                      ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                      ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                      ;
+; VCO_MIN                       ; 0                  ; Untyped                      ;
+; VCO_MAX                       ; 0                  ; Untyped                      ;
+; VCO_CENTER                    ; 0                  ; Untyped                      ;
+; PFD_MIN                       ; 0                  ; Untyped                      ;
+; PFD_MAX                       ; 0                  ; Untyped                      ;
+; M_INITIAL                     ; 0                  ; Untyped                      ;
+; M                             ; 0                  ; Untyped                      ;
+; N                             ; 1                  ; Untyped                      ;
+; M2                            ; 1                  ; Untyped                      ;
+; N2                            ; 1                  ; Untyped                      ;
+; SS                            ; 1                  ; Untyped                      ;
+; C0_HIGH                       ; 0                  ; Untyped                      ;
+; C1_HIGH                       ; 0                  ; Untyped                      ;
+; C2_HIGH                       ; 0                  ; Untyped                      ;
+; C3_HIGH                       ; 0                  ; Untyped                      ;
+; C4_HIGH                       ; 0                  ; Untyped                      ;
+; C5_HIGH                       ; 0                  ; Untyped                      ;
+; C6_HIGH                       ; 0                  ; Untyped                      ;
+; C7_HIGH                       ; 0                  ; Untyped                      ;
+; C8_HIGH                       ; 0                  ; Untyped                      ;
+; C9_HIGH                       ; 0                  ; Untyped                      ;
+; C0_LOW                        ; 0                  ; Untyped                      ;
+; C1_LOW                        ; 0                  ; Untyped                      ;
+; C2_LOW                        ; 0                  ; Untyped                      ;
+; C3_LOW                        ; 0                  ; Untyped                      ;
+; C4_LOW                        ; 0                  ; Untyped                      ;
+; C5_LOW                        ; 0                  ; Untyped                      ;
+; C6_LOW                        ; 0                  ; Untyped                      ;
+; C7_LOW                        ; 0                  ; Untyped                      ;
+; C8_LOW                        ; 0                  ; Untyped                      ;
+; C9_LOW                        ; 0                  ; Untyped                      ;
+; C0_INITIAL                    ; 0                  ; Untyped                      ;
+; C1_INITIAL                    ; 0                  ; Untyped                      ;
+; C2_INITIAL                    ; 0                  ; Untyped                      ;
+; C3_INITIAL                    ; 0                  ; Untyped                      ;
+; C4_INITIAL                    ; 0                  ; Untyped                      ;
+; C5_INITIAL                    ; 0                  ; Untyped                      ;
+; C6_INITIAL                    ; 0                  ; Untyped                      ;
+; C7_INITIAL                    ; 0                  ; Untyped                      ;
+; C8_INITIAL                    ; 0                  ; Untyped                      ;
+; C9_INITIAL                    ; 0                  ; Untyped                      ;
+; C0_MODE                       ; BYPASS             ; Untyped                      ;
+; C1_MODE                       ; BYPASS             ; Untyped                      ;
+; C2_MODE                       ; BYPASS             ; Untyped                      ;
+; C3_MODE                       ; BYPASS             ; Untyped                      ;
+; C4_MODE                       ; BYPASS             ; Untyped                      ;
+; C5_MODE                       ; BYPASS             ; Untyped                      ;
+; C6_MODE                       ; BYPASS             ; Untyped                      ;
+; C7_MODE                       ; BYPASS             ; Untyped                      ;
+; C8_MODE                       ; BYPASS             ; Untyped                      ;
+; C9_MODE                       ; BYPASS             ; Untyped                      ;
+; C0_PH                         ; 0                  ; Untyped                      ;
+; C1_PH                         ; 0                  ; Untyped                      ;
+; C2_PH                         ; 0                  ; Untyped                      ;
+; C3_PH                         ; 0                  ; Untyped                      ;
+; C4_PH                         ; 0                  ; Untyped                      ;
+; C5_PH                         ; 0                  ; Untyped                      ;
+; C6_PH                         ; 0                  ; Untyped                      ;
+; C7_PH                         ; 0                  ; Untyped                      ;
+; C8_PH                         ; 0                  ; Untyped                      ;
+; C9_PH                         ; 0                  ; Untyped                      ;
+; L0_HIGH                       ; 1                  ; Untyped                      ;
+; L1_HIGH                       ; 1                  ; Untyped                      ;
+; G0_HIGH                       ; 1                  ; Untyped                      ;
+; G1_HIGH                       ; 1                  ; Untyped                      ;
+; G2_HIGH                       ; 1                  ; Untyped                      ;
+; G3_HIGH                       ; 1                  ; Untyped                      ;
+; E0_HIGH                       ; 1                  ; Untyped                      ;
+; E1_HIGH                       ; 1                  ; Untyped                      ;
+; E2_HIGH                       ; 1                  ; Untyped                      ;
+; E3_HIGH                       ; 1                  ; Untyped                      ;
+; L0_LOW                        ; 1                  ; Untyped                      ;
+; L1_LOW                        ; 1                  ; Untyped                      ;
+; G0_LOW                        ; 1                  ; Untyped                      ;
+; G1_LOW                        ; 1                  ; Untyped                      ;
+; G2_LOW                        ; 1                  ; Untyped                      ;
+; G3_LOW                        ; 1                  ; Untyped                      ;
+; E0_LOW                        ; 1                  ; Untyped                      ;
+; E1_LOW                        ; 1                  ; Untyped                      ;
+; E2_LOW                        ; 1                  ; Untyped                      ;
+; E3_LOW                        ; 1                  ; Untyped                      ;
+; L0_INITIAL                    ; 1                  ; Untyped                      ;
+; L1_INITIAL                    ; 1                  ; Untyped                      ;
+; G0_INITIAL                    ; 1                  ; Untyped                      ;
+; G1_INITIAL                    ; 1                  ; Untyped                      ;
+; G2_INITIAL                    ; 1                  ; Untyped                      ;
+; G3_INITIAL                    ; 1                  ; Untyped                      ;
+; E0_INITIAL                    ; 1                  ; Untyped                      ;
+; E1_INITIAL                    ; 1                  ; Untyped                      ;
+; E2_INITIAL                    ; 1                  ; Untyped                      ;
+; E3_INITIAL                    ; 1                  ; Untyped                      ;
+; L0_MODE                       ; BYPASS             ; Untyped                      ;
+; L1_MODE                       ; BYPASS             ; Untyped                      ;
+; G0_MODE                       ; BYPASS             ; Untyped                      ;
+; G1_MODE                       ; BYPASS             ; Untyped                      ;
+; G2_MODE                       ; BYPASS             ; Untyped                      ;
+; G3_MODE                       ; BYPASS             ; Untyped                      ;
+; E0_MODE                       ; BYPASS             ; Untyped                      ;
+; E1_MODE                       ; BYPASS             ; Untyped                      ;
+; E2_MODE                       ; BYPASS             ; Untyped                      ;
+; E3_MODE                       ; BYPASS             ; Untyped                      ;
+; L0_PH                         ; 0                  ; Untyped                      ;
+; L1_PH                         ; 0                  ; Untyped                      ;
+; G0_PH                         ; 0                  ; Untyped                      ;
+; G1_PH                         ; 0                  ; Untyped                      ;
+; G2_PH                         ; 0                  ; Untyped                      ;
+; G3_PH                         ; 0                  ; Untyped                      ;
+; E0_PH                         ; 0                  ; Untyped                      ;
+; E1_PH                         ; 0                  ; Untyped                      ;
+; E2_PH                         ; 0                  ; Untyped                      ;
+; E3_PH                         ; 0                  ; Untyped                      ;
+; M_PH                          ; 0                  ; Untyped                      ;
+; C1_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C2_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C3_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C4_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C5_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C6_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C7_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C8_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; C9_USE_CASC_IN                ; OFF                ; Untyped                      ;
+; CLK0_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK1_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK2_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK3_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK4_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK5_COUNTER                  ; G0                 ; Untyped                      ;
+; CLK6_COUNTER                  ; E0                 ; Untyped                      ;
+; CLK7_COUNTER                  ; E1                 ; Untyped                      ;
+; CLK8_COUNTER                  ; E2                 ; Untyped                      ;
+; CLK9_COUNTER                  ; E3                 ; Untyped                      ;
+; L0_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; L1_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; G0_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; G1_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; G2_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; G3_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; E0_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; E1_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; E2_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; E3_TIME_DELAY                 ; 0                  ; Untyped                      ;
+; M_TIME_DELAY                  ; 0                  ; Untyped                      ;
+; N_TIME_DELAY                  ; 0                  ; Untyped                      ;
+; EXTCLK3_COUNTER               ; E3                 ; Untyped                      ;
+; EXTCLK2_COUNTER               ; E2                 ; Untyped                      ;
+; EXTCLK1_COUNTER               ; E1                 ; Untyped                      ;
+; EXTCLK0_COUNTER               ; E0                 ; Untyped                      ;
+; ENABLE0_COUNTER               ; L0                 ; Untyped                      ;
+; ENABLE1_COUNTER               ; L0                 ; Untyped                      ;
+; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                      ;
+; LOOP_FILTER_R                 ;  1.000000          ; Untyped                      ;
+; LOOP_FILTER_C                 ; 5                  ; Untyped                      ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                      ;
+; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                      ;
+; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                      ;
+; VCO_POST_SCALE                ; 0                  ; Untyped                      ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                      ;
+; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK0                     ; PORT_USED          ; Untyped                      ;
+; PORT_CLK1                     ; PORT_USED          ; Untyped                      ;
+; PORT_CLK2                     ; PORT_USED          ; Untyped                      ;
+; PORT_CLK3                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK4                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                      ;
+; PORT_INCLK0                   ; PORT_USED          ; Untyped                      ;
+; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                      ;
+; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                      ;
+; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                      ;
+; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                      ;
+; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                      ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_LOCKED                   ; PORT_USED          ; Untyped                      ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                      ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                      ;
+; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                      ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                      ;
+; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                      ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                      ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                      ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                      ;
+; M_TEST_SOURCE                 ; 5                  ; Untyped                      ;
+; C0_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C1_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C2_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C3_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C4_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C5_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C6_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C7_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C8_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; C9_TEST_SOURCE                ; 5                  ; Untyped                      ;
+; CBXI_PARAMETER                ; altpll_pul2        ; Untyped                      ;
+; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                      ;
+; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                      ;
+; WIDTH_CLOCK                   ; 5                  ; Signed Integer               ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                      ;
+; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                      ;
+; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                      ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                      ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                      ;
+; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                   ;
+; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                 ;
+; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                 ;
+; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE               ;
++-------------------------------+--------------------+------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Name           ; Value       ; Type                                                                                                                            ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+; ACF_DISABLE_MLAB_RAM_USE ; FALSE       ; Untyped                                                                                                                         ;
+; ADD_RAM_OUTPUT_REGISTER  ; OFF         ; Untyped                                                                                                                         ;
+; ADD_USEDW_MSB_BIT        ; OFF         ; Untyped                                                                                                                         ;
+; CLOCKS_ARE_SYNCHRONIZED  ; FALSE       ; Untyped                                                                                                                         ;
+; DELAY_RDUSEDW            ; 1           ; Untyped                                                                                                                         ;
+; DELAY_WRUSEDW            ; 1           ; Untyped                                                                                                                         ;
+; LPM_NUMWORDS             ; 1024        ; Signed Integer                                                                                                                  ;
+; LPM_SHOWAHEAD            ; OFF         ; Untyped                                                                                                                         ;
+; LPM_WIDTH                ; 8           ; Signed Integer                                                                                                                  ;
+; LPM_WIDTH_R              ; 32          ; Signed Integer                                                                                                                  ;
+; LPM_WIDTHU               ; 10          ; Signed Integer                                                                                                                  ;
+; LPM_WIDTHU_R             ; 8           ; Signed Integer                                                                                                                  ;
+; MAXIMIZE_SPEED           ; 5           ; Untyped                                                                                                                         ;
+; OVERFLOW_CHECKING        ; ON          ; Untyped                                                                                                                         ;
+; RAM_BLOCK_TYPE           ; AUTO        ; Untyped                                                                                                                         ;
+; RDSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
+; UNDERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                         ;
+; USE_EAB                  ; ON          ; Untyped                                                                                                                         ;
+; WRITE_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                         ;
+; WRSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
+; CBXI_PARAMETER           ; dcfifo_0hh1 ; Untyped                                                                                                                         ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Name           ; Value       ; Type                                                                                                                            ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+; ACF_DISABLE_MLAB_RAM_USE ; FALSE       ; Untyped                                                                                                                         ;
+; ADD_RAM_OUTPUT_REGISTER  ; OFF         ; Untyped                                                                                                                         ;
+; ADD_USEDW_MSB_BIT        ; OFF         ; Untyped                                                                                                                         ;
+; CLOCKS_ARE_SYNCHRONIZED  ; FALSE       ; Untyped                                                                                                                         ;
+; DELAY_RDUSEDW            ; 1           ; Untyped                                                                                                                         ;
+; DELAY_WRUSEDW            ; 1           ; Untyped                                                                                                                         ;
+; LPM_NUMWORDS             ; 256         ; Signed Integer                                                                                                                  ;
+; LPM_SHOWAHEAD            ; OFF         ; Untyped                                                                                                                         ;
+; LPM_WIDTH                ; 32          ; Signed Integer                                                                                                                  ;
+; LPM_WIDTH_R              ; 8           ; Signed Integer                                                                                                                  ;
+; LPM_WIDTHU               ; 8           ; Signed Integer                                                                                                                  ;
+; LPM_WIDTHU_R             ; 10          ; Signed Integer                                                                                                                  ;
+; MAXIMIZE_SPEED           ; 5           ; Untyped                                                                                                                         ;
+; OVERFLOW_CHECKING        ; ON          ; Untyped                                                                                                                         ;
+; RAM_BLOCK_TYPE           ; AUTO        ; Untyped                                                                                                                         ;
+; RDSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
+; UNDERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                         ;
+; USE_EAB                  ; ON          ; Untyped                                                                                                                         ;
+; WRITE_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                         ;
+; WRSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
+; CBXI_PARAMETER           ; dcfifo_3fh1 ; Untyped                                                                                                                         ;
++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ;
++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                                                        ;
++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
+; TOP            ; 152   ; Signed Integer                                                                                                                              ;
+; BOTTOM         ; 104   ; Signed Integer                                                                                                                              ;
+; PHASE_CORR     ; 75    ; Signed Integer                                                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component ;
++-------------------------------+--------------------+--------------------------------+
+; Parameter Name                ; Value              ; Type                           ;
++-------------------------------+--------------------+--------------------------------+
+; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                        ;
+; PLL_TYPE                      ; AUTO               ; Untyped                        ;
+; QUALIFY_CONF_DONE             ; OFF                ; Untyped                        ;
+; COMPENSATE_CLOCK              ; CLK1               ; Untyped                        ;
+; SCAN_CHAIN                    ; LONG               ; Untyped                        ;
+; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                        ;
+; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer                 ;
+; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                        ;
+; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                        ;
+; GATE_LOCK_COUNTER             ; 0                  ; Untyped                        ;
+; LOCK_HIGH                     ; 1                  ; Untyped                        ;
+; LOCK_LOW                      ; 1                  ; Untyped                        ;
+; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                        ;
+; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                        ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                        ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                        ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                        ;
+; SKIP_VCO                      ; OFF                ; Untyped                        ;
+; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                        ;
+; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                        ;
+; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                        ;
+; BANDWIDTH                     ; 0                  ; Untyped                        ;
+; BANDWIDTH_TYPE                ; AUTO               ; Untyped                        ;
+; SPREAD_FREQUENCY              ; 0                  ; Untyped                        ;
+; DOWN_SPREAD                   ; 0                  ; Untyped                        ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                        ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                        ;
+; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                        ;
+; CLK4_MULTIPLY_BY              ; 1                  ; Untyped                        ;
+; CLK3_MULTIPLY_BY              ; 16                 ; Signed Integer                 ;
+; CLK2_MULTIPLY_BY              ; 25                 ; Signed Integer                 ;
+; CLK1_MULTIPLY_BY              ; 16                 ; Signed Integer                 ;
+; CLK0_MULTIPLY_BY              ; 2                  ; Signed Integer                 ;
+; CLK9_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK8_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK7_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK6_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK5_DIVIDE_BY                ; 1                  ; Untyped                        ;
+; CLK4_DIVIDE_BY                ; 1                  ; Untyped                        ;
+; CLK3_DIVIDE_BY                ; 11                 ; Signed Integer                 ;
+; CLK2_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
+; CLK1_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
+; CLK0_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
+; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK4_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK3_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK2_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK0_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK5_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK4_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK3_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK2_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK1_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK0_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK4_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK3_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; LOCK_WINDOW_UI                ;  0.05              ; Untyped                        ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                        ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                        ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                        ;
+; DPA_MULTIPLY_BY               ; 0                  ; Untyped                        ;
+; DPA_DIVIDE_BY                 ; 1                  ; Untyped                        ;
+; DPA_DIVIDER                   ; 0                  ; Untyped                        ;
+; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; VCO_MULTIPLY_BY               ; 0                  ; Untyped                        ;
+; VCO_DIVIDE_BY                 ; 0                  ; Untyped                        ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                        ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                        ;
+; VCO_MIN                       ; 0                  ; Untyped                        ;
+; VCO_MAX                       ; 0                  ; Untyped                        ;
+; VCO_CENTER                    ; 0                  ; Untyped                        ;
+; PFD_MIN                       ; 0                  ; Untyped                        ;
+; PFD_MAX                       ; 0                  ; Untyped                        ;
+; M_INITIAL                     ; 0                  ; Untyped                        ;
+; M                             ; 0                  ; Untyped                        ;
+; N                             ; 1                  ; Untyped                        ;
+; M2                            ; 1                  ; Untyped                        ;
+; N2                            ; 1                  ; Untyped                        ;
+; SS                            ; 1                  ; Untyped                        ;
+; C0_HIGH                       ; 0                  ; Untyped                        ;
+; C1_HIGH                       ; 0                  ; Untyped                        ;
+; C2_HIGH                       ; 0                  ; Untyped                        ;
+; C3_HIGH                       ; 0                  ; Untyped                        ;
+; C4_HIGH                       ; 0                  ; Untyped                        ;
+; C5_HIGH                       ; 0                  ; Untyped                        ;
+; C6_HIGH                       ; 0                  ; Untyped                        ;
+; C7_HIGH                       ; 0                  ; Untyped                        ;
+; C8_HIGH                       ; 0                  ; Untyped                        ;
+; C9_HIGH                       ; 0                  ; Untyped                        ;
+; C0_LOW                        ; 0                  ; Untyped                        ;
+; C1_LOW                        ; 0                  ; Untyped                        ;
+; C2_LOW                        ; 0                  ; Untyped                        ;
+; C3_LOW                        ; 0                  ; Untyped                        ;
+; C4_LOW                        ; 0                  ; Untyped                        ;
+; C5_LOW                        ; 0                  ; Untyped                        ;
+; C6_LOW                        ; 0                  ; Untyped                        ;
+; C7_LOW                        ; 0                  ; Untyped                        ;
+; C8_LOW                        ; 0                  ; Untyped                        ;
+; C9_LOW                        ; 0                  ; Untyped                        ;
+; C0_INITIAL                    ; 0                  ; Untyped                        ;
+; C1_INITIAL                    ; 0                  ; Untyped                        ;
+; C2_INITIAL                    ; 0                  ; Untyped                        ;
+; C3_INITIAL                    ; 0                  ; Untyped                        ;
+; C4_INITIAL                    ; 0                  ; Untyped                        ;
+; C5_INITIAL                    ; 0                  ; Untyped                        ;
+; C6_INITIAL                    ; 0                  ; Untyped                        ;
+; C7_INITIAL                    ; 0                  ; Untyped                        ;
+; C8_INITIAL                    ; 0                  ; Untyped                        ;
+; C9_INITIAL                    ; 0                  ; Untyped                        ;
+; C0_MODE                       ; BYPASS             ; Untyped                        ;
+; C1_MODE                       ; BYPASS             ; Untyped                        ;
+; C2_MODE                       ; BYPASS             ; Untyped                        ;
+; C3_MODE                       ; BYPASS             ; Untyped                        ;
+; C4_MODE                       ; BYPASS             ; Untyped                        ;
+; C5_MODE                       ; BYPASS             ; Untyped                        ;
+; C6_MODE                       ; BYPASS             ; Untyped                        ;
+; C7_MODE                       ; BYPASS             ; Untyped                        ;
+; C8_MODE                       ; BYPASS             ; Untyped                        ;
+; C9_MODE                       ; BYPASS             ; Untyped                        ;
+; C0_PH                         ; 0                  ; Untyped                        ;
+; C1_PH                         ; 0                  ; Untyped                        ;
+; C2_PH                         ; 0                  ; Untyped                        ;
+; C3_PH                         ; 0                  ; Untyped                        ;
+; C4_PH                         ; 0                  ; Untyped                        ;
+; C5_PH                         ; 0                  ; Untyped                        ;
+; C6_PH                         ; 0                  ; Untyped                        ;
+; C7_PH                         ; 0                  ; Untyped                        ;
+; C8_PH                         ; 0                  ; Untyped                        ;
+; C9_PH                         ; 0                  ; Untyped                        ;
+; L0_HIGH                       ; 1                  ; Untyped                        ;
+; L1_HIGH                       ; 1                  ; Untyped                        ;
+; G0_HIGH                       ; 1                  ; Untyped                        ;
+; G1_HIGH                       ; 1                  ; Untyped                        ;
+; G2_HIGH                       ; 1                  ; Untyped                        ;
+; G3_HIGH                       ; 1                  ; Untyped                        ;
+; E0_HIGH                       ; 1                  ; Untyped                        ;
+; E1_HIGH                       ; 1                  ; Untyped                        ;
+; E2_HIGH                       ; 1                  ; Untyped                        ;
+; E3_HIGH                       ; 1                  ; Untyped                        ;
+; L0_LOW                        ; 1                  ; Untyped                        ;
+; L1_LOW                        ; 1                  ; Untyped                        ;
+; G0_LOW                        ; 1                  ; Untyped                        ;
+; G1_LOW                        ; 1                  ; Untyped                        ;
+; G2_LOW                        ; 1                  ; Untyped                        ;
+; G3_LOW                        ; 1                  ; Untyped                        ;
+; E0_LOW                        ; 1                  ; Untyped                        ;
+; E1_LOW                        ; 1                  ; Untyped                        ;
+; E2_LOW                        ; 1                  ; Untyped                        ;
+; E3_LOW                        ; 1                  ; Untyped                        ;
+; L0_INITIAL                    ; 1                  ; Untyped                        ;
+; L1_INITIAL                    ; 1                  ; Untyped                        ;
+; G0_INITIAL                    ; 1                  ; Untyped                        ;
+; G1_INITIAL                    ; 1                  ; Untyped                        ;
+; G2_INITIAL                    ; 1                  ; Untyped                        ;
+; G3_INITIAL                    ; 1                  ; Untyped                        ;
+; E0_INITIAL                    ; 1                  ; Untyped                        ;
+; E1_INITIAL                    ; 1                  ; Untyped                        ;
+; E2_INITIAL                    ; 1                  ; Untyped                        ;
+; E3_INITIAL                    ; 1                  ; Untyped                        ;
+; L0_MODE                       ; BYPASS             ; Untyped                        ;
+; L1_MODE                       ; BYPASS             ; Untyped                        ;
+; G0_MODE                       ; BYPASS             ; Untyped                        ;
+; G1_MODE                       ; BYPASS             ; Untyped                        ;
+; G2_MODE                       ; BYPASS             ; Untyped                        ;
+; G3_MODE                       ; BYPASS             ; Untyped                        ;
+; E0_MODE                       ; BYPASS             ; Untyped                        ;
+; E1_MODE                       ; BYPASS             ; Untyped                        ;
+; E2_MODE                       ; BYPASS             ; Untyped                        ;
+; E3_MODE                       ; BYPASS             ; Untyped                        ;
+; L0_PH                         ; 0                  ; Untyped                        ;
+; L1_PH                         ; 0                  ; Untyped                        ;
+; G0_PH                         ; 0                  ; Untyped                        ;
+; G1_PH                         ; 0                  ; Untyped                        ;
+; G2_PH                         ; 0                  ; Untyped                        ;
+; G3_PH                         ; 0                  ; Untyped                        ;
+; E0_PH                         ; 0                  ; Untyped                        ;
+; E1_PH                         ; 0                  ; Untyped                        ;
+; E2_PH                         ; 0                  ; Untyped                        ;
+; E3_PH                         ; 0                  ; Untyped                        ;
+; M_PH                          ; 0                  ; Untyped                        ;
+; C1_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C2_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C3_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C4_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C5_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C6_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C7_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C8_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C9_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; CLK0_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK1_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK2_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK3_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK4_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK5_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK6_COUNTER                  ; E0                 ; Untyped                        ;
+; CLK7_COUNTER                  ; E1                 ; Untyped                        ;
+; CLK8_COUNTER                  ; E2                 ; Untyped                        ;
+; CLK9_COUNTER                  ; E3                 ; Untyped                        ;
+; L0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; L1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G2_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G3_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E2_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E3_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; M_TIME_DELAY                  ; 0                  ; Untyped                        ;
+; N_TIME_DELAY                  ; 0                  ; Untyped                        ;
+; EXTCLK3_COUNTER               ; E3                 ; Untyped                        ;
+; EXTCLK2_COUNTER               ; E2                 ; Untyped                        ;
+; EXTCLK1_COUNTER               ; E1                 ; Untyped                        ;
+; EXTCLK0_COUNTER               ; E0                 ; Untyped                        ;
+; ENABLE0_COUNTER               ; L0                 ; Untyped                        ;
+; ENABLE1_COUNTER               ; L0                 ; Untyped                        ;
+; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                        ;
+; LOOP_FILTER_R                 ;  1.000000          ; Untyped                        ;
+; LOOP_FILTER_C                 ; 5                  ; Untyped                        ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                        ;
+; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                        ;
+; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                        ;
+; VCO_POST_SCALE                ; 0                  ; Untyped                        ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                        ;
+; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK0                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK1                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK2                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK3                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK4                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_INCLK0                   ; PORT_USED          ; Untyped                        ;
+; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_LOCKED                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                        ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                        ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                        ;
+; M_TEST_SOURCE                 ; 5                  ; Untyped                        ;
+; C0_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C1_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C2_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C3_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C4_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C5_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C6_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C7_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C8_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C9_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; CBXI_PARAMETER                ; altpll_41p2        ; Untyped                        ;
+; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                        ;
+; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                        ;
+; WIDTH_CLOCK                   ; 5                  ; Signed Integer                 ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                        ;
+; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                        ;
+; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                        ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                        ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                        ;
+; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                     ;
+; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                   ;
+; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                   ;
+; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE                 ;
++-------------------------------+--------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 16    ; Signed Integer                                                                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 16    ; Signed Integer                                                                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                  ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
+; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                             ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                                   ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                             ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                                   ;
++----------------+-------+------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                  ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                               ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                            ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                          ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                          ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                        ;
+; LPM_WIDTH               ; 128         ; Signed Integer                                                        ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                        ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                        ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                               ;
+; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                               ;
+; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                               ;
+; USE_EAB                 ; ON          ; Untyped                                                               ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                               ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                               ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                               ;
+; RDSYNC_DELAYPIPE        ; 6           ; Signed Integer                                                        ;
+; WRSYNC_DELAYPIPE        ; 6           ; Signed Integer                                                        ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                               ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                               ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                               ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                               ;
+; WRITE_ACLR_SYNCH        ; ON          ; Untyped                                                               ;
+; CBXI_PARAMETER          ; dcfifo_8fi1 ; Untyped                                                               ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                  ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
+; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+---------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                      ;
++------------------------+-------------+---------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                              ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                              ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                            ;
+; LPM_WIDTH              ; 128         ; Signed Integer                                                            ;
+; LPM_SIZE               ; 16          ; Signed Integer                                                            ;
+; LPM_WIDTHS             ; 4           ; Signed Integer                                                            ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                                            ;
+; CBXI_PARAMETER         ; mux_bbe     ; Untyped                                                                   ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                   ;
++------------------------+-------------+---------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ;
++------------------------+-------------+--------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                               ;
++------------------------+-------------+--------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
++------------------------+-------------+--------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ;
++------------------------+-------------+--------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                               ;
++------------------------+-------------+--------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
++------------------------+-------------+--------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ;
++--------------------------+----------------+------------------------------------------------------------------------------------+
+; Parameter Name           ; Value          ; Type                                                                               ;
++--------------------------+----------------+------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS        ; ON             ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS     ; OFF            ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS      ; ON             ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS   ; OFF            ; IGNORE_CASCADE                                                                     ;
+; WIDTH                    ; 32             ; Signed Integer                                                                     ;
+; POWER_UP_HIGH            ; OFF            ; Untyped                                                                            ;
+; OE_REG                   ; UNUSED         ; Untyped                                                                            ;
+; extend_oe_disable        ; UNUSED         ; Untyped                                                                            ;
+; IMPLEMENT_INPUT_IN_LCELL ; ON             ; Untyped                                                                            ;
+; INTENDED_DEVICE_FAMILY   ; Cyclone III    ; Untyped                                                                            ;
+; DEVICE_FAMILY            ; Cyclone III    ; Untyped                                                                            ;
+; CBXI_PARAMETER           ; ddio_bidir_3jl ; Untyped                                                                            ;
++--------------------------+----------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                   ;
++------------------------+-------------+------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
+; LPM_WIDTH              ; 64          ; Signed Integer                                                         ;
+; LPM_SIZE               ; 4           ; Signed Integer                                                         ;
+; LPM_WIDTHS             ; 2           ; Signed Integer                                                         ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                                         ;
+; CBXI_PARAMETER         ; mux_58e     ; Untyped                                                                ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
++------------------------+-------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ;
++----------------+--------+-------------------------------------------------------------------------------------------+
+; Parameter Name ; Value  ; Type                                                                                      ;
++----------------+--------+-------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 32     ; Signed Integer                                                                            ;
+; LPM_AVALUE     ; UNUSED ; Untyped                                                                                   ;
++----------------+--------+-------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                  ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
+; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
++------------------------+-------------+---------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+------------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                   ;
++------------------------------------+-----------------+------------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                         ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                ;
+; WIDTH_A                            ; 6               ; Signed Integer                                                         ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                         ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                         ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                ;
+; WIDTH_B                            ; 6               ; Signed Integer                                                         ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                         ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                         ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                         ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                         ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                                ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                                ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                                ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                ;
+; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                ;
++------------------------------------+-----------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+-------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                    ;
++------------------------+-------------+-------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                              ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                            ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                            ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                          ;
+; LPM_WIDTH              ; 128         ; Signed Integer                                                          ;
+; LPM_SIZE               ; 2           ; Signed Integer                                                          ;
+; LPM_WIDTHS             ; 1           ; Signed Integer                                                          ;
+; LPM_PIPELINE           ; 1           ; Signed Integer                                                          ;
+; CBXI_PARAMETER         ; mux_dcf     ; Untyped                                                                 ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                 ;
++------------------------+-------------+-------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                  ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                            ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                          ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                          ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                        ;
+; lpm_width               ; 128         ; Signed Integer                                                        ;
+; LPM_NUMWORDS            ; 128         ; Signed Integer                                                        ;
+; LPM_WIDTHU              ; 7           ; Signed Integer                                                        ;
+; LPM_SHOWAHEAD           ; ON          ; Untyped                                                               ;
+; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                               ;
+; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                               ;
+; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                               ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                               ;
+; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                               ;
+; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                               ;
+; USE_EAB                 ; ON          ; Untyped                                                               ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                               ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                               ;
+; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                               ;
+; CBXI_PARAMETER          ; scfifo_lk21 ; Untyped                                                               ;
++-------------------------+-------------+-----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                               ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
+; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
++------------------------+-------------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+--------------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                     ;
++------------------------------------+-----------------+--------------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                  ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                               ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                             ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                             ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                           ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                  ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                  ;
+; WIDTH_A                            ; 6               ; Signed Integer                                                           ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                           ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                           ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                  ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                  ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                  ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                  ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                  ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                  ;
+; WIDTH_B                            ; 6               ; Signed Integer                                                           ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                           ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                           ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                  ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                  ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                  ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                  ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                  ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                  ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                  ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                  ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                  ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                           ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                           ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                  ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                                  ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                  ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                  ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                  ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                                  ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                  ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                  ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                  ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                  ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                  ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                  ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                  ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                  ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                                  ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                  ;
+; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                  ;
++------------------------------------+-----------------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+-------------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                    ;
++------------------------------------+-----------------+-------------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                 ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                              ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                            ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                            ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                          ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                 ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                 ;
+; WIDTH_A                            ; 6               ; Signed Integer                                                          ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                          ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                          ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                 ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                 ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                 ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                 ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
+; WIDTH_B                            ; 6               ; Signed Integer                                                          ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                          ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                          ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                 ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                 ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                 ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                 ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                 ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                          ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                          ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                 ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                                 ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                 ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                 ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                 ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                                 ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                 ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                 ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                 ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                 ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                 ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                 ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                 ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                 ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                                 ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                 ;
+; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                 ;
++------------------------------------+-----------------+-------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+--------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                               ;
++------------------------------------+-----------------+--------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                            ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                         ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                       ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                       ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                     ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                            ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                            ;
+; WIDTH_A                            ; 3               ; Signed Integer                                                     ;
+; WIDTHAD_A                          ; 4               ; Signed Integer                                                     ;
+; NUMWORDS_A                         ; 16              ; Signed Integer                                                     ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                            ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                            ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                            ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                            ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                            ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                            ;
+; WIDTH_B                            ; 3               ; Signed Integer                                                     ;
+; WIDTHAD_B                          ; 4               ; Signed Integer                                                     ;
+; NUMWORDS_B                         ; 16              ; Signed Integer                                                     ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                            ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                            ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                            ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                            ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                            ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                            ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                            ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                            ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                            ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                            ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                            ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                            ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                     ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                     ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                            ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                            ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                            ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                            ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                            ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                            ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                            ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                            ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                            ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                            ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                            ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                            ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                            ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                            ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                            ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                            ;
+; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                            ;
++------------------------------------+-----------------+--------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+----------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                 ;
++------------------------------------+-----------------+----------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                              ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                           ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                         ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                         ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                       ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                              ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                              ;
+; WIDTH_A                            ; 3               ; Signed Integer                                                       ;
+; WIDTHAD_A                          ; 4               ; Signed Integer                                                       ;
+; NUMWORDS_A                         ; 16              ; Signed Integer                                                       ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                              ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                              ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                              ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                              ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                              ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                              ;
+; WIDTH_B                            ; 3               ; Signed Integer                                                       ;
+; WIDTHAD_B                          ; 4               ; Signed Integer                                                       ;
+; NUMWORDS_B                         ; 16              ; Signed Integer                                                       ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                              ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                              ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                              ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                              ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                              ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                              ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                              ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                              ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                              ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                              ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                              ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                              ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                       ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                       ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                              ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                              ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                              ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                              ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                              ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                              ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                              ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                              ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                              ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                              ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                              ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                              ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                              ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                              ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                              ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                              ;
+; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                              ;
++------------------------------------+-----------------+----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                          ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
++----------------+-------+-----------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                      ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                             ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                             ;
+; WIDTH_A                            ; 3               ; Signed Integer                                                      ;
+; WIDTHAD_A                          ; 4               ; Signed Integer                                                      ;
+; NUMWORDS_A                         ; 16              ; Signed Integer                                                      ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                             ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                             ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                             ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; WIDTH_B                            ; 3               ; Signed Integer                                                      ;
+; WIDTHAD_B                          ; 4               ; Signed Integer                                                      ;
+; NUMWORDS_B                         ; 16              ; Signed Integer                                                      ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                             ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                             ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                             ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                             ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                      ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                      ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                             ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                             ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                             ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                             ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                             ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                             ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                             ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                             ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                             ;
+; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                             ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                             ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                  ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                               ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                            ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                          ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                          ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                        ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                               ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                               ;
+; WIDTH_A                            ; 8               ; Signed Integer                                                        ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                        ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                        ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                               ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                               ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                               ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; WIDTH_B                            ; 8               ; Signed Integer                                                        ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                        ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                        ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                               ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                               ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                               ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                               ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                        ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                        ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                               ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                               ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                               ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                               ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                               ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                               ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                               ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                               ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                               ;
+; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                               ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+-------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                    ;
++------------------------+-------------+-------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                              ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                            ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                            ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                          ;
+; LPM_WIDTH              ; 1           ; Signed Integer                                                          ;
+; LPM_SIZE               ; 2           ; Signed Integer                                                          ;
+; LPM_WIDTHS             ; 1           ; Signed Integer                                                          ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                                          ;
+; CBXI_PARAMETER         ; mux_96e     ; Untyped                                                                 ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                 ;
++------------------------+-------------+-------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 8           ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                   ;
++------------------------+-------------+------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
+; LPM_WIDTH              ; 8           ; Signed Integer                                                         ;
+; LPM_SIZE               ; 16          ; Signed Integer                                                         ;
+; LPM_WIDTHS             ; 4           ; Signed Integer                                                         ;
+; LPM_PIPELINE           ; 2           ; Signed Integer                                                         ;
+; CBXI_PARAMETER         ; mux_mpe     ; Untyped                                                                ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
++------------------------+-------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                   ;
++------------------------+-------------+------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
+; LPM_WIDTH              ; 7           ; Signed Integer                                                         ;
+; LPM_SIZE               ; 2           ; Signed Integer                                                         ;
+; LPM_WIDTHS             ; 1           ; Signed Integer                                                         ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                                         ;
+; CBXI_PARAMETER         ; mux_f6e     ; Untyped                                                                ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
++------------------------+-------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 7                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_pf6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                             ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                  ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                               ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                            ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                          ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                          ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                        ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                               ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                               ;
+; WIDTH_A                            ; 8               ; Signed Integer                                                        ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                        ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                        ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                               ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                               ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                               ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                               ;
+; WIDTH_B                            ; 8               ; Signed Integer                                                        ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                        ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                        ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                               ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                               ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                               ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                               ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                               ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                        ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                        ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                               ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                               ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                               ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                               ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                               ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                               ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                               ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                               ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                               ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                               ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                               ;
+; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                               ;
++------------------------------------+-----------------+-----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                             ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
++----------------+-------+--------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+; Parameter Name                     ; Value           ; Type                                                                ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                      ;
+; WIDTH_BYTEENA                      ; 1               ; Untyped                                                             ;
+; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                             ;
+; WIDTH_A                            ; 8               ; Signed Integer                                                      ;
+; WIDTHAD_A                          ; 8               ; Signed Integer                                                      ;
+; NUMWORDS_A                         ; 256             ; Signed Integer                                                      ;
+; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                             ;
+; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                             ;
+; INDATA_ACLR_A                      ; NONE            ; Untyped                                                             ;
+; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                             ;
+; WIDTH_B                            ; 8               ; Signed Integer                                                      ;
+; WIDTHAD_B                          ; 8               ; Signed Integer                                                      ;
+; NUMWORDS_B                         ; 256             ; Signed Integer                                                      ;
+; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                             ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                             ;
+; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                             ;
+; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
+; INDATA_ACLR_B                      ; NONE            ; Untyped                                                             ;
+; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
+; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
+; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                             ;
+; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                      ;
+; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                      ;
+; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                             ;
+; BYTE_SIZE                          ; 8               ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                             ;
+; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                             ;
+; INIT_FILE                          ; UNUSED          ; Untyped                                                             ;
+; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                             ;
+; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                             ;
+; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                             ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                             ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                             ;
+; ENABLE_ECC                         ; FALSE           ; Untyped                                                             ;
+; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                             ;
+; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                             ;
++------------------------------------+-----------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                                             ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                       ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                     ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                     ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                   ;
+; WIDTH                  ; 24           ; Signed Integer                                                                   ;
+; POWER_UP_HIGH          ; OFF          ; Untyped                                                                          ;
+; OE_REG                 ; UNUSED       ; Untyped                                                                          ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                                          ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                                          ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                                          ;
+; CBXI_PARAMETER         ; ddio_out_o2f ; Untyped                                                                          ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+-----------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                  ;
++------------------------+-------------+-----------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                        ;
+; LPM_WIDTH              ; 24          ; Signed Integer                                                        ;
+; LPM_SIZE               ; 8           ; Signed Integer                                                        ;
+; LPM_WIDTHS             ; 3           ; Signed Integer                                                        ;
+; LPM_PIPELINE           ; 2           ; Signed Integer                                                        ;
+; CBXI_PARAMETER         ; mux_kpe     ; Untyped                                                               ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                               ;
++------------------------+-------------+-----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 16          ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                   ;
++------------------------+-------------+------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
+; LPM_WIDTH              ; 16          ; Signed Integer                                                         ;
+; LPM_SIZE               ; 8           ; Signed Integer                                                         ;
+; LPM_WIDTHS             ; 3           ; Signed Integer                                                         ;
+; LPM_PIPELINE           ; 4           ; Signed Integer                                                         ;
+; CBXI_PARAMETER         ; mux_npe     ; Untyped                                                                ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
++------------------------+-------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; Parameter Name     ; Value            ; Type                                                                                 ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+; LPM_WIDTH          ; 8                ; Signed Integer                                                                       ;
+; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
+; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
+; CBXI_PARAMETER     ; lpm_constant_qf6 ; Untyped                                                                              ;
++--------------------+------------------+--------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ;
++------------------------+-------------+--------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                               ;
++------------------------+-------------+--------------------------------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
++------------------------+-------------+--------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component ;
++------------------------+-------------+------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                   ;
++------------------------+-------------+------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
+; LPM_WIDTH              ; 32          ; Signed Integer                                                         ;
+; LPM_SIZE               ; 4           ; Signed Integer                                                         ;
+; LPM_WIDTHS             ; 2           ; Signed Integer                                                         ;
+; LPM_PIPELINE           ; 4           ; Signed Integer                                                         ;
+; CBXI_PARAMETER         ; mux_gpe     ; Untyped                                                                ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
++------------------------+-------------+------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                                             ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                       ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                     ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                     ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                   ;
+; WIDTH                  ; 4            ; Signed Integer                                                                   ;
+; POWER_UP_HIGH          ; ON           ; Untyped                                                                          ;
+; OE_REG                 ; UNUSED       ; Untyped                                                                          ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                                          ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                                          ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                                          ;
+; CBXI_PARAMETER         ; ddio_out_are ; Untyped                                                                          ;
++------------------------+--------------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                ;
++------------------------+-------------+---------------------------------------------------------------------+
+; LPM_WIDTH              ; 8           ; Signed Integer                                                      ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
++------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component ;
++-------------------------------+--------------------+--------------------------------+
+; Parameter Name                ; Value              ; Type                           ;
++-------------------------------+--------------------+--------------------------------+
+; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                        ;
+; PLL_TYPE                      ; AUTO               ; Untyped                        ;
+; QUALIFY_CONF_DONE             ; OFF                ; Untyped                        ;
+; COMPENSATE_CLOCK              ; CLK0               ; Untyped                        ;
+; SCAN_CHAIN                    ; LONG               ; Untyped                        ;
+; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                        ;
+; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer                 ;
+; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                        ;
+; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                        ;
+; GATE_LOCK_COUNTER             ; 0                  ; Untyped                        ;
+; LOCK_HIGH                     ; 1                  ; Untyped                        ;
+; LOCK_LOW                      ; 1                  ; Untyped                        ;
+; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                        ;
+; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                        ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                        ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                        ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                        ;
+; SKIP_VCO                      ; OFF                ; Untyped                        ;
+; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                        ;
+; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                        ;
+; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                        ;
+; BANDWIDTH                     ; 0                  ; Untyped                        ;
+; BANDWIDTH_TYPE                ; AUTO               ; Untyped                        ;
+; SPREAD_FREQUENCY              ; 0                  ; Untyped                        ;
+; DOWN_SPREAD                   ; 0                  ; Untyped                        ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                        ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                        ;
+; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                        ;
+; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                        ;
+; CLK4_MULTIPLY_BY              ; 2                  ; Signed Integer                 ;
+; CLK3_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
+; CLK2_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
+; CLK1_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
+; CLK0_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
+; CLK9_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK8_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK7_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK6_DIVIDE_BY                ; 0                  ; Untyped                        ;
+; CLK5_DIVIDE_BY                ; 1                  ; Untyped                        ;
+; CLK4_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
+; CLK3_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
+; CLK2_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
+; CLK1_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
+; CLK0_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
+; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK4_PHASE_SHIFT              ; 11364              ; Untyped                        ;
+; CLK3_PHASE_SHIFT              ; 2210               ; Untyped                        ;
+; CLK2_PHASE_SHIFT              ; 3788               ; Untyped                        ;
+; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                        ;
+; CLK0_PHASE_SHIFT              ; 5051               ; Untyped                        ;
+; CLK5_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK4_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK3_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK2_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK1_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK0_TIME_DELAY               ; 0                  ; Untyped                        ;
+; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                        ;
+; CLK4_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK3_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
+; LOCK_WINDOW_UI                ;  0.05              ; Untyped                        ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                        ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                        ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                        ;
+; DPA_MULTIPLY_BY               ; 0                  ; Untyped                        ;
+; DPA_DIVIDE_BY                 ; 1                  ; Untyped                        ;
+; DPA_DIVIDER                   ; 0                  ; Untyped                        ;
+; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                        ;
+; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                        ;
+; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                        ;
+; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                        ;
+; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                        ;
+; VCO_MULTIPLY_BY               ; 0                  ; Untyped                        ;
+; VCO_DIVIDE_BY                 ; 0                  ; Untyped                        ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                        ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                        ;
+; VCO_MIN                       ; 0                  ; Untyped                        ;
+; VCO_MAX                       ; 0                  ; Untyped                        ;
+; VCO_CENTER                    ; 0                  ; Untyped                        ;
+; PFD_MIN                       ; 0                  ; Untyped                        ;
+; PFD_MAX                       ; 0                  ; Untyped                        ;
+; M_INITIAL                     ; 0                  ; Untyped                        ;
+; M                             ; 0                  ; Untyped                        ;
+; N                             ; 1                  ; Untyped                        ;
+; M2                            ; 1                  ; Untyped                        ;
+; N2                            ; 1                  ; Untyped                        ;
+; SS                            ; 1                  ; Untyped                        ;
+; C0_HIGH                       ; 0                  ; Untyped                        ;
+; C1_HIGH                       ; 0                  ; Untyped                        ;
+; C2_HIGH                       ; 0                  ; Untyped                        ;
+; C3_HIGH                       ; 0                  ; Untyped                        ;
+; C4_HIGH                       ; 0                  ; Untyped                        ;
+; C5_HIGH                       ; 0                  ; Untyped                        ;
+; C6_HIGH                       ; 0                  ; Untyped                        ;
+; C7_HIGH                       ; 0                  ; Untyped                        ;
+; C8_HIGH                       ; 0                  ; Untyped                        ;
+; C9_HIGH                       ; 0                  ; Untyped                        ;
+; C0_LOW                        ; 0                  ; Untyped                        ;
+; C1_LOW                        ; 0                  ; Untyped                        ;
+; C2_LOW                        ; 0                  ; Untyped                        ;
+; C3_LOW                        ; 0                  ; Untyped                        ;
+; C4_LOW                        ; 0                  ; Untyped                        ;
+; C5_LOW                        ; 0                  ; Untyped                        ;
+; C6_LOW                        ; 0                  ; Untyped                        ;
+; C7_LOW                        ; 0                  ; Untyped                        ;
+; C8_LOW                        ; 0                  ; Untyped                        ;
+; C9_LOW                        ; 0                  ; Untyped                        ;
+; C0_INITIAL                    ; 0                  ; Untyped                        ;
+; C1_INITIAL                    ; 0                  ; Untyped                        ;
+; C2_INITIAL                    ; 0                  ; Untyped                        ;
+; C3_INITIAL                    ; 0                  ; Untyped                        ;
+; C4_INITIAL                    ; 0                  ; Untyped                        ;
+; C5_INITIAL                    ; 0                  ; Untyped                        ;
+; C6_INITIAL                    ; 0                  ; Untyped                        ;
+; C7_INITIAL                    ; 0                  ; Untyped                        ;
+; C8_INITIAL                    ; 0                  ; Untyped                        ;
+; C9_INITIAL                    ; 0                  ; Untyped                        ;
+; C0_MODE                       ; BYPASS             ; Untyped                        ;
+; C1_MODE                       ; BYPASS             ; Untyped                        ;
+; C2_MODE                       ; BYPASS             ; Untyped                        ;
+; C3_MODE                       ; BYPASS             ; Untyped                        ;
+; C4_MODE                       ; BYPASS             ; Untyped                        ;
+; C5_MODE                       ; BYPASS             ; Untyped                        ;
+; C6_MODE                       ; BYPASS             ; Untyped                        ;
+; C7_MODE                       ; BYPASS             ; Untyped                        ;
+; C8_MODE                       ; BYPASS             ; Untyped                        ;
+; C9_MODE                       ; BYPASS             ; Untyped                        ;
+; C0_PH                         ; 0                  ; Untyped                        ;
+; C1_PH                         ; 0                  ; Untyped                        ;
+; C2_PH                         ; 0                  ; Untyped                        ;
+; C3_PH                         ; 0                  ; Untyped                        ;
+; C4_PH                         ; 0                  ; Untyped                        ;
+; C5_PH                         ; 0                  ; Untyped                        ;
+; C6_PH                         ; 0                  ; Untyped                        ;
+; C7_PH                         ; 0                  ; Untyped                        ;
+; C8_PH                         ; 0                  ; Untyped                        ;
+; C9_PH                         ; 0                  ; Untyped                        ;
+; L0_HIGH                       ; 1                  ; Untyped                        ;
+; L1_HIGH                       ; 1                  ; Untyped                        ;
+; G0_HIGH                       ; 1                  ; Untyped                        ;
+; G1_HIGH                       ; 1                  ; Untyped                        ;
+; G2_HIGH                       ; 1                  ; Untyped                        ;
+; G3_HIGH                       ; 1                  ; Untyped                        ;
+; E0_HIGH                       ; 1                  ; Untyped                        ;
+; E1_HIGH                       ; 1                  ; Untyped                        ;
+; E2_HIGH                       ; 1                  ; Untyped                        ;
+; E3_HIGH                       ; 1                  ; Untyped                        ;
+; L0_LOW                        ; 1                  ; Untyped                        ;
+; L1_LOW                        ; 1                  ; Untyped                        ;
+; G0_LOW                        ; 1                  ; Untyped                        ;
+; G1_LOW                        ; 1                  ; Untyped                        ;
+; G2_LOW                        ; 1                  ; Untyped                        ;
+; G3_LOW                        ; 1                  ; Untyped                        ;
+; E0_LOW                        ; 1                  ; Untyped                        ;
+; E1_LOW                        ; 1                  ; Untyped                        ;
+; E2_LOW                        ; 1                  ; Untyped                        ;
+; E3_LOW                        ; 1                  ; Untyped                        ;
+; L0_INITIAL                    ; 1                  ; Untyped                        ;
+; L1_INITIAL                    ; 1                  ; Untyped                        ;
+; G0_INITIAL                    ; 1                  ; Untyped                        ;
+; G1_INITIAL                    ; 1                  ; Untyped                        ;
+; G2_INITIAL                    ; 1                  ; Untyped                        ;
+; G3_INITIAL                    ; 1                  ; Untyped                        ;
+; E0_INITIAL                    ; 1                  ; Untyped                        ;
+; E1_INITIAL                    ; 1                  ; Untyped                        ;
+; E2_INITIAL                    ; 1                  ; Untyped                        ;
+; E3_INITIAL                    ; 1                  ; Untyped                        ;
+; L0_MODE                       ; BYPASS             ; Untyped                        ;
+; L1_MODE                       ; BYPASS             ; Untyped                        ;
+; G0_MODE                       ; BYPASS             ; Untyped                        ;
+; G1_MODE                       ; BYPASS             ; Untyped                        ;
+; G2_MODE                       ; BYPASS             ; Untyped                        ;
+; G3_MODE                       ; BYPASS             ; Untyped                        ;
+; E0_MODE                       ; BYPASS             ; Untyped                        ;
+; E1_MODE                       ; BYPASS             ; Untyped                        ;
+; E2_MODE                       ; BYPASS             ; Untyped                        ;
+; E3_MODE                       ; BYPASS             ; Untyped                        ;
+; L0_PH                         ; 0                  ; Untyped                        ;
+; L1_PH                         ; 0                  ; Untyped                        ;
+; G0_PH                         ; 0                  ; Untyped                        ;
+; G1_PH                         ; 0                  ; Untyped                        ;
+; G2_PH                         ; 0                  ; Untyped                        ;
+; G3_PH                         ; 0                  ; Untyped                        ;
+; E0_PH                         ; 0                  ; Untyped                        ;
+; E1_PH                         ; 0                  ; Untyped                        ;
+; E2_PH                         ; 0                  ; Untyped                        ;
+; E3_PH                         ; 0                  ; Untyped                        ;
+; M_PH                          ; 0                  ; Untyped                        ;
+; C1_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C2_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C3_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C4_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C5_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C6_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C7_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C8_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; C9_USE_CASC_IN                ; OFF                ; Untyped                        ;
+; CLK0_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK1_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK2_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK3_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK4_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK5_COUNTER                  ; G0                 ; Untyped                        ;
+; CLK6_COUNTER                  ; E0                 ; Untyped                        ;
+; CLK7_COUNTER                  ; E1                 ; Untyped                        ;
+; CLK8_COUNTER                  ; E2                 ; Untyped                        ;
+; CLK9_COUNTER                  ; E3                 ; Untyped                        ;
+; L0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; L1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G2_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; G3_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E0_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E1_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E2_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; E3_TIME_DELAY                 ; 0                  ; Untyped                        ;
+; M_TIME_DELAY                  ; 0                  ; Untyped                        ;
+; N_TIME_DELAY                  ; 0                  ; Untyped                        ;
+; EXTCLK3_COUNTER               ; E3                 ; Untyped                        ;
+; EXTCLK2_COUNTER               ; E2                 ; Untyped                        ;
+; EXTCLK1_COUNTER               ; E1                 ; Untyped                        ;
+; EXTCLK0_COUNTER               ; E0                 ; Untyped                        ;
+; ENABLE0_COUNTER               ; L0                 ; Untyped                        ;
+; ENABLE1_COUNTER               ; L0                 ; Untyped                        ;
+; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                        ;
+; LOOP_FILTER_R                 ;  1.000000          ; Untyped                        ;
+; LOOP_FILTER_C                 ; 5                  ; Untyped                        ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                        ;
+; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                        ;
+; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                        ;
+; VCO_POST_SCALE                ; 0                  ; Untyped                        ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                        ;
+; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK0                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK1                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK2                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK3                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK4                     ; PORT_USED          ; Untyped                        ;
+; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_INCLK0                   ; PORT_USED          ; Untyped                        ;
+; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_LOCKED                   ; PORT_UNUSED        ; Untyped                        ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                        ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                        ;
+; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                        ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                        ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                        ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                        ;
+; M_TEST_SOURCE                 ; 5                  ; Untyped                        ;
+; C0_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C1_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C2_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C3_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C4_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C5_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C6_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C7_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C8_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; C9_TEST_SOURCE                ; 5                  ; Untyped                        ;
+; CBXI_PARAMETER                ; altpll_isv2        ; Untyped                        ;
+; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                        ;
+; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                        ;
+; WIDTH_CLOCK                   ; 5                  ; Signed Integer                 ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                        ;
+; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                        ;
+; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                        ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                        ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                        ;
+; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                     ;
+; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                   ;
+; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                   ;
+; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE                 ;
++-------------------------------+--------------------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component ;
++-------------------------------+-------------------+---------------------------------+
+; Parameter Name                ; Value             ; Type                            ;
++-------------------------------+-------------------+---------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                         ;
+; PLL_TYPE                      ; AUTO              ; Untyped                         ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                         ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                         ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                         ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                         ;
+; INCLK0_INPUT_FREQUENCY        ; 20833             ; Untyped                         ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                         ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                         ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                         ;
+; LOCK_HIGH                     ; 1                 ; Untyped                         ;
+; LOCK_LOW                      ; 1                 ; Untyped                         ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                         ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                         ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                         ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                         ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                         ;
+; SKIP_VCO                      ; OFF               ; Untyped                         ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                         ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                         ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                         ;
+; BANDWIDTH                     ; 0                 ; Untyped                         ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                         ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                         ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                         ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                         ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                         ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                         ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                         ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                         ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                         ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                         ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                         ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                         ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                         ;
+; CLK1_MULTIPLY_BY              ; 1                 ; Untyped                         ;
+; CLK0_MULTIPLY_BY              ; 2                 ; Untyped                         ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                         ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                         ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                         ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                         ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK1_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK0_DIVIDE_BY                ; 1                 ; Untyped                         ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                         ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                         ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK1_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK0_DUTY_CYCLE               ; 50                ; Untyped                         ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                         ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                         ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                         ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                         ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                         ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                         ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                         ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                         ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                         ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                         ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                         ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                         ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                         ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                         ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                         ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                         ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                         ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                         ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                         ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                         ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                         ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                         ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                         ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                         ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                         ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                         ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                         ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                         ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                         ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                         ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                         ;
+; VCO_MIN                       ; 0                 ; Untyped                         ;
+; VCO_MAX                       ; 0                 ; Untyped                         ;
+; VCO_CENTER                    ; 0                 ; Untyped                         ;
+; PFD_MIN                       ; 0                 ; Untyped                         ;
+; PFD_MAX                       ; 0                 ; Untyped                         ;
+; M_INITIAL                     ; 0                 ; Untyped                         ;
+; M                             ; 0                 ; Untyped                         ;
+; N                             ; 1                 ; Untyped                         ;
+; M2                            ; 1                 ; Untyped                         ;
+; N2                            ; 1                 ; Untyped                         ;
+; SS                            ; 1                 ; Untyped                         ;
+; C0_HIGH                       ; 0                 ; Untyped                         ;
+; C1_HIGH                       ; 0                 ; Untyped                         ;
+; C2_HIGH                       ; 0                 ; Untyped                         ;
+; C3_HIGH                       ; 0                 ; Untyped                         ;
+; C4_HIGH                       ; 0                 ; Untyped                         ;
+; C5_HIGH                       ; 0                 ; Untyped                         ;
+; C6_HIGH                       ; 0                 ; Untyped                         ;
+; C7_HIGH                       ; 0                 ; Untyped                         ;
+; C8_HIGH                       ; 0                 ; Untyped                         ;
+; C9_HIGH                       ; 0                 ; Untyped                         ;
+; C0_LOW                        ; 0                 ; Untyped                         ;
+; C1_LOW                        ; 0                 ; Untyped                         ;
+; C2_LOW                        ; 0                 ; Untyped                         ;
+; C3_LOW                        ; 0                 ; Untyped                         ;
+; C4_LOW                        ; 0                 ; Untyped                         ;
+; C5_LOW                        ; 0                 ; Untyped                         ;
+; C6_LOW                        ; 0                 ; Untyped                         ;
+; C7_LOW                        ; 0                 ; Untyped                         ;
+; C8_LOW                        ; 0                 ; Untyped                         ;
+; C9_LOW                        ; 0                 ; Untyped                         ;
+; C0_INITIAL                    ; 0                 ; Untyped                         ;
+; C1_INITIAL                    ; 0                 ; Untyped                         ;
+; C2_INITIAL                    ; 0                 ; Untyped                         ;
+; C3_INITIAL                    ; 0                 ; Untyped                         ;
+; C4_INITIAL                    ; 0                 ; Untyped                         ;
+; C5_INITIAL                    ; 0                 ; Untyped                         ;
+; C6_INITIAL                    ; 0                 ; Untyped                         ;
+; C7_INITIAL                    ; 0                 ; Untyped                         ;
+; C8_INITIAL                    ; 0                 ; Untyped                         ;
+; C9_INITIAL                    ; 0                 ; Untyped                         ;
+; C0_MODE                       ; BYPASS            ; Untyped                         ;
+; C1_MODE                       ; BYPASS            ; Untyped                         ;
+; C2_MODE                       ; BYPASS            ; Untyped                         ;
+; C3_MODE                       ; BYPASS            ; Untyped                         ;
+; C4_MODE                       ; BYPASS            ; Untyped                         ;
+; C5_MODE                       ; BYPASS            ; Untyped                         ;
+; C6_MODE                       ; BYPASS            ; Untyped                         ;
+; C7_MODE                       ; BYPASS            ; Untyped                         ;
+; C8_MODE                       ; BYPASS            ; Untyped                         ;
+; C9_MODE                       ; BYPASS            ; Untyped                         ;
+; C0_PH                         ; 0                 ; Untyped                         ;
+; C1_PH                         ; 0                 ; Untyped                         ;
+; C2_PH                         ; 0                 ; Untyped                         ;
+; C3_PH                         ; 0                 ; Untyped                         ;
+; C4_PH                         ; 0                 ; Untyped                         ;
+; C5_PH                         ; 0                 ; Untyped                         ;
+; C6_PH                         ; 0                 ; Untyped                         ;
+; C7_PH                         ; 0                 ; Untyped                         ;
+; C8_PH                         ; 0                 ; Untyped                         ;
+; C9_PH                         ; 0                 ; Untyped                         ;
+; L0_HIGH                       ; 1                 ; Untyped                         ;
+; L1_HIGH                       ; 1                 ; Untyped                         ;
+; G0_HIGH                       ; 1                 ; Untyped                         ;
+; G1_HIGH                       ; 1                 ; Untyped                         ;
+; G2_HIGH                       ; 1                 ; Untyped                         ;
+; G3_HIGH                       ; 1                 ; Untyped                         ;
+; E0_HIGH                       ; 1                 ; Untyped                         ;
+; E1_HIGH                       ; 1                 ; Untyped                         ;
+; E2_HIGH                       ; 1                 ; Untyped                         ;
+; E3_HIGH                       ; 1                 ; Untyped                         ;
+; L0_LOW                        ; 1                 ; Untyped                         ;
+; L1_LOW                        ; 1                 ; Untyped                         ;
+; G0_LOW                        ; 1                 ; Untyped                         ;
+; G1_LOW                        ; 1                 ; Untyped                         ;
+; G2_LOW                        ; 1                 ; Untyped                         ;
+; G3_LOW                        ; 1                 ; Untyped                         ;
+; E0_LOW                        ; 1                 ; Untyped                         ;
+; E1_LOW                        ; 1                 ; Untyped                         ;
+; E2_LOW                        ; 1                 ; Untyped                         ;
+; E3_LOW                        ; 1                 ; Untyped                         ;
+; L0_INITIAL                    ; 1                 ; Untyped                         ;
+; L1_INITIAL                    ; 1                 ; Untyped                         ;
+; G0_INITIAL                    ; 1                 ; Untyped                         ;
+; G1_INITIAL                    ; 1                 ; Untyped                         ;
+; G2_INITIAL                    ; 1                 ; Untyped                         ;
+; G3_INITIAL                    ; 1                 ; Untyped                         ;
+; E0_INITIAL                    ; 1                 ; Untyped                         ;
+; E1_INITIAL                    ; 1                 ; Untyped                         ;
+; E2_INITIAL                    ; 1                 ; Untyped                         ;
+; E3_INITIAL                    ; 1                 ; Untyped                         ;
+; L0_MODE                       ; BYPASS            ; Untyped                         ;
+; L1_MODE                       ; BYPASS            ; Untyped                         ;
+; G0_MODE                       ; BYPASS            ; Untyped                         ;
+; G1_MODE                       ; BYPASS            ; Untyped                         ;
+; G2_MODE                       ; BYPASS            ; Untyped                         ;
+; G3_MODE                       ; BYPASS            ; Untyped                         ;
+; E0_MODE                       ; BYPASS            ; Untyped                         ;
+; E1_MODE                       ; BYPASS            ; Untyped                         ;
+; E2_MODE                       ; BYPASS            ; Untyped                         ;
+; E3_MODE                       ; BYPASS            ; Untyped                         ;
+; L0_PH                         ; 0                 ; Untyped                         ;
+; L1_PH                         ; 0                 ; Untyped                         ;
+; G0_PH                         ; 0                 ; Untyped                         ;
+; G1_PH                         ; 0                 ; Untyped                         ;
+; G2_PH                         ; 0                 ; Untyped                         ;
+; G3_PH                         ; 0                 ; Untyped                         ;
+; E0_PH                         ; 0                 ; Untyped                         ;
+; E1_PH                         ; 0                 ; Untyped                         ;
+; E2_PH                         ; 0                 ; Untyped                         ;
+; E3_PH                         ; 0                 ; Untyped                         ;
+; M_PH                          ; 0                 ; Untyped                         ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                         ;
+; CLK0_COUNTER                  ; G0                ; Untyped                         ;
+; CLK1_COUNTER                  ; G0                ; Untyped                         ;
+; CLK2_COUNTER                  ; G0                ; Untyped                         ;
+; CLK3_COUNTER                  ; G0                ; Untyped                         ;
+; CLK4_COUNTER                  ; G0                ; Untyped                         ;
+; CLK5_COUNTER                  ; G0                ; Untyped                         ;
+; CLK6_COUNTER                  ; E0                ; Untyped                         ;
+; CLK7_COUNTER                  ; E1                ; Untyped                         ;
+; CLK8_COUNTER                  ; E2                ; Untyped                         ;
+; CLK9_COUNTER                  ; E3                ; Untyped                         ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                         ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                         ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                         ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                         ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                         ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                         ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                         ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                         ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                         ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                         ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                         ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                         ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                         ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                         ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                         ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                         ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                         ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                         ;
+; PORT_CLK1                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_SCANDATA                 ; PORT_USED         ; Untyped                         ;
+; PORT_SCANDATAOUT              ; PORT_USED         ; Untyped                         ;
+; PORT_SCANDONE                 ; PORT_USED         ; Untyped                         ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                         ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                         ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                         ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                         ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                         ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                         ;
+; PORT_ARESET                   ; PORT_USED         ; Untyped                         ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                         ;
+; PORT_SCANCLK                  ; PORT_USED         ; Untyped                         ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                         ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                         ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                         ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_LOCKED                   ; PORT_USED         ; Untyped                         ;
+; PORT_CONFIGUPDATE             ; PORT_USED         ; Untyped                         ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                         ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                         ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                         ;
+; PORT_SCANCLKENA               ; PORT_USED         ; Untyped                         ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                         ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                         ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                         ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                         ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                         ;
+; CBXI_PARAMETER                ; altpll_c6j2       ; Untyped                         ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                         ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                         ;
+; WIDTH_CLOCK                   ; 5                 ; Untyped                         ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                         ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                         ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                         ;
+; SCAN_CHAIN_MIF_FILE           ; altpll4.mif       ; Untyped                         ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                         ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                      ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                    ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                    ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                  ;
++-------------------------------+-------------------+---------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ;
++-----------------+-------+---------------------------------------------------------------------------------------------------------------+
+; Parameter Name  ; Value ; Type                                                                                                          ;
++-----------------+-------+---------------------------------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA_A ; 1     ; Untyped                                                                                                       ;
+; WIDTH_BYTEENA_B ; 1     ; Untyped                                                                                                       ;
++-----------------+-------+---------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ;
++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
+; Parameter Name                     ; Value                ; Type                                                                                               ;
++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
+; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                            ;
+; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                         ;
+; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                       ;
+; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                       ;
+; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                     ;
+; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                            ;
+; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                                                                            ;
+; WIDTH_A                            ; 1                    ; Untyped                                                                                            ;
+; WIDTHAD_A                          ; 8                    ; Untyped                                                                                            ;
+; NUMWORDS_A                         ; 144                  ; Untyped                                                                                            ;
+; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                            ;
+; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
+; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
+; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                            ;
+; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                            ;
+; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
+; WIDTH_B                            ; 1                    ; Untyped                                                                                            ;
+; WIDTHAD_B                          ; 1                    ; Untyped                                                                                            ;
+; NUMWORDS_B                         ; 1                    ; Untyped                                                                                            ;
+; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                            ;
+; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                            ;
+; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                            ;
+; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                            ;
+; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                            ;
+; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                            ;
+; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                            ;
+; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                            ;
+; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
+; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
+; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                            ;
+; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
+; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                            ;
+; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                            ;
+; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                            ;
+; BYTE_SIZE                          ; 8                    ; Untyped                                                                                            ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                            ;
+; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                            ;
+; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                            ;
+; INIT_FILE                          ; UNUSED               ; Untyped                                                                                            ;
+; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                            ;
+; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                            ;
+; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                            ;
+; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                            ;
+; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                            ;
+; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                            ;
+; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                            ;
+; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                            ;
+; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                            ;
+; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                            ;
+; CBXI_PARAMETER                     ; altsyncram_46r       ; Untyped                                                                                            ;
++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                  ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 9           ; Untyped                                                                                                               ;
+; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                               ;
+; LPM_DIRECTION          ; DEFAULT     ; Untyped                                                                                                               ;
+; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                               ;
+; LPM_PIPELINE           ; 0           ; Untyped                                                                                                               ;
+; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                               ;
+; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                               ;
+; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                                                                                               ;
+; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                               ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                               ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                    ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                               ;
+; USE_WYS                ; OFF         ; Untyped                                                                                                               ;
+; STYLE                  ; FAST        ; Untyped                                                                                                               ;
+; CBXI_PARAMETER         ; add_sub_hpa ; Untyped                                                                                                               ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                        ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                  ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 8           ; Untyped                                                                                                               ;
+; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                               ;
+; LPM_DIRECTION          ; DEFAULT     ; Untyped                                                                                                               ;
+; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                               ;
+; LPM_PIPELINE           ; 0           ; Untyped                                                                                                               ;
+; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                               ;
+; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                               ;
+; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                                                                                               ;
+; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                               ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                               ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                    ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                               ;
+; USE_WYS                ; OFF         ; Untyped                                                                                                               ;
+; STYLE                  ; FAST        ; Untyped                                                                                                               ;
+; CBXI_PARAMETER         ; add_sub_k8a ; Untyped                                                                                                               ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                            ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                          ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                          ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                        ;
++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                               ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; lpm_width              ; 8           ; Untyped                                                                                                            ;
+; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                                                                                            ;
+; LPM_PIPELINE           ; 0           ; Untyped                                                                                                            ;
+; CHAIN_SIZE             ; 8           ; Untyped                                                                                                            ;
+; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                            ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
+; CASCADE_CHAIN          ; MANUAL      ; Untyped                                                                                                            ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
+; CASCADE_CHAIN_LENGTH   ; 2           ; CASCADE_CHAIN_LENGTH                                                                                               ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
+; CBXI_PARAMETER         ; cmpr_tnd    ; Untyped                                                                                                            ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                               ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
+; LPM_WIDTH              ; 8           ; Untyped                                                                                                            ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                            ;
+; LPM_MODULUS            ; 144         ; Untyped                                                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
+; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                            ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
+; LPM_WIDTH              ; 8           ; Untyped                                                                                                             ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
+; LPM_MODULUS            ; 144         ; Untyped                                                                                                             ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
+; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                             ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
+; LPM_WIDTH              ; 6           ; Untyped                                                                                                             ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
+; LPM_MODULUS            ; 0           ; Untyped                                                                                                             ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
+; CBXI_PARAMETER         ; cntr_qij    ; Untyped                                                                                                             ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
+; LPM_WIDTH              ; 5           ; Untyped                                                                                                             ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
+; LPM_MODULUS            ; 0           ; Untyped                                                                                                             ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
+; CBXI_PARAMETER         ; cntr_pij    ; Untyped                                                                                                             ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
+; LPM_WIDTH              ; 8           ; Untyped                                                                                                             ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
+; LPM_MODULUS            ; 144         ; Untyped                                                                                                             ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
+; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                             ;
++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                               ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
+; LPM_WIDTH              ; 8           ; Untyped                                                                                                            ;
+; LPM_DIRECTION          ; UP          ; Untyped                                                                                                            ;
+; LPM_MODULUS            ; 0           ; Untyped                                                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
+; CBXI_PARAMETER         ; cntr_9cj    ; Untyped                                                                                                            ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                               ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
+; LPM_WIDTH              ; 5           ; Untyped                                                                                                            ;
+; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                            ;
+; LPM_MODULUS            ; 0           ; Untyped                                                                                                            ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
+; CBXI_PARAMETER         ; cntr_pij    ; Untyped                                                                                                            ;
++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 ;
++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                                                                                 ;
++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
+; LPM_WIDTH              ; 3           ; Untyped                                                                                                              ;
+; LPM_DECODES            ; 5           ; Untyped                                                                                                              ;
+; LPM_PIPELINE           ; 0           ; Untyped                                                                                                              ;
+; CASCADE_CHAIN          ; MANUAL      ; Untyped                                                                                                              ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                              ;
+; CBXI_PARAMETER         ; decode_2af  ; Untyped                                                                                                              ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                           ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                         ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                         ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                       ;
++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component ;
++------------------------+-------------+---------------------------------------------+
+; Parameter Name         ; Value       ; Type                                        ;
++------------------------+-------------+---------------------------------------------+
+; LPM_WIDTH              ; 32          ; Signed Integer                              ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                     ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                     ;
+; LPM_FFTYPE             ; DFF         ; Untyped                                     ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                     ;
+; CBXI_PARAMETER         ; NOTHING     ; Untyped                                     ;
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                  ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
++------------------------+-------------+---------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                               ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component ;
++------------------------+-------------+-------------------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                                        ;
++------------------------+-------------+-------------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                  ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                              ;
+; LPM_WIDTH              ; 18          ; Signed Integer                                              ;
+; LPM_DIRECTION          ; UP          ; Untyped                                                     ;
+; LPM_MODULUS            ; 0           ; Untyped                                                     ;
+; LPM_AVALUE             ; UNUSED      ; Untyped                                                     ;
+; LPM_SVALUE             ; UNUSED      ; Untyped                                                     ;
+; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                     ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                     ;
+; CARRY_CHAIN            ; MANUAL      ; Untyped                                                     ;
+; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                          ;
+; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                          ;
+; CARRY_CNT_EN           ; SMART       ; Untyped                                                     ;
+; LABWIDE_SCLR           ; ON          ; Untyped                                                     ;
+; USE_NEW_VERSION        ; TRUE        ; Untyped                                                     ;
+; CBXI_PARAMETER         ; cntr_mph    ; Untyped                                                     ;
++------------------------+-------------+-------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component ;
++------------------------+--------------+-----------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                      ;
++------------------------+--------------+-----------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
+; WIDTH                  ; 1            ; Signed Integer                                            ;
+; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
+; OE_REG                 ; UNUSED       ; Untyped                                                   ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
+; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
++------------------------+--------------+-----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component ;
++------------------------+--------------+-----------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                      ;
++------------------------+--------------+-----------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
+; WIDTH                  ; 1            ; Signed Integer                                            ;
+; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
+; OE_REG                 ; UNUSED       ; Untyped                                                   ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
+; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
++------------------------+--------------+-----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component ;
++------------------------+--------------+-----------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                      ;
++------------------------+--------------+-----------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
+; WIDTH                  ; 1            ; Signed Integer                                            ;
+; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
+; OE_REG                 ; UNUSED       ; Untyped                                                   ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
+; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
++------------------------+--------------+-----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component ;
++------------------------+--------------+-----------------------------------------------------------+
+; Parameter Name         ; Value        ; Type                                                      ;
++------------------------+--------------+-----------------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
+; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
+; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
+; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
+; WIDTH                  ; 1            ; Signed Integer                                            ;
+; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
+; OE_REG                 ; UNUSED       ; Untyped                                                   ;
+; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
+; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
+; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
+; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
++------------------------+--------------+-----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                                ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                      ;
+; LPM_WIDTHA                                     ; 12          ; Untyped                                                             ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                             ;
+; LPM_WIDTHP                                     ; 18          ; Untyped                                                             ;
+; LPM_WIDTHR                                     ; 18          ; Untyped                                                             ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                             ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                             ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                             ;
+; LATENCY                                        ; 0           ; Untyped                                                             ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
+; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
+; USE_EAB                                        ; OFF         ; Untyped                                                             ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                             ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                             ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                             ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                 ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                             ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                             ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                             ;
+; CBXI_PARAMETER                                 ; mult_cat    ; Untyped                                                             ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                             ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ;
++------------------------------------------------+-------------+--------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                               ;
++------------------------------------------------+-------------+--------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                         ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                       ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                       ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                     ;
+; LPM_WIDTHA                                     ; 12          ; Untyped                                                            ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                                                            ;
+; LPM_WIDTHP                                     ; 17          ; Untyped                                                            ;
+; LPM_WIDTHR                                     ; 17          ; Untyped                                                            ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                            ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                            ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                            ;
+; LATENCY                                        ; 0           ; Untyped                                                            ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                            ;
+; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                            ;
+; USE_EAB                                        ; OFF         ; Untyped                                                            ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                            ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                            ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                            ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                            ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                            ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                            ;
+; CBXI_PARAMETER                                 ; mult_aat    ; Untyped                                                            ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                            ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                            ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                            ;
++------------------------------------------------+-------------+--------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                                ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                          ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                        ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                        ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                      ;
+; LPM_WIDTHA                                     ; 12          ; Untyped                                                             ;
+; LPM_WIDTHB                                     ; 5           ; Untyped                                                             ;
+; LPM_WIDTHP                                     ; 17          ; Untyped                                                             ;
+; LPM_WIDTHR                                     ; 17          ; Untyped                                                             ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                             ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                             ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                             ;
+; LATENCY                                        ; 0           ; Untyped                                                             ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
+; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
+; USE_EAB                                        ; OFF         ; Untyped                                                             ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                             ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                             ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                             ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                 ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                             ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                             ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                             ;
+; CBXI_PARAMETER                                 ; mult_aat    ; Untyped                                                             ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                             ;
++------------------------------------------------+-------------+---------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                           ;
++-------------------------------+----------------------------------------+
+; Name                          ; Value                                  ;
++-------------------------------+----------------------------------------+
+; Number of entity instances    ; 4                                      ;
+; Entity Instance               ; altpll1:inst|altpll:altpll_component   ;
+;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
+;     -- PLL_TYPE               ; AUTO                                   ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
+;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
+;     -- VCO_MULTIPLY_BY        ; 0                                      ;
+;     -- VCO_DIVIDE_BY          ; 0                                      ;
+; Entity Instance               ; altpll3:inst13|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
+;     -- PLL_TYPE               ; AUTO                                   ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
+;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
+;     -- VCO_MULTIPLY_BY        ; 0                                      ;
+;     -- VCO_DIVIDE_BY          ; 0                                      ;
+; Entity Instance               ; altpll2:inst12|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
+;     -- PLL_TYPE               ; AUTO                                   ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
+;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
+;     -- VCO_MULTIPLY_BY        ; 0                                      ;
+;     -- VCO_DIVIDE_BY          ; 0                                      ;
+; Entity Instance               ; altpll4:inst22|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                 ;
+;     -- PLL_TYPE               ; AUTO                                   ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20833                                  ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
+;     -- VCO_MULTIPLY_BY        ; 0                                      ;
+;     -- VCO_DIVIDE_BY          ; 0                                      ;
++-------------------------------+----------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; lpm_shiftreg Parameter Settings by Entity Instance                                                           ;
++----------------------------+---------------------------------------------------------------------------------+
+; Name                       ; Value                                                                           ;
++----------------------------+---------------------------------------------------------------------------------+
+; Number of entity instances ; 11                                                                              ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ;
+;     -- LPM_WIDTH           ; 5                                                                               ;
+;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ;
+;     -- LPM_WIDTH           ; 5                                                                               ;
+;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ;
+;     -- LPM_WIDTH           ; 5                                                                               ;
+;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component    ;
+;     -- LPM_WIDTH           ; 16                                                                              ;
+;     -- LPM_DIRECTION       ; LEFT                                                                            ;
++----------------------------+---------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                  ;
++----------------------------+------------------------------------------------------------------+
+; Name                       ; Value                                                            ;
++----------------------------+------------------------------------------------------------------+
+; Number of entity instances ; 1                                                                ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                       ;
+;     -- LPM_WIDTH           ; 128                                                              ;
+;     -- LPM_NUMWORDS        ; 512                                                              ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                              ;
+;     -- USE_EAB             ; ON                                                               ;
++----------------------------+------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------+
+; scfifo Parameter Settings by Entity Instance                                                  ;
++----------------------------+------------------------------------------------------------------+
+; Name                       ; Value                                                            ;
++----------------------------+------------------------------------------------------------------+
+; Number of entity instances ; 1                                                                ;
+; Entity Instance            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ;
+;     -- FIFO Type           ; Single Clock                                                     ;
+;     -- lpm_width           ; 128                                                              ;
+;     -- LPM_NUMWORDS        ; 128                                                              ;
+;     -- LPM_SHOWAHEAD       ; ON                                                               ;
+;     -- USE_EAB             ; ON                                                               ;
++----------------------------+------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance                                                                                                              ;
++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
+; Name                                      ; Value                                                                                                             ;
++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
+; Number of entity instances                ; 10                                                                                                                ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                  ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                 ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 6                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                      ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 16                                                                                                                ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 16                                                                                                                ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                    ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 16                                                                                                                ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 16                                                                                                                ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                     ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 16                                                                                                                ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 3                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 16                                                                                                                ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                   ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                   ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                     ;
+;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
+;     -- WIDTH_A                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 256                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
+;     -- WIDTH_B                            ; 8                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 256                                                                                                               ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
+; Entity Instance                           ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ;
+;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                       ;
+;     -- WIDTH_A                            ; 1                                                                                                                 ;
+;     -- NUMWORDS_A                         ; 144                                                                                                               ;
+;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                      ;
+;     -- WIDTH_B                            ; 1                                                                                                                 ;
+;     -- NUMWORDS_B                         ; 1                                                                                                                 ;
+;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
+;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                      ;
+;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
+;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                                            ;
++---------------------------------------+-----------------------------------------------------------------------------------+
+; Name                                  ; Value                                                                             ;
++---------------------------------------+-----------------------------------------------------------------------------------+
+; Number of entity instances            ; 3                                                                                 ;
+; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ;
+;     -- LPM_WIDTHA                     ; 12                                                                                ;
+;     -- LPM_WIDTHB                     ; 6                                                                                 ;
+;     -- LPM_WIDTHP                     ; 18                                                                                ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
+;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
+;     -- USE_EAB                        ; OFF                                                                               ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
+; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6  ;
+;     -- LPM_WIDTHA                     ; 12                                                                                ;
+;     -- LPM_WIDTHB                     ; 5                                                                                 ;
+;     -- LPM_WIDTHP                     ; 17                                                                                ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
+;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
+;     -- USE_EAB                        ; OFF                                                                               ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
+; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ;
+;     -- LPM_WIDTHA                     ; 12                                                                                ;
+;     -- LPM_WIDTHB                     ; 5                                                                                 ;
+;     -- LPM_WIDTHP                     ; 17                                                                                ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
+;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
+;     -- USE_EAB                        ; OFF                                                                               ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
++---------------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"    ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port        ; Type   ; Severity ; Details                                                                             ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; seln        ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; bc2         ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; a9n         ; Input  ; Info     ; Stuck at GND                                                                        ;
+; a8          ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; da_en       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; io_a_in     ; Input  ; Info     ; Stuck at GND                                                                        ;
+; io_a_out[2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; io_a_en     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; io_b_en     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"  ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; data_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; gpip_out ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; gpip_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; iein     ; Input  ; Info     ; Stuck at GND                                                                        ;
+; ieon     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; tai      ; Input  ; Info     ; Stuck at GND                                                                        ;
+; tao      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; tbo      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; tco      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; so_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; rrn      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; trn      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" ;
++---------+--------+----------+------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                  ;
++---------+--------+----------+------------------------------------------------------------------------------------------+
+; cs2n    ; Input  ; Info     ; Stuck at GND                                                                             ;
+; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.      ;
+; ctsn    ; Input  ; Info     ; Stuck at GND                                                                             ;
+; dcdn    ; Input  ; Info     ; Stuck at GND                                                                             ;
+; rtsn    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.      ;
++---------+--------+----------+------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" ;
++---------+--------+----------+----------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                      ;
++---------+--------+----------+----------------------------------------------------------------------------------------------+
+; cs1     ; Input  ; Info     ; Stuck at VCC                                                                                 ;
+; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.          ;
+; ctsn    ; Input  ; Info     ; Stuck at GND                                                                                 ;
+; dcdn    ; Input  ; Info     ; Stuck at GND                                                                                 ;
+; rtsn    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.          ;
++---------+--------+----------+----------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" ;
++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                                                     ;
++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
+; icr_out[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
+; icr_out[5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"    ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                             ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+; data_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; csn      ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; eopn     ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; ready    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; ack_inn  ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; ack_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; atn_inn  ; Input  ; Info     ; Stuck at VCC                                                                        ;
+; atn_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; req_outn ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; req_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; ion_out  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; io_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; cdn_out  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; cd_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; msg_outn ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; msg_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"  ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                             ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; dden    ; Input  ; Info     ; Stuck at GND                                                                        ;
++---------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Wed Dec 15 02:20:37 2010
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_control.vhd
+    Info: Found design unit 1: WF5380_CONTROL-BEHAVIOUR
+    Info: Found entity 1: WF5380_CONTROL
+Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_pkg.vhd
+    Info: Found design unit 1: WF5380_PKG
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_registers.vhd
+    Info: Found design unit 1: WF5380_REGISTERS-BEHAVIOUR
+    Info: Found entity 1: WF5380_REGISTERS
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_soc_top.vhd
+    Info: Found design unit 1: WF5380_TOP_SOC-STRUCTURE
+    Info: Found entity 1: WF5380_TOP_SOC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_top.vhd
+    Info: Found design unit 1: WF5380_TOP-STRUCTURE
+    Info: Found entity 1: WF5380_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_am_detector.vhd
+    Info: Found design unit 1: WF1772IP_AM_DETECTOR-BEHAVIOR
+    Info: Found entity 1: WF1772IP_AM_DETECTOR
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo0.vhd
+    Info: Found design unit 1: dcfifo0-SYN
+    Info: Found entity 1: dcfifo0
+Info: Found 1 design units, including 1 entities, in source file video/ddr_ctr.tdf
+    Info: Found entity 1: DDR_CTR
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri0.vhd
+    Info: Found design unit 1: lpm_bustri0-SYN
+    Info: Found entity 1: lpm_bustri0
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_control.vhd
+    Info: Found design unit 1: WF1772IP_CONTROL-BEHAVIOR
+    Info: Found entity 1: WF1772IP_CONTROL
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_crc_logic.vhd
+    Info: Found design unit 1: WF1772IP_CRC_LOGIC-BEHAVIOR
+    Info: Found entity 1: WF1772IP_CRC_LOGIC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_digital_pll.vhd
+    Info: Found design unit 1: WF1772IP_DIGITAL_PLL-BEHAVIOR
+    Info: Found entity 1: WF1772IP_DIGITAL_PLL
+Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_pkg.vhd
+    Info: Found design unit 1: WF1772IP_PKG
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_registers.vhd
+    Info: Found design unit 1: WF1772IP_REGISTERS-BEHAVIOR
+    Info: Found entity 1: WF1772IP_REGISTERS
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top.vhd
+    Info: Found design unit 1: WF1772IP_TOP-STRUCTURE
+    Info: Found entity 1: WF1772IP_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top_soc.vhd
+    Info: Found design unit 1: WF1772IP_TOP_SOC-STRUCTURE
+    Info: Found entity 1: WF1772IP_TOP_SOC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_transceiver.vhd
+    Info: Found design unit 1: WF1772IP_TRANSCEIVER-BEHAVIOR
+    Info: Found entity 1: WF1772IP_TRANSCEIVER
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri5.vhd
+    Info: Found design unit 1: lpm_bustri5-SYN
+    Info: Found entity 1: lpm_bustri5
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_ctrl_status.vhd
+    Info: Found design unit 1: WF6850IP_CTRL_STATUS-BEHAVIOR
+    Info: Found entity 1: WF6850IP_CTRL_STATUS
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri7.vhd
+    Info: Found design unit 1: lpm_bustri7-SYN
+    Info: Found entity 1: lpm_bustri7
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_receive.vhd
+    Info: Found design unit 1: WF6850IP_RECEIVE-BEHAVIOR
+    Info: Found entity 1: WF6850IP_RECEIVE
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top.vhd
+    Info: Found design unit 1: WF6850IP_TOP-STRUCTURE
+    Info: Found entity 1: WF6850IP_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top_soc.vhd
+    Info: Found design unit 1: WF6850IP_TOP_SOC-STRUCTURE
+    Info: Found entity 1: WF6850IP_TOP_SOC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_transmit.vhd
+    Info: Found design unit 1: WF6850IP_TRANSMIT-BEHAVIOR
+    Info: Found entity 1: WF6850IP_TRANSMIT
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_gpio.vhd
+    Info: Found design unit 1: WF68901IP_GPIO-BEHAVIOR
+    Info: Found entity 1: WF68901IP_GPIO
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_interrupts.vhd
+    Info: Found design unit 1: WF68901IP_INTERRUPTS-BEHAVIOR
+    Info: Found entity 1: WF68901IP_INTERRUPTS
+Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_pkg.vhd
+    Info: Found design unit 1: WF68901IP_PKG
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_timers.vhd
+    Info: Found design unit 1: WF68901IP_TIMERS-BEHAVIOR
+    Info: Found entity 1: WF68901IP_TIMERS
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top.vhd
+    Info: Found design unit 1: WF68901IP_TOP-STRUCTURE
+    Info: Found entity 1: WF68901IP_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top_soc.vhd
+    Info: Found design unit 1: WF68901IP_TOP_SOC-STRUCTURE
+    Info: Found entity 1: WF68901IP_TOP_SOC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_ctrl.vhd
+    Info: Found design unit 1: WF68901IP_USART_CTRL-BEHAVIOR
+    Info: Found entity 1: WF68901IP_USART_CTRL
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_rx.vhd
+    Info: Found design unit 1: WF68901IP_USART_RX-BEHAVIOR
+    Info: Found entity 1: WF68901IP_USART_RX
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_top.vhd
+    Info: Found design unit 1: WF68901IP_USART_TOP-STRUCTURE
+    Info: Found entity 1: WF68901IP_USART_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_tx.vhd
+    Info: Found design unit 1: WF68901IP_USART_TX-BEHAVIOR
+    Info: Found entity 1: WF68901IP_USART_TX
+Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_pkg.vhd
+    Info: Found design unit 1: WF2149IP_PKG
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top.vhd
+    Info: Found design unit 1: WF2149IP_TOP-STRUCTURE
+    Info: Found entity 1: WF2149IP_TOP
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top_soc.vhd
+    Info: Found design unit 1: WF2149IP_TOP_SOC-STRUCTURE
+    Info: Found entity 1: WF2149IP_TOP_SOC
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_wave.vhd
+    Info: Found design unit 1: WF2149IP_WAVE-BEHAVIOR
+    Info: Found entity 1: WF2149IP_WAVE
+Info: Found 2 design units, including 1 entities, in source file lpm_latch0.vhd
+    Info: Found design unit 1: lpm_latch0-SYN
+    Info: Found entity 1: lpm_latch0
+Info: Found 2 design units, including 1 entities, in source file altpll1.vhd
+    Info: Found design unit 1: altpll1-SYN
+    Info: Found entity 1: altpll1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_fifodz.vhd
+    Info: Found design unit 1: lpm_fifodz-SYN
+    Info: Found entity 1: lpm_fifoDZ
+Info: Found 2 design units, including 1 entities, in source file altpll2.vhd
+    Info: Found design unit 1: altpll2-SYN
+    Info: Found entity 1: altpll2
+Info: Found 2 design units, including 1 entities, in source file altpll3.vhd
+    Info: Found design unit 1: altpll3-SYN
+    Info: Found entity 1: altpll3
+Info: Found 2 design units, including 1 entities, in source file video/altdpram0.vhd
+    Info: Found design unit 1: altdpram0-SYN
+    Info: Found entity 1: altdpram0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz2.vhd
+    Info: Found design unit 1: lpm_muxdz2-SYN
+    Info: Found entity 1: lpm_muxDZ2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz.vhd
+    Info: Found design unit 1: lpm_muxdz-SYN
+    Info: Found entity 1: lpm_muxDZ
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri3.vhd
+    Info: Found design unit 1: lpm_bustri3-SYN
+    Info: Found entity 1: lpm_bustri3
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff0.vhd
+    Info: Found design unit 1: lpm_ff0-SYN
+    Info: Found entity 1: lpm_ff0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff1.vhd
+    Info: Found design unit 1: lpm_ff1-SYN
+    Info: Found entity 1: lpm_ff1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff3.vhd
+    Info: Found design unit 1: lpm_ff3-SYN
+    Info: Found entity 1: lpm_ff3
+Info: Found 1 design units, including 1 entities, in source file video/video_mod_mux_clutctr.tdf
+    Info: Found entity 1: VIDEO_MOD_MUX_CLUTCTR
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff2.vhd
+    Info: Found design unit 1: lpm_ff2-SYN
+    Info: Found entity 1: lpm_ff2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_fifo_dc0.vhd
+    Info: Found design unit 1: lpm_fifo_dc0-SYN
+    Info: Found entity 1: lpm_fifo_dc0
+Info: Found 1 design units, including 1 entities, in source file video/video.bdf
+    Info: Found entity 1: Video
+Info: Found 1 design units, including 1 entities, in source file firebee1.bdf
+    Info: Found entity 1: firebee1
+Info: Found 2 design units, including 1 entities, in source file altpll0.vhd
+    Info: Found design unit 1: altpll0-SYN
+    Info: Found entity 1: altpll0
+Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd
+    Info: Found design unit 1: lpm_counter0-SYN
+    Info: Found entity 1: lpm_counter0
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf.vhd
+    Info: Found design unit 1: FalconIO_SDCard_IDE_CF-FalconIO_SDCard_IDE_CF_architecture
+    Info: Found entity 1: FalconIO_SDCard_IDE_CF
+Info: Found 2 design units, including 1 entities, in source file dsp/dsp.vhd
+    Info: Found design unit 1: DSP-DSP_architecture
+    Info: Found entity 1: DSP
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg0.vhd
+    Info: Found design unit 1: lpm_shiftreg0-SYN
+    Info: Found entity 1: lpm_shiftreg0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri1.vhd
+    Info: Found design unit 1: lpm_bustri1-SYN
+    Info: Found entity 1: lpm_bustri1
+Info: Found 2 design units, including 1 entities, in source file video/altdpram1.vhd
+    Info: Found design unit 1: altdpram1-SYN
+    Info: Found entity 1: altdpram1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri2.vhd
+    Info: Found design unit 1: lpm_bustri2-SYN
+    Info: Found entity 1: lpm_bustri2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri4.vhd
+    Info: Found design unit 1: lpm_bustri4-SYN
+    Info: Found entity 1: lpm_bustri4
+Info: Found 2 design units, including 1 entities, in source file video/lpm_constant0.vhd
+    Info: Found design unit 1: lpm_constant0-SYN
+    Info: Found entity 1: lpm_constant0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_constant1.vhd
+    Info: Found design unit 1: lpm_constant1-SYN
+    Info: Found entity 1: lpm_constant1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux0.vhd
+    Info: Found design unit 1: lpm_mux0-SYN
+    Info: Found entity 1: lpm_mux0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux1.vhd
+    Info: Found design unit 1: lpm_mux1-SYN
+    Info: Found entity 1: lpm_mux1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux2.vhd
+    Info: Found design unit 1: lpm_mux2-SYN
+    Info: Found entity 1: lpm_mux2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_constant2.vhd
+    Info: Found design unit 1: lpm_constant2-SYN
+    Info: Found entity 1: lpm_constant2
+Info: Found 2 design units, including 1 entities, in source file video/altdpram2.vhd
+    Info: Found design unit 1: altdpram2-SYN
+    Info: Found entity 1: altdpram2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri6.vhd
+    Info: Found design unit 1: lpm_bustri6-SYN
+    Info: Found entity 1: lpm_bustri6
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux3.vhd
+    Info: Found design unit 1: lpm_mux3-SYN
+    Info: Found entity 1: lpm_mux3
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux4.vhd
+    Info: Found design unit 1: lpm_mux4-SYN
+    Info: Found entity 1: lpm_mux4
+Info: Found 2 design units, including 1 entities, in source file video/lpm_constant3.vhd
+    Info: Found design unit 1: lpm_constant3-SYN
+    Info: Found entity 1: lpm_constant3
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg1.vhd
+    Info: Found design unit 1: lpm_shiftreg1-SYN
+    Info: Found entity 1: lpm_shiftreg1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_latch1.vhd
+    Info: Found design unit 1: lpm_latch1-SYN
+    Info: Found entity 1: lpm_latch1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_constant4.vhd
+    Info: Found design unit 1: lpm_constant4-SYN
+    Info: Found entity 1: lpm_constant4
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg2.vhd
+    Info: Found design unit 1: lpm_shiftreg2-SYN
+    Info: Found entity 1: lpm_shiftreg2
+Info: Found 2 design units, including 1 entities, in source file video/lpm_compare1.vhd
+    Info: Found design unit 1: lpm_compare1-SYN
+    Info: Found entity 1: lpm_compare1
+Info: Found 1 design units, including 1 entities, in source file interrupt_handler/interrupt_handler.tdf
+    Info: Found entity 1: interrupt_handler
+Info: Found 2 design units, including 1 entities, in source file lpm_bustri_long.vhd
+    Info: Found design unit 1: lpm_bustri_long-SYN
+    Info: Found entity 1: lpm_bustri_LONG
+Info: Found 2 design units, including 1 entities, in source file lpm_bustri_byt.vhd
+    Info: Found design unit 1: lpm_bustri_byt-SYN
+    Info: Found entity 1: lpm_bustri_BYT
+Info: Found 2 design units, including 1 entities, in source file lpm_bustri_word.vhd
+    Info: Found design unit 1: lpm_bustri_word-SYN
+    Info: Found entity 1: lpm_bustri_WORD
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff4.vhd
+    Info: Found design unit 1: lpm_ff4-SYN
+    Info: Found entity 1: lpm_ff4
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff5.vhd
+    Info: Found design unit 1: lpm_ff5-SYN
+    Info: Found entity 1: lpm_ff5
+Info: Found 2 design units, including 1 entities, in source file video/lpm_ff6.vhd
+    Info: Found design unit 1: lpm_ff6-SYN
+    Info: Found entity 1: lpm_ff6
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg3.vhd
+    Info: Found design unit 1: lpm_shiftreg3-SYN
+    Info: Found entity 1: lpm_shiftreg3
+Info: Found 2 design units, including 1 entities, in source file video/altddio_bidir0.vhd
+    Info: Found design unit 1: altddio_bidir0-SYN
+    Info: Found entity 1: altddio_bidir0
+Info: Found 2 design units, including 1 entities, in source file video/altddio_out0.vhd
+    Info: Found design unit 1: altddio_out0-SYN
+    Info: Found entity 1: altddio_out0
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux5.vhd
+    Info: Found design unit 1: lpm_mux5-SYN
+    Info: Found entity 1: lpm_mux5
+Info: Found 2 design units, including 1 entities, in source file video/blitter/blitter.vhd
+    Info: Found design unit 1: BLITTER-BLITTER_architecture
+    Info: Found entity 1: BLITTER
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg5.vhd
+    Info: Found design unit 1: lpm_shiftreg5-SYN
+    Info: Found entity 1: lpm_shiftreg5
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg6.vhd
+    Info: Found design unit 1: lpm_shiftreg6-SYN
+    Info: Found entity 1: lpm_shiftreg6
+Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg4.vhd
+    Info: Found design unit 1: lpm_shiftreg4-SYN
+    Info: Found entity 1: lpm_shiftreg4
+Info: Found 2 design units, including 1 entities, in source file video/altddio_out1.vhd
+    Info: Found design unit 1: altddio_out1-SYN
+    Info: Found entity 1: altddio_out1
+Info: Found 2 design units, including 1 entities, in source file video/altddio_out2.vhd
+    Info: Found design unit 1: altddio_out2-SYN
+    Info: Found entity 1: altddio_out2
+Info: Found 2 design units, including 1 entities, in source file altddio_out3.vhd
+    Info: Found design unit 1: altddio_out3-SYN
+    Info: Found entity 1: altddio_out3
+Info: Found 2 design units, including 1 entities, in source file video/lpm_mux6.vhd
+    Info: Found design unit 1: lpm_mux6-SYN
+    Info: Found entity 1: lpm_mux6
+Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf_pgk.vhd
+    Info: Found design unit 1: FalconIO_SDCard_IDE_CF_PKG
+Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo1.vhd
+    Info: Found design unit 1: dcfifo1-SYN
+    Info: Found entity 1: dcfifo1
+Info: Found 2 design units, including 1 entities, in source file video/lpm_muxvdm.vhd
+    Info: Found design unit 1: lpm_muxvdm-SYN
+    Info: Found entity 1: lpm_muxVDM
+Info: Elaborating entity "firebee1" for the top level hierarchy
+Warning: Pin "TOUT0" not connected
+Warning: Pin "nMASTER" not connected
+Info: Elaborating entity "altpll1" for hierarchy "altpll1:inst"
+Info: Elaborating entity "altpll" for hierarchy "altpll1:inst|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "altpll1:inst|altpll:altpll_component"
+Info: Instantiated megafunction "altpll1:inst|altpll:altpll_component" with the following parameter:
+    Info: Parameter "bandwidth_type" = "AUTO"
+    Info: Parameter "clk0_divide_by" = "66"
+    Info: Parameter "clk0_duty_cycle" = "50"
+    Info: Parameter "clk0_multiply_by" = "1"
+    Info: Parameter "clk0_phase_shift" = "0"
+    Info: Parameter "clk1_divide_by" = "900"
+    Info: Parameter "clk1_duty_cycle" = "50"
+    Info: Parameter "clk1_multiply_by" = "67"
+    Info: Parameter "clk1_phase_shift" = "0"
+    Info: Parameter "clk2_divide_by" = "90"
+    Info: Parameter "clk2_duty_cycle" = "50"
+    Info: Parameter "clk2_multiply_by" = "67"
+    Info: Parameter "clk2_phase_shift" = "0"
+    Info: Parameter "compensate_clock" = "CLK0"
+    Info: Parameter "inclk0_input_frequency" = "30303"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altpll"
+    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
+    Info: Parameter "pll_type" = "AUTO"
+    Info: Parameter "port_activeclock" = "PORT_UNUSED"
+    Info: Parameter "port_areset" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info: Parameter "port_clkloss" = "PORT_UNUSED"
+    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info: Parameter "port_configupdate" = "PORT_UNUSED"
+    Info: Parameter "port_fbin" = "PORT_UNUSED"
+    Info: Parameter "port_inclk0" = "PORT_USED"
+    Info: Parameter "port_inclk1" = "PORT_UNUSED"
+    Info: Parameter "port_locked" = "PORT_USED"
+    Info: Parameter "port_pfdena" = "PORT_UNUSED"
+    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info: Parameter "port_phasedone" = "PORT_UNUSED"
+    Info: Parameter "port_phasestep" = "PORT_UNUSED"
+    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info: Parameter "port_pllena" = "PORT_UNUSED"
+    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info: Parameter "port_scanclk" = "PORT_UNUSED"
+    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info: Parameter "port_scandata" = "PORT_UNUSED"
+    Info: Parameter "port_scandataout" = "PORT_UNUSED"
+    Info: Parameter "port_scandone" = "PORT_UNUSED"
+    Info: Parameter "port_scanread" = "PORT_UNUSED"
+    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info: Parameter "port_clk0" = "PORT_USED"
+    Info: Parameter "port_clk1" = "PORT_USED"
+    Info: Parameter "port_clk2" = "PORT_USED"
+    Info: Parameter "port_clk3" = "PORT_UNUSED"
+    Info: Parameter "port_clk4" = "PORT_UNUSED"
+    Info: Parameter "port_clk5" = "PORT_UNUSED"
+    Info: Parameter "port_clkena0" = "PORT_UNUSED"
+    Info: Parameter "port_clkena1" = "PORT_UNUSED"
+    Info: Parameter "port_clkena2" = "PORT_UNUSED"
+    Info: Parameter "port_clkena3" = "PORT_UNUSED"
+    Info: Parameter "port_clkena4" = "PORT_UNUSED"
+    Info: Parameter "port_clkena5" = "PORT_UNUSED"
+    Info: Parameter "port_extclk0" = "PORT_UNUSED"
+    Info: Parameter "port_extclk1" = "PORT_UNUSED"
+    Info: Parameter "port_extclk2" = "PORT_UNUSED"
+    Info: Parameter "port_extclk3" = "PORT_UNUSED"
+    Info: Parameter "self_reset_on_loss_lock" = "OFF"
+    Info: Parameter "width_clock" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/altpll_pul2.tdf
+    Info: Found entity 1: altpll_pul2
+Info: Elaborating entity "altpll_pul2" for hierarchy "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated"
+Info: Elaborating entity "FalconIO_SDCard_IDE_CF" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden"
+Warning (10036): Verilog HDL or VHDL warning at FalconIO_SDCard_IDE_CF.vhd(244): object "SCSI_CSn" assigned a value but never read
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(303): signal "nIDE_RD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(304): signal "nIDE_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(313): signal "IDE_CF_CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(314): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(315): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(324): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(325): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(335): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(336): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
+Critical Warning (10920): VHDL Incomplete Partial Association warning at FalconIO_SDCard_IDE_CF.vhd(928): port or argument "IO_A_OUT" has 1/8 unassociated elements
+Info: Elaborating entity "dcfifo0" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF"
+Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
+Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
+Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter:
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_numwords" = "1024"
+    Info: Parameter "lpm_showahead" = "OFF"
+    Info: Parameter "lpm_type" = "dcfifo"
+    Info: Parameter "lpm_width" = "8"
+    Info: Parameter "lpm_widthu" = "10"
+    Info: Parameter "lpm_widthu_r" = "8"
+    Info: Parameter "lpm_width_r" = "32"
+    Info: Parameter "overflow_checking" = "ON"
+    Info: Parameter "rdsync_delaypipe" = "5"
+    Info: Parameter "underflow_checking" = "ON"
+    Info: Parameter "use_eab" = "ON"
+    Info: Parameter "write_aclr_synch" = "OFF"
+    Info: Parameter "wrsync_delaypipe" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/dcfifo_0hh1.tdf
+    Info: Found entity 1: dcfifo_0hh1
+Info: Elaborating entity "dcfifo_0hh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated"
+Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_lfb.tdf
+    Info: Found entity 1: a_gray2bin_lfb
+Info: Elaborating entity "a_gray2bin_lfb" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_k47.tdf
+    Info: Found entity 1: a_graycounter_k47
+Info: Elaborating entity "a_graycounter_k47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fic.tdf
+    Info: Found entity 1: a_graycounter_fic
+Info: Elaborating entity "a_graycounter_fic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bi31.tdf
+    Info: Found entity 1: altsyncram_bi31
+Info: Elaborating entity "altsyncram_bi31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf
+    Info: Found entity 1: alt_synch_pipe_ikd
+Info: Elaborating entity "alt_synch_pipe_ikd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf
+    Info: Found entity 1: dffpipe_hd9
+Info: Elaborating entity "dffpipe_hd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
+    Info: Found entity 1: dffpipe_gd9
+Info: Elaborating entity "dffpipe_gd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info: Found entity 1: dffpipe_pe9
+Info: Elaborating entity "dffpipe_pe9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jkd.tdf
+    Info: Found entity 1: alt_synch_pipe_jkd
+Info: Elaborating entity "alt_synch_pipe_jkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf
+    Info: Found entity 1: dffpipe_id9
+Info: Elaborating entity "dffpipe_id9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17"
+Info: Found 1 design units, including 1 entities, in source file db/cmpr_256.tdf
+    Info: Found entity 1: cmpr_256
+Info: Elaborating entity "cmpr_256" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_256:rdempty_eq_comp1_lsb"
+Info: Found 1 design units, including 1 entities, in source file db/cmpr_156.tdf
+    Info: Found entity 1: cmpr_156
+Info: Elaborating entity "cmpr_156" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_t2e.tdf
+    Info: Found entity 1: cntr_t2e
+Info: Elaborating entity "cntr_t2e" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b"
+Info: Found 1 design units, including 1 entities, in source file db/mux_a18.tdf
+    Info: Found entity 1: mux_a18
+Info: Elaborating entity "mux_a18" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux"
+Info: Elaborating entity "dcfifo1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF"
+Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
+Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
+Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter:
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_numwords" = "256"
+    Info: Parameter "lpm_showahead" = "OFF"
+    Info: Parameter "lpm_type" = "dcfifo"
+    Info: Parameter "lpm_width" = "32"
+    Info: Parameter "lpm_widthu" = "8"
+    Info: Parameter "lpm_widthu_r" = "10"
+    Info: Parameter "lpm_width_r" = "8"
+    Info: Parameter "overflow_checking" = "ON"
+    Info: Parameter "rdsync_delaypipe" = "5"
+    Info: Parameter "underflow_checking" = "ON"
+    Info: Parameter "use_eab" = "ON"
+    Info: Parameter "write_aclr_synch" = "OFF"
+    Info: Parameter "wrsync_delaypipe" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/dcfifo_3fh1.tdf
+    Info: Found entity 1: dcfifo_3fh1
+Info: Elaborating entity "dcfifo_3fh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j47.tdf
+    Info: Found entity 1: a_graycounter_j47
+Info: Elaborating entity "a_graycounter_j47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_gic.tdf
+    Info: Found entity 1: a_graycounter_gic
+Info: Elaborating entity "a_graycounter_gic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ci31.tdf
+    Info: Found entity 1: altsyncram_ci31
+Info: Elaborating entity "altsyncram_ci31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_kkd.tdf
+    Info: Found entity 1: alt_synch_pipe_kkd
+Info: Elaborating entity "alt_synch_pipe_kkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf
+    Info: Found entity 1: dffpipe_jd9
+Info: Elaborating entity "dffpipe_jd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lkd.tdf
+    Info: Found entity 1: alt_synch_pipe_lkd
+Info: Elaborating entity "alt_synch_pipe_lkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_kd9.tdf
+    Info: Found entity 1: dffpipe_kd9
+Info: Elaborating entity "dffpipe_kd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15"
+Info: Elaborating entity "WF1772IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"
+Info: Elaborating entity "WF1772IP_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL"
+Info: Elaborating entity "WF1772IP_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS"
+Info: Elaborating entity "WF1772IP_DIGITAL_PLL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL"
+Info: Elaborating entity "WF1772IP_AM_DETECTOR" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR"
+Info: Elaborating entity "WF1772IP_CRC_LOGIC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC"
+Info: Elaborating entity "WF1772IP_TRANSCEIVER" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER"
+Info: Elaborating entity "WF5380_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"
+Info: Elaborating entity "WF5380_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS"
+Info: Elaborating entity "WF5380_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL"
+Info: Elaborating entity "WF6850IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD"
+Info: Elaborating entity "WF6850IP_CTRL_STATUS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS"
+Info: Elaborating entity "WF6850IP_RECEIVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE"
+Info: Elaborating entity "WF6850IP_TRANSMIT" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT"
+Info: Elaborating entity "WF68901IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"
+Info: Elaborating entity "WF68901IP_USART_TOP" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART"
+Info: Elaborating entity "WF68901IP_USART_CTRL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL"
+Info: Elaborating entity "WF68901IP_USART_RX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE"
+Info: Elaborating entity "WF68901IP_USART_TX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT"
+Info: Elaborating entity "WF68901IP_INTERRUPTS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS"
+Info: Elaborating entity "WF68901IP_GPIO" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO"
+Info: Elaborating entity "WF68901IP_TIMERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS"
+Info: Elaborating entity "WF2149IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"
+Info: Elaborating entity "WF2149IP_WAVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE"
+Info: Elaborating entity "altpll3" for hierarchy "altpll3:inst13"
+Info: Elaborating entity "altpll" for hierarchy "altpll3:inst13|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "altpll3:inst13|altpll:altpll_component"
+Info: Instantiated megafunction "altpll3:inst13|altpll:altpll_component" with the following parameter:
+    Info: Parameter "bandwidth_type" = "AUTO"
+    Info: Parameter "clk0_divide_by" = "33"
+    Info: Parameter "clk0_duty_cycle" = "50"
+    Info: Parameter "clk0_multiply_by" = "2"
+    Info: Parameter "clk0_phase_shift" = "0"
+    Info: Parameter "clk1_divide_by" = "33"
+    Info: Parameter "clk1_duty_cycle" = "50"
+    Info: Parameter "clk1_multiply_by" = "16"
+    Info: Parameter "clk1_phase_shift" = "0"
+    Info: Parameter "clk2_divide_by" = "33"
+    Info: Parameter "clk2_duty_cycle" = "50"
+    Info: Parameter "clk2_multiply_by" = "25"
+    Info: Parameter "clk2_phase_shift" = "0"
+    Info: Parameter "clk3_divide_by" = "11"
+    Info: Parameter "clk3_duty_cycle" = "50"
+    Info: Parameter "clk3_multiply_by" = "16"
+    Info: Parameter "clk3_phase_shift" = "0"
+    Info: Parameter "compensate_clock" = "CLK1"
+    Info: Parameter "inclk0_input_frequency" = "30303"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altpll"
+    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
+    Info: Parameter "pll_type" = "AUTO"
+    Info: Parameter "port_activeclock" = "PORT_UNUSED"
+    Info: Parameter "port_areset" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info: Parameter "port_clkloss" = "PORT_UNUSED"
+    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info: Parameter "port_configupdate" = "PORT_UNUSED"
+    Info: Parameter "port_fbin" = "PORT_UNUSED"
+    Info: Parameter "port_inclk0" = "PORT_USED"
+    Info: Parameter "port_inclk1" = "PORT_UNUSED"
+    Info: Parameter "port_locked" = "PORT_UNUSED"
+    Info: Parameter "port_pfdena" = "PORT_UNUSED"
+    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info: Parameter "port_phasedone" = "PORT_UNUSED"
+    Info: Parameter "port_phasestep" = "PORT_UNUSED"
+    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info: Parameter "port_pllena" = "PORT_UNUSED"
+    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info: Parameter "port_scanclk" = "PORT_UNUSED"
+    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info: Parameter "port_scandata" = "PORT_UNUSED"
+    Info: Parameter "port_scandataout" = "PORT_UNUSED"
+    Info: Parameter "port_scandone" = "PORT_UNUSED"
+    Info: Parameter "port_scanread" = "PORT_UNUSED"
+    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info: Parameter "port_clk0" = "PORT_USED"
+    Info: Parameter "port_clk1" = "PORT_USED"
+    Info: Parameter "port_clk2" = "PORT_USED"
+    Info: Parameter "port_clk3" = "PORT_USED"
+    Info: Parameter "port_clk4" = "PORT_UNUSED"
+    Info: Parameter "port_clk5" = "PORT_UNUSED"
+    Info: Parameter "port_clkena0" = "PORT_UNUSED"
+    Info: Parameter "port_clkena1" = "PORT_UNUSED"
+    Info: Parameter "port_clkena2" = "PORT_UNUSED"
+    Info: Parameter "port_clkena3" = "PORT_UNUSED"
+    Info: Parameter "port_clkena4" = "PORT_UNUSED"
+    Info: Parameter "port_clkena5" = "PORT_UNUSED"
+    Info: Parameter "port_extclk0" = "PORT_UNUSED"
+    Info: Parameter "port_extclk1" = "PORT_UNUSED"
+    Info: Parameter "port_extclk2" = "PORT_UNUSED"
+    Info: Parameter "port_extclk3" = "PORT_UNUSED"
+    Info: Parameter "width_clock" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/altpll_41p2.tdf
+    Info: Found entity 1: altpll_41p2
+Info: Elaborating entity "altpll_41p2" for hierarchy "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated"
+Info: Elaborating entity "Video" for hierarchy "Video:Fredi_Aschwanden"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ADR[31..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "MAIN_CLK"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS1"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS2"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS3"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_WR"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE0"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE1"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nRSTO"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_OE"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ALE"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDRCLK[3..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDR_SYNC_66M"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK33M"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK25M"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK_VIDEO"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_D[8..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_BUSY"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VG[7..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VB[7..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR[7..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nBLANK"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VA[12..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVWE"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCAS"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVRAS"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCS"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDM[3..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nPD_VGA"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VCKE"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VSYNC"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "HSYNC"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nSYNC"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_TA"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "PIXEL_CLK"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "BA[1..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_RECONFIG"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_WR"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_RD"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDQS[3..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_AD[31..0]"
+Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VD[31..0]"
+Info: Elaborating entity "VIDEO_MOD_MUX_CLUTCTR" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR"
+Warning: Variable or input pin "nRSTO" is defined but never used
+Warning: Variable or input pin "nFB_CS3" is defined but never used
+Warning: Variable or input pin "nFB_BURST" is defined but never used
+Info: Elaborating entity "lpm_bustri_WORD" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000"
+Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_BUSTRI"
+    Info: Parameter "lpm_width" = "16"
+Info: Elaborating entity "BLITTER" for hierarchy "Video:Fredi_Aschwanden|BLITTER:BLITTER"
+Info: Elaborating entity "lpm_shiftreg6" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89"
+Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
+    Info: Parameter "lpm_direction" = "RIGHT"
+    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
+    Info: Parameter "lpm_width" = "5"
+Info: Elaborating entity "DDR_CTR" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR"
+Warning: Variable or input pin "nFB_CS2" is defined but never used
+Warning: Variable or input pin "nFB_CS3" is defined but never used
+Warning: Variable or input pin "nRSTO" is defined but never used
+Info: Elaborating entity "lpm_bustri_BYT" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002"
+Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_BUSTRI"
+    Info: Parameter "lpm_width" = "8"
+Info: Elaborating entity "lpm_fifo_dc0" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst"
+Info: Elaborating entity "dcfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" with the following parameter:
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_numwords" = "512"
+    Info: Parameter "lpm_showahead" = "OFF"
+    Info: Parameter "lpm_type" = "dcfifo"
+    Info: Parameter "lpm_width" = "128"
+    Info: Parameter "lpm_widthu" = "9"
+    Info: Parameter "overflow_checking" = "OFF"
+    Info: Parameter "rdsync_delaypipe" = "6"
+    Info: Parameter "underflow_checking" = "OFF"
+    Info: Parameter "use_eab" = "ON"
+    Info: Parameter "write_aclr_synch" = "ON"
+    Info: Parameter "wrsync_delaypipe" = "6"
+Info: Found 1 design units, including 1 entities, in source file db/dcfifo_8fi1.tdf
+    Info: Found entity 1: dcfifo_8fi1
+Info: Elaborating entity "dcfifo_8fi1" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated"
+Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info: Found entity 1: a_gray2bin_tgb
+Info: Elaborating entity "a_gray2bin_tgb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info: Found entity 1: a_graycounter_s57
+Info: Elaborating entity "a_graycounter_s57" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info: Found entity 1: a_graycounter_ojc
+Info: Elaborating entity "a_graycounter_ojc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_njc.tdf
+    Info: Found entity 1: a_graycounter_njc
+Info: Elaborating entity "a_graycounter_njc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tl31.tdf
+    Info: Found entity 1: altsyncram_tl31
+Info: Elaborating entity "altsyncram_tl31" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info: Found entity 1: alt_synch_pipe_rld
+Info: Elaborating entity "alt_synch_pipe_rld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info: Found entity 1: dffpipe_qe9
+Info: Elaborating entity "dffpipe_qe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_9d9.tdf
+    Info: Found entity 1: dffpipe_9d9
+Info: Elaborating entity "dffpipe_9d9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info: Found entity 1: dffpipe_oe9
+Info: Elaborating entity "dffpipe_oe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp"
+Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf
+    Info: Found entity 1: alt_synch_pipe_sld
+Info: Elaborating entity "alt_synch_pipe_sld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp"
+Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
+    Info: Found entity 1: dffpipe_re9
+Info: Elaborating entity "dffpipe_re9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22"
+Info: Elaborating entity "lpm_shiftreg4" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26"
+Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
+    Info: Parameter "lpm_direction" = "RIGHT"
+    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
+    Info: Parameter "lpm_width" = "5"
+Info: Elaborating entity "lpm_muxVDM" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "128"
+    Info: Parameter "LPM_SIZE" = "16"
+    Info: Parameter "LPM_WIDTHS" = "4"
+    Info: Parameter "LPM_PIPELINE" = "0"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_bbe.tdf
+    Info: Found entity 1: mux_bbe
+Info: Elaborating entity "mux_bbe" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component|mux_bbe:auto_generated"
+Info: Elaborating entity "lpm_ff6" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "128"
+Info: Elaborating entity "lpm_ff1" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "32"
+Info: Elaborating entity "altddio_bidir0" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1"
+Info: Elaborating entity "altddio_bidir" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" with the following parameter:
+    Info: Parameter "extend_oe_disable" = "UNUSED"
+    Info: Parameter "implement_input_in_lcell" = "ON"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "invert_output" = "OFF"
+    Info: Parameter "lpm_type" = "altddio_bidir"
+    Info: Parameter "oe_reg" = "UNUSED"
+    Info: Parameter "power_up_high" = "OFF"
+    Info: Parameter "width" = "32"
+Info: Found 1 design units, including 1 entities, in source file db/ddio_bidir_3jl.tdf
+    Info: Found entity 1: ddio_bidir_3jl
+Info: Elaborating entity "ddio_bidir_3jl" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated"
+Info: Elaborating entity "lpm_mux5" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "64"
+    Info: Parameter "LPM_SIZE" = "4"
+    Info: Parameter "LPM_WIDTHS" = "2"
+    Info: Parameter "LPM_PIPELINE" = "0"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_58e.tdf
+    Info: Found entity 1: mux_58e
+Info: Elaborating entity "mux_58e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component|mux_58e:auto_generated"
+Info: Elaborating entity "lpm_ff0" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "32"
+Info: Elaborating entity "lpm_bustri_LONG" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108"
+Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_BUSTRI"
+    Info: Parameter "lpm_width" = "32"
+Info: Elaborating entity "lpm_latch0" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27"
+Info: Elaborating entity "lpm_latch" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_LATCH"
+    Info: Parameter "lpm_width" = "32"
+Info: Elaborating entity "lpm_bustri3" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66"
+Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_BUSTRI"
+    Info: Parameter "lpm_width" = "6"
+Info: Elaborating entity "altdpram1" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED"
+Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" with the following parameter:
+    Info: Parameter "address_reg_b" = "CLOCK1"
+    Info: Parameter "clock_enable_input_a" = "BYPASS"
+    Info: Parameter "clock_enable_input_b" = "BYPASS"
+    Info: Parameter "clock_enable_output_a" = "BYPASS"
+    Info: Parameter "clock_enable_output_b" = "BYPASS"
+    Info: Parameter "indata_reg_b" = "CLOCK1"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altsyncram"
+    Info: Parameter "numwords_a" = "256"
+    Info: Parameter "numwords_b" = "256"
+    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
+    Info: Parameter "outdata_aclr_a" = "NONE"
+    Info: Parameter "outdata_aclr_b" = "NONE"
+    Info: Parameter "outdata_reg_a" = "CLOCK0"
+    Info: Parameter "outdata_reg_b" = "CLOCK1"
+    Info: Parameter "power_up_uninitialized" = "FALSE"
+    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
+    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
+    Info: Parameter "widthad_a" = "8"
+    Info: Parameter "widthad_b" = "8"
+    Info: Parameter "width_a" = "6"
+    Info: Parameter "width_b" = "6"
+    Info: Parameter "width_byteena_a" = "1"
+    Info: Parameter "width_byteena_b" = "1"
+    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lf92.tdf
+    Info: Found entity 1: altsyncram_lf92
+Info: Elaborating entity "altsyncram_lf92" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated"
+Info: Elaborating entity "lpm_shiftreg0" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0"
+Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
+    Info: Parameter "lpm_direction" = "LEFT"
+    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
+    Info: Parameter "lpm_width" = "16"
+Info: Elaborating entity "MUX41" for hierarchy "Video:Fredi_Aschwanden|MUX41:inst45"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|MUX41:inst45"
+Info: Elaborating entity "lpm_muxDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "128"
+    Info: Parameter "LPM_SIZE" = "2"
+    Info: Parameter "LPM_WIDTHS" = "1"
+    Info: Parameter "LPM_PIPELINE" = "1"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_dcf.tdf
+    Info: Found entity 1: mux_dcf
+Info: Elaborating entity "mux_dcf" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component|mux_dcf:auto_generated"
+Info: Elaborating entity "lpm_fifoDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63"
+Info: Elaborating entity "scfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" with the following parameter:
+    Info: Parameter "add_ram_output_register" = "OFF"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_numwords" = "128"
+    Info: Parameter "lpm_showahead" = "ON"
+    Info: Parameter "lpm_type" = "scfifo"
+    Info: Parameter "lpm_width" = "128"
+    Info: Parameter "lpm_widthu" = "7"
+    Info: Parameter "overflow_checking" = "OFF"
+    Info: Parameter "underflow_checking" = "OFF"
+    Info: Parameter "use_eab" = "ON"
+Info: Found 1 design units, including 1 entities, in source file db/scfifo_lk21.tdf
+    Info: Found entity 1: scfifo_lk21
+Info: Elaborating entity "scfifo_lk21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated"
+Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oq21.tdf
+    Info: Found entity 1: a_dpfifo_oq21
+Info: Elaborating entity "a_dpfifo_oq21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gj81.tdf
+    Info: Found entity 1: altsyncram_gj81
+Info: Elaborating entity "altsyncram_gj81" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram"
+Info: Found 1 design units, including 1 entities, in source file db/cmpr_br8.tdf
+    Info: Found entity 1: cmpr_br8
+Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:almost_full_comparer"
+Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:three_comparison"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf
+    Info: Found entity 1: cntr_omb
+Info: Elaborating entity "cntr_omb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_5n7.tdf
+    Info: Found entity 1: cntr_5n7
+Info: Elaborating entity "cntr_5n7" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_pmb.tdf
+    Info: Found entity 1: cntr_pmb
+Info: Elaborating entity "cntr_pmb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr"
+Info: Elaborating entity "lpm_bustri1" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51"
+Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" with the following parameter:
+    Info: Parameter "lpm_type" = "LPM_BUSTRI"
+    Info: Parameter "lpm_width" = "3"
+Info: Elaborating entity "altdpram0" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED"
+Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" with the following parameter:
+    Info: Parameter "address_reg_b" = "CLOCK1"
+    Info: Parameter "clock_enable_input_a" = "BYPASS"
+    Info: Parameter "clock_enable_input_b" = "BYPASS"
+    Info: Parameter "clock_enable_output_a" = "BYPASS"
+    Info: Parameter "clock_enable_output_b" = "BYPASS"
+    Info: Parameter "indata_reg_b" = "CLOCK1"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altsyncram"
+    Info: Parameter "numwords_a" = "16"
+    Info: Parameter "numwords_b" = "16"
+    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
+    Info: Parameter "outdata_aclr_a" = "NONE"
+    Info: Parameter "outdata_aclr_b" = "NONE"
+    Info: Parameter "outdata_reg_a" = "CLOCK0"
+    Info: Parameter "outdata_reg_b" = "CLOCK1"
+    Info: Parameter "power_up_uninitialized" = "FALSE"
+    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
+    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
+    Info: Parameter "widthad_a" = "4"
+    Info: Parameter "widthad_b" = "4"
+    Info: Parameter "width_a" = "3"
+    Info: Parameter "width_b" = "3"
+    Info: Parameter "width_byteena_a" = "1"
+    Info: Parameter "width_byteena_b" = "1"
+    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rb92.tdf
+    Info: Found entity 1: altsyncram_rb92
+Info: Elaborating entity "altsyncram_rb92" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated"
+Info: Elaborating entity "altdpram2" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55"
+Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" with the following parameter:
+    Info: Parameter "address_reg_b" = "CLOCK1"
+    Info: Parameter "clock_enable_input_a" = "BYPASS"
+    Info: Parameter "clock_enable_input_b" = "BYPASS"
+    Info: Parameter "clock_enable_output_a" = "BYPASS"
+    Info: Parameter "clock_enable_output_b" = "BYPASS"
+    Info: Parameter "indata_reg_b" = "CLOCK1"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altsyncram"
+    Info: Parameter "numwords_a" = "256"
+    Info: Parameter "numwords_b" = "256"
+    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
+    Info: Parameter "outdata_aclr_a" = "NONE"
+    Info: Parameter "outdata_aclr_b" = "NONE"
+    Info: Parameter "outdata_reg_a" = "CLOCK0"
+    Info: Parameter "outdata_reg_b" = "CLOCK1"
+    Info: Parameter "power_up_uninitialized" = "FALSE"
+    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
+    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
+    Info: Parameter "widthad_a" = "8"
+    Info: Parameter "widthad_b" = "8"
+    Info: Parameter "width_a" = "8"
+    Info: Parameter "width_b" = "8"
+    Info: Parameter "width_byteena_a" = "1"
+    Info: Parameter "width_byteena_b" = "1"
+    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pf92.tdf
+    Info: Found entity 1: altsyncram_pf92
+Info: Elaborating entity "altsyncram_pf92" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated"
+Info: Elaborating entity "lpm_mux3" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "1"
+    Info: Parameter "LPM_SIZE" = "2"
+    Info: Parameter "LPM_WIDTHS" = "1"
+    Info: Parameter "LPM_PIPELINE" = "0"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_96e.tdf
+    Info: Found entity 1: mux_96e
+Info: Elaborating entity "mux_96e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component|mux_96e:auto_generated"
+Info: Elaborating entity "lpm_ff5" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "8"
+Info: Elaborating entity "lpm_mux2" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "8"
+    Info: Parameter "LPM_SIZE" = "16"
+    Info: Parameter "LPM_WIDTHS" = "4"
+    Info: Parameter "LPM_PIPELINE" = "2"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_mpe.tdf
+    Info: Found entity 1: mux_mpe
+Info: Elaborating entity "mux_mpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component|mux_mpe:auto_generated"
+Info: Elaborating entity "lpm_mux4" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "7"
+    Info: Parameter "LPM_SIZE" = "2"
+    Info: Parameter "LPM_WIDTHS" = "1"
+    Info: Parameter "LPM_PIPELINE" = "0"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_f6e.tdf
+    Info: Found entity 1: mux_f6e
+Info: Elaborating entity "mux_f6e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component|mux_f6e:auto_generated"
+Info: Elaborating entity "lpm_constant3" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82"
+Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" with the following parameter:
+    Info: Parameter "lpm_cvalue" = "0"
+    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info: Parameter "lpm_type" = "LPM_CONSTANT"
+    Info: Parameter "lpm_width" = "7"
+Info: Elaborating entity "altddio_out2" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5"
+Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" with the following parameter:
+    Info: Parameter "extend_oe_disable" = "UNUSED"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "invert_output" = "OFF"
+    Info: Parameter "lpm_type" = "altddio_out"
+    Info: Parameter "oe_reg" = "UNUSED"
+    Info: Parameter "power_up_high" = "OFF"
+    Info: Parameter "width" = "24"
+Info: Found 1 design units, including 1 entities, in source file db/ddio_out_o2f.tdf
+    Info: Found entity 1: ddio_out_o2f
+Info: Elaborating entity "ddio_out_o2f" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated"
+Info: Elaborating entity "lpm_mux6" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "24"
+    Info: Parameter "LPM_SIZE" = "8"
+    Info: Parameter "LPM_WIDTHS" = "3"
+    Info: Parameter "LPM_PIPELINE" = "2"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_kpe.tdf
+    Info: Found entity 1: mux_kpe
+Info: Elaborating entity "mux_kpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component|mux_kpe:auto_generated"
+Info: Elaborating entity "lpm_ff3" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "24"
+Info: Elaborating entity "lpm_constant0" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59"
+Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" with the following parameter:
+    Info: Parameter "lpm_cvalue" = "0"
+    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info: Parameter "lpm_type" = "LPM_CONSTANT"
+    Info: Parameter "lpm_width" = "5"
+Info: Elaborating entity "lpm_constant1" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77"
+Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" with the following parameter:
+    Info: Parameter "lpm_cvalue" = "0"
+    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info: Parameter "lpm_type" = "LPM_CONSTANT"
+    Info: Parameter "lpm_width" = "2"
+Info: Elaborating entity "lpm_ff4" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10"
+Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" with the following parameter:
+    Info: Parameter "lpm_fftype" = "DFF"
+    Info: Parameter "lpm_type" = "LPM_FF"
+    Info: Parameter "lpm_width" = "16"
+Info: Elaborating entity "lpm_mux1" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component"
+Info: Assertion information: Value of LPM_PIPELINE parameter (4) should be lower -- use 1 for best performance/utilization
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "16"
+    Info: Parameter "LPM_SIZE" = "8"
+    Info: Parameter "LPM_WIDTHS" = "3"
+    Info: Parameter "LPM_PIPELINE" = "4"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Assertion information: Value of LPM_PIPELINE parameter 4 should be lower -- use 1 for best performance/utilization
+Info: Found 1 design units, including 1 entities, in source file db/mux_npe.tdf
+    Info: Found entity 1: mux_npe
+Info: Elaborating entity "mux_npe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component|mux_npe:auto_generated"
+Info: Elaborating entity "lpm_constant2" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23"
+Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" with the following parameter:
+    Info: Parameter "lpm_cvalue" = "0"
+    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
+    Info: Parameter "lpm_type" = "LPM_CONSTANT"
+    Info: Parameter "lpm_width" = "8"
+Info: Elaborating entity "lpm_mux0" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21"
+Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "32"
+    Info: Parameter "LPM_SIZE" = "4"
+    Info: Parameter "LPM_WIDTHS" = "2"
+    Info: Parameter "LPM_PIPELINE" = "4"
+    Info: Parameter "LPM_TYPE" = "LPM_MUX"
+    Info: Parameter "LPM_HINT" = "UNUSED"
+Info: Found 1 design units, including 1 entities, in source file db/mux_gpe.tdf
+    Info: Found entity 1: mux_gpe
+Info: Elaborating entity "mux_gpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component|mux_gpe:auto_generated"
+Info: Elaborating entity "altddio_out0" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2"
+Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" with the following parameter:
+    Info: Parameter "extend_oe_disable" = "UNUSED"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "invert_output" = "ON"
+    Info: Parameter "lpm_type" = "altddio_out"
+    Info: Parameter "oe_reg" = "UNUSED"
+    Info: Parameter "power_up_high" = "ON"
+    Info: Parameter "width" = "4"
+Info: Found 1 design units, including 1 entities, in source file db/ddio_out_are.tdf
+    Info: Found entity 1: ddio_out_are
+Info: Elaborating entity "ddio_out_are" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated"
+Info: Elaborating entity "altpll2" for hierarchy "altpll2:inst12"
+Info: Elaborating entity "altpll" for hierarchy "altpll2:inst12|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "altpll2:inst12|altpll:altpll_component"
+Info: Instantiated megafunction "altpll2:inst12|altpll:altpll_component" with the following parameter:
+    Info: Parameter "bandwidth_type" = "AUTO"
+    Info: Parameter "clk0_divide_by" = "1"
+    Info: Parameter "clk0_duty_cycle" = "50"
+    Info: Parameter "clk0_multiply_by" = "4"
+    Info: Parameter "clk0_phase_shift" = "5051"
+    Info: Parameter "clk1_divide_by" = "1"
+    Info: Parameter "clk1_duty_cycle" = "50"
+    Info: Parameter "clk1_multiply_by" = "4"
+    Info: Parameter "clk1_phase_shift" = "0"
+    Info: Parameter "clk2_divide_by" = "1"
+    Info: Parameter "clk2_duty_cycle" = "50"
+    Info: Parameter "clk2_multiply_by" = "4"
+    Info: Parameter "clk2_phase_shift" = "3788"
+    Info: Parameter "clk3_divide_by" = "1"
+    Info: Parameter "clk3_duty_cycle" = "50"
+    Info: Parameter "clk3_multiply_by" = "4"
+    Info: Parameter "clk3_phase_shift" = "2210"
+    Info: Parameter "clk4_divide_by" = "1"
+    Info: Parameter "clk4_duty_cycle" = "50"
+    Info: Parameter "clk4_multiply_by" = "2"
+    Info: Parameter "clk4_phase_shift" = "11364"
+    Info: Parameter "compensate_clock" = "CLK0"
+    Info: Parameter "inclk0_input_frequency" = "30303"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altpll"
+    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
+    Info: Parameter "pll_type" = "AUTO"
+    Info: Parameter "port_activeclock" = "PORT_UNUSED"
+    Info: Parameter "port_areset" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info: Parameter "port_clkloss" = "PORT_UNUSED"
+    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info: Parameter "port_configupdate" = "PORT_UNUSED"
+    Info: Parameter "port_fbin" = "PORT_UNUSED"
+    Info: Parameter "port_inclk0" = "PORT_USED"
+    Info: Parameter "port_inclk1" = "PORT_UNUSED"
+    Info: Parameter "port_locked" = "PORT_UNUSED"
+    Info: Parameter "port_pfdena" = "PORT_UNUSED"
+    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info: Parameter "port_phasedone" = "PORT_UNUSED"
+    Info: Parameter "port_phasestep" = "PORT_UNUSED"
+    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info: Parameter "port_pllena" = "PORT_UNUSED"
+    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info: Parameter "port_scanclk" = "PORT_UNUSED"
+    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info: Parameter "port_scandata" = "PORT_UNUSED"
+    Info: Parameter "port_scandataout" = "PORT_UNUSED"
+    Info: Parameter "port_scandone" = "PORT_UNUSED"
+    Info: Parameter "port_scanread" = "PORT_UNUSED"
+    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info: Parameter "port_clk0" = "PORT_USED"
+    Info: Parameter "port_clk1" = "PORT_USED"
+    Info: Parameter "port_clk2" = "PORT_USED"
+    Info: Parameter "port_clk3" = "PORT_USED"
+    Info: Parameter "port_clk4" = "PORT_USED"
+    Info: Parameter "port_clk5" = "PORT_UNUSED"
+    Info: Parameter "port_clkena0" = "PORT_UNUSED"
+    Info: Parameter "port_clkena1" = "PORT_UNUSED"
+    Info: Parameter "port_clkena2" = "PORT_UNUSED"
+    Info: Parameter "port_clkena3" = "PORT_UNUSED"
+    Info: Parameter "port_clkena4" = "PORT_UNUSED"
+    Info: Parameter "port_clkena5" = "PORT_UNUSED"
+    Info: Parameter "port_extclk0" = "PORT_UNUSED"
+    Info: Parameter "port_extclk1" = "PORT_UNUSED"
+    Info: Parameter "port_extclk2" = "PORT_UNUSED"
+    Info: Parameter "port_extclk3" = "PORT_UNUSED"
+    Info: Parameter "width_clock" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/altpll_isv2.tdf
+    Info: Found entity 1: altpll_isv2
+Info: Elaborating entity "altpll_isv2" for hierarchy "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated"
+Warning: Using design file altpll4.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info: Found entity 1: altpll4
+Info: Elaborating entity "altpll4" for hierarchy "altpll4:inst22"
+Info: Elaborating entity "altpll" for hierarchy "altpll4:inst22|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "altpll4:inst22|altpll:altpll_component"
+Info: Instantiated megafunction "altpll4:inst22|altpll:altpll_component" with the following parameter:
+    Info: Parameter "bandwidth_type" = "AUTO"
+    Info: Parameter "clk0_divide_by" = "1"
+    Info: Parameter "clk0_duty_cycle" = "50"
+    Info: Parameter "clk0_multiply_by" = "2"
+    Info: Parameter "clk0_phase_shift" = "0"
+    Info: Parameter "compensate_clock" = "CLK0"
+    Info: Parameter "inclk0_input_frequency" = "20833"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "lpm_type" = "altpll"
+    Info: Parameter "operation_mode" = "NORMAL"
+    Info: Parameter "pll_type" = "AUTO"
+    Info: Parameter "port_activeclock" = "PORT_UNUSED"
+    Info: Parameter "port_areset" = "PORT_USED"
+    Info: Parameter "port_clk0" = "PORT_USED"
+    Info: Parameter "port_clk1" = "PORT_UNUSED"
+    Info: Parameter "port_clk2" = "PORT_UNUSED"
+    Info: Parameter "port_clk3" = "PORT_UNUSED"
+    Info: Parameter "port_clk4" = "PORT_UNUSED"
+    Info: Parameter "port_clk5" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info: Parameter "port_clkena0" = "PORT_UNUSED"
+    Info: Parameter "port_clkena1" = "PORT_UNUSED"
+    Info: Parameter "port_clkena2" = "PORT_UNUSED"
+    Info: Parameter "port_clkena3" = "PORT_UNUSED"
+    Info: Parameter "port_clkena4" = "PORT_UNUSED"
+    Info: Parameter "port_clkena5" = "PORT_UNUSED"
+    Info: Parameter "port_clkloss" = "PORT_UNUSED"
+    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info: Parameter "port_configupdate" = "PORT_USED"
+    Info: Parameter "port_extclk0" = "PORT_UNUSED"
+    Info: Parameter "port_extclk1" = "PORT_UNUSED"
+    Info: Parameter "port_extclk2" = "PORT_UNUSED"
+    Info: Parameter "port_extclk3" = "PORT_UNUSED"
+    Info: Parameter "port_fbin" = "PORT_UNUSED"
+    Info: Parameter "port_inclk0" = "PORT_USED"
+    Info: Parameter "port_inclk1" = "PORT_UNUSED"
+    Info: Parameter "port_locked" = "PORT_USED"
+    Info: Parameter "port_pfdena" = "PORT_UNUSED"
+    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info: Parameter "port_phasedone" = "PORT_UNUSED"
+    Info: Parameter "port_phasestep" = "PORT_UNUSED"
+    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info: Parameter "port_pllena" = "PORT_UNUSED"
+    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info: Parameter "port_scanclk" = "PORT_USED"
+    Info: Parameter "port_scanclkena" = "PORT_USED"
+    Info: Parameter "port_scandata" = "PORT_USED"
+    Info: Parameter "port_scandataout" = "PORT_USED"
+    Info: Parameter "port_scandone" = "PORT_USED"
+    Info: Parameter "port_scanread" = "PORT_UNUSED"
+    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info: Parameter "scan_chain_mif_file" = "altpll4.mif"
+    Info: Parameter "self_reset_on_loss_lock" = "OFF"
+    Info: Parameter "width_clock" = "5"
+    Info: Parameter "width_phasecounterselect" = "4"
+Info: Found 1 design units, including 1 entities, in source file db/altpll_c6j2.tdf
+    Info: Found entity 1: altpll_c6j2
+Info: Elaborating entity "altpll_c6j2" for hierarchy "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated"
+Warning: Using design file altpll_reconfig1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info: Found entity 1: altpll_reconfig1
+Info: Elaborating entity "altpll_reconfig1" for hierarchy "altpll_reconfig1:inst7"
+Warning: Using design file altpll_reconfig1_pllrcfg_t4q.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info: Found entity 1: altpll_reconfig1_pllrcfg_t4q
+Info: Elaborating entity "altpll_reconfig1_pllrcfg_t4q" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component"
+Info: Elaborating entity "altsyncram" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" with the following parameter:
+    Info: Parameter "OPERATION_MODE" = "SINGLE_PORT"
+    Info: Parameter "WIDTH_A" = "1"
+    Info: Parameter "WIDTHAD_A" = "8"
+    Info: Parameter "NUMWORDS_A" = "144"
+    Info: Parameter "WIDTH_BYTEENA_A" = "1"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46r.tdf
+    Info: Found entity 1: altsyncram_46r
+Info: Elaborating entity "altsyncram_46r" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated"
+Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "9"
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_hpa.tdf
+    Info: Found entity 1: add_sub_hpa
+Info: Elaborating entity "add_sub_hpa" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5|add_sub_hpa:auto_generated"
+Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "8"
+Info: Found 1 design units, including 1 entities, in source file db/add_sub_k8a.tdf
+    Info: Found entity 1: add_sub_k8a
+Info: Elaborating entity "add_sub_k8a" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6|add_sub_k8a:auto_generated"
+Info: Elaborating entity "lpm_compare" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" with the following parameter:
+    Info: Parameter "LPM_WIDTH" = "8"
+Info: Found 1 design units, including 1 entities, in source file db/cmpr_tnd.tdf
+    Info: Found entity 1: cmpr_tnd
+Info: Elaborating entity "cmpr_tnd" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated"
+Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" with the following parameter:
+    Info: Parameter "LPM_DIRECTION" = "DOWN"
+    Info: Parameter "lpm_modulus" = "144"
+    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info: Parameter "LPM_WIDTH" = "8"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_30l.tdf
+    Info: Found entity 1: cntr_30l
+Info: Elaborating entity "cntr_30l" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated"
+Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" with the following parameter:
+    Info: Parameter "LPM_DIRECTION" = "DOWN"
+    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info: Parameter "LPM_WIDTH" = "6"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_qij.tdf
+    Info: Found entity 1: cntr_qij
+Info: Elaborating entity "cntr_qij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated"
+Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" with the following parameter:
+    Info: Parameter "LPM_DIRECTION" = "DOWN"
+    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info: Parameter "LPM_WIDTH" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_pij.tdf
+    Info: Found entity 1: cntr_pij
+Info: Elaborating entity "cntr_pij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated"
+Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" with the following parameter:
+    Info: Parameter "LPM_DIRECTION" = "UP"
+    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info: Parameter "LPM_WIDTH" = "8"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_9cj.tdf
+    Info: Found entity 1: cntr_9cj
+Info: Elaborating entity "cntr_9cj" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated"
+Info: Elaborating entity "lpm_decode" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11"
+Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11"
+Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" with the following parameter:
+    Info: Parameter "LPM_DECODES" = "5"
+    Info: Parameter "LPM_WIDTH" = "3"
+Info: Found 1 design units, including 1 entities, in source file db/decode_2af.tdf
+    Info: Found entity 1: decode_2af
+Info: Elaborating entity "decode_2af" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11|decode_2af:auto_generated"
+Info: Elaborating entity "DSP" for hierarchy "DSP:Mathias_Alles"
+Info: Elaborating entity "interrupt_handler" for hierarchy "interrupt_handler:nobody"
+Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst18"
+Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component"
+Info: Elaborated megafunction instantiation "lpm_counter0:inst18|lpm_counter:lpm_counter_component"
+Info: Instantiated megafunction "lpm_counter0:inst18|lpm_counter:lpm_counter_component" with the following parameter:
+    Info: Parameter "lpm_direction" = "UP"
+    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
+    Info: Parameter "lpm_type" = "LPM_COUNTER"
+    Info: Parameter "lpm_width" = "18"
+Info: Found 1 design units, including 1 entities, in source file db/cntr_mph.tdf
+    Info: Found entity 1: cntr_mph
+Info: Elaborating entity "cntr_mph" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated"
+Info: Elaborating entity "altddio_out3" for hierarchy "altddio_out3:inst5"
+Info: Elaborating entity "altddio_out" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component"
+Info: Elaborated megafunction instantiation "altddio_out3:inst5|altddio_out:altddio_out_component"
+Info: Instantiated megafunction "altddio_out3:inst5|altddio_out:altddio_out_component" with the following parameter:
+    Info: Parameter "extend_oe_disable" = "UNUSED"
+    Info: Parameter "intended_device_family" = "Cyclone III"
+    Info: Parameter "invert_output" = "OFF"
+    Info: Parameter "lpm_type" = "altddio_out"
+    Info: Parameter "oe_reg" = "UNUSED"
+    Info: Parameter "power_up_high" = "OFF"
+    Info: Parameter "width" = "1"
+Info: Found 1 design units, including 1 entities, in source file db/ddio_out_31f.tdf
+    Info: Found entity 1: ddio_out_31f
+Info: Elaborating entity "ddio_out_31f" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated"
+Warning: Timing-Driven Synthesis is skipped because the Classic Timing Analyzer is turned on
+Info: Inferred 3 megafunctions from design logic
+    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_14"
+    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_6"
+    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_12"
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" with the following parameter:
+    Info: Parameter "LPM_WIDTHA" = "12"
+    Info: Parameter "LPM_WIDTHB" = "6"
+    Info: Parameter "LPM_WIDTHP" = "18"
+    Info: Parameter "LPM_WIDTHR" = "18"
+    Info: Parameter "LPM_WIDTHS" = "1"
+    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
+    Info: Parameter "MAXIMIZE_SPEED" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/mult_cat.tdf
+    Info: Found entity 1: mult_cat
+Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6"
+Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" with the following parameter:
+    Info: Parameter "LPM_WIDTHA" = "12"
+    Info: Parameter "LPM_WIDTHB" = "5"
+    Info: Parameter "LPM_WIDTHP" = "17"
+    Info: Parameter "LPM_WIDTHR" = "17"
+    Info: Parameter "LPM_WIDTHS" = "1"
+    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
+    Info: Parameter "MAXIMIZE_SPEED" = "5"
+Info: Found 1 design units, including 1 entities, in source file db/mult_aat.tdf
+    Info: Found entity 1: mult_aat
+Warning: The following nodes have both tri-state and non-tri-state drivers
+    Warning: Inserted always-enabled tri-state buffer between "IO[17]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[16]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[15]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[14]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[13]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[12]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[11]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[10]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[9]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[8]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[7]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[6]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[5]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[4]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[3]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[2]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[1]" and its non-tri-state driver.
+    Warning: Inserted always-enabled tri-state buffer between "IO[0]" and its non-tri-state driver.
+Info: Registers with preset signals will power-up high
+Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning: TRI or OPNDRN buffers permanently disabled
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_PAR~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_RST~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[7]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[6]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[5]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[4]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[3]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[2]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[1]~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[0]~synth"
+Warning: TRI or OPNDRN buffers permanently enabled
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "IO~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_SEL~synth"
+    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_BUSY~synth"
+Warning: Output pins are stuck at VCC or GND
+    Warning (13410): Pin "nACSI_ACK" is stuck at VCC
+    Warning (13410): Pin "nACSI_CS" is stuck at VCC
+    Warning (13410): Pin "ACSI_DIR" is stuck at GND
+    Warning (13410): Pin "nSCSI_ACK" is stuck at VCC
+    Warning (13410): Pin "nSCSI_ATN" is stuck at VCC
+    Warning (13410): Pin "SCSI_DIR" is stuck at VCC
+    Warning (13410): Pin "nSYNC" is stuck at GND
+Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[31]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[30]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[29]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[28]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[27]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[26]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[25]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[24]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[23]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[22]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[21]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[20]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[19]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[18]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[17]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[16]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[15]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[14]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[13]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[12]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[11]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[10]" lost all its fanouts during netlist optimizations.
+    Info: Register "interrupt_handler:nobody|INT_CLEAR[7]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[6]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[5]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[4]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[3]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[2]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[1]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[5]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[4]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[3]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[2]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[1]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[7]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[6]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[5]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[4]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[3]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[2]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[1]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[2]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[1]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[7]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]" lost all its fanouts during netlist optimizations.
+    Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" lost all its fanouts during netlist optimizations.
+    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]" lost all its fanouts during netlist optimizations.
+Info: Found the following redundant logic cells in design
+    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[0]"
+    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[1]"
+    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[2]"
+Warning: Design contains 18 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "nFB_BURST"
+    Warning (15610): No output dependent on input pin "nACSI_DRQ"
+    Warning (15610): No output dependent on input pin "nACSI_INT"
+    Warning (15610): No output dependent on input pin "nSCSI_DRQ"
+    Warning (15610): No output dependent on input pin "nSCSI_MSG"
+    Warning (15610): No output dependent on input pin "nDCHG"
+    Warning (15610): No output dependent on input pin "SD_DATA0"
+    Warning (15610): No output dependent on input pin "SD_DATA1"
+    Warning (15610): No output dependent on input pin "SD_DATA2"
+    Warning (15610): No output dependent on input pin "SD_CARD_DEDECT"
+    Warning (15610): No output dependent on input pin "SD_WP"
+    Warning (15610): No output dependent on input pin "nDACK0"
+    Warning (15610): No output dependent on input pin "WP_CF_CARD"
+    Warning (15610): No output dependent on input pin "nSCSI_C_D"
+    Warning (15610): No output dependent on input pin "nSCSI_I_O"
+    Warning (15610): No output dependent on input pin "nFB_CS3"
+    Warning (15610): No output dependent on input pin "TOUT0"
+    Warning (15610): No output dependent on input pin "nMASTER"
+Info: Implemented 11489 device resources after synthesis - the final resource count might be different
+    Info: Implemented 51 input pins
+    Info: Implemented 112 output pins
+    Info: Implemented 132 bidirectional pins
+    Info: Implemented 10796 logic cells
+    Info: Implemented 324 RAM segments
+    Info: Implemented 4 PLLs
+    Info: Implemented 6 DSP elements
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 143 warnings
+    Info: Peak virtual memory: 347 megabytes
+    Info: Processing ended: Wed Dec 15 02:21:56 2010
+    Info: Elapsed time: 00:01:19
+    Info: Total CPU time (on all processors): 00:01:20
+
+
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
new file mode 100644
index 0000000..f8da91e
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010
+Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+Revision Name : firebee1
+Top-level Entity Name : firebee1
+Family : Cyclone III
+Total logic elements : 10,706
+    Total combinational functions : 8,060
+    Dedicated logic registers : 4,612
+Total registers : 4740
+Total pins : 295
+Total virtual pins : 0
+Total memory bits : 109,344
+Embedded Multiplier 9-bit elements : 6
+Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.pin b/FPGA_by_Fredi/firebee1.pin
new file mode 100644
index 0000000..50b8dd7
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.pin
@@ -0,0 +1,557 @@
+ -- Copyright (C) 1991-2010 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		2.5V
+ --					Bank 5:		2.5V
+ --					Bank 6:		3.0V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
+ --           	    either individually through a 10k Ohm resistor to GND or tie all pins
+ --           	    together and connect through a single 10k Ohm resistor to GND.
+ --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+CHIP  "firebee1"  ASSIGNED TO AN: EP3C40F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+LP_D[6]                      : A3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nSRBLE                       : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+SRD[1]                       : A5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[3]                        : A6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[1]                        : A7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[0]                        : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[10]                      : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[9]                       : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DVI_INT                      : A11       : input  : 3.3-V LVTTL       :         : 8         : Y              
+nDACK1                       : A12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+IO[16]                       : A13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+IO[14]                       : A14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+IO[9]                        : A15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+SD_DATA1                     : A16       : input  : 3.3-V LVTTL       :         : 7         : Y              
+YM_QA                        : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+TxD                          : A18       : output : 3.3-V LVTTL       :         : 7         : Y              
+DCD                          : A19       : input  : 3.3-V LVTTL       :         : 7         : Y              
+nRD_DATA                     : A20       : input  : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+nPCI_INTA                    : AA1       : input  : 3.3-V LVTTL       :         : 2         : Y              
+PIC_INT                      : AA2       : input  : 3.3-V LVTTL       :         : 2         : Y              
+FB_AD[2]                     : AA3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[6]                     : AA4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[8]                     : AA5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+FB_AD[15]                    : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[22]                    : AA8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[25]                    : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[31]                    : AA10      : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+VD[18]                       : AA13      : bidir  : 2.5 V             :         : 4         : Y              
+VD[25]                       : AA14      : bidir  : 2.5 V             :         : 4         : Y              
+VDQS[0]                      : AA15      : bidir  : 2.5 V             :         : 4         : Y              
+VDM[0]                       : AA16      : output : 2.5 V             :         : 4         : Y              
+nDDR_CLK                     : AA17      : output : 2.5 V             :         : 4         : Y              
+VA[12]                       : AA18      : output : 2.5 V             :         : 4         : Y              
+BA[1]                        : AA19      : output : 2.5 V             :         : 4         : Y              
+VA[7]                        : AA20      : output : 2.5 V             :         : 4         : Y              
+VA[6]                        : AA21      : output : 2.5 V             :         : 5         : Y              
+VA[4]                        : AA22      : output : 2.5 V             :         : 5         : Y              
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+FB_AD[3]                     : AB3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[7]                     : AB4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[9]                     : AB5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GND                          : AB6       : gnd    :                   :         :           :                
+FB_AD[16]                    : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[23]                    : AB8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[26]                    : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+CLK24M576                    : AB10      : output : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB11      :        :                   :         : 3         :                
+CLK33M                       : AB12      : input  : 3.3-V LVTTL       :         : 4         : Y              
+VD[29]                       : AB13      : bidir  : 2.5 V             :         : 4         : Y              
+VD[26]                       : AB14      : bidir  : 2.5 V             :         : 4         : Y              
+VD[24]                       : AB15      : bidir  : 2.5 V             :         : 4         : Y              
+VD[23]                       : AB16      : bidir  : 2.5 V             :         : 4         : Y              
+DDR_CLK                      : AB17      : output : 2.5 V             :         : 4         : Y              
+nVCAS                        : AB18      : output : 2.5 V             :         : 4         : Y              
+VA[9]                        : AB19      : output : 2.5 V             :         : 4         : Y              
+VA[8]                        : AB20      : output : 2.5 V             :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+ACSI_D[0]                    : B1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+MIDI_TLR                     : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LP_D[5]                      : B3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nSRBHE                       : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+SRD[0]                       : B5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[4]                        : B6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[2]                        : B7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nSRCS                        : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+SRD[8]                       : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[11]                      : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nRSTO_MCF                    : B11       : input  : 3.3-V LVTTL       :         : 8         : Y              
+nDACK0                       : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+IO[17]                       : B13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+IO[15]                       : B14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+IO[10]                       : B15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+SD_DATA0                     : B16       : input  : 3.3-V LVTTL       :         : 7         : Y              
+SD_DATA2                     : B17       : input  : 3.3-V LVTTL       :         : 7         : Y              
+RTS                          : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+RI                           : B19       : input  : 3.3-V LVTTL       :         : 7         : Y              
+nSDSEL                       : B20       : output : 3.3-V LVTTL       :         : 7         : Y              
+VB[5]                        : B21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VB[4]                        : B22       : output : 3.0-V LVTTL       :         : 6         : Y              
+ACSI_D[4]                    : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+ACSI_D[3]                    : C2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+LP_D[2]                      : C3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[1]                      : C4        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+SRD[2]                       : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[7]                        : C7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[6]                        : C8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C9        : gnd    :                   :         :           :                
+SRD[4]                       : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+IO[11]                       : C13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+SD_CLK                       : C15       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C16       : gnd    :                   :         :           :                
+nDCHG                        : C17       : input  : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C18       : gnd    :                   :         :           :                
+TRACK00                      : C19       : input  : 3.3-V LVTTL       :         : 7         : Y              
+VB[6]                        : C20       : output : 3.0-V LVTTL       :         : 6         : Y              
+VB[3]                        : C21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VB[2]                        : C22       : output : 3.0-V LVTTL       :         : 6         : Y              
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+ACSI_D[5]                    : D2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+LP_D[4]                      : D6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8         :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+SRD[12]                      : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+IO[12]                       : D13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+DTR                          : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+nWR_GATE                     : D17       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+nWP                          : D19       : input  : 3.3-V LVTTL       :         : 7         : Y              
+VB[7]                        : D20       : output : 3.0-V LVTTL       :         : 6         : Y              
+VG[7]                        : D21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VG[6]                        : D22       : output : 3.0-V LVTTL       :         : 6         : Y              
+SCSI_D[1]                    : E1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+ACSI_D[2]                    : E3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
+LPDIR                        : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+LP_STR                       : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[3]                      : E7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+IO[5]                        : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[6]                       : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nDREQ1                       : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+MIDI_IN                      : E12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+IO[13]                       : E13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+SD_CMD_D1                    : E14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+YM_QC                        : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+nINDEX                       : E16       : input  : 3.3-V LVTTL       :         : 7         : Y              
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.0V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+VG[2]                        : E21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VG[1]                        : E22       : output : 3.0-V LVTTL       :         : 6         : Y              
+SCSI_D[3]                    : F1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SCSI_D[2]                    : F2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+LP_D[0]                      : F7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nSRWE                        : F8        : output : 3.3-V LVTTL       :         : 8         : Y              
+SRD[5]                       : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[13]                      : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+nSROE                        : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : F12       : gnd    :                   :         :           :                
+SD_CD_DATA3                  : F13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
+nSTEP                        : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+DSA_D                        : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HD_DD                        : F16       : input  : 3.3-V LVTTL       :         : 7         : Y              
+nSYNC                        : F17       : output : 3.0-V LVCMOS      :         : 6         : Y              
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+PIXEL_CLK_PAD                : F19       : output : 3.0-V LVTTL       :         : 6         : Y              
+nIRQ[4]                      : F20       : output : 3.0-V LVCMOS      :         : 6         : Y              
+nIRQ[2]                      : F21       : output : 3.0-V LVCMOS      :         : 6         : Y              
+VR[7]                        : F22       : output : 3.0-V LVTTL       :         : 6         : Y              
+GND+                         : G1        :        :                   :         : 1         :                
+MAIN_CLK                     : G2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SCSI_D[5]                    : G3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SCSI_D[4]                    : G4        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+ACSI_D[1]                    : G5        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+LP_BUSY                      : G7        : input  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[7]                      : G8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[14]                      : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+IO[8]                        : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[3]                       : G11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCINT                       : G12       : power  :                   : 1.2V    :           :                
+YM_QB                        : G13       : output : 3.3-V LVTTL       :         : 7         : Y              
+nWR                          : G14       : output : 3.3-V LVTTL       :         : 7         : Y              
+nSTEP_DIR                    : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+nMOT_ON                      : G16       : output : 3.3-V LVTTL       :         : 7         : Y              
+nBLANK_PAD                   : G17       : output : 3.0-V LVTTL       :         : 6         : Y              
+VB[0]                        : G18       : output : 3.0-V LVTTL       :         : 6         : Y              
+VCCIO6                       : G19       : power  :                   : 3.0V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+E0_INT                       : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+IDE_INT                      : G22       : input  : 3.3-V LVTTL       :         : 6         : Y              
+nSCSI_C_D                    : H1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nSCSI_MSG                    : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+MIDI_OLR                     : H5        : output : 3.3-V LVTTL       :         : 1         : Y              
+ACSI_D[7]                    : H6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+ACSI_D[6]                    : H7        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 1         :                
+VCCINT                       : H9        : power  :                   : 1.2V    :           :                
+SRD[15]                      : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[7]                       : H11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : H12       : gnd    :                   :         :           :                
+GND                          : H13       : gnd    :                   :         :           :                
+CTS                          : H14       : input  : 3.3-V LVTTL       :         : 7         : Y              
+RxD                          : H15       : input  : 3.3-V LVTTL       :         : 7         : Y              
+VG[5]                        : H16       : output : 3.0-V LVTTL       :         : 6         : Y              
+VB[1]                        : H17       : output : 3.0-V LVTTL       :         : 6         : Y              
+VG[3]                        : H18       : output : 3.0-V LVTTL       :         : 6         : Y              
+VG[0]                        : H19       : output : 3.0-V LVTTL       :         : 6         : Y              
+nIRQ[3]                      : H20       : output : 3.0-V LVCMOS      :         : 6         : Y              
+VR[3]                        : H21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VR[2]                        : H22       : output : 3.0-V LVTTL       :         : 6         : Y              
+CLKUSB                       : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
+nSCSI_I_O                    : J3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+nACSI_INT                    : J4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J5        :        :                   :         : 1         :                
+SCSI_D[0]                    : J6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+SCSI_DIR                     : J7        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 1         :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+GND                          : J15       : gnd    :                   :         :           :                
+VCCINT                       : J16       : power  :                   : 1.2V    :           :                
+VG[4]                        : J17       : output : 3.0-V LVTTL       :         : 6         : Y              
+VR[6]                        : J18       : output : 3.0-V LVTTL       :         : 6         : Y              
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.0V    : 6         :                
+VR[1]                        : J21       : output : 3.0-V LVTTL       :         : 6         : Y              
+VR[0]                        : J22       : output : 3.0-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~ / RESERVED_INPUT : K2        : input  : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+nACSI_DRQ                    : K7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SCSI_D[7]                    : K8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+VCCINT                       : K15       : power  :                   : 1.2V    :           :                
+GND                          : K16       : gnd    :                   :         :           :                
+VR[4]                        : K17       : output : 3.0-V LVTTL       :         : 6         : Y              
+VR[5]                        : K18       : output : 3.0-V LVTTL       :         : 6         : Y              
+VSYNC_PAD                    : K19       : output : 3.0-V LVTTL       :         : 6         : Y              
+MSEL3                        : K20       :        :                   :         : 6         :                
+HSYNC_PAD                    : K21       : output : 3.0-V LVTTL       :         : 6         : Y              
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 3.0-V LVTTL       :         : 6         : N              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+ACSI_DIR                     : L6        : output : 3.3-V LVTTL       :         : 2         : Y              
+PIC_AMKB_RX                  : L7        : input  : 3.3-V LVTTL       :         : 2         : Y              
+SCSI_D[6]                    : L8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+GND                          : L15       : gnd    :                   :         :           :                
+VCCINT                       : L16       : power  :                   : 1.2V    :           :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.0V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
+nACSI_RESET                  : M1        : output : 3.3-V LVTTL       :         : 2         : Y              
+nACSI_CS                     : M2        : output : 3.3-V LVTTL       :         : 2         : Y              
+nSCSI_ATN                    : M3        : output : 3.3-V LVTTL       :         : 2         : Y              
+nACSI_ACK                    : M4        : output : 3.3-V LVTTL       :         : 2         : Y              
+IDE_RES                      : M5        : output : 3.3-V LVTTL       :         : 2         : Y              
+ACSI_A1                      : M6        : output : 3.3-V LVTTL       :         : 2         : Y              
+SCSI_PAR                     : M7        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+nSCSI_SEL                    : M8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+VCCINT                       : M15       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+SD_WP                        : M19       : input  : 3.3-V LVTTL       :         : 5         : Y              
+SD_CARD_DEDECT               : M20       : input  : 3.3-V LVTTL       :         : 5         : Y              
+VD[1]                        : M21       : bidir  : 2.5 V             :         : 5         : Y              
+VD[0]                        : M22       : bidir  : 2.5 V             :         : 5         : Y              
+AMKB_TX                      : N1        : output : 3.3-V LVCMOS      :         : 2         : Y              
+nSCSI_ACK                    : N2        : output : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+nRP_LDS                      : N5        : output : 3.3-V LVTTL       :         : 2         : Y              
+nSCSI_RST                    : N6        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+nIRQ[7]                      : N7        : output : 3.3-V LVTTL       :         : 2         : Y              
+nSCSI_BUSY                   : N8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+VCCINT                       : N14       : power  :                   : 1.2V    :           :                
+GND                          : N15       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+VD[12]                       : N17       : bidir  : 2.5 V             :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+LED_FPGA_OK                  : N19       : output : 2.5 V             :         : 5         : Y              
+VD[15]                       : N20       : bidir  : 2.5 V             :         : 5         : Y              
+~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21       : input  : 2.5 V             :         : 5         : N              
+~ALTERA_DEV_OE~ / RESERVED_INPUT : N22       : input  : 2.5 V             :         : 5         : N              
+nIDE_RD                      : P1        : output : 3.3-V LVTTL       :         : 2         : Y              
+nIDE_WR                      : P2        : output : 3.3-V LVTTL       :         : 2         : Y              
+nROM3                        : P3        : output : 3.3-V LVTTL       :         : 2         : Y              
+nRP_UDS                      : P4        : output : 3.3-V LVTTL       :         : 2         : Y              
+nIRQ[5]                      : P5        : output : 3.3-V LVTTL       :         : 2         : Y              
+nPCI_INTD                    : P6        : input  : 3.3-V LVTTL       :         : 2         : Y              
+nIRQ[6]                      : P7        : output : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : P8        : gnd    :                   :         :           :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+VCCINT                       : P14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+VD[10]                       : P17       : bidir  : 2.5 V             :         : 5         : Y              
+VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+VD[13]                       : P20       : bidir  : 2.5 V             :         : 5         : Y              
+VD[4]                        : P21       : bidir  : 2.5 V             :         : 5         : Y              
+VD[2]                        : P22       : bidir  : 2.5 V             :         : 5         : Y              
+nIDE_CS1                     : R1        : output : 3.3-V LVTTL       :         : 2         : Y              
+nIDE_CS0                     : R2        : output : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+TIN0                         : R5        : output : 3.3-V LVTTL       :         : 2         : Y              
+nFB_OE                       : R6        : input  : 3.3-V LVTTL       :         : 2         : Y              
+FB_ALE                       : R7        : input  : 3.3-V LVTTL       :         : 2         : Y              
+VCCINT                       : R8        : power  :                   : 1.2V    :           :                
+GND                          : R9        : gnd    :                   :         :           :                
+VCCINT                       : R10       : power  :                   : 1.2V    :           :                
+GND                          : R11       : gnd    :                   :         :           :                
+VCCINT                       : R12       : power  :                   : 1.2V    :           :                
+GND                          : R13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+VD[5]                        : R17       : bidir  : 2.5 V             :         : 5         : Y              
+VD[9]                        : R18       : bidir  : 2.5 V             :         : 5         : Y              
+VD[6]                        : R19       : bidir  : 2.5 V             :         : 5         : Y              
+VD[3]                        : R20       : bidir  : 2.5 V             :         : 5         : Y              
+VD[11]                       : R21       : bidir  : 2.5 V             :         : 5         : Y              
+VD[14]                       : R22       : bidir  : 2.5 V             :         : 5         : Y              
+WP_CF_CARD                   : T1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+GND+                         : T2        :        :                   :         : 2         :                
+nFB_BURST                    : T3        : input  : 3.3-V LVTTL       :         : 2         : Y              
+CLK25M                       : T4        : output : 3.3-V LVTTL       :         : 2         : Y              
+nFB_WR                       : T5        : input  : 3.3-V LVTTL       :         : 2         : Y              
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+nFB_TA                       : T7        : output : 3.3-V LVTTL       :         : 2         : Y              
+nFB_CS1                      : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
+nFB_CS2                      : T9        : input  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[20]                    : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[24]                    : T11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VD[16]                       : T12       : bidir  : 2.5 V             :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+VDQS[3]                      : T16       : bidir  : 2.5 V             :         : 4         : Y              
+VDM[3]                       : T17       : output : 2.5 V             :         : 5         : Y              
+nVCS                         : T18       : output : 2.5 V             :         : 5         : Y              
+VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+nMASTER                      : T21       : input  : 3.3-V LVTTL       :         : 5         : Y              
+TOUT0                        : T22       : input  : 3.3-V LVTTL       :         : 5         : Y              
+nSCSI_DRQ                    : U1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+nROM4                        : U2        : output : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+FB_SIZE0                     : U8        : input  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[12]                    : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[21]                    : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[27]                    : U11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VD[31]                       : U12       : bidir  : 2.5 V             :         : 4         : Y              
+VD[20]                       : U13       : bidir  : 2.5 V             :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+VCKE                         : U15       : output : 2.5 V             :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4         :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+VA[11]                       : U19       : output : 2.5 V             :         : 5         : Y              
+VDM[2]                       : U20       : output : 2.5 V             :         : 5         : Y              
+VD[7]                        : U21       : bidir  : 2.5 V             :         : 5         : Y              
+VDQS[2]                      : U22       : bidir  : 2.5 V             :         : 5         : Y              
+nPD_VGA                      : V1        : output : 3.3-V LVTTL       :         : 2         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+nPCI_INTC                    : V3        : input  : 3.3-V LVTTL       :         : 2         : Y              
+nPCI_INTB                    : V4        : input  : 3.3-V LVTTL       :         : 2         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+nFB_CS3                      : V6        : input  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[5]                     : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[13]                    : V8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[18]                    : V9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[19]                    : V10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[28]                    : V11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VD[30]                       : V12       : bidir  : 2.5 V             :         : 4         : Y              
+VD[27]                       : V13       : bidir  : 2.5 V             :         : 4         : Y              
+VD[19]                       : V14       : bidir  : 2.5 V             :         : 4         : Y              
+VD[21]                       : V15       : bidir  : 2.5 V             :         : 4         : Y              
+VDM[1]                       : V16       : output : 2.5 V             :         : 4         : Y              
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+VA[10]                       : V21       : output : 2.5 V             :         : 5         : Y              
+VD[8]                        : V22       : bidir  : 2.5 V             :         : 5         : Y              
+nCF_CS1                      : W1        : output : 3.3-V LVTTL       :         : 2         : Y              
+nCF_CS0                      : W2        : output : 3.3-V LVTTL       :         : 2         : Y              
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+FB_AD[4]                     : W6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[10]                    : W7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[14]                    : W8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+FB_AD[29]                    : W10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+VD[28]                       : W13       : bidir  : 2.5 V             :         : 4         : Y              
+VD[22]                       : W14       : bidir  : 2.5 V             :         : 4         : Y              
+VDQS[1]                      : W15       : bidir  : 2.5 V             :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+nVRAS                        : W17       : output : 2.5 V             :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+BA[0]                        : W19       : output : 2.5 V             :         : 5         : Y              
+VA[0]                        : W20       : output : 2.5 V             :         : 5         : Y              
+VA[2]                        : W21       : output : 2.5 V             :         : 5         : Y              
+VA[1]                        : W22       : output : 2.5 V             :         : 5         : Y              
+IDE_RDY                      : Y1        : input  : 3.3-V LVTTL       :         : 2         : Y              
+AMKB_RX                      : Y2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+FB_AD[0]                     : Y3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_SIZE1                     : Y4        : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND                          : Y5        : gnd    :                   :         :           :                
+FB_AD[1]                     : Y6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[11]                    : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+FB_AD[17]                    : Y8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GND                          : Y9        : gnd    :                   :         :           :                
+FB_AD[30]                    : Y10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+VD[17]                       : Y13       : bidir  : 2.5 V             :         : 4         : Y              
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+nVWE                         : Y17       : output : 2.5 V             :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+VA[5]                        : Y21       : output : 2.5 V             :         : 5         : Y              
+VA[3]                        : Y22       : output : 2.5 V             :         : 5         : Y              
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
new file mode 100644
index 0000000..86e8842
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -0,0 +1,740 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 12:45:00  November 06, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		firebee1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
+set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name BDF_FILE Video/Video.bdf
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name BDF_FILE firebee1.bdf
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
+set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd"
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_AB12 -to CLK33M
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_E12 -to MIDI_IN
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY firebee1
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+
+# start EDA_TOOL_SETTINGS(eda_blast_fpga)
+# ---------------------------------------
+
+	# Analysis & Synthesis Assignments
+	# ================================
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+
+# end EDA_TOOL_SETTINGS(eda_blast_fpga)
+# -------------------------------------
+
+# start CLOCK(fast)
+# -----------------
+
+	# Classic Timing Assignments
+	# ==========================
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+
+# end CLOCK(fast)
+# ---------------
+
+# start ASSIGNMENT_GROUP(fast)
+# ----------------------------
+
+	# Assignment Group Assignments
+	# ============================
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
+
+# end ASSIGNMENT_GROUP(fast)
+# --------------------------
+
+# ----------------------
+# start ENTITY(firebee1)
+
+	# Classic Timing Assignments
+	# ==========================
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+
+	# Fitter Assignments
+	# ==================
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+
+	# Simulator Assignments
+	# =====================
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+
+	# start LOGICLOCK_REGION(Root Region)
+	# -----------------------------------
+
+		# LogicLock Region Assignments
+		# ============================
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+	# end LOGICLOCK_REGION(Root Region)
+	# ---------------------------------
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(firebee1)
+# --------------------
+set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
+set_global_assignment -name QIP_FILE altpll_reconfig1.qip
+set_global_assignment -name QIP_FILE altpll4.qip
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.qws b/FPGA_by_Fredi/firebee1.qws
new file mode 100644
index 0000000..ed1a121
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.qws
@@ -0,0 +1,4 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
diff --git a/FPGA_by_Fredi/firebee1.rbf b/FPGA_by_Fredi/firebee1.rbf
new file mode 100644
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zhN9U@DcdFV4{lGS(0Yt+wYONJaPeU=n=e0q@l^>DUVEYs!Erd6Ek>B$KL5_qd9epH
z-i~C(G$+rA_!4>@#x!?pIPZT4Go?dWF2S@bGLS2bX*(*s;QblFbQY<N=|r%aJnt7j
z1t-*(J~<nKOL@Pp*fH%VJTs=Pt7e#Ul43v=mlw3t;z&I44kgriBx3(NnEDYTQP%=0
z2pTRdK8Thhe<YrI*q}m;Ksj9j<&wiJ&3RBflt4Xf<X*goLI~U41{rc6g>BSZ?@gnD
z%Vq+yRnuBsv7nh2W0bKNrEsF4hq<qG85FR%K%vDcTj(lUh$tnmoxkV)3I+9zZgOMx
f#5>Fa5jub%>KX-2m$Qk6HbwQ=PDAatKK1_r&C)gu

literal 0
HcmV?d00001

diff --git a/FPGA_by_Fredi/firebee1.tan.rpt b/FPGA_by_Fredi/firebee1.tan.rpt
new file mode 100644
index 0000000..b84e104
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.tan.rpt
@@ -0,0 +1,6936 @@
+Classic Timing Analyzer report for firebee1
+Wed Dec 15 02:25:22 2010
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Timing Analyzer Summary
+  3. Timing Analyzer Settings
+  4. Clock Settings Summary
+  5. Parallel Compilation
+  6. Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+  7. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+  8. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+  9. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+ 10. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+ 11. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+ 12. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+ 13. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+ 14. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+ 15. Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+ 16. Clock Setup: 'CLK33M'
+ 17. Clock Setup: 'MAIN_CLK'
+ 18. Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+ 19. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+ 20. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+ 21. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+ 22. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+ 23. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+ 24. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+ 25. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+ 26. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+ 27. Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+ 28. Clock Hold: 'CLK33M'
+ 29. Clock Hold: 'MAIN_CLK'
+ 30. tsu
+ 31. tco
+ 32. tpd
+ 33. th
+ 34. Board Trace Model Assignments
+ 35. Input Transition Times
+ 36. Slow Corner Signal Integrity Metrics
+ 37. Fast Corner Signal Integrity Metrics
+ 38. Ignored Timing Assignments
+ 39. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
+; Type                                                                                    ; Slack       ; Required Time                     ; Actual Time                                    ; From                                                                                                                                                                     ; To                                                                                                                                                                                            ; From Clock                                                               ; To Clock                                                                 ; Failed Paths ;
++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
+; Worst-case tsu                                                                          ; -4.528 ns   ; 1.000 ns                          ; 5.528 ns                                       ; MAIN_CLK                                                                                                                                                                 ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                                                         ; --                                                                       ; MAIN_CLK                                                                 ; 6867         ;
+; Worst-case tco                                                                          ; -14.840 ns  ; 1.000 ns                          ; 15.840 ns                                      ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                                                    ; nIRQ[5]                                                                                                                                                                                       ; MAIN_CLK                                                                 ; --                                                                       ; 4976         ;
+; Worst-case tpd                                                                          ; -11.944 ns  ; 1.000 ns                          ; 12.944 ns                                      ; nFB_CS1                                                                                                                                                                  ; FB_AD[18]                                                                                                                                                                                     ; --                                                                       ; --                                                                       ; 514          ;
+; Worst-case th                                                                           ; -0.401 ns   ; 1.000 ns                          ; 1.401 ns                                       ; FB_AD[25]                                                                                                                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                                                                 ; --                                                                       ; MAIN_CLK                                                                 ; 117          ;
+; Clock Setup: 'CLK33M'                                                                   ; -5.966 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M                                                                   ; 3741         ;
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -4.615 ns   ; 24.98 MHz ( period = 40.033 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 3741         ;
+; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -4.294 ns   ; 95.92 MHz ( period = 10.425 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 3741         ;
+; Clock Setup: 'MAIN_CLK'                                                                 ; -4.261 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK                                                                 ; 27347        ;
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -2.673 ns   ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 86           ;
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -1.712 ns   ; 66.00 MHz ( period = 15.151 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 29           ;
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 1.672 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]                                                                                                    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0            ;
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 2.965 ns    ; 132.01 MHz ( period = 7.575 ns )  ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]                                          ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]                                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0            ;
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 5.299 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]                                                                                                                        ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0            ;
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 28.590 ns   ; 15.99 MHz ( period = 62.552 ns )  ; 186.15 MHz ( period = 5.372 ns )               ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0            ;
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 498.663 ns  ; 2.00 MHz ( period = 500.416 ns )  ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0            ;
+; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'   ; 1997.239 ns ; 0.50 MHz ( period = 1999.998 ns ) ; 362.45 MHz ( period = 2.759 ns )               ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]                                                                         ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]                                                                                             ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; 0            ;
+; Clock Hold: 'MAIN_CLK'                                                                  ; -3.786 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                                            ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                                                 ; MAIN_CLK                                                                 ; MAIN_CLK                                                                 ; 108          ;
+; Clock Hold: 'CLK33M'                                                                    ; -0.687 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; CLK33M                                                                   ; CLK33M                                                                   ; 26           ;
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'  ; -0.454 ns   ; 24.98 MHz ( period = 40.033 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 26           ;
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'  ; 0.502 ns    ; 15.99 MHz ( period = 62.552 ns )  ; N/A                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0            ;
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'  ; 0.502 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                                     ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0            ;
+; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'  ; 0.502 ns    ; 95.92 MHz ( period = 10.425 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0            ;
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'  ; 0.564 ns    ; 2.00 MHz ( period = 500.416 ns )  ; N/A                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0            ;
+; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'    ; 0.825 ns    ; 0.50 MHz ( period = 1999.998 ns ) ; N/A                                            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]                                                                        ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]                                                                                             ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; 0            ;
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'  ; 1.825 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                                        ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0            ;
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'  ; 2.664 ns    ; 66.00 MHz ( period = 15.151 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0            ;
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'  ; 3.263 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                                   ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0            ;
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'  ; 4.336 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]                                          ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]                                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0            ;
+; Total number of failed paths                                                            ;             ;                                   ;                                                ;                                                                                                                                                                          ;                                                                                                                                                                                               ;                                                                          ;                                                                          ; 51319        ;
++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings                                                                                                                                                              ;
++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
+; Option                                                                                               ; Setting            ; From            ; To                        ; Entity Name ;
++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
+; Device Name                                                                                          ; EP3C40F484C6       ;                 ;                           ;             ;
+; Timing Models                                                                                        ; Final              ;                 ;                           ;             ;
+; Default hold multicycle                                                                              ; Same as Multicycle ;                 ;                           ;             ;
+; Cut paths between unrelated clock domains                                                            ; On                 ;                 ;                           ;             ;
+; Cut off read during write signal paths                                                               ; On                 ;                 ;                           ;             ;
+; Cut off feedback from I/O pins                                                                       ; On                 ;                 ;                           ;             ;
+; Report Combined Fast/Slow Timing                                                                     ; Off                ;                 ;                           ;             ;
+; tpd Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
+; th Requirement                                                                                       ; 1 ns               ;                 ;                           ;             ;
+; tsu Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
+; tco Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
+; fmax Requirement                                                                                     ; 30 ns              ;                 ;                           ;             ;
+; Ignore Clock Settings                                                                                ; Off                ;                 ;                           ;             ;
+; Analyze latches as synchronous elements                                                              ; On                 ;                 ;                           ;             ;
+; Enable Recovery/Removal analysis                                                                     ; Off                ;                 ;                           ;             ;
+; Enable Clock Latency                                                                                 ; Off                ;                 ;                           ;             ;
+; Use TimeQuest Timing Analyzer                                                                        ; Off                ;                 ;                           ;             ;
+; Nominal Core Supply Voltage                                                                          ; 1.2V               ;                 ;                           ;             ;
+; Minimum Core Junction Temperature                                                                    ; 0                  ;                 ;                           ;             ;
+; Maximum Core Junction Temperature                                                                    ; 85                 ;                 ;                           ;             ;
+; Number of source nodes to report per destination node                                                ; 10                 ;                 ;                           ;             ;
+; Number of destination nodes to report                                                                ; 10                 ;                 ;                           ;             ;
+; Number of paths to report                                                                            ; 200                ;                 ;                           ;             ;
+; Report Minimum Timing Checks                                                                         ; Off                ;                 ;                           ;             ;
+; Use Fast Timing Models                                                                               ; Off                ;                 ;                           ;             ;
+; Report IO Paths Separately                                                                           ; Off                ;                 ;                           ;             ;
+; Perform Multicorner Analysis                                                                         ; On                 ;                 ;                           ;             ;
+; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;                 ;                           ;             ;
+; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;                 ;                           ;             ;
+; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;                 ;                           ;             ;
+; Removes common clock path pessimism (CCPP) during slack computation                                  ; On                 ;                 ;                           ;             ;
+; Output I/O Timing Endpoint                                                                           ; Near End           ;                 ;                           ;             ;
+; Cut Timing Path                                                                                      ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_0hh1 ;
+; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe17|dffe18a ; dcfifo_0hh1 ;
+; Cut Timing Path                                                                                      ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_3fh1 ;
+; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe15|dffe16a ; dcfifo_3fh1 ;
+; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe22|dffe23a ; dcfifo_8fi1 ;
+; Input Maximum Delay                                                                                  ; 4 ns               ; *               ; FB_ALE                    ;             ;
+; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; BA                        ;             ;
+; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; VA                        ;             ;
+; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; nVRAS                     ;             ;
++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary                                                                                                                                                                                                                           ;
++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; Clock Node Name                                                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ;                    ; PLL output ; 0.5 MHz          ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 1                     ; 66                  ; -9.578 ns ;              ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]   ;                    ; PLL output ; 2.46 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 67                    ; 900                 ; -9.578 ns ;              ;
+; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]   ;                    ; PLL output ; 24.57 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 67                    ; 90                  ; -9.578 ns ;              ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ;                    ; PLL output ; 2.0 MHz          ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 1800                ; -1.864 ns ;              ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ;                    ; PLL output ; 15.99 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 225                 ; -1.864 ns ;              ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ;                    ; PLL output ; 24.98 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 144                 ; -1.864 ns ;              ;
+; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ;                    ; PLL output ; 47.96 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 75                  ; -1.864 ns ;              ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; -3.620 ns ;              ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; -1.094 ns ;              ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; 2.693 ns  ;              ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; 1.115 ns  ;              ;
+; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ;                    ; PLL output ; 66.0 MHz         ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 2                     ; 1                   ; -4.884 ns ;              ;
+; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ;                    ; PLL output ; 95.92 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 218                   ; 75                  ; -2.843 ns ;              ;
+; CLK33M                                                                   ;                    ; User Pin   ; 33.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+; MAIN_CLK                                                                 ;                    ; User Pin   ; 33.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+
+
+Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
++-------------------------------------+
+; Parallel Compilation                ;
++----------------------------+--------+
+; Processors                 ; Number ;
++----------------------------+--------+
+; Number detected on machine ; 4      ;
+; Maximum allowed            ; 1      ;
++----------------------------+--------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack       ; Actual fmax (period)                        ; From                                                                                              ; To                                                                                                ; From Clock                                                             ; To Clock                                                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 1997.239 ns ; 362.45 MHz ( period = 2.759 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.574 ns                ;
+; 1997.297 ns ; 370.23 MHz ( period = 2.701 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.516 ns                ;
+; 1997.355 ns ; 378.36 MHz ( period = 2.643 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.458 ns                ;
+; 1997.413 ns ; 386.85 MHz ( period = 2.585 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.400 ns                ;
+; 1997.476 ns ; 396.51 MHz ( period = 2.522 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.337 ns                ;
+; 1997.531 ns ; 405.35 MHz ( period = 2.467 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.282 ns                ;
+; 1997.593 ns ; 415.80 MHz ( period = 2.405 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.220 ns                ;
+; 1997.626 ns ; 421.59 MHz ( period = 2.372 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.187 ns                ;
+; 1997.647 ns ; 425.35 MHz ( period = 2.351 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.166 ns                ;
+; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.129 ns                ;
+; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.129 ns                ;
+; 1997.709 ns ; 436.87 MHz ( period = 2.289 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.104 ns                ;
+; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
+; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
+; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
+; 1997.765 ns ; 447.83 MHz ( period = 2.233 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 2.049 ns                ;
+; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
+; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
+; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
+; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
+; 1997.822 ns ; 459.56 MHz ( period = 2.176 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.992 ns                ;
+; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
+; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
+; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
+; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
+; 1997.863 ns ; 468.38 MHz ( period = 2.135 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.950 ns                ;
+; 1997.880 ns ; 472.14 MHz ( period = 2.118 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.934 ns                ;
+; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
+; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
+; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
+; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
+; 1997.918 ns ; 480.77 MHz ( period = 2.080 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.895 ns                ;
+; 1997.921 ns ; 481.46 MHz ( period = 2.077 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.892 ns                ;
+; 1997.941 ns ; 486.14 MHz ( period = 2.057 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.873 ns                ;
+; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
+; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
+; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
+; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
+; 1997.976 ns ; 494.56 MHz ( period = 2.022 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.837 ns                ;
+; 1997.979 ns ; 495.29 MHz ( period = 2.019 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.834 ns                ;
+; 1997.980 ns ; 495.54 MHz ( period = 2.018 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.833 ns                ;
+; 1997.995 ns ; 499.25 MHz ( period = 2.003 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.819 ns                ;
+; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
+; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
+; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
+; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
+; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.779 ns                ;
+; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.779 ns                ;
+; 1998.037 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.776 ns                ;
+; 1998.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.775 ns                ;
+; 1998.055 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.759 ns                ;
+; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
+; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
+; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
+; 1998.091 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.723 ns                ;
+; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.721 ns                ;
+; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.721 ns                ;
+; 1998.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.718 ns                ;
+; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.717 ns                ;
+; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.717 ns                ;
+; 1998.113 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.701 ns                ;
+; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.665 ns                ;
+; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.665 ns                ;
+; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.665 ns                ;
+; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.665 ns                ;
+; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.663 ns                ;
+; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.663 ns                ;
+; 1998.152 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.662 ns                ;
+; 1998.153 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.660 ns                ;
+; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.659 ns                ;
+; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.659 ns                ;
+; 1998.167 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.647 ns                ;
+; 1998.206 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.607 ns                ;
+; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
+; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
+; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
+; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.605 ns                ;
+; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.605 ns                ;
+; 1998.209 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.605 ns                ;
+; 1998.210 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.604 ns                ;
+; 1998.211 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.602 ns                ;
+; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.601 ns                ;
+; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.601 ns                ;
+; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
+; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
+; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
+; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
+; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.547 ns                ;
+; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.547 ns                ;
+; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.547 ns                ;
+; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.547 ns                ;
+; 1998.268 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.546 ns                ;
+; 1998.269 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.544 ns                ;
+; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.543 ns                ;
+; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.543 ns                ;
+; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
+; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
+; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
+; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
+; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.489 ns                ;
+; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.489 ns                ;
+; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.489 ns                ;
+; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.489 ns                ;
+; 1998.326 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.488 ns                ;
+; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.486 ns                ;
+; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.485 ns                ;
+; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.485 ns                ;
+; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.486 ns                ;
+; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
+; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
+; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
+; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
+; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.432 ns                ;
+; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.431 ns                ;
+; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
+; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
+; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
+; 1998.384 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.430 ns                ;
+; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.428 ns                ;
+; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.427 ns                ;
+; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.427 ns                ;
+; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.428 ns                ;
+; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
+; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
+; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
+; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
+; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.374 ns                ;
+; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.373 ns                ;
+; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
+; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
+; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
+; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.372 ns                ;
+; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.372 ns                ;
+; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.370 ns                ;
+; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.369 ns                ;
+; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.370 ns                ;
+; 1998.445 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.369 ns                ;
+; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
+; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
+; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
+; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
+; 1998.498 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.316 ns                ;
+; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
+; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
+; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
+; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
+; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
+; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
+; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
+; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.312 ns                ;
+; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.311 ns                ;
+; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.312 ns                ;
+; 1998.503 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.311 ns                ;
+; 1998.671 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.143 ns                ;
+; 1999.023 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.791 ns                ;
+; 1999.024 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.790 ns                ;
+; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.789 ns                ;
+; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.789 ns                ;
+; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
+; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
+; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
+; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
+; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
+; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
+; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
+; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
+; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.786 ns                ;
+; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.786 ns                ;
+; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.785 ns                ;
+; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.785 ns                ;
+; 1999.031 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.783 ns                ;
++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                    ;
++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack      ; Actual fmax (period)                        ; From                                                                      ; To                                                                        ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
+; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
+; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
+; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
+; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
+; 498.729 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.503 ns                ;
+; 498.743 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.489 ns                ;
+; 498.787 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.445 ns                ;
+; 498.800 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.432 ns                ;
+; 498.801 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.431 ns                ;
+; 498.858 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.374 ns                ;
+; 498.859 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.373 ns                ;
+; 498.894 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.338 ns                ;
+; 498.916 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.316 ns                ;
+; 498.917 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.315 ns                ;
+; 499.319 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.913 ns                ;
+; 499.422 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.810 ns                ;
+; 499.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.788 ns                ;
+; 499.449 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.783 ns                ;
++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                ; To                                                                                                                                                                                                              ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 28.590 ns                               ; 186.15 MHz ( period = 5.372 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns                   ; 31.135 ns                 ; 2.545 ns                ;
+; 28.759 ns                               ; 198.65 MHz ( period = 5.034 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns                   ; 31.135 ns                 ; 2.376 ns                ;
+; 54.429 ns                               ; 123.11 MHz ( period = 8.123 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.941 ns                ;
+; 54.452 ns                               ; 123.46 MHz ( period = 8.100 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.920 ns                ;
+; 54.563 ns                               ; 125.17 MHz ( period = 7.989 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.803 ns                ;
+; 54.586 ns                               ; 125.53 MHz ( period = 7.966 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.782 ns                ;
+; 54.600 ns                               ; 125.75 MHz ( period = 7.952 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.766 ns                ;
+; 54.623 ns                               ; 126.12 MHz ( period = 7.929 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.745 ns                ;
+; 54.812 ns                               ; 129.20 MHz ( period = 7.740 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.551 ns                ;
+; 54.822 ns                               ; 129.37 MHz ( period = 7.730 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.550 ns                ;
+; 54.835 ns                               ; 129.58 MHz ( period = 7.717 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.530 ns                ;
+; 54.845 ns                               ; 129.75 MHz ( period = 7.707 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.374 ns                 ; 7.529 ns                ;
+; 54.868 ns                               ; 130.14 MHz ( period = 7.684 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.491 ns                ;
+; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.474 ns                ;
+; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
+; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
+; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
+; 54.910 ns                               ; 130.86 MHz ( period = 7.642 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.456 ns                ;
+; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.453 ns                ;
+; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
+; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
+; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
+; 54.933 ns                               ; 131.25 MHz ( period = 7.619 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.435 ns                ;
+; 54.944 ns                               ; 131.44 MHz ( period = 7.608 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.417 ns                ;
+; 54.947 ns                               ; 131.49 MHz ( period = 7.605 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.414 ns                ;
+; 54.948 ns                               ; 131.51 MHz ( period = 7.604 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.413 ns                ;
+; 54.948 ns                               ; 131.51 MHz ( period = 7.604 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.413 ns                ;
+; 54.967 ns                               ; 131.84 MHz ( period = 7.585 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.396 ns                ;
+; 54.970 ns                               ; 131.89 MHz ( period = 7.582 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.393 ns                ;
+; 54.971 ns                               ; 131.91 MHz ( period = 7.581 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.392 ns                ;
+; 54.971 ns                               ; 131.91 MHz ( period = 7.581 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.392 ns                ;
+; 54.979 ns                               ; 132.05 MHz ( period = 7.573 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.382 ns                ;
+; 54.981 ns                               ; 132.08 MHz ( period = 7.571 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.387 ns                ;
+; 54.996 ns                               ; 132.35 MHz ( period = 7.556 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.374 ns                ;
+; 55.002 ns                               ; 132.45 MHz ( period = 7.550 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.361 ns                ;
+; 55.002 ns                               ; 132.45 MHz ( period = 7.550 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.353 ns                ;
+; 55.010 ns                               ; 132.59 MHz ( period = 7.542 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.362 ns                ;
+; 55.035 ns                               ; 133.03 MHz ( period = 7.517 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.326 ns                ;
+; 55.039 ns                               ; 133.10 MHz ( period = 7.513 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.316 ns                ;
+; 55.047 ns                               ; 133.24 MHz ( period = 7.505 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.312 ns                ;
+; 55.078 ns                               ; 133.80 MHz ( period = 7.474 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.291 ns                ;
+; 55.090 ns                               ; 134.01 MHz ( period = 7.462 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.270 ns                ;
+; 55.094 ns                               ; 134.08 MHz ( period = 7.458 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.266 ns                ;
+; 55.101 ns                               ; 134.21 MHz ( period = 7.451 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.371 ns                 ; 7.270 ns                ;
+; 55.102 ns                               ; 134.23 MHz ( period = 7.450 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.259 ns                ;
+; 55.104 ns                               ; 134.26 MHz ( period = 7.448 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.257 ns                ;
+; 55.113 ns                               ; 134.43 MHz ( period = 7.439 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.249 ns                ;
+; 55.113 ns                               ; 134.43 MHz ( period = 7.439 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.248 ns                ;
+; 55.115 ns                               ; 134.46 MHz ( period = 7.437 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.249 ns                ;
+; 55.117 ns                               ; 134.50 MHz ( period = 7.435 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.245 ns                ;
+; 55.125 ns                               ; 134.64 MHz ( period = 7.427 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.238 ns                ;
+; 55.127 ns                               ; 134.68 MHz ( period = 7.425 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.236 ns                ;
+; 55.127 ns                               ; 134.68 MHz ( period = 7.425 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.243 ns                ;
+; 55.130 ns                               ; 134.73 MHz ( period = 7.422 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.236 ns                ;
+; 55.136 ns                               ; 134.84 MHz ( period = 7.416 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.227 ns                ;
+; 55.140 ns                               ; 134.92 MHz ( period = 7.412 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.232 ns                ;
+; 55.144 ns                               ; 134.99 MHz ( period = 7.408 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.224 ns                ;
+; 55.152 ns                               ; 135.14 MHz ( period = 7.400 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.212 ns                ;
+; 55.152 ns                               ; 135.14 MHz ( period = 7.400 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.218 ns                ;
+; 55.161 ns                               ; 135.30 MHz ( period = 7.391 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.208 ns                ;
+; 55.167 ns                               ; 135.41 MHz ( period = 7.385 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.199 ns                ;
+; 55.169 ns                               ; 135.45 MHz ( period = 7.383 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.357 ns                 ; 7.188 ns                ;
+; 55.181 ns                               ; 135.67 MHz ( period = 7.371 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.174 ns                ;
+; 55.181 ns                               ; 135.67 MHz ( period = 7.371 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.187 ns                ;
+; 55.190 ns                               ; 135.83 MHz ( period = 7.362 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.169 ns                ;
+; 55.204 ns                               ; 136.09 MHz ( period = 7.348 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.166 ns                ;
+; 55.206 ns                               ; 136.13 MHz ( period = 7.346 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.357 ns                 ; 7.151 ns                ;
+; 55.218 ns                               ; 136.35 MHz ( period = 7.334 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.137 ns                ;
+; 55.227 ns                               ; 136.52 MHz ( period = 7.325 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.145 ns                ;
+; 55.251 ns                               ; 136.97 MHz ( period = 7.301 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 7.101 ns                ;
+; 55.261 ns                               ; 137.16 MHz ( period = 7.291 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.105 ns                ;
+; 55.261 ns                               ; 137.16 MHz ( period = 7.291 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.100 ns                ;
+; 55.272 ns                               ; 137.36 MHz ( period = 7.280 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.097 ns                ;
+; 55.274 ns                               ; 137.40 MHz ( period = 7.278 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.094 ns                ;
+; 55.278 ns                               ; 137.48 MHz ( period = 7.274 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[2]    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.274 ns                 ; 6.996 ns                ;
+; 55.286 ns                               ; 137.63 MHz ( period = 7.266 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.080 ns                ;
+; 55.288 ns                               ; 137.67 MHz ( period = 7.264 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.084 ns                ;
+; 55.294 ns                               ; 137.78 MHz ( period = 7.258 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.076 ns                ;
+; 55.295 ns                               ; 137.80 MHz ( period = 7.257 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.070 ns                ;
+; 55.298 ns                               ; 137.85 MHz ( period = 7.254 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.068 ns                ;
+; 55.299 ns                               ; 137.87 MHz ( period = 7.253 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.065 ns                ;
+; 55.300 ns                               ; 137.89 MHz ( period = 7.252 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.068 ns                ;
+; 55.303 ns                               ; 137.95 MHz ( period = 7.249 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.061 ns                ;
+; 55.311 ns                               ; 138.10 MHz ( period = 7.241 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.057 ns                ;
+; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.045 ns                ;
+; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.045 ns                ;
+; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.052 ns                ;
+; 55.317 ns                               ; 138.22 MHz ( period = 7.235 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.044 ns                ;
+; 55.319 ns                               ; 138.26 MHz ( period = 7.233 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.042 ns                ;
+; 55.322 ns                               ; 138.31 MHz ( period = 7.230 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.044 ns                ;
+; 55.323 ns                               ; 138.33 MHz ( period = 7.229 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.043 ns                ;
+; 55.323 ns                               ; 138.33 MHz ( period = 7.229 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.047 ns                ;
+; 55.324 ns                               ; 138.35 MHz ( period = 7.228 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.031 ns                ;
+; 55.326 ns                               ; 138.39 MHz ( period = 7.226 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.040 ns                ;
+; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 7.024 ns                ;
+; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
+; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
+; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
+; 55.331 ns                               ; 138.48 MHz ( period = 7.221 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.032 ns                ;
+; 55.331 ns                               ; 138.48 MHz ( period = 7.221 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.029 ns                ;
+; 55.332 ns                               ; 138.50 MHz ( period = 7.220 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.028 ns                ;
+; 55.332 ns                               ; 138.50 MHz ( period = 7.220 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.033 ns                ;
+; 55.333 ns                               ; 138.52 MHz ( period = 7.219 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.027 ns                ;
+; 55.333 ns                               ; 138.52 MHz ( period = 7.219 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.027 ns                ;
+; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.024 ns                ;
+; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.024 ns                ;
+; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.031 ns                ;
+; 55.340 ns                               ; 138.66 MHz ( period = 7.212 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.023 ns                ;
+; 55.341 ns                               ; 138.68 MHz ( period = 7.211 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.019 ns                ;
+; 55.342 ns                               ; 138.70 MHz ( period = 7.210 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.021 ns                ;
+; 55.344 ns                               ; 138.73 MHz ( period = 7.208 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.016 ns                ;
+; 55.344 ns                               ; 138.73 MHz ( period = 7.208 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.022 ns                ;
+; 55.349 ns                               ; 138.83 MHz ( period = 7.203 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.006 ns                ;
+; 55.354 ns                               ; 138.93 MHz ( period = 7.198 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.011 ns                ;
+; 55.354 ns                               ; 138.93 MHz ( period = 7.198 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.008 ns                ;
+; 55.355 ns                               ; 138.95 MHz ( period = 7.197 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.007 ns                ;
+; 55.356 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.006 ns                ;
+; 55.356 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.006 ns                ;
+; 55.361 ns                               ; 139.06 MHz ( period = 7.191 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 6.994 ns                ;
+; 55.364 ns                               ; 139.12 MHz ( period = 7.188 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.997 ns                ;
+; 55.364 ns                               ; 139.12 MHz ( period = 7.188 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 6.998 ns                ;
+; 55.367 ns                               ; 139.18 MHz ( period = 7.185 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 6.995 ns                ;
+; 55.367 ns                               ; 139.18 MHz ( period = 7.185 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.001 ns                ;
+; 55.374 ns                               ; 139.31 MHz ( period = 7.178 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.996 ns                ;
+; 55.376 ns                               ; 139.35 MHz ( period = 7.176 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.987 ns                ;
+; 55.379 ns                               ; 139.41 MHz ( period = 7.173 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.984 ns                ;
+; 55.383 ns                               ; 139.49 MHz ( period = 7.169 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.980 ns                ;
+; 55.383 ns                               ; 139.49 MHz ( period = 7.169 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.967 ns                ;
+; 55.384 ns                               ; 139.51 MHz ( period = 7.168 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.986 ns                ;
+; 55.386 ns                               ; 139.55 MHz ( period = 7.166 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.964 ns                ;
+; 55.386 ns                               ; 139.55 MHz ( period = 7.166 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.982 ns                ;
+; 55.387 ns                               ; 139.57 MHz ( period = 7.165 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.963 ns                ;
+; 55.387 ns                               ; 139.57 MHz ( period = 7.165 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.963 ns                ;
+; 55.389 ns                               ; 139.61 MHz ( period = 7.163 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.983 ns                ;
+; 55.393 ns                               ; 139.68 MHz ( period = 7.159 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.972 ns                ;
+; 55.399 ns                               ; 139.80 MHz ( period = 7.153 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.966 ns                ;
+; 55.403 ns                               ; 139.88 MHz ( period = 7.149 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.374 ns                 ; 6.971 ns                ;
+; 55.406 ns                               ; 139.94 MHz ( period = 7.146 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.959 ns                ;
+; 55.406 ns                               ; 139.94 MHz ( period = 7.146 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.959 ns                ;
+; 55.408 ns                               ; 139.98 MHz ( period = 7.144 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.739 ns                 ; 7.331 ns                ;
+; 55.409 ns                               ; 140.00 MHz ( period = 7.143 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.961 ns                ;
+; 55.415 ns                               ; 140.11 MHz ( period = 7.137 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.944 ns                ;
+; 55.418 ns                               ; 140.17 MHz ( period = 7.134 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.354 ns                 ; 6.936 ns                ;
+; 55.418 ns                               ; 140.17 MHz ( period = 7.134 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.932 ns                ;
+; 55.422 ns                               ; 140.25 MHz ( period = 7.130 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.946 ns                ;
+; 55.428 ns                               ; 140.37 MHz ( period = 7.124 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.938 ns                ;
+; 55.428 ns                               ; 140.37 MHz ( period = 7.124 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.935 ns                ;
+; 55.430 ns                               ; 140.41 MHz ( period = 7.122 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 6.922 ns                ;
+; 55.440 ns                               ; 140.61 MHz ( period = 7.112 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.921 ns                ;
+; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.920 ns                ;
+; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
+; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
+; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
+; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.918 ns                ;
+; 55.443 ns                               ; 140.67 MHz ( period = 7.109 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.922 ns                ;
+; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.907 ns                ;
+; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
+; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
+; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
+; 55.459 ns                               ; 140.98 MHz ( period = 7.093 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.909 ns                ;
+; 55.462 ns                               ; 141.04 MHz ( period = 7.090 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.902 ns                ;
+; 55.463 ns                               ; 141.06 MHz ( period = 7.089 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.901 ns                ;
+; 55.465 ns                               ; 141.10 MHz ( period = 7.087 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.901 ns                ;
+; 55.467 ns                               ; 141.14 MHz ( period = 7.085 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.897 ns                ;
+; 55.469 ns                               ; 141.18 MHz ( period = 7.083 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.895 ns                ;
+; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.895 ns                ;
+; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
+; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
+; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
+; 55.471 ns                               ; 141.22 MHz ( period = 7.081 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.893 ns                ;
+; 55.477 ns                               ; 141.34 MHz ( period = 7.075 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.889 ns                ;
+; 55.478 ns                               ; 141.36 MHz ( period = 7.074 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.890 ns                ;
+; 55.480 ns                               ; 141.40 MHz ( period = 7.072 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.888 ns                ;
+; 55.483 ns                               ; 141.46 MHz ( period = 7.069 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.885 ns                ;
+; 55.486 ns                               ; 141.52 MHz ( period = 7.066 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.880 ns                ;
+; 55.487 ns                               ; 141.54 MHz ( period = 7.065 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.883 ns                ;
+; 55.490 ns                               ; 141.60 MHz ( period = 7.062 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.278 ns                 ; 6.788 ns                ;
+; 55.490 ns                               ; 141.60 MHz ( period = 7.062 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.876 ns                ;
+; 55.491 ns                               ; 141.62 MHz ( period = 7.061 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.877 ns                ;
+; 55.492 ns                               ; 141.64 MHz ( period = 7.060 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.874 ns                ;
+; 55.494 ns                               ; 141.68 MHz ( period = 7.058 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.872 ns                ;
+; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.354 ns                 ; 6.859 ns                ;
+; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
+; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
+; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
+; 55.496 ns                               ; 141.72 MHz ( period = 7.056 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.863 ns                ;
+; 55.497 ns                               ; 141.74 MHz ( period = 7.055 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.866 ns                ;
+; 55.499 ns                               ; 141.78 MHz ( period = 7.053 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.860 ns                ;
+; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.859 ns                ;
+; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.861 ns                ;
+; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.859 ns                ;
+; 55.501 ns                               ; 141.82 MHz ( period = 7.051 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.869 ns                ;
+; 55.503 ns                               ; 141.86 MHz ( period = 7.049 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.867 ns                ;
+; 55.506 ns                               ; 141.92 MHz ( period = 7.046 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.864 ns                ;
+; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 6.845 ns                ;
+; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
+; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
+; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.856 ns                ;
+; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
+; 55.508 ns                               ; 141.96 MHz ( period = 7.044 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.855 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                     ;                                                                                                                                                                                                                 ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; -4.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.928 ns                 ; 3.687 ns                ;
+; -4.573 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.921 ns                 ; 3.652 ns                ;
+; -4.568 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.642 ns                ;
+; -4.562 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.915 ns                 ; 3.647 ns                ;
+; -4.553 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.635 ns                ;
+; -4.549 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.631 ns                ;
+; -4.541 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.928 ns                 ; 3.613 ns                ;
+; -4.533 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.610 ns                ;
+; -4.526 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.608 ns                ;
+; -4.479 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.898 ns                ;
+; -4.440 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.141 ns                ;
+; -4.440 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.517 ns                ;
+; -4.413 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.114 ns                ;
+; -4.409 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.486 ns                ;
+; -4.407 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.916 ns                 ; 3.491 ns                ;
+; -4.406 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.914 ns                 ; 3.492 ns                ;
+; -4.394 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.468 ns                ;
+; -4.391 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.465 ns                ;
+; -4.391 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.466 ns                ;
+; -4.386 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.461 ns                ;
+; -4.381 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.458 ns                ;
+; -4.378 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.455 ns                ;
+; -4.372 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.447 ns                ;
+; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.447 ns                ;
+; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.447 ns                ;
+; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.445 ns                ;
+; -4.369 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 4.068 ns                ;
+; -4.367 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.444 ns                ;
+; -4.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.441 ns                ;
+; -4.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.441 ns                ;
+; -4.364 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.441 ns                ;
+; -4.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 4.063 ns                ;
+; -4.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.440 ns                ;
+; -4.361 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.436 ns                ;
+; -4.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.434 ns                ;
+; -4.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.435 ns                ;
+; -4.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.431 ns                ;
+; -4.356 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.433 ns                ;
+; -4.353 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.428 ns                ;
+; -4.353 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.428 ns                ;
+; -4.351 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.931 ns                 ; 3.420 ns                ;
+; -4.348 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.426 ns                ;
+; -4.318 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.916 ns                 ; 3.402 ns                ;
+; -4.316 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.919 ns                 ; 3.397 ns                ;
+; -4.308 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 4.008 ns                ;
+; -4.306 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.725 ns                ;
+; -4.305 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.379 ns                ;
+; -4.301 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.002 ns                ;
+; -4.299 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.376 ns                ;
+; -4.298 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.924 ns                 ; 3.374 ns                ;
+; -4.297 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.374 ns                ;
+; -4.294 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.372 ns                ;
+; -4.293 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.370 ns                ;
+; -4.293 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.371 ns                ;
+; -4.290 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.365 ns                ;
+; -4.289 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.366 ns                ;
+; -4.289 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.364 ns                ;
+; -4.288 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.363 ns                ;
+; -4.279 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.356 ns                ;
+; -4.278 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.355 ns                ;
+; -4.277 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.354 ns                ;
+; -4.273 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.347 ns                ;
+; -4.271 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.972 ns                ;
+; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.970 ns                ;
+; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.343 ns                ;
+; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.346 ns                ;
+; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.346 ns                ;
+; -4.268 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.345 ns                ;
+; -4.268 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.345 ns                ;
+; -4.267 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.344 ns                ;
+; -4.266 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.343 ns                ;
+; -4.264 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.341 ns                ;
+; -4.264 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.341 ns                ;
+; -4.262 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.339 ns                ;
+; -4.262 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.339 ns                ;
+; -4.259 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.960 ns                ;
+; -4.259 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.334 ns                ;
+; -4.258 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.332 ns                ;
+; -4.256 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.333 ns                ;
+; -4.256 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.333 ns                ;
+; -4.255 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.329 ns                ;
+; -4.255 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.330 ns                ;
+; -4.253 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.330 ns                ;
+; -4.253 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.327 ns                ;
+; -4.251 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.328 ns                ;
+; -4.248 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.325 ns                ;
+; -4.247 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.324 ns                ;
+; -4.246 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.323 ns                ;
+; -4.245 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.319 ns                ;
+; -4.243 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.944 ns                ;
+; -4.241 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.316 ns                ;
+; -4.236 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.310 ns                ;
+; -4.230 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.929 ns                ;
+; -4.229 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.928 ns                ;
+; -4.219 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.919 ns                ;
+; -4.217 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.292 ns                ;
+; -4.215 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.916 ns                ;
+; -4.203 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.904 ns                ;
+; -4.199 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.899 ns                ;
+; -4.195 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.614 ns                ;
+; -4.194 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.269 ns                ;
+; -4.190 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.257 ns                ;
+; -4.188 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.887 ns                ;
+; -4.188 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.624 ns                 ; 3.564 ns                ;
+; -4.179 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.931 ns                 ; 3.248 ns                ;
+; -4.175 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.876 ns                ;
+; -4.172 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.591 ns                ;
+; -4.156 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.855 ns                ;
+; -4.154 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.551 ns                ;
+; -4.149 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.850 ns                ;
+; -4.148 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.847 ns                ;
+; -4.143 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.540 ns                ;
+; -4.142 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.612 ns                 ; 3.530 ns                ;
+; -4.140 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.624 ns                 ; 3.516 ns                ;
+; -4.139 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.216 ns                ;
+; -4.138 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.838 ns                ;
+; -4.137 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.211 ns                ;
+; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
+; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
+; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
+; -4.134 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.211 ns                ;
+; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.210 ns                ;
+; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.208 ns                ;
+; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.208 ns                ;
+; -4.130 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.204 ns                ;
+; -4.130 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.205 ns                ;
+; -4.128 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.205 ns                ;
+; -4.127 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.202 ns                ;
+; -4.125 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.199 ns                ;
+; -4.124 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.191 ns                ;
+; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.190 ns                ;
+; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.190 ns                ;
+; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.616 ns                 ; 3.497 ns                ;
+; -4.109 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.186 ns                ;
+; -4.108 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.505 ns                ;
+; -4.104 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.171 ns                ;
+; -4.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.176 ns                ;
+; -4.101 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.802 ns                ;
+; -4.100 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.519 ns                ;
+; -4.098 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.936 ns                 ; 3.162 ns                ;
+; -4.098 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.495 ns                ;
+; -4.097 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.796 ns                ;
+; -4.092 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.793 ns                ;
+; -4.088 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.507 ns                ;
+; -4.083 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.480 ns                ;
+; -4.078 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.779 ns                ;
+; -4.069 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.306 ns                 ; 3.763 ns                ;
+; -4.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.612 ns                 ; 3.456 ns                ;
+; -4.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.306 ns                 ; 3.762 ns                ;
+; -4.064 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.307 ns                 ; 3.757 ns                ;
+; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.613 ns                 ; 3.436 ns                ;
+; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.442 ns                ;
+; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.442 ns                ;
+; -4.041 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.308 ns                 ; 3.733 ns                ;
+; -4.038 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.615 ns                 ; 3.423 ns                ;
+; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.938 ns                 ; 3.096 ns                ;
+; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.943 ns                 ; 3.091 ns                ;
+; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.734 ns                ;
+; -4.024 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.613 ns                 ; 3.411 ns                ;
+; -4.019 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.438 ns                ;
+; -4.016 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.093 ns                ;
+; -4.015 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.092 ns                ;
+; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.091 ns                ;
+; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.091 ns                ;
+; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.089 ns                ;
+; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
+; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
+; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
+; -4.011 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.088 ns                ;
+; -4.011 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.085 ns                ;
+; -4.009 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.084 ns                ;
+; -4.006 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.080 ns                ;
+; -4.006 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.403 ns                ;
+; -4.005 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.080 ns                ;
+; -4.004 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.703 ns                ;
+; -4.000 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.419 ns                ;
+; -3.998 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.075 ns                ;
+; -3.998 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.699 ns                ;
+; -3.996 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.073 ns                ;
+; -3.995 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.392 ns                ;
+; -3.993 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.070 ns                ;
+; -3.991 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.068 ns                ;
+; -3.989 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.938 ns                 ; 3.051 ns                ;
+; -3.989 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.610 ns                 ; 3.379 ns                ;
+; -3.988 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.065 ns                ;
+; -3.986 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.061 ns                ;
+; -3.986 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.061 ns                ;
+; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.060 ns                ;
+; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.059 ns                ;
+; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.059 ns                ;
+; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.060 ns                ;
+; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.058 ns                ;
+; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.059 ns                ;
+; -3.983 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.057 ns                ;
+; -3.982 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.056 ns                ;
+; -3.981 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.055 ns                ;
+; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.369 ns                ;
+; -3.970 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.037 ns                ;
+; -3.966 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.666 ns                ;
+; -3.954 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.935 ns                 ; 3.019 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                              ; To                                                                                                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; -2.673 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.814 ns                  ; 3.487 ns                ;
+; -2.447 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 3.530 ns                ;
+; -2.348 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_BANK_OK                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.155 ns                ;
+; -2.346 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.153 ns                ;
+; -2.275 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.082 ns                ;
+; -2.254 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.061 ns                ;
+; -2.243 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.138 ns                  ; 3.381 ns                ;
+; -2.194 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.100 ns                  ; 3.294 ns                ;
+; -2.187 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 3.262 ns                ;
+; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.239 ns                ;
+; -2.024 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.169 ns                ;
+; -2.006 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.151 ns                ;
+; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.132 ns                  ; 3.125 ns                ;
+; -1.990 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_FIFO_WRE                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.797 ns                ;
+; -1.911 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.140 ns                  ; 3.051 ns                ;
+; -1.896 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 2.986 ns                ;
+; -1.895 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 2.985 ns                ;
+; -1.873 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7F                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.680 ns                ;
+; -1.871 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T3                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.678 ns                ;
+; -1.838 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                                       ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC                                                                                                  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; -1.306 ns                 ; 0.532 ns                ;
+; -1.834 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.131 ns                  ; 2.965 ns                ;
+; -1.828 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.907 ns                ;
+; -1.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.906 ns                ;
+; -1.824 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.903 ns                ;
+; -1.800 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.131 ns                  ; 2.931 ns                ;
+; -1.800 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.879 ns                ;
+; -1.765 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.910 ns                ;
+; -1.763 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.132 ns                  ; 2.895 ns                ;
+; -1.755 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.136 ns                  ; 2.891 ns                ;
+; -1.647 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.133 ns                  ; 2.780 ns                ;
+; -1.646 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.133 ns                  ; 2.779 ns                ;
+; -1.641 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.770 ns                ;
+; -1.610 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.739 ns                ;
+; -1.593 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.152 ns                  ; 2.745 ns                ;
+; -1.556 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.134 ns                  ; 2.690 ns                ;
+; -1.553 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.682 ns                ;
+; -1.470 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.612 ns                ;
+; -1.465 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.594 ns                ;
+; -1.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.127 ns                  ; 2.590 ns                ;
+; -1.451 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.596 ns                ;
+; -1.441 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.586 ns                ;
+; -1.436 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.136 ns                  ; 2.572 ns                ;
+; -1.413 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.555 ns                ;
+; -1.361 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.506 ns                ;
+; -1.341 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.486 ns                ;
+; -1.329 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.404 ns                ;
+; -1.327 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.410 ns                ;
+; -1.326 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.410 ns                ;
+; -1.302 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.385 ns                ;
+; -1.298 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.126 ns                  ; 2.424 ns                ;
+; -1.271 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 2.348 ns                ;
+; -1.252 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.335 ns                ;
+; -1.216 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.358 ns                ;
+; -1.202 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.277 ns                ;
+; -1.202 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.277 ns                ;
+; -1.181 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.264 ns                ;
+; -1.167 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_CB8                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.246 ns                ;
+; -1.162 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8F                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.241 ns                ;
+; -1.139 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.130 ns                  ; 2.269 ns                ;
+; -1.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.186 ns                ;
+; -1.077 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.140 ns                  ; 2.217 ns                ;
+; -1.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.151 ns                  ; 2.199 ns                ;
+; -1.047 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.131 ns                ;
+; -0.910 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.123 ns                  ; 2.033 ns                ;
+; -0.901 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.992 ns                ;
+; -0.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.917 ns                ;
+; -0.750 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.841 ns                ;
+; -0.750 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.841 ns                ;
+; -0.741 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.832 ns                ;
+; -0.642 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.730 ns                ;
+; -0.623 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.711 ns                ;
+; -0.616 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.704 ns                ;
+; -0.600 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.688 ns                ;
+; -0.596 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.087 ns                  ; 1.683 ns                ;
+; -0.413 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 1.490 ns                ;
+; -0.410 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 1.487 ns                ;
+; -0.199 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.289 ns                ;
+; -0.193 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2B                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.283 ns                ;
+; -0.191 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.282 ns                ;
+; -0.186 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.175 ns                  ; 4.361 ns                ;
+; -0.183 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.274 ns                ;
+; -0.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 3.040 ns                  ; 3.142 ns                ;
+; -0.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.171 ns                  ; 4.239 ns                ;
+; -0.062 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.175 ns                  ; 4.237 ns                ;
+; -0.041 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.162 ns                  ; 4.203 ns                ;
+; -0.024 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.181 ns                  ; 4.205 ns                ;
+; 0.003 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.168 ns                  ; 4.165 ns                ;
+; 0.039 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.173 ns                  ; 4.134 ns                ;
+; 0.059 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.032 ns                ;
+; 0.073 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.171 ns                  ; 4.098 ns                ;
+; 0.080 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.167 ns                  ; 4.087 ns                ;
+; 0.108 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.181 ns                  ; 4.073 ns                ;
+; 0.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.168 ns                  ; 4.045 ns                ;
+; 0.165 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.182 ns                  ; 4.017 ns                ;
+; 0.166 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.173 ns                  ; 4.007 ns                ;
+; 0.194 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.167 ns                  ; 3.973 ns                ;
+; 0.201 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.162 ns                  ; 3.961 ns                ;
+; 0.250 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.464 ns                  ; 4.214 ns                ;
+; 0.301 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.522 ns                  ; 4.221 ns                ;
+; 0.306 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.483 ns                  ; 4.177 ns                ;
+; 0.375 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.514 ns                  ; 4.139 ns                ;
+; 0.401 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.475 ns                  ; 4.074 ns                ;
+; 0.451 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.182 ns                  ; 3.731 ns                ;
+; 0.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.477 ns                  ; 4.023 ns                ;
+; 0.467 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.473 ns                  ; 4.006 ns                ;
+; 0.509 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.503 ns                  ; 3.994 ns                ;
+; 0.514 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.469 ns                  ; 3.955 ns                ;
+; 0.539 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.484 ns                  ; 3.945 ns                ;
+; 0.568 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.823 ns                ;
+; 0.576 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.470 ns                  ; 3.894 ns                ;
+; 0.579 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.804 ns                ;
+; 0.580 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.408 ns                  ; 3.828 ns                ;
+; 0.619 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.768 ns                ;
+; 0.677 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.516 ns                  ; 3.839 ns                ;
+; 0.695 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.508 ns                  ; 3.813 ns                ;
+; 0.773 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.512 ns                  ; 3.739 ns                ;
+; 0.800 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.587 ns                ;
+; 0.805 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.582 ns                ;
+; 0.810 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.509 ns                  ; 3.699 ns                ;
+; 0.818 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.523 ns                  ; 3.705 ns                ;
+; 0.834 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.212 ns                  ; 3.378 ns                ;
+; 0.838 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.545 ns                ;
+; 0.840 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.551 ns                ;
+; 0.841 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.551 ns                ;
+; 0.933 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.454 ns                ;
+; 0.965 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.418 ns                ;
+; 0.965 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.418 ns                ;
+; 1.026 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.365 ns                ;
+; 1.038 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 3.347 ns                ;
+; 1.057 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.334 ns                ;
+; 1.110 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.057 ns                  ; 2.947 ns                ;
+; 1.120 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.272 ns                ;
+; 1.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.244 ns                ;
+; 1.153 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 3.245 ns                ;
+; 1.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.185 ns                ;
+; 1.266 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 3.133 ns                ;
+; 1.344 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.057 ns                  ; 2.713 ns                ;
+; 1.374 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 3.024 ns                ;
+; 1.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.982 ns                ;
+; 1.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A                                                                                                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.982 ns                ;
+; 1.426 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.973 ns                ;
+; 1.426 ns                                ; 162.63 MHz ( period = 6.149 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.936 ns                ;
+; 1.427 ns                                ; 162.65 MHz ( period = 6.148 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.935 ns                ;
+; 1.481 ns                                ; 164.10 MHz ( period = 6.094 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.881 ns                ;
+; 1.482 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 2.916 ns                ;
+; 1.484 ns                                ; 164.18 MHz ( period = 6.091 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.878 ns                ;
+; 1.526 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT                                                                                                 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 3.055 ns                  ; 1.529 ns                ;
+; 1.527 ns                                ; 165.34 MHz ( period = 6.048 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.835 ns                ;
+; 1.540 ns                                ; 165.70 MHz ( period = 6.035 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.822 ns                ;
+; 1.543 ns                                ; 165.78 MHz ( period = 6.032 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.819 ns                ;
+; 1.582 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[16]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.858 ns                  ; 3.276 ns                ;
+; 1.589 ns                                ; 167.06 MHz ( period = 5.986 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.773 ns                ;
+; 1.598 ns                                ; 167.31 MHz ( period = 5.977 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.764 ns                ;
+; 1.601 ns                                ; 167.39 MHz ( period = 5.974 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.761 ns                ;
+; 1.656 ns                                ; 168.95 MHz ( period = 5.919 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.706 ns                ;
+; 1.676 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.850 ns                  ; 3.174 ns                ;
+; 1.677 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.147 ns                ;
+; 1.679 ns                                ; 169.61 MHz ( period = 5.896 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.700 ns                ;
+; 1.680 ns                                ; 169.64 MHz ( period = 5.895 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.699 ns                ;
+; 1.686 ns                                ; 169.81 MHz ( period = 5.889 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.668 ns                ;
+; 1.687 ns                                ; 169.84 MHz ( period = 5.888 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.667 ns                ;
+; 1.714 ns                                ; 170.62 MHz ( period = 5.861 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.648 ns                ;
+; 1.734 ns                                ; 171.20 MHz ( period = 5.841 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.645 ns                ;
+; 1.737 ns                                ; 171.29 MHz ( period = 5.838 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.642 ns                ;
+; 1.738 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[21]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.841 ns                  ; 3.103 ns                ;
+; 1.741 ns                                ; 171.41 MHz ( period = 5.834 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.613 ns                ;
+; 1.744 ns                                ; 171.50 MHz ( period = 5.831 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.610 ns                ;
+; 1.746 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[21]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.841 ns                  ; 3.095 ns                ;
+; 1.747 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]   ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[1]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.865 ns                  ; 3.118 ns                ;
+; 1.750 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]  ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[26]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.866 ns                  ; 3.116 ns                ;
+; 1.756 ns                                ; 171.85 MHz ( period = 5.819 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[6]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.606 ns                ;
+; 1.760 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]   ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[1]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.865 ns                  ; 3.105 ns                ;
+; 1.779 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.045 ns                ;
+; 1.780 ns                                ; 172.56 MHz ( period = 5.795 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.599 ns                ;
+; 1.787 ns                                ; 172.77 MHz ( period = 5.788 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.567 ns                ;
+; 1.792 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.032 ns                ;
+; 1.793 ns                                ; 172.95 MHz ( period = 5.782 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.586 ns                ;
+; 1.796 ns                                ; 173.04 MHz ( period = 5.779 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.583 ns                ;
+; 1.800 ns                                ; 173.16 MHz ( period = 5.775 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.554 ns                ;
+; 1.803 ns                                ; 173.25 MHz ( period = 5.772 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.551 ns                ;
+; 1.805 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 2.580 ns                ;
+; 1.808 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 2.577 ns                ;
+; 1.812 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[23]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.831 ns                  ; 3.019 ns                ;
+; 1.829 ns                                ; 174.03 MHz ( period = 5.746 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.525 ns                ;
+; 1.830 ns                                ; 174.06 MHz ( period = 5.745 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.524 ns                ;
+; 1.840 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.559 ns                ;
+; 1.842 ns                                ; 174.43 MHz ( period = 5.733 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.537 ns                ;
+; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.557 ns                ;
+; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[28]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 2.982 ns                ;
+; 1.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[31]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.847 ns                  ; 3.002 ns                ;
+; 1.847 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[23]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.847 ns                  ; 3.000 ns                ;
+; 1.849 ns                                ; 174.64 MHz ( period = 5.726 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.505 ns                ;
+; 1.851 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 2.547 ns                ;
+; 1.851 ns                                ; 174.70 MHz ( period = 5.724 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.528 ns                ;
+; 1.854 ns                                ; 174.79 MHz ( period = 5.721 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.525 ns                ;
+; 1.858 ns                                ; 174.92 MHz ( period = 5.717 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.496 ns                ;
+; 1.861 ns                                ; 175.01 MHz ( period = 5.714 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.493 ns                ;
+; 1.865 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[16]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.826 ns                  ; 2.961 ns                ;
+; 1.873 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.829 ns                  ; 2.956 ns                ;
+; 1.881 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.829 ns                  ; 2.948 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                   ;                                                                                                                                                       ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack    ; Actual fmax (period)                        ; From                                                                                                                             ; To                                                                                                                                ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 2.965 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.639 ns                ;
+; 2.966 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.638 ns                ;
+; 2.967 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.637 ns                ;
+; 2.968 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.636 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
+; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
+; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
+; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
+; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
+; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
+; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
+; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
+; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                               ;
++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack    ; Actual fmax (period) ; From                                              ; To                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 5.299 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.118 ns                  ; 0.819 ns                ;
+; 5.479 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.637 ns                ;
+; 5.480 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.636 ns                ;
+; 5.606 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.510 ns                ;
+; 5.608 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.508 ns                ;
++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                   ; To                                                                                                                                  ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; 1.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 3.636 ns                ;
+; 1.683 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.304 ns                  ; 3.621 ns                ;
+; 1.703 ns                                ; 170.30 MHz ( period = 5.872 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 5.190 ns                ;
+; 1.806 ns                                ; 173.34 MHz ( period = 5.769 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.887 ns                  ; 5.081 ns                ;
+; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.327 ns                  ; 3.485 ns                ;
+; 1.881 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.428 ns                ;
+; 1.904 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.325 ns                  ; 3.421 ns                ;
+; 1.914 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.395 ns                ;
+; 1.923 ns                                ; 176.93 MHz ( period = 5.652 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 4.970 ns                ;
+; 2.000 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 3.308 ns                ;
+; 2.018 ns                                ; 179.95 MHz ( period = 5.557 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.883 ns                  ; 4.865 ns                ;
+; 2.034 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.321 ns                  ; 3.287 ns                ;
+; 2.040 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 3.253 ns                ;
+; 2.068 ns                                ; 181.59 MHz ( period = 5.507 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.887 ns                  ; 4.819 ns                ;
+; 2.105 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.302 ns                  ; 3.197 ns                ;
+; 2.112 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.488 ns                  ; 2.376 ns                ;
+; 2.131 ns                                ; 183.69 MHz ( period = 5.444 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.896 ns                  ; 4.765 ns                ;
+; 2.141 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 3.175 ns                ;
+; 2.151 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.307 ns                  ; 3.156 ns                ;
+; 2.155 ns                                ; 184.50 MHz ( period = 5.420 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.900 ns                  ; 4.745 ns                ;
+; 2.159 ns                                ; 184.64 MHz ( period = 5.416 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.891 ns                  ; 4.732 ns                ;
+; 2.166 ns                                ; 184.88 MHz ( period = 5.409 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.712 ns                ;
+; 2.178 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.131 ns                ;
+; 2.202 ns                                ; 186.12 MHz ( period = 5.373 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 4.691 ns                ;
+; 2.203 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 3.109 ns                ;
+; 2.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.335 ns                  ; 3.128 ns                ;
+; 2.238 ns                                ; 187.37 MHz ( period = 5.337 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.640 ns                ;
+; 2.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.317 ns                  ; 3.075 ns                ;
+; 2.260 ns                                ; 188.15 MHz ( period = 5.315 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.891 ns                  ; 4.631 ns                ;
+; 2.265 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.428 ns                  ; 2.163 ns                ;
+; 2.273 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.492 ns                  ; 2.219 ns                ;
+; 2.298 ns                                ; 189.50 MHz ( period = 5.277 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.901 ns                  ; 4.603 ns                ;
+; 2.325 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.991 ns                ;
+; 2.338 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.383 ns                  ; 3.045 ns                ;
+; 2.357 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.321 ns                  ; 2.964 ns                ;
+; 2.370 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.302 ns                  ; 2.932 ns                ;
+; 2.376 ns                                ; 192.34 MHz ( period = 5.199 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.883 ns                  ; 4.507 ns                ;
+; 2.385 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 3.250 ns                ;
+; 2.410 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.906 ns                ;
+; 2.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.307 ns                  ; 2.890 ns                ;
+; 2.434 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.373 ns                  ; 2.939 ns                ;
+; 2.445 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.495 ns                  ; 2.050 ns                ;
+; 2.447 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 2.865 ns                ;
+; 2.470 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.175 ns                ;
+; 2.502 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.652 ns                  ; 3.150 ns                ;
+; 2.509 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 3.134 ns                ;
+; 2.516 ns                                ; 197.67 MHz ( period = 5.059 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.725 ns                ;
+; 2.517 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 2.791 ns                ;
+; 2.520 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 2.773 ns                ;
+; 2.523 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.122 ns                ;
+; 2.531 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 3.108 ns                ;
+; 2.548 ns                                ; 198.93 MHz ( period = 5.027 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.248 ns                  ; 4.700 ns                ;
+; 2.549 ns                                ; 198.97 MHz ( period = 5.026 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.329 ns                ;
+; 2.550 ns                                ; 199.00 MHz ( period = 5.025 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.901 ns                  ; 4.351 ns                ;
+; 2.550 ns                                ; 199.00 MHz ( period = 5.025 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.239 ns                  ; 4.689 ns                ;
+; 2.561 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 2.814 ns                ;
+; 2.567 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.290 ns                  ; 2.723 ns                ;
+; 2.569 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.317 ns                  ; 2.748 ns                ;
+; 2.569 ns                                ; 199.76 MHz ( period = 5.006 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.231 ns                  ; 4.662 ns                ;
+; 2.570 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 2.805 ns                ;
+; 2.571 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 3.072 ns                ;
+; 2.572 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.306 ns                  ; 2.734 ns                ;
+; 2.597 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.719 ns                ;
+; 2.603 ns                                ; 201.13 MHz ( period = 4.972 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.638 ns                ;
+; 2.614 ns                                ; 201.57 MHz ( period = 4.961 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.239 ns                  ; 4.625 ns                ;
+; 2.616 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.377 ns                  ; 2.761 ns                ;
+; 2.622 ns                                ; 201.90 MHz ( period = 4.953 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 4.325 ns                ;
+; 2.641 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.004 ns                ;
+; 2.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.330 ns                  ; 2.645 ns                ;
+; 2.690 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.949 ns                ;
+; 2.695 ns                                ; 204.92 MHz ( period = 4.880 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.254 ns                ;
+; 2.697 ns                                ; 205.00 MHz ( period = 4.878 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.529 ns                ;
+; 2.708 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.648 ns                  ; 2.940 ns                ;
+; 2.716 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 2.596 ns                ;
+; 2.717 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.913 ns                ;
+; 2.718 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.912 ns                ;
+; 2.724 ns                                ; 206.14 MHz ( period = 4.851 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.517 ns                ;
+; 2.733 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.356 ns                  ; 2.623 ns                ;
+; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.911 ns                ;
+; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.381 ns                  ; 2.647 ns                ;
+; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.559 ns                  ; 1.825 ns                ;
+; 2.751 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.377 ns                  ; 2.626 ns                ;
+; 2.758 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.244 ns                  ; 4.486 ns                ;
+; 2.761 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.874 ns                ;
+; 2.761 ns                                ; 207.73 MHz ( period = 4.814 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.188 ns                ;
+; 2.764 ns                                ; 207.86 MHz ( period = 4.811 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.185 ns                ;
+; 2.768 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.652 ns                  ; 2.884 ns                ;
+; 2.771 ns                                ; 208.16 MHz ( period = 4.804 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.235 ns                  ; 4.464 ns                ;
+; 2.776 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 2.867 ns                ;
+; 2.778 ns                                ; 208.46 MHz ( period = 4.797 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.948 ns                  ; 4.170 ns                ;
+; 2.780 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.855 ns                ;
+; 2.793 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.852 ns                ;
+; 2.793 ns                                ; 209.12 MHz ( period = 4.782 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.433 ns                ;
+; 2.797 ns                                ; 209.29 MHz ( period = 4.778 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.429 ns                ;
+; 2.798 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.378 ns                  ; 2.580 ns                ;
+; 2.807 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.779 ns                  ; 2.972 ns                ;
+; 2.808 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.374 ns                  ; 2.566 ns                ;
+; 2.815 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.373 ns                  ; 2.558 ns                ;
+; 2.821 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.818 ns                ;
+; 2.838 ns                                ; 211.10 MHz ( period = 4.737 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.231 ns                  ; 4.393 ns                ;
+; 2.839 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 2.804 ns                ;
+; 2.846 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 2.447 ns                ;
+; 2.851 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.334 ns                  ; 2.483 ns                ;
+; 2.862 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.454 ns                ;
+; 2.909 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.736 ns                ;
+; 2.935 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.423 ns                ;
+; 2.937 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 4.006 ns                ;
+; 2.951 ns                                ; 216.26 MHz ( period = 4.624 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 3.998 ns                ;
+; 2.954 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.685 ns                ;
+; 2.960 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.655 ns                  ; 2.695 ns                ;
+; 2.963 ns                                ; 216.83 MHz ( period = 4.612 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 3.980 ns                ;
+; 2.969 ns                                ; 217.11 MHz ( period = 4.606 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.978 ns                ;
+; 2.977 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.648 ns                  ; 2.671 ns                ;
+; 2.983 ns                                ; 217.77 MHz ( period = 4.592 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.235 ns                  ; 4.252 ns                ;
+; 2.984 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.646 ns                ;
+; 2.985 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.645 ns                ;
+; 2.988 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.779 ns                  ; 2.791 ns                ;
+; 3.004 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 2.358 ns                ;
+; 3.005 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.364 ns                  ; 2.359 ns                ;
+; 3.010 ns                                ; 219.06 MHz ( period = 4.565 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.292 ns                  ; 4.282 ns                ;
+; 3.018 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.653 ns                  ; 2.635 ns                ;
+; 3.027 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.608 ns                ;
+; 3.042 ns                                ; 220.60 MHz ( period = 4.533 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.294 ns                  ; 4.252 ns                ;
+; 3.047 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.729 ns                  ; 2.682 ns                ;
+; 3.051 ns                                ; 221.04 MHz ( period = 4.524 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.249 ns                  ; 4.198 ns                ;
+; 3.058 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.354 ns                  ; 2.296 ns                ;
+; 3.061 ns                                ; 221.53 MHz ( period = 4.514 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.249 ns                  ; 4.188 ns                ;
+; 3.074 ns                                ; 222.17 MHz ( period = 4.501 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.946 ns                  ; 3.872 ns                ;
+; 3.096 ns                                ; 223.26 MHz ( period = 4.479 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.851 ns                ;
+; 3.115 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.246 ns                ;
+; 3.127 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.234 ns                ;
+; 3.131 ns                                ; 225.02 MHz ( period = 4.444 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 3.812 ns                ;
+; 3.141 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.325 ns                  ; 2.184 ns                ;
+; 3.143 ns                                ; 225.63 MHz ( period = 4.432 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 4.152 ns                ;
+; 3.151 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.479 ns                ;
+; 3.158 ns                                ; 226.40 MHz ( period = 4.417 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.292 ns                  ; 4.134 ns                ;
+; 3.159 ns                                ; 226.45 MHz ( period = 4.416 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.132 ns                ;
+; 3.162 ns                                ; 226.60 MHz ( period = 4.413 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 4.133 ns                ;
+; 3.163 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.780 ns                  ; 2.617 ns                ;
+; 3.173 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.680 ns                  ; 2.507 ns                ;
+; 3.181 ns                                ; 227.58 MHz ( period = 4.394 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.944 ns                  ; 3.763 ns                ;
+; 3.192 ns                                ; 228.15 MHz ( period = 4.383 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.755 ns                ;
+; 3.199 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.431 ns                ;
+; 3.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.671 ns                  ; 2.464 ns                ;
+; 3.208 ns                                ; 228.99 MHz ( period = 4.367 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.946 ns                  ; 3.738 ns                ;
+; 3.209 ns                                ; 229.04 MHz ( period = 4.366 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.944 ns                  ; 3.735 ns                ;
+; 3.225 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.470 ns                ;
+; 3.226 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.655 ns                  ; 2.429 ns                ;
+; 3.233 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 2.126 ns                ;
+; 3.236 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.125 ns                ;
+; 3.251 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.107 ns                ;
+; 3.253 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.355 ns                  ; 2.102 ns                ;
+; 3.261 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.097 ns                ;
+; 3.262 ns                                ; 231.86 MHz ( period = 4.313 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 4.035 ns                ;
+; 3.263 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.363 ns                  ; 2.100 ns                ;
+; 3.266 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.363 ns                  ; 2.097 ns                ;
+; 3.271 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 2.091 ns                ;
+; 3.277 ns                                ; 232.67 MHz ( period = 4.298 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.014 ns                ;
+; 3.279 ns                                ; 232.77 MHz ( period = 4.296 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.012 ns                ;
+; 3.282 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.653 ns                  ; 2.371 ns                ;
+; 3.307 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.383 ns                  ; 2.076 ns                ;
+; 3.346 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.352 ns                ;
+; 3.351 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.344 ns                ;
+; 3.365 ns                                ; 237.53 MHz ( period = 4.210 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.296 ns                  ; 3.931 ns                ;
+; 3.387 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 1.974 ns                ;
+; 3.390 ns                                ; 238.95 MHz ( period = 4.185 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.294 ns                  ; 3.904 ns                ;
+; 3.410 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 1.952 ns                ;
+; 3.415 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.283 ns                ;
+; 3.429 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 1.929 ns                ;
+; 3.438 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 1.937 ns                ;
+; 3.450 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.700 ns                  ; 2.250 ns                ;
+; 3.458 ns                                ; 242.90 MHz ( period = 4.117 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 3.837 ns                ;
+; 3.459 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.239 ns                ;
+; 3.461 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.781 ns                  ; 2.320 ns                ;
+; 3.474 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.380 ns                  ; 1.906 ns                ;
+; 3.477 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 1.882 ns                ;
+; 3.492 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.203 ns                ;
+; 3.495 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.700 ns                  ; 2.205 ns                ;
+; 3.499 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 1.860 ns                ;
+; 3.504 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 1.857 ns                ;
+; 3.558 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.141 ns                ;
+; 3.575 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 2.122 ns                ;
+; 3.602 ns                                ; 251.70 MHz ( period = 3.973 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 3.693 ns                ;
+; 3.610 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.089 ns                ;
+; 3.614 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.084 ns                ;
+; 3.616 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.701 ns                  ; 2.085 ns                ;
+; 3.617 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.696 ns                  ; 2.079 ns                ;
+; 3.620 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 2.077 ns                ;
+; 3.625 ns                                ; 253.16 MHz ( period = 3.950 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 3.672 ns                ;
+; 3.640 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.059 ns                ;
+; 3.649 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.726 ns                  ; 2.077 ns                ;
+; 3.657 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.042 ns                ;
+; 3.663 ns                                ; 255.62 MHz ( period = 3.912 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 3.634 ns                ;
+; 3.664 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.696 ns                  ; 2.032 ns                ;
+; 3.673 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.703 ns                  ; 2.030 ns                ;
+; 3.675 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.024 ns                ;
+; 3.708 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.702 ns                  ; 1.994 ns                ;
+; 3.720 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.703 ns                  ; 1.983 ns                ;
+; 3.738 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 1.959 ns                ;
+; 3.825 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 1.874 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                        ;                                                                                                                                     ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'                                                                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                           ; To                                                                     ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; -1.712 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 1.118 ns                  ; 2.830 ns                ;
+; -1.664 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.656 ns                ;
+; -1.597 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.589 ns                ;
+; -1.597 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.589 ns                ;
+; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
+; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
+; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
+; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
+; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
+; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
+; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
+; -1.333 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.319 ns                ;
+; -1.333 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.319 ns                ;
+; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
+; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
+; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
+; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
+; -1.278 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.264 ns                ;
+; -1.278 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.264 ns                ;
+; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
+; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
+; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
+; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
+; -1.248 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.989 ns                  ; 2.237 ns                ;
+; -1.243 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.989 ns                  ; 2.232 ns                ;
+; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
+; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
+; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
+; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
+; 4.485 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 6.311 ns                    ; 6.117 ns                  ; 1.632 ns                ;
+; 6.612 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.393 ns                 ; 3.781 ns                ;
+; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
+; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
+; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
+; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
+; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
+; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
+; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
+; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
+; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
+; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
+; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
+; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
+; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
+; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
+; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
+; 6.843 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.545 ns                 ; 3.702 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
+; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
+; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
+; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
+; 7.011 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.390 ns                 ; 3.379 ns                ;
+; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
+; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
+; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
+; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
+; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
+; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
+; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
+; 7.111 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.514 ns                 ; 3.403 ns                ;
+; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
+; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
+; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
+; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
+; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
+; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
+; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
+; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
+; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
+; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
+; 7.264 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.548 ns                 ; 3.284 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
+; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
+; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
+; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
+; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
+; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
+; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
+; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
+; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
+; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
+; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
+; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
+; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                ;                                                                        ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+; -4.294 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.607 ns                 ; 3.687 ns                ;
+; -4.252 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.600 ns                 ; 3.652 ns                ;
+; -4.247 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.642 ns                ;
+; -4.241 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.594 ns                 ; 3.647 ns                ;
+; -4.232 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.635 ns                ;
+; -4.228 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.631 ns                ;
+; -4.220 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.607 ns                 ; 3.613 ns                ;
+; -4.212 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.610 ns                ;
+; -4.205 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.608 ns                ;
+; -4.158 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.898 ns                ;
+; -4.119 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.141 ns                ;
+; -4.119 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.517 ns                ;
+; -4.092 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.114 ns                ;
+; -4.088 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.486 ns                ;
+; -4.086 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.595 ns                 ; 3.491 ns                ;
+; -4.085 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.593 ns                 ; 3.492 ns                ;
+; -4.073 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.468 ns                ;
+; -4.070 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.465 ns                ;
+; -4.070 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.466 ns                ;
+; -4.065 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.461 ns                ;
+; -4.060 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.458 ns                ;
+; -4.057 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.455 ns                ;
+; -4.051 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.447 ns                ;
+; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.447 ns                ;
+; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.447 ns                ;
+; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.445 ns                ;
+; -4.048 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 4.068 ns                ;
+; -4.046 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.444 ns                ;
+; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.441 ns                ;
+; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.441 ns                ;
+; -4.043 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.441 ns                ;
+; -4.042 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 4.063 ns                ;
+; -4.042 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.440 ns                ;
+; -4.040 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.436 ns                ;
+; -4.039 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.434 ns                ;
+; -4.039 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.435 ns                ;
+; -4.036 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.431 ns                ;
+; -4.035 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.433 ns                ;
+; -4.032 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.428 ns                ;
+; -4.032 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.428 ns                ;
+; -4.030 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.610 ns                 ; 3.420 ns                ;
+; -4.027 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.426 ns                ;
+; -3.997 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.595 ns                 ; 3.402 ns                ;
+; -3.995 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.598 ns                 ; 3.397 ns                ;
+; -3.987 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 4.008 ns                ;
+; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.725 ns                ;
+; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.379 ns                ;
+; -3.980 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.002 ns                ;
+; -3.978 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.376 ns                ;
+; -3.977 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.603 ns                 ; 3.374 ns                ;
+; -3.976 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.374 ns                ;
+; -3.973 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.372 ns                ;
+; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.370 ns                ;
+; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.371 ns                ;
+; -3.969 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.365 ns                ;
+; -3.968 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.366 ns                ;
+; -3.968 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.364 ns                ;
+; -3.967 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.363 ns                ;
+; -3.958 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.356 ns                ;
+; -3.957 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.355 ns                ;
+; -3.956 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.354 ns                ;
+; -3.952 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.347 ns                ;
+; -3.950 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.972 ns                ;
+; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.970 ns                ;
+; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.343 ns                ;
+; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.346 ns                ;
+; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.346 ns                ;
+; -3.947 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.345 ns                ;
+; -3.947 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.345 ns                ;
+; -3.946 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.344 ns                ;
+; -3.945 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.343 ns                ;
+; -3.943 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.341 ns                ;
+; -3.943 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.341 ns                ;
+; -3.941 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.339 ns                ;
+; -3.941 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.339 ns                ;
+; -3.938 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.960 ns                ;
+; -3.938 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.334 ns                ;
+; -3.937 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.332 ns                ;
+; -3.935 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.333 ns                ;
+; -3.935 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.333 ns                ;
+; -3.934 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.329 ns                ;
+; -3.934 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.330 ns                ;
+; -3.932 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.330 ns                ;
+; -3.932 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.327 ns                ;
+; -3.930 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.328 ns                ;
+; -3.927 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.325 ns                ;
+; -3.926 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.324 ns                ;
+; -3.925 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.323 ns                ;
+; -3.924 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.319 ns                ;
+; -3.922 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.944 ns                ;
+; -3.920 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.316 ns                ;
+; -3.915 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.310 ns                ;
+; -3.909 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.929 ns                ;
+; -3.908 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.928 ns                ;
+; -3.898 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.919 ns                ;
+; -3.896 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.292 ns                ;
+; -3.894 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.916 ns                ;
+; -3.882 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.904 ns                ;
+; -3.878 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.899 ns                ;
+; -3.874 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.614 ns                ;
+; -3.873 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.269 ns                ;
+; -3.869 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.257 ns                ;
+; -3.867 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.887 ns                ;
+; -3.867 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.303 ns                 ; 3.564 ns                ;
+; -3.858 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.610 ns                 ; 3.248 ns                ;
+; -3.854 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.876 ns                ;
+; -3.851 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.591 ns                ;
+; -3.835 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.855 ns                ;
+; -3.833 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.551 ns                ;
+; -3.828 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.850 ns                ;
+; -3.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.847 ns                ;
+; -3.822 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.540 ns                ;
+; -3.821 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.291 ns                 ; 3.530 ns                ;
+; -3.819 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.303 ns                 ; 3.516 ns                ;
+; -3.818 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.216 ns                ;
+; -3.817 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.838 ns                ;
+; -3.816 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.211 ns                ;
+; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
+; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
+; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
+; -3.813 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.211 ns                ;
+; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.210 ns                ;
+; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.208 ns                ;
+; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.208 ns                ;
+; -3.809 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.204 ns                ;
+; -3.809 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.205 ns                ;
+; -3.807 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.205 ns                ;
+; -3.806 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.202 ns                ;
+; -3.804 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.199 ns                ;
+; -3.803 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.191 ns                ;
+; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.190 ns                ;
+; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.190 ns                ;
+; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.295 ns                 ; 3.497 ns                ;
+; -3.788 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.186 ns                ;
+; -3.787 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.505 ns                ;
+; -3.783 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.171 ns                ;
+; -3.781 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.176 ns                ;
+; -3.780 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.802 ns                ;
+; -3.779 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.519 ns                ;
+; -3.777 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.615 ns                 ; 3.162 ns                ;
+; -3.777 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.495 ns                ;
+; -3.776 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.796 ns                ;
+; -3.771 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.793 ns                ;
+; -3.767 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.507 ns                ;
+; -3.762 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.480 ns                ;
+; -3.757 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.779 ns                ;
+; -3.748 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.015 ns                  ; 3.763 ns                ;
+; -3.747 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.291 ns                 ; 3.456 ns                ;
+; -3.747 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.015 ns                  ; 3.762 ns                ;
+; -3.743 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.014 ns                  ; 3.757 ns                ;
+; -3.728 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.292 ns                 ; 3.436 ns                ;
+; -3.724 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.442 ns                ;
+; -3.724 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.442 ns                ;
+; -3.720 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.013 ns                  ; 3.733 ns                ;
+; -3.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.294 ns                 ; 3.423 ns                ;
+; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.617 ns                 ; 3.096 ns                ;
+; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.622 ns                 ; 3.091 ns                ;
+; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.734 ns                ;
+; -3.703 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.292 ns                 ; 3.411 ns                ;
+; -3.698 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.438 ns                ;
+; -3.695 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.093 ns                ;
+; -3.694 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.092 ns                ;
+; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.091 ns                ;
+; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.091 ns                ;
+; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.089 ns                ;
+; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
+; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
+; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
+; -3.690 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.088 ns                ;
+; -3.690 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.085 ns                ;
+; -3.688 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.084 ns                ;
+; -3.685 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.080 ns                ;
+; -3.685 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.403 ns                ;
+; -3.684 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.080 ns                ;
+; -3.683 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.703 ns                ;
+; -3.679 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.419 ns                ;
+; -3.677 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.075 ns                ;
+; -3.677 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.699 ns                ;
+; -3.675 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.073 ns                ;
+; -3.674 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.392 ns                ;
+; -3.672 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.070 ns                ;
+; -3.670 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.068 ns                ;
+; -3.668 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.617 ns                 ; 3.051 ns                ;
+; -3.668 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.289 ns                 ; 3.379 ns                ;
+; -3.667 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.065 ns                ;
+; -3.665 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.061 ns                ;
+; -3.665 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.061 ns                ;
+; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.060 ns                ;
+; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.059 ns                ;
+; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.059 ns                ;
+; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.060 ns                ;
+; -3.663 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.058 ns                ;
+; -3.663 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.059 ns                ;
+; -3.662 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.057 ns                ;
+; -3.661 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.056 ns                ;
+; -3.660 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.055 ns                ;
+; -3.651 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.369 ns                ;
+; -3.649 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.037 ns                ;
+; -3.645 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.666 ns                ;
+; -3.633 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.614 ns                 ; 3.019 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'CLK33M'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+; -5.966 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.279 ns                 ; 3.687 ns                ;
+; -5.924 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.272 ns                 ; 3.652 ns                ;
+; -5.919 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.642 ns                ;
+; -5.913 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.266 ns                 ; 3.647 ns                ;
+; -5.904 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.635 ns                ;
+; -5.900 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.631 ns                ;
+; -5.892 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.279 ns                 ; 3.613 ns                ;
+; -5.884 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.610 ns                ;
+; -5.877 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.608 ns                ;
+; -5.830 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.898 ns                ;
+; -5.791 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.141 ns                ;
+; -5.791 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.517 ns                ;
+; -5.764 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.114 ns                ;
+; -5.760 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.486 ns                ;
+; -5.758 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.267 ns                 ; 3.491 ns                ;
+; -5.757 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.265 ns                 ; 3.492 ns                ;
+; -5.745 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.468 ns                ;
+; -5.742 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.465 ns                ;
+; -5.742 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.466 ns                ;
+; -5.737 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.461 ns                ;
+; -5.732 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.458 ns                ;
+; -5.729 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.455 ns                ;
+; -5.723 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.447 ns                ;
+; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.447 ns                ;
+; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.447 ns                ;
+; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.445 ns                ;
+; -5.720 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 4.068 ns                ;
+; -5.718 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.444 ns                ;
+; -5.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.441 ns                ;
+; -5.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.441 ns                ;
+; -5.715 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.441 ns                ;
+; -5.714 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 4.063 ns                ;
+; -5.714 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.440 ns                ;
+; -5.712 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.436 ns                ;
+; -5.711 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.434 ns                ;
+; -5.711 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.435 ns                ;
+; -5.708 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.431 ns                ;
+; -5.707 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.433 ns                ;
+; -5.704 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.428 ns                ;
+; -5.704 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.428 ns                ;
+; -5.702 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.282 ns                 ; 3.420 ns                ;
+; -5.699 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.426 ns                ;
+; -5.669 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.267 ns                 ; 3.402 ns                ;
+; -5.667 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.270 ns                 ; 3.397 ns                ;
+; -5.659 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 4.008 ns                ;
+; -5.657 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.725 ns                ;
+; -5.656 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.379 ns                ;
+; -5.652 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.002 ns                ;
+; -5.650 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.376 ns                ;
+; -5.649 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.275 ns                 ; 3.374 ns                ;
+; -5.648 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.374 ns                ;
+; -5.645 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.372 ns                ;
+; -5.644 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.370 ns                ;
+; -5.644 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.371 ns                ;
+; -5.641 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.365 ns                ;
+; -5.640 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.366 ns                ;
+; -5.640 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.364 ns                ;
+; -5.639 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.363 ns                ;
+; -5.630 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.356 ns                ;
+; -5.629 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.355 ns                ;
+; -5.628 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.354 ns                ;
+; -5.624 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.347 ns                ;
+; -5.622 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.972 ns                ;
+; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.970 ns                ;
+; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.343 ns                ;
+; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.346 ns                ;
+; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.346 ns                ;
+; -5.619 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.345 ns                ;
+; -5.619 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.345 ns                ;
+; -5.618 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.344 ns                ;
+; -5.617 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.343 ns                ;
+; -5.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.341 ns                ;
+; -5.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.341 ns                ;
+; -5.613 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.339 ns                ;
+; -5.613 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.339 ns                ;
+; -5.610 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.960 ns                ;
+; -5.610 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.334 ns                ;
+; -5.609 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.332 ns                ;
+; -5.607 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.333 ns                ;
+; -5.607 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.333 ns                ;
+; -5.606 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.329 ns                ;
+; -5.606 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.330 ns                ;
+; -5.604 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.330 ns                ;
+; -5.604 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.327 ns                ;
+; -5.602 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.328 ns                ;
+; -5.599 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.325 ns                ;
+; -5.598 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.324 ns                ;
+; -5.597 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.323 ns                ;
+; -5.596 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.319 ns                ;
+; -5.594 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.944 ns                ;
+; -5.592 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.316 ns                ;
+; -5.587 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.310 ns                ;
+; -5.581 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.929 ns                ;
+; -5.580 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.928 ns                ;
+; -5.570 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.919 ns                ;
+; -5.568 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.292 ns                ;
+; -5.566 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.916 ns                ;
+; -5.554 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.904 ns                ;
+; -5.550 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.899 ns                ;
+; -5.546 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.614 ns                ;
+; -5.545 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.269 ns                ;
+; -5.541 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.257 ns                ;
+; -5.539 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.887 ns                ;
+; -5.539 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.975 ns                 ; 3.564 ns                ;
+; -5.530 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.282 ns                 ; 3.248 ns                ;
+; -5.526 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.876 ns                ;
+; -5.523 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.591 ns                ;
+; -5.507 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.855 ns                ;
+; -5.505 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.551 ns                ;
+; -5.500 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.850 ns                ;
+; -5.499 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.847 ns                ;
+; -5.494 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.540 ns                ;
+; -5.493 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.963 ns                 ; 3.530 ns                ;
+; -5.491 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.975 ns                 ; 3.516 ns                ;
+; -5.490 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.216 ns                ;
+; -5.489 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.838 ns                ;
+; -5.488 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.211 ns                ;
+; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
+; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
+; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
+; -5.485 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.211 ns                ;
+; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.210 ns                ;
+; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.208 ns                ;
+; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.208 ns                ;
+; -5.481 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.204 ns                ;
+; -5.481 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.205 ns                ;
+; -5.479 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.205 ns                ;
+; -5.478 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.202 ns                ;
+; -5.476 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.199 ns                ;
+; -5.475 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.191 ns                ;
+; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.190 ns                ;
+; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.190 ns                ;
+; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.967 ns                 ; 3.497 ns                ;
+; -5.460 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.186 ns                ;
+; -5.459 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.505 ns                ;
+; -5.455 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.171 ns                ;
+; -5.453 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.176 ns                ;
+; -5.452 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.802 ns                ;
+; -5.451 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.519 ns                ;
+; -5.449 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.287 ns                 ; 3.162 ns                ;
+; -5.449 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.495 ns                ;
+; -5.448 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.796 ns                ;
+; -5.443 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.793 ns                ;
+; -5.439 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.507 ns                ;
+; -5.434 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.480 ns                ;
+; -5.429 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.779 ns                ;
+; -5.420 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.657 ns                 ; 3.763 ns                ;
+; -5.419 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.963 ns                 ; 3.456 ns                ;
+; -5.419 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.657 ns                 ; 3.762 ns                ;
+; -5.415 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.658 ns                 ; 3.757 ns                ;
+; -5.400 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.964 ns                 ; 3.436 ns                ;
+; -5.396 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.442 ns                ;
+; -5.396 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.442 ns                ;
+; -5.392 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.659 ns                 ; 3.733 ns                ;
+; -5.389 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.966 ns                 ; 3.423 ns                ;
+; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.289 ns                 ; 3.096 ns                ;
+; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.294 ns                 ; 3.091 ns                ;
+; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.734 ns                ;
+; -5.375 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.964 ns                 ; 3.411 ns                ;
+; -5.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.438 ns                ;
+; -5.367 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.093 ns                ;
+; -5.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.092 ns                ;
+; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.091 ns                ;
+; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.091 ns                ;
+; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.089 ns                ;
+; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
+; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
+; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
+; -5.362 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.088 ns                ;
+; -5.362 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.085 ns                ;
+; -5.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.084 ns                ;
+; -5.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.080 ns                ;
+; -5.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.403 ns                ;
+; -5.356 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.080 ns                ;
+; -5.355 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.703 ns                ;
+; -5.351 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.419 ns                ;
+; -5.349 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.075 ns                ;
+; -5.349 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.699 ns                ;
+; -5.347 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.073 ns                ;
+; -5.346 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.392 ns                ;
+; -5.344 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.070 ns                ;
+; -5.342 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.068 ns                ;
+; -5.340 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.289 ns                 ; 3.051 ns                ;
+; -5.340 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.961 ns                 ; 3.379 ns                ;
+; -5.339 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.065 ns                ;
+; -5.337 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.061 ns                ;
+; -5.337 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.061 ns                ;
+; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.060 ns                ;
+; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.059 ns                ;
+; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.059 ns                ;
+; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.060 ns                ;
+; -5.335 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.058 ns                ;
+; -5.335 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.059 ns                ;
+; -5.334 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.057 ns                ;
+; -5.333 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.056 ns                ;
+; -5.332 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.055 ns                ;
+; -5.323 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.369 ns                ;
+; -5.321 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.037 ns                ;
+; -5.317 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.666 ns                ;
+; -5.305 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.286 ns                 ; 3.019 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'MAIN_CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack                                   ; Actual fmax (period)                                ; From                                           ; To                                                                                                                                                                                                               ; From Clock                                                               ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+; -4.261 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.318 ns                ;
+; -4.260 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a8                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.317 ns                ;
+; -4.258 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a6                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.315 ns                ;
+; -4.239 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a5                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.296 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[31]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[30]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[29]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[28]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[27]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[26]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[25]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[24]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[23]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[22]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[21]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[20]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[19]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[18]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[17]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[16]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[15]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[14]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[13]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[12]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[11]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[10]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[9]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
+; -4.071 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~portb_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.225 ns                  ; 4.296 ns                ;
+; -4.023 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.012 ns                  ; 4.035 ns                ;
+; -4.023 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[4]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.012 ns                  ; 4.035 ns                ;
+; -3.979 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a2                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.272 ns                  ; 4.251 ns                ;
+; -3.910 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a4                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.967 ns                ;
+; -3.907 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a3                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.964 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[1]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[2]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[0]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[0]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[1]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[6]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[2]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[7]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[8]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[3]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[5]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
+; -3.546 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a1                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.603 ns                ;
+; -3.544 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.601 ns                ;
+; -3.541 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.096 ns                  ; 3.637 ns                ;
+; -3.426 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; -0.013 ns                 ; 3.413 ns                ;
+; -3.055 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.360 ns                  ; 3.415 ns                ;
+; -3.039 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WRF_WRE                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; -0.013 ns                 ; 3.026 ns                ;
+; -2.598 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.205 ns                  ; 2.803 ns                ;
+; -2.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.530 ns                ;
+; -2.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.530 ns                ;
+; -2.375 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 7.143 ns                ;
+; -2.355 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.341 ns                ;
+; -2.320 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.304 ns                ;
+; -2.317 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.384 ns                ;
+; -2.317 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.384 ns                ;
+; -2.290 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 7.056 ns                ;
+; -2.250 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.317 ns                ;
+; -2.250 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.317 ns                ;
+; -2.246 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 6.245 ns                ;
+; -2.239 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.307 ns                ;
+; -2.239 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.307 ns                ;
+; -2.229 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.997 ns                ;
+; -2.209 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.195 ns                ;
+; -2.199 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.317 ns                ;
+; -2.199 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.317 ns                ;
+; -2.183 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.129 ns                  ; 6.312 ns                ;
+; -2.177 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.390 ns                ;
+; -2.177 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.390 ns                ;
+; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.769 ns                  ; 6.920 ns                ;
+; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.270 ns                ;
+; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.270 ns                ;
+; -2.147 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.265 ns                ;
+; -2.147 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.265 ns                ;
+; -2.146 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.120 ns                  ; 6.266 ns                ;
+; -2.146 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.120 ns                  ; 6.266 ns                ;
+; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.260 ns                ;
+; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.261 ns                ;
+; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.260 ns                ;
+; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.261 ns                ;
+; -2.139 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 6.905 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
+; -2.133 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.119 ns                ;
+; -2.132 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.116 ns                ;
+; -2.131 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.987 ns                  ; 6.118 ns                ;
+; -2.129 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.248 ns                ;
+; -2.129 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.248 ns                ;
+; -2.122 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.187 ns                ;
+; -2.122 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.187 ns                ;
+; -2.118 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.186 ns                ;
+; -2.118 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.186 ns                ;
+; -2.100 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 6.099 ns                ;
+; -2.098 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.215 ns                ;
+; -2.098 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.215 ns                ;
+; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.159 ns                ;
+; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.159 ns                ;
+; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
+; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
+; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
+; -2.083 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.620 ns                ;
+; -2.062 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.830 ns                ;
+; -2.060 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.828 ns                ;
+; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
+; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
+; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
+; -2.045 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 6.811 ns                ;
+; -2.045 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|UE                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.701 ns                  ; 5.746 ns                ;
+; -2.037 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.129 ns                  ; 6.166 ns                ;
+; -2.035 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.573 ns                ;
+; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[3][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
+; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[4][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
+; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[5][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
+; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.017 ns                ;
+; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.568 ns                ;
+; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.244 ns                ;
+; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.244 ns                ;
+; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.144 ns                ;
+; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.144 ns                ;
+; -2.030 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.769 ns                  ; 6.799 ns                ;
+; -2.030 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.539 ns                  ; 6.569 ns                ;
+; -2.026 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.563 ns                ;
+; -2.026 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.564 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.000 ns                  ; 6.022 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
+; -2.013 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.551 ns                ;
+; -2.010 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.987 ns                  ; 5.997 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
+; -2.002 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.986 ns                ;
+; -2.001 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.985 ns                ;
+; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[4]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
+; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[5]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
+; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[6]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
+; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
+; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 5.997 ns                ;
+; -1.997 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.981 ns                ;
+; -1.996 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.064 ns                  ; 6.060 ns                ;
+; -1.996 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.064 ns                  ; 6.060 ns                ;
+; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.106 ns                ;
+; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.106 ns                ;
+; -1.991 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.050 ns                  ; 6.041 ns                ;
+; -1.991 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.050 ns                  ; 6.041 ns                ;
+; -1.990 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.109 ns                ;
+; -1.990 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.109 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.106 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.106 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                ;                                                                                                                                                                                                                  ;                                                                          ;          ;                             ;                           ;                         ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                         ;
++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From                                                                                              ; To                                                                                                ; From Clock                                                             ; To Clock                                                               ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.825 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.783 ns                 ;
+; 0.827 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.785 ns                 ;
+; 0.827 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.785 ns                 ;
+; 0.828 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.786 ns                 ;
+; 0.828 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.786 ns                 ;
+; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
+; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
+; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
+; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
+; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
+; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
+; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
+; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
+; 0.831 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.789 ns                 ;
+; 0.831 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.789 ns                 ;
+; 0.832 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.790 ns                 ;
+; 0.833 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.791 ns                 ;
+; 1.185 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.143 ns                 ;
+; 1.353 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.311 ns                 ;
+; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.312 ns                 ;
+; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.311 ns                 ;
+; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.312 ns                 ;
+; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
+; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
+; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
+; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
+; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
+; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
+; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
+; 1.358 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.316 ns                 ;
+; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
+; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
+; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
+; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
+; 1.411 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.369 ns                 ;
+; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.370 ns                 ;
+; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.369 ns                 ;
+; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.370 ns                 ;
+; 1.414 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.372 ns                 ;
+; 1.414 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.372 ns                 ;
+; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
+; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
+; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
+; 1.416 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.374 ns                 ;
+; 1.416 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.373 ns                 ;
+; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
+; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
+; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
+; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
+; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.428 ns                 ;
+; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.427 ns                 ;
+; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.427 ns                 ;
+; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.428 ns                 ;
+; 1.472 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.430 ns                 ;
+; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
+; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
+; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
+; 1.474 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.432 ns                 ;
+; 1.474 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.431 ns                 ;
+; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
+; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
+; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
+; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
+; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.486 ns                 ;
+; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.485 ns                 ;
+; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.485 ns                 ;
+; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.486 ns                 ;
+; 1.530 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.488 ns                 ;
+; 1.531 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
+; 1.531 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
+; 1.532 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.489 ns                 ;
+; 1.532 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.489 ns                 ;
+; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
+; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
+; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
+; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
+; 1.586 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.543 ns                 ;
+; 1.586 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.543 ns                 ;
+; 1.587 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.544 ns                 ;
+; 1.588 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.546 ns                 ;
+; 1.589 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.547 ns                 ;
+; 1.589 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.547 ns                 ;
+; 1.590 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.547 ns                 ;
+; 1.590 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.547 ns                 ;
+; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
+; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
+; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
+; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
+; 1.644 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.601 ns                 ;
+; 1.644 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.601 ns                 ;
+; 1.645 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.602 ns                 ;
+; 1.646 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.604 ns                 ;
+; 1.647 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.605 ns                 ;
+; 1.648 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.605 ns                 ;
+; 1.648 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.605 ns                 ;
+; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
+; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
+; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
+; 1.650 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.607 ns                 ;
+; 1.689 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.647 ns                 ;
+; 1.702 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.659 ns                 ;
+; 1.702 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.659 ns                 ;
+; 1.703 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.660 ns                 ;
+; 1.704 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.662 ns                 ;
+; 1.706 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.663 ns                 ;
+; 1.706 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.663 ns                 ;
+; 1.707 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.665 ns                 ;
+; 1.707 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.665 ns                 ;
+; 1.708 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.665 ns                 ;
+; 1.708 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.665 ns                 ;
+; 1.743 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.701 ns                 ;
+; 1.760 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.717 ns                 ;
+; 1.760 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.717 ns                 ;
+; 1.761 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.718 ns                 ;
+; 1.764 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.721 ns                 ;
+; 1.764 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.721 ns                 ;
+; 1.765 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.723 ns                 ;
+; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
+; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
+; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
+; 1.801 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.759 ns                 ;
+; 1.818 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.775 ns                 ;
+; 1.819 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.776 ns                 ;
+; 1.822 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.779 ns                 ;
+; 1.822 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.779 ns                 ;
+; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
+; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
+; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
+; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
+; 1.861 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.819 ns                 ;
+; 1.876 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.833 ns                 ;
+; 1.877 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.834 ns                 ;
+; 1.880 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.837 ns                 ;
+; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
+; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
+; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
+; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
+; 1.915 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.873 ns                 ;
+; 1.935 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.892 ns                 ;
+; 1.938 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.895 ns                 ;
+; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
+; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
+; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
+; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
+; 1.976 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.934 ns                 ;
+; 1.993 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.950 ns                 ;
+; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
+; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
+; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
+; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
+; 2.034 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.992 ns                 ;
+; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
+; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
+; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
+; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
+; 2.091 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 2.049 ns                 ;
+; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
+; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
+; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
+; 2.147 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.104 ns                 ;
+; 2.172 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.129 ns                 ;
+; 2.172 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.129 ns                 ;
+; 2.209 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.166 ns                 ;
+; 2.230 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.187 ns                 ;
+; 2.263 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.220 ns                 ;
+; 2.325 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.282 ns                 ;
+; 2.380 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.337 ns                 ;
+; 2.443 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.400 ns                 ;
+; 2.501 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.458 ns                 ;
+; 2.559 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.516 ns                 ;
+; 2.617 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.574 ns                 ;
++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                           ;
++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From                                                                      ; To                                                                        ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.564 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.522 ns                 ;
+; 0.825 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.783 ns                 ;
+; 0.830 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
+; 0.852 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.810 ns                 ;
+; 0.955 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.913 ns                 ;
+; 1.357 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
+; 1.358 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.316 ns                 ;
+; 1.380 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.338 ns                 ;
+; 1.415 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
+; 1.416 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.374 ns                 ;
+; 1.473 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
+; 1.474 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.432 ns                 ;
+; 1.487 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.445 ns                 ;
+; 1.531 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
+; 1.545 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.503 ns                 ;
+; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
+; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
+; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
+; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                                                                               ; To                                                                                                                                                                                                                 ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR                                                                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1                                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5]                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5]                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK                                                                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK                                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                                                                      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                                                                                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY                                                                                               ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0]                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0]                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.547 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.505 ns                 ;
+; 0.549 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[19]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[3]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[3]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[12]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[13]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[7]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[6]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[18]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[21]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[1]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\ADRMARK_STROBES:DDATA_AM_LOCK                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|DDATA_AM                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[31]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.559 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7]                                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7]                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
+; 0.562 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD                                                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
+; 0.563 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
+; 0.569 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
+; 0.569 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11]                                                                      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11]                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
+; 0.571 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
+; 0.572 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_ADR                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_AM                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
+; 0.572 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[5]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
+; 0.573 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[0]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.577 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[3]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.535 ns                 ;
+; 0.580 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a2                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.538 ns                 ;
+; 0.582 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.540 ns                 ;
+; 0.584 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.542 ns                 ;
+; 0.591 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.549 ns                 ;
+; 0.592 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a2                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.550 ns                 ;
+; 0.593 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.551 ns                 ;
+; 0.608 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.566 ns                 ;
+; 0.609 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.567 ns                 ;
+; 0.610 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.568 ns                 ;
+; 0.610 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.568 ns                 ;
+; 0.614 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.572 ns                 ;
+; 0.614 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.572 ns                 ;
+; 0.616 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.574 ns                 ;
+; 0.616 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.574 ns                 ;
+; 0.625 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.583 ns                 ;
+; 0.626 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.584 ns                 ;
+; 0.627 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.585 ns                 ;
+; 0.667 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[23]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.625 ns                 ;
+; 0.668 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[9]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.626 ns                 ;
+; 0.669 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[15]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.627 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[12]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[21]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[23]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[6]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[10]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[11]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[16]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[17]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[4]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[4]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
+; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
+; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
+; 0.673 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.631 ns                 ;
+; 0.675 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.633 ns                 ;
+; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
+; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
+; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
+; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T1                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.679 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
+; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[4]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.639 ns                 ;
+; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
+; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T6                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
+; 0.681 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.639 ns                 ;
+; 0.683 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[14]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[15]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.641 ns                 ;
+; 0.683 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[6]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.641 ns                 ;
+; 0.689 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[2]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.689 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[0]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.649 ns                 ;
+; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.691 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.693 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[1]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.652 ns                 ;
+; 0.698 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; 0.330 ns                   ; 1.028 ns                 ;
+; 0.699 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[5]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
+; 0.700 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[1]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[1]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[5]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[8]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.704 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.662 ns                 ;
+; 0.704 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.662 ns                 ;
+; 0.706 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[1]                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[0]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.664 ns                 ;
+; 0.708 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[7]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.666 ns                 ;
+; 0.711 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[1]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.669 ns                 ;
+; 0.712 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.043 ns                  ; 0.669 ns                 ;
+; 0.712 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.670 ns                 ;
+; 0.714 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[6]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.673 ns                 ;
+; 0.715 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[3]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.673 ns                 ;
+; 0.715 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[2]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.673 ns                 ;
+; 0.720 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_PRES                                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[1]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.678 ns                 ;
+; 0.724 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.682 ns                 ;
+; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; 0.330 ns                   ; 1.056 ns                 ;
+; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[10]                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[8]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.685 ns                 ;
+; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_g[8]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.684 ns                 ;
+; 0.728 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[4]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.686 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                                                                                ;                                                                                                                                                                                                                    ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.531 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.443 ns                 ;
+; 0.536 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.403 ns                   ; 2.939 ns                 ;
+; 0.538 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.450 ns                 ;
+; 0.538 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.450 ns                 ;
+; 0.541 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.453 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.908 ns                   ; 1.459 ns                 ;
+; 0.556 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.503 ns                 ;
+; 0.557 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.960 ns                   ; 1.517 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.471 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.935 ns                   ; 1.494 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.583 ns                   ; 1.143 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.476 ns                 ;
+; 0.561 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.478 ns                 ;
+; 0.564 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.570 ns                   ; 1.134 ns                 ;
+; 0.567 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.514 ns                 ;
+; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.486 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.905 ns                   ; 1.478 ns                 ;
+; 0.576 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.929 ns                   ; 1.505 ns                 ;
+; 0.578 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.490 ns                 ;
+; 0.579 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.493 ns                 ;
+; 0.580 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.864 ns                 ;
+; 0.583 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.919 ns                   ; 1.502 ns                 ;
+; 0.583 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.584 ns                   ; 1.167 ns                 ;
+; 0.583 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.494 ns                 ;
+; 0.584 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.551 ns                 ;
+; 0.585 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.496 ns                 ;
+; 0.586 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.500 ns                 ;
+; 0.588 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.504 ns                 ;
+; 0.589 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.495 ns                 ;
+; 0.589 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.909 ns                   ; 1.498 ns                 ;
+; 0.590 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.504 ns                 ;
+; 0.591 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.875 ns                 ;
+; 0.592 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.507 ns                 ;
+; 0.592 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.929 ns                   ; 1.521 ns                 ;
+; 0.597 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.511 ns                 ;
+; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.517 ns                 ;
+; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.524 ns                 ;
+; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.521 ns                 ;
+; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.282 ns                   ; 1.882 ns                 ;
+; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.513 ns                 ;
+; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.926 ns                   ; 1.527 ns                 ;
+; 0.604 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.551 ns                 ;
+; 0.608 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.524 ns                 ;
+; 0.608 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.522 ns                 ;
+; 0.609 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.401 ns                   ; 3.010 ns                 ;
+; 0.610 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.894 ns                 ;
+; 0.611 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.528 ns                 ;
+; 0.613 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.527 ns                 ;
+; 0.613 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.530 ns                 ;
+; 0.613 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.580 ns                 ;
+; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.526 ns                 ;
+; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.526 ns                 ;
+; 0.614 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.531 ns                 ;
+; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.561 ns                 ;
+; 0.614 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.531 ns                 ;
+; 0.617 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.534 ns                 ;
+; 0.618 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.962 ns                   ; 1.580 ns                 ;
+; 0.619 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.540 ns                 ;
+; 0.620 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.541 ns                 ;
+; 0.620 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.534 ns                 ;
+; 0.620 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.541 ns                 ;
+; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.542 ns                 ;
+; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.539 ns                 ;
+; 0.622 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.546 ns                 ;
+; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.597 ns                   ; 1.219 ns                 ;
+; 0.622 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.528 ns                 ;
+; 0.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.537 ns                 ;
+; 0.623 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.544 ns                 ;
+; 0.623 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.283 ns                   ; 1.906 ns                 ;
+; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.547 ns                 ;
+; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.550 ns                 ;
+; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.550 ns                 ;
+; 0.627 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.548 ns                 ;
+; 0.627 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.551 ns                 ;
+; 0.627 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.544 ns                 ;
+; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.543 ns                 ;
+; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.543 ns                 ;
+; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.912 ns                 ;
+; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.545 ns                 ;
+; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.541 ns                 ;
+; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.550 ns                 ;
+; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.550 ns                 ;
+; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.553 ns                 ;
+; 0.630 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.544 ns                 ;
+; 0.630 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.554 ns                 ;
+; 0.631 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.545 ns                 ;
+; 0.632 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.588 ns                   ; 1.220 ns                 ;
+; 0.633 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.546 ns                 ;
+; 0.633 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.549 ns                 ;
+; 0.636 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.909 ns                   ; 1.545 ns                 ;
+; 0.637 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.551 ns                 ;
+; 0.637 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.551 ns                 ;
+; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.555 ns                 ;
+; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.549 ns                 ;
+; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.552 ns                 ;
+; 0.639 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.556 ns                 ;
+; 0.639 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.555 ns                 ;
+; 0.641 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.558 ns                 ;
+; 0.641 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.555 ns                 ;
+; 0.642 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.558 ns                 ;
+; 0.643 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.557 ns                 ;
+; 0.644 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.558 ns                 ;
+; 0.644 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.611 ns                 ;
+; 0.645 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.557 ns                 ;
+; 0.646 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.560 ns                 ;
+; 0.646 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.586 ns                   ; 1.232 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.561 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
+; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.907 ns                   ; 1.555 ns                 ;
+; 0.648 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.577 ns                   ; 1.225 ns                 ;
+; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.560 ns                 ;
+; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.907 ns                   ; 1.555 ns                 ;
+; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.562 ns                 ;
+; 0.649 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.566 ns                 ;
+; 0.649 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.567 ns                 ;
+; 0.649 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.563 ns                 ;
+; 0.650 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.568 ns                 ;
+; 0.650 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.570 ns                   ; 1.220 ns                 ;
+; 0.651 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.577 ns                   ; 1.228 ns                 ;
+; 0.651 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.404 ns                   ; 3.055 ns                 ;
+; 0.652 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.576 ns                 ;
+; 0.653 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.567 ns                 ;
+; 0.653 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.567 ns                 ;
+; 0.655 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.602 ns                 ;
+; 0.656 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.585 ns                   ; 1.241 ns                 ;
+; 0.656 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.282 ns                   ; 1.938 ns                 ;
+; 0.657 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.581 ns                 ;
+; 0.657 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.571 ns                 ;
+; 0.658 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.905 ns                   ; 1.563 ns                 ;
+; 0.658 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.572 ns                 ;
+; 0.659 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.565 ns                 ;
+; 0.660 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.627 ns                 ;
+; 0.661 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.608 ns                 ;
+; 0.661 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.575 ns                 ;
+; 0.662 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.577 ns                 ;
+; 0.662 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.574 ns                 ;
+; 0.662 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.576 ns                 ;
+; 0.662 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.580 ns                 ;
+; 0.663 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.579 ns                 ;
+; 0.663 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.610 ns                 ;
+; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.575 ns                 ;
+; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.930 ns                   ; 1.594 ns                 ;
+; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.570 ns                 ;
+; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.584 ns                 ;
+; 0.665 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.582 ns                 ;
+; 0.665 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.579 ns                 ;
+; 0.665 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.578 ns                 ;
+; 0.666 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.580 ns                 ;
+; 0.666 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.580 ns                 ;
+; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.581 ns                 ;
+; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.581 ns                 ;
+; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.587 ns                 ;
+; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.580 ns                 ;
+; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.634 ns                 ;
+; 0.669 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.585 ns                   ; 1.254 ns                 ;
+; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.582 ns                 ;
+; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.953 ns                 ;
+; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.636 ns                 ;
+; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.583 ns                 ;
+; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.584 ns                 ;
+; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.587 ns                 ;
+; 0.671 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.586 ns                 ;
+; 0.671 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.908 ns                   ; 1.579 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                    ; To                                                                                                                                                      ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                          ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[75]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[99]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[65]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[81]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[5]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[87]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[105]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[110]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[94]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[28]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[124]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[123]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[66]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[126]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[4]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[7]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe19a[0]                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0]                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[6]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[102]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[22]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[86]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[118]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[67]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[83]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C6                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[125]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[92]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[73]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[121]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.553 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[1]                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_DDR_SYNC                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
+; 0.554 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[120]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.512 ns                 ;
+; 0.554 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.512 ns                 ;
+; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
+; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
+; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
+; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[42]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
+; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[56]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[32]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
+; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
+; 0.561 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[39]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.519 ns                 ;
+; 0.561 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.519 ns                 ;
+; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
+; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
+; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
+; 0.563 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[52]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
+; 0.563 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[57]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
+; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
+; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[31]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[31]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
+; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
+; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.528 ns                 ;
+; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.528 ns                 ;
+; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
+; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
+; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
+; 0.572 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]                                                                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[84]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[84]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[95]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[95]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
+; 0.574 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.532 ns                 ;
+; 0.582 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[70]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[70]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.540 ns                 ;
+; 0.583 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.541 ns                 ;
+; 0.592 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.550 ns                 ;
+; 0.593 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a1                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.551 ns                 ;
+; 0.595 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.553 ns                 ;
+; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.559 ns                 ;
+; 0.604 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.562 ns                 ;
+; 0.605 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.563 ns                 ;
+; 0.605 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.563 ns                 ;
+; 0.643 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.340 ns                   ; 0.983 ns                 ;
+; 0.647 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.332 ns                   ; 0.979 ns                 ;
+; 0.654 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 0.988 ns                 ;
+; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.332 ns                   ; 1.002 ns                 ;
+; 0.671 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
+; 0.673 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 1.007 ns                 ;
+; 0.675 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[26]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[90]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.633 ns                 ;
+; 0.676 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C2                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.634 ns                 ;
+; 0.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[13]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
+; 0.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[24]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[88]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
+; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[97]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
+; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[21]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[85]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
+; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[4]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[100]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
+; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
+; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
+; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[29]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[93]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
+; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[18]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[114]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
+; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[3]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
+; 0.681 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[2]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[98]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.639 ns                 ;
+; 0.687 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.645 ns                 ;
+; 0.687 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.645 ns                 ;
+; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
+; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
+; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
+; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
+; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
+; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[41]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[49]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[44]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[33]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[61]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.690 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
+; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[43]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[54]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[91]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.649 ns                 ;
+; 0.692 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_N5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
+; 0.693 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.651 ns                 ;
+; 0.694 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 1.028 ns                 ;
+; 0.695 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[106]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[13]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[45]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[15]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[15]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[13]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[109]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.655 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[14]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[14]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
+; 0.698 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 0.657 ns                 ;
+; 0.699 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
+; 0.699 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[78]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[78]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
+; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[21]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[53]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[82]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.700 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7W                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8W                                                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
+; 0.701 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R2                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T4W                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T5W                                                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
+; 0.703 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.661 ns                 ;
+; 0.703 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.661 ns                 ;
+; 0.704 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.031 ns                 ;
+; 0.705 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.341 ns                   ; 1.046 ns                 ;
+; 0.706 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.033 ns                 ;
+; 0.707 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[51]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.665 ns                 ;
+; 0.710 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 0.669 ns                 ;
+; 0.712 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.669 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                     ;                                                                                                                                                         ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From                                                                                                                             ; To                                                                                                                                ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
+; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
+; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
+; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
+; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
+; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
+; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
+; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
+; 4.465 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.636 ns                 ;
+; 4.466 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.637 ns                 ;
+; 4.467 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.638 ns                 ;
+; 4.468 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.639 ns                 ;
++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                               ;
++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack ; From                                              ; To                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 1.825 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.508 ns                 ;
+; 1.827 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.510 ns                 ;
+; 1.953 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.636 ns                 ;
+; 1.954 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.637 ns                 ;
+; 2.134 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.315 ns                  ; 0.819 ns                 ;
++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'                                                                                                                                                                                                                                                                                                                                                                                                            ;
++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                   ; To                                                                                                                                  ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 3.263 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.570 ns                 ;
+; 3.273 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.580 ns                 ;
+; 3.460 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.363 ns                 ;
+; 3.511 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.818 ns                 ;
+; 3.539 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 1.845 ns                 ;
+; 3.543 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 1.857 ns                 ;
+; 3.548 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 1.860 ns                 ;
+; 3.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 1.874 ns                 ;
+; 3.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 1.882 ns                 ;
+; 3.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.667 ns                  ; 1.906 ns                 ;
+; 3.609 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 1.937 ns                 ;
+; 3.618 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 1.929 ns                 ;
+; 3.637 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 1.952 ns                 ;
+; 3.656 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 1.959 ns                 ;
+; 3.660 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 1.974 ns                 ;
+; 3.674 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 1.983 ns                 ;
+; 3.686 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.692 ns                  ; 1.994 ns                 ;
+; 3.719 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.024 ns                 ;
+; 3.721 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 2.030 ns                 ;
+; 3.730 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.698 ns                  ; 2.032 ns                 ;
+; 3.731 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.634 ns                 ;
+; 3.737 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.042 ns                 ;
+; 3.740 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.664 ns                  ; 2.076 ns                 ;
+; 3.745 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.668 ns                  ; 2.077 ns                 ;
+; 3.754 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.059 ns                 ;
+; 3.769 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.672 ns                 ;
+; 3.774 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 2.077 ns                 ;
+; 3.776 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 2.091 ns                 ;
+; 3.777 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.698 ns                  ; 2.079 ns                 ;
+; 3.778 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 2.085 ns                 ;
+; 3.780 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.084 ns                 ;
+; 3.781 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.684 ns                  ; 2.097 ns                 ;
+; 3.784 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.089 ns                 ;
+; 3.784 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.684 ns                  ; 2.100 ns                 ;
+; 3.786 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.097 ns                 ;
+; 3.792 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 3.693 ns                 ;
+; 3.794 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.692 ns                  ; 2.102 ns                 ;
+; 3.796 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.107 ns                 ;
+; 3.811 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.125 ns                 ;
+; 3.814 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 2.126 ns                 ;
+; 3.819 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 2.122 ns                 ;
+; 3.836 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.141 ns                 ;
+; 3.838 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 3.735 ns                 ;
+; 3.839 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.101 ns                  ; 3.738 ns                 ;
+; 3.855 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.755 ns                 ;
+; 3.866 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 3.763 ns                 ;
+; 3.899 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 2.205 ns                 ;
+; 3.902 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.203 ns                 ;
+; 3.906 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.722 ns                  ; 2.184 ns                 ;
+; 3.916 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 3.812 ns                 ;
+; 3.920 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.234 ns                 ;
+; 3.932 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.246 ns                 ;
+; 3.933 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.613 ns                  ; 2.320 ns                 ;
+; 3.935 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.239 ns                 ;
+; 3.936 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 3.837 ns                 ;
+; 3.944 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 2.250 ns                 ;
+; 3.951 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.851 ns                 ;
+; 3.973 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.101 ns                  ; 3.872 ns                 ;
+; 3.979 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.283 ns                 ;
+; 3.989 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 2.296 ns                 ;
+; 4.004 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.904 ns                 ;
+; 4.029 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 3.931 ns                 ;
+; 4.042 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.683 ns                  ; 2.359 ns                 ;
+; 4.043 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 2.358 ns                 ;
+; 4.043 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.344 ns                 ;
+; 4.048 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.352 ns                 ;
+; 4.078 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.978 ns                 ;
+; 4.084 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 3.980 ns                 ;
+; 4.096 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 3.998 ns                 ;
+; 4.110 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 4.006 ns                 ;
+; 4.112 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.371 ns                 ;
+; 4.112 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.423 ns                 ;
+; 4.115 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.012 ns                 ;
+; 4.117 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.014 ns                 ;
+; 4.132 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 4.035 ns                 ;
+; 4.168 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.429 ns                 ;
+; 4.169 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.470 ns                 ;
+; 4.185 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.454 ns                 ;
+; 4.187 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.723 ns                  ; 2.464 ns                 ;
+; 4.195 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.431 ns                 ;
+; 4.196 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.713 ns                  ; 2.483 ns                 ;
+; 4.201 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 2.447 ns                 ;
+; 4.221 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.714 ns                  ; 2.507 ns                 ;
+; 4.231 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.614 ns                  ; 2.617 ns                 ;
+; 4.232 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.133 ns                 ;
+; 4.232 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.674 ns                  ; 2.558 ns                 ;
+; 4.235 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.132 ns                 ;
+; 4.236 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.102 ns                  ; 4.134 ns                 ;
+; 4.239 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.673 ns                  ; 2.566 ns                 ;
+; 4.243 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.479 ns                 ;
+; 4.249 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.669 ns                  ; 2.580 ns                 ;
+; 4.251 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.152 ns                 ;
+; 4.269 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.170 ns                 ;
+; 4.283 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.185 ns                 ;
+; 4.286 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.188 ns                 ;
+; 4.296 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.670 ns                  ; 2.626 ns                 ;
+; 4.313 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.666 ns                  ; 2.647 ns                 ;
+; 4.314 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 2.623 ns                 ;
+; 4.331 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 2.596 ns                 ;
+; 4.333 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.145 ns                  ; 4.188 ns                 ;
+; 4.343 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.145 ns                  ; 4.198 ns                 ;
+; 4.347 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.665 ns                  ; 2.682 ns                 ;
+; 4.352 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.254 ns                 ;
+; 4.352 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 4.252 ns                 ;
+; 4.362 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.717 ns                  ; 2.645 ns                 ;
+; 4.367 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.608 ns                 ;
+; 4.376 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.635 ns                 ;
+; 4.384 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.102 ns                  ; 4.282 ns                 ;
+; 4.406 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.615 ns                  ; 2.791 ns                 ;
+; 4.409 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.645 ns                 ;
+; 4.410 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.646 ns                 ;
+; 4.411 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.159 ns                  ; 4.252 ns                 ;
+; 4.417 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.746 ns                  ; 2.671 ns                 ;
+; 4.425 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 4.325 ns                 ;
+; 4.431 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.670 ns                  ; 2.761 ns                 ;
+; 4.434 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.695 ns                 ;
+; 4.440 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.685 ns                 ;
+; 4.450 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.719 ns                 ;
+; 4.475 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.734 ns                 ;
+; 4.477 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 2.805 ns                 ;
+; 4.478 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.730 ns                  ; 2.748 ns                 ;
+; 4.480 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.757 ns                  ; 2.723 ns                 ;
+; 4.485 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.736 ns                 ;
+; 4.486 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 2.814 ns                 ;
+; 4.497 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.351 ns                 ;
+; 4.498 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.329 ns                 ;
+; 4.527 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 2.773 ns                 ;
+; 4.530 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.791 ns                 ;
+; 4.555 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 2.804 ns                 ;
+; 4.556 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.163 ns                  ; 4.393 ns                 ;
+; 4.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.818 ns                 ;
+; 4.587 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.615 ns                  ; 2.972 ns                 ;
+; 4.597 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.429 ns                 ;
+; 4.600 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 2.865 ns                 ;
+; 4.601 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.852 ns                 ;
+; 4.601 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.433 ns                 ;
+; 4.613 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.674 ns                  ; 2.939 ns                 ;
+; 4.614 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.855 ns                 ;
+; 4.618 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 2.867 ns                 ;
+; 4.623 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.159 ns                  ; 4.464 ns                 ;
+; 4.626 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.742 ns                  ; 2.884 ns                 ;
+; 4.630 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.740 ns                  ; 2.890 ns                 ;
+; 4.633 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.874 ns                 ;
+; 4.636 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.150 ns                  ; 4.486 ns                 ;
+; 4.637 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.906 ns                 ;
+; 4.660 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.911 ns                 ;
+; 4.670 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.517 ns                 ;
+; 4.671 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.164 ns                  ; 4.507 ns                 ;
+; 4.676 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.912 ns                 ;
+; 4.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.745 ns                  ; 2.932 ns                 ;
+; 4.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.913 ns                 ;
+; 4.686 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.746 ns                  ; 2.940 ns                 ;
+; 4.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.726 ns                  ; 2.964 ns                 ;
+; 4.697 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.529 ns                 ;
+; 4.699 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.874 ns                  ; 1.825 ns                 ;
+; 4.704 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.949 ns                 ;
+; 4.709 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.664 ns                  ; 3.045 ns                 ;
+; 4.722 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.991 ns                 ;
+; 4.749 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.603 ns                 ;
+; 4.753 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.004 ns                 ;
+; 4.780 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.155 ns                  ; 4.625 ns                 ;
+; 4.787 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.156 ns                  ; 4.631 ns                 ;
+; 4.791 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.638 ns                 ;
+; 4.805 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.730 ns                  ; 3.075 ns                 ;
+; 4.809 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.640 ns                 ;
+; 4.823 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 3.072 ns                 ;
+; 4.825 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.163 ns                  ; 4.662 ns                 ;
+; 4.840 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.712 ns                  ; 3.128 ns                 ;
+; 4.844 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 3.109 ns                 ;
+; 4.844 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.155 ns                  ; 4.689 ns                 ;
+; 4.845 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.154 ns                  ; 4.691 ns                 ;
+; 4.846 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.700 ns                 ;
+; 4.863 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 3.108 ns                 ;
+; 4.869 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.131 ns                 ;
+; 4.871 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.122 ns                 ;
+; 4.878 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.725 ns                 ;
+; 4.881 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.712 ns                 ;
+; 4.885 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 3.134 ns                 ;
+; 4.888 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.156 ns                  ; 4.732 ns                 ;
+; 4.892 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.147 ns                  ; 4.745 ns                 ;
+; 4.892 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.742 ns                  ; 3.150 ns                 ;
+; 4.896 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.740 ns                  ; 3.156 ns                 ;
+; 4.906 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 3.175 ns                 ;
+; 4.916 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.866 ns                  ; 2.050 ns                 ;
+; 4.916 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.151 ns                  ; 4.765 ns                 ;
+; 4.924 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.175 ns                 ;
+; 4.942 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.745 ns                  ; 3.197 ns                 ;
+; 4.979 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.160 ns                  ; 4.819 ns                 ;
+; 5.007 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 3.253 ns                 ;
+; 5.009 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 3.250 ns                 ;
+; 5.013 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.726 ns                  ; 3.287 ns                 ;
+; 5.029 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.164 ns                  ; 4.865 ns                 ;
+; 5.047 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 3.308 ns                 ;
+; 5.088 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.869 ns                  ; 2.219 ns                 ;
+; 5.096 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.933 ns                  ; 2.163 ns                 ;
+; 5.124 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.154 ns                  ; 4.970 ns                 ;
+; 5.133 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.395 ns                 ;
+; 5.143 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.722 ns                  ; 3.421 ns                 ;
+; 5.166 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.428 ns                 ;
+; 5.205 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.720 ns                  ; 3.485 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                    ;                                                                                                                                     ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'                                                                                                                                                                                                                                                                                                                                                        ;
++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                            ; To                                                                     ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
+; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
+; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
+; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
+; 2.679 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.447 ns                  ; 2.232 ns                 ;
+; 2.684 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.447 ns                  ; 2.237 ns                 ;
+; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
+; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
+; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
+; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
+; 2.714 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.264 ns                 ;
+; 2.714 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.264 ns                 ;
+; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
+; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
+; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
+; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
+; 2.769 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.319 ns                 ;
+; 2.769 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.319 ns                 ;
+; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
+; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
+; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
+; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
+; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
+; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
+; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
+; 2.948 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -1.264 ns                  ; -1.316 ns                  ; 1.632 ns                 ;
+; 3.033 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.589 ns                 ;
+; 3.033 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.589 ns                 ;
+; 3.088 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.042 ns                  ; 3.046 ns                 ;
+; 3.100 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.656 ns                 ;
+; 3.146 ns                                ; FB_ALE                                                                          ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.316 ns                  ; 2.830 ns                 ;
+; 6.237 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.309 ns                  ; 1.928 ns                 ;
+; 6.282 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.386 ns                  ; 1.896 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
+; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
+; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
+; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
+; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
+; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
+; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
+; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
+; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
+; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
+; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
+; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
+; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
+; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
+; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
+; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
+; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
+; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
+; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
+; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
+; 7.218 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.355 ns                  ; 2.863 ns                 ;
+; 7.413 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.650 ns                  ; 2.763 ns                 ;
+; 7.427 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.650 ns                  ; 2.777 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
+; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
+; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
+; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
+; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
+; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
+; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
+; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
+; 7.686 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.470 ns                  ; 3.216 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                             ;                                                                        ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
+; 1.487 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.443 ns                 ;
+; 1.492 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.447 ns                   ; 2.939 ns                 ;
+; 1.494 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.450 ns                 ;
+; 1.494 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.450 ns                 ;
+; 1.497 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.453 ns                 ;
+; 1.507 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.048 ns                  ; 1.459 ns                 ;
+; 1.512 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.503 ns                 ;
+; 1.513 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.004 ns                   ; 1.517 ns                 ;
+; 1.515 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.471 ns                 ;
+; 1.515 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.021 ns                  ; 1.494 ns                 ;
+; 1.516 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.373 ns                  ; 1.143 ns                 ;
+; 1.516 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.476 ns                 ;
+; 1.517 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.478 ns                 ;
+; 1.520 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.386 ns                  ; 1.134 ns                 ;
+; 1.523 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.514 ns                 ;
+; 1.526 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.486 ns                 ;
+; 1.529 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.051 ns                  ; 1.478 ns                 ;
+; 1.532 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.027 ns                  ; 1.505 ns                 ;
+; 1.534 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.490 ns                 ;
+; 1.535 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.493 ns                 ;
+; 1.536 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.864 ns                 ;
+; 1.539 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.037 ns                  ; 1.502 ns                 ;
+; 1.539 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.372 ns                  ; 1.167 ns                 ;
+; 1.539 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.494 ns                 ;
+; 1.540 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.551 ns                 ;
+; 1.541 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.496 ns                 ;
+; 1.542 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.500 ns                 ;
+; 1.544 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.504 ns                 ;
+; 1.545 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.495 ns                 ;
+; 1.545 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.047 ns                  ; 1.498 ns                 ;
+; 1.546 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.504 ns                 ;
+; 1.547 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.875 ns                 ;
+; 1.548 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.507 ns                 ;
+; 1.548 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.027 ns                  ; 1.521 ns                 ;
+; 1.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.511 ns                 ;
+; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.517 ns                 ;
+; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.524 ns                 ;
+; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.521 ns                 ;
+; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.326 ns                   ; 1.882 ns                 ;
+; 1.557 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.513 ns                 ;
+; 1.557 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.030 ns                  ; 1.527 ns                 ;
+; 1.560 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.551 ns                 ;
+; 1.564 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.524 ns                 ;
+; 1.564 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.522 ns                 ;
+; 1.565 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.445 ns                   ; 3.010 ns                 ;
+; 1.566 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.894 ns                 ;
+; 1.567 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.528 ns                 ;
+; 1.569 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.527 ns                 ;
+; 1.569 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.530 ns                 ;
+; 1.569 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.580 ns                 ;
+; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.526 ns                 ;
+; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.526 ns                 ;
+; 1.570 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.531 ns                 ;
+; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.561 ns                 ;
+; 1.570 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.531 ns                 ;
+; 1.573 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.534 ns                 ;
+; 1.574 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.006 ns                   ; 1.580 ns                 ;
+; 1.575 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.540 ns                 ;
+; 1.576 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.541 ns                 ;
+; 1.576 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.534 ns                 ;
+; 1.576 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.541 ns                 ;
+; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.542 ns                 ;
+; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.539 ns                 ;
+; 1.578 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.546 ns                 ;
+; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.359 ns                  ; 1.219 ns                 ;
+; 1.578 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.528 ns                 ;
+; 1.579 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.537 ns                 ;
+; 1.579 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.544 ns                 ;
+; 1.579 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.906 ns                 ;
+; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.547 ns                 ;
+; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.550 ns                 ;
+; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.550 ns                 ;
+; 1.583 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.548 ns                 ;
+; 1.583 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.551 ns                 ;
+; 1.583 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.544 ns                 ;
+; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.543 ns                 ;
+; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.543 ns                 ;
+; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.912 ns                 ;
+; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.545 ns                 ;
+; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.541 ns                 ;
+; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.550 ns                 ;
+; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.550 ns                 ;
+; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.553 ns                 ;
+; 1.586 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.544 ns                 ;
+; 1.586 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.554 ns                 ;
+; 1.587 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.545 ns                 ;
+; 1.588 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.368 ns                  ; 1.220 ns                 ;
+; 1.589 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.546 ns                 ;
+; 1.589 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.549 ns                 ;
+; 1.592 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.047 ns                  ; 1.545 ns                 ;
+; 1.593 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.551 ns                 ;
+; 1.593 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.551 ns                 ;
+; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.555 ns                 ;
+; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.549 ns                 ;
+; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.552 ns                 ;
+; 1.595 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.556 ns                 ;
+; 1.595 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.555 ns                 ;
+; 1.597 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.558 ns                 ;
+; 1.597 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.555 ns                 ;
+; 1.598 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.558 ns                 ;
+; 1.599 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.557 ns                 ;
+; 1.600 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.558 ns                 ;
+; 1.600 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.611 ns                 ;
+; 1.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.557 ns                 ;
+; 1.602 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.560 ns                 ;
+; 1.602 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.370 ns                  ; 1.232 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.561 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
+; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.049 ns                  ; 1.555 ns                 ;
+; 1.604 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.379 ns                  ; 1.225 ns                 ;
+; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.560 ns                 ;
+; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.049 ns                  ; 1.555 ns                 ;
+; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.562 ns                 ;
+; 1.605 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.566 ns                 ;
+; 1.605 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.567 ns                 ;
+; 1.605 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.563 ns                 ;
+; 1.606 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.568 ns                 ;
+; 1.606 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.386 ns                  ; 1.220 ns                 ;
+; 1.607 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.379 ns                  ; 1.228 ns                 ;
+; 1.607 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.448 ns                   ; 3.055 ns                 ;
+; 1.608 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.576 ns                 ;
+; 1.609 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.567 ns                 ;
+; 1.609 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.567 ns                 ;
+; 1.611 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.602 ns                 ;
+; 1.612 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.371 ns                  ; 1.241 ns                 ;
+; 1.612 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.326 ns                   ; 1.938 ns                 ;
+; 1.613 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.581 ns                 ;
+; 1.613 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.571 ns                 ;
+; 1.614 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.051 ns                  ; 1.563 ns                 ;
+; 1.614 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.572 ns                 ;
+; 1.615 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.565 ns                 ;
+; 1.616 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.627 ns                 ;
+; 1.617 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.608 ns                 ;
+; 1.617 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.575 ns                 ;
+; 1.618 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.577 ns                 ;
+; 1.618 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.574 ns                 ;
+; 1.618 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.576 ns                 ;
+; 1.618 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.580 ns                 ;
+; 1.619 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.579 ns                 ;
+; 1.619 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.610 ns                 ;
+; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.575 ns                 ;
+; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.026 ns                  ; 1.594 ns                 ;
+; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.570 ns                 ;
+; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.584 ns                 ;
+; 1.621 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.582 ns                 ;
+; 1.621 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.579 ns                 ;
+; 1.621 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.578 ns                 ;
+; 1.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.580 ns                 ;
+; 1.622 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.580 ns                 ;
+; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.581 ns                 ;
+; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.581 ns                 ;
+; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.587 ns                 ;
+; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.580 ns                 ;
+; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.634 ns                 ;
+; 1.625 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.371 ns                  ; 1.254 ns                 ;
+; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.582 ns                 ;
+; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.953 ns                 ;
+; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.636 ns                 ;
+; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.583 ns                 ;
+; 1.626 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.584 ns                 ;
+; 1.626 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.587 ns                 ;
+; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.586 ns                 ;
+; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.048 ns                  ; 1.579 ns                 ;
+; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.585 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                            ;                            ;                          ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'CLK33M'                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
+; 0.298 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.443 ns                 ;
+; 0.303 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.636 ns                   ; 2.939 ns                 ;
+; 0.305 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.450 ns                 ;
+; 0.305 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.450 ns                 ;
+; 0.308 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.453 ns                 ;
+; 0.318 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.141 ns                   ; 1.459 ns                 ;
+; 0.323 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.503 ns                 ;
+; 0.324 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.193 ns                   ; 1.517 ns                 ;
+; 0.326 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.471 ns                 ;
+; 0.326 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.168 ns                   ; 1.494 ns                 ;
+; 0.327 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.816 ns                   ; 1.143 ns                 ;
+; 0.327 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.476 ns                 ;
+; 0.328 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.478 ns                 ;
+; 0.331 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.803 ns                   ; 1.134 ns                 ;
+; 0.334 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.514 ns                 ;
+; 0.337 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.486 ns                 ;
+; 0.340 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.138 ns                   ; 1.478 ns                 ;
+; 0.343 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.162 ns                   ; 1.505 ns                 ;
+; 0.345 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.490 ns                 ;
+; 0.346 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.493 ns                 ;
+; 0.347 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.864 ns                 ;
+; 0.350 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.152 ns                   ; 1.502 ns                 ;
+; 0.350 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.817 ns                   ; 1.167 ns                 ;
+; 0.350 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.494 ns                 ;
+; 0.351 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.551 ns                 ;
+; 0.352 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.496 ns                 ;
+; 0.353 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.500 ns                 ;
+; 0.355 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.504 ns                 ;
+; 0.356 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.495 ns                 ;
+; 0.356 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.142 ns                   ; 1.498 ns                 ;
+; 0.357 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.504 ns                 ;
+; 0.358 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.875 ns                 ;
+; 0.359 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.507 ns                 ;
+; 0.359 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.162 ns                   ; 1.521 ns                 ;
+; 0.364 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.511 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.517 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.524 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.521 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.515 ns                   ; 1.882 ns                 ;
+; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.513 ns                 ;
+; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.159 ns                   ; 1.527 ns                 ;
+; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.551 ns                 ;
+; 0.375 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.524 ns                 ;
+; 0.375 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.522 ns                 ;
+; 0.376 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.634 ns                   ; 3.010 ns                 ;
+; 0.377 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.894 ns                 ;
+; 0.378 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.528 ns                 ;
+; 0.380 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.527 ns                 ;
+; 0.380 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.530 ns                 ;
+; 0.380 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.580 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.526 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.526 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.531 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.561 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.531 ns                 ;
+; 0.384 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.534 ns                 ;
+; 0.385 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.195 ns                   ; 1.580 ns                 ;
+; 0.386 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.540 ns                 ;
+; 0.387 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.541 ns                 ;
+; 0.387 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.534 ns                 ;
+; 0.387 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.541 ns                 ;
+; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.542 ns                 ;
+; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.539 ns                 ;
+; 0.389 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.546 ns                 ;
+; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.830 ns                   ; 1.219 ns                 ;
+; 0.389 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.528 ns                 ;
+; 0.390 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.537 ns                 ;
+; 0.390 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.544 ns                 ;
+; 0.390 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.516 ns                   ; 1.906 ns                 ;
+; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.547 ns                 ;
+; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.550 ns                 ;
+; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.550 ns                 ;
+; 0.394 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.548 ns                 ;
+; 0.394 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.551 ns                 ;
+; 0.394 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.544 ns                 ;
+; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.543 ns                 ;
+; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.543 ns                 ;
+; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.912 ns                 ;
+; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.545 ns                 ;
+; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.541 ns                 ;
+; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.550 ns                 ;
+; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.550 ns                 ;
+; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.553 ns                 ;
+; 0.397 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.544 ns                 ;
+; 0.397 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.554 ns                 ;
+; 0.398 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.545 ns                 ;
+; 0.399 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.821 ns                   ; 1.220 ns                 ;
+; 0.400 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.546 ns                 ;
+; 0.400 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.549 ns                 ;
+; 0.403 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.142 ns                   ; 1.545 ns                 ;
+; 0.404 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.551 ns                 ;
+; 0.404 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.551 ns                 ;
+; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.555 ns                 ;
+; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.549 ns                 ;
+; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.552 ns                 ;
+; 0.406 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.556 ns                 ;
+; 0.406 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.555 ns                 ;
+; 0.408 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.558 ns                 ;
+; 0.408 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.555 ns                 ;
+; 0.409 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.558 ns                 ;
+; 0.410 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.557 ns                 ;
+; 0.411 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.558 ns                 ;
+; 0.411 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.611 ns                 ;
+; 0.412 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.557 ns                 ;
+; 0.413 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.560 ns                 ;
+; 0.413 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.819 ns                   ; 1.232 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.561 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
+; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.140 ns                   ; 1.555 ns                 ;
+; 0.415 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.810 ns                   ; 1.225 ns                 ;
+; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.560 ns                 ;
+; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.140 ns                   ; 1.555 ns                 ;
+; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.562 ns                 ;
+; 0.416 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.566 ns                 ;
+; 0.416 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.567 ns                 ;
+; 0.416 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.563 ns                 ;
+; 0.417 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.568 ns                 ;
+; 0.417 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.803 ns                   ; 1.220 ns                 ;
+; 0.418 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.810 ns                   ; 1.228 ns                 ;
+; 0.418 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.637 ns                   ; 3.055 ns                 ;
+; 0.419 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.576 ns                 ;
+; 0.420 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.567 ns                 ;
+; 0.420 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.567 ns                 ;
+; 0.422 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.602 ns                 ;
+; 0.423 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.818 ns                   ; 1.241 ns                 ;
+; 0.423 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.515 ns                   ; 1.938 ns                 ;
+; 0.424 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.581 ns                 ;
+; 0.424 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.571 ns                 ;
+; 0.425 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.138 ns                   ; 1.563 ns                 ;
+; 0.425 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.572 ns                 ;
+; 0.426 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.565 ns                 ;
+; 0.427 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.627 ns                 ;
+; 0.428 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.608 ns                 ;
+; 0.428 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.575 ns                 ;
+; 0.429 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.577 ns                 ;
+; 0.429 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.574 ns                 ;
+; 0.429 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.576 ns                 ;
+; 0.429 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.580 ns                 ;
+; 0.430 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.579 ns                 ;
+; 0.430 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.610 ns                 ;
+; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.575 ns                 ;
+; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.163 ns                   ; 1.594 ns                 ;
+; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.570 ns                 ;
+; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.584 ns                 ;
+; 0.432 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.582 ns                 ;
+; 0.432 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.579 ns                 ;
+; 0.432 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.578 ns                 ;
+; 0.433 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.580 ns                 ;
+; 0.433 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.580 ns                 ;
+; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.581 ns                 ;
+; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.581 ns                 ;
+; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.587 ns                 ;
+; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.580 ns                 ;
+; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.634 ns                 ;
+; 0.436 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.818 ns                   ; 1.254 ns                 ;
+; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.582 ns                 ;
+; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.953 ns                 ;
+; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.636 ns                 ;
+; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.583 ns                 ;
+; 0.437 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.584 ns                 ;
+; 0.437 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.587 ns                 ;
+; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.586 ns                 ;
+; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.141 ns                   ; 1.579 ns                 ;
+; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.585 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;            ;          ;                            ;                            ;                          ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Hold: 'MAIN_CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+; -3.786 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.716 ns                   ; 1.930 ns                 ;
+; -3.611 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.756 ns                   ; 2.145 ns                 ;
+; -3.448 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.709 ns                   ; 2.261 ns                 ;
+; -3.293 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[0]                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.327 ns                   ; 1.034 ns                 ;
+; -3.012 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 2.694 ns                 ;
+; -2.912 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 2.794 ns                 ;
+; -2.048 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.740 ns                   ; 1.692 ns                 ;
+; -1.996 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.143 ns                   ; 1.147 ns                 ;
+; -1.985 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.371 ns                 ;
+; -1.961 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.104 ns                   ; 1.143 ns                 ;
+; -1.958 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.142 ns                   ; 1.184 ns                 ;
+; -1.934 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.422 ns                 ;
+; -1.923 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.433 ns                 ;
+; -1.867 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.143 ns                   ; 1.276 ns                 ;
+; -1.842 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.514 ns                 ;
+; -1.835 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.390 ns                   ; 1.555 ns                 ;
+; -1.795 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.392 ns                   ; 1.597 ns                 ;
+; -1.749 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.390 ns                   ; 1.641 ns                 ;
+; -1.745 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.392 ns                   ; 1.647 ns                 ;
+; -1.641 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.348 ns                   ; 1.707 ns                 ;
+; -1.595 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.204 ns                   ; 1.609 ns                 ;
+; -1.569 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.142 ns                   ; 1.573 ns                 ;
+; -1.508 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.111 ns                   ; 1.603 ns                 ;
+; -1.350 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe31                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.398 ns                   ; 2.048 ns                 ;
+; -1.326 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.623 ns                   ; 2.297 ns                 ;
+; -1.242 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.145 ns                   ; 1.903 ns                 ;
+; -1.234 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.973 ns                   ; 0.739 ns                 ;
+; -1.159 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 1.922 ns                 ;
+; -1.152 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe35                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 1.989 ns                 ;
+; -1.113 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.740 ns                   ; 2.627 ns                 ;
+; -1.095 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 2.046 ns                 ;
+; -1.072 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe19                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.362 ns                   ; 2.290 ns                 ;
+; -1.055 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 2.086 ns                 ;
+; -1.001 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.966 ns                   ; 0.965 ns                 ;
+; -0.993 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 1.310 ns                 ;
+; -0.961 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 2.120 ns                 ;
+; -0.918 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.364 ns                   ; 2.446 ns                 ;
+; -0.893 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.350 ns                   ; 1.457 ns                 ;
+; -0.849 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.714 ns                 ;
+; -0.825 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.091 ns                   ; 2.266 ns                 ;
+; -0.819 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe5                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.080 ns                   ; 2.261 ns                 ;
+; -0.770 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe3                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.080 ns                   ; 2.310 ns                 ;
+; -0.743 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.179 ns                   ; 1.436 ns                 ;
+; -0.742 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.179 ns                   ; 1.437 ns                 ;
+; -0.692 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.089 ns                   ; 2.397 ns                 ;
+; -0.675 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.521 ns                   ; 2.846 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
+; -0.668 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 2.975 ns                 ;
+; -0.658 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.905 ns                 ;
+; -0.655 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.908 ns                 ;
+; -0.591 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 2.490 ns                 ;
+; -0.569 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.731 ns                 ;
+; -0.553 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.296 ns                   ; 1.743 ns                 ;
+; -0.530 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 2.033 ns                 ;
+; -0.447 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.350 ns                   ; 1.903 ns                 ;
+; -0.441 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.090 ns                   ; 1.649 ns                 ;
+; -0.422 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.878 ns                 ;
+; -0.420 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.880 ns                 ;
+; -0.407 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe7                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.091 ns                   ; 2.684 ns                 ;
+; -0.353 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 2.210 ns                 ;
+; -0.320 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.980 ns                 ;
+; -0.319 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.981 ns                 ;
+; -0.198 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.328 ns                 ;
+; -0.184 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.709 ns                   ; 5.525 ns                 ;
+; -0.155 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.216 ns                   ; 3.061 ns                 ;
+; -0.143 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 3.990 ns                 ;
+; -0.133 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.718 ns                   ; 5.585 ns                 ;
+; -0.126 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.007 ns                 ;
+; -0.126 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.685 ns                   ; 5.559 ns                 ;
+; -0.125 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.004 ns                 ;
+; -0.116 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.017 ns                 ;
+; -0.097 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 5.593 ns                 ;
+; -0.097 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.314 ns                 ;
+; -0.092 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.037 ns                 ;
+; -0.070 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.885 ns                   ; 3.815 ns                 ;
+; -0.067 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.214 ns                   ; 3.147 ns                 ;
+; -0.065 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 3.784 ns                 ;
+; -0.060 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.917 ns                   ; 3.857 ns                 ;
+; -0.059 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe21                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.363 ns                   ; 3.304 ns                 ;
+; -0.046 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.311 ns                   ; 4.265 ns                 ;
+; -0.025 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 5.665 ns                 ;
+; -0.022 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.389 ns                 ;
+; -0.006 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.036 ns                   ; 2.030 ns                 ;
+; 0.007 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.760 ns                   ; 3.767 ns                 ;
+; 0.026 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.689 ns                   ; 5.715 ns                 ;
+; 0.067 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.593 ns                 ;
+; 0.072 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.598 ns                 ;
+; 0.091 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.637 ns                   ; 3.728 ns                 ;
+; 0.093 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.885 ns                   ; 3.978 ns                 ;
+; 0.093 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.961 ns                   ; 1.054 ns                 ;
+; 0.097 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.036 ns                   ; 2.133 ns                 ;
+; 0.104 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.718 ns                   ; 5.822 ns                 ;
+; 0.118 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 3.761 ns                 ;
+; 0.119 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.422 ns                 ;
+; 0.119 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.422 ns                 ;
+; 0.121 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.598 ns                   ; 4.719 ns                 ;
+; 0.123 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 3.972 ns                 ;
+; 0.132 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.083 ns                   ; 2.215 ns                 ;
+; 0.150 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.815 ns                   ; 3.965 ns                 ;
+; 0.151 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.280 ns                 ;
+; 0.158 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.228 ns                   ; 1.386 ns                 ;
+; 0.167 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.470 ns                 ;
+; 0.168 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.817 ns                   ; 3.985 ns                 ;
+; 0.177 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.357 ns                   ; 2.534 ns                 ;
+; 0.181 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.689 ns                   ; 5.870 ns                 ;
+; 0.184 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.017 ns                   ; 6.201 ns                 ;
+; 0.186 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.615 ns                   ; 3.801 ns                 ;
+; 0.188 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 4.037 ns                 ;
+; 0.191 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.323 ns                 ;
+; 0.192 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.324 ns                 ;
+; 0.195 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.693 ns                 ;
+; 0.216 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.685 ns                   ; 3.901 ns                 ;
+; 0.226 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.598 ns                   ; 4.824 ns                 ;
+; 0.231 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.707 ns                   ; 5.938 ns                 ;
+; 0.235 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.013 ns                   ; 6.248 ns                 ;
+; 0.243 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.459 ns                   ; 3.702 ns                 ;
+; 0.261 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.916 ns                   ; 2.177 ns                 ;
+; 0.262 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.916 ns                   ; 2.178 ns                 ;
+; 0.265 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.397 ns                 ;
+; 0.266 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.707 ns                   ; 5.973 ns                 ;
+; 0.291 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.917 ns                   ; 4.208 ns                 ;
+; 0.311 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.722 ns                 ;
+; 0.313 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.443 ns                 ;
+; 0.314 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.447 ns                 ;
+; 0.315 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.813 ns                 ;
+; 0.315 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.033 ns                   ; 2.348 ns                 ;
+; 0.318 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.621 ns                   ; 2.939 ns                 ;
+; 0.320 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.450 ns                 ;
+; 0.320 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.450 ns                 ;
+; 0.323 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.453 ns                 ;
+; 0.324 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.768 ns                   ; 6.092 ns                 ;
+; 0.333 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.126 ns                   ; 1.459 ns                 ;
+; 0.338 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.165 ns                   ; 1.503 ns                 ;
+; 0.339 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.178 ns                   ; 1.517 ns                 ;
+; 0.341 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.471 ns                 ;
+; 0.341 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.153 ns                   ; 1.494 ns                 ;
+; 0.342 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.801 ns                   ; 1.143 ns                 ;
+; 0.342 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.476 ns                 ;
+; 0.343 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.135 ns                   ; 1.478 ns                 ;
+; 0.344 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.637 ns                   ; 3.981 ns                 ;
+; 0.346 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.788 ns                   ; 1.134 ns                 ;
+; 0.347 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 3.990 ns                 ;
+; 0.349 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.165 ns                   ; 1.514 ns                 ;
+; 0.350 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.653 ns                 ;
+; 0.352 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.486 ns                 ;
+; 0.354 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.067 ns                   ; 6.421 ns                 ;
+; 0.355 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.123 ns                   ; 1.478 ns                 ;
+; 0.355 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.853 ns                 ;
+; 0.358 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.147 ns                   ; 1.505 ns                 ;
+; 0.360 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.490 ns                 ;
+; 0.360 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.771 ns                 ;
+; 0.361 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.493 ns                 ;
+; 0.362 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.502 ns                   ; 1.864 ns                 ;
+; 0.365 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.137 ns                   ; 1.502 ns                 ;
+; 0.365 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.802 ns                   ; 1.167 ns                 ;
+; 0.365 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.129 ns                   ; 1.494 ns                 ;
+; 0.366 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.185 ns                   ; 1.551 ns                 ;
+; 0.366 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.747 ns                   ; 6.113 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.129 ns                   ; 1.496 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.868 ns                   ; 1.235 ns                 ;
+; 0.367 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.746 ns                   ; 6.113 ns                 ;
+; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.500 ns                 ;
+; 0.368 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.264 ns                   ; 4.632 ns                 ;
+; 0.370 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.504 ns                 ;
+; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.124 ns                   ; 1.495 ns                 ;
+; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.127 ns                   ; 1.498 ns                 ;
+; 0.372 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.504 ns                 ;
+; 0.373 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.502 ns                   ; 1.875 ns                 ;
+; 0.374 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.133 ns                   ; 1.507 ns                 ;
+; 0.374 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 6.080 ns                 ;
+; 0.374 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.147 ns                   ; 1.521 ns                 ;
+; 0.376 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 6.066 ns                 ;
+; 0.379 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.511 ns                 ;
+; 0.381 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.460 ns                   ; 3.841 ns                 ;
+; 0.382 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.135 ns                   ; 1.517 ns                 ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;            ;          ;                            ;                            ;                          ;
++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; tsu                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
+; Slack                                   ; Required tsu                                        ; Actual tsu ; From      ; To                                                                                                                                                        ; To Clock ;
++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
+; -4.528 ns                               ; 1.000 ns                                            ; 5.528 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                     ; MAIN_CLK ;
+; -4.169 ns                               ; 1.000 ns                                            ; 5.169 ns   ; VD[19]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]                                                                        ; MAIN_CLK ;
+; -4.134 ns                               ; 1.000 ns                                            ; 5.134 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -4.083 ns                               ; 1.000 ns                                            ; 5.083 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
+; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
+; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
+; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
+; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
+; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
+; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
+; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
+; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
+; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
+; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
+; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
+; -3.956 ns                               ; 1.000 ns                                            ; 4.956 ns   ; VD[27]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]                                                                        ; MAIN_CLK ;
+; -3.930 ns                               ; 1.000 ns                                            ; 4.930 ns   ; nINDEX    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                        ; CLK33M   ;
+; -3.930 ns                               ; 1.000 ns                                            ; 4.930 ns   ; VD[31]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]                                                                        ; MAIN_CLK ;
+; -3.927 ns                               ; 1.000 ns                                            ; 4.927 ns   ; VD[1]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]                                                                         ; MAIN_CLK ;
+; -3.927 ns                               ; 1.000 ns                                            ; 4.927 ns   ; VD[9]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]                                                                         ; MAIN_CLK ;
+; -3.913 ns                               ; 1.000 ns                                            ; 4.913 ns   ; VD[2]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]                                                                         ; MAIN_CLK ;
+; -3.912 ns                               ; 1.000 ns                                            ; 4.912 ns   ; VD[12]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]                                                                        ; MAIN_CLK ;
+; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
+; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
+; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
+; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
+; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
+; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
+; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
+; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
+; -3.885 ns                               ; 1.000 ns                                            ; 4.885 ns   ; VD[20]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]                                                                        ; MAIN_CLK ;
+; -3.883 ns                               ; 1.000 ns                                            ; 4.883 ns   ; VD[25]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]                                                                        ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
+; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.859 ns                               ; 1.000 ns                                            ; 4.859 ns   ; VD[28]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]                                                                        ; MAIN_CLK ;
+; -3.855 ns                               ; 1.000 ns                                            ; 4.855 ns   ; VD[22]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]                                                                        ; MAIN_CLK ;
+; -3.851 ns                               ; 1.000 ns                                            ; 4.851 ns   ; VD[17]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]                                                                        ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
+; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
+; -3.827 ns                               ; 1.000 ns                                            ; 4.827 ns   ; VD[11]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]                                                                        ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
+; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
+; -3.804 ns                               ; 1.000 ns                                            ; 4.804 ns   ; VD[0]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]                                                                         ; MAIN_CLK ;
+; -3.801 ns                               ; 1.000 ns                                            ; 4.801 ns   ; VD[10]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]                                                                        ; MAIN_CLK ;
+; -3.796 ns                               ; 1.000 ns                                            ; 4.796 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state                                            ; MAIN_CLK ;
+; -3.794 ns                               ; 1.000 ns                                            ; 4.794 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1                                            ; MAIN_CLK ;
+; -3.794 ns                               ; 1.000 ns                                            ; 4.794 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state                                            ; MAIN_CLK ;
+; -3.783 ns                               ; 1.000 ns                                            ; 4.783 ns   ; VD[14]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]                                                                        ; MAIN_CLK ;
+; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
+; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.765 ns                               ; 1.000 ns                                            ; 4.765 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                        ; CLK33M   ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
+; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
+; -3.752 ns                               ; 1.000 ns                                            ; 4.752 ns   ; VD[6]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]                                                                         ; MAIN_CLK ;
+; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
+; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
+; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
+; -3.744 ns                               ; 1.000 ns                                            ; 4.744 ns   ; VD[21]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]                                                                        ; MAIN_CLK ;
+; -3.742 ns                               ; 1.000 ns                                            ; 4.742 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.740 ns                               ; 1.000 ns                                            ; 4.740 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
+; -3.740 ns                               ; 1.000 ns                                            ; 4.740 ns   ; VD[16]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]                                                                        ; MAIN_CLK ;
+; -3.739 ns                               ; 1.000 ns                                            ; 4.739 ns   ; VD[29]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]                                                                        ; MAIN_CLK ;
+; -3.735 ns                               ; 1.000 ns                                            ; 4.735 ns   ; VD[15]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]                                                                        ; MAIN_CLK ;
+; -3.708 ns                               ; 1.000 ns                                            ; 4.708 ns   ; VD[26]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]                                                                        ; MAIN_CLK ;
+; -3.707 ns                               ; 1.000 ns                                            ; 4.707 ns   ; VD[13]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]                                                                        ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
+; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
+; -3.703 ns                               ; 1.000 ns                                            ; 4.703 ns   ; VD[3]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]                                                                         ; MAIN_CLK ;
+; -3.699 ns                               ; 1.000 ns                                            ; 4.699 ns   ; VD[30]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]                                                                        ; MAIN_CLK ;
+; -3.694 ns                               ; 1.000 ns                                            ; 4.694 ns   ; VD[24]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]                                                                        ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
+; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
+; -3.684 ns                               ; 1.000 ns                                            ; 4.684 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
+; -3.684 ns                               ; 1.000 ns                                            ; 4.684 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.680 ns                               ; 1.000 ns                                            ; 4.680 ns   ; FB_AD[30] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
+; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
+; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
+; -3.634 ns                               ; 1.000 ns                                            ; 4.634 ns   ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
+; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
+; -3.471 ns                               ; 1.000 ns                                            ; 4.471 ns   ; VD[4]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]                                                                         ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
+; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
+; -3.386 ns                               ; 1.000 ns                                            ; 4.386 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                            ; MAIN_CLK ;
+; -3.339 ns                               ; 1.000 ns                                            ; 4.339 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
+; -3.334 ns                               ; 1.000 ns                                            ; 4.334 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE                            ; CLK33M   ;
+; -3.324 ns                               ; 1.000 ns                                            ; 4.324 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.290 ns                               ; 1.000 ns                                            ; 4.290 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
+; -3.272 ns                               ; 1.000 ns                                            ; 4.272 ns   ; FB_AD[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
+; -3.248 ns                               ; 1.000 ns                                            ; 4.248 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                     ; CLK33M   ;
+; -3.245 ns                               ; 1.000 ns                                            ; 4.245 ns   ; FB_AD[7]  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.236 ns                               ; 1.000 ns                                            ; 4.236 ns   ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.226 ns                               ; 1.000 ns                                            ; 4.226 ns   ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.226 ns                               ; 1.000 ns                                            ; 4.226 ns   ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
+; -3.218 ns                               ; 1.000 ns                                            ; 4.218 ns   ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
+; -3.214 ns                               ; 1.000 ns                                            ; 4.214 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.214 ns                               ; 1.000 ns                                            ; 4.214 ns   ; FB_AD[7]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
+; -3.211 ns                               ; 1.000 ns                                            ; 4.211 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                             ; MAIN_CLK ;
+; -3.208 ns                               ; 1.000 ns                                            ; 4.208 ns   ; FB_AD[3]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -3.206 ns                               ; 1.000 ns                                            ; 4.206 ns   ; FB_AD[4]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.203 ns                               ; 1.000 ns                                            ; 4.203 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.199 ns                               ; 1.000 ns                                            ; 4.199 ns   ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
+; -3.197 ns                               ; 1.000 ns                                            ; 4.197 ns   ; FB_AD[3]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
+; -3.194 ns                               ; 1.000 ns                                            ; 4.194 ns   ; FB_AD[4]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
+; -3.193 ns                               ; 1.000 ns                                            ; 4.193 ns   ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -3.190 ns                               ; 1.000 ns                                            ; 4.190 ns   ; FB_AD[10] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
+; -3.187 ns                               ; 1.000 ns                                            ; 4.187 ns   ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
+; -3.182 ns                               ; 1.000 ns                                            ; 4.182 ns   ; HD_DD     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[1] ; CLK33M   ;
+; -3.181 ns                               ; 1.000 ns                                            ; 4.181 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.174 ns                               ; 1.000 ns                                            ; 4.174 ns   ; FB_AD[12] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
+; -3.173 ns                               ; 1.000 ns                                            ; 4.173 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
+; -3.172 ns                               ; 1.000 ns                                            ; 4.172 ns   ; FB_ALE    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
+; -3.171 ns                               ; 1.000 ns                                            ; 4.171 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
+; -3.167 ns                               ; 1.000 ns                                            ; 4.167 ns   ; FB_AD[6]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
+; -3.162 ns                               ; 1.000 ns                                            ; 4.162 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
+; -3.160 ns                               ; 1.000 ns                                            ; 4.160 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                            ; MAIN_CLK ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;           ;                                                                                                                                                           ;          ;
++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; tco                                                                                                                                                                                                                                                                                ;
++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
+; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                                                         ; To        ; From Clock ;
++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
+; -14.840 ns                              ; 1.000 ns                                            ; 15.840 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; nIRQ[5]   ; MAIN_CLK   ;
+; -14.829 ns                              ; 1.000 ns                                            ; 15.829 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; nIRQ[5]   ; MAIN_CLK   ;
+; -13.764 ns                              ; 1.000 ns                                            ; 14.764 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; FB_AD[8]  ; MAIN_CLK   ;
+; -13.654 ns                              ; 1.000 ns                                            ; 14.654 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; FB_AD[9]  ; MAIN_CLK   ;
+; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; FB_AD[29] ; MAIN_CLK   ;
+; -13.575 ns                              ; 1.000 ns                                            ; 14.575 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; FB_AD[29] ; MAIN_CLK   ;
+; -13.493 ns                              ; 1.000 ns                                            ; 14.493 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.477 ns                              ; 1.000 ns                                            ; 14.477 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.457 ns                              ; 1.000 ns                                            ; 14.457 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                   ; FB_AD[18] ; MAIN_CLK   ;
+; -13.418 ns                              ; 1.000 ns                                            ; 14.418 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.386 ns                              ; 1.000 ns                                            ; 14.386 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                    ; FB_AD[7]  ; MAIN_CLK   ;
+; -13.358 ns                              ; 1.000 ns                                            ; 14.358 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.358 ns                              ; 1.000 ns                                            ; 14.358 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.309 ns                              ; 1.000 ns                                            ; 14.309 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
+; -13.294 ns                              ; 1.000 ns                                            ; 14.294 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -13.259 ns                              ; 1.000 ns                                            ; 14.259 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.250 ns                              ; 1.000 ns                                            ; 14.250 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                      ; FB_AD[18] ; MAIN_CLK   ;
+; -13.227 ns                              ; 1.000 ns                                            ; 14.227 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.207 ns                              ; 1.000 ns                                            ; 14.207 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
+; -13.171 ns                              ; 1.000 ns                                            ; 14.171 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.170 ns                              ; 1.000 ns                                            ; 14.170 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -13.157 ns                              ; 1.000 ns                                            ; 14.157 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -13.028 ns                              ; 1.000 ns                                            ; 14.028 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -13.015 ns                              ; 1.000 ns                                            ; 14.015 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -12.999 ns                              ; 1.000 ns                                            ; 13.999 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[2]                 ; FB_AD[18] ; MAIN_CLK   ;
+; -12.921 ns                              ; 1.000 ns                                            ; 13.921 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -12.886 ns                              ; 1.000 ns                                            ; 13.886 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -12.876 ns                              ; 1.000 ns                                            ; 13.876 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -12.861 ns                              ; 1.000 ns                                            ; 13.861 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -12.846 ns                              ; 1.000 ns                                            ; 13.846 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
+; -12.836 ns                              ; 1.000 ns                                            ; 13.836 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
+; -12.823 ns                              ; 1.000 ns                                            ; 13.823 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[2]                 ; FB_AD[18] ; MAIN_CLK   ;
+; -12.817 ns                              ; 1.000 ns                                            ; 13.817 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -12.784 ns                              ; 1.000 ns                                            ; 13.784 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
+; -12.732 ns                              ; 1.000 ns                                            ; 13.732 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.620 ns                              ; 1.000 ns                                            ; 13.620 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -12.567 ns                              ; 1.000 ns                                            ; 13.567 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -12.434 ns                              ; 1.000 ns                                            ; 13.434 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.425 ns                              ; 1.000 ns                                            ; 13.425 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.404 ns                              ; 1.000 ns                                            ; 13.404 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                     ; FB_AD[8]  ; MAIN_CLK   ;
+; -12.403 ns                              ; 1.000 ns                                            ; 13.403 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.361 ns                              ; 1.000 ns                                            ; 13.361 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -12.361 ns                              ; 1.000 ns                                            ; 13.361 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -12.302 ns                              ; 1.000 ns                                            ; 13.302 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]                     ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.301 ns                              ; 1.000 ns                                            ; 13.301 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -12.300 ns                              ; 1.000 ns                                            ; 13.300 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[2]                 ; FB_AD[18] ; MAIN_CLK   ;
+; -12.286 ns                              ; 1.000 ns                                            ; 13.286 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
+; -12.285 ns                              ; 1.000 ns                                            ; 13.285 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]                     ; FB_AD[18] ; MAIN_CLK   ;
+; -12.283 ns                              ; 1.000 ns                                            ; 13.283 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                        ; FB_AD[7]  ; CLK33M     ;
+; -12.260 ns                              ; 1.000 ns                                            ; 13.260 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.241 ns                              ; 1.000 ns                                            ; 13.241 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.219 ns                              ; 1.000 ns                                            ; 13.219 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2]                      ; FB_AD[18] ; MAIN_CLK   ;
+; -12.211 ns                              ; 1.000 ns                                            ; 13.211 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -12.205 ns                              ; 1.000 ns                                            ; 13.205 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
+; -12.200 ns                              ; 1.000 ns                                            ; 13.200 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.186 ns                              ; 1.000 ns                                            ; 13.186 ns  ; interrupt_handler:nobody|WERTE[2][0]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -12.182 ns                              ; 1.000 ns                                            ; 13.182 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                   ; FB_AD[22] ; MAIN_CLK   ;
+; -12.177 ns                              ; 1.000 ns                                            ; 13.177 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -12.175 ns                              ; 1.000 ns                                            ; 13.175 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[2]                 ; FB_AD[18] ; MAIN_CLK   ;
+; -12.173 ns                              ; 1.000 ns                                            ; 13.173 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -12.166 ns                              ; 1.000 ns                                            ; 13.166 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
+; -12.158 ns                              ; 1.000 ns                                            ; 13.158 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -12.157 ns                              ; 1.000 ns                                            ; 13.157 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -12.082 ns                              ; 1.000 ns                                            ; 13.082 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2]                      ; FB_AD[18] ; MAIN_CLK   ;
+; -12.055 ns                              ; 1.000 ns                                            ; 13.055 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                   ; FB_AD[21] ; MAIN_CLK   ;
+; -12.052 ns                              ; 1.000 ns                                            ; 13.052 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
+; -12.039 ns                              ; 1.000 ns                                            ; 13.039 ns  ; interrupt_handler:nobody|ACP_CONF[28]                                                                                                        ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.038 ns                              ; 1.000 ns                                            ; 13.038 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -12.022 ns                              ; 1.000 ns                                            ; 13.022 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -12.008 ns                              ; 1.000 ns                                            ; 13.008 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QB     ; MAIN_CLK   ;
+; -12.005 ns                              ; 1.000 ns                                            ; 13.005 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_DOUT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -12.004 ns                              ; 1.000 ns                                            ; 13.004 ns  ; interrupt_handler:nobody|WERTE[2][62]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.984 ns                              ; 1.000 ns                                            ; 12.984 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
+; -11.978 ns                              ; 1.000 ns                                            ; 12.978 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                           ; YM_QB     ; MAIN_CLK   ;
+; -11.968 ns                              ; 1.000 ns                                            ; 12.968 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -11.957 ns                              ; 1.000 ns                                            ; 12.957 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.946 ns                              ; 1.000 ns                                            ; 12.946 ns  ; interrupt_handler:nobody|WERTE[2][42]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.939 ns                              ; 1.000 ns                                            ; 12.939 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -11.938 ns                              ; 1.000 ns                                            ; 12.938 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                           ; YM_QB     ; MAIN_CLK   ;
+; -11.937 ns                              ; 1.000 ns                                            ; 12.937 ns  ; interrupt_handler:nobody|WERTE[2][10]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.935 ns                              ; 1.000 ns                                            ; 12.935 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                     ; FB_AD[9]  ; MAIN_CLK   ;
+; -11.933 ns                              ; 1.000 ns                                            ; 12.933 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.924 ns                              ; 1.000 ns                                            ; 12.924 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                     ; FB_AD[26] ; MAIN_CLK   ;
+; -11.922 ns                              ; 1.000 ns                                            ; 12.922 ns  ; interrupt_handler:nobody|WERTE[2][58]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.900 ns                              ; 1.000 ns                                            ; 12.900 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -11.874 ns                              ; 1.000 ns                                            ; 12.874 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
+; -11.871 ns                              ; 1.000 ns                                            ; 12.871 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[20] ; MAIN_CLK   ;
+; -11.867 ns                              ; 1.000 ns                                            ; 12.867 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.859 ns                              ; 1.000 ns                                            ; 12.859 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.857 ns                              ; 1.000 ns                                            ; 12.857 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                      ; FB_AD[20] ; MAIN_CLK   ;
+; -11.845 ns                              ; 1.000 ns                                            ; 12.845 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
+; -11.842 ns                              ; 1.000 ns                                            ; 12.842 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                   ; FB_AD[20] ; MAIN_CLK   ;
+; -11.834 ns                              ; 1.000 ns                                            ; 12.834 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
+; -11.831 ns                              ; 1.000 ns                                            ; 12.831 ns  ; interrupt_handler:nobody|WERTE[2][4]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -11.813 ns                              ; 1.000 ns                                            ; 12.813 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
+; -11.794 ns                              ; 1.000 ns                                            ; 12.794 ns  ; interrupt_handler:nobody|WERTE[2][43]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.787 ns                              ; 1.000 ns                                            ; 12.787 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.775 ns                              ; 1.000 ns                                            ; 12.775 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.774 ns                              ; 1.000 ns                                            ; 12.774 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -11.769 ns                              ; 1.000 ns                                            ; 12.769 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[18] ; MAIN_CLK   ;
+; -11.762 ns                              ; 1.000 ns                                            ; 12.762 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                ; FB_AD[20] ; MAIN_CLK   ;
+; -11.751 ns                              ; 1.000 ns                                            ; 12.751 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                           ; YM_QC     ; MAIN_CLK   ;
+; -11.747 ns                              ; 1.000 ns                                            ; 12.747 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.746 ns                              ; 1.000 ns                                            ; 12.746 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -11.736 ns                              ; 1.000 ns                                            ; 12.736 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.727 ns                              ; 1.000 ns                                            ; 12.727 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.725 ns                              ; 1.000 ns                                            ; 12.725 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.VECTOR_OUT ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.724 ns                              ; 1.000 ns                                            ; 12.724 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                           ; YM_QC     ; MAIN_CLK   ;
+; -11.721 ns                              ; 1.000 ns                                            ; 12.721 ns  ; interrupt_handler:nobody|WERTE[5][8]                                                                                                         ; FB_AD[21] ; MAIN_CLK   ;
+; -11.717 ns                              ; 1.000 ns                                            ; 12.717 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.710 ns                              ; 1.000 ns                                            ; 12.710 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7]                 ; FB_AD[9]  ; MAIN_CLK   ;
+; -11.709 ns                              ; 1.000 ns                                            ; 12.709 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.708 ns                              ; 1.000 ns                                            ; 12.708 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB[5]              ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.700 ns                              ; 1.000 ns                                            ; 12.700 ns  ; interrupt_handler:nobody|WERTE[2][2]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -11.694 ns                              ; 1.000 ns                                            ; 12.694 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                     ; FB_AD[28] ; MAIN_CLK   ;
+; -11.693 ns                              ; 1.000 ns                                            ; 12.693 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                   ; FB_AD[9]  ; MAIN_CLK   ;
+; -11.692 ns                              ; 1.000 ns                                            ; 12.692 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
+; -11.680 ns                              ; 1.000 ns                                            ; 12.680 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
+; -11.675 ns                              ; 1.000 ns                                            ; 12.675 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.673 ns                              ; 1.000 ns                                            ; 12.673 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.659 ns                              ; 1.000 ns                                            ; 12.659 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.649 ns                              ; 1.000 ns                                            ; 12.649 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.648 ns                              ; 1.000 ns                                            ; 12.648 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[25] ; MAIN_CLK   ;
+; -11.646 ns                              ; 1.000 ns                                            ; 12.646 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
+; -11.640 ns                              ; 1.000 ns                                            ; 12.640 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.633 ns                              ; 1.000 ns                                            ; 12.633 ns  ; interrupt_handler:nobody|WERTE[2][38]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.631 ns                              ; 1.000 ns                                            ; 12.631 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[19] ; MAIN_CLK   ;
+; -11.628 ns                              ; 1.000 ns                                            ; 12.628 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
+; -11.628 ns                              ; 1.000 ns                                            ; 12.628 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -11.627 ns                              ; 1.000 ns                                            ; 12.627 ns  ; interrupt_handler:nobody|WERTE[2][63]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.620 ns                              ; 1.000 ns                                            ; 12.620 ns  ; interrupt_handler:nobody|WERTE[2][61]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.620 ns                              ; 1.000 ns                                            ; 12.620 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.619 ns                              ; 1.000 ns                                            ; 12.619 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]                   ; YM_QB     ; MAIN_CLK   ;
+; -11.618 ns                              ; 1.000 ns                                            ; 12.618 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.616 ns                              ; 1.000 ns                                            ; 12.616 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
+; -11.616 ns                              ; 1.000 ns                                            ; 12.616 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                ; FB_AD[25] ; MAIN_CLK   ;
+; -11.608 ns                              ; 1.000 ns                                            ; 12.608 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[19] ; MAIN_CLK   ;
+; -11.607 ns                              ; 1.000 ns                                            ; 12.607 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[21] ; MAIN_CLK   ;
+; -11.595 ns                              ; 1.000 ns                                            ; 12.595 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
+; -11.592 ns                              ; 1.000 ns                                            ; 12.592 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[20] ; MAIN_CLK   ;
+; -11.592 ns                              ; 1.000 ns                                            ; 12.592 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
+; -11.589 ns                              ; 1.000 ns                                            ; 12.589 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                           ; YM_QA     ; MAIN_CLK   ;
+; -11.588 ns                              ; 1.000 ns                                            ; 12.588 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.588 ns                              ; 1.000 ns                                            ; 12.588 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.583 ns                              ; 1.000 ns                                            ; 12.583 ns  ; interrupt_handler:nobody|WERTE[2][57]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.582 ns                              ; 1.000 ns                                            ; 12.582 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
+; -11.579 ns                              ; 1.000 ns                                            ; 12.579 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QA     ; MAIN_CLK   ;
+; -11.578 ns                              ; 1.000 ns                                            ; 12.578 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
+; -11.576 ns                              ; 1.000 ns                                            ; 12.576 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7]                 ; FB_AD[23] ; MAIN_CLK   ;
+; -11.576 ns                              ; 1.000 ns                                            ; 12.576 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
+; -11.567 ns                              ; 1.000 ns                                            ; 12.567 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
+; -11.559 ns                              ; 1.000 ns                                            ; 12.559 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                   ; FB_AD[23] ; MAIN_CLK   ;
+; -11.552 ns                              ; 1.000 ns                                            ; 12.552 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QC     ; MAIN_CLK   ;
+; -11.550 ns                              ; 1.000 ns                                            ; 12.550 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -11.545 ns                              ; 1.000 ns                                            ; 12.545 ns  ; interrupt_handler:nobody|WERTE[2][31]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.544 ns                              ; 1.000 ns                                            ; 12.544 ns  ; interrupt_handler:nobody|WERTE[2][6]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -11.543 ns                              ; 1.000 ns                                            ; 12.543 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.542 ns                              ; 1.000 ns                                            ; 12.542 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.541 ns                              ; 1.000 ns                                            ; 12.541 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[23] ; MAIN_CLK   ;
+; -11.540 ns                              ; 1.000 ns                                            ; 12.540 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[4]                 ; FB_AD[20] ; MAIN_CLK   ;
+; -11.540 ns                              ; 1.000 ns                                            ; 12.540 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
+; -11.537 ns                              ; 1.000 ns                                            ; 12.537 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                    ; FB_AD[3]  ; MAIN_CLK   ;
+; -11.531 ns                              ; 1.000 ns                                            ; 12.531 ns  ; interrupt_handler:nobody|WERTE[2][45]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.527 ns                              ; 1.000 ns                                            ; 12.527 ns  ; interrupt_handler:nobody|WERTE[2][7]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -11.527 ns                              ; 1.000 ns                                            ; 12.527 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                ; FB_AD[25] ; MAIN_CLK   ;
+; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                ; FB_AD[20] ; MAIN_CLK   ;
+; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.508 ns                              ; 1.000 ns                                            ; 12.508 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3]                   ; FB_AD[27] ; MAIN_CLK   ;
+; -11.507 ns                              ; 1.000 ns                                            ; 12.507 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.505 ns                              ; 1.000 ns                                            ; 12.505 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.504 ns                              ; 1.000 ns                                            ; 12.504 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
+; -11.502 ns                              ; 1.000 ns                                            ; 12.502 ns  ; interrupt_handler:nobody|WERTE[2][60]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.502 ns                              ; 1.000 ns                                            ; 12.502 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                               ; FB_AD[26] ; MAIN_CLK   ;
+; -11.495 ns                              ; 1.000 ns                                            ; 12.495 ns  ; interrupt_handler:nobody|WERTE[2][53]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.492 ns                              ; 1.000 ns                                            ; 12.492 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
+; -11.488 ns                              ; 1.000 ns                                            ; 12.488 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                               ; FB_AD[3]  ; MAIN_CLK   ;
+; -11.487 ns                              ; 1.000 ns                                            ; 12.487 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.480 ns                              ; 1.000 ns                                            ; 12.480 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
+; -11.480 ns                              ; 1.000 ns                                            ; 12.480 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
+; -11.479 ns                              ; 1.000 ns                                            ; 12.479 ns  ; interrupt_handler:nobody|WERTE[2][36]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.478 ns                              ; 1.000 ns                                            ; 12.478 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[2]                   ; YM_QB     ; MAIN_CLK   ;
+; -11.470 ns                              ; 1.000 ns                                            ; 12.470 ns  ; interrupt_handler:nobody|WERTE[2][15]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.461 ns                              ; 1.000 ns                                            ; 12.461 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -11.460 ns                              ; 1.000 ns                                            ; 12.460 ns  ; interrupt_handler:nobody|WERTE[2][8]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
+; -11.459 ns                              ; 1.000 ns                                            ; 12.459 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
+; -11.455 ns                              ; 1.000 ns                                            ; 12.455 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                           ; YM_QA     ; MAIN_CLK   ;
+; -11.455 ns                              ; 1.000 ns                                            ; 12.455 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
+; -11.451 ns                              ; 1.000 ns                                            ; 12.451 ns  ; interrupt_handler:nobody|WERTE[2][50]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.447 ns                              ; 1.000 ns                                            ; 12.447 ns  ; interrupt_handler:nobody|WERTE[2][52]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; -11.444 ns                              ; 1.000 ns                                            ; 12.444 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
+; -11.443 ns                              ; 1.000 ns                                            ; 12.443 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
+; -11.441 ns                              ; 1.000 ns                                            ; 12.441 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
+; -11.435 ns                              ; 1.000 ns                                            ; 12.435 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
+; -11.433 ns                              ; 1.000 ns                                            ; 12.433 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[4]                   ; YM_QB     ; MAIN_CLK   ;
+; -11.432 ns                              ; 1.000 ns                                            ; 12.432 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5]              ; FB_AD[7]  ; MAIN_CLK   ;
+; -11.431 ns                              ; 1.000 ns                                            ; 12.431 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[20] ; MAIN_CLK   ;
+; -11.429 ns                              ; 1.000 ns                                            ; 12.429 ns  ; interrupt_handler:nobody|WERTE[2][55]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                                                              ;           ;            ;
++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; tpd                                                                                                                                    ;
++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
+; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From     ; To        ;
++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
+; -11.944 ns                              ; 1.000 ns                                            ; 12.944 ns       ; nFB_CS1  ; FB_AD[18] ;
+; -11.849 ns                              ; 1.000 ns                                            ; 12.849 ns       ; FB_SIZE0 ; FB_AD[27] ;
+; -11.785 ns                              ; 1.000 ns                                            ; 12.785 ns       ; nFB_CS1  ; FB_AD[27] ;
+; -11.694 ns                              ; 1.000 ns                                            ; 12.694 ns       ; nFB_CS1  ; FB_AD[7]  ;
+; -11.672 ns                              ; 1.000 ns                                            ; 12.672 ns       ; FB_SIZE1 ; FB_AD[27] ;
+; -11.625 ns                              ; 1.000 ns                                            ; 12.625 ns       ; nFB_WR   ; FB_AD[7]  ;
+; -11.514 ns                              ; 1.000 ns                                            ; 12.514 ns       ; FB_SIZE0 ; FB_AD[18] ;
+; -11.464 ns                              ; 1.000 ns                                            ; 12.464 ns       ; IDE_INT  ; FB_AD[7]  ;
+; -11.450 ns                              ; 1.000 ns                                            ; 12.450 ns       ; SRD[11]  ; FB_AD[27] ;
+; -11.438 ns                              ; 1.000 ns                                            ; 12.438 ns       ; nFB_OE   ; FB_AD[27] ;
+; -11.420 ns                              ; 1.000 ns                                            ; 12.420 ns       ; nFB_CS2  ; FB_AD[27] ;
+; -11.399 ns                              ; 1.000 ns                                            ; 12.399 ns       ; nFB_WR   ; FB_AD[27] ;
+; -11.376 ns                              ; 1.000 ns                                            ; 12.376 ns       ; nFB_WR   ; FB_AD[18] ;
+; -11.337 ns                              ; 1.000 ns                                            ; 12.337 ns       ; FB_SIZE1 ; FB_AD[18] ;
+; -11.243 ns                              ; 1.000 ns                                            ; 12.243 ns       ; nFB_CS2  ; FB_AD[18] ;
+; -10.918 ns                              ; 1.000 ns                                            ; 11.918 ns       ; nFB_CS1  ; FB_AD[20] ;
+; -10.824 ns                              ; 1.000 ns                                            ; 11.824 ns       ; nFB_CS2  ; FB_AD[7]  ;
+; -10.814 ns                              ; 1.000 ns                                            ; 11.814 ns       ; FB_SIZE0 ; FB_AD[7]  ;
+; -10.798 ns                              ; 1.000 ns                                            ; 11.798 ns       ; nFB_OE   ; FB_AD[7]  ;
+; -10.779 ns                              ; 1.000 ns                                            ; 11.779 ns       ; CTS      ; FB_AD[18] ;
+; -10.758 ns                              ; 1.000 ns                                            ; 11.758 ns       ; FB_SIZE1 ; FB_AD[7]  ;
+; -10.658 ns                              ; 1.000 ns                                            ; 11.658 ns       ; MAIN_CLK ; FB_AD[27] ;
+; -10.631 ns                              ; 1.000 ns                                            ; 11.631 ns       ; nFB_OE   ; FB_AD[18] ;
+; -10.578 ns                              ; 1.000 ns                                            ; 11.578 ns       ; MAIN_CLK ; FB_AD[7]  ;
+; -10.573 ns                              ; 1.000 ns                                            ; 11.573 ns       ; nFB_CS2  ; FB_AD[20] ;
+; -10.561 ns                              ; 1.000 ns                                            ; 11.561 ns       ; nFB_CS1  ; FB_AD[6]  ;
+; -10.549 ns                              ; 1.000 ns                                            ; 11.549 ns       ; FB_SIZE0 ; FB_AD[20] ;
+; -10.543 ns                              ; 1.000 ns                                            ; 11.543 ns       ; nFB_CS1  ; FB_AD[9]  ;
+; -10.529 ns                              ; 1.000 ns                                            ; 11.529 ns       ; FB_SIZE0 ; FB_AD[23] ;
+; -10.521 ns                              ; 1.000 ns                                            ; 11.521 ns       ; nFB_CS1  ; FB_AD[23] ;
+; -10.471 ns                              ; 1.000 ns                                            ; 11.471 ns       ; FB_SIZE1 ; FB_AD[20] ;
+; -10.451 ns                              ; 1.000 ns                                            ; 11.451 ns       ; FB_SIZE1 ; FB_AD[23] ;
+; -10.425 ns                              ; 1.000 ns                                            ; 11.425 ns       ; nFB_WR   ; FB_AD[9]  ;
+; -10.420 ns                              ; 1.000 ns                                            ; 11.420 ns       ; nFB_CS1  ; FB_AD[17] ;
+; -10.415 ns                              ; 1.000 ns                                            ; 11.415 ns       ; nFB_CS1  ; FB_AD[25] ;
+; -10.412 ns                              ; 1.000 ns                                            ; 11.412 ns       ; nFB_CS1  ; FB_AD[21] ;
+; -10.370 ns                              ; 1.000 ns                                            ; 11.370 ns       ; nFB_OE   ; FB_AD[20] ;
+; -10.364 ns                              ; 1.000 ns                                            ; 11.364 ns       ; nFB_WR   ; FB_AD[25] ;
+; -10.362 ns                              ; 1.000 ns                                            ; 11.362 ns       ; nFB_CS1  ; FB_AD[26] ;
+; -10.361 ns                              ; 1.000 ns                                            ; 11.361 ns       ; nFB_WR   ; FB_AD[20] ;
+; -10.335 ns                              ; 1.000 ns                                            ; 11.335 ns       ; nFB_CS2  ; FB_AD[23] ;
+; -10.318 ns                              ; 1.000 ns                                            ; 11.318 ns       ; nFB_CS2  ; FB_AD[21] ;
+; -10.317 ns                              ; 1.000 ns                                            ; 11.317 ns       ; nFB_WR   ; FB_AD[22] ;
+; -10.312 ns                              ; 1.000 ns                                            ; 11.312 ns       ; nFB_CS1  ; FB_AD[22] ;
+; -10.311 ns                              ; 1.000 ns                                            ; 11.311 ns       ; nFB_WR   ; FB_AD[26] ;
+; -10.291 ns                              ; 1.000 ns                                            ; 11.291 ns       ; nFB_WR   ; FB_AD[23] ;
+; -10.278 ns                              ; 1.000 ns                                            ; 11.278 ns       ; FB_SIZE0 ; FB_AD[17] ;
+; -10.277 ns                              ; 1.000 ns                                            ; 11.277 ns       ; MAIN_CLK ; FB_AD[18] ;
+; -10.221 ns                              ; 1.000 ns                                            ; 11.221 ns       ; FB_SIZE0 ; FB_AD[29] ;
+; -10.220 ns                              ; 1.000 ns                                            ; 11.220 ns       ; nFB_CS2  ; FB_AD[22] ;
+; -10.178 ns                              ; 1.000 ns                                            ; 11.178 ns       ; FB_SIZE0 ; FB_AD[19] ;
+; -10.146 ns                              ; 1.000 ns                                            ; 11.146 ns       ; FB_SIZE0 ; FB_AD[31] ;
+; -10.136 ns                              ; 1.000 ns                                            ; 11.136 ns       ; nFB_CS1  ; FB_AD[24] ;
+; -10.123 ns                              ; 1.000 ns                                            ; 11.123 ns       ; nFB_CS1  ; FB_AD[19] ;
+; -10.101 ns                              ; 1.000 ns                                            ; 11.101 ns       ; FB_SIZE1 ; FB_AD[17] ;
+; -10.085 ns                              ; 1.000 ns                                            ; 11.085 ns       ; nFB_WR   ; FB_AD[24] ;
+; -10.081 ns                              ; 1.000 ns                                            ; 11.081 ns       ; nFB_CS1  ; FB_AD[16] ;
+; -10.077 ns                              ; 1.000 ns                                            ; 11.077 ns       ; nFB_CS2  ; FB_AD[19] ;
+; -10.077 ns                              ; 1.000 ns                                            ; 11.077 ns       ; FB_SIZE0 ; FB_AD[21] ;
+; -10.076 ns                              ; 1.000 ns                                            ; 11.076 ns       ; FB_SIZE1 ; FB_AD[19] ;
+; -10.074 ns                              ; 1.000 ns                                            ; 11.074 ns       ; SRD[9]   ; FB_AD[25] ;
+; -10.070 ns                              ; 1.000 ns                                            ; 11.070 ns       ; nFB_CS1  ; FB_AD[29] ;
+; -10.061 ns                              ; 1.000 ns                                            ; 11.061 ns       ; nFB_OE   ; FB_AD[21] ;
+; -10.060 ns                              ; 1.000 ns                                            ; 11.060 ns       ; nFB_WR   ; FB_AD[21] ;
+; -10.051 ns                              ; 1.000 ns                                            ; 11.051 ns       ; nFB_WR   ; FB_AD[19] ;
+; -10.044 ns                              ; 1.000 ns                                            ; 11.044 ns       ; FB_SIZE1 ; FB_AD[29] ;
+; -10.041 ns                              ; 1.000 ns                                            ; 11.041 ns       ; FB_SIZE0 ; FB_AD[30] ;
+; -10.021 ns                              ; 1.000 ns                                            ; 11.021 ns       ; FB_SIZE1 ; FB_AD[21] ;
+; -10.019 ns                              ; 1.000 ns                                            ; 11.019 ns       ; nFB_WR   ; FB_AD[29] ;
+; -10.004 ns                              ; 1.000 ns                                            ; 11.004 ns       ; nFB_WR   ; FB_AD[6]  ;
+; -9.969 ns                               ; 1.000 ns                                            ; 10.969 ns       ; FB_SIZE1 ; FB_AD[31] ;
+; -9.951 ns                               ; 1.000 ns                                            ; 10.951 ns       ; FB_SIZE0 ; FB_AD[22] ;
+; -9.938 ns                               ; 1.000 ns                                            ; 10.938 ns       ; nFB_CS2  ; FB_AD[26] ;
+; -9.918 ns                               ; 1.000 ns                                            ; 10.918 ns       ; nFB_CS1  ; FB_AD[31] ;
+; -9.914 ns                               ; 1.000 ns                                            ; 10.914 ns       ; nFB_CS2  ; FB_AD[17] ;
+; -9.903 ns                               ; 1.000 ns                                            ; 10.903 ns       ; FB_SIZE0 ; FB_AD[25] ;
+; -9.899 ns                               ; 1.000 ns                                            ; 10.899 ns       ; IDE_INT  ; FB_AD[21] ;
+; -9.876 ns                               ; 1.000 ns                                            ; 10.876 ns       ; nFB_CS2  ; FB_AD[31] ;
+; -9.864 ns                               ; 1.000 ns                                            ; 10.864 ns       ; FB_SIZE1 ; FB_AD[30] ;
+; -9.835 ns                               ; 1.000 ns                                            ; 10.835 ns       ; LP_D[3]  ; FB_AD[27] ;
+; -9.823 ns                               ; 1.000 ns                                            ; 10.823 ns       ; nFB_WR   ; FB_AD[17] ;
+; -9.820 ns                               ; 1.000 ns                                            ; 10.820 ns       ; nFB_CS2  ; FB_AD[30] ;
+; -9.813 ns                               ; 1.000 ns                                            ; 10.813 ns       ; MAIN_CLK ; FB_AD[20] ;
+; -9.802 ns                               ; 1.000 ns                                            ; 10.802 ns       ; nFB_CS2  ; FB_AD[25] ;
+; -9.801 ns                               ; 1.000 ns                                            ; 10.801 ns       ; FB_SIZE1 ; FB_AD[25] ;
+; -9.792 ns                               ; 1.000 ns                                            ; 10.792 ns       ; nFB_CS2  ; FB_AD[29] ;
+; -9.791 ns                               ; 1.000 ns                                            ; 10.791 ns       ; nFB_OE   ; FB_AD[25] ;
+; -9.778 ns                               ; 1.000 ns                                            ; 10.778 ns       ; FB_SIZE1 ; FB_AD[22] ;
+; -9.770 ns                               ; 1.000 ns                                            ; 10.770 ns       ; nFB_OE   ; FB_AD[23] ;
+; -9.763 ns                               ; 1.000 ns                                            ; 10.763 ns       ; nFB_CS1  ; FB_AD[2]  ;
+; -9.750 ns                               ; 1.000 ns                                            ; 10.750 ns       ; nFB_WR   ; FB_AD[31] ;
+; -9.729 ns                               ; 1.000 ns                                            ; 10.729 ns       ; FB_SIZE0 ; FB_AD[9]  ;
+; -9.729 ns                               ; 1.000 ns                                            ; 10.729 ns       ; nFB_CS1  ; FB_AD[30] ;
+; -9.701 ns                               ; 1.000 ns                                            ; 10.701 ns       ; MAIN_CLK ; FB_AD[21] ;
+; -9.699 ns                               ; 1.000 ns                                            ; 10.699 ns       ; FB_SIZE0 ; FB_AD[24] ;
+; -9.692 ns                               ; 1.000 ns                                            ; 10.692 ns       ; nFB_OE   ; FB_AD[22] ;
+; -9.685 ns                               ; 1.000 ns                                            ; 10.685 ns       ; nFB_OE   ; FB_AD[31] ;
+; -9.684 ns                               ; 1.000 ns                                            ; 10.684 ns       ; nFB_OE   ; FB_AD[19] ;
+; -9.671 ns                               ; 1.000 ns                                            ; 10.671 ns       ; nFB_OE   ; FB_AD[17] ;
+; -9.634 ns                               ; 1.000 ns                                            ; 10.634 ns       ; nFB_CS2  ; FB_AD[24] ;
+; -9.630 ns                               ; 1.000 ns                                            ; 10.630 ns       ; SRD[2]   ; FB_AD[18] ;
+; -9.629 ns                               ; 1.000 ns                                            ; 10.629 ns       ; nFB_WR   ; FB_AD[30] ;
+; -9.628 ns                               ; 1.000 ns                                            ; 10.628 ns       ; nFB_CS2  ; FB_AD[9]  ;
+; -9.627 ns                               ; 1.000 ns                                            ; 10.627 ns       ; FB_SIZE1 ; FB_AD[9]  ;
+; -9.600 ns                               ; 1.000 ns                                            ; 10.600 ns       ; nFB_CS1  ; FB_AD[28] ;
+; -9.597 ns                               ; 1.000 ns                                            ; 10.597 ns       ; FB_SIZE1 ; FB_AD[24] ;
+; -9.593 ns                               ; 1.000 ns                                            ; 10.593 ns       ; nFB_WR   ; FB_AD[16] ;
+; -9.574 ns                               ; 1.000 ns                                            ; 10.574 ns       ; FB_SIZE0 ; FB_AD[28] ;
+; -9.572 ns                               ; 1.000 ns                                            ; 10.572 ns       ; DCD      ; FB_AD[17] ;
+; -9.565 ns                               ; 1.000 ns                                            ; 10.565 ns       ; nFB_OE   ; FB_AD[24] ;
+; -9.559 ns                               ; 1.000 ns                                            ; 10.559 ns       ; nFB_WR   ; FB_AD[8]  ;
+; -9.554 ns                               ; 1.000 ns                                            ; 10.554 ns       ; nFB_CS1  ; FB_AD[8]  ;
+; -9.521 ns                               ; 1.000 ns                                            ; 10.521 ns       ; nFB_CS1  ; FB_AD[3]  ;
+; -9.491 ns                               ; 1.000 ns                                            ; 10.491 ns       ; nFB_WR   ; FB_AD[28] ;
+; -9.477 ns                               ; 1.000 ns                                            ; 10.477 ns       ; nFB_CS2  ; FB_AD[3]  ;
+; -9.455 ns                               ; 1.000 ns                                            ; 10.455 ns       ; FB_SIZE0 ; FB_AD[26] ;
+; -9.418 ns                               ; 1.000 ns                                            ; 10.418 ns       ; RI       ; FB_AD[22] ;
+; -9.410 ns                               ; 1.000 ns                                            ; 10.410 ns       ; nFB_CS1  ; FB_AD[5]  ;
+; -9.398 ns                               ; 1.000 ns                                            ; 10.398 ns       ; MAIN_CLK ; FB_AD[26] ;
+; -9.397 ns                               ; 1.000 ns                                            ; 10.397 ns       ; FB_SIZE1 ; FB_AD[28] ;
+; -9.394 ns                               ; 1.000 ns                                            ; 10.394 ns       ; SRD[8]   ; FB_AD[24] ;
+; -9.381 ns                               ; 1.000 ns                                            ; 10.381 ns       ; nFB_OE   ; FB_AD[26] ;
+; -9.380 ns                               ; 1.000 ns                                            ; 10.380 ns       ; nFB_CS2  ; FB_AD[11] ;
+; -9.371 ns                               ; 1.000 ns                                            ; 10.371 ns       ; FB_SIZE0 ; FB_AD[4]  ;
+; -9.370 ns                               ; 1.000 ns                                            ; 10.370 ns       ; nFB_WR   ; FB_AD[5]  ;
+; -9.355 ns                               ; 1.000 ns                                            ; 10.355 ns       ; nFB_OE   ; FB_AD[4]  ;
+; -9.344 ns                               ; 1.000 ns                                            ; 10.344 ns       ; nFB_CS2  ; FB_AD[5]  ;
+; -9.333 ns                               ; 1.000 ns                                            ; 10.333 ns       ; FB_SIZE0 ; FB_AD[16] ;
+; -9.328 ns                               ; 1.000 ns                                            ; 10.328 ns       ; FB_SIZE0 ; FB_AD[2]  ;
+; -9.315 ns                               ; 1.000 ns                                            ; 10.315 ns       ; FB_SIZE1 ; FB_AD[4]  ;
+; -9.312 ns                               ; 1.000 ns                                            ; 10.312 ns       ; FB_SIZE0 ; FB_AD[3]  ;
+; -9.312 ns                               ; 1.000 ns                                            ; 10.312 ns       ; nFB_OE   ; FB_AD[2]  ;
+; -9.309 ns                               ; 1.000 ns                                            ; 10.309 ns       ; MAIN_CLK ; FB_AD[22] ;
+; -9.305 ns                               ; 1.000 ns                                            ; 10.305 ns       ; MAIN_CLK ; FB_AD[25] ;
+; -9.296 ns                               ; 1.000 ns                                            ; 10.296 ns       ; nFB_OE   ; FB_AD[3]  ;
+; -9.278 ns                               ; 1.000 ns                                            ; 10.278 ns       ; FB_SIZE1 ; FB_AD[26] ;
+; -9.275 ns                               ; 1.000 ns                                            ; 10.275 ns       ; nFB_WR   ; FB_AD[2]  ;
+; -9.273 ns                               ; 1.000 ns                                            ; 10.273 ns       ; nFB_CS1  ; nFB_TA    ;
+; -9.272 ns                               ; 1.000 ns                                            ; 10.272 ns       ; FB_SIZE1 ; FB_AD[2]  ;
+; -9.271 ns                               ; 1.000 ns                                            ; 10.271 ns       ; nFB_CS2  ; FB_AD[16] ;
+; -9.262 ns                               ; 1.000 ns                                            ; 10.262 ns       ; nFB_OE   ; FB_AD[28] ;
+; -9.256 ns                               ; 1.000 ns                                            ; 10.256 ns       ; FB_SIZE1 ; FB_AD[3]  ;
+; -9.245 ns                               ; 1.000 ns                                            ; 10.245 ns       ; nFB_CS2  ; FB_AD[2]  ;
+; -9.231 ns                               ; 1.000 ns                                            ; 10.231 ns       ; CLK33M   ; VB[7]     ;
+; -9.210 ns                               ; 1.000 ns                                            ; 10.210 ns       ; nFB_CS2  ; FB_AD[4]  ;
+; -9.203 ns                               ; 1.000 ns                                            ; 10.203 ns       ; nFB_OE   ; FB_AD[9]  ;
+; -9.201 ns                               ; 1.000 ns                                            ; 10.201 ns       ; nFB_CS2  ; FB_AD[8]  ;
+; -9.199 ns                               ; 1.000 ns                                            ; 10.199 ns       ; MAIN_CLK ; FB_AD[31] ;
+; -9.198 ns                               ; 1.000 ns                                            ; 10.198 ns       ; CLK33M   ; VSYNC_PAD ;
+; -9.193 ns                               ; 1.000 ns                                            ; 10.193 ns       ; CLK33M   ; VR[6]     ;
+; -9.191 ns                               ; 1.000 ns                                            ; 10.191 ns       ; CLK33M   ; VG[3]     ;
+; -9.176 ns                               ; 1.000 ns                                            ; 10.176 ns       ; nFB_CS1  ; FB_AD[4]  ;
+; -9.168 ns                               ; 1.000 ns                                            ; 10.168 ns       ; LP_D[7]  ; FB_AD[31] ;
+; -9.156 ns                               ; 1.000 ns                                            ; 10.156 ns       ; FB_SIZE1 ; FB_AD[16] ;
+; -9.145 ns                               ; 1.000 ns                                            ; 10.145 ns       ; MAIN_CLK ; FB_AD[23] ;
+; -9.145 ns                               ; 1.000 ns                                            ; 10.145 ns       ; nFB_CS2  ; FB_AD[28] ;
+; -9.112 ns                               ; 1.000 ns                                            ; 10.112 ns       ; nFB_WR   ; FB_AD[3]  ;
+; -9.099 ns                               ; 1.000 ns                                            ; 10.099 ns       ; MAIN_CLK ; FB_AD[19] ;
+; -9.089 ns                               ; 1.000 ns                                            ; 10.089 ns       ; nFB_OE   ; FB_AD[5]  ;
+; -9.088 ns                               ; 1.000 ns                                            ; 10.088 ns       ; SRD[5]   ; FB_AD[21] ;
+; -9.081 ns                               ; 1.000 ns                                            ; 10.081 ns       ; nFB_OE   ; FB_AD[16] ;
+; -9.079 ns                               ; 1.000 ns                                            ; 10.079 ns       ; MAIN_CLK ; FB_AD[24] ;
+; -9.047 ns                               ; 1.000 ns                                            ; 10.047 ns       ; nFB_CS2  ; FB_AD[10] ;
+; -9.019 ns                               ; 1.000 ns                                            ; 10.019 ns       ; nFB_CS2  ; FB_AD[13] ;
+; -9.004 ns                               ; 1.000 ns                                            ; 10.004 ns       ; FB_SIZE0 ; FB_AD[8]  ;
+; -8.984 ns                               ; 1.000 ns                                            ; 9.984 ns        ; LP_D[5]  ; FB_AD[29] ;
+; -8.935 ns                               ; 1.000 ns                                            ; 9.935 ns        ; SRD[4]   ; FB_AD[20] ;
+; -8.933 ns                               ; 1.000 ns                                            ; 9.933 ns        ; nFB_OE   ; FB_AD[30] ;
+; -8.927 ns                               ; 1.000 ns                                            ; 9.927 ns        ; SRD[10]  ; FB_AD[26] ;
+; -8.926 ns                               ; 1.000 ns                                            ; 9.926 ns        ; nFB_OE   ; FB_AD[8]  ;
+; -8.924 ns                               ; 1.000 ns                                            ; 9.924 ns        ; nFB_CS2  ; FB_AD[6]  ;
+; -8.921 ns                               ; 1.000 ns                                            ; 9.921 ns        ; nFB_WR   ; FB_AD[4]  ;
+; -8.916 ns                               ; 1.000 ns                                            ; 9.916 ns        ; LP_D[6]  ; FB_AD[30] ;
+; -8.909 ns                               ; 1.000 ns                                            ; 9.909 ns        ; nFB_CS2  ; FB_AD[15] ;
+; -8.902 ns                               ; 1.000 ns                                            ; 9.902 ns        ; FB_SIZE1 ; FB_AD[8]  ;
+; -8.896 ns                               ; 1.000 ns                                            ; 9.896 ns        ; FB_SIZE0 ; FB_AD[5]  ;
+; -8.876 ns                               ; 1.000 ns                                            ; 9.876 ns        ; nFB_CS2  ; FB_AD[14] ;
+; -8.873 ns                               ; 1.000 ns                                            ; 9.873 ns        ; LP_BUSY  ; FB_AD[16] ;
+; -8.869 ns                               ; 1.000 ns                                            ; 9.869 ns        ; MAIN_CLK ; FB_AD[4]  ;
+; -8.864 ns                               ; 1.000 ns                                            ; 9.864 ns        ; nFB_OE   ; FB_AD[29] ;
+; -8.852 ns                               ; 1.000 ns                                            ; 9.852 ns        ; nFB_CS2  ; FB_AD[12] ;
+; -8.840 ns                               ; 1.000 ns                                            ; 9.840 ns        ; FB_SIZE1 ; FB_AD[5]  ;
+; -8.826 ns                               ; 1.000 ns                                            ; 9.826 ns        ; MAIN_CLK ; FB_AD[2]  ;
+; -8.819 ns                               ; 1.000 ns                                            ; 9.819 ns        ; DCD      ; FB_AD[3]  ;
+; -8.810 ns                               ; 1.000 ns                                            ; 9.810 ns        ; MAIN_CLK ; FB_AD[3]  ;
+; -8.804 ns                               ; 1.000 ns                                            ; 9.804 ns        ; nFB_OE   ; FB_AD[13] ;
+; -8.803 ns                               ; 1.000 ns                                            ; 9.803 ns        ; SRD[7]   ; FB_AD[23] ;
+; -8.780 ns                               ; 1.000 ns                                            ; 9.780 ns        ; nFB_CS2  ; FB_AD[1]  ;
+; -8.776 ns                               ; 1.000 ns                                            ; 9.776 ns        ; MAIN_CLK ; FB_AD[28] ;
+; -8.715 ns                               ; 1.000 ns                                            ; 9.715 ns        ; FB_SIZE0 ; FB_AD[12] ;
+; -8.715 ns                               ; 1.000 ns                                            ; 9.715 ns        ; FB_SIZE0 ; FB_AD[11] ;
+; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; FB_SIZE0 ; BA[0]     ;
+; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; nFB_OE   ; FB_AD[12] ;
+; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; nFB_OE   ; FB_AD[11] ;
+; -8.672 ns                               ; 1.000 ns                                            ; 9.672 ns        ; FB_SIZE0 ; FB_AD[6]  ;
+; -8.660 ns                               ; 1.000 ns                                            ; 9.660 ns        ; RI       ; FB_AD[8]  ;
+; -8.659 ns                               ; 1.000 ns                                            ; 9.659 ns        ; FB_SIZE1 ; FB_AD[12] ;
+; -8.659 ns                               ; 1.000 ns                                            ; 9.659 ns        ; FB_SIZE1 ; FB_AD[11] ;
+; -8.656 ns                               ; 1.000 ns                                            ; 9.656 ns        ; nFB_OE   ; FB_AD[6]  ;
+; -8.651 ns                               ; 1.000 ns                                            ; 9.651 ns        ; FB_SIZE0 ; FB_AD[0]  ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                 ;          ;           ;
++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; th                                                                                                                                                                                                                                                                               ;
++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
+; Minimum Slack                           ; Required th                                         ; Actual th ; From      ; To                                                                                                                                            ; To Clock ;
++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
+; -0.401 ns                               ; 1.000 ns                                            ; 1.401 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                 ; MAIN_CLK ;
+; -0.386 ns                               ; 1.000 ns                                            ; 1.386 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9]                                                                 ; MAIN_CLK ;
+; -0.383 ns                               ; 1.000 ns                                            ; 1.383 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5]                                                                 ; MAIN_CLK ;
+; -0.383 ns                               ; 1.000 ns                                            ; 1.383 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21]                                                               ; MAIN_CLK ;
+; -0.370 ns                               ; 1.000 ns                                            ; 1.370 ns  ; CTS       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[2]       ; MAIN_CLK ;
+; -0.339 ns                               ; 1.000 ns                                            ; 1.339 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                 ; MAIN_CLK ;
+; -0.333 ns                               ; 1.000 ns                                            ; 1.333 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                    ; MAIN_CLK ;
+; -0.328 ns                               ; 1.000 ns                                            ; 1.328 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9]                                                                 ; MAIN_CLK ;
+; -0.325 ns                               ; 1.000 ns                                            ; 1.325 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                                ; MAIN_CLK ;
+; -0.325 ns                               ; 1.000 ns                                            ; 1.325 ns  ; RI        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[14]      ; MAIN_CLK ;
+; -0.321 ns                               ; 1.000 ns                                            ; 1.321 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]                                                                 ; MAIN_CLK ;
+; -0.320 ns                               ; 1.000 ns                                            ; 1.320 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]                                                               ; MAIN_CLK ;
+; -0.310 ns                               ; 1.000 ns                                            ; 1.310 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                     ; MAIN_CLK ;
+; -0.302 ns                               ; 1.000 ns                                            ; 1.302 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                                ; MAIN_CLK ;
+; -0.302 ns                               ; 1.000 ns                                            ; 1.302 ns  ; CTS       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[2]     ; MAIN_CLK ;
+; -0.293 ns                               ; 1.000 ns                                            ; 1.293 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                 ; MAIN_CLK ;
+; -0.285 ns                               ; 1.000 ns                                            ; 1.285 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6]                                                                ; MAIN_CLK ;
+; -0.283 ns                               ; 1.000 ns                                            ; 1.283 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]                                                                 ; MAIN_CLK ;
+; -0.275 ns                               ; 1.000 ns                                            ; 1.275 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]                                                               ; MAIN_CLK ;
+; -0.272 ns                               ; 1.000 ns                                            ; 1.272 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                 ; MAIN_CLK ;
+; -0.269 ns                               ; 1.000 ns                                            ; 1.269 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4]                                                                ; MAIN_CLK ;
+; -0.265 ns                               ; 1.000 ns                                            ; 1.265 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                     ; MAIN_CLK ;
+; -0.252 ns                               ; 1.000 ns                                            ; 1.252 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3]                                                                 ; MAIN_CLK ;
+; -0.247 ns                               ; 1.000 ns                                            ; 1.247 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]                                                                 ; MAIN_CLK ;
+; -0.246 ns                               ; 1.000 ns                                            ; 1.246 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]                                                               ; MAIN_CLK ;
+; -0.245 ns                               ; 1.000 ns                                            ; 1.245 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                    ; MAIN_CLK ;
+; -0.238 ns                               ; 1.000 ns                                            ; 1.238 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16]                                                               ; MAIN_CLK ;
+; -0.235 ns                               ; 1.000 ns                                            ; 1.235 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3]                                                                  ; MAIN_CLK ;
+; -0.235 ns                               ; 1.000 ns                                            ; 1.235 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8]                                                                 ; MAIN_CLK ;
+; -0.227 ns                               ; 1.000 ns                                            ; 1.227 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                    ; MAIN_CLK ;
+; -0.226 ns                               ; 1.000 ns                                            ; 1.226 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]                                                               ; MAIN_CLK ;
+; -0.224 ns                               ; 1.000 ns                                            ; 1.224 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                               ; MAIN_CLK ;
+; -0.223 ns                               ; 1.000 ns                                            ; 1.223 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                 ; MAIN_CLK ;
+; -0.222 ns                               ; 1.000 ns                                            ; 1.222 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                 ; MAIN_CLK ;
+; -0.216 ns                               ; 1.000 ns                                            ; 1.216 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]                                                                ; MAIN_CLK ;
+; -0.208 ns                               ; 1.000 ns                                            ; 1.208 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8]                                                                 ; MAIN_CLK ;
+; -0.202 ns                               ; 1.000 ns                                            ; 1.202 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22]                                                               ; MAIN_CLK ;
+; -0.197 ns                               ; 1.000 ns                                            ; 1.197 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]                                                                ; MAIN_CLK ;
+; -0.194 ns                               ; 1.000 ns                                            ; 1.194 ns  ; FB_AD[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                               ; MAIN_CLK ;
+; -0.191 ns                               ; 1.000 ns                                            ; 1.191 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]                                                                ; MAIN_CLK ;
+; -0.189 ns                               ; 1.000 ns                                            ; 1.189 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                     ; MAIN_CLK ;
+; -0.187 ns                               ; 1.000 ns                                            ; 1.187 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                     ; MAIN_CLK ;
+; -0.181 ns                               ; 1.000 ns                                            ; 1.181 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                       ; MAIN_CLK ;
+; -0.179 ns                               ; 1.000 ns                                            ; 1.179 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3]                                                                ; MAIN_CLK ;
+; -0.173 ns                               ; 1.000 ns                                            ; 1.173 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                               ; MAIN_CLK ;
+; -0.172 ns                               ; 1.000 ns                                            ; 1.172 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                 ; MAIN_CLK ;
+; -0.166 ns                               ; 1.000 ns                                            ; 1.166 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]                                                                ; MAIN_CLK ;
+; -0.165 ns                               ; 1.000 ns                                            ; 1.165 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10]                                                                ; MAIN_CLK ;
+; -0.162 ns                               ; 1.000 ns                                            ; 1.162 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6]                                                                 ; MAIN_CLK ;
+; -0.159 ns                               ; 1.000 ns                                            ; 1.159 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                    ; MAIN_CLK ;
+; -0.159 ns                               ; 1.000 ns                                            ; 1.159 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                               ; MAIN_CLK ;
+; -0.154 ns                               ; 1.000 ns                                            ; 1.154 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19]                                                               ; MAIN_CLK ;
+; -0.151 ns                               ; 1.000 ns                                            ; 1.151 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9]                                                                 ; MAIN_CLK ;
+; -0.149 ns                               ; 1.000 ns                                            ; 1.149 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                               ; MAIN_CLK ;
+; -0.146 ns                               ; 1.000 ns                                            ; 1.146 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                 ; MAIN_CLK ;
+; -0.145 ns                               ; 1.000 ns                                            ; 1.145 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5]                                                                 ; MAIN_CLK ;
+; -0.142 ns                               ; 1.000 ns                                            ; 1.142 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9]                                                                 ; MAIN_CLK ;
+; -0.141 ns                               ; 1.000 ns                                            ; 1.141 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                ; MAIN_CLK ;
+; -0.140 ns                               ; 1.000 ns                                            ; 1.140 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4]                                                                ; MAIN_CLK ;
+; -0.137 ns                               ; 1.000 ns                                            ; 1.137 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                     ; MAIN_CLK ;
+; -0.134 ns                               ; 1.000 ns                                            ; 1.134 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]                                                                  ; MAIN_CLK ;
+; -0.130 ns                               ; 1.000 ns                                            ; 1.130 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]                                                               ; MAIN_CLK ;
+; -0.130 ns                               ; 1.000 ns                                            ; 1.130 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                ; MAIN_CLK ;
+; -0.125 ns                               ; 1.000 ns                                            ; 1.125 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                     ; MAIN_CLK ;
+; -0.121 ns                               ; 1.000 ns                                            ; 1.121 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0]                                                                 ; MAIN_CLK ;
+; -0.121 ns                               ; 1.000 ns                                            ; 1.121 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                       ; MAIN_CLK ;
+; -0.113 ns                               ; 1.000 ns                                            ; 1.113 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5]                                                                 ; MAIN_CLK ;
+; -0.109 ns                               ; 1.000 ns                                            ; 1.109 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]                                                                 ; MAIN_CLK ;
+; -0.108 ns                               ; 1.000 ns                                            ; 1.108 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                 ; MAIN_CLK ;
+; -0.099 ns                               ; 1.000 ns                                            ; 1.099 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10]                                                               ; MAIN_CLK ;
+; -0.094 ns                               ; 1.000 ns                                            ; 1.094 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]                                                               ; MAIN_CLK ;
+; -0.092 ns                               ; 1.000 ns                                            ; 1.092 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9]                                                                 ; MAIN_CLK ;
+; -0.090 ns                               ; 1.000 ns                                            ; 1.090 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]                                                                ; MAIN_CLK ;
+; -0.089 ns                               ; 1.000 ns                                            ; 1.089 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]                                                               ; MAIN_CLK ;
+; -0.087 ns                               ; 1.000 ns                                            ; 1.087 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3]                                                                 ; MAIN_CLK ;
+; -0.086 ns                               ; 1.000 ns                                            ; 1.086 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5]                                                       ; MAIN_CLK ;
+; -0.085 ns                               ; 1.000 ns                                            ; 1.085 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                     ; MAIN_CLK ;
+; -0.081 ns                               ; 1.000 ns                                            ; 1.081 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0   ; MAIN_CLK ;
+; -0.079 ns                               ; 1.000 ns                                            ; 1.079 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                               ; MAIN_CLK ;
+; -0.078 ns                               ; 1.000 ns                                            ; 1.078 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9]                                                                 ; MAIN_CLK ;
+; -0.077 ns                               ; 1.000 ns                                            ; 1.077 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                 ; MAIN_CLK ;
+; -0.075 ns                               ; 1.000 ns                                            ; 1.075 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                 ; MAIN_CLK ;
+; -0.074 ns                               ; 1.000 ns                                            ; 1.074 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                    ; MAIN_CLK ;
+; -0.070 ns                               ; 1.000 ns                                            ; 1.070 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]                                                                ; MAIN_CLK ;
+; -0.070 ns                               ; 1.000 ns                                            ; 1.070 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14]                                                               ; MAIN_CLK ;
+; -0.068 ns                               ; 1.000 ns                                            ; 1.068 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5]                                                                 ; MAIN_CLK ;
+; -0.068 ns                               ; 1.000 ns                                            ; 1.068 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
+; -0.065 ns                               ; 1.000 ns                                            ; 1.065 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]                                                               ; MAIN_CLK ;
+; -0.064 ns                               ; 1.000 ns                                            ; 1.064 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                                ; MAIN_CLK ;
+; -0.064 ns                               ; 1.000 ns                                            ; 1.064 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]                                                                ; MAIN_CLK ;
+; -0.062 ns                               ; 1.000 ns                                            ; 1.062 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27]                                                               ; MAIN_CLK ;
+; -0.059 ns                               ; 1.000 ns                                            ; 1.059 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                 ; MAIN_CLK ;
+; -0.057 ns                               ; 1.000 ns                                            ; 1.057 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4]                                                                 ; MAIN_CLK ;
+; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                               ; MAIN_CLK ;
+; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6]                                                                ; MAIN_CLK ;
+; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25]                                                               ; MAIN_CLK ;
+; -0.053 ns                               ; 1.000 ns                                            ; 1.053 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                 ; MAIN_CLK ;
+; -0.047 ns                               ; 1.000 ns                                            ; 1.047 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3]                                                                 ; MAIN_CLK ;
+; -0.047 ns                               ; 1.000 ns                                            ; 1.047 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9]                                                       ; MAIN_CLK ;
+; -0.046 ns                               ; 1.000 ns                                            ; 1.046 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                 ; MAIN_CLK ;
+; -0.042 ns                               ; 1.000 ns                                            ; 1.042 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]                                                               ; MAIN_CLK ;
+; -0.042 ns                               ; 1.000 ns                                            ; 1.042 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8]                                                                 ; MAIN_CLK ;
+; -0.039 ns                               ; 1.000 ns                                            ; 1.039 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]                                                               ; MAIN_CLK ;
+; -0.037 ns                               ; 1.000 ns                                            ; 1.037 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]                                                       ; MAIN_CLK ;
+; -0.037 ns                               ; 1.000 ns                                            ; 1.037 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4]                                                                ; MAIN_CLK ;
+; -0.035 ns                               ; 1.000 ns                                            ; 1.035 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14]                                                               ; MAIN_CLK ;
+; -0.033 ns                               ; 1.000 ns                                            ; 1.033 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]                                                               ; MAIN_CLK ;
+; -0.028 ns                               ; 1.000 ns                                            ; 1.028 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4]                                                                 ; MAIN_CLK ;
+; -0.026 ns                               ; 1.000 ns                                            ; 1.026 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]                                                                 ; MAIN_CLK ;
+; -0.022 ns                               ; 1.000 ns                                            ; 1.022 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0]                                                                ; MAIN_CLK ;
+; -0.018 ns                               ; 1.000 ns                                            ; 1.018 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                 ; MAIN_CLK ;
+; -0.018 ns                               ; 1.000 ns                                            ; 1.018 ns  ; FB_AD[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12]                                                               ; MAIN_CLK ;
+; -0.017 ns                               ; 1.000 ns                                            ; 1.017 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                    ; MAIN_CLK ;
+; -0.017 ns                               ; 1.000 ns                                            ; 1.017 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                 ; MAIN_CLK ;
+; -0.011 ns                               ; 1.000 ns                                            ; 1.011 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                                ; MAIN_CLK ;
+; -0.010 ns                               ; 1.000 ns                                            ; 1.010 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3]                                                                 ; MAIN_CLK ;
+; -0.004 ns                               ; 1.000 ns                                            ; 1.004 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3]                                                                 ; MAIN_CLK ;
+; 0.007 ns                                ; 1.000 ns                                            ; 0.993 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                 ; MAIN_CLK ;
+; 0.008 ns                                ; 1.000 ns                                            ; 0.992 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]                                                               ; MAIN_CLK ;
+; 0.009 ns                                ; 1.000 ns                                            ; 0.991 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10]                                                               ; MAIN_CLK ;
+; 0.009 ns                                ; 1.000 ns                                            ; 0.991 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]                                                                ; MAIN_CLK ;
+; 0.010 ns                                ; 1.000 ns                                            ; 0.990 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]                                                               ; MAIN_CLK ;
+; 0.015 ns                                ; 1.000 ns                                            ; 0.985 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                 ; MAIN_CLK ;
+; 0.018 ns                                ; 1.000 ns                                            ; 0.982 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]                                                                 ; MAIN_CLK ;
+; 0.021 ns                                ; 1.000 ns                                            ; 0.979 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1]                                                                ; MAIN_CLK ;
+; 0.022 ns                                ; 1.000 ns                                            ; 0.978 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2]                                                                ; MAIN_CLK ;
+; 0.027 ns                                ; 1.000 ns                                            ; 0.973 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                                ; MAIN_CLK ;
+; 0.033 ns                                ; 1.000 ns                                            ; 0.967 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                     ; MAIN_CLK ;
+; 0.036 ns                                ; 1.000 ns                                            ; 0.964 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6]                                                                 ; MAIN_CLK ;
+; 0.042 ns                                ; 1.000 ns                                            ; 0.958 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8]                                                                 ; MAIN_CLK ;
+; 0.044 ns                                ; 1.000 ns                                            ; 0.956 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0]                                                                ; MAIN_CLK ;
+; 0.045 ns                                ; 1.000 ns                                            ; 0.955 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22]                                                               ; MAIN_CLK ;
+; 0.045 ns                                ; 1.000 ns                                            ; 0.955 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                ; MAIN_CLK ;
+; 0.046 ns                                ; 1.000 ns                                            ; 0.954 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14]                                                               ; MAIN_CLK ;
+; 0.047 ns                                ; 1.000 ns                                            ; 0.953 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3]                                                                 ; MAIN_CLK ;
+; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]                                                       ; MAIN_CLK ;
+; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[14]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]              ; MAIN_CLK ;
+; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[5]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]               ; MAIN_CLK ;
+; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[5]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]               ; MAIN_CLK ;
+; 0.050 ns                                ; 1.000 ns                                            ; 0.950 ns  ; VD[14]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]              ; MAIN_CLK ;
+; 0.050 ns                                ; 1.000 ns                                            ; 0.950 ns  ; RI        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[14]    ; MAIN_CLK ;
+; 0.054 ns                                ; 1.000 ns                                            ; 0.946 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3]                                                                ; MAIN_CLK ;
+; 0.054 ns                                ; 1.000 ns                                            ; 0.946 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]                                                                 ; MAIN_CLK ;
+; 0.055 ns                                ; 1.000 ns                                            ; 0.945 ns  ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29]                                                               ; MAIN_CLK ;
+; 0.055 ns                                ; 1.000 ns                                            ; 0.945 ns  ; VD[4]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]               ; MAIN_CLK ;
+; 0.057 ns                                ; 1.000 ns                                            ; 0.943 ns  ; VD[4]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]               ; MAIN_CLK ;
+; 0.064 ns                                ; 1.000 ns                                            ; 0.936 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20]                                                               ; MAIN_CLK ;
+; 0.078 ns                                ; 1.000 ns                                            ; 0.922 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]                                                                  ; MAIN_CLK ;
+; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                       ; MAIN_CLK ;
+; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; VD[8]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]               ; MAIN_CLK ;
+; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; VD[8]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]               ; MAIN_CLK ;
+; 0.081 ns                                ; 1.000 ns                                            ; 0.919 ns  ; VD[7]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]               ; MAIN_CLK ;
+; 0.082 ns                                ; 1.000 ns                                            ; 0.918 ns  ; VD[7]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]               ; MAIN_CLK ;
+; 0.091 ns                                ; 1.000 ns                                            ; 0.909 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                 ; MAIN_CLK ;
+; 0.098 ns                                ; 1.000 ns                                            ; 0.902 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3]                                                                ; MAIN_CLK ;
+; 0.106 ns                                ; 1.000 ns                                            ; 0.894 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9]                                                                 ; MAIN_CLK ;
+; 0.107 ns                                ; 1.000 ns                                            ; 0.893 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                    ; MAIN_CLK ;
+; 0.109 ns                                ; 1.000 ns                                            ; 0.891 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0]                                                                ; MAIN_CLK ;
+; 0.110 ns                                ; 1.000 ns                                            ; 0.890 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                               ; MAIN_CLK ;
+; 0.114 ns                                ; 1.000 ns                                            ; 0.886 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
+; 0.119 ns                                ; 1.000 ns                                            ; 0.881 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]                                                               ; MAIN_CLK ;
+; 0.125 ns                                ; 1.000 ns                                            ; 0.875 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                 ; MAIN_CLK ;
+; 0.125 ns                                ; 1.000 ns                                            ; 0.875 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5]                                                                ; MAIN_CLK ;
+; 0.128 ns                                ; 1.000 ns                                            ; 0.872 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2]                                                                ; MAIN_CLK ;
+; 0.131 ns                                ; 1.000 ns                                            ; 0.869 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21]                                                               ; MAIN_CLK ;
+; 0.131 ns                                ; 1.000 ns                                            ; 0.869 ns  ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29]                                                               ; MAIN_CLK ;
+; 0.132 ns                                ; 1.000 ns                                            ; 0.868 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0    ; MAIN_CLK ;
+; 0.133 ns                                ; 1.000 ns                                            ; 0.867 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8]                                                                ; MAIN_CLK ;
+; 0.136 ns                                ; 1.000 ns                                            ; 0.864 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]                                                                 ; MAIN_CLK ;
+; 0.148 ns                                ; 1.000 ns                                            ; 0.852 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9]                                                                ; MAIN_CLK ;
+; 0.149 ns                                ; 1.000 ns                                            ; 0.851 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6]                                                                 ; MAIN_CLK ;
+; 0.151 ns                                ; 1.000 ns                                            ; 0.849 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]                                                                 ; MAIN_CLK ;
+; 0.151 ns                                ; 1.000 ns                                            ; 0.849 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                ; MAIN_CLK ;
+; 0.158 ns                                ; 1.000 ns                                            ; 0.842 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                                ; MAIN_CLK ;
+; 0.159 ns                                ; 1.000 ns                                            ; 0.841 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]                                                                 ; MAIN_CLK ;
+; 0.159 ns                                ; 1.000 ns                                            ; 0.841 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22]                                                               ; MAIN_CLK ;
+; 0.161 ns                                ; 1.000 ns                                            ; 0.839 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                 ; MAIN_CLK ;
+; 0.163 ns                                ; 1.000 ns                                            ; 0.837 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0]                                                                 ; MAIN_CLK ;
+; 0.168 ns                                ; 1.000 ns                                            ; 0.832 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                                ; MAIN_CLK ;
+; 0.170 ns                                ; 1.000 ns                                            ; 0.830 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0   ; MAIN_CLK ;
+; 0.170 ns                                ; 1.000 ns                                            ; 0.830 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]                                                                 ; MAIN_CLK ;
+; 0.172 ns                                ; 1.000 ns                                            ; 0.828 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                     ; MAIN_CLK ;
+; 0.178 ns                                ; 1.000 ns                                            ; 0.822 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]                                                                    ; MAIN_CLK ;
+; 0.180 ns                                ; 1.000 ns                                            ; 0.820 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10]                                                               ; MAIN_CLK ;
+; 0.181 ns                                ; 1.000 ns                                            ; 0.819 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1]                                                                 ; MAIN_CLK ;
+; 0.186 ns                                ; 1.000 ns                                            ; 0.814 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                     ; MAIN_CLK ;
+; 0.188 ns                                ; 1.000 ns                                            ; 0.812 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                       ; MAIN_CLK ;
+; 0.191 ns                                ; 1.000 ns                                            ; 0.809 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]                                                               ; MAIN_CLK ;
+; 0.195 ns                                ; 1.000 ns                                            ; 0.805 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
+; 0.198 ns                                ; 1.000 ns                                            ; 0.802 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                 ; MAIN_CLK ;
+; 0.201 ns                                ; 1.000 ns                                            ; 0.799 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8]                                                                ; MAIN_CLK ;
+; 0.202 ns                                ; 1.000 ns                                            ; 0.798 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                 ; MAIN_CLK ;
+; 0.209 ns                                ; 1.000 ns                                            ; 0.791 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4]                                                                 ; MAIN_CLK ;
+; 0.213 ns                                ; 1.000 ns                                            ; 0.787 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0]                                                           ; MAIN_CLK ;
+; 0.216 ns                                ; 1.000 ns                                            ; 0.784 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                    ; MAIN_CLK ;
+; 0.220 ns                                ; 1.000 ns                                            ; 0.780 ns  ; VD[26]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]              ; MAIN_CLK ;
+; 0.221 ns                                ; 1.000 ns                                            ; 0.779 ns  ; VD[26]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]              ; MAIN_CLK ;
+; 0.228 ns                                ; 1.000 ns                                            ; 0.772 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0]                                                                 ; MAIN_CLK ;
+; 0.228 ns                                ; 1.000 ns                                            ; 0.772 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                 ; MAIN_CLK ;
+; 0.233 ns                                ; 1.000 ns                                            ; 0.767 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3]                                                                ; MAIN_CLK ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;                                                                                                                                               ;          ;
++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
+; CLK24M576     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_STR        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; CLK25M        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nACSI_ACK     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nACSI_RESET   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nACSI_CS      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_DIR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_A1       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_DIR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; MIDI_OLR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; MIDI_TLR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; TxD           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; RTS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; DTR           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; AMKB_TX       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IDE_RES       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIDE_CS0      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIDE_CS1      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIDE_WR       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIDE_RD       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nCF_CS0       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nCF_CS1       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nROM3         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nROM4         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nRP_UDS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nRP_LDS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSDSEL        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nWR_GATE      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nWR           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; YM_QA         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; YM_QB         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; YM_QC         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SD_CLK        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; DSA_D         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nVWE          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nVCAS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nVRAS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nVCS          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nPD_VGA       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; TIN0          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSRCS         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSRBLE        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSRBHE        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSRWE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nDREQ1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LED_FPGA_OK   ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSROE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VCKE          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nFB_TA        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nDDR_CLK      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; DDR_CLK       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSYNC         ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nMOT_ON       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSTEP         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; CLKUSB        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LPDIR         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; BA[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; BA[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[4]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[3]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nIRQ[2]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[12]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[11]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[10]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[9]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[8]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[7]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[6]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[5]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[4]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[3]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VA[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VB[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDM[3]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDM[2]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDM[1]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDM[0]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VG[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VR[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[31]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[30]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[29]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[28]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[27]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[26]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[25]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[24]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[23]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[22]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[21]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[20]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[19]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[18]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[17]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[16]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[15]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[14]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[13]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[12]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[11]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[10]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[9]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[8]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[7]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[6]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[5]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[4]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; FB_AD[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[31]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[30]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[29]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[28]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[27]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[26]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[25]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[24]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[23]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[22]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[21]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[20]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[19]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[18]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[17]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[16]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[15]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[14]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[13]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[12]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[11]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[10]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[9]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[8]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[7]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[6]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[5]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[4]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[3]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VD[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDQS[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDQS[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDQS[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; VDQS[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[17]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[16]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[15]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[14]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[13]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[12]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[11]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[10]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[9]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[8]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[7]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[6]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[5]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[4]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; IO[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SRD[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_PAR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; nSCSI_RST     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; LP_D[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; nFB_BURST               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nACSI_DRQ               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nACSI_INT               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_DRQ               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_MSG               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nDCHG                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_DATA0                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_DATA1                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_DATA2                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_CARD_DEDECT          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_WP                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nDACK0                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; WP_CF_CARD              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_C_D               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_I_O               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nFB_CS3                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; TOUT0                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nMASTER                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[31]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[30]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[29]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[28]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[27]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[26]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[25]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[24]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[23]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[22]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[21]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[20]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[19]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[18]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[17]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[16]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[15]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[14]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[13]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[12]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[11]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[10]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[9]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[8]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[7]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[6]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[5]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[4]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[3]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[2]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[1]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_AD[0]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; VD[31]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[30]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[29]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[28]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[27]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[26]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[25]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[24]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[23]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[22]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[21]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[20]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[19]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[18]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[17]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[16]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[15]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[14]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[13]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[12]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[11]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[10]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[9]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[8]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[7]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[6]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[5]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[4]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[3]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[2]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[1]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VD[0]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VDQS[3]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VDQS[2]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VDQS[1]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; VDQS[0]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; IO[17]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[16]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[15]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[14]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[13]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[12]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[11]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[10]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IO[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[15]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[14]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[13]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[12]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[11]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[10]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[9]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[8]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[7]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[6]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[5]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[4]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[3]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SRD[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_PAR                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_SEL               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_BUSY              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nSCSI_RST               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_CD_DATA3             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SD_CMD_D1               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ACSI_D[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[7]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[6]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[5]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[4]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[3]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_D[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SCSI_D[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nRSTO_MCF               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nFB_WR                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nFB_CS1                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_SIZE1                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_SIZE0                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; FB_ALE                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nFB_CS2                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; MAIN_CLK                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nDACK1                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nFB_OE                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IDE_RDY                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLK33M                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; HD_DD                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nINDEX                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; RxD                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nWP                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; LP_BUSY                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DCD                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CTS                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; TRACK00                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; IDE_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; RI                      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nPCI_INTD               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nPCI_INTC               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nPCI_INTB               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nPCI_INTA               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DVI_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; E0_INT                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PIC_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PIC_AMKB_RX             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; MIDI_IN                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; nRD_DATA                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; AMKB_RX                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DCLK~           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DEV_OE~         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
+; ~ALTERA_DEV_CLRn~       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; CLK24M576     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_STR        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; CLK25M        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0394 V           ; 0.292 V                              ; 0.188 V                              ; 9.15e-010 s                 ; 8.35e-010 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0394 V          ; 0.292 V                             ; 0.188 V                             ; 9.15e-010 s                ; 8.35e-010 s                ; No                        ; Yes                       ;
+; nACSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nACSI_RESET   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nACSI_CS      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_A1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; MIDI_OLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; MIDI_TLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; RTS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; DTR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; AMKB_TX       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.36e-006 V                  ; 3.09 V              ; -0.013 V            ; 0.103 V                              ; 0.224 V                              ; 1.59e-009 s                 ; 1.71e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.36e-006 V                 ; 3.09 V             ; -0.013 V           ; 0.103 V                             ; 0.224 V                             ; 1.59e-009 s                ; 1.71e-009 s                ; Yes                       ; Yes                       ;
+; IDE_RES       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; nIDE_CS0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nIDE_CS1      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nIDE_WR       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nIDE_RD       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nCF_CS0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nCF_CS1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nROM3         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nROM4         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nRP_UDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nRP_LDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0394 V           ; 0.292 V                              ; 0.188 V                              ; 9.15e-010 s                 ; 8.35e-010 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0394 V          ; 0.292 V                             ; 0.188 V                             ; 9.15e-010 s                ; 8.35e-010 s                ; No                        ; Yes                       ;
+; nSDSEL        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nWR_GATE      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; nWR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; YM_QA         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; YM_QB         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; YM_QC         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SD_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; DSA_D         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nVWE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; nVCAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; nVRAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; nVCS          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
+; nPD_VGA       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; TIN0          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; nSRCS         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nSRBLE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nSRBHE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nSRWE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nDREQ1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LED_FPGA_OK   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.97e-006 V                  ; 2.34 V              ; -0.00258 V          ; 0.168 V                              ; 0.069 V                              ; 1.53e-009 s                 ; 1.92e-009 s                 ; No                         ; Yes                        ; 2.32 V                      ; 1.97e-006 V                 ; 2.34 V             ; -0.00258 V         ; 0.168 V                             ; 0.069 V                             ; 1.53e-009 s                ; 1.92e-009 s                ; No                        ; Yes                       ;
+; nSROE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; VCKE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; nFB_TA        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nDDR_CLK      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; DDR_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
+; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; nSYNC         ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.97e-007 V                  ; 2.86 V              ; -0.0234 V           ; 0.145 V                              ; 0.061 V                              ; 4.67e-010 s                 ; 4.98e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.97e-007 V                 ; 2.86 V             ; -0.0234 V          ; 0.145 V                             ; 0.061 V                             ; 4.67e-010 s                ; 4.98e-010 s                ; Yes                       ; Yes                       ;
+; nMOT_ON       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; nSTEP         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; CLKUSB        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; LPDIR         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; BA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; BA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
+; nIRQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nIRQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nIRQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; nIRQ[4]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
+; nIRQ[3]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
+; nIRQ[2]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
+; VA[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
+; VA[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VA[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VA[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VA[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
+; VB[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
+; VB[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VB[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VDM[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
+; VDM[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VDM[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
+; VDM[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VG[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
+; VG[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VG[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
+; VR[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; VR[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
+; FB_AD[31]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[30]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[29]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[28]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[27]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; FB_AD[26]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[25]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[24]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[23]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[22]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[21]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[20]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[19]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[18]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; FB_AD[17]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[16]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[15]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[14]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[13]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; FB_AD[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; FB_AD[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; VD[31]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[30]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
+; VD[29]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[28]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[27]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[26]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[25]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[24]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[23]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[22]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
+; VD[21]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[20]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[19]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[18]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[17]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[16]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VD[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
+; VD[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
+; VD[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
+; VD[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VD[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VDQS[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VDQS[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
+; VDQS[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; VDQS[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
+; IO[17]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[16]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[15]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[14]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[13]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; IO[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; IO[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; IO[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; SRD[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SRD[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; SCSI_PAR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; nSCSI_RST     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
+; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; LP_D[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
+; LP_D[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; LP_D[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
+; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
+; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.43e-006 V                  ; 2.84 V              ; -0.0141 V           ; 0.183 V                              ; 0.066 V                              ; 8.84e-010 s                 ; 1.02e-009 s                 ; No                         ; Yes                        ; 2.8 V                       ; 1.43e-006 V                 ; 2.84 V             ; -0.0141 V          ; 0.183 V                             ; 0.066 V                             ; 8.84e-010 s                ; 1.02e-009 s                ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; CLK24M576     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_STR        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; CLK25M        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.57 V              ; -0.0649 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-010 s                 ; 6.19e-010 s                 ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-007 V                 ; 3.57 V             ; -0.0649 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-010 s                ; 6.19e-010 s                ; No                        ; Yes                       ;
+; nACSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nACSI_RESET   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nACSI_CS      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_A1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; MIDI_OLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; MIDI_TLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; RTS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; DTR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; AMKB_TX       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-007 V                   ; 3.5 V               ; -0.042 V            ; 0.297 V                              ; 0.24 V                               ; 1.12e-009 s                 ; 1.29e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 2.1e-007 V                  ; 3.5 V              ; -0.042 V           ; 0.297 V                             ; 0.24 V                              ; 1.12e-009 s                ; 1.29e-009 s                ; No                        ; No                        ;
+; IDE_RES       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; nIDE_CS0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nIDE_CS1      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nIDE_WR       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nIDE_RD       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nCF_CS0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nCF_CS1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nROM3         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nROM4         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nRP_UDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nRP_LDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.57 V              ; -0.0649 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-010 s                 ; 6.19e-010 s                 ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-007 V                 ; 3.57 V             ; -0.0649 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-010 s                ; 6.19e-010 s                ; No                        ; Yes                       ;
+; nSDSEL        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nWR_GATE      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; nWR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; YM_QA         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; YM_QB         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; YM_QC         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SD_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; DSA_D         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nVWE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; nVCAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; nVRAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; nVCS          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
+; nPD_VGA       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; TIN0          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; nSRCS         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nSRBLE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nSRBHE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nSRWE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nDREQ1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LED_FPGA_OK   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 7.2e-008 V                   ; 2.68 V              ; -0.0147 V           ; 0.295 V                              ; 0.167 V                              ; 9.36e-010 s                 ; 1.3e-009 s                  ; No                         ; Yes                        ; 2.62 V                      ; 7.2e-008 V                  ; 2.68 V             ; -0.0147 V          ; 0.295 V                             ; 0.167 V                             ; 9.36e-010 s                ; 1.3e-009 s                 ; No                        ; Yes                       ;
+; nSROE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; VCKE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; nFB_TA        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nDDR_CLK      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; DDR_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
+; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; nSYNC         ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.66e-008 V                  ; 3.29 V              ; -0.0256 V           ; 0.236 V                              ; 0.049 V                              ; 2.86e-010 s                 ; 3.59e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.66e-008 V                 ; 3.29 V             ; -0.0256 V          ; 0.236 V                             ; 0.049 V                             ; 2.86e-010 s                ; 3.59e-010 s                ; Yes                       ; Yes                       ;
+; nMOT_ON       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; nSTEP         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; CLKUSB        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; LPDIR         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; BA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; BA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
+; nIRQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nIRQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nIRQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; nIRQ[4]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
+; nIRQ[3]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
+; nIRQ[2]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
+; VA[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
+; VA[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VA[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VA[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VA[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
+; VB[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
+; VB[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VB[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VDM[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
+; VDM[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VDM[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
+; VDM[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VG[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
+; VG[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VG[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
+; VR[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; VR[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
+; FB_AD[31]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[30]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[29]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[28]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[27]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; FB_AD[26]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[25]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[24]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[23]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[22]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[21]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[20]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[19]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[18]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; FB_AD[17]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[16]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[15]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[14]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[13]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; FB_AD[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; FB_AD[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; VD[31]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[30]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
+; VD[29]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[28]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[27]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[26]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[25]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[24]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[23]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[22]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
+; VD[21]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[20]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[19]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[18]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[17]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[16]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VD[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
+; VD[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
+; VD[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
+; VD[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VD[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VDQS[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VDQS[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
+; VDQS[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; VDQS[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
+; IO[17]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[16]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[15]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[14]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[13]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; IO[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; IO[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; IO[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; SRD[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SRD[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; SCSI_PAR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; nSCSI_RST     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
+; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; LP_D[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
+; LP_D[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; LP_D[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
+; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
+; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 7.44e-008 V                  ; 3.24 V              ; -0.0384 V           ; 0.38 V                               ; 0.235 V                              ; 5.22e-010 s                 ; 7e-010 s                    ; No                         ; Yes                        ; 3.15 V                      ; 7.44e-008 V                 ; 3.24 V             ; -0.0384 V          ; 0.38 V                              ; 0.235 V                             ; 5.22e-010 s                ; 7e-010 s                   ; No                        ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Ignored Timing Assignments                                                                                                                                                                                                                 ;
++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
+; Option          ; Setting  ; From            ; To                                                               ; Entity Name ; Help                                                                                                       ;
++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
+; Cut Timing Path ; On       ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a                                        ; dcfifo_8fi1 ; Node named delayed_wrptr_g removed during synthesis                                                        ;
+; Clock Settings  ; fast     ;                 ; DDRCLK                                                           ;             ; Node named DDRCLK removed during synthesis                                                                 ;
+; Clock Settings  ; fast     ;                 ; DDRCLK[0]                                                        ;             ; Node named DDRCLK[0] removed during synthesis                                                              ;
+; Clock Settings  ; fast     ;                 ; DDRCLK[1]                                                        ;             ; Node named DDRCLK[1] removed during synthesis                                                              ;
+; Clock Settings  ; fast     ;                 ; DDRCLK[2]                                                        ;             ; Node named DDRCLK[2] removed during synthesis                                                              ;
+; Clock Settings  ; fast     ;                 ; DDRCLK[3]                                                        ;             ; Node named DDRCLK[3] removed during synthesis                                                              ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK                                    ;             ; Node named Video:Fredi_Aschwanden|DDRCLK removed during synthesis                                          ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[0]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[0] removed during synthesis                                       ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[1]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[1] removed during synthesis                                       ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[2]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[2] removed during synthesis                                       ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[3]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[3] removed during synthesis                                       ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK    ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK was found in the netlist    ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] was found in the netlist ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] was found in the netlist ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] was found in the netlist ;
+; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] was found in the netlist ;
+; Maximum Delay   ; 5 ns     ; VD              ; FB_AD                                                            ;             ; No timing path applicable to specified source and destination                                              ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[16]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[22]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[17]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[18]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[18]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[24]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[15]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[25]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[19]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[23]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[14]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[26]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[21]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[20]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
+; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Wed Dec 15 02:25:14 2010
+Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only
+Warning: Timing Analysis is analyzing one or more combinational loops as latches
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]" is a latch
+    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]" is a latch
+Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
+Warning: Clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" frequency requirement of 47.96 MHz overrides "Cyclone III" PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 48.0 MHz
+Warning: Clock Setting "fast" is unassigned
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" input frequency requirement of 0.5 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" input frequency requirement of 2.46 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" input frequency requirement of 24.57 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" input frequency requirement of 2.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" input frequency requirement of 15.99 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" input frequency requirement of 24.98 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" input frequency requirement of 47.96 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" input frequency requirement of 66.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 95.92 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
+Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[3]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[1]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[4]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[2]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[5]" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[3]~23" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[1]~25" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[4]~22" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[2]~24" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[0]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[6]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[9]" as buffer
+    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[8]" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[5]~21" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[0]~26" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[6]~20" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[9]~18" as buffer
+    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[8]~19" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~31" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~30" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~2" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]" as buffer
+    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~29" as buffer
+    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1" as buffer
+Info: Found timing assignments -- calculating delays
+Info: Slack time is 1.997 us for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]"
+    Info: Fmax is 362.45 MHz (period= 2.759 ns)
+    Info: + Largest register to register requirement is 1999.813 ns
+        Info: + Setup relationship between source and destination is 1999.998 ns
+            Info: + Latch edge is 1990.420 ns
+                Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is -9.578 ns
+                Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -0.001 ns
+            Info: + Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
+            Info: - Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.532 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.084 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.998 ns ( 84.88 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest register to register delay is 2.574 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]'
+        Info: 2: + IC(0.325 ns) + CELL(0.446 ns) = 0.771 ns; Loc. = LCCOMB_X65_Y16_N14; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita0~COUT'
+        Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.829 ns; Loc. = LCCOMB_X65_Y16_N16; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita1~COUT'
+        Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.887 ns; Loc. = LCCOMB_X65_Y16_N18; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita2~COUT'
+        Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.945 ns; Loc. = LCCOMB_X65_Y16_N20; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita3~COUT'
+        Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 1.003 ns; Loc. = LCCOMB_X65_Y16_N22; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita4~COUT'
+        Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 1.061 ns; Loc. = LCCOMB_X65_Y16_N24; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita5~COUT'
+        Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 1.119 ns; Loc. = LCCOMB_X65_Y16_N26; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita6~COUT'
+        Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 1.177 ns; Loc. = LCCOMB_X65_Y16_N28; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita7~COUT'
+        Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 1.235 ns; Loc. = LCCOMB_X65_Y16_N30; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita8~COUT'
+        Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 1.293 ns; Loc. = LCCOMB_X65_Y15_N0; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita9~COUT'
+        Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 1.351 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10~COUT'
+        Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 1.409 ns; Loc. = LCCOMB_X65_Y15_N4; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita11~COUT'
+        Info: 14: + IC(0.000 ns) + CELL(0.058 ns) = 1.467 ns; Loc. = LCCOMB_X65_Y15_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita12~COUT'
+        Info: 15: + IC(0.000 ns) + CELL(0.058 ns) = 1.525 ns; Loc. = LCCOMB_X65_Y15_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita13~COUT'
+        Info: 16: + IC(0.000 ns) + CELL(0.058 ns) = 1.583 ns; Loc. = LCCOMB_X65_Y15_N10; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita14~COUT'
+        Info: 17: + IC(0.000 ns) + CELL(0.058 ns) = 1.641 ns; Loc. = LCCOMB_X65_Y15_N12; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita15~COUT'
+        Info: 18: + IC(0.000 ns) + CELL(0.058 ns) = 1.699 ns; Loc. = LCCOMB_X65_Y15_N14; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita16~COUT'
+        Info: 19: + IC(0.000 ns) + CELL(0.455 ns) = 2.154 ns; Loc. = LCCOMB_X65_Y15_N16; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita17'
+        Info: 20: + IC(0.199 ns) + CELL(0.130 ns) = 2.483 ns; Loc. = LCCOMB_X65_Y15_N26; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]~feeder'
+        Info: 21: + IC(0.000 ns) + CELL(0.091 ns) = 2.574 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]'
+        Info: Total cell delay = 2.050 ns ( 79.64 % )
+        Info: Total interconnect delay = 0.524 ns ( 20.36 % )
+Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]"
+Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]"
+Info: Slack time is 498.663 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]"
+    Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits
+    Info: + Largest register to register requirement is 500.232 ns
+        Info: + Setup relationship between source and destination is 500.416 ns
+            Info: + Latch edge is 498.552 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is -1.864 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 0.000 ns
+            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]'
+                Info: Total cell delay = 0.534 ns ( 15.16 % )
+                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
+            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+                Info: Total cell delay = 0.534 ns ( 15.16 % )
+                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest register to register delay is 1.569 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+        Info: 2: + IC(0.344 ns) + CELL(0.376 ns) = 0.720 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 5; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13'
+        Info: 3: + IC(0.240 ns) + CELL(0.609 ns) = 1.569 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]'
+        Info: Total cell delay = 0.985 ns ( 62.78 % )
+        Info: Total interconnect delay = 0.584 ns ( 37.22 % )
+Info: Slack time is 28.59 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK"
+    Info: Fmax is 186.15 MHz (period= 5.372 ns)
+    Info: + Largest register to register requirement is 31.135 ns
+        Info: + Setup relationship between source and destination is 31.276 ns
+            Info: + Latch edge is 60.688 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 29.412 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with inverted offset of 29.412 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 0.020 ns
+            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.508 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.065 ns) + CELL(0.534 ns) = 3.508 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK'
+                Info: Total cell delay = 0.534 ns ( 15.22 % )
+                Info: Total interconnect delay = 2.974 ns ( 84.78 % )
+            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.488 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.131 ns) + CELL(0.448 ns) = 3.488 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In'
+                Info: Total cell delay = 0.448 ns ( 12.84 % )
+                Info: Total interconnect delay = 3.040 ns ( 87.16 % )
+        Info: - Micro clock to output delay of source is 0.176 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest register to register delay is 2.545 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.418 ns) = 0.418 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In'
+        Info: 2: + IC(1.655 ns) + CELL(0.381 ns) = 2.454 ns; Loc. = LCCOMB_X30_Y32_N2; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK~0'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 2.545 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK'
+        Info: Total cell delay = 0.890 ns ( 34.97 % )
+        Info: Total interconnect delay = 1.655 ns ( 65.03 % )
+Info: Slack time is -4.615 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
+    Info: + Largest memory to register requirement is -0.928 ns
+        Info: + Setup relationship between source and destination is 0.145 ns
+            Info: + Latch edge is 0.221 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 0.076 ns
+                Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -0.862 ns
+            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 7.507 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
+                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 7.507 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+                Info: Total cell delay = 1.084 ns ( 14.44 % )
+                Info: Total interconnect delay = 6.423 ns ( 85.56 % )
+            Info: - Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source memory is 8.369 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.112 ns) + CELL(0.816 ns) = 8.369 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+                Info: Total cell delay = 1.525 ns ( 18.22 % )
+                Info: Total interconnect delay = 6.844 ns ( 81.78 % )
+        Info: - Micro clock to output delay of source is 0.226 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest memory to register delay is 3.687 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
+        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
+        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+        Info: Total cell delay = 2.700 ns ( 73.23 % )
+        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
+Warning: Can't achieve timing requirement Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' along 3741 path(s). See Report window for details.
+Info: No valid register-to-register data paths exist for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]"
+Info: Slack time is -2.673 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC"
+    Info: + Largest pin to register requirement is 0.814 ns
+        Info: + Setup relationship between source and destination is 1.262 ns
+            Info: + Latch edge is 3.955 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 2.693 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 3.537 ns
+            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.537 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.102 ns) + CELL(0.534 ns) = 3.537 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC'
+                Info: Total cell delay = 0.534 ns ( 15.10 % )
+                Info: Total interconnect delay = 3.003 ns ( 84.90 % )
+        Info: - Micro setup delay of destination is -0.015 ns
+        Info: - Max Input delay of pin is 4.0 ns
+    Info: - Longest pin to register delay is 3.487 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
+        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
+        Info: 3: + IC(1.144 ns) + CELL(0.130 ns) = 2.215 ns; Loc. = LCCOMB_X22_Y6_N18; Fanout = 18; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5'
+        Info: 4: + IC(0.241 ns) + CELL(0.130 ns) = 2.586 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 19; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~0'
+        Info: 5: + IC(0.680 ns) + CELL(0.130 ns) = 3.396 ns; Loc. = LCCOMB_X25_Y6_N20; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC~1'
+        Info: 6: + IC(0.000 ns) + CELL(0.091 ns) = 3.487 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC'
+        Info: Total cell delay = 1.422 ns ( 40.78 % )
+        Info: Total interconnect delay = 2.065 ns ( 59.22 % )
+Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' along 86 path(s). See Report window for details.
+Info: Slack time is 2.965 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]"
+    Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits
+    Info: + Largest register to register requirement is 3.604 ns
+        Info: + Setup relationship between source and destination is 3.788 ns
+            Info: + Latch edge is 6.481 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 2.693 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 0.000 ns
+            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.531 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
+            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.531 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest register to register delay is 0.639 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]'
+        Info: 2: + IC(0.297 ns) + CELL(0.342 ns) = 0.639 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]'
+        Info: Total cell delay = 0.342 ns ( 53.52 % )
+        Info: Total interconnect delay = 0.297 ns ( 46.48 % )
+Info: Slack time is 5.299 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]"
+    Info: + Largest register to register requirement is 6.118 ns
+        Info: + Setup relationship between source and destination is 6.313 ns
+            Info: + Latch edge is 10.268 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 3.955 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -0.011 ns
+            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.532 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.097 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.998 ns ( 84.88 % )
+            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]'
+                Info: Total cell delay = 0.534 ns ( 15.07 % )
+                Info: Total interconnect delay = 3.009 ns ( 84.93 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest register to register delay is 0.819 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]'
+        Info: 2: + IC(0.598 ns) + CELL(0.130 ns) = 0.728 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]~feeder'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.819 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]'
+        Info: Total cell delay = 0.221 ns ( 26.98 % )
+        Info: Total interconnect delay = 0.598 ns ( 73.02 % )
+Info: Slack time is 1.672 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI"
+    Info: + Largest register to register requirement is 5.308 ns
+        Info: + Setup relationship between source and destination is 5.999 ns
+            Info: + Latch edge is 8.690 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 2.691 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -0.064 ns
+            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.487 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl'
+                Info: 3: + IC(1.098 ns) + CELL(0.488 ns) = 3.487 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI'
+                Info: Total cell delay = 0.488 ns ( 13.99 % )
+                Info: Total interconnect delay = 2.999 ns ( 86.01 % )
+            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.551 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
+                Info: 3: + IC(1.116 ns) + CELL(0.534 ns) = 3.551 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]'
+                Info: Total cell delay = 0.534 ns ( 15.04 % )
+                Info: Total interconnect delay = 3.017 ns ( 84.96 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: - Micro setup delay of destination is 0.428 ns
+    Info: - Longest register to register delay is 3.636 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]'
+        Info: 2: + IC(0.330 ns) + CELL(0.367 ns) = 0.697 ns; Loc. = LCCOMB_X22_Y2_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[34]~59'
+        Info: 3: + IC(2.591 ns) + CELL(0.348 ns) = 3.636 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI'
+        Info: Total cell delay = 0.715 ns ( 19.66 % )
+        Info: Total interconnect delay = 2.921 ns ( 80.34 % )
+Info: Slack time is -1.712 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ"
+    Info: + Largest pin to register requirement is 1.118 ns
+        Info: + Setup relationship between source and destination is 1.576 ns
+            Info: + Latch edge is 2.691 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 1.115 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 3.527 ns
+            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.527 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
+                Info: 3: + IC(1.092 ns) + CELL(0.534 ns) = 3.527 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ'
+                Info: Total cell delay = 0.534 ns ( 15.14 % )
+                Info: Total interconnect delay = 2.993 ns ( 84.86 % )
+        Info: - Micro setup delay of destination is -0.015 ns
+        Info: - Max Input delay of pin is 4.0 ns
+    Info: - Longest pin to register delay is 2.830 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
+        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
+        Info: 3: + IC(1.138 ns) + CELL(0.130 ns) = 2.209 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 7; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL'
+        Info: 4: + IC(0.400 ns) + CELL(0.130 ns) = 2.739 ns; Loc. = LCCOMB_X21_Y6_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~2'
+        Info: 5: + IC(0.000 ns) + CELL(0.091 ns) = 2.830 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ'
+        Info: Total cell delay = 1.292 ns ( 45.65 % )
+        Info: Total interconnect delay = 1.538 ns ( 54.35 % )
+Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' along 29 path(s). See Report window for details.
+Info: Slack time is -4.294 ns for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
+    Info: + Largest memory to register requirement is -0.607 ns
+        Info: + Setup relationship between source and destination is 0.272 ns
+            Info: + Latch edge is 0.493 ns
+                Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 0.221 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -0.668 ns
+            Info: + Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.082 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 8.082 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+                Info: Total cell delay = 1.243 ns ( 15.38 % )
+                Info: Total interconnect delay = 6.839 ns ( 84.62 % )
+            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
+                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+                Info: Total cell delay = 1.680 ns ( 19.20 % )
+                Info: Total interconnect delay = 7.070 ns ( 80.80 % )
+        Info: - Micro clock to output delay of source is 0.226 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest memory to register delay is 3.687 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
+        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
+        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+        Info: Total cell delay = 2.700 ns ( 73.23 % )
+        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
+Warning: Can't achieve timing requirement Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' along 3741 path(s). See Report window for details.
+Info: Slack time is -5.966 ns for clock "CLK33M" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
+    Info: + Largest memory to register requirement is -2.279 ns
+        Info: + Setup relationship between source and destination is 0.196 ns
+            Info: + Latch edge is 0.278 ns
+                Info: Clock period of Destination clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 0.082 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is -2.264 ns
+            Info: + Shortest clock path from clock "CLK33M" to destination register is 6.486 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
+                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
+                Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
+                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 6.486 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+                Info: Total cell delay = 2.006 ns ( 30.93 % )
+                Info: Total interconnect delay = 4.480 ns ( 69.07 % )
+            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
+                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+                Info: Total cell delay = 1.680 ns ( 19.20 % )
+                Info: Total interconnect delay = 7.070 ns ( 80.80 % )
+        Info: - Micro clock to output delay of source is 0.226 ns
+        Info: - Micro setup delay of destination is -0.015 ns
+    Info: - Longest memory to register delay is 3.687 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
+        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
+        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
+        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
+        Info: Total cell delay = 2.700 ns ( 73.23 % )
+        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
+Warning: Can't achieve timing requirement Clock Setup: 'CLK33M' along 3741 path(s). See Report window for details.
+Info: Slack time is -4.261 ns for clock "MAIN_CLK" between source pin "FB_ALE" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7"
+    Info: + Largest pin to register requirement is 0.057 ns
+        Info: + Setup relationship between source and destination is 1.094 ns
+            Info: + Latch edge is 7.575 ns
+                Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+            Info: - Launch edge is 6.481 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+        Info: + Largest clock skew is 2.948 ns
+            Info: + Shortest clock path from clock "MAIN_CLK" to destination register is 2.948 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+                Info: 3: + IC(1.433 ns) + CELL(0.534 ns) = 2.948 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7'
+                Info: Total cell delay = 1.515 ns ( 51.39 % )
+                Info: Total interconnect delay = 1.433 ns ( 48.61 % )
+        Info: - Micro setup delay of destination is -0.015 ns
+        Info: - Max Input delay of pin is 4.0 ns
+    Info: - Longest pin to register delay is 4.318 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
+        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
+        Info: 3: + IC(1.524 ns) + CELL(0.130 ns) = 2.595 ns; Loc. = LCCOMB_X23_Y7_N20; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2'
+        Info: 4: + IC(0.212 ns) + CELL(0.130 ns) = 2.937 ns; Loc. = LCCOMB_X23_Y7_N18; Fanout = 52; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1'
+        Info: 5: + IC(0.445 ns) + CELL(0.130 ns) = 3.512 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 4; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~2'
+        Info: 6: + IC(0.235 ns) + CELL(0.130 ns) = 3.877 ns; Loc. = LCCOMB_X22_Y7_N28; Fanout = 3; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~4'
+        Info: 7: + IC(0.220 ns) + CELL(0.130 ns) = 4.227 ns; Loc. = LCCOMB_X22_Y7_N16; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7~0'
+        Info: 8: + IC(0.000 ns) + CELL(0.091 ns) = 4.318 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7'
+        Info: Total cell delay = 1.682 ns ( 38.95 % )
+        Info: Total interconnect delay = 2.636 ns ( 61.05 % )
+Warning: Can't achieve timing requirement Clock Setup: 'MAIN_CLK' along 27347 path(s). See Report window for details.
+Info: Minimum slack time is 825 ps for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]"
+    Info: + Shortest register to register delay is 0.783 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
+        Info: 2: + IC(0.323 ns) + CELL(0.369 ns) = 0.692 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.783 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
+        Info: Total cell delay = 0.460 ns ( 58.75 % )
+        Info: Total interconnect delay = 0.323 ns ( 41.25 % )
+    Info: - Smallest register to register requirement is -0.042 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -9.578 ns
+                Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -9.578 ns
+                Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
+            Info: - Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.531 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
+                Info: Total cell delay = 0.534 ns ( 15.12 % )
+                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is 564 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]"
+    Info: + Shortest register to register delay is 0.522 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+        Info: 2: + IC(0.301 ns) + CELL(0.130 ns) = 0.431 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+        Info: Total cell delay = 0.221 ns ( 42.34 % )
+        Info: Total interconnect delay = 0.301 ns ( 57.66 % )
+    Info: - Smallest register to register requirement is -0.042 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -1.864 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -1.864 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+                Info: Total cell delay = 0.534 ns ( 15.16 % )
+                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
+            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
+                Info: Total cell delay = 0.534 ns ( 15.16 % )
+                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is 502 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1"
+    Info: + Shortest register to register delay is 0.460 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y28_N4; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector77~1'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
+        Info: Total cell delay = 0.460 ns ( 100.00 % )
+    Info: - Smallest register to register requirement is -0.042 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -1.864 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -1.864 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.526 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
+                Info: Total cell delay = 0.534 ns ( 15.14 % )
+                Info: Total interconnect delay = 2.992 ns ( 84.86 % )
+            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.526 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
+                Info: Total cell delay = 0.534 ns ( 15.14 % )
+                Info: Total interconnect delay = 2.992 ns ( 84.86 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is -454 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
+    Info: + Shortest register to register delay is 0.460 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: Total cell delay = 0.460 ns ( 100.00 % )
+    Info: - Smallest register to register requirement is 0.914 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -1.864 ns
+                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -1.864 ns
+                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.956 ns
+            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 8.469 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
+                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 8.469 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 1.398 ns ( 16.51 % )
+                Info: Total interconnect delay = 7.071 ns ( 83.49 % )
+            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source register is 7.513 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
+                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 7.513 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 1.084 ns ( 14.43 % )
+                Info: Total interconnect delay = 6.429 ns ( 85.57 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Warning: Can't achieve minimum setup and hold requirement altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] along 26 path(s). See Report window for details.
+Info: Minimum slack time is 502 ps for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]"
+    Info: + Shortest register to register delay is 0.460 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X45_Y15_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]~3'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
+        Info: Total cell delay = 0.460 ns ( 100.00 % )
+    Info: - Smallest register to register requirement is -0.042 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -3.620 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -3.620 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.559 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
+                Info: Total cell delay = 0.534 ns ( 15.00 % )
+                Info: Total interconnect delay = 3.025 ns ( 85.00 % )
+            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.559 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
+                Info: Total cell delay = 0.534 ns ( 15.00 % )
+                Info: Total interconnect delay = 3.025 ns ( 85.00 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is 4.336 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]"
+    Info: + Shortest register to register delay is 0.507 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]'
+        Info: 2: + IC(0.286 ns) + CELL(0.130 ns) = 0.416 ns; Loc. = LCCOMB_X66_Y14_N30; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]~feeder'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.507 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]'
+        Info: Total cell delay = 0.221 ns ( 43.59 % )
+        Info: Total interconnect delay = 0.286 ns ( 56.41 % )
+    Info: - Smallest register to register requirement is -3.829 ns
+        Info: + Hold relationship between source and destination is -3.787 ns
+            Info: + Latch edge is -1.094 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is 2.693 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.538 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]'
+                Info: Total cell delay = 0.534 ns ( 15.09 % )
+                Info: Total interconnect delay = 3.004 ns ( 84.91 % )
+            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.538 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
+                Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]'
+                Info: Total cell delay = 0.534 ns ( 15.09 % )
+                Info: Total interconnect delay = 3.004 ns ( 84.91 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is 1.825 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]"
+    Info: + Shortest register to register delay is 0.508 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]'
+        Info: 2: + IC(0.287 ns) + CELL(0.130 ns) = 0.417 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]~feeder'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.508 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]'
+        Info: Total cell delay = 0.221 ns ( 43.50 % )
+        Info: Total interconnect delay = 0.287 ns ( 56.50 % )
+    Info: - Smallest register to register requirement is -1.317 ns
+        Info: + Hold relationship between source and destination is -1.262 ns
+            Info: + Latch edge is 2.693 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is 3.955 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is -0.013 ns
+            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.530 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl'
+                Info: 3: + IC(1.095 ns) + CELL(0.534 ns) = 3.530 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]'
+                Info: Total cell delay = 0.534 ns ( 15.13 % )
+                Info: Total interconnect delay = 2.996 ns ( 84.87 % )
+            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]'
+                Info: Total cell delay = 0.534 ns ( 15.07 % )
+                Info: Total interconnect delay = 3.009 ns ( 84.93 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is 3.263 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO"
+    Info: + Shortest register to register delay is 1.570 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y2_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[29]~4'
+        Info: 3: + IC(0.737 ns) + CELL(0.464 ns) = 1.570 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO'
+        Info: Total cell delay = 0.833 ns ( 53.06 % )
+        Info: Total interconnect delay = 0.737 ns ( 46.94 % )
+    Info: - Smallest register to register requirement is -1.693 ns
+        Info: + Hold relationship between source and destination is -1.576 ns
+            Info: + Latch edge is 1.115 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is 2.691 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is -0.019 ns
+            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.543 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl'
+                Info: 3: + IC(1.154 ns) + CELL(0.488 ns) = 3.543 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO'
+                Info: Total cell delay = 0.488 ns ( 13.77 % )
+                Info: Total interconnect delay = 3.055 ns ( 86.23 % )
+            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.562 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
+                Info: 3: + IC(1.127 ns) + CELL(0.534 ns) = 3.562 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]'
+                Info: Total cell delay = 0.534 ns ( 14.99 % )
+                Info: Total interconnect delay = 3.028 ns ( 85.01 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.101 ns
+Info: Minimum slack time is 2.664 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]"
+    Info: + Shortest pin to register delay is 2.216 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
+        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
+        Info: 3: + IC(0.929 ns) + CELL(0.346 ns) = 2.216 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]'
+        Info: Total cell delay = 1.287 ns ( 58.08 % )
+        Info: Total interconnect delay = 0.929 ns ( 41.92 % )
+    Info: - Smallest pin to register requirement is -0.448 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -4.884 ns
+                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -4.884 ns
+                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 3.500 ns
+            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.500 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
+                Info: 3: + IC(1.151 ns) + CELL(0.448 ns) = 3.500 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]'
+                Info: Total cell delay = 0.448 ns ( 12.80 % )
+                Info: Total interconnect delay = 3.052 ns ( 87.20 % )
+        Info: + Micro hold delay of destination is 0.052 ns
+        Info: - Min Input delay of pin is 4.0 ns
+Info: Minimum slack time is 502 ps for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
+    Info: + Shortest register to register delay is 0.460 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: Total cell delay = 0.460 ns ( 100.00 % )
+    Info: - Smallest register to register requirement is -0.042 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is -2.843 ns
+                Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is -2.843 ns
+                Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 0.000 ns
+            Info: + Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.088 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 1.243 ns ( 15.37 % )
+                Info: Total interconnect delay = 6.845 ns ( 84.63 % )
+            Info: - Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source register is 8.088 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
+                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 1.243 ns ( 15.37 % )
+                Info: Total interconnect delay = 6.845 ns ( 84.63 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Info: Minimum slack time is -687 ps for clock "CLK33M" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
+    Info: + Shortest register to register delay is 0.460 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+        Info: Total cell delay = 0.460 ns ( 100.00 % )
+    Info: - Smallest register to register requirement is 1.147 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is 0.000 ns
+                Info: Clock period of Destination clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is 0.000 ns
+                Info: Clock period of Source clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 1.189 ns
+            Info: + Longest clock path from clock "CLK33M" to destination register is 7.681 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
+                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
+                Info: 3: + IC(1.161 ns) + CELL(0.733 ns) = 2.812 ns; Loc. = FF_X33_Y18_N25; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M'
+                Info: 4: + IC(0.852 ns) + CELL(0.311 ns) = 3.975 ns; Loc. = LCCOMB_X26_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4'
+                Info: 5: + IC(0.197 ns) + CELL(0.130 ns) = 4.302 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.034 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 7.681 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 2.626 ns ( 34.19 % )
+                Info: Total interconnect delay = 5.055 ns ( 65.81 % )
+            Info: - Shortest clock path from clock "CLK33M" to source register is 6.492 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
+                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
+                Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
+                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 6.492 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
+                Info: Total cell delay = 2.006 ns ( 30.90 % )
+                Info: Total interconnect delay = 4.486 ns ( 69.10 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Warning: Can't achieve minimum setup and hold requirement CLK33M along 26 path(s). See Report window for details.
+Info: Minimum slack time is -3.786 ns for clock "MAIN_CLK" between source register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]"
+    Info: + Shortest register to register delay is 1.930 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]'
+        Info: 2: + IC(1.597 ns) + CELL(0.242 ns) = 1.839 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]~1'
+        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 1.930 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]'
+        Info: Total cell delay = 0.333 ns ( 17.25 % )
+        Info: Total interconnect delay = 1.597 ns ( 82.75 % )
+    Info: - Smallest register to register requirement is 5.716 ns
+        Info: + Hold relationship between source and destination is 0.000 ns
+            Info: + Latch edge is 0.000 ns
+                Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Destination register is 1
+                Info: Multicycle Hold factor for Destination register is 1
+            Info: - Launch edge is 0.000 ns
+                Info: Clock period of Source clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
+                Info: Multicycle Setup factor for Source register is 1
+                Info: Multicycle Hold factor for Source register is 1
+        Info: + Smallest clock skew is 5.758 ns
+            Info: + Longest clock path from clock "MAIN_CLK" to destination register is 8.630 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+                Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]'
+                Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.988 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
+                Info: 7: + IC(1.108 ns) + CELL(0.534 ns) = 8.630 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]'
+                Info: Total cell delay = 2.858 ns ( 33.12 % )
+                Info: Total interconnect delay = 5.772 ns ( 66.88 % )
+            Info: - Shortest clock path from clock "MAIN_CLK" to source register is 2.872 ns
+                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+                Info: 3: + IC(1.357 ns) + CELL(0.534 ns) = 2.872 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]'
+                Info: Total cell delay = 1.515 ns ( 52.75 % )
+                Info: Total interconnect delay = 1.357 ns ( 47.25 % )
+        Info: - Micro clock to output delay of source is 0.199 ns
+        Info: + Micro hold delay of destination is 0.157 ns
+Warning: Can't achieve minimum setup and hold requirement MAIN_CLK along 108 path(s). See Report window for details.
+Warning: Can't achieve timing requirement tsu along 6867 path(s). See Report window for details.
+Info: Slack time is -4.528 ns for clock "MAIN_CLK" between source clock "MAIN_CLK" and destination register "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state"
+    Info: + tsu requirement for source pin and destination register is 1.000 ns
+    Info: - tsu from clock to input pin is 5.528 ns
+        Info: + Longest clock to register delay is 8.706 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+            Info: 3: + IC(4.109 ns) + CELL(0.869 ns) = 5.959 ns; Loc. = PLL_2; Fanout = 4; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|scandone'
+            Info: 4: + IC(1.722 ns) + CELL(0.130 ns) = 7.811 ns; Loc. = LCCOMB_X21_Y26_N18; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~0'
+            Info: 5: + IC(0.198 ns) + CELL(0.130 ns) = 8.139 ns; Loc. = LCCOMB_X21_Y26_N28; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~1'
+            Info: 6: + IC(0.346 ns) + CELL(0.130 ns) = 8.615 ns; Loc. = LCCOMB_X22_Y26_N16; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~2'
+            Info: 7: + IC(0.000 ns) + CELL(0.091 ns) = 8.706 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state'
+            Info: Total cell delay = 2.331 ns ( 26.77 % )
+            Info: Total interconnect delay = 6.375 ns ( 73.23 % )
+        Info: + Micro setup delay of destination is -0.015 ns
+        Info: - Shortest clock path from clock "MAIN_CLK" to destination register is 3.163 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+            Info: 3: + IC(1.648 ns) + CELL(0.534 ns) = 3.163 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state'
+            Info: Total cell delay = 1.515 ns ( 47.90 % )
+            Info: Total interconnect delay = 1.648 ns ( 52.10 % )
+Warning: Can't achieve timing requirement tco along 4976 path(s). See Report window for details.
+Info: Slack time is -14.84 ns for clock "MAIN_CLK" between source register "interrupt_handler:nobody|INT_LATCH[8]" and destination pin "nIRQ[5]"
+    Info: + tco requirement for source register and destination pin is 1.000 ns
+    Info: - tco from clock to output pin is 15.840 ns
+        Info: + Longest clock path from clock "MAIN_CLK" to source register is 9.460 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+            Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]'
+            Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
+            Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
+            Info: 6: + IC(1.232 ns) + CELL(0.733 ns) = 7.221 ns; Loc. = FF_X18_Y15_N21; Fanout = 5; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+            Info: 7: + IC(0.716 ns) + CELL(0.308 ns) = 8.245 ns; Loc. = LCCOMB_X15_Y15_N6; Fanout = 1; COMB Node = 'interrupt_handler:nobody|INT_LATCH[8]~19'
+            Info: 8: + IC(0.681 ns) + CELL(0.534 ns) = 9.460 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]'
+            Info: Total cell delay = 3.899 ns ( 41.22 % )
+            Info: Total interconnect delay = 5.561 ns ( 58.78 % )
+        Info: + Micro clock to output delay of source is 0.199 ns
+        Info: + Longest register to pin delay is 6.181 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]'
+            Info: 2: + IC(0.325 ns) + CELL(0.241 ns) = 0.566 ns; Loc. = LCCOMB_X16_Y12_N20; Fanout = 1; COMB Node = 'interrupt_handler:nobody|_~17'
+            Info: 3: + IC(0.198 ns) + CELL(0.130 ns) = 0.894 ns; Loc. = LCCOMB_X16_Y12_N22; Fanout = 1; COMB Node = 'interrupt_handler:nobody|nIRQ[5]'
+            Info: 4: + IC(1.158 ns) + CELL(4.129 ns) = 6.181 ns; Loc. = IOOBUF_X0_Y12_N16; Fanout = 1; COMB Node = 'nIRQ[5]~output'
+            Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 6.181 ns; Loc. = PIN_P5; Fanout = 0; PIN Node = 'nIRQ[5]'
+            Info: Total cell delay = 4.500 ns ( 72.80 % )
+            Info: Total interconnect delay = 1.681 ns ( 27.20 % )
+Info: Slack time is -11.944 ns between source pin "nFB_CS1" and destination pin "FB_AD[18]"
+    Info: + Longest pin to pin requirement is 1.000 ns
+    Info: - Longest pin to pin delay is 12.944 ns
+        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T8; Fanout = 1; PIN Node = 'nFB_CS1'
+        Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X14_Y0_N29; Fanout = 59; COMB Node = 'nFB_CS1~input'
+        Info: 3: + IC(1.591 ns) + CELL(0.241 ns) = 2.750 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 68; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1'
+        Info: 4: + IC(0.915 ns) + CELL(0.130 ns) = 3.795 ns; Loc. = LCCOMB_X29_Y10_N14; Fanout = 12; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB_CS'
+        Info: 5: + IC(0.302 ns) + CELL(0.342 ns) = 4.439 ns; Loc. = LCCOMB_X29_Y10_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~44'
+        Info: 6: + IC(0.648 ns) + CELL(0.243 ns) = 5.330 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~48'
+        Info: 7: + IC(0.807 ns) + CELL(0.243 ns) = 6.380 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~55'
+        Info: 8: + IC(0.200 ns) + CELL(0.130 ns) = 6.710 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5'
+        Info: 9: + IC(1.088 ns) + CELL(0.242 ns) = 8.040 ns; Loc. = LCCOMB_X21_Y14_N4; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180'
+        Info: 10: + IC(0.876 ns) + CELL(4.028 ns) = 12.944 ns; Loc. = IOOBUF_X20_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[18]~output'
+        Info: 11: + IC(0.000 ns) + CELL(0.000 ns) = 12.944 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'FB_AD[18]'
+        Info: Total cell delay = 6.517 ns ( 50.35 % )
+        Info: Total interconnect delay = 6.427 ns ( 49.65 % )
+Warning: Can't achieve timing requirement tpd along 514 path(s). See Report window for details.
+Warning: Can't achieve timing requirement th along 117 path(s). See Report window for details.
+Info: Minimum slack time is -401 ps for clock "MAIN_CLK" between source pin "FB_AD[25]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]"
+    Info: + th requirement for source pin and destination register is 1.000 ns
+    Info: - th from clock to input pin is 1.401 ns
+        Info: + Longest clock path from clock "MAIN_CLK" to destination register is 4.679 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
+            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
+            Info: 3: + IC(3.164 ns) + CELL(0.534 ns) = 4.679 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]'
+            Info: Total cell delay = 1.515 ns ( 32.38 % )
+            Info: Total interconnect delay = 3.164 ns ( 67.62 % )
+        Info: + Micro hold delay of destination is 0.157 ns
+        Info: - Shortest pin to register delay is 3.435 ns
+            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'FB_AD[25]'
+            Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X27_Y0_N8; Fanout = 59; COMB Node = 'FB_AD[25]~input'
+            Info: 3: + IC(2.175 ns) + CELL(0.342 ns) = 3.435 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]'
+            Info: Total cell delay = 1.260 ns ( 36.68 % )
+            Info: Total interconnect delay = 2.175 ns ( 63.32 % )
+Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
+Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 65 warnings
+    Info: Peak virtual memory: 238 megabytes
+    Info: Processing ended: Wed Dec 15 02:25:23 2010
+    Info: Elapsed time: 00:00:09
+    Info: Total CPU time (on all processors): 00:00:11
+
+
diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
new file mode 100644
index 0000000..219f117
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.tan.summary
@@ -0,0 +1,296 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type           : Worst-case tsu
+Slack          : -4.528 ns
+Required Time  : 1.000 ns
+Actual Time    : 5.528 ns
+From           : MAIN_CLK
+To             : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state
+From Clock     : --
+To Clock       : MAIN_CLK
+Failed Paths   : 6867
+
+Type           : Worst-case tco
+Slack          : -14.840 ns
+Required Time  : 1.000 ns
+Actual Time    : 15.840 ns
+From           : interrupt_handler:nobody|INT_LATCH[8]
+To             : nIRQ[5]
+From Clock     : MAIN_CLK
+To Clock       : --
+Failed Paths   : 4976
+
+Type           : Worst-case tpd
+Slack          : -11.944 ns
+Required Time  : 1.000 ns
+Actual Time    : 12.944 ns
+From           : nFB_CS1
+To             : FB_AD[18]
+From Clock     : --
+To Clock       : --
+Failed Paths   : 514
+
+Type           : Worst-case th
+Slack          : -0.401 ns
+Required Time  : 1.000 ns
+Actual Time    : 1.401 ns
+From           : FB_AD[25]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]
+From Clock     : --
+To Clock       : MAIN_CLK
+Failed Paths   : 117
+
+Type           : Clock Setup: 'CLK33M'
+Slack          : -5.966 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
+To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+To Clock       : CLK33M
+Failed Paths   : 3741
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+Slack          : -4.615 ns
+Required Time  : 24.98 MHz ( period = 40.033 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
+To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
+From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+Failed Paths   : 3741
+
+Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+Slack          : -4.294 ns
+Required Time  : 95.92 MHz ( period = 10.425 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
+To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+Failed Paths   : 3741
+
+Type           : Clock Setup: 'MAIN_CLK'
+Slack          : -4.261 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+To Clock       : MAIN_CLK
+Failed Paths   : 27347
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : -2.673 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 86
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+Slack          : -1.712 ns
+Required Time  : 66.00 MHz ( period = 15.151 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+Failed Paths   : 29
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : 1.672 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+Slack          : 2.965 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 5.299 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+Slack          : 28.590 ns
+Required Time  : 15.99 MHz ( period = 62.552 ns )
+Actual Time    : 186.15 MHz ( period = 5.372 ns )
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+Slack          : 498.663 ns
+Required Time  : 2.00 MHz ( period = 500.416 ns )
+Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+Slack          : 1997.239 ns
+Required Time  : 0.50 MHz ( period = 1999.998 ns )
+Actual Time    : 362.45 MHz ( period = 2.759 ns )
+From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]
+To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]
+From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'MAIN_CLK'
+Slack          : -3.786 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]
+From Clock     : MAIN_CLK
+To Clock       : MAIN_CLK
+Failed Paths   : 108
+
+Type           : Clock Hold: 'CLK33M'
+Slack          : -0.687 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+From Clock     : CLK33M
+To Clock       : CLK33M
+Failed Paths   : 26
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
+Slack          : -0.454 ns
+Required Time  : 24.98 MHz ( period = 40.033 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+Failed Paths   : 26
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+Slack          : 0.502 ns
+Required Time  : 15.99 MHz ( period = 62.552 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : 0.502 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
+To             : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+Slack          : 0.502 ns
+Required Time  : 95.92 MHz ( period = 10.425 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
+Slack          : 0.564 ns
+Required Time  : 2.00 MHz ( period = 500.416 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
+Slack          : 0.825 ns
+Required Time  : 0.50 MHz ( period = 1999.998 ns )
+Actual Time    : N/A
+From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
+To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
+From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 1.825 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+Slack          : 2.664 ns
+Required Time  : 66.00 MHz ( period = 15.151 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : 3.263 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+Slack          : 4.336 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Total number of failed paths
+Slack          : 
+Required Time  : 
+Actual Time    : 
+From           : 
+To             : 
+From Clock     : 
+To Clock       : 
+Failed Paths   : 51319
+
+--------------------------------------------------------------------------------------
+
diff --git a/FPGA_by_Fredi/firebee1_assignment_defaults.qdf b/FPGA_by_Fredi/firebee1_assignment_defaults.qdf
new file mode 100644
index 0000000..2119467
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1_assignment_defaults.qdf
@@ -0,0 +1,687 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 08:49:57  June 14, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV E"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS -value ON
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Arria II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy IV"
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
diff --git a/FPGA_by_Fredi/firebeei1.qpf b/FPGA_by_Fredi/firebeei1.qpf
new file mode 100644
index 0000000..8ab6c97
--- /dev/null
+++ b/FPGA_by_Fredi/firebeei1.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2008 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "8.1"
+DATE = "10:07:29  September 03, 2009"
+
+
+# Revisions
+
+PROJECT_REVISION = "firebee1"
diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws
new file mode 100644
index 0000000..89bdcec
--- /dev/null
+++ b/FPGA_by_Fredi/firebeei1.qws
@@ -0,0 +1,27 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+ptn_Child2=Document-1
+ptn_Child3=Document-2
+ptn_Child4=Document-3
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=firebee1.bdf
+DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
+IsChildFrameDetached=False
+IsActiveChildFrame=False
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-1]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
+DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
+IsChildFrameDetached=False
+IsActiveChildFrame=False
+ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
diff --git a/FPGA_by_Fredi/lpm_bustri_BYT.bsf b/FPGA_by_Fredi/lpm_bustri_BYT.bsf
new file mode 100644
index 0000000..dcc4b63
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_BYT.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 40)
+	(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 96 24)
+		(bidir)
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "8" (rect 71 25 76 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 66 28)(pt 74 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_bustri_BYT.cmp b/FPGA_by_Fredi/lpm_bustri_BYT.cmp
new file mode 100644
index 0000000..3cf925e
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_BYT.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri_BYT
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_bustri_BYT.inc b/FPGA_by_Fredi/lpm_bustri_BYT.inc
new file mode 100644
index 0000000..8cb4941
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_BYT.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_BYT 
+(
+	data[7..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[7..0]
+);
diff --git a/FPGA_by_Fredi/lpm_bustri_BYT.qip b/FPGA_by_Fredi/lpm_bustri_BYT.qip
new file mode 100644
index 0000000..89e40bd
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_BYT.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.cmp"]
diff --git a/FPGA_by_Fredi/lpm_bustri_BYT.vhd b/FPGA_by_Fredi/lpm_bustri_BYT.vhd
new file mode 100644
index 0000000..d24e3cb
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_BYT.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_BYT.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_BYT IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_bustri_BYT;
+
+
+ARCHITECTURE SYN OF lpm_bustri_byt IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 8
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
+-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_bustri_LONG.bsf b/FPGA_by_Fredi/lpm_bustri_LONG.bsf
new file mode 100644
index 0000000..6535d3e
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_LONG.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 112 40)
+	(text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 112 24)
+		(bidir)
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 112 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "32" (rect 77 25 87 37)(font "Arial" ))
+		(text "32" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_bustri_LONG.cmp b/FPGA_by_Fredi/lpm_bustri_LONG.cmp
new file mode 100644
index 0000000..3a268db
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_LONG.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri_LONG
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_bustri_LONG.inc b/FPGA_by_Fredi/lpm_bustri_LONG.inc
new file mode 100644
index 0000000..f180c48
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_LONG.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_LONG 
+(
+	data[31..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[31..0]
+);
diff --git a/FPGA_by_Fredi/lpm_bustri_LONG.qip b/FPGA_by_Fredi/lpm_bustri_LONG.qip
new file mode 100644
index 0000000..67b7232
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_LONG.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.cmp"]
diff --git a/FPGA_by_Fredi/lpm_bustri_LONG.vhd b/FPGA_by_Fredi/lpm_bustri_LONG.vhd
new file mode 100644
index 0000000..3de83c0
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_LONG.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_LONG.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_LONG IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_bustri_LONG;
+
+
+ARCHITECTURE SYN OF lpm_bustri_long IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
+-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_bustri_WORD.bsf b/FPGA_by_Fredi/lpm_bustri_WORD.bsf
new file mode 100644
index 0000000..4e882d1
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_WORD.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 112 40)
+	(text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 112 24)
+		(bidir)
+		(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 112 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "16" (rect 77 25 87 37)(font "Arial" ))
+		(text "16" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_bustri_WORD.cmp b/FPGA_by_Fredi/lpm_bustri_WORD.cmp
new file mode 100644
index 0000000..1f03a0e
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_WORD.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_bustri_WORD
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_bustri_WORD.inc b/FPGA_by_Fredi/lpm_bustri_WORD.inc
new file mode 100644
index 0000000..09f6251
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_WORD.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_WORD 
+(
+	data[15..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[15..0]
+);
diff --git a/FPGA_by_Fredi/lpm_bustri_WORD.qip b/FPGA_by_Fredi/lpm_bustri_WORD.qip
new file mode 100644
index 0000000..57bbe2e
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_WORD.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.cmp"]
diff --git a/FPGA_by_Fredi/lpm_bustri_WORD.vhd b/FPGA_by_Fredi/lpm_bustri_WORD.vhd
new file mode 100644
index 0000000..85cbdd1
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_bustri_WORD.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_WORD.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_WORD IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_bustri_WORD;
+
+
+ARCHITECTURE SYN OF lpm_bustri_word IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 16
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
+-- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_counter0.bsf b/FPGA_by_Fredi/lpm_counter0.bsf
new file mode 100644
index 0000000..7fc7aaa
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter0.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 64)
+	(text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 48 25 60)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "up counter" (rect 84 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 48)(line_width 1))
+		(line (pt 128 48)(pt 16 48)(line_width 1))
+		(line (pt 16 48)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_counter0.cmp b/FPGA_by_Fredi/lpm_counter0.cmp
new file mode 100644
index 0000000..ad18248
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter0.cmp
@@ -0,0 +1,22 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_counter0
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_counter0.qip b/FPGA_by_Fredi/lpm_counter0.qip
new file mode 100644
index 0000000..a72845b
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"]
diff --git a/FPGA_by_Fredi/lpm_counter0.vhd b/FPGA_by_Fredi/lpm_counter0.vhd
new file mode 100644
index 0000000..9135dbc
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter0.vhd
@@ -0,0 +1,126 @@
+-- megafunction wizard: %LPM_COUNTER%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_counter 
+
+-- ============================================================
+-- File Name: lpm_counter0.vhd
+-- Megafunction Name(s):
+-- 			lpm_counter
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_counter0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+END lpm_counter0;
+
+
+ARCHITECTURE SYN OF lpm_counter0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (17 DOWNTO 0);
+
+
+
+	COMPONENT lpm_counter
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_port_updown		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(17 DOWNTO 0);
+
+	lpm_counter_component : lpm_counter
+	GENERIC MAP (
+		lpm_direction => "UP",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_type => "LPM_COUNTER",
+		lpm_width => 18
+	)
+	PORT MAP (
+		clock => clock,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: Direction NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "18"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_counter0_wave0.jpg b/FPGA_by_Fredi/lpm_counter0_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/lpm_counter0_waveforms.html b/FPGA_by_Fredi/lpm_counter0_waveforms.html
new file mode 100644
index 0000000..b166f94
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter0_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for lpm_counter0.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file lpm_counter0.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter. </P>
+<CENTER><img src=lpm_counter0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/lpm_counter1_waveforms.html b/FPGA_by_Fredi/lpm_counter1_waveforms.html
new file mode 100644
index 0000000..cea3320
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for lpm_counter1.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file lpm_counter1.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter. </P>
+<CENTER><img src=lpm_counter1_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
+<P><FONT size=3></P>
+<CENTER><img src=lpm_counter1_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Wave showing counter cout and/or modulus operation. </CENTER></P>
+<P><FONT size=3>The counter counts till the modulus value 7. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
new file mode 100644
index 0000000..12ad5c2
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
+<P>The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd".  The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
+<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>
+<CENTER><img src=lpm_fifo_dc0_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/lpm_latch0.bsf b/FPGA_by_Fredi/lpm_latch0.bsf
new file mode 100644
index 0000000..ddb325c
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_latch0.bsf
@@ -0,0 +1,53 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 80)
+	(text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 64)(line_width 1))
+		(line (pt 144 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_latch0.cmp b/FPGA_by_Fredi/lpm_latch0.cmp
new file mode 100644
index 0000000..87fbc04
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_latch0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_latch0
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_latch0.qip b/FPGA_by_Fredi/lpm_latch0.qip
new file mode 100644
index 0000000..1bda27a
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_latch0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_LATCH"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.cmp"]
diff --git a/FPGA_by_Fredi/lpm_latch0.vhd b/FPGA_by_Fredi/lpm_latch0.vhd
new file mode 100644
index 0000000..1eda161
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_latch0.vhd
@@ -0,0 +1,110 @@
+-- megafunction wizard: %LPM_LATCH%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_latch 
+
+-- ============================================================
+-- File Name: lpm_latch0.vhd
+-- Megafunction Name(s):
+-- 			lpm_latch
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_latch0 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_latch0;
+
+
+ARCHITECTURE SYN OF lpm_latch0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_latch
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			gate	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_latch_component : lpm_latch
+	GENERIC MAP (
+		lpm_type => "LPM_LATCH",
+		lpm_width => 32
+	)
+	PORT MAP (
+		data => data,
+		gate => gate,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: aset NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/serv_req_info.txt b/FPGA_by_Fredi/serv_req_info.txt
new file mode 100644
index 0000000..51a4176
--- /dev/null
+++ b/FPGA_by_Fredi/serv_req_info.txt
@@ -0,0 +1,115 @@
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>VDB</sub_system>
+	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
+	<line>4101</line>
+	<callstack>
+	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
+	</callstack>
+	<error>loc &lt; m_value-&gt;size()</error>
+	<date>Tue Oct 13 17:01:46 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>loc &lt; m_value-&gt;size()
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>VDB</sub_system>
+	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
+	<line>4101</line>
+	<callstack>
+	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
+	</callstack>
+	<error>loc &lt; m_value-&gt;size()</error>
+	<date>Tue Oct 13 17:11:00 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>loc &lt; m_value-&gt;size()
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: GED</error>
+	<date>Wed Oct 14 23:17:06 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: GED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: SFW, STED</error>
+	<date>Thu Oct 15 19:23:19 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: SFW, STED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<callstack>
+	0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
+	</callstack>
+	<error>Current editor: RPW, SFW
+Current dockable window: PJN</error>
+	<date>Fri Oct 16 00:14:03 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 0X1002D196
+Current editor: RPW, SFW
+Current dockable window: PJN
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: SFW</error>
+	<date>Sat Oct 17 19:01:54 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: SFW
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>AFC</sub_system>
+	<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
+	<line>1940</line>
+	<callstack>
+	0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
+	</callstack>
+	<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
+	<date>Mon Oct 19 21:58:36 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: RPW, GED</error>
+	<date>Tue Oct 20 00:53:11 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: RPW, GED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt
new file mode 100644
index 0000000..e69de29

From 68129dbe57fc710d2348563b7b44b527c42bde02 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20G=C3=A1lvez?= <dgalvez75@gmail.com>
Date: Mon, 9 Apr 2018 17:19:13 +0200
Subject: [PATCH 02/16] Sync with Fredi's source tree 13/06/2015

Parallel port fix.
---
 FPGA_by_Fredi/BLITTER.tdf                     |  314 +
 FPGA_by_Fredi/BLITTER.tdf.bak                 |  313 +
 FPGA_by_Fredi/DSP/dsp56k.zip                  |  Bin 39208 -> 0 bytes
 .../FalconIO_SDCard_IDE_CF.vhd                |  319 +-
 .../FalconIO_SDCard_IDE_CF.vhd.bak            |  322 +-
 .../wf68901ip_interrupts.vhd.bak              |  391 +
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd        |    4 +-
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd.bak    |  229 +
 .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd   |  166 +-
 .../wf6850ip_ctrl_status.vhd.bak              |  178 +-
 .../wf6850ip_receive - Kopie.vhd              |  419 +
 .../WF_UART6850_IP/wf6850ip_receive.vhd       |  316 +-
 .../WF_UART6850_IP/wf6850ip_receive.vhd.bak   |  324 +-
 .../WF_UART6850_IP/wf6850ip_transmit.vhd      |  147 +-
 .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak  |  145 +-
 .../Interrupt_Handler/interrupt_handler.tdf   |  182 +-
 .../interrupt_handler.tdf.bak                 |  182 +-
 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt            |   20 +
 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd       |   75 -
 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak   |   75 -
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf   |  110 +
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp   |   26 +
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc   |   27 +
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip   |    6 +
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf   |  181 +
 .../Video/BLITTER/altsyncram0_wave0.jpg       |  Bin 0 -> 90072 bytes
 .../Video/BLITTER/altsyncram0_waveforms.html  |   13 +
 FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT   |  427 +
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf  |   54 +
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp  |   23 +
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc  |   24 +
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip  |    6 +
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf  |   92 +
 FPGA_by_Fredi/Video/DDR_CTR.tdf               |    6 +-
 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak           |    1 -
 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf |    2 +-
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       |    6 +-
 FPGA_by_Fredi/Video/Video.bdf                 |  380 +-
 FPGA_by_Fredi/Video/altdpram0_wave0.jpg       |  Bin 125146 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram0_wave1.jpg       |  Bin 171723 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram1_wave0.jpg       |  Bin 151954 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram1_wave1.jpg       |  Bin 203609 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram2_wave0.jpg       |  Bin 152433 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram2_wave1.jpg       |  Bin 204342 -> 0 bytes
 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg    |  Bin 30655 -> 0 bytes
 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg      |  Bin 86257 -> 0 bytes
 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg    |  Bin 121926 -> 0 bytes
 FPGA_by_Fredi/altiobuf_bidir0.bsf             |   71 +
 FPGA_by_Fredi/altiobuf_bidir0.cmp             |   24 +
 FPGA_by_Fredi/altiobuf_bidir0.inc             |   25 +
 FPGA_by_Fredi/altiobuf_bidir0.qip             |    6 +
 FPGA_by_Fredi/altiobuf_bidir0.tdf             |   90 +
 .../altiobuf_bidir0_iobuf_bidir_quo.tdf       |   53 +
 FPGA_by_Fredi/altpll1.bsf                     |  120 +-
 FPGA_by_Fredi/altpll1.vhd                     |   46 +-
 FPGA_by_Fredi/altpll3.bsf                     |  137 +-
 FPGA_by_Fredi/altpll3.cmp                     |    3 +-
 FPGA_by_Fredi/altpll3.inc                     |    3 +-
 FPGA_by_Fredi/altpll3.ppf                     |    1 +
 FPGA_by_Fredi/altpll3.vhd                     |  108 +-
 FPGA_by_Fredi/firebee1.asm.rpt                |  128 -
 FPGA_by_Fredi/firebee1.bdf                    | 5016 +++++-----
 FPGA_by_Fredi/firebee1.done                   |    2 +-
 FPGA_by_Fredi/firebee1.fit.rpt                | 6866 -------------
 FPGA_by_Fredi/firebee1.fit.summary            |   12 +-
 FPGA_by_Fredi/firebee1.flow.rpt               |  380 -
 FPGA_by_Fredi/firebee1.map.rpt                | 8590 -----------------
 FPGA_by_Fredi/firebee1.map.summary            |   12 +-
 FPGA_by_Fredi/firebee1.pin                    |   96 +-
 FPGA_by_Fredi/firebee1.qsf                    |  448 +-
 FPGA_by_Fredi/firebee1.rbf                    |  Bin 428953 -> 0 bytes
 FPGA_by_Fredi/firebee1.sof                    |  Bin 1171297 -> 0 bytes
 FPGA_by_Fredi/firebee1.sta.summary            |  857 ++
 FPGA_by_Fredi/firebee1.tan.rpt                | 6936 -------------
 FPGA_by_Fredi/firebee1.tan.summary            |  278 +-
 FPGA_by_Fredi/firebeei1.qws                   |   27 -
 FPGA_by_Fredi/incremental_db/README           |   11 +
 .../firebee1.root_partition.cmp.cdb           |  Bin 0 -> 957707 bytes
 .../firebee1.root_partition.cmp.dfp           |  Bin 0 -> 33 bytes
 .../firebee1.root_partition.cmp.hdb           |  Bin 0 -> 311894 bytes
 .../firebee1.root_partition.cmp.kpt           |  Bin 0 -> 209 bytes
 .../firebee1.root_partition.cmp.logdb         |    5 +
 .../firebee1.root_partition.cmp.rcfdb         |  Bin 0 -> 1235709 bytes
 .../firebee1.root_partition.cmp.re.rcfdb      |  Bin 0 -> 1334605 bytes
 .../firebee1.root_partition.map.cdb           |  Bin 0 -> 627274 bytes
 .../firebee1.root_partition.map.dpi           |  Bin 0 -> 34612 bytes
 .../firebee1.root_partition.map.hdb           |  Bin 0 -> 322501 bytes
 .../firebee1.root_partition.map.kpt           |  Bin 0 -> 152376 bytes
 .../firebee1.root_partition.merge_hb.atm      |  Bin 0 -> 349010 bytes
 FPGA_by_Fredi/lpm_counter1.bsf                |   56 +
 FPGA_by_Fredi/lpm_counter1.cmp                |   23 +
 FPGA_by_Fredi/lpm_counter1.inc                |   24 +
 FPGA_by_Fredi/lpm_counter1.qip                |    6 +
 FPGA_by_Fredi/lpm_counter1.tdf                |  103 +
 FPGA_by_Fredi/lpm_counter1_wave0.jpg          |  Bin 0 -> 57012 bytes
 FPGA_by_Fredi/lpm_counter1_waveforms.html     |   11 +-
 FPGA_by_Fredi/lpm_mux0.bsf                    | 1838 ++++
 FPGA_by_Fredi/lpm_mux0.cmp                    |  278 +
 FPGA_by_Fredi/lpm_mux0.inc                    |  279 +
 FPGA_by_Fredi/lpm_mux0.qip                    |    6 +
 FPGA_by_Fredi/lpm_mux0.tdf                    | 1105 +++
 FPGA_by_Fredi/lpm_shiftreg0.bsf               |   56 +
 FPGA_by_Fredi/lpm_shiftreg0.cmp               |   23 +
 FPGA_by_Fredi/lpm_shiftreg0.inc               |   24 +
 FPGA_by_Fredi/lpm_shiftreg0.qip               |    6 +
 FPGA_by_Fredi/lpm_shiftreg0.tdf               |   98 +
 FPGA_by_Fredi/undo_redo.txt                   |   27 +
 107 files changed, 12435 insertions(+), 27384 deletions(-)
 create mode 100644 FPGA_by_Fredi/BLITTER.tdf
 create mode 100644 FPGA_by_Fredi/BLITTER.tdf.bak
 delete mode 100644 FPGA_by_Fredi/DSP/dsp56k.zip
 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd
 create mode 100644 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0.bsf
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0.cmp
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0.inc
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0.qip
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0.tdf
 create mode 100644 FPGA_by_Fredi/altiobuf_bidir0_iobuf_bidir_quo.tdf
 delete mode 100644 FPGA_by_Fredi/firebee1.asm.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.fit.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.flow.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.map.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.rbf
 delete mode 100644 FPGA_by_Fredi/firebee1.sof
 create mode 100644 FPGA_by_Fredi/firebee1.sta.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.tan.rpt
 delete mode 100644 FPGA_by_Fredi/firebeei1.qws
 create mode 100644 FPGA_by_Fredi/incremental_db/README
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.re.rcfdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.dpi
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.hdb
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.kpt
 create mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm
 create mode 100644 FPGA_by_Fredi/lpm_counter1.bsf
 create mode 100644 FPGA_by_Fredi/lpm_counter1.cmp
 create mode 100644 FPGA_by_Fredi/lpm_counter1.inc
 create mode 100644 FPGA_by_Fredi/lpm_counter1.qip
 create mode 100644 FPGA_by_Fredi/lpm_counter1.tdf
 create mode 100644 FPGA_by_Fredi/lpm_counter1_wave0.jpg
 create mode 100644 FPGA_by_Fredi/lpm_mux0.bsf
 create mode 100644 FPGA_by_Fredi/lpm_mux0.cmp
 create mode 100644 FPGA_by_Fredi/lpm_mux0.inc
 create mode 100644 FPGA_by_Fredi/lpm_mux0.qip
 create mode 100644 FPGA_by_Fredi/lpm_mux0.tdf
 create mode 100644 FPGA_by_Fredi/lpm_shiftreg0.bsf
 create mode 100644 FPGA_by_Fredi/lpm_shiftreg0.cmp
 create mode 100644 FPGA_by_Fredi/lpm_shiftreg0.inc
 create mode 100644 FPGA_by_Fredi/lpm_shiftreg0.qip
 create mode 100644 FPGA_by_Fredi/lpm_shiftreg0.tdf

diff --git a/FPGA_by_Fredi/BLITTER.tdf b/FPGA_by_Fredi/BLITTER.tdf
new file mode 100644
index 0000000..536bd9a
--- /dev/null
+++ b/FPGA_by_Fredi/BLITTER.tdf
@@ -0,0 +1,314 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
+-- Created on Sat Jan 15 11:06:17 2011
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
+INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
+
+CONSTANT	BL_SKEW_LF = 255;
+
+--  Title Statement (optional)
+TITLE "Blitter";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ON : INPUT;
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	DDRCLK0 : INPUT;
+	BLITTER_DIN[127..0] : INPUT;
+	BLITTER_DACK[4..0] : INPUT;
+	SR_BLITTER_DACK : INPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_ADR[31..0] : OUTPUT;
+	BLITTER_SIG : OUTPUT;
+	BLITTER_WR : OUTPUT;
+	BLITTER_TA : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	BLITTER_CS					:NODE;
+	BL_BUSY						:NODE;
+	BL_HRAM_CS 					:NODE;
+	BL_HRAM_ADR[3..0]			:NODE;
+	BL_HRAM_OUT[15..0]			:NODE;
+	BL_HRAM_BE[1..0]			:NODE;
+	BL_SRC_X_INC_CS				:NODE;
+	BL_SRC_X_INC[15..0]			:DFFE;
+	BL_SRC_Y_INC_CS				:NODE;
+	BL_SRC_Y_INC[15..0]			:DFFE;
+	BL_ENDMASK1_CS				:NODE;
+	BL_ENDMASK1[15..0]			:DFFE;
+	BL_ENDMASK2_CS				:NODE;
+	BL_ENDMASK2[15..0]			:DFFE;
+	BL_ENDMASK3_CS				:NODE;
+	BL_ENDMASK3[15..0]			:DFFE;
+	BL_SRC_ADRH_CS				:NODE;
+	BL_SRC_ADRL_CS				:NODE;
+	BL_SRC_ADR[31..0]			:DFFE;
+	BL_DST_X_INC_CS				:NODE;
+	BL_DST_X_INC[15..0]			:DFFE;
+	BL_DST_Y_INC_CS				:NODE;
+	BL_DST_Y_INC[15..0]			:DFFE;
+	BL_DST_ADRH_CS				:NODE;
+	BL_DST_ADRL_CS				:NODE;
+	BL_DST_ADR[31..0]			:DFFE;
+	BL_X_CNT_CS					:NODE;
+	BL_X_CNT[15..0]				:DFFE;
+	BL_Y_CNT_CS					:NODE;
+	BL_Y_CNT[15..0]				:DFFE;
+	BL_HT_OP_CS					:NODE;
+	BL_HT_OP[7..0]				:DFFE;
+	BL_LC_OP[7..0]				:DFFE;
+	BL_LN_CS					:NODE;
+	BL_LN[7..0]					:DFFE;
+	BL_SKEW[7..0]				:DFFE;
+	
+	BL_SKEW_EXT[6..0]			:NODE;
+	BL_SKEW_IN[255..0]			:DFFE;
+	BL_SKEW_OUT[255..0]			:NODE;
+	
+	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
+	BL_READ_SRC					:DFFE;
+	BL_DST_BUFFER[127..0]		:DFFE;
+	BL_READ_DST					:DFFE;
+	
+	HOP_OUT[127..0]				:NODE;
+	
+	COUNT[18..0]				:DFF;
+	
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- BLITTER CS
+	BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40  
+	BLITTER_TA = BLITTER_CS;
+-- REGISTER
+	-- HALFTON RAM 
+	BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50";			-- $F8A00/20
+	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
+	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
+	BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1] 
+				 # !BL_HRAM_CS & BL_LN[3..0];
+	BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
+	-- SRC X INC
+	BL_SRC_X_INC[].CLK = MAIN_CLK;
+	BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510";		-- $F8A20/2
+	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC Y INC
+	BL_SRC_Y_INC[].CLK = MAIN_CLK;
+	BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511";		-- $F8A22/2
+	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR HIGH
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
+	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR LOW
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
+	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 1
+	BL_ENDMASK1[].CLK = MAIN_CLK;
+	BL_ENDMASK1[] = FB_AD[31..16];
+	BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514";		-- $F8A28/2
+	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 2
+	BL_ENDMASK2[].CLK = MAIN_CLK;
+	BL_ENDMASK2[] = FB_AD[31..16];
+	BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515";		-- $F8A2A/2
+	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 3
+	BL_ENDMASK3[].CLK = MAIN_CLK;
+	BL_ENDMASK3[] = FB_AD[31..16];
+	BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516";		-- $F8A2C/2
+	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
+	-- DST X INC
+	BL_DST_X_INC[].CLK = MAIN_CLK;
+	BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517";		-- $F8A2E/2
+	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
+	-- DST Y INC
+	BL_DST_Y_INC[].CLK = MAIN_CLK;
+	BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518";		-- $F8A30/2
+	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- DST ADR HIGH
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
+	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
+	-- DST ADR LOW
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
+	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
+	-- X COUNT
+	BL_X_CNT[].CLK = MAIN_CLK;
+	BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
+	BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B";			-- $F8A36/2
+	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
+	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
+	-- Y COUNT
+	BL_Y_CNT[].CLK = MAIN_CLK;
+	BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
+	BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C";			-- $F8A38/2
+	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
+	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
+	-- HALFTONE OP BYT
+	BL_HT_OP[].CLK = MAIN_CLK;
+	BL_HT_OP[] = FB_AD[31..24];
+	BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D";			-- $F8A3A/2
+	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
+	-- LOGIC OP BYT
+	BL_LC_OP[].CLK = MAIN_CLK;
+	BL_LC_OP[] = FB_AD[23..16];
+	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;				-- $F8A3B
+	-- LINE NUMBER BYT
+	BL_LN[].CLK = MAIN_CLK;
+	BL_LN[] = !BL_BUSY & FB_AD[31..24];
+	BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E";			-- $F8A3C/2
+	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
+	-- SKEW BYT
+	BL_SKEW[].CLK = MAIN_CLK;
+	BL_SKEW[] = FB_AD[31..24];
+	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;					-- $F8A3D
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						BL_HRAM_CS	    & BL_HRAM_OUT[]
+					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
+					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
+					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
+					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
+					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
+					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
+					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
+					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
+					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
+					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
+					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
+					  # BL_X_CNT_CS 	& BL_X_CNT[]
+					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
+					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
+					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
+					  ,BLITTER_CS & !nFB_OE); 								-- FFFF8A00-3F/40
+-----------------------------------------
+--  
+	BL_READ_SRC.CLK = DDRCLK0;
+	BL_READ_DST.CLK = DDRCLK0;
+	
+-- READY SIGNAL 1 CLOCK SPÄTER
+	BL_DATA_DDR_READY.CLK	= DDRCLK0;
+	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
+-- SRC BUFFER LADEN
+	BL_SKEW_IN[].CLK = DDRCLK0;
+	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
+	BL_SKEW_IN[255..128] = BLITTER_DIN[];
+	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
+-- DST BUFFER LADEN	
+	BL_DST_BUFFER[].CLK = DDRCLK0;
+	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
+	BL_DST_BUFFER[] = BLITTER_DIN[];
+-- SKEW EXTENDET
+	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
+	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
+-- SKEW EXT MUX
+	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
+-- HOP
+	IF BL_HT_OP[1..0]==B"00" THEN
+		HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+	ELSE 
+		IF BL_HT_OP[1..0]==B"01" THEN
+			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+		ELSE
+			IF BL_HT_OP[1..0]==B"10" THEN
+				HOP_OUT[] = BL_SKEW_OUT[127..0];
+			ELSE 
+				HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+			END IF;
+		END IF;
+	END IF;
+
+			
+		
+	BLITTER_RUN = GND; --VCC;
+	BLITTER_SIG = GND; --VCC;
+	BLITTER_WR = GND; --VCC;
+	BL_BUSY = GND;
+	
+	COUNT[] = COUNT[] + 16;
+	COUNT[].CLK = BLITTER_DACK0;
+	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
+	BLITTER_ADR[] = (0, COUNT[]) + 400000;
+	
+END;
+
diff --git a/FPGA_by_Fredi/BLITTER.tdf.bak b/FPGA_by_Fredi/BLITTER.tdf.bak
new file mode 100644
index 0000000..b80e5c2
--- /dev/null
+++ b/FPGA_by_Fredi/BLITTER.tdf.bak
@@ -0,0 +1,313 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
+-- Created on Sat Jan 15 11:06:17 2011
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
+INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
+
+CONSTANT	BL_SKEW_LF = 255;
+
+--  Title Statement (optional)
+TITLE "Blitter";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ON : INPUT;
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	DDRCLK0 : INPUT;
+	BLITTER_DIN[127..0] : INPUT;
+	BLITTER_DACK[4..0] : INPUT;
+	SR_BLITTER_DACK : INPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_ADR[31..0] : OUTPUT;
+	BLITTER_SIG : OUTPUT;
+	BLITTER_WR : OUTPUT;
+	BLITTER_TA : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	BLITTER_CS					:NODE;
+	BL_BUSY						:NODE;
+	BL_HRAM_CS 					:NODE;
+	BL_HRAM_ADR[3..0]			:NODE;
+	BL_HRAM_OUT[15..0]			:NODE;
+	BL_HRAM_BE[1..0]			:NODE;
+	BL_SRC_X_INC_CS				:NODE;
+	BL_SRC_X_INC[15..0]			:DFFE;
+	BL_SRC_Y_INC_CS				:NODE;
+	BL_SRC_Y_INC[15..0]			:DFFE;
+	BL_ENDMASK1_CS				:NODE;
+	BL_ENDMASK1[15..0]			:DFFE;
+	BL_ENDMASK2_CS				:NODE;
+	BL_ENDMASK2[15..0]			:DFFE;
+	BL_ENDMASK3_CS				:NODE;
+	BL_ENDMASK3[15..0]			:DFFE;
+	BL_SRC_ADRH_CS				:NODE;
+	BL_SRC_ADRL_CS				:NODE;
+	BL_SRC_ADR[31..0]			:DFFE;
+	BL_DST_X_INC_CS				:NODE;
+	BL_DST_X_INC[15..0]			:DFFE;
+	BL_DST_Y_INC_CS				:NODE;
+	BL_DST_Y_INC[15..0]			:DFFE;
+	BL_DST_ADRH_CS				:NODE;
+	BL_DST_ADRL_CS				:NODE;
+	BL_DST_ADR[31..0]			:DFFE;
+	BL_X_CNT_CS					:NODE;
+	BL_X_CNT[15..0]				:DFFE;
+	BL_Y_CNT_CS					:NODE;
+	BL_Y_CNT[15..0]				:DFFE;
+	BL_HT_OP_CS					:NODE;
+	BL_HT_OP[7..0]				:DFFE;
+	BL_LC_OP[7..0]				:DFFE;
+	BL_LN_CS					:NODE;
+	BL_LN[7..0]					:DFFE;
+	BL_SKEW[7..0]				:DFFE;
+	
+	BL_SKEW_EXT[6..0]			:NODE;
+	BL_SKEW_IN[255..0]			:DFFE;
+	BL_SKEW_OUT[255..0]			:NODE;
+	
+	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
+	BL_READ_SRC					:DFFE;
+	BL_DST_BUFFER[127..0]		:DFFE;
+	BL_READ_DST					:DFFE;
+	
+	HOP_OUT[127..0]				:NODE;
+	
+	COUNT[18..0]				:DFF;
+	
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- BLITTER CS
+	BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40  
+	BLITTER_TA = BLITTER_CS;
+-- REGISTER
+	-- HALFTON RAM 
+	BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50";			-- $F8A00/20
+	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
+	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
+	BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1] 
+				 # !BL_HRAM_CS & BL_LN[3..0];
+	BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
+	-- SRC X INC
+	BL_SRC_X_INC[].CLK = MAIN_CLK;
+	BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510";		-- $F8A20/2
+	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC Y INC
+	BL_SRC_Y_INC[].CLK = MAIN_CLK;
+	BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511";		-- $F8A22/2
+	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR HIGH
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
+	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR LOW
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
+	BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
+	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 1
+	BL_ENDMASK1[].CLK = MAIN_CLK;
+	BL_ENDMASK1[] = FB_AD[31..16];
+	BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514";		-- $F8A28/2
+	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 2
+	BL_ENDMASK2[].CLK = MAIN_CLK;
+	BL_ENDMASK2[] = FB_AD[31..16];
+	BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515";		-- $F8A2A/2
+	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 3
+	BL_ENDMASK3[].CLK = MAIN_CLK;
+	BL_ENDMASK3[] = FB_AD[31..16];
+	BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516";		-- $F8A2C/2
+	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
+	-- DST X INC
+	BL_DST_X_INC[].CLK = MAIN_CLK;
+	BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517";		-- $F8A2E/2
+	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
+	-- DST Y INC
+	BL_DST_Y_INC[].CLK = MAIN_CLK;
+	BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518";		-- $F8A30/2
+	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- DST ADR HIGH
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
+	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
+	-- DST ADR LOW
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
+	BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
+	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
+	-- X COUNT
+	BL_X_CNT[].CLK = MAIN_CLK;
+	BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
+	BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B";			-- $F8A36/2
+	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
+	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
+	-- Y COUNT
+	BL_Y_CNT[].CLK = MAIN_CLK;
+	BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
+	BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C";			-- $F8A38/2
+	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
+	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
+	-- HALFTONE OP BYT
+	BL_HT_OP[].CLK = MAIN_CLK;
+	BL_HT_OP[] = FB_AD[31..24];
+	BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D";			-- $F8A3A/2
+	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
+	-- LOGIC OP BYT
+	BL_LC_OP[].CLK = MAIN_CLK;
+	BL_LC_OP[] = FB_AD[23..16];
+	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;				-- $F8A3B
+	-- LINE NUMBER BYT
+	BL_LN[].CLK = MAIN_CLK;
+	BL_LN[] = !BL_BUSY & FB_AD[31..24];
+	BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E";			-- $F8A3C/2
+	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
+	-- SKEW BYT
+	BL_SKEW[].CLK = MAIN_CLK;
+	BL_SKEW[] = FB_AD[31..24];
+	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;					-- $F8A3D
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						BL_HRAM_CS	    & BL_HRAM_OUT[]
+					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
+					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
+					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
+					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
+					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
+					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
+					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
+					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
+					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
+					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
+					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
+					  # BL_X_CNT_CS 	& BL_X_CNT[]
+					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
+					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
+					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
+					  ,BLITTER_CS & !nFB_OE); 								-- FFFF8A00-3F/40
+-----------------------------------------
+--  
+	BL_READ_SRC.CLK = DDRCLK0;
+	BL_READ_DST.CLK = DDRCLK0;
+	
+-- READY SIGNAL 1 CLOCK SPÄTER
+	BL_DATA_DDR_READY.CLK	= DDRCLK0;
+	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
+-- SRC BUFFER LADEN
+	BL_SKEW_IN[].CLK = DDRCLK0;
+	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
+	BL_SKEW_IN[255..128] = BLITTER_DIN[];
+	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
+-- DST BUFFER LADEN	
+	BL_DST_BUFFER[].CLK = DDRCLK0;
+	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
+	BL_DST_BUFFER[] = BLITTER_DIN[];
+-- SKEW EXTENDET
+	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
+	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
+-- SKEW EXT MUX
+	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
+-- HOP
+	IF BL_HT_OP[1..0]==B"00" THEN
+		HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+	ELSE 
+		IF BL_HT_OP[1..0]==B"01" THEN
+			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+		ELSE
+			IF BL_HT_OP[1..0]==B"10" THEN
+				HOP_OUT[] = BL_SKEW_OUT[127..0];
+			ELSE 
+				HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+			END IF;
+		END IF;
+	END IF;
+
+			
+		
+	BLITTER_RUN = gnd; --VCC;
+	BLITTER_SIG = gnd; --VCC;
+	BLITTER_WR = gnd; --VCC;
+	
+	COUNT[] = COUNT[] + 16;
+	COUNT[].CLK = BLITTER_DACK0;
+	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
+	BLITTER_ADR[] = (0, COUNT[]) + 400000;
+	
+END;
+
diff --git a/FPGA_by_Fredi/DSP/dsp56k.zip b/FPGA_by_Fredi/DSP/dsp56k.zip
deleted file mode 100644
index 6522299f5635ba5560150e498fbbdf0fde8328f5..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
index b2b8dbb..f3aeb16 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
@@ -115,7 +115,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		nCF_CS0 : OUT STD_LOGIC;
 		nIDE_RD : INOUT STD_LOGIC;
 		nIDE_WR : INOUT STD_LOGIC;
-		AMKB_TX : OUT STD_LOGIC;
+		AMKB_TX : buffer STD_LOGIC;
 		IDE_RES : OUT STD_LOGIC;
 		DTR : OUT STD_LOGIC;
 		RTS : OUT STD_LOGIC;
@@ -132,6 +132,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		DMA_DRQ : OUT STD_LOGIC;
 		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
 		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_PAR : INOUT STD_LOGIC;
@@ -156,12 +157,15 @@ signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
 signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
 signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
 signal LONG						: STD_LOGIC;	-- WENN  -> 1
+signal FB_ADI					: STD_LOGIC_VECTOR(15 downto 0);	-- gespeicherte writedaten
+signal nResetatio				: STD_LOGIC;	-- reset atari bausteine
 -- KEYBOARD MIDI
 signal ACIA_CS_I				: STD_LOGIC;
 signal IRQ_KEYBDn				: STD_LOGIC;
 signal IRQ_MIDIn				: STD_LOGIC;
 signal KEYB_RxD					: STD_LOGIC;
-signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal AMKB_REG					: STD_LOGIC_VECTOR(3 downto 0);
+signal AMKB_TX_sync				: std_logic;
 signal MIDI_OUT					: STD_LOGIC;
 signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
 signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
@@ -169,8 +173,8 @@ signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
 signal MFP_CS					: STD_LOGIC;
 signal MFP_INTACK				: STD_LOGIC;
 signal LDS						: STD_LOGIC;
+signal acia_irq					: STD_LOGIC;
 signal DTACK_OUT_MFPn			: STD_LOGIC;
-signal IRQ_ACIAn				: STD_LOGIC;
 signal DINTn					: STD_LOGIC;
 signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
 signal TDO						: STD_LOGIC;
@@ -180,7 +184,22 @@ signal SNDCS_I					: STD_LOGIC;
 signal SNDIR_I					: STD_LOGIC;
 signal LP_DIR_X					: STD_LOGIC;
 signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal SND_A_X					: STD_LOGIC_VECTOR(7 downto 0);
 signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal nLP_STR					: STD_LOGIC;
+-- DMA SOUND
+signal dma_snd_cs				: STD_LOGIC;
+signal sndmactl					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbashi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbasmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbaslo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrhi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrlo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendhi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendlo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndmode					: STD_LOGIC_VECTOR(7 downto 0);
 -- DIV
 signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
 signal ROM_CS					: STD_LOGIC;
@@ -265,22 +284,36 @@ signal NEXT_nIDE_WR				: STD_LOGIC;
 type CMD_STATES is(	IDLE, T1, T6, T7);
 signal CMD_STATE				: CMD_STATES;
 signal NEXT_CMD_STATE			: CMD_STATES;
+-- Paddle
+signal paddle_cs				: STD_LOGIC;
 
-	
 BEGIN
 LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
 BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
 FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
 FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
 
-FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
-				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
-SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or 
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
            '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
            '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
-nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
-nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; 
 nDREQ0 <= '0';
+-- input daten halten
+process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
+	begin
+		if rising_edge(MAIN_CLK) then
+			IF nFB_WR = '0' THEN
+				FB_ADI <= FB_AD(31 downto 16); 
+			ELSE
+				FB_ADI <= FB_ADI; 
+			end if;
+		ELSE
+			FB_ADI <= FB_ADI; 
+		end if;
+	END PROCESS;
 ----------------------------------------------------------------------------
 -- SD
 ----------------------------------------------------------------------------
@@ -386,7 +419,7 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
 			q					=> WRF_DOUT,
 			rdusedw				=> WRF_AZ
 	);
-CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); 							-- BEI DMA WRITE <-FIFO SONST <-FB
 DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
 FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
 DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
@@ -513,7 +546,7 @@ SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_
 	I_FDC: WF1772IP_TOP_SOC
 		port map(
             CLK					=> FDC_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 			CSn					=> FDCS_In,
 			RWn					=> nFDC_WR,
 			A1					=> CA2,
@@ -695,13 +728,13 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
     I_SCSI: WF5380_TOP_SOC
         port map(
             CLK					=> FDC_CLK,
-            RESETn				=> nRSTO,
+            RESETn				=> nResetatio,
 			ADR			        => CA2 & CA1 & CA0,
 			DATA_IN		        => CD_IN_FDC,	
 			DATA_OUT			=> SCSI_DOUT,
 			--DATA_EN			: out bit;
             -- Bus and DMA controls:
-			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			CSn			        => SCSI_CSn,
 			RDn		            => (not nFDC_WR) or (not SCSI_CS),
 			WRn	                =>      nFDC_WR  or (not SCSI_CS),
             EOPn                => '1',
@@ -745,18 +778,19 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
 --            MSG_EN              => MSG_EN
         );              
 -- SCSI ACSI ---------------------------------------------------------------
-SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
-SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1';-- when DB_EN = '1' else '1';	 
 SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
-nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
-nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
-nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
 ACSI_DIR <= '0';
 ACSI_D <= "ZZZZZZZZ";
 nACSI_CS <= '1';
 ACSI_A1 <= CA1;
 nACSI_RESET <= nRSTO;
 nACSI_ACK <= '1';
+nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
 ----------------------------------------------------------------------------
 -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
 ----------------------------------------------------------------------------
@@ -769,16 +803,16 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
 	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
 	  port map(
 			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 
 			CS2n				=> FB_ADR(2),
 			CS1					=> '1',
 			CS0					=> ACIA_CS_I,
-            E					=> ACIA_CS_I,
+			E					=> ACIA_CS_I,
 			RWn					=> nFB_WR,
 			RS					=> FB_ADR(1),
 
-			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_IN				=> FB_ADI(15 downto 8),
 			DATA_OUT			=> DATA_OUT_ACIA_I,
 --			DATA_EN				=> DATA_EN_ACIA_I,
 
@@ -790,40 +824,45 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
 			DCDn				=> '0',
         
 			IRQn				=> IRQ_KEYBDn,
-			TXDATA				=> AMKB_TX
+			TXDATA				=> AMKB_TX_sync
 			--RTSn				=> -- Not used.
 		);                                              
 ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
-KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
--- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL  // 
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I  when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else  
+					   DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  und sychronisieren ------------------------------------------
 	process(CLK2M, AMKB_RX, AMKB_REG)
 	begin
-		if rising_edge(CLK2M) then
+		if rising_edge(CLK500k) then
+			AMKB_TX <= AMKB_TX_sync;
 			IF AMKB_RX = '0' THEN
-				IF AMKB_REG < 16 THEN
-					AMKB_REG <= "00000";
+				IF AMKB_REG < 8 THEN
+					AMKB_REG <= "0000";
 				ELSE
 					AMKB_REG <= AMKB_REG - 1;
 				END IF;
 			ELSE
-				IF AMKB_REG > 15 THEN
-					AMKB_REG <= "11111";
+				IF AMKB_REG > 7 THEN
+					AMKB_REG <= "1111";
 				ELSE
 					AMKB_REG <= AMKB_REG + 1;
 				END IF;
 			END IF;
 		ELSE
+			AMKB_TX <= AMKB_TX;
 			AMKB_REG <= AMKB_REG;
 		end if;
 	END PROCESS;
+-- acia interrupt  ------------------------------------------
+acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
 ----------------------------------------------------------------------------
 -- ACIA MIDI
 ----------------------------------------------------------------------------
 	I_ACIA_MIDI: WF6850IP_TOP_SOC
 		port map(
 			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 
 			CS2n				=> '0',
 			CS1					=> FB_ADR(2),
@@ -832,7 +871,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
 			RWn					=> nFB_WR,
 			RS					=> FB_ADR(1),
 
-			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_IN				=> FB_ADI(15 downto 8),
 			DATA_OUT			=> DATA_OUT_ACIA_II,
 --			DATA_EN				=> DATA_EN_ACIA_II,
 
@@ -845,18 +884,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
 			IRQn				=> IRQ_MIDIn,
 			TXDATA				=> MIDI_OUT
 			--RTSn				=> -- Not used.
-	    );                                              
-MIDI_TLR <= MIDI_OUT;
+	    );
+MIDI_TLR <= MIDI_IN;
 MIDI_OLR <= MIDI_OUT;
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
 ----------------------------------------------------------------------------
 -- MFP
 ----------------------------------------------------------------------------
 	I_MFP: WF68901IP_TOP_SOC
 		port map(  
 			-- System control:
-			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			CLK					=> not MAIN_CLK,
+			RESETn				=> nResetatio,
 			-- Asynchronous bus control:
 			DSn					=> not LDS,
 			CSn					=> not MFP_CS,
@@ -867,14 +905,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
 			DATA_IN				=> FB_AD(23 downto 16),
 			DATA_OUT			=> DATA_OUT_MFP,
 --			DATA_EN				=> DATA_EN_MFP,
-            GPIP_IN(7)			=> not DMA_DRQ_Q,
-            GPIP_IN(6)			=> not RI,
+			GPIP_IN(7)			=> not DMA_DRQ_Q,
+			GPIP_IN(6)			=> not RI,
 			GPIP_IN(5)			=> DINTn,
-			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(4)			=> acia_irq,
 			GPIP_IN(3)			=> DSP_INT,
-            GPIP_IN(2)			=> not CTS,
-            GPIP_IN(1)			=> not DCD,
-            GPIP_IN(0)			=> LP_BUSY,
+			GPIP_IN(2)			=> not CTS,
+			GPIP_IN(1)			=> not DCD,
+			GPIP_IN(0)			=> LP_BUSY,
 			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
 			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
 			-- Interrupt control:
@@ -885,7 +923,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
 			-- Timers and timer control:
 			XTAL1				=> CLK2M4576,
             TAI					=> '0',
-			TBI				    => nBLANK,
+			TBI				   	=> nBLANK,
             -- TAO				=>,
 			-- TBO				=>,
             -- TCO				=>,
@@ -911,24 +949,13 @@ FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
 DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
          '0' when FDINT = '1' else
          '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
--- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
-	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
-	begin
-		if nRSTO = '0' THEN
-			IRQ_ACIAn <= '1';
-		elsif rising_edge(MAIN_CLK) then
-				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
-			else
-				IRQ_ACIAn <= IRQ_ACIAn;
-			end if;
-	END PROCESS;
-----------------------------------------------------------------------------
+ ----------------------------------------------------------------------------
 -- Sound
 ----------------------------------------------------------------------------
  	I_SOUND: WF2149IP_TOP_SOC
 		port map(
-			SYS_CLK				=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			SYS_CLK				=> not MAIN_CLK,
+			RESETn				=> nResetatio,
 
 			WAV_CLK				=> CLK2M,
 			SELn				=> '1',
@@ -939,18 +966,11 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
 
 			A9n					=> '0',
 			A8					=> '1',
-			DA_IN				=> FB_AD(31 downto 24),
+			DA_IN				=> FB_ADI(15 downto 8),
 			DA_OUT 				=> DA_OUT_X,
 
-			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
-			IO_A_OUT(7)			=> nnIDE_RES,
-            IO_A_OUT(6)			=> LP_DIR_X,
-			IO_A_OUT(5)			=> LP_STR,
-			IO_A_OUT(4)			=> DTR,
-			IO_A_OUT(3)			=> RTS,
---			IO_A_OUT(2)			=> FDD_D1SEL,
-			IO_A_OUT(1)			=> DSA_D,
-			IO_A_OUT(0)			=> nSDSEL,
+			IO_A_IN				=> SND_A,	
+			IO_A_OUT			=> SND_A_X,
 			-- IO_A_EN			=>, -- Not required.
 			IO_B_IN				=> LP_D,
 			IO_B_OUT			=> LP_D_X,
@@ -965,7 +985,170 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		--
 SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
 SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
 FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+nnIDE_RES <= SND_A_X(7);
+LP_DIR_X  <= SND_A_X(6);
+LP_STR    <= SND_A_X(5);
+DTR       <= SND_A_X(4); 
+RTS		  <= SND_A_X(3);
+-- FDD_D1SEL   <= SND_A_X(2)
+DSA_D	  <= SND_A_X(1);
+nSDSEL    <= SND_A_X(0);
+SND_A <= SND_A_X;
 LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
 LP_DIR <= LP_DIR_X;
 
+
+----------------------------------------------------------------------------
+-- DMA Sound register
+----------------------------------------------------------------------------
+
+dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';	-- F8900-F893F
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndmactl <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
+				sndmactl <= FB_AD(23 downto 16);
+			else
+				sndmactl <= sndmactl;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbashi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbashi <= FB_AD(23 downto 16);
+			else
+				sndbashi <= sndbashi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbasmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbasmi <= FB_AD(23downto 16);
+			else
+				sndbasmi <= sndbasmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbaslo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbaslo <= FB_AD(23 downto 16);
+			else
+				sndbaslo <= sndbaslo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrhi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrhi <= FB_AD(23 downto 16);
+			else
+				sndadrhi <= sndadrhi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrmi <= FB_AD(23 downto 16);
+			else
+				sndadrmi <= sndadrmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrlo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrlo <= FB_AD(23 downto 16);
+			else
+				sndadrlo <= sndadrlo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendhi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendhi <= FB_AD(23 downto 16);
+			else
+				sndendhi <= sndendhi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendmi <= FB_AD(23 downto 16);
+			else
+				sndendmi <= sndendmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendlo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendlo <= FB_AD(23 downto 16);
+			else
+				sndendlo <= sndendlo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndmode <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
+				sndmode <= FB_AD(23 downto 16);
+			else
+				sndmode <= sndmode;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";
+
+----------------------------------------------------------------------------
+-- Paddle
+----------------------------------------------------------------------------
+
+paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0';	-- F9200-F923F
+
+FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+
 END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
index a339eda..a789c9f 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
@@ -115,7 +115,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		nCF_CS0 : OUT STD_LOGIC;
 		nIDE_RD : INOUT STD_LOGIC;
 		nIDE_WR : INOUT STD_LOGIC;
-		AMKB_TX : OUT STD_LOGIC;
+		AMKB_TX : buffer STD_LOGIC;
 		IDE_RES : OUT STD_LOGIC;
 		DTR : OUT STD_LOGIC;
 		RTS : OUT STD_LOGIC;
@@ -132,6 +132,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		DMA_DRQ : OUT STD_LOGIC;
 		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
 		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_PAR : INOUT STD_LOGIC;
@@ -156,12 +157,15 @@ signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
 signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
 signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
 signal LONG						: STD_LOGIC;	-- WENN  -> 1
+signal FB_ADI					: STD_LOGIC_VECTOR(15 downto 0);	-- gespeicherte writedaten
+signal nResetatio				: STD_LOGIC;	-- reset atari bausteine
 -- KEYBOARD MIDI
 signal ACIA_CS_I				: STD_LOGIC;
 signal IRQ_KEYBDn				: STD_LOGIC;
 signal IRQ_MIDIn				: STD_LOGIC;
 signal KEYB_RxD					: STD_LOGIC;
-signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal AMKB_REG					: STD_LOGIC_VECTOR(3 downto 0);
+signal AMKB_TX_sync				: std_logic;
 signal MIDI_OUT					: STD_LOGIC;
 signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
 signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
@@ -169,8 +173,8 @@ signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
 signal MFP_CS					: STD_LOGIC;
 signal MFP_INTACK				: STD_LOGIC;
 signal LDS						: STD_LOGIC;
+signal acia_irq					: STD_LOGIC;
 signal DTACK_OUT_MFPn			: STD_LOGIC;
-signal IRQ_ACIAn				: STD_LOGIC;
 signal DINTn					: STD_LOGIC;
 signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
 signal TDO						: STD_LOGIC;
@@ -180,7 +184,22 @@ signal SNDCS_I					: STD_LOGIC;
 signal SNDIR_I					: STD_LOGIC;
 signal LP_DIR_X					: STD_LOGIC;
 signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal SND_A_X					: STD_LOGIC_VECTOR(7 downto 0);
 signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal nLP_STR					: STD_LOGIC;
+-- DMA SOUND
+signal dma_snd_cs				: STD_LOGIC;
+signal sndmactl					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbashi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbasmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndbaslo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrhi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndadrlo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendhi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendmi					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndendlo					: STD_LOGIC_VECTOR(7 downto 0);
+signal sndmode					: STD_LOGIC_VECTOR(7 downto 0);
 -- DIV
 signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
 signal ROM_CS					: STD_LOGIC;
@@ -265,22 +284,36 @@ signal NEXT_nIDE_WR				: STD_LOGIC;
 type CMD_STATES is(	IDLE, T1, T6, T7);
 signal CMD_STATE				: CMD_STATES;
 signal NEXT_CMD_STATE			: CMD_STATES;
+-- Paddle
+signal paddle_cs				: STD_LOGIC;
 
-	
 BEGIN
 LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
 BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
 FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
 FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
 
-FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
-				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
-SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or 
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
            '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
            '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
-nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
-nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; 
 nDREQ0 <= '0';
+-- input daten halten
+process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
+	begin
+		if rising_edge(MAIN_CLK) then
+			IF nFB_WR = '0' THEN
+				FB_ADI <= FB_AD(31 downto 16); 
+			ELSE
+				FB_ADI <= FB_ADI; 
+			end if;
+		ELSE
+			FB_ADI <= FB_ADI; 
+		end if;
+	END PROCESS;
 ----------------------------------------------------------------------------
 -- SD
 ----------------------------------------------------------------------------
@@ -386,7 +419,7 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
 			q					=> WRF_DOUT,
 			rdusedw				=> WRF_AZ
 	);
-CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); 							-- BEI DMA WRITE <-FIFO SONST <-FB
 DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
 FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
 DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
@@ -513,7 +546,7 @@ SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_
 	I_FDC: WF1772IP_TOP_SOC
 		port map(
             CLK					=> FDC_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 			CSn					=> FDCS_In,
 			RWn					=> nFDC_WR,
 			A1					=> CA2,
@@ -695,13 +728,13 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
     I_SCSI: WF5380_TOP_SOC
         port map(
             CLK					=> FDC_CLK,
-            RESETn				=> nRSTO,
+            RESETn				=> nResetatio,
 			ADR			        => CA2 & CA1 & CA0,
 			DATA_IN		        => CD_IN_FDC,	
 			DATA_OUT			=> SCSI_DOUT,
 			--DATA_EN			: out bit;
             -- Bus and DMA controls:
-			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			CSn			        => SCSI_CSn,
 			RDn		            => (not nFDC_WR) or (not SCSI_CS),
 			WRn	                =>      nFDC_WR  or (not SCSI_CS),
             EOPn                => '1',
@@ -745,18 +778,19 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
 --            MSG_EN              => MSG_EN
         );              
 -- SCSI ACSI ---------------------------------------------------------------
-SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
-SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1';-- when DB_EN = '1' else '1';	 
 SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
-nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
-nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
-nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
 ACSI_DIR <= '0';
 ACSI_D <= "ZZZZZZZZ";
 nACSI_CS <= '1';
 ACSI_A1 <= CA1;
 nACSI_RESET <= nRSTO;
 nACSI_ACK <= '1';
+nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
 ----------------------------------------------------------------------------
 -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
 ----------------------------------------------------------------------------
@@ -769,16 +803,16 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
 	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
 	  port map(
 			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 
 			CS2n				=> FB_ADR(2),
 			CS1					=> '1',
 			CS0					=> ACIA_CS_I,
-            E					=> ACIA_CS_I,
+			E					=> ACIA_CS_I,
 			RWn					=> nFB_WR,
 			RS					=> FB_ADR(1),
 
-			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_IN				=> FB_ADI(15 downto 8),
 			DATA_OUT			=> DATA_OUT_ACIA_I,
 --			DATA_EN				=> DATA_EN_ACIA_I,
 
@@ -790,40 +824,45 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
 			DCDn				=> '0',
         
 			IRQn				=> IRQ_KEYBDn,
-			TXDATA				=> AMKB_TX
+			TXDATA				=> AMKB_TX_sync
 			--RTSn				=> -- Not used.
 		);                                              
 ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
-KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
--- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL  // 
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I  when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else  
+					   DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  und sychronisieren ------------------------------------------
 	process(CLK2M, AMKB_RX, AMKB_REG)
 	begin
-		if rising_edge(CLK2M) then
+		if rising_edge(CLK500k) then
+			AMKB_TX <= AMKB_TX_sync;
 			IF AMKB_RX = '0' THEN
-				IF AMKB_REG < 16 THEN
-					AMKB_REG <= "00000";
+				IF AMKB_REG < 8 THEN
+					AMKB_REG <= "0000";
 				ELSE
 					AMKB_REG <= AMKB_REG - 1;
 				END IF;
 			ELSE
-				IF AMKB_REG > 15 THEN
-					AMKB_REG <= "11111";
+				IF AMKB_REG > 7 THEN
+					AMKB_REG <= "1111";
 				ELSE
 					AMKB_REG <= AMKB_REG + 1;
 				END IF;
 			END IF;
 		ELSE
+			AMKB_TX <= AMKB_TX;
 			AMKB_REG <= AMKB_REG;
 		end if;
 	END PROCESS;
+-- acia interrupt  ------------------------------------------
+acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
 ----------------------------------------------------------------------------
 -- ACIA MIDI
 ----------------------------------------------------------------------------
 	I_ACIA_MIDI: WF6850IP_TOP_SOC
 		port map(
 			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			RESETn				=> nResetatio,
 
 			CS2n				=> '0',
 			CS1					=> FB_ADR(2),
@@ -832,7 +871,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
 			RWn					=> nFB_WR,
 			RS					=> FB_ADR(1),
 
-			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_IN				=> FB_ADI(15 downto 8),
 			DATA_OUT			=> DATA_OUT_ACIA_II,
 --			DATA_EN				=> DATA_EN_ACIA_II,
 
@@ -845,18 +884,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0'
 			IRQn				=> IRQ_MIDIn,
 			TXDATA				=> MIDI_OUT
 			--RTSn				=> -- Not used.
-	    );                                              
-MIDI_TLR <= MIDI_OUT;
+	    );
+MIDI_TLR <= MIDI_IN;
 MIDI_OLR <= MIDI_OUT;
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
 ----------------------------------------------------------------------------
 -- MFP
 ----------------------------------------------------------------------------
 	I_MFP: WF68901IP_TOP_SOC
 		port map(  
 			-- System control:
-			CLK					=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			CLK					=> not MAIN_CLK,
+			RESETn				=> nResetatio,
 			-- Asynchronous bus control:
 			DSn					=> not LDS,
 			CSn					=> not MFP_CS,
@@ -867,14 +905,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
 			DATA_IN				=> FB_AD(23 downto 16),
 			DATA_OUT			=> DATA_OUT_MFP,
 --			DATA_EN				=> DATA_EN_MFP,
-            GPIP_IN(7)			=> not DMA_DRQ_Q,
-            GPIP_IN(6)			=> not RI,
+			GPIP_IN(7)			=> not DMA_DRQ_Q,
+			GPIP_IN(6)			=> not RI,
 			GPIP_IN(5)			=> DINTn,
-			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(4)			=> acia_irq,
 			GPIP_IN(3)			=> DSP_INT,
-            GPIP_IN(2)			=> not CTS,
-            GPIP_IN(1)			=> not DCD,
-            GPIP_IN(0)			=> LP_BUSY,
+			GPIP_IN(2)			=> not CTS,
+			GPIP_IN(1)			=> not DCD,
+			GPIP_IN(0)			=> LP_BUSY,
 			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
 			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
 			-- Interrupt control:
@@ -885,7 +923,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1'
 			-- Timers and timer control:
 			XTAL1				=> CLK2M4576,
             TAI					=> '0',
-			TBI				    => nBLANK,
+			TBI				   	=> nBLANK,
             -- TAO				=>,
 			-- TBO				=>,
             -- TCO				=>,
@@ -908,27 +946,16 @@ FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZ
 FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
 FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
 FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
-DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
+DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
          '0' when FDINT = '1' else
-         '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
--- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
-	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
-	begin
-		if nRSTO = '0' THEN
-			IRQ_ACIAn <= '1';
-		elsif rising_edge(MAIN_CLK) then
-				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
-			else
-				IRQ_ACIAn <= IRQ_ACIAn;
-			end if;
-	END PROCESS;
-----------------------------------------------------------------------------
+         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
+ ----------------------------------------------------------------------------
 -- Sound
 ----------------------------------------------------------------------------
  	I_SOUND: WF2149IP_TOP_SOC
 		port map(
-			SYS_CLK				=> MAIN_CLK,
-			RESETn				=> nRSTO,
+			SYS_CLK				=> not MAIN_CLK,
+			RESETn				=> nResetatio,
 
 			WAV_CLK				=> CLK2M,
 			SELn				=> '1',
@@ -939,18 +966,11 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
 
 			A9n					=> '0',
 			A8					=> '1',
-			DA_IN				=> FB_AD(31 downto 24),
+			DA_IN				=> FB_ADI(15 downto 8),
 			DA_OUT 				=> DA_OUT_X,
 
-			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
-			IO_A_OUT(7)			=> nnIDE_RES,
-            IO_A_OUT(6)			=> LP_DIR_X,
-			IO_A_OUT(5)			=> LP_STR,
-			IO_A_OUT(4)			=> DTR,
-			IO_A_OUT(3)			=> RTS,
---			IO_A_OUT(2)			=> FDD_D1SEL,
-			IO_A_OUT(1)			=> DSA_D,
-			IO_A_OUT(0)			=> nSDSEL,
+			IO_A_IN				=> SND_A,	
+			IO_A_OUT			=> SND_A_X,
 			-- IO_A_EN			=>, -- Not required.
 			IO_B_IN				=> LP_D,
 			IO_B_OUT			=> LP_D_X,
@@ -965,7 +985,169 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		--
 SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
 SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
 FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+nnIDE_RES <= SND_A_X(7);
+LP_DIR_X  <= SND_A_X(6);
+LP_STR    <= SND_A_X(5);
+DTR       <= SND_A_X(4); 
+RTS		  <= SND_A_X(3);
+-- FDD_D1SEL   <= SND_A_X(2)
+DSA_D	  <= SND_A_X(1);
+nSDSEL    <= SND_A_X(0);
 LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
 LP_DIR <= LP_DIR_X;
 
+
+----------------------------------------------------------------------------
+-- DMA Sound register
+----------------------------------------------------------------------------
+
+dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';	-- F8900-F893F
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndmactl <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
+				sndmactl <= FB_AD(23 downto 16);
+			else
+				sndmactl <= sndmactl;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbashi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbashi <= FB_AD(23 downto 16);
+			else
+				sndbashi <= sndbashi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbasmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbasmi <= FB_AD(23downto 16);
+			else
+				sndbasmi <= sndbasmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndbaslo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
+				sndbaslo <= FB_AD(23 downto 16);
+			else
+				sndbaslo <= sndbaslo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrhi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrhi <= FB_AD(23 downto 16);
+			else
+				sndadrhi <= sndadrhi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrmi <= FB_AD(23 downto 16);
+			else
+				sndadrmi <= sndadrmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndadrlo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
+				sndadrlo <= FB_AD(23 downto 16);
+			else
+				sndadrlo <= sndadrlo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendhi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendhi <= FB_AD(23 downto 16);
+			else
+				sndendhi <= sndendhi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendmi <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendmi <= FB_AD(23 downto 16);
+			else
+				sndendmi <= sndendmi;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndendlo <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
+				sndendlo <= FB_AD(23 downto 16);
+			else
+				sndendlo <= sndendlo;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";
+
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	begin
+		if nRSTO = '0' THEN
+			sndmode <= x"00";
+		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
+				sndmode <= FB_AD(23 downto 16);
+			else
+				sndmode <= sndmode;
+			end if;
+	END PROCESS;
+FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";
+
+----------------------------------------------------------------------------
+-- Paddle
+----------------------------------------------------------------------------
+
+paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0';	-- F9200-F923F
+
+FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+
 END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
new file mode 100644
index 0000000..915c271
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
@@ -0,0 +1,391 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core interrupt logic file.          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/06/03 WF
+--   Fixed Pending register logic.
+-- Revision 2K9A  2009/06/20 WF
+--   Fixed interrupt polarity for TA_I and TB_I.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_INTERRUPTS is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out bit;
+			
+			-- Interrupt sources:
+			GP_INT		: in bit_vector(7 downto 0);
+
+			AER_4		: in bit;
+			AER_3		: in bit;
+			TAI			: in bit;
+			TBI			: in bit;
+			TA_PWM		: in bit;
+			TB_PWM		: in bit;
+			TIMER_A_INT	: in bit;
+			TIMER_B_INT	: in bit;
+			TIMER_C_INT	: in bit;
+			TIMER_D_INT	: in bit;
+
+			RCV_ERR		: in bit;
+			TRM_ERR		: in bit;
+			RCV_BUF_F	: in bit;
+			TRM_BUF_E	: in bit
+	);
+end entity WF68901IP_INTERRUPTS;
+
+architecture BEHAVIOR of WF68901IP_INTERRUPTS is
+-- Interrupt state machine:
+type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
+signal INT_STATE : INT_STATES;
+-- The registers:
+signal IERA			: bit_vector(7 downto 0);
+signal IERB			: bit_vector(7 downto 0);
+signal IPRA			: bit_vector(7 downto 0);
+signal IPRB			: bit_vector(7 downto 0);
+signal ISRA			: bit_vector(7 downto 0);
+signal ISRB			: bit_vector(7 downto 0);
+signal IMRA			: bit_vector(7 downto 0);
+signal IMRB			: bit_vector(7 downto 0);
+signal VR			: bit_vector(7 downto 3);
+-- Interconnect:
+signal VECT_NUMBER	: bit_vector(7 downto 0);
+signal INT_SRC		: bit_vector(15 downto 0);
+signal INT_SRC_EDGE	: bit_vector(15 downto 0);
+signal INT_ENA		: bit_vector(15 downto 0);
+signal INT_MASK		: bit_vector(15 downto 0);
+signal INT_PENDING	: bit_vector(15 downto 0);
+signal INT_SERVICE	: bit_vector(15 downto 0);
+signal INT_PASS		: bit_vector(15 downto 0);
+signal INT_OUT		: bit_vector(15 downto 0);
+signal GP_INT_4		: bit;
+signal GP_INT_3		: bit;
+begin
+	-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
+	-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
+	-- to timer A and timer B.
+	-- The xor logic provides polarity control for the interrupt transition. Be aware,
+	-- that the PWM signals cause an interrupt on the opposite transition like the
+	-- respective GPIP port pins (with the same AER settings).
+    --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4;
+    --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3;
+    GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct.
+    GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3;
+
+
+	-- Interrupt source priority sorted (15 = highest):
+    INT_SRC <= 	GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & 
+    GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0);
+
+	INT_ENA 	<= IERA & IERB;
+	INT_MASK 	<= IMRA & IMRB;
+	INT_PENDING <= IPRA & IPRB;
+	INT_SERVICE <= ISRA & ISRB;
+	INT_OUT 	<= INT_PENDING and INT_MASK; -- Masking:
+
+	-- Enable the daisy chain, if there is no pending interrupt and
+	-- the interrupt state machine is not in service.
+	IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
+
+	-- Interrupt request:
+	IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
+
+	EDGE_ENA: process(RESETn, CLK)
+	-- These are the 16 edge detectors of the 16 interrupt input sources. This
+	-- process also provides the disabling or enabling via the IERA and IERB registers.
+	variable LOCK : bit_vector(15 downto 0);
+	begin
+		if RESETn = '0' then
+			INT_SRC_EDGE <= x"0000";
+			LOCK := x"0000";
+		elsif CLK = '0' and CLK' event then
+			for i in 15 downto 0 loop
+				if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then
+					LOCK(i) := '1';
+					INT_SRC_EDGE(i) <= '1';
+				elsif INT_SRC(i) = '0' then
+					LOCK(i) := '0';
+					INT_SRC_EDGE(i) <= '0';
+				else
+					INT_SRC_EDGE(i) <= '0';
+				end if;
+			end loop;
+		end if;
+	end process EDGE_ENA;
+	
+	INT_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			IERA <= (others => '0');
+			IERB <= (others => '0');
+			IPRA <= (others => '0');
+			IPRB <= (others => '0');
+			ISRA <= (others => '0');
+			ISRB <= (others => '0');
+			IMRA <= (others => '0');
+			IMRB <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "00011"	=> IERA <= DATA_IN; -- Enable A.
+					when "00100"	=> IERB <= DATA_IN; -- Enable B.
+					when "00101"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRA(i) <= '0'; -- Pending A.
+							end if;
+						end loop;
+					when "00110"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRB(i) <= '0'; -- Pending B.
+							end if;
+						end loop;
+					when "00111"	=> 
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRA(i) <= '0'; -- In Service A.
+							end if;
+						end loop;
+					when "01000"	=>
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRB(i) <= '0'; -- In Service B.
+							end if;
+						end loop;
+					when "01001"	=> IMRA <= DATA_IN; -- Mask A.
+					when "01010"	=> IMRB <= DATA_IN; -- Mask B.
+					when "01011"	=> VR <= DATA_IN(7 downto 3); -- Vector register.
+					when others		=> null;
+				end case;
+			end if;
+
+			-- Pending register:
+			-- set and clear bit logic.
+			for i in 15 downto 8 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRA(i-8) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRA(i-8) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRA(i-8) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRB(i) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRB(i) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRB(i) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+
+			-- In-Service register:
+			-- Set bit logic, VR(3) is the service register enable.
+			for i in 15 downto 8 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRA(i-8) <= '1';
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRB(i) <= '1';
+				end if;
+			end loop;
+		end if;
+	end process INT_REGISTERS;
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else 																	 '1' when INT_STATE = VECTOR_OUT else '0';
+
+	DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else
+				IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else
+				IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else
+				IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else
+				ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else
+				ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else
+				IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else
+				IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else
+				VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else
+				VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00";
+
+	P_INT_STATE	: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_STATE <= SCAN;
+		elsif CLK = '1' and CLK' event then
+			case INT_STATE is
+				when SCAN =>
+					INT_PASS <= x"0000";
+					-- Automatic End of Interrupt mode. Service register disabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0").
+					if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then
+						INT_STATE <= REQUEST; -- Non masked interrupt is pending.
+					-- The following 16 are the Software end of interrupt mode. Service register enabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized.
+					elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then
+						if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then
+							INT_STATE <= REQUEST;
+						else
+							INT_STATE <= SCAN; -- Wait for interrupt.
+						end if;
+					else
+						INT_STATE <= SCAN;
+					end if;
+				when REQUEST =>
+					if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode.
+						INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending.
+						if INT_OUT(15) = '1' then 
+							INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7.
+						elsif INT_OUT(14) = '1' then 
+							INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6.
+						elsif INT_OUT(13) = '1' then 
+							INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A.
+						elsif INT_OUT(12) = '1' then 
+							INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full.
+						elsif INT_OUT(11) = '1' then 
+							INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error.
+						elsif INT_OUT(10) = '1' then 
+							INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty.
+						elsif INT_OUT(9) = '1' then 
+							INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error.
+						elsif INT_OUT(8) = '1' then 
+							INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B.
+						elsif INT_OUT(7) = '1' then 
+							INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5.
+						elsif INT_OUT(6) = '1' then 
+							INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4.
+						elsif INT_OUT(5) = '1' then 
+							INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C.
+						elsif INT_OUT(4) = '1' then 
+							INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D.
+						elsif INT_OUT(3) = '1' then 
+							INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3.
+						elsif INT_OUT(2) = '1' then 
+							INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2.
+						elsif INT_OUT(1) = '1' then 
+							INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1.
+						elsif INT_OUT(0) = '1' then 
+							INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0.
+						end if;
+					 -- Polled interrupt mode: End of interrupt by writing to the pending registers.
+					elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then
+						INT_STATE <= SCAN;
+					else
+						INT_STATE <= REQUEST; -- Wait.
+					end if;
+				when VECTOR_OUT =>
+					INT_PASS <= x"0000";
+					if DSn = '1' or IACKn = '1' then
+						INT_STATE <= SCAN; -- Finished.
+					else
+						INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector.
+					end if;
+			end case;
+		end if;
+	end process P_INT_STATE;
+end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
index 77ea5ef..dac4e9d 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
@@ -190,8 +190,8 @@ begin
 		end if;	
 	end process DIG_PORTS;
 	-- Set port direction to input or to output:
-	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
-	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
+	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';  
+	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';  
 	IO_A_OUT <= PORT_A;
 	IO_B_OUT <= PORT_B;
 
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
new file mode 100644
index 0000000..d81f23c
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
@@ -0,0 +1,229 @@
+----------------------------------------------------------------------
+----                                                              ----
+----  YM2149 compatible sound generator.			              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+---- This IP core of the sound generator differs slightly from    ----
+---- the original. Firstly it is a synchronous design without any ----
+---- latches (like assumed in the original chip). This required   ----
+---- the introduction of a system adequate clock. In detail this  ----
+---- SYS_CLK should on the one hand be fast enough to meet the    ----
+---- timing requirements of the system's bus cycle and should one ----
+---- the other hand drive the PWM modules correctly. To meet both ----
+---- a SYS_CLK of 16MHz or above is recommended.                  ----
+---- Secondly, the original chip has an implemented DA converter. ----
+---- This feature is not possible in today's FPGAs. Therefore the ----
+---- converter is replaced by pulse width modulators. This solu-  ----
+---- tion is very simple in comparison to other approaches like   ----
+---- external DA converters with wave tables etc. The soltution   ----
+---- with the pulse width modulators is probably not as accurate  ----
+---- DAs with wavetables. For a detailed descrition of the hard-  ----
+---- ware PWM filter look at the end of the wave file, where the  ----
+---- pulse width modulators can be found.                         ----
+---- For a proper operation it is required, that the wave clock   ----
+---- is lower than the system clock. A good choice is for example ----
+---- 2MHz for the wave clock and 16MHz for the system clock.      ----
+----                                                              ----
+---- Main module file.                                            ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_TOP_SOC is
+	port(
+		
+		SYS_CLK		: in bit; -- Read the inforation in the header!
+		RESETn   	: in bit;
+
+		WAV_CLK		: in bit; -- Read the inforation in the header!
+		SELn		: in bit;
+		
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+
+		A9n, A8		: in bit;
+		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_EN		: out bit;
+		
+		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_EN		: out bit;
+		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_EN		: out bit;
+
+		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end WF2149IP_TOP_SOC;
+
+architecture STRUCTURE of WF2149IP_TOP_SOC is
+signal BUSCYCLE		: BUSCYCLES;
+signal DATA_OUT_I	: std_logic_vector(7 downto 0);
+signal DATA_EN_I	: bit;
+signal WAV_STRB		: bit;
+signal ADR_I		: bit_vector(3 downto 0);
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal PORT_A		: bit_vector(7 downto 0);
+signal PORT_B		: bit_vector(7 downto 0);
+begin
+	P_WAVSTRB: process(RESETn, SYS_CLK)
+	variable LOCK	: boolean;
+	variable TMP	: bit;
+	begin
+		if RESETn = '0' then
+			LOCK := false;
+			TMP := '0';
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_CLK = '1' and LOCK = false then
+				LOCK := true;
+				TMP := not TMP; -- Divider by 2.
+				case SELn is
+					when '1' 	=> WAV_STRB <= '1';
+					when others => WAV_STRB <= TMP;
+				end case;
+			elsif WAV_CLK = '0' then
+				LOCK := false;
+				WAV_STRB <= '0';
+			else
+				WAV_STRB <= '0';
+			end if;
+		end if;
+	end process P_WAVSTRB;		
+
+	with BDIR & BC2 & BC1 select
+		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
+					ADDRESS 	when "001" | "100" | "111",
+					R_READ 		when "011",
+					R_WRITE 	when "110";
+
+	ADDRESSLATCH: process(RESETn, SYS_CLK)
+	-- This process is responsible to store the desired register
+	-- address. The default (after reset) is channel A fine tone 
+	-- adjustment.
+	begin
+		if RESETn = '0' then
+			ADR_I <= (others => '0');
+        elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
+				ADR_I <= To_BitVector(DA_IN(3 downto 0));
+			end if;
+		end if;
+	end process ADDRESSLATCH;	
+
+	P_CTRL_REG: process(RESETn, SYS_CLK)
+	-- THIS is the Control register for the mixer and for the I/O ports.
+	begin
+		if RESETn = '0' then
+			CTRL_REG <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
+				CTRL_REG <= To_BitVector(DA_IN);
+			end if;
+		end if;
+	end process P_CTRL_REG;
+	
+	DIG_PORTS: process(RESETn, SYS_CLK)
+	begin
+		if RESETn = '0' then
+			PORT_A <= x"00";
+			PORT_B <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
+				PORT_A <= To_BitVector(DA_IN);
+			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
+				PORT_B <= To_BitVector(DA_IN);
+			end if;
+		end if;	
+	end process DIG_PORTS;
+	-- Set port direction to input or to output:
+	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '1'; --0
+	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '1'; --0
+	IO_A_OUT <= PORT_A;
+	IO_B_OUT <= PORT_B;
+
+	I_PSG_WAVE: WF2149IP_WAVE
+		port map(
+			RESETn		=> RESETn,
+			SYS_CLK	=> SYS_CLK,
+
+			WAV_STRB	=> WAV_STRB,
+
+			ADR			=> ADR_I,
+			DATA_IN		=> DA_IN,
+			DATA_OUT	=> DATA_OUT_I,
+			DATA_EN		=> DATA_EN_I,
+			
+			BUSCYCLE	=> BUSCYCLE,
+			CTRL_REG	=> CTRL_REG(5 downto 0),
+						
+			OUT_A		=> OUT_A,
+			OUT_B		=> OUT_B,
+			OUT_C		=> OUT_C
+		);
+
+	-- Read the ports and registers:
+	DA_EN <= 	'1' when DATA_EN_I = '1' else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
+				
+	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
+				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
+				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
+				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
+
+end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
index e60cc43..5ce2f2e 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_CTRL_STATUS is
   port (
-		CLK			: in bit;
+		CLK			: in std_logic;
         RESETn		: in bit;
 
         CS			: in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
 		CDS			: out bit_vector(1 downto 0); -- Clock control.
 		WS			: out bit_vector(2 downto 0); -- Word select.
 		TC			: out bit_vector(1 downto 0); -- Transmit control.
-		IRQn		: out bit -- Interrupt request.
+		IRQn		: buffer bit -- Interrupt request.
        );                                              
 end entity WF6850IP_CTRL_STATUS;
 
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
 signal CTRL_REG		: bit_vector(7 downto 0);
 signal STATUS_REG	: bit_vector(7 downto 0);
 signal RIE			: bit;
-signal IRQ_I		: bit;
 signal CTS_In		: bit;
 signal DCD_In		: bit;
 signal DCD_FLAGn	: bit;
 begin
-	P_SAMPLE: process
-	begin
-		wait until CLK = '0' and CLK' event;
-		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
-		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
-	end process P_SAMPLE;
+	CTS_In <= CTSn;  
+	DCD_In <= DCDn;  -- immer 0
 
-	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(7) <= not IRQn;
 	STATUS_REG(6) <= PE;
 	STATUS_REG(5) <= OVR;
 	STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
 	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
 	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
 
-	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
-	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
 	
 	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
 	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,110 +129,73 @@ begin
 	TC <= CTRL_REG(6 downto 5);
 	RIE <= CTRL_REG(7);
 	
-	P_IRQ: process
-	variable DCD_OVR_LOCK	: boolean;
-	variable DCD_LOCK	    : boolean;
-	variable DCD_TRANS	    : boolean;	
-	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			DCD_OVR_LOCK := false;
-			IRQn <= '1';
-			IRQ_I <= '0';
-		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
-			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+	P_IRQ: process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if RESETn = '0'  or MCLR = '1' then
+				IRQn <= '1';
+			else
+				-- Transmitter interrupt:
+				if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
+					IRQn <= '0';
+				end if;
+				-- Receiver interrupts:
+				if RDRF = '1' and RIE = '1' then
+					IRQn <= '0';
+				end if;
+				-- Overrun
+				if OVR = '1' and RIE = '1' then
+					IRQn <= '0';
+				end if;
+				-- The reset of the IRQ status flag:
+				-- Clear by writing to the transmit data register.
+				-- Clear by reading the receive data register.
+				if  CS = "011" and RS = '1' then
+					IRQn <= '1';
+				end if;
+			end if;
 		end if;
-
-        -- Clear interrupts when disabled.
-        if CTRL_REG(7) = '0' then
-            IRQn <= '1';
-            IRQ_I <= '0';
-        elsif CTRL_REG(6 downto 5) /= "01" then
-            IRQn <= '1';
-            IRQ_I <= '0';
-        end if;
-
-		-- Transmitter interrupt:
-        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
-			IRQn <= '1'; -- Clear by writing to the transmit data register.
-		end if;
-					
-		-- Receiver interrupts:
-		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
-			IRQn <= '1'; -- Clear by reading the receive data register.
-		end if;
-
-		if OVR = '1' and RIE = '1' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-			DCD_OVR_LOCK := true;
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
-			IRQn <= '1'; -- Clear by reading the receive data register after the status.
-		end if;
-					
-		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
-			IRQn <= '0';
-			IRQ_I <= '1';
-			-- DCD_TRANS is used to detect a low to high transition of DCDn.
-			DCD_TRANS := true;
-			DCD_OVR_LOCK := true;
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
-			IRQn <= '1'; -- Clear by reading the receive data register after the status.
-		elsif DCD_In = '0' then
-			DCD_TRANS := false;
-		end if;
-
-		-- The reset of the IRQ status flag:
-		-- Clear by writing to the transmit data register.
-		-- Clear by reading the receive data register.
-		if  CS = "011" and RS = '1' and E = '1' then
-			IRQ_I <= '0'; 
-		end if;
 	end process P_IRQ;
 	
-	CONTROL: process
+	CONTROL: process(CLK)
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			CTRL_REG <= "01000000";
-		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
-			CTRL_REG <= DATA_IN;
+		if rising_edge(CLK) then
+			if RESETn = '0' then
+				CTRL_REG <= "01000000";
+			elsif CS = "011" and RWn = '0' and RS = '0' then
+				CTRL_REG <= DATA_IN;
+			end if;
 		end if;
 	end process CONTROL;	
 
-	P_DCD: process
+	P_DCD: process(CLK)
 	-- This process is some kind of tricky. Refer to the MC6850 data
 	-- sheet for more information.
 	variable READ_LOCK		: boolean;
 	variable DCD_RELEASE	: boolean;
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
-			READ_LOCK := true;
-			DCD_RELEASE := false;
-		elsif MCLR = '1' then
-			DCD_FLAGn <= DCD_In;
-			READ_LOCK := true;
-		elsif DCD_In = '1' then
-			DCD_FLAGn <= '1';
-		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
-			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
-			-- Clear if receiver status register read access.
-			-- After data register has ben read and READ_LOCK again.
-			DCD_RELEASE := true;
-			READ_LOCK := true;
-			DCD_FLAGn <= DCD_In;
-		elsif DCD_In = '0' and DCD_RELEASE = true then
-			DCD_FLAGn <= '0';
-			DCD_RELEASE := false;
+		if rising_edge(CLK) then
+			if RESETn = '0' then
+				DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+				READ_LOCK := true;
+				DCD_RELEASE := false;
+			elsif MCLR = '1' then
+				DCD_FLAGn <= DCD_In;
+				READ_LOCK := true;
+			elsif DCD_In = '1' then
+				DCD_FLAGn <= '1';
+			elsif CS = "011" and RWn = '1' and RS = '0' then
+				READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+			elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
+				-- Clear if receiver status register read access.
+				-- After data register has ben read and READ_LOCK again.
+				DCD_RELEASE := true;
+				READ_LOCK := true;
+				DCD_FLAGn <= DCD_In;
+			elsif DCD_In = '0' and DCD_RELEASE = true then
+				DCD_FLAGn <= '0';
+				DCD_RELEASE := false;
+			end if;
 		end if;
 	end process P_DCD;	
 end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
index a0ea9e4..2e85cdd 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_CTRL_STATUS is
   port (
-		CLK			: in bit;
+		CLK			: in std_logic;
         RESETn		: in bit;
 
         CS			: in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
 		CDS			: out bit_vector(1 downto 0); -- Clock control.
 		WS			: out bit_vector(2 downto 0); -- Word select.
 		TC			: out bit_vector(1 downto 0); -- Transmit control.
-		IRQn		: out bit -- Interrupt request.
+		IRQn		: buffer bit -- Interrupt request.
        );                                              
 end entity WF6850IP_CTRL_STATUS;
 
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
 signal CTRL_REG		: bit_vector(7 downto 0);
 signal STATUS_REG	: bit_vector(7 downto 0);
 signal RIE			: bit;
-signal IRQ_I		: bit;
 signal CTS_In		: bit;
 signal DCD_In		: bit;
 signal DCD_FLAGn	: bit;
 begin
-	P_SAMPLE: process
-	begin
-		wait until CLK = '0' and CLK' event;
-		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
-		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
-	end process P_SAMPLE;
+	CTS_In <= CTSn;  
+	DCD_In <= DCDn;  -- immer 0
 
-	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(7) <= not IRQn;
 	STATUS_REG(6) <= PE;
 	STATUS_REG(5) <= OVR;
 	STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
 	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
 	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
 
-	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
-	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
 	
 	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
 	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,110 +129,85 @@ begin
 	TC <= CTRL_REG(6 downto 5);
 	RIE <= CTRL_REG(7);
 	
-	P_IRQ: process
-	variable DCD_OVR_LOCK	: boolean;
-	variable DCD_LOCK	    : boolean;
-	variable DCD_TRANS	    : boolean;	
-	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			DCD_OVR_LOCK := false;
-			IRQn <= '1';
-			IRQ_I <= '0';
-		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
-			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+	P_IRQ: process(CLK)
+	variable irq_v 	: std_logic_vector(3 downto 0);
+	begin
+		if rising_edge(CLK) then
+			if RESETn = '0'  or MCLR = '1' then
+				irq_v := x"0";
+				IRQn <= '1';
+			else
+				-- Transmitter interrupt:
+				if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
+					if irq_v = x"F" then
+						irq_v := irq_v + 1;
+					end if;
+				-- Receiver interrupts:
+				elsif RDRF = '1' and RIE = '1' then
+					if irq_v < 15 then
+						irq_v := irq_v + 1;
+					end if;
+				-- Overrun
+				elsif OVR = '1' and RIE = '1' then
+					if irq_v < 15 then
+						irq_v := irq_v + 1;
+					end if;
+				else
+					if irq_v > 0 then
+						irq_v := irq_v - 1;
+					end if;
+				end if;
+				if irq_v < 8 then
+					IRQn <= '1';
+				else
+					IRQn <= '0';
+				end if;
+				-- The reset of the IRQ status flag:
+				-- Clear by writing to the transmit data register.
+				-- Clear by reading the receive data register.
+			end if;
 		end if;
-
--- Clear interrupts when disabled.
-if CTRL_REG(7) = '0' then
-    IRQn <= '1';
-    IRQ_I <= '0';
-elsif CTRL_REG(6 downto 5) /= "01" then
-    IRQn <= '1';
-    IRQ_I <= '0';
-end if;
-
-		-- Transmitter interrupt:
-        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
-			IRQn <= '1'; -- Clear by writing to the transmit data register.
-		end if;
-					
-		-- Receiver interrupts:
-		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
-			IRQn <= '1'; -- Clear by reading the receive data register.
-		end if;
-
-		if OVR = '1' and RIE = '1' then
-			IRQn <= '0';
-			IRQ_I <= '1';
-			DCD_OVR_LOCK := true;
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
-			IRQn <= '1'; -- Clear by reading the receive data register after the status.
-		end if;
-					
-		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
-			IRQn <= '0';
-			IRQ_I <= '1';
-			-- DCD_TRANS is used to detect a low to high transition of DCDn.
-			DCD_TRANS := true;
-			DCD_OVR_LOCK := true;
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
-			IRQn <= '1'; -- Clear by reading the receive data register after the status.
-		elsif DCD_In = '0' then
-			DCD_TRANS := false;
-		end if;
-
-		-- The reset of the IRQ status flag:
-		-- Clear by writing to the transmit data register.
-		-- Clear by reading the receive data register.
-		if  CS = "011" and RS = '1' and E = '1' then
-			IRQ_I <= '0'; 
-		end if;
 	end process P_IRQ;
 	
-	CONTROL: process
+	CONTROL: process(CLK)
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			CTRL_REG <= "01000000";
-		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
-			CTRL_REG <= DATA_IN;
+		if rising_edge(CLK) then
+			if RESETn = '0' then
+				CTRL_REG <= "01000000";
+			elsif CS = "011" and RWn = '0' and RS = '0' then
+				CTRL_REG <= DATA_IN;
+			end if;
 		end if;
 	end process CONTROL;	
 
-	P_DCD: process
+	P_DCD: process(CLK)
 	-- This process is some kind of tricky. Refer to the MC6850 data
 	-- sheet for more information.
 	variable READ_LOCK		: boolean;
 	variable DCD_RELEASE	: boolean;
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RESETn = '0' then
-			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
-			READ_LOCK := true;
-			DCD_RELEASE := false;
-		elsif MCLR = '1' then
-			DCD_FLAGn <= DCD_In;
-			READ_LOCK := true;
-		elsif DCD_In = '1' then
-			DCD_FLAGn <= '1';
-		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
-			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
-		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
-			-- Clear if receiver status register read access.
-			-- After data register has ben read and READ_LOCK again.
-			DCD_RELEASE := true;
-			READ_LOCK := true;
-			DCD_FLAGn <= DCD_In;
-		elsif DCD_In = '0' and DCD_RELEASE = true then
-			DCD_FLAGn <= '0';
-			DCD_RELEASE := false;
+		if rising_edge(CLK) then
+			if RESETn = '0' then
+				DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+				READ_LOCK := true;
+				DCD_RELEASE := false;
+			elsif MCLR = '1' then
+				DCD_FLAGn <= DCD_In;
+				READ_LOCK := true;
+			elsif DCD_In = '1' then
+				DCD_FLAGn <= '1';
+			elsif CS = "011" and RWn = '1' and RS = '0' then
+				READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+			elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
+				-- Clear if receiver status register read access.
+				-- After data register has ben read and READ_LOCK again.
+				DCD_RELEASE := true;
+				READ_LOCK := true;
+				DCD_FLAGn <= DCD_In;
+			elsif DCD_In = '0' and DCD_RELEASE = true then
+				DCD_FLAGn <= '0';
+				DCD_RELEASE := false;
+			end if;
 		end if;
 	end process P_DCD;	
 end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd
new file mode 100644
index 0000000..c6626df
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd	
@@ -0,0 +1,419 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's receiver unit.                                        ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_RECEIVE is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+
+		RDRF				: buffer bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end entity WF6850IP_RECEIVE;
+
+architecture BEHAVIOR of WF6850IP_RECEIVE is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal RXDATA_I		: bit;
+signal RXDATA_S		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal CLK_STRB		: bit;
+signal BITCNT		: std_logic_vector(2 downto 0);
+begin
+	P_SAMPLE: process
+	-- This filter provides a synchronisation to the system
+	-- clock, even for random baud rates of the received data
+	-- stream.
+	variable FLT_TMP	: integer range 0 to 2;
+	begin
+		wait until CLK = '1' and CLK' event;
+		--
+		RXDATA_I <= RXDATA;
+		--
+		if RXDATA_I = '1' and FLT_TMP < 2 then
+			FLT_TMP := FLT_TMP + 1;
+		elsif RXDATA_I = '1' then
+			RXDATA_S <= '1';
+		elsif RXDATA_I = '0' and FLT_TMP > 0 then
+			FLT_TMP := FLT_TMP - 1;
+		elsif RXDATA_I = '0' then
+			RXDATA_S <= '0';
+		end if;
+	end process P_SAMPLE;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif RCV_STATE = IDLE then
+			-- Preset the CLKDIV with the start delays.
+			if CDS = "01" then
+				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+			elsif CDS = "10" then
+				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
+			end if;
+	 		CLK_STRB <= '0';
+		else
+			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				--
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= SHIFT_REG;
+			end if;
+		end if;
+	end process DATAREG;	
+    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
+    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	OVERRUN: process(RESETn, CLK)
+	variable OVR_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OVR_I := '0';
+			OVR <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				OVR_I := '0';
+				OVR <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+				OVR_I := RDRF;
+			end if;
+			if CS = "011" and RWn = '1' and RS = '1' then
+				-- If an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OVR_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					if OVR_I = '1' then
+						OVR <= '1';
+						OVR_I := '0';
+						FIRST_READ := true;
+					else
+						OVR <= '0';
+					end if;
+				end if;	
+			else
+				FIRST_READ := false;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable PE_I		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				PE <= '0';
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				PE_I := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				    	PE_I := PAR_TMP xor RXDATA_S;
+					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+						PE_I := not PAR_TMP xor RXDATA_S;
+					else -- No parity for WS = "100" and WS = "101".
+						PE_I := '0';		
+					end if;
+				end if;
+			end if;
+			-- Transmit the parity flag together with the data
+			-- In other words: no parity to the status register
+			-- when RDRF inhibits the data transfer to the
+			-- receiver data register.
+			if RCV_STATE = SYNC and RDRF = '0' then
+				PE <= PE_I;
+			elsif CS = "011" and RWn = '1' and RS = '1' then
+				PE <= '0'; -- Clear when reading the data register.
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	P_RDRF: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RDRF <= '0';
+			elsif RCV_STATE = SYNC then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif CS = "011" and RWn = '1' and RS = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process P_RDRF;
+	
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if RXDATA_S = '0' and CDS = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif RXDATA_S = '0' and CDS = "01" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				elsif RXDATA_S = '0' and CDS = "10" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
+					else
+						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
+					end if;
+				else
+					RCV_NEXT_STATE <= WAIT_START; -- Stay.
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= STOP1;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif WS = "000" or WS = "001" or WS = "100" then
+						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC;
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
index 755e018..9461136 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
@@ -60,7 +60,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_RECEIVE is
   port (
-		CLK					: in bit;
+		CLK					: in std_logic;
         RESETn				: in bit;
 		MCLR				: in bit;
 
@@ -95,124 +95,127 @@ signal SHIFT_REG	: bit_vector(7 downto 0);
 signal CLK_STRB		: bit;
 signal BITCNT		: std_logic_vector(2 downto 0);
 begin
-	P_SAMPLE: process
+	P_SAMPLE: process(CLK)
 	-- This filter provides a synchronisation to the system
 	-- clock, even for random baud rates of the received data
 	-- stream.
 	variable FLT_TMP	: integer range 0 to 2;
 	begin
-		wait until CLK = '1' and CLK' event;
-		--
-		RXDATA_I <= RXDATA;
-		--
-		if RXDATA_I = '1' and FLT_TMP < 2 then
-			FLT_TMP := FLT_TMP + 1;
-		elsif RXDATA_I = '1' then
-			RXDATA_S <= '1';
-		elsif RXDATA_I = '0' and FLT_TMP > 0 then
-			FLT_TMP := FLT_TMP - 1;
-		elsif RXDATA_I = '0' then
-			RXDATA_S <= '0';
+		if rising_edge(CLK) then
+			--
+			RXDATA_I <= RXDATA;
+			--
+			if RXDATA_I = '1' and FLT_TMP < 2 then
+				FLT_TMP := FLT_TMP + 1;
+			elsif RXDATA_I = '1' then
+				RXDATA_S <= '1';
+			elsif RXDATA_I = '0' and FLT_TMP > 0 then
+				FLT_TMP := FLT_TMP - 1;
+			elsif RXDATA_I = '0' then
+				RXDATA_S <= '0';
+			end if;
 		end if;
 	end process P_SAMPLE;
 
-	CLKDIV: process
+	CLKDIV: process(CLK)
 	variable CLK_LOCK	: boolean;
 	variable STRB_LOCK	: boolean;
 	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
 	begin
-		wait until CLK = '1' and CLK' event;
-		if CDS = "00" then -- Divider off.
-			if RXCLK = '1' and STRB_LOCK = false then
-				CLK_STRB <= '1';
-				STRB_LOCK := true;
-			elsif RXCLK = '0' then
-				CLK_STRB <= '0';
-				STRB_LOCK := false;
-			else
-				CLK_STRB <= '0';
-			end if;
-		elsif RCV_STATE = IDLE then
-			-- Preset the CLKDIV with the start delays.
-			if CDS = "01" then
-				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
-			elsif CDS = "10" then
-				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
-			end if;
-	 		CLK_STRB <= '0';
-		else
-			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
-				CLK_DIVCNT := CLK_DIVCNT - '1';
-				CLK_STRB <= '0';
-				CLK_LOCK := true;
-			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-				--
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
+		if rising_edge(CLK) then
+			if CDS = "00" then -- Divider off.
+				if RXCLK = '1' and STRB_LOCK = false then
 					CLK_STRB <= '1';
+					STRB_LOCK := true;
+				elsif RXCLK = '0' then
+					CLK_STRB <= '0';
+					STRB_LOCK := false;
 				else
 					CLK_STRB <= '0';
 				end if;
-			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
+			elsif RCV_STATE = IDLE then
+				-- Preset the CLKDIV with the start delays.
+				if CDS = "01" then
+					CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+				elsif CDS = "10" then
+					CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
 				end if;
-			elsif RXCLK = '0' then
-				CLK_LOCK := false;
-				STRB_LOCK := false;
 				CLK_STRB <= '0';
 			else
-				CLK_STRB <= '0';
+				if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+					CLK_DIVCNT := CLK_DIVCNT - '1';
+					CLK_STRB <= '0';
+					CLK_LOCK := true;
+				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+					--
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif RXCLK = '0' then
+					CLK_LOCK := false;
+					STRB_LOCK := false;
+					CLK_STRB <= '0';
+				else
+					CLK_STRB <= '0';
+				end if;
 			end if;
 		end if;
 	end process CLKDIV;
 	
 	DATAREG: process(RESETn, CLK)
 	begin
-		if RESETn = '0' then
+		if RESETn = '0' or MCLR = '1' then
 			DATA_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				DATA_REG <= x"00";
-			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
-			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= SHIFT_REG;
+		else
+			if rising_edge(CLK) then
+				if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+					-- Transfer from shift- to data register only if
+					-- data register is empty (RDRF = '0').
+					DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+				elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+					-- Transfer from shift- to data register only if
+					-- data register is empty (RDRF = '0').
+					DATA_REG <= SHIFT_REG;
+				end if;
 			end if;
 		end if;
 	end process DATAREG;	
-    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
-    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
+    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
 	
 	SHIFTREG: process(RESETn, CLK)
 	begin
-		if RESETn = '0' then
-			SHIFT_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				SHIFT_REG <= x"00";
-			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
-				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+		if RESETn = '0' or MCLR = '1' then
+			SHIFT_REG <= x"00";
+		else
+			if rising_edge(CLK) then
+				if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+					SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+				end if;
 			end if;
 		end if;
 	end process SHIFTREG;	
 
-	P_BITCNT: process
+	P_BITCNT: process(CLK)
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
-			BITCNT <= BITCNT + '1';
-		elsif RCV_STATE /= SAMPLE then
-			BITCNT <= (others => '0');
+		if rising_edge(CLK) then
+			if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				BITCNT <= BITCNT + '1';
+			elsif RCV_STATE /= SAMPLE then
+				BITCNT <= (others => '0');
+			end if;
 		end if;
 	end process P_BITCNT;
 
@@ -224,84 +227,88 @@ begin
 		if RESETn = '0' then
 			FE_I := '0';
 			FE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				FE_I := '0';
-				FE <= '0';
-			elsif CLK_STRB = '1' then
-				if RCV_STATE = STOP1 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
-					FE_I := '0'; -- Error resets when correct data appears.
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					FE_I := '0';
+					FE <= '0';
+				elsif CLK_STRB = '1' then
+					if RCV_STATE = STOP1 and RXDATA_S = '0' then
+						FE_I := '1';
+					elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+						FE_I := '1';
+					elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+						FE_I := '0'; -- Error resets when correct data appears.
+					end if;
+				end if;
+				if RCV_STATE = SYNC then
+					FE <= FE_I; -- Update the FE every SYNC time.
 				end if;
-			end if;
-			if RCV_STATE = SYNC then
-				FE <= FE_I; -- Update the FE every SYNC time.
 			end if;
 		end if;
 	end process FRAME_ERR;
 
 	OVERRUN: process(RESETn, CLK)
-	variable OVR_I		: bit;
+	variable OVR_I		: bit;
 	variable FIRST_READ	: boolean;
 	begin
-		if RESETn = '0' then
-			OVR_I := '0';
-			OVR <= '0';
-			FIRST_READ := false;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
+		if rising_edge(CLK) then
+			if RESETn = '0'  or MCLR = '1' then
 				OVR_I := '0';
 				OVR <= '0';
 				FIRST_READ := false;
-			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-				-- Overrun appears if RDRF is '1' in this state.
-				OVR_I := RDRF;
-			end if;
-			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+			else
+				if CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+					OVR_I := RDRF;
+				end if;
+				if CS = "011" and RWn = '1' and RS = '1' then
 				-- If an overrun was detected, the concerning flag is
 				-- set when the valid data word in the receiver data
 				-- register is read. Thereafter the RDRF flag is reset
 				-- and the overrun disappears (OVR_I goes low) after 
 				-- a second read (in time) of the receiver data register.
-				if FIRST_READ = false then
-					OVR <= '1';
-					FIRST_READ := true;
-				else
-					OVR <= '0';
-					FIRST_READ := false;
-				end if;
+					if FIRST_READ = false then
+						if OVR_I = '1' then
+							OVR <= '1';
+							OVR_I := '0';
+							FIRST_READ := true;
+						else
+							OVR <= '0';
+						end if;
+					end if;
+				else
+					FIRST_READ := false;
+				end if;
 			end if;
 		end if;
 	end process OVERRUN;
 	
-	PARITY_TEST: process(RESETn, CLK)
+	PARITY_TEST: process(RESETn,MCLR,CLK)
 	variable PAR_TMP	: bit;
 	variable PE_I		: bit;
 	begin
-		if RESETn = '0' then
+		if RESETn = '0' or MCLR = '1' then
 			PE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				PE <= '0';
-			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
-				PE_I := '0'; -- Initialise.
-				if RCV_STATE = PARITY then
-				    for i in 1 to 7 loop
-				        if i = 1 then
-				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
-				        else
-				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
-				        end if;
-				    end loop;
-					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
-				    	PE_I := PAR_TMP xor RXDATA_S;
-					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
-						PE_I := not PAR_TMP xor RXDATA_S;
-					else -- No parity for WS = "100" and WS = "101".
-						PE_I := '0';		
+		else
+			if rising_edge(CLK) then
+				if CLK_STRB = '1' then -- Sample parity on clock strobe.
+					PE_I := '0'; -- Initialise.
+					if RCV_STATE = PARITY then
+						for i in 1 to 7 loop
+							if i = 1 then
+								PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+							else
+								PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+							end if;
+						end loop;
+						if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+							PE_I := PAR_TMP xor RXDATA_S;
+						elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+							PE_I := not PAR_TMP xor RXDATA_S;
+						else -- No parity for WS = "100" and WS = "101".
+							PE_I := '0';	
+						end if;	
 					end if;
 				end if;
 			end if;
@@ -311,7 +318,7 @@ begin
 			-- receiver data register.
 			if RCV_STATE = SYNC and RDRF = '0' then
 				PE <= PE_I;
-			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			elsif CS = "011" and RWn = '1' and RS = '1' then
 				PE <= '0'; -- Clear when reading the data register.
 			end if;
 		end if;
@@ -320,28 +327,31 @@ begin
 	P_RDRF: process(RESETn, CLK)
 	-- Receive data register full flag.
 	begin
-		if RESETn = '0' then
-			RDRF <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RDRF <= '0';
-			elsif RCV_STATE = SYNC then
-				RDRF <= '1'; -- Data register is full until now!
-			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
-				RDRF <= '0'; -- After reading the data register ...
-			end if;
-		end if;
+		if rising_edge(CLK) then
+			if RESETn = '0' or MCLR = '1' then
+				RDRF <= '0';
+			else
+				if RCV_STATE = SYNC then
+					RDRF <= '1'; -- Data register is full until now!
+				end if;
+				if CS = "011" and RWn = '1' and RS = '1' then
+					RDRF <= '0'; -- when reading the data register ...
+				end if;
+			end if;
+		end if;
 	end process P_RDRF;
 	
 	RCV_STATEREG: process(RESETn, CLK)
 	begin
 		if RESETn = '0' then
 			RCV_STATE <= IDLE;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RCV_STATE <= IDLE;
-			else
-				RCV_STATE <= RCV_NEXT_STATE;
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					RCV_STATE <= IDLE;
+				else
+					RCV_STATE <= RCV_NEXT_STATE;
+				end if;
 			end if;
 		end if;
 	end process RCV_STATEREG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
index e8c82b2..8877e05 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
@@ -19,7 +19,7 @@
 ----                                                              ----
 ----------------------------------------------------------------------
 ----                                                              ----
----- Copyright (C) 2006 Wolfgang Foerster                         ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
 ----                                                              ----
 ---- This source file may be used and distributed without         ----
 ---- restriction provided that this copyright statement is not    ----
@@ -48,8 +48,10 @@
 -- 
 -- Revision 2K6A  2006/06/03 WF
 --   Initial Release.
--- Revision 2K6B	2006/11/07 WF
+-- Revision 2K6B  2006/11/07 WF
 --   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
 --
 
 library ieee;
@@ -58,7 +60,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_RECEIVE is
   port (
-		CLK					: in bit;
+		CLK					: in std_logic;
         RESETn				: in bit;
 		MCLR				: in bit;
 
@@ -93,126 +95,127 @@ signal SHIFT_REG	: bit_vector(7 downto 0);
 signal CLK_STRB		: bit;
 signal BITCNT		: std_logic_vector(2 downto 0);
 begin
-	P_SAMPLE: process
+	P_SAMPLE: process(CLK)
 	-- This filter provides a synchronisation to the system
 	-- clock, even for random baud rates of the received data
 	-- stream.
 	variable FLT_TMP	: integer range 0 to 2;
 	begin
-		wait until CLK = '1' and CLK' event;
-		--
-		RXDATA_I <= RXDATA;
-		--
-		if RXDATA_I = '1' and FLT_TMP < 2 then
-			FLT_TMP := FLT_TMP + 1;
-		elsif RXDATA_I = '1' then
-			RXDATA_S <= '1';
-		elsif RXDATA_I = '0' and FLT_TMP > 0 then
-			FLT_TMP := FLT_TMP - 1;
-		elsif RXDATA_I = '0' then
-			RXDATA_S <= '0';
+		if rising_edge(CLK) then
+			--
+			RXDATA_I <= RXDATA;
+			--
+			if RXDATA_I = '1' and FLT_TMP < 2 then
+				FLT_TMP := FLT_TMP + 1;
+			elsif RXDATA_I = '1' then
+				RXDATA_S <= '1';
+			elsif RXDATA_I = '0' and FLT_TMP > 0 then
+				FLT_TMP := FLT_TMP - 1;
+			elsif RXDATA_I = '0' then
+				RXDATA_S <= '0';
+			end if;
 		end if;
 	end process P_SAMPLE;
 
-	CLKDIV: process
+	CLKDIV: process(CLK)
 	variable CLK_LOCK	: boolean;
 	variable STRB_LOCK	: boolean;
 	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
 	begin
-		wait until CLK = '1' and CLK' event;
-		if CDS = "00" then -- Divider off.
-			if RXCLK = '1' and STRB_LOCK = false then
-				CLK_STRB <= '1';
-				STRB_LOCK := true;
-			elsif RXCLK = '0' then
-				CLK_STRB <= '0';
-				STRB_LOCK := false;
-			else
-				CLK_STRB <= '0';
-			end if;
-		elsif RCV_STATE = IDLE then
-			-- Preset the CLKDIV with the start delays.
-			if CDS = "01" then
-				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
-			elsif CDS = "10" then
-				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
-			end if;
-	 		CLK_STRB <= '0';
-		else
-			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
-				CLK_DIVCNT := CLK_DIVCNT - '1';
-				CLK_STRB <= '0';
-				CLK_LOCK := true;
-			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-				--
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
+		if rising_edge(CLK) then
+			if CDS = "00" then -- Divider off.
+				if RXCLK = '1' and STRB_LOCK = false then
 					CLK_STRB <= '1';
+					STRB_LOCK := true;
+				elsif RXCLK = '0' then
+					CLK_STRB <= '0';
+					STRB_LOCK := false;
 				else
 					CLK_STRB <= '0';
 				end if;
-			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
+			elsif RCV_STATE = IDLE then
+				-- Preset the CLKDIV with the start delays.
+				if CDS = "01" then
+					CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+				elsif CDS = "10" then
+					CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
 				end if;
-			elsif RXCLK = '0' then
-				CLK_LOCK := false;
-				STRB_LOCK := false;
 				CLK_STRB <= '0';
 			else
-				CLK_STRB <= '0';
+				if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+					CLK_DIVCNT := CLK_DIVCNT - '1';
+					CLK_STRB <= '0';
+					CLK_LOCK := true;
+				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+					--
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif RXCLK = '0' then
+					CLK_LOCK := false;
+					STRB_LOCK := false;
+					CLK_STRB <= '0';
+				else
+					CLK_STRB <= '0';
+				end if;
 			end if;
 		end if;
 	end process CLKDIV;
 	
 	DATAREG: process(RESETn, CLK)
 	begin
-		if RESETn = '0' then
+		if RESETn = '0' or MCLR = '1' then
 			DATA_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				DATA_REG <= x"00";
-			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
-			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= SHIFT_REG;
+		else
+			if rising_edge(CLK) then
+				if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+					-- Transfer from shift- to data register only if
+					-- data register is empty (RDRF = '0').
+					DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+				elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+					-- Transfer from shift- to data register only if
+					-- data register is empty (RDRF = '0').
+					DATA_REG <= SHIFT_REG;
+				end if;
 			end if;
 		end if;
 	end process DATAREG;	
---DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
---DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
-DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
-DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
+    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
+    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
 	
 	SHIFTREG: process(RESETn, CLK)
 	begin
-		if RESETn = '0' then
-			SHIFT_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				SHIFT_REG <= x"00";
-			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
-				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+		if RESETn = '0' or MCLR = '1' then
+			SHIFT_REG <= x"00";
+		else
+			if rising_edge(CLK) then
+				if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+					SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+				end if;
 			end if;
 		end if;
 	end process SHIFTREG;	
 
-	P_BITCNT: process
+	P_BITCNT: process(CLK)
 	begin
-		wait until CLK = '1' and CLK' event;
-		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
-			BITCNT <= BITCNT + '1';
-		elsif RCV_STATE /= SAMPLE then
-			BITCNT <= (others => '0');
+		if rising_edge(CLK) then
+			if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				BITCNT <= BITCNT + '1';
+			elsif RCV_STATE /= SAMPLE then
+				BITCNT <= (others => '0');
+			end if;
 		end if;
 	end process P_BITCNT;
 
@@ -224,84 +227,88 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
 		if RESETn = '0' then
 			FE_I := '0';
 			FE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				FE_I := '0';
-				FE <= '0';
-			elsif CLK_STRB = '1' then
-				if RCV_STATE = STOP1 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
-					FE_I := '0'; -- Error resets when correct data appears.
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					FE_I := '0';
+					FE <= '0';
+				elsif CLK_STRB = '1' then
+					if RCV_STATE = STOP1 and RXDATA_S = '0' then
+						FE_I := '1';
+					elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+						FE_I := '1';
+					elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+						FE_I := '0'; -- Error resets when correct data appears.
+					end if;
+				end if;
+				if RCV_STATE = SYNC then
+					FE <= FE_I; -- Update the FE every SYNC time.
 				end if;
-			end if;
-			if RCV_STATE = SYNC then
-				FE <= FE_I; -- Update the FE every SYNC time.
 			end if;
 		end if;
 	end process FRAME_ERR;
 
 	OVERRUN: process(RESETn, CLK)
-	variable OVR_I		: bit;
+	variable OVR_I		: bit;
 	variable FIRST_READ	: boolean;
 	begin
-		if RESETn = '0' then
-			OVR_I := '0';
-			OVR <= '0';
-			FIRST_READ := false;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
+		if rising_edge(CLK) then
+			if RESETn = '0'  or MCLR = '1' then
 				OVR_I := '0';
 				OVR <= '0';
 				FIRST_READ := false;
-			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-				-- Overrun appears if RDRF is '1' in this state.
-				OVR_I := RDRF;
-			end if;
-			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+			else
+				if CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+					OVR_I := RDRF;
+				end if;
+				if CS = "011" and RWn = '1' and RS = '1' then
 				-- If an overrun was detected, the concerning flag is
 				-- set when the valid data word in the receiver data
 				-- register is read. Thereafter the RDRF flag is reset
 				-- and the overrun disappears (OVR_I goes low) after 
 				-- a second read (in time) of the receiver data register.
-				if FIRST_READ = false then
-					OVR <= '1';
-					FIRST_READ := true;
-				else
-					OVR <= '0';
-					FIRST_READ := false;
-				end if;
+					if FIRST_READ = false then
+						if OVR_I = '1' then
+							OVR <= '1';
+							OVR_I := '0';
+							FIRST_READ := true;
+						else
+							OVR <= '0';
+						end if;
+					end if;
+				else
+					FIRST_READ := false;
+				end if;
 			end if;
 		end if;
 	end process OVERRUN;
 	
-	PARITY_TEST: process(RESETn, CLK)
+	PARITY_TEST: process(RESETn,MCLR,CLK)
 	variable PAR_TMP	: bit;
 	variable PE_I		: bit;
 	begin
-		if RESETn = '0' then
+		if RESETn = '0' or MCRL = '1' then
 			PE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				PE <= '0';
-			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
-				PE_I := '0'; -- Initialise.
-				if RCV_STATE = PARITY then
-				    for i in 1 to 7 loop
-				        if i = 1 then
-				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
-				        else
-				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
-				        end if;
-				    end loop;
-					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
-				    	PE_I := PAR_TMP xor RXDATA_S;
-					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
-						PE_I := not PAR_TMP xor RXDATA_S;
-					else -- No parity for WS = "100" and WS = "101".
-						PE_I := '0';		
+		else
+			if rising_edge(CLK) then
+				if CLK_STRB = '1' then -- Sample parity on clock strobe.
+					PE_I := '0'; -- Initialise.
+					if RCV_STATE = PARITY then
+						for i in 1 to 7 loop
+							if i = 1 then
+								PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+							else
+								PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+							end if;
+						end loop;
+						if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+							PE_I := PAR_TMP xor RXDATA_S;
+						elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+							PE_I := not PAR_TMP xor RXDATA_S;
+						else -- No parity for WS = "100" and WS = "101".
+							PE_I := '0';	
+						end if;	
 					end if;
 				end if;
 			end if;
@@ -311,7 +318,7 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
 			-- receiver data register.
 			if RCV_STATE = SYNC and RDRF = '0' then
 				PE <= PE_I;
-			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			elsif CS = "011" and RWn = '1' and RS = '1' then
 				PE <= '0'; -- Clear when reading the data register.
 			end if;
 		end if;
@@ -320,28 +327,31 @@ DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
 	P_RDRF: process(RESETn, CLK)
 	-- Receive data register full flag.
 	begin
-		if RESETn = '0' then
-			RDRF <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RDRF <= '0';
-			elsif RCV_STATE = SYNC then
-				RDRF <= '1'; -- Data register is full until now!
-			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
-				RDRF <= '0'; -- After reading the data register ...
-			end if;
-		end if;
+		if rising_edge(CLK) then
+			if RESETn = '0' or MCLR = '1' then
+				RDRF <= '0';
+			else
+				if RCV_STATE = SYNC then
+					RDRF <= '1'; -- Data register is full until now!
+				end if;
+				if CS = "011" and RWn = '1' and RS = '1' then
+					RDRF <= '0'; -- when reading the data register ...
+				end if;
+			end if;
+		end if;
 	end process P_RDRF;
 	
 	RCV_STATEREG: process(RESETn, CLK)
 	begin
 		if RESETn = '0' then
 			RCV_STATE <= IDLE;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RCV_STATE <= IDLE;
-			else
-				RCV_STATE <= RCV_NEXT_STATE;
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					RCV_STATE <= IDLE;
+				else
+					RCV_STATE <= RCV_NEXT_STATE;
+				end if;
 			end if;
 		end if;
 	end process RCV_STATEREG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
index c8ae6fc..8a0a9fa 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_TRANSMIT is
   port (
-		CLK					: in bit;
+		CLK					: in std_logic;
         RESETn				: in bit;
 		MCLR				: in bit;
 
@@ -108,58 +108,59 @@ begin
 				'1'				when TR_STATE = STOP1 		else
 				'1'				when TR_STATE = STOP2 		else '1';
 
-	CLKDIV: process
+	CLKDIV: process(CLK)
 	variable CLK_LOCK	: boolean;
 	variable STRB_LOCK	: boolean;
 	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
 	begin
-		wait until CLK = '1' and CLK' event;
-		if CDS = "00" then -- divider off
-			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
-				CLK_STRB <= '1';
-				STRB_LOCK := true;
-			elsif TXCLK = '1' then
-				CLK_STRB <= '0';
-				STRB_LOCK := false;
-			else
-				CLK_STRB <= '0';
-			end if;
-		elsif TR_STATE = IDLE then
-			-- preset the CLKDIV with the start delays
-			if CDS = "01" then
-				CLK_DIVCNT := "0010000"; -- div by 16 mode
-			elsif CDS = "10" then
-				CLK_DIVCNT := "1000000"; -- div by 64 mode
-			end if;
-			CLK_STRB <= '0';
-		else
-			-- Works on negative TXCLK edge:
-			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
-				CLK_DIVCNT := CLK_DIVCNT - '1';
-				CLK_STRB <= '0';
-				CLK_LOCK := true;
-			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
+		if rising_edge(CLK) then
+			if CDS = "00" then -- divider off
+				if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
 					CLK_STRB <= '1';
+					STRB_LOCK := true;
+				elsif TXCLK = '1' then
+					CLK_STRB <= '0';
+					STRB_LOCK := false;
 				else
 					CLK_STRB <= '0';
 				end if;
-			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
+			elsif TR_STATE = IDLE then
+				-- preset the CLKDIV with the start delays
+				if CDS = "01" then
+					CLK_DIVCNT := "0010000"; -- div by 16 mode
+				elsif CDS = "10" then
+					CLK_DIVCNT := "1000000"; -- div by 64 mode
 				end if;
-			elsif TXCLK = '1' then
-				CLK_LOCK := false;
-				STRB_LOCK := false;
 				CLK_STRB <= '0';
 			else
-				CLK_STRB <= '0';
+				-- Works on negative TXCLK edge:
+				if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+					CLK_DIVCNT := CLK_DIVCNT - '1';
+					CLK_STRB <= '0';
+					CLK_LOCK := true;
+				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif TXCLK = '1' then
+					CLK_LOCK := false;
+					STRB_LOCK := false;
+					CLK_STRB <= '0';
+				else
+					CLK_STRB <= '0';
+				end if;
 			end if;
 		end if;
 	end process CLKDIV;
@@ -168,7 +169,7 @@ begin
 	begin
 		if RESETn = '0' then
 			DATA_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
+		elsif rising_edge(CLK) then
 			if MCLR = '1' then
 				DATA_REG <= x"00";
 			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
 	begin
 		if RESETn = '0' then
 			SHIFT_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
+		elsif rising_edge(CLK) then
 			if MCLR = '1' then
 				SHIFT_REG <= x"00";
 			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
 		end if;
 	end process SHIFTREG;	
 
-	P_BITCNT: process
+	P_BITCNT: process(CLK)
 	-- Counter for the data bits transmitted.
 	begin
-		wait until CLK = '1' and CLK' event;
-		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
-			BITCNT <= BITCNT + '1';
-		elsif TR_STATE /= SHIFTOUT then
-			BITCNT <= "000";
+		if rising_edge(CLK) then
+			if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				BITCNT <= BITCNT + '1';
+			elsif TR_STATE /= SHIFTOUT then
+				BITCNT <= "000";
+			end if;
 		end if;
 	end process P_BITCNT;
 
 	P_TDRE: process(RESETn, CLK)
 	-- Transmit data register empty flag.
-	variable LOCK	: boolean;
 	begin
-		if RESETn = '0' then
-			TDRE <= '1';
-			LOCK := false;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				TDRE <= '1';
-            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+		if rising_edge(CLK) then
+			if RESETn = '0' or MCLR = '1' then
+				TDRE <= '1';
+			else
+				if TR_NEXT_STATE = START and TR_STATE /= START then
 				-- Data has been loaded to shift register, thus data register is free again.
 				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-				-- entering the state now.
-				TDRE <= '1';
-			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
-				LOCK := true;
-			elsif E = '0' and LOCK = true then
-				-- This construction clears TDRE after the falling edge of E
-				-- and after the transmit data register has been written to.
-				TDRE <= '0';
-				LOCK := false;
+				-- entering the state now.
+					TDRE <= '1';
+				end if;
+				if  CS = "011" and RWn = '0' and RS = '1' then
+					TDRE <= '0';
+				end if;
 			end if;
 		end if;
 	end process P_TDRE;
 
-	PARITY_GEN: process
+	PARITY_GEN: process(CLK)
 	variable PAR_TMP	: bit;
 	begin
-		wait until CLK = '1' and CLK' event;
+		if rising_edge(CLK) then
 		if TR_STATE = START then -- Calculate the parity during the start phase.
 		    for i in 1 to 7 loop
 		        if i = 1 then
@@ -254,6 +250,7 @@ begin
 			else -- No parity for WS = "100" and WS = "101".
 				PARITY_I <= '0';		
 			end if;
+		end if;
 		end if;
 	end process PARITY_GEN;
 
@@ -261,11 +258,13 @@ begin
 	begin
 		if RESETn = '0' then
 			TR_STATE <= IDLE;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				TR_STATE <= IDLE;
-			else
-				TR_STATE <= TR_NEXT_STATE;
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					TR_STATE <= IDLE;
+				else
+					TR_STATE <= TR_NEXT_STATE;
+				end if;
 			end if;
 		end if;
 	end process TR_STATEREG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
index bcff094..d6953d5 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
 
 entity WF6850IP_TRANSMIT is
   port (
-		CLK					: in bit;
+		CLK					: in std_logic;
         RESETn				: in bit;
 		MCLR				: in bit;
 
@@ -113,53 +113,54 @@ begin
 	variable STRB_LOCK	: boolean;
 	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
 	begin
-		wait until CLK = '1' and CLK' event;
-		if CDS = "00" then -- divider off
-			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
-				CLK_STRB <= '1';
-				STRB_LOCK := true;
-			elsif TXCLK = '1' then
-				CLK_STRB <= '0';
-				STRB_LOCK := false;
-			else
-				CLK_STRB <= '0';
-			end if;
-		elsif TR_STATE = IDLE then
-			-- preset the CLKDIV with the start delays
-			if CDS = "01" then
-				CLK_DIVCNT := "0010000"; -- div by 16 mode
-			elsif CDS = "10" then
-				CLK_DIVCNT := "1000000"; -- div by 64 mode
-			end if;
-			CLK_STRB <= '0';
-		else
-			-- Works on negative TXCLK edge:
-			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
-				CLK_DIVCNT := CLK_DIVCNT - '1';
-				CLK_STRB <= '0';
-				CLK_LOCK := true;
-			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
+		if rising_edge(CLK) then
+			if CDS = "00" then -- divider off
+				if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
 					CLK_STRB <= '1';
+					STRB_LOCK := true;
+				elsif TXCLK = '1' then
+					CLK_STRB <= '0';
+					STRB_LOCK := false;
 				else
 					CLK_STRB <= '0';
 				end if;
-			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
+			elsif TR_STATE = IDLE then
+				-- preset the CLKDIV with the start delays
+				if CDS = "01" then
+					CLK_DIVCNT := "0010000"; -- div by 16 mode
+				elsif CDS = "10" then
+					CLK_DIVCNT := "1000000"; -- div by 64 mode
 				end if;
-			elsif TXCLK = '1' then
-				CLK_LOCK := false;
-				STRB_LOCK := false;
 				CLK_STRB <= '0';
 			else
-				CLK_STRB <= '0';
+				-- Works on negative TXCLK edge:
+				if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+					CLK_DIVCNT := CLK_DIVCNT - '1';
+					CLK_STRB <= '0';
+					CLK_LOCK := true;
+				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+					if STRB_LOCK = false then
+						STRB_LOCK := true;
+						CLK_STRB <= '1';
+					else
+						CLK_STRB <= '0';
+					end if;
+				elsif TXCLK = '1' then
+					CLK_LOCK := false;
+					STRB_LOCK := false;
+					CLK_STRB <= '0';
+				else
+					CLK_STRB <= '0';
+				end if;
 			end if;
 		end if;
 	end process CLKDIV;
@@ -168,7 +169,7 @@ begin
 	begin
 		if RESETn = '0' then
 			DATA_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
+		elsif rising_edge(CLK) then
 			if MCLR = '1' then
 				DATA_REG <= x"00";
 			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
 	begin
 		if RESETn = '0' then
 			SHIFT_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
+		elsif rising_edge(CLK) then
 			if MCLR = '1' then
 				SHIFT_REG <= x"00";
 			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
 		end if;
 	end process SHIFTREG;	
 
-	P_BITCNT: process
+	P_BITCNT: process(CLK)
 	-- Counter for the data bits transmitted.
 	begin
-		wait until CLK = '1' and CLK' event;
-		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
-			BITCNT <= BITCNT + '1';
-		elsif TR_STATE /= SHIFTOUT then
-			BITCNT <= "000";
+		if rising_edge(CLK) then
+			if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				BITCNT <= BITCNT + '1';
+			elsif TR_STATE /= SHIFTOUT then
+				BITCNT <= "000";
+			end if;
 		end if;
 	end process P_BITCNT;
 
 	P_TDRE: process(RESETn, CLK)
 	-- Transmit data register empty flag.
-	variable LOCK	: boolean;
 	begin
-		if RESETn = '0' then
-			TDRE <= '1';
-			LOCK := false;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				TDRE <= '1';
-            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+		if rising_edge(CLK) then
+			if RESETn = '0' or MCLR = '1' then
+				TDRE <= '1';
+			else
+				if TR_NEXT_STATE = START and TR_STATE /= START then
 				-- Data has been loaded to shift register, thus data register is free again.
 				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-				-- entering the state now.
-				TDRE <= '1';
-			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
-				LOCK := true;
-			elsif E = '0' and LOCK = true and CS /= "011" then
-				-- This construction clears TDRE after the falling edge of E
-				-- and after the transmit data register has been written to.
-				TDRE <= '0';
-				LOCK := false;
+				-- entering the state now.
+					TDRE <= '1';
+				end if;
+				if  CS = "011" and RWn = '0' and RS = '1' then
+					TDRE <= '0';
+				end if;
 			end if;
 		end if;
 	end process P_TDRE;
 
-	PARITY_GEN: process
+	PARITY_GEN: process(CLK)
 	variable PAR_TMP	: bit;
 	begin
-		wait until CLK = '1' and CLK' event;
+		if rising_edge(CLK) then
 		if TR_STATE = START then -- Calculate the parity during the start phase.
 		    for i in 1 to 7 loop
 		        if i = 1 then
@@ -254,6 +250,7 @@ begin
 			else -- No parity for WS = "100" and WS = "101".
 				PARITY_I <= '0';		
 			end if;
+		end if;
 		end if;
 	end process PARITY_GEN;
 
@@ -261,11 +258,13 @@ begin
 	begin
 		if RESETn = '0' then
 			TR_STATE <= IDLE;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				TR_STATE <= IDLE;
-			else
-				TR_STATE <= TR_NEXT_STATE;
+		else
+			if rising_edge(CLK) then
+				if MCLR = '1' then
+					TR_STATE <= IDLE;
+				else
+					TR_STATE <= TR_NEXT_STATE;
+				end if;
 			end if;
 		end if;
 	end process TR_STATEREG;
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
index a455469..16de480 100644
--- a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
@@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler
 	VSYNC : INPUT;
 	HSYNC : INPUT;
 	DMA_DRQ : INPUT;
+	nRSTO : INPUT;
 	nIRQ[7..2] : OUTPUT;
 	INT_HANDLER_TA : OUTPUT;
 	ACP_CONF[31..0] : OUTPUT;
@@ -56,6 +57,8 @@ VARIABLE
 	INT_IN[31..0]			:NODE;
 	INT_ENA[31..0]			:DFFE;
 	INT_ENA_CS				:NODE;
+	INT_L[9..0]				:DFF;
+	INT_LA[9..0][3..0]		:DFF;
 	ACP_CONF[31..0]			:DFFE;
 	ACP_CONF_CS				:NODE;
 	PSEUDO_BUS_ERROR		:NODE;
@@ -101,6 +104,7 @@ BEGIN
 	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
 -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
 	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA[].CLRN = nRSTO;
 	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
 	INT_ENA[] = FB_AD[];
 	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
@@ -120,15 +124,15 @@ BEGIN
 	!nIRQ2 = HSYNC 						& INT_ENA[26];
 	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
 	!nIRQ4 = VSYNC 						& INT_ENA[28];
-	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
+	!nIRQ5 = INT_LATCH[]!=H"00000000" 	& INT_ENA[29];
 	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
 	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
 
 PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..4]==H"F8E0"			-- VME
-							#  FB_ADR[19..4]==H"F920"			-- PADDLE
-							#  FB_ADR[19..4]==H"F921"			-- PADDLE
-							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F922"			-- PADDLE
 							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
 							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
 							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
@@ -136,27 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
 							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
 							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
-							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
-							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
-							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F892"			-- DMA SOUND
+							 );
 -- IF VIDEO ADR CHANGE
 TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
 
 -- INTERRUPT LATCH
-	INT_LATCH[] = H"FFFFFFFF";
-	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
-	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
-	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
-	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
-	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
-	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
-	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
-	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
-	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
-	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	INT_L[].CLK = MAIN_CLK;
+	INT_L[].CLRN = nRSTO;
+	INT_L0 = PIC_INT & INT_ENA[0];
+	INT_L1 = E0_INT & INT_ENA[1];
+	INT_L2 = DVI_INT & INT_ENA[2];
+	INT_L3 = !nPCI_INTA & INT_ENA[3];
+	INT_L4 = !nPCI_INTB & INT_ENA[4];
+	INT_L5 = !nPCI_INTC & INT_ENA[5];
+	INT_L6 = !nPCI_INTD & INT_ENA[6];
+	INT_L7 = DSP_INT & INT_ENA[7];
+	INT_L8 = VSYNC & INT_ENA[8];
+	INT_L9 = HSYNC & INT_ENA[9];
 	
--- INTERRUPT CLEAR
-	INT_LATCH[].CLRN = !INT_CLEAR[];
+	INT_LA[][].CLK = MAIN_CLK;
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
+	FOR I IN 0 TO 9 GENERATE
+		INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
+		INT_LA[I][] = INT_LA[I][]+1 &  INT_L[I] & INT_LA[I][]<7 
+		            # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
+		            # 15            &  INT_L[I] & INT_LA[I][]>6
+		            # 0             & !INT_L[I] & INT_LA[I][]<9;
+		INT_LATCH[I].CLK = INT_LA[I][3];
+	END GENERATE;
 	
 -- INT_IN
 	INT_IN0 = PIC_INT;
@@ -206,125 +221,14 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
 	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
 	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	WERTE[7..0][10] = FB_AD[23..16];
-	WERTE[7..0][11] = FB_AD[23..16];
-	WERTE[7..0][12] = FB_AD[23..16];
-	WERTE[7..0][13] = FB_AD[23..16];
-	WERTE[7..0][14] = FB_AD[23..16];
-	WERTE[7..0][15] = FB_AD[23..16];
-	WERTE[7..0][16] = FB_AD[23..16];
-	WERTE[7..0][17] = FB_AD[23..16];
-	WERTE[7..0][18] = FB_AD[23..16];
-	WERTE[7..0][19] = FB_AD[23..16];
-	WERTE[7..0][20] = FB_AD[23..16];
-	WERTE[7..0][21] = FB_AD[23..16];
-	WERTE[7..0][22] = FB_AD[23..16];
-	WERTE[7..0][23] = FB_AD[23..16];
-	WERTE[7..0][24] = FB_AD[23..16];
-	WERTE[7..0][25] = FB_AD[23..16];
-	WERTE[7..0][26] = FB_AD[23..16];
-	WERTE[7..0][27] = FB_AD[23..16];
-	WERTE[7..0][28] = FB_AD[23..16];
-	WERTE[7..0][29] = FB_AD[23..16];
-	WERTE[7..0][30] = FB_AD[23..16];
-	WERTE[7..0][31] = FB_AD[23..16];
-	WERTE[7..0][32] = FB_AD[23..16];
-	WERTE[7..0][33] = FB_AD[23..16];
-	WERTE[7..0][34] = FB_AD[23..16];
-	WERTE[7..0][35] = FB_AD[23..16];
-	WERTE[7..0][36] = FB_AD[23..16];
-	WERTE[7..0][37] = FB_AD[23..16];
-	WERTE[7..0][38] = FB_AD[23..16];
-	WERTE[7..0][39] = FB_AD[23..16];
-	WERTE[7..0][40] = FB_AD[23..16];
-	WERTE[7..0][41] = FB_AD[23..16];
-	WERTE[7..0][42] = FB_AD[23..16];
-	WERTE[7..0][43] = FB_AD[23..16];
-	WERTE[7..0][44] = FB_AD[23..16];
-	WERTE[7..0][45] = FB_AD[23..16];
-	WERTE[7..0][46] = FB_AD[23..16];
-	WERTE[7..0][47] = FB_AD[23..16];
-	WERTE[7..0][48] = FB_AD[23..16];
-	WERTE[7..0][49] = FB_AD[23..16];
-	WERTE[7..0][50] = FB_AD[23..16];
-	WERTE[7..0][51] = FB_AD[23..16];
-	WERTE[7..0][52] = FB_AD[23..16];
-	WERTE[7..0][53] = FB_AD[23..16];
-	WERTE[7..0][54] = FB_AD[23..16];
-	WERTE[7..0][55] = FB_AD[23..16];
-	WERTE[7..0][56] = FB_AD[23..16];
-	WERTE[7..0][57] = FB_AD[23..16];
-	WERTE[7..0][58] = FB_AD[23..16];
-	WERTE[7..0][59] = FB_AD[23..16];
-	WERTE[7..0][60] = FB_AD[23..16];
-	WERTE[7..0][61] = FB_AD[23..16];
-	WERTE[7..0][62] = FB_AD[23..16];
-	WERTE[7..0][63] = FB_AD[23..16];
-	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
-	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
-	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
-	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
-	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
-	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
-	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
-	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
-	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
-	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
-	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
-	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
-	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
-	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
-	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
-	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
-	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
-	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
-	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
-	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
-	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
-	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
-	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
-	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
-	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
-	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
-	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
-	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
-	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
-	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
-	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
-	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
-	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
-	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
-	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
-	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
-	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
-	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
-	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
-	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
-	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
-	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
-	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
-	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
-	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
-	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
-	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
-	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
-	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
-	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
-	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
-	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
-	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
-	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
-	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
-	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
-	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
-	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
-	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
-	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
-	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
-	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
-	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	FOR I IN 10 TO 63 GENERATE
+		WERTE[7..0][I] = FB_AD[23..16];
+	END GENERATE;
+	FOR I IN 0 TO 63 GENERATE
+		WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
+	END GENERATE;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	
+	PIC_INT_SYNC[0] = PIC_INT;
 	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
 	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
 	UPDATE_ON = !WERTE[7][11];		
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
index e3e49eb..459192d 100644
--- a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
@@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler
 	VSYNC : INPUT;
 	HSYNC : INPUT;
 	DMA_DRQ : INPUT;
+	nRSTO : INPUT;
 	nIRQ[7..2] : OUTPUT;
 	INT_HANDLER_TA : OUTPUT;
 	ACP_CONF[31..0] : OUTPUT;
@@ -56,6 +57,8 @@ VARIABLE
 	INT_IN[31..0]			:NODE;
 	INT_ENA[31..0]			:DFFE;
 	INT_ENA_CS				:NODE;
+	INT_L[9..0]				:DFF;
+	INT_LA[9..0][3..0]		:DFF;
 	ACP_CONF[31..0]			:DFFE;
 	ACP_CONF_CS				:NODE;
 	PSEUDO_BUS_ERROR		:NODE;
@@ -101,6 +104,7 @@ BEGIN
 	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
 -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
 	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA[].CLRN = nRSTO;
 	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
 	INT_ENA[] = FB_AD[];
 	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
@@ -126,9 +130,9 @@ BEGIN
 
 PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..4]==H"F8E0"			-- VME
-							#  FB_ADR[19..4]==H"F920"			-- PADDLE
-							#  FB_ADR[19..4]==H"F921"			-- PADDLE
-							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F922"			-- PADDLE
 							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
 							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
 							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
@@ -136,27 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
 							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
 							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
 							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
-							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
-							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
-							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F892"			-- DMA SOUND
+							 );
 -- IF VIDEO ADR CHANGE
-TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			-- VIDEO BASE ADR HIGH 0xFFFF8201/2
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
 
 -- INTERRUPT LATCH
-	INT_LATCH[] = H"FFFFFFFF";
-	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
-	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
-	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
-	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
-	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
-	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
-	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
-	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
-	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
-	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	INT_L[].CLK = MAIN_CLK;
+	INT_L[].CLRN = nRSTO;
+	INT_L0 = PIC_INT & INT_ENA[0];
+	INT_L1 = E0_INT & INT_ENA[1];
+	INT_L2 = DVI_INT & INT_ENA[2];
+	INT_L3 = !nPCI_INTA & INT_ENA[3];
+	INT_L4 = !nPCI_INTB & INT_ENA[4];
+	INT_L5 = !nPCI_INTC & INT_ENA[5];
+	INT_L6 = !nPCI_INTD & INT_ENA[6];
+	INT_L7 = DSP_INT & INT_ENA[7];
+	INT_L8 = VSYNC & INT_ENA[8];
+	INT_L9 = HSYNC & INT_ENA[9];
 	
--- INTERRUPT CLEAR
-	INT_LATCH[].CLRN = !INT_CLEAR[];
+	INT_LA[][].CLK = MAIN_CLK;
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
+	FOR I IN 0 TO 9 GENERATE
+		INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
+		INT_LA[I][] = INT_LA[I][]+1 &  INT_L[I] & INT_LA[I][]<7 
+		            # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
+		            # 15            &  INT_L[I] & INT_LA[I][]>6
+		            # 0             & !INT_L[I] & INT_LA[I][]<9;
+		INT_LATCH[I].CLK = INT_LA[I][3];
+	END GENERATE;
 	
 -- INT_IN
 	INT_IN0 = PIC_INT;
@@ -206,125 +221,14 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			-- VIDEO BASE ADR HIGH 0xFFFF8201/2
 	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
 	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
 	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	WERTE[7..0][10] = FB_AD[23..16];
-	WERTE[7..0][11] = FB_AD[23..16];
-	WERTE[7..0][12] = FB_AD[23..16];
-	WERTE[7..0][13] = FB_AD[23..16];
-	WERTE[7..0][14] = FB_AD[23..16];
-	WERTE[7..0][15] = FB_AD[23..16];
-	WERTE[7..0][16] = FB_AD[23..16];
-	WERTE[7..0][17] = FB_AD[23..16];
-	WERTE[7..0][18] = FB_AD[23..16];
-	WERTE[7..0][19] = FB_AD[23..16];
-	WERTE[7..0][20] = FB_AD[23..16];
-	WERTE[7..0][21] = FB_AD[23..16];
-	WERTE[7..0][22] = FB_AD[23..16];
-	WERTE[7..0][23] = FB_AD[23..16];
-	WERTE[7..0][24] = FB_AD[23..16];
-	WERTE[7..0][25] = FB_AD[23..16];
-	WERTE[7..0][26] = FB_AD[23..16];
-	WERTE[7..0][27] = FB_AD[23..16];
-	WERTE[7..0][28] = FB_AD[23..16];
-	WERTE[7..0][29] = FB_AD[23..16];
-	WERTE[7..0][30] = FB_AD[23..16];
-	WERTE[7..0][31] = FB_AD[23..16];
-	WERTE[7..0][32] = FB_AD[23..16];
-	WERTE[7..0][33] = FB_AD[23..16];
-	WERTE[7..0][34] = FB_AD[23..16];
-	WERTE[7..0][35] = FB_AD[23..16];
-	WERTE[7..0][36] = FB_AD[23..16];
-	WERTE[7..0][37] = FB_AD[23..16];
-	WERTE[7..0][38] = FB_AD[23..16];
-	WERTE[7..0][39] = FB_AD[23..16];
-	WERTE[7..0][40] = FB_AD[23..16];
-	WERTE[7..0][41] = FB_AD[23..16];
-	WERTE[7..0][42] = FB_AD[23..16];
-	WERTE[7..0][43] = FB_AD[23..16];
-	WERTE[7..0][44] = FB_AD[23..16];
-	WERTE[7..0][45] = FB_AD[23..16];
-	WERTE[7..0][46] = FB_AD[23..16];
-	WERTE[7..0][47] = FB_AD[23..16];
-	WERTE[7..0][48] = FB_AD[23..16];
-	WERTE[7..0][49] = FB_AD[23..16];
-	WERTE[7..0][50] = FB_AD[23..16];
-	WERTE[7..0][51] = FB_AD[23..16];
-	WERTE[7..0][52] = FB_AD[23..16];
-	WERTE[7..0][53] = FB_AD[23..16];
-	WERTE[7..0][54] = FB_AD[23..16];
-	WERTE[7..0][55] = FB_AD[23..16];
-	WERTE[7..0][56] = FB_AD[23..16];
-	WERTE[7..0][57] = FB_AD[23..16];
-	WERTE[7..0][58] = FB_AD[23..16];
-	WERTE[7..0][59] = FB_AD[23..16];
-	WERTE[7..0][60] = FB_AD[23..16];
-	WERTE[7..0][61] = FB_AD[23..16];
-	WERTE[7..0][62] = FB_AD[23..16];
-	WERTE[7..0][63] = FB_AD[23..16];
-	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
-	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
-	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
-	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
-	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
-	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
-	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
-	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
-	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
-	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
-	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
-	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
-	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
-	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
-	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
-	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
-	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
-	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
-	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
-	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
-	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
-	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
-	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
-	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
-	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
-	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
-	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
-	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
-	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
-	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
-	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
-	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
-	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
-	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
-	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
-	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
-	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
-	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
-	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
-	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
-	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
-	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
-	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
-	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
-	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
-	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
-	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
-	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
-	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
-	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
-	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
-	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
-	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
-	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
-	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
-	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
-	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
-	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
-	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
-	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
-	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
-	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
-	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	FOR I IN 10 TO 63 GENERATE
+		WERTE[7..0][I] = FB_AD[23..16];
+	END GENERATE;
+	FOR I IN 0 TO 63 GENERATE
+		WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
+	END GENERATE;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	
+	PIC_INT_SYNC[0] = PIC_INT;
 	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
 	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
 	UPDATE_ON = !WERTE[7][11];		
diff --git a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
new file mode 100644
index 0000000..797d4f8
--- /dev/null
+++ b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
@@ -0,0 +1,20 @@
+PLL_Name	altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
+PLLJITTER	36
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
+PLLJITTER	43
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
+PLLJITTER	NA
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
+PLLJITTER	31
+PLLSPEmax	84
+PLLSPEmin	-53
+
diff --git a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
deleted file mode 100644
index e09ed0b..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd
+++ /dev/null
@@ -1,75 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2008 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
--- Created on Fri Oct 16 15:40:59 2009
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-
---  Entity Declaration
-
-ENTITY BLITTER IS
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	PORT
-	(
-		nRSTO : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		FB_ALE : IN STD_LOGIC;
-		nFB_WR : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
-		BLITTER_ON : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		nFB_CS1 : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		nFB_CS3 : IN STD_LOGIC;
-		DDRCLK0 : IN STD_LOGIC;
-		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
-		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
-		BLITTER_RUN : OUT STD_LOGIC;
-		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
-		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
-		BLITTER_SIG : OUT STD_LOGIC;
-		BLITTER_WR : OUT STD_LOGIC;
-		BLITTER_TA : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
-	);
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-	
-END BLITTER;
-
-
---  Architecture Body
-
-ARCHITECTURE BLITTER_architecture OF BLITTER IS
-
-	
-BEGIN
-	BLITTER_RUN <= '0';
-	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
-	BLITTER_ADR <=  x"76543210";
-	BLITTER_SIG <= '0';
-	BLITTER_WR <= '0';
-	BLITTER_TA <= '0';
-
-END BLITTER_architecture;
diff --git a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak b/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
deleted file mode 100644
index f674080..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/BLITTER.vhd.bak
+++ /dev/null
@@ -1,75 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2008 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
--- Created on Fri Oct 16 15:40:59 2009
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-
---  Entity Declaration
-
-ENTITY BLITTER IS
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	PORT
-	(
-		nRSTO : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		FB_ALE : IN STD_LOGIC;
-		nFB_WR : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
-		BLITTER_ON : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		nFB_CS1 : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		nFB_CS3 : IN STD_LOGIC;
-		DDRCLK0 : IN STD_LOGIC;
-		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
-		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
-		BLITTER_RUN : OUT STD_LOGIC;
-		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
-		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
-		BLITTER_SIG : OUT STD_LOGIC;
-		BLITTER_WR : OUT STD_LOGIC;
-		BLITTER_TA : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
-	);
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-	
-END BLITTER;
-
-
---  Architecture Body
-
-ARCHITECTURE BLITTER_architecture OF BLITTER IS
-
-	
-BEGIN
-	BLITTER_RUN <= '0';
-	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
-	BLITTER_ADR <=  x"FEDCBA9876543210";
-	BLITTER_SIG <= '0';
-	BLITTER_WR <= '0';
-	BLITTER_TA <= '0';
-
-END BLITTER_architecture;
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
new file mode 100644
index 0000000..b0acfb7
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
@@ -0,0 +1,110 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 128)
+	(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 109 31 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
+		(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 112 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 104 104)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 168 32)(line_width 3))
+	)
+	(drawing
+		(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 96)(line_width 1))
+		(line (pt 168 96)(pt 128 96)(line_width 1))
+		(line (pt 128 96)(pt 128 24)(line_width 1))
+		(line (pt 112 27)(pt 120 27)(line_width 1))
+		(line (pt 120 27)(pt 120 39)(line_width 1))
+		(line (pt 120 39)(pt 112 39)(line_width 1))
+		(line (pt 112 39)(pt 112 27)(line_width 1))
+		(line (pt 112 34)(pt 114 36)(line_width 1))
+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 104 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
+		(line (pt 120 43)(pt 120 55)(line_width 1))
+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
+		(line (pt 112 50)(pt 114 52)(line_width 1))
+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 104 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 104 68)(pt 112 68)(line_width 1))
+		(line (pt 120 64)(pt 128 64)(line_width 1))
+		(line (pt 112 83)(pt 120 83)(line_width 1))
+		(line (pt 120 83)(pt 120 95)(line_width 1))
+		(line (pt 120 95)(pt 112 95)(line_width 1))
+		(line (pt 112 95)(pt 112 83)(line_width 1))
+		(line (pt 112 90)(pt 114 92)(line_width 1))
+		(line (pt 114 92)(pt 112 94)(line_width 1))
+		(line (pt 104 92)(pt 112 92)(line_width 1))
+		(line (pt 120 88)(pt 128 88)(line_width 3))
+		(line (pt 104 36)(pt 104 105)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp
new file mode 100644
index 0000000..d0a0d93
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altsyncram0
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		byteena_a		: IN STD_LOGIC_VECTOR (1 DOWNTO 0) :=  (OTHERS => '1');
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		wren		: IN STD_LOGIC  := '0';
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
new file mode 100644
index 0000000..f3eee7b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altsyncram0 
+(
+	address[3..0],
+	byteena_a[1..0],
+	clock,
+	data[15..0],
+	wren
+)
+
+RETURNS (
+	q[15..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
new file mode 100644
index 0000000..c42bd21
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
new file mode 100644
index 0000000..f260092
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
@@ -0,0 +1,181 @@
+-- megafunction wizard: %ALTSYNCRAM%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altsyncram0.tdf
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "altsyncram.inc";
+
+
+
+SUBDESIGN altsyncram0
+(
+	address[3..0]	 : INPUT;
+	byteena_a[1..0]	 : INPUT = VCC;
+	clock	 : INPUT = VCC;
+	data[15..0]	 : INPUT;
+	wren	 : INPUT = GND;
+	q[15..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	altsyncram_component : altsyncram WITH (
+			BYTE_SIZE = 8,
+			CLOCK_ENABLE_INPUT_A = "BYPASS",
+			CLOCK_ENABLE_OUTPUT_A = "BYPASS",
+			INTENDED_DEVICE_FAMILY = "Cyclone III",
+			LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
+			LPM_TYPE = "altsyncram",
+			NUMWORDS_A = 16,
+			OPERATION_MODE = "SINGLE_PORT",
+			OUTDATA_ACLR_A = "NONE",
+			OUTDATA_REG_A = "UNREGISTERED",
+			POWER_UP_UNINITIALIZED = "FALSE",
+			READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
+			READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
+			WIDTHAD_A = 4,
+			WIDTH_A = 16,
+			WIDTH_BYTEENA_A = 2
+			);
+
+BEGIN
+
+	q[15..0] = altsyncram_component.q_a[15..0];
+	altsyncram_component.wren_a = wren;
+	altsyncram_component.clock0 = clock;
+	altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
+	altsyncram_component.address_a[3..0] = address[3..0];
+	altsyncram_component.data_a[15..0] = data[15..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
+-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]
+-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
+-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
+-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
+-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg b/FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..84314f4e1a03352ec152e2aff9a922132f3d7fea
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HcmV?d00001

diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html b/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
new file mode 100644
index 0000000..7b89eb9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for "altsyncram0.tdf" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
+<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT b/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
new file mode 100644
index 0000000..1ad8825
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
@@ -0,0 +1,427 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
+-- Created on Sat Jan 15 11:06:17 2011
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
+
+CONSTANT	BL_SKEW_LF = 255;
+
+--  Title Statement (optional)
+TITLE "Blitter";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ON : INPUT;
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	DDRCLK0 : INPUT;
+	BLITTER_DIN[127..0] : INPUT;
+	BLITTER_DACK[4..0] : INPUT;
+	SR_BLITTER_DACK : INPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_ADR[31..0] : OUTPUT;
+	BLITTER_SIG : OUTPUT;
+	BLITTER_WR : OUTPUT;
+	BLITTER_TA : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	BLITTER_CS					:NODE;
+	BL_HRAM0_CS					:NODE;
+	BL_HRAM0[15..0]				:DFFE;
+	BL_HRAM1_CS					:NODE;
+	BL_HRAM1[15..0]				:DFFE;
+	BL_HRAM2_CS					:NODE;
+	BL_HRAM2[15..0]				:DFFE;
+	BL_HRAM3_CS					:NODE;
+	BL_HRAM3[15..0]				:DFFE;
+	BL_HRAM4_CS					:NODE;
+	BL_HRAM4[15..0]				:DFFE;
+	BL_HRAM5_CS					:NODE;
+	BL_HRAM5[15..0]				:DFFE;
+	BL_HRAM6_CS					:NODE;
+	BL_HRAM6[15..0]				:DFFE;
+	BL_HRAM7_CS					:NODE;
+	BL_HRAM7[15..0]				:DFFE;
+	BL_HRAM8_CS					:NODE;
+	BL_HRAM8[15..0]				:DFFE;
+	BL_HRAM9_CS					:NODE;
+	BL_HRAM9[15..0]				:DFFE;
+	BL_HRAMA_CS					:NODE;
+	BL_HRAMA[15..0]				:DFFE;
+	BL_HRAMB_CS					:NODE;
+	BL_HRAMB[15..0]				:DFFE;
+	BL_HRAMC_CS					:NODE;
+	BL_HRAMC[15..0]				:DFFE;
+	BL_HRAMD_CS					:NODE;
+	BL_HRAMD[15..0]				:DFFE;
+	BL_HRAME_CS					:NODE;
+	BL_HRAME[15..0]				:DFFE;
+	BL_HRAMF_CS					:NODE;
+	BL_HRAMF[15..0]				:DFFE;
+	BL_SRC_X_INC_CS				:NODE;
+	BL_SRC_X_INC[15..0]			:DFFE;
+	BL_SRC_Y_INC_CS				:NODE;
+	BL_SRC_Y_INC[15..0]			:DFFE;
+	BL_ENDMASK1_CS				:NODE;
+	BL_ENDMASK1[15..0]			:DFFE;
+	BL_ENDMASK2_CS				:NODE;
+	BL_ENDMASK2[15..0]			:DFFE;
+	BL_ENDMASK3_CS				:NODE;
+	BL_ENDMASK3[15..0]			:DFFE;
+	BL_SRC_ADRH_CS				:NODE;
+	BL_SRC_ADRL_CS				:NODE;
+	BL_SRC_ADR[31..0]			:DFFE;
+	BL_DST_X_INC_CS				:NODE;
+	BL_DST_X_INC[15..0]			:DFFE;
+	BL_DST_Y_INC_CS				:NODE;
+	BL_DST_Y_INC[15..0]			:DFFE;
+	BL_DST_ADRH_CS				:NODE;
+	BL_DST_ADRL_CS				:NODE;
+	BL_DST_ADR[31..0]			:DFFE;
+	BL_X_CNT_CS					:NODE;
+	BL_X_CNT[15..0]				:DFFE;
+	BL_Y_CNT_CS					:NODE;
+	BL_Y_CNT[15..0]				:DFFE;
+	BL_HT_OP_CS					:NODE;
+	BL_HT_OP[7..0]				:DFFE;
+	BL_LC_OP[7..0]				:DFFE;
+	BL_LN_CS					:NODE;
+	BL_LN[7..0]					:DFFE;
+	BL_SKEW[7..0]				:DFFE;
+	
+	BL_SKEW_EXT[6..0]			:NODE;
+	BL_SKEW_IN[255..0]			:DFFE;
+	BL_SKEW_OUT[255..0]			:DFFE;
+	
+	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
+	BL_READ_SRC					:DFFE;
+	BL_DST_BUFFER[127..0]		:DFFE;
+	BL_READ_DST					:DFFE;
+	
+	COUNT[18..0]				:DFF;
+	
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- BLITTER CS
+	BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40
+	BLITTER_TA = BLITTER_CS;
+-- REGISTER
+	-- HALFTON RAM 0
+	BL_HRAM0[].CLK = MAIN_CLK;
+	BL_HRAM0[15..0] = FB_AD[31..16];
+	BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500";						-- $F8A00/2
+	BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
+	BL_HRAM0[7..0].ENA  = BL_HRAM0_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 1
+	BL_HRAM1[].CLK = MAIN_CLK;
+	BL_HRAM1[15..0] = FB_AD[31..16];
+	BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501";						-- $F8A02/2
+	BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
+	BL_HRAM1[7..0].ENA  = BL_HRAM1_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 2
+	BL_HRAM2[].CLK = MAIN_CLK;
+	BL_HRAM2[15..0] = FB_AD[31..16];
+	BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502";						-- $F8A04/2
+	BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
+	BL_HRAM2[7..0].ENA  = BL_HRAM2_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 3
+	BL_HRAM3[].CLK = MAIN_CLK;
+	BL_HRAM3[15..0] = FB_AD[31..16];
+	BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503";						-- $F8A06/2
+	BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
+	BL_HRAM3[7..0].ENA  = BL_HRAM3_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 4
+	BL_HRAM4[].CLK = MAIN_CLK;
+	BL_HRAM4[15..0] = FB_AD[31..16];
+	BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504";						-- $F8A08/2
+	BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
+	BL_HRAM4[7..0].ENA  = BL_HRAM4_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 5
+	BL_HRAM5[].CLK = MAIN_CLK;
+	BL_HRAM5[15..0] = FB_AD[31..16];
+	BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505";						-- $F8A08/2
+	BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
+	BL_HRAM5[7..0].ENA  = BL_HRAM5_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 6
+	BL_HRAM6[].CLK = MAIN_CLK;
+	BL_HRAM6[15..0] = FB_AD[31..16];
+	BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506";						-- $F8A08/2
+	BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
+	BL_HRAM6[7..0].ENA  = BL_HRAM6_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 7
+	BL_HRAM7[].CLK = MAIN_CLK;
+	BL_HRAM7[15..0] = FB_AD[31..16];
+	BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507";						-- $F8A08/2
+	BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
+	BL_HRAM7[7..0].ENA  = BL_HRAM7_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 8
+	BL_HRAM8[].CLK = MAIN_CLK;
+	BL_HRAM8[15..0] = FB_AD[31..16];
+	BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508";						-- $F8A10/2
+	BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
+	BL_HRAM8[7..0].ENA  = BL_HRAM8_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 9
+	BL_HRAM9[].CLK = MAIN_CLK;
+	BL_HRAM9[15..0] = FB_AD[31..16];
+	BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509";						-- $F8A12/2
+	BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
+	BL_HRAM9[7..0].ENA  = BL_HRAM9_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 10
+	BL_HRAMA[].CLK = MAIN_CLK;
+	BL_HRAMA[15..0] = FB_AD[31..16];
+	BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A";						-- $F8A4/2
+	BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
+	BL_HRAMA[7..0].ENA  = BL_HRAMA_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 11
+	BL_HRAMB[].CLK = MAIN_CLK;
+	BL_HRAMB[15..0] = FB_AD[31..16];
+	BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B";						-- $F8A16/2
+	BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
+	BL_HRAMB[7..0].ENA  = BL_HRAMB_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 12
+	BL_HRAMC[].CLK = MAIN_CLK;
+	BL_HRAMC[15..0] = FB_AD[31..16];
+	BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C";						-- $F8A18/2
+	BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
+	BL_HRAMC[7..0].ENA  = BL_HRAMC_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 13
+	BL_HRAMD[].CLK = MAIN_CLK;
+	BL_HRAMD[15..0] = FB_AD[31..16];
+	BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D";						-- $F8A1A/2
+	BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
+	BL_HRAMD[7..0].ENA  = BL_HRAMD_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 14
+	BL_HRAME[].CLK = MAIN_CLK;
+	BL_HRAME[15..0] = FB_AD[31..16];
+	BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E";						-- $F8A1C/2
+	BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
+	BL_HRAME[7..0].ENA  = BL_HRAME_CS & !nFB_WR & FB_16B1;
+	-- HALFTON RAM 15
+	BL_HRAMF[].CLK = MAIN_CLK;
+	BL_HRAMF[15..0] = FB_AD[31..16];
+	BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F";						-- $F8A1E/2
+	BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
+	BL_HRAMF[7..0].ENA  = BL_HRAMF_CS & !nFB_WR & FB_16B1;
+	-- SRC X INC
+	BL_SRC_X_INC[].CLK = MAIN_CLK;
+	BL_SRC_X_INC[] = FB_AD[31..16];
+	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20/2
+	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC Y INC
+	BL_SRC_Y_INC[].CLK = MAIN_CLK;
+	BL_SRC_Y_INC[] = FB_AD[31..16];
+	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22/2
+	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR HIGH
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[31..16] = FB_AD[31..16];
+	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
+	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR LOW
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[15..0] = FB_AD[31..16];
+	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
+	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 1
+	BL_ENDMASK1[].CLK = MAIN_CLK;
+	BL_ENDMASK1[] = FB_AD[31..16];
+	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";					-- $F8A28/2
+	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 2
+	BL_ENDMASK2[].CLK = MAIN_CLK;
+	BL_ENDMASK2[] = FB_AD[31..16];
+	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";					-- $F8A2A/2
+	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 3
+	BL_ENDMASK3[].CLK = MAIN_CLK;
+	BL_ENDMASK3[] = FB_AD[31..16];
+	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";					-- $F8A2C/2
+	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
+	-- DST X INC
+	BL_DST_X_INC[].CLK = MAIN_CLK;
+	BL_DST_X_INC[] = FB_AD[31..16];
+	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";					-- $F8A2E/2
+	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
+	-- DST Y INC
+	BL_DST_Y_INC[].CLK = MAIN_CLK;
+	BL_DST_Y_INC[] = FB_AD[31..16];
+	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";					-- $F8A30/2
+	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
+	-- DST ADR HIGH
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[31..16] = FB_AD[31..16];
+	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
+	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
+	-- DST ADR LOW
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[15..0] = FB_AD[31..16];
+	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
+	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
+	-- X COUNT
+	BL_X_CNT[].CLK = MAIN_CLK;
+	BL_X_CNT[] = FB_AD[31..16];
+	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";						-- $F8A36/2
+	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
+	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
+	-- Y COUNT
+	BL_Y_CNT[].CLK = MAIN_CLK;
+	BL_Y_CNT[] = FB_AD[31..16];
+	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";						-- $F8A38/2
+	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
+	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
+	-- HALFTONE OP BYT
+	BL_HT_OP[].CLK = MAIN_CLK;
+	BL_HT_OP[] = FB_AD[31..24];
+	BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A/2
+	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
+	-- LOGIC OP BYT
+	BL_LC_OP[].CLK = MAIN_CLK;
+	BL_LC_OP[] = FB_AD[23..16];
+	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
+	-- LINE NUMBER BYT
+	BL_LN[].CLK = MAIN_CLK;
+	BL_LN[] = FB_AD[31..24];
+	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";							-- $F8A3C/2
+	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
+	-- SKEW BYT
+	BL_SKEW[].CLK = MAIN_CLK;
+	BL_SKEW[] = FB_AD[31..24];
+	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						BL_HRAM0_CS	& BL_HRAM0[15..0]
+					  #	BL_HRAM1_CS	& BL_HRAM1[15..0]
+					  #	BL_HRAM2_CS	& BL_HRAM2[15..0]
+					  #	BL_HRAM3_CS	& BL_HRAM3[15..0]
+					  #	BL_HRAM4_CS	& BL_HRAM4[15..0]
+					  #	BL_HRAM5_CS	& BL_HRAM5[15..0]
+					  #	BL_HRAM6_CS	& BL_HRAM6[15..0]
+					  #	BL_HRAM7_CS	& BL_HRAM7[15..0]
+					  #	BL_HRAM8_CS	& BL_HRAM8[15..0]
+					  #	BL_HRAM9_CS	& BL_HRAM9[15..0]
+					  #	BL_HRAMA_CS	& BL_HRAMA[15..0]
+					  #	BL_HRAMB_CS	& BL_HRAMB[15..0]
+					  #	BL_HRAMC_CS	& BL_HRAMC[15..0]
+					  #	BL_HRAMD_CS	& BL_HRAMD[15..0]
+					  #	BL_HRAME_CS	& BL_HRAME[15..0]
+					  #	BL_HRAMF_CS	& BL_HRAMF[15..0]
+					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
+					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
+					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
+					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
+					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
+					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
+					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
+					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
+					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
+					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
+					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
+					  # BL_X_CNT_CS 	& BL_X_CNT[]
+					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
+					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
+					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
+					  ,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); 				-- FFFF8A00-3F/40
+-----------------------------------------
+--  
+	BL_READ_SRC.CLK = DDRCLK0;
+	BL_READ_DST.CLK = DDRCLK0;
+
+	
+	BLITTER_RUN = VCC;
+	BLITTER_SIG = VCC;
+	BLITTER_WR = VCC;
+-- READY SIGNAL 1 CLOCK SPÄTER
+	BL_DATA_DDR_READY.CLK	= DDRCLK0;
+	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
+-- SRC BUFFER LADEN
+	BL_SKEW_IN[].CLK = DDRCLK0;
+	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
+	BL_SKEW_IN[255..128] = BLITTER_DIN[];
+	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
+-- DST BUFFER LADEN	
+	BL_DST_BUFFER[].CLK = DDRCLK0;
+	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
+	BL_DST_BUFFER[] = BLITTER_DIN[];
+-- SKEW EXTENDET
+	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
+	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
+-- SKEW EXT MUX
+	BL_SKEW_OUT[].CLK = DDRCLK0;
+	BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
+	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
+	
+	COUNT[] = COUNT[] + 16;
+	COUNT[].CLK = BLITTER_DACK0;
+	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
+	BLITTER_ADR[] = (0, COUNT[]) + 400000;
+	
+END;
+
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
new file mode 100644
index 0000000..9b12256
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
@@ -0,0 +1,54 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 208 80)
+	(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 61 31 76)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 16 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
+		(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 208 24)
+		(output)
+		(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
+		(line (pt 208 24)(pt 192 24)(line_width 3))
+	)
+	(drawing
+		(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
+		(line (pt 16 16)(pt 16 64)(line_width 1))
+		(line (pt 192 16)(pt 192 64)(line_width 1))
+		(line (pt 16 16)(pt 192 16)(line_width 1))
+		(line (pt 16 64)(pt 192 64)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp
new file mode 100644
index 0000000..d428d99
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_clshift0
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (255 DOWNTO 0);
+		distance		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (255 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc
new file mode 100644
index 0000000..ccf215e
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_clshift0 
+(
+	data[255..0],
+	distance[6..0]
+)
+
+RETURNS (
+	result[255..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip
new file mode 100644
index 0000000..737f0c0
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf
new file mode 100644
index 0000000..d7d910f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf
@@ -0,0 +1,92 @@
+-- megafunction wizard: %LPM_CLSHIFT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_clshift 
+
+-- ============================================================
+-- File Name: lpm_clshift0.tdf
+-- Megafunction Name(s):
+-- 			lpm_clshift
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_clshift.inc";
+
+
+
+SUBDESIGN lpm_clshift0
+(
+	data[255..0]	 : INPUT;
+	distance[6..0]	 : INPUT;
+	result[255..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_clshift_component : lpm_clshift WITH (
+			LPM_SHIFTTYPE = "LOGICAL",
+			LPM_TYPE = "LPM_CLSHIFT",
+			LPM_WIDTH = 256,
+			LPM_WIDTHDIST = 7
+			);
+
+BEGIN
+
+	result[255..0] = lpm_clshift_component.result[255..0];
+	lpm_clshift_component.distance[6..0] = distance[6..0];
+	lpm_clshift_component.direction = VCC;
+	lpm_clshift_component.data[255..0] = data[255..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
+-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
+-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
+-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
+-- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0]
+-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
+-- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0]
+-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
+-- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0
+-- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0
+-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf b/FPGA_by_Fredi/Video/DDR_CTR.tdf
index d5b5ec2..6c74c7a 100644
--- a/FPGA_by_Fredi/Video/DDR_CTR.tdf
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf
@@ -373,8 +373,8 @@ BEGIN
 			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
 			BA_S[]  = CPU_AC     & CPU_BA[]
 				    # BLITTER_AC & BLITTER_BA[];
-			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
-			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111";			-- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
+			SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111";			-- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
 			DDR_SM = DS_T6W;
 			
 		WHEN DS_T6W =>								 
@@ -384,7 +384,7 @@ BEGIN
 			VWE  = VCC;
 			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
 			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
-			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111";			-- WENN LINE DANN ACTIV 
 			DDR_SM = DS_T7W;
 
 		WHEN DS_T7W =>								 
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
index ead66e8..d5b5ec2 100644
--- a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
@@ -43,7 +43,6 @@ SUBDESIGN DDR_CTR
 	nVCAS : OUTPUT;
 	FB_LE[3..0] : OUTPUT;
 	FB_VDOE[3..0] : OUTPUT;
-	CLEAR_FIFO_CNT : OUTPUT;
 	SR_FIFO_WRE : OUTPUT;
 	SR_DDR_FB : OUTPUT;
 	SR_DDR_WR : OUTPUT;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
index 2c9adcc..6a77969 100644
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -620,7 +620,7 @@ BEGIN
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
 	VERZ[0][0] = DISP_ON;
-	VERZ[1][0] = HSYNC_I[]!=0;
+--	VERZ[1][0] = HSYNC_I[]!=0;
 	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
 				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
 	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
index fda03c9..2c9adcc 100644
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
@@ -650,11 +650,11 @@ BEGIN
 	START_ZEILE.ENA = LAST;
 	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
-	SYNC_PIX  = VHCNT[]==1 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;
-	SYNC_PIX1 = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
 	SYNC_PIX2.CLK = PIXEL_CLK;
-	SYNC_PIX2 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
 	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
 	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
 	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
diff --git a/FPGA_by_Fredi/Video/Video.bdf b/FPGA_by_Fredi/Video/Video.bdf
index 6210cb7..669eb72 100644
--- a/FPGA_by_Fredi/Video/Video.bdf
+++ b/FPGA_by_Fredi/Video/Video.bdf
@@ -6758,124 +6758,6 @@ applicable agreement for further details.
 		(line (pt 22 96)(pt 16 102)(line_width 1))
 	)
 )
-(block
-	(rect 296 2552 568 3000)
-	(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8)))	(text "BLITTER" (rect 5 434 62 449)(font "Arial" ))	(block_io "nRSTO" (input))
-	(block_io "MAIN_CLK" (input))
-	(block_io "FB_ALE" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "VIDEO_RAM_CTR[15..0]" (input))
-	(block_io "BLITTER_ON" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "nFB_CS3" (input))
-	(block_io "DDRCLK0" (input))
-	(block_io "BLITTER_DIN[127..0]" (input))
-	(block_io "BLITTER_DACK[4..0]" (input))
-	(block_io "BLITTER_RUN" (output))
-	(block_io "BLITTER_DOUT[127..0]" (output))
-	(block_io "BLITTER_ADR[31..0]" (output))
-	(block_io "BLITTER_SIG" (output))
-	(block_io "BLITTER_WR" (output))
-	(block_io "BLITTER_TA" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(mapper
-		(pt 272 176)
-		(bidir)
-		)
-	(mapper
-		(pt 272 208)
-		(bidir)
-		)
-	(mapper
-		(pt 272 240)
-		(bidir)
-		)
-	(mapper
-		(pt 272 264)
-		(bidir)
-		)
-	(mapper
-		(pt 272 288)
-		(bidir)
-		)
-	(mapper
-		(pt 0 384)
-		(bidir)
-		)
-	(mapper
-		(pt 272 72)
-		(bidir)
-		)
-	(mapper
-		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 32)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 0 272)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 248)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 360)
-		(bidir)
-		)
-	(mapper
-		(pt 0 328)
-		(bidir)
-		)
-	(mapper
-		(pt 272 424)
-		(bidir)
-		)
-	(mapper
-		(pt 0 408)
-		(bidir)
-		)
-)
 (block
 	(rect 1664 1664 2016 2600)
 	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 211 21)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 200 937)(font "Arial" ))	(block_io "nRSTO" (input))
@@ -7322,6 +7204,129 @@ applicable agreement for further details.
 		(bidir)
 		)
 )
+(block
+	(rect 296 2552 568 3040)
+	(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8)))	(text "BLITTER" (rect 5 474 62 489)(font "Arial" ))	(block_io "nRSTO" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "VIDEO_RAM_CTR[15..0]" (input))
+	(block_io "BLITTER_ON" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "DDRCLK0" (input))
+	(block_io "BLITTER_DIN[127..0]" (input))
+	(block_io "BLITTER_DACK[4..0]" (input))
+	(block_io "SR_BLITTER_DACK" (input))
+	(block_io "BLITTER_RUN" (output))
+	(block_io "BLITTER_DOUT[127..0]" (output))
+	(block_io "BLITTER_ADR[31..0]" (output))
+	(block_io "BLITTER_SIG" (output))
+	(block_io "BLITTER_WR" (output))
+	(block_io "BLITTER_TA" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 272 176)
+		(bidir)
+		)
+	(mapper
+		(pt 272 208)
+		(bidir)
+		)
+	(mapper
+		(pt 272 240)
+		(bidir)
+		)
+	(mapper
+		(pt 272 264)
+		(bidir)
+		)
+	(mapper
+		(pt 272 288)
+		(bidir)
+		)
+	(mapper
+		(pt 0 384)
+		(bidir)
+		)
+	(mapper
+		(pt 272 72)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 360)
+		(bidir)
+		)
+	(mapper
+		(pt 0 328)
+		(bidir)
+		)
+	(mapper
+		(pt 272 424)
+		(bidir)
+		)
+	(mapper
+		(pt 0 408)
+		(bidir)
+		)
+	(mapper
+		(pt 0 440)
+		(bidir)
+		)
+)
 (connector
 	(text "CLUT_ADR0" (rect 2786 1272 2869 1287)(font "Arial" ))
 	(pt 2776 1288)
@@ -8363,34 +8368,12 @@ applicable agreement for further details.
 	(pt 560 2376)
 	(pt 664 2376)
 )
-(connector
-	(text "BLITTER_ON" (rect 226 2920 313 2935)(font "Arial" ))
-	(pt 296 2936)
-	(pt 216 2936)
-)
-(connector
-	(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
-	(pt 568 2728)
-	(pt 648 2728)
-)
 (connector
 	(text "VDVZ[127..0]" (rect 810 2920 892 2935)(font "Arial" ))
 	(pt 800 2936)
 	(pt 888 2936)
 	(bus)
 )
-(connector
-	(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
-	(pt 680 2760)
-	(pt 568 2760)
-	(bus)
-)
-(connector
-	(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
-	(pt 568 2792)
-	(pt 680 2792)
-	(bus)
-)
 (connector
 	(text "BLITTER_SIG" (rect 578 2800 667 2815)(font "Arial" ))
 	(pt 568 2816)
@@ -8457,12 +8440,6 @@ applicable agreement for further details.
 	(pt 192 2584)
 	(pt 296 2584)
 )
-(connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 178 2896 334 2911)(font "Arial" ))
-	(pt 296 2912)
-	(pt 168 2912)
-	(bus)
-)
 (connector
 	(text "FB_AD[31..0]" (rect 578 2608 661 2623)(font "Arial" ))
 	(pt 688 2624)
@@ -8613,23 +8590,6 @@ applicable agreement for further details.
 	(pt 1192 1288)
 	(bus)
 )
-(connector
-	(text "BLITTER_DACK[0]" (rect 802 2952 922 2967)(font "Arial" ))
-	(pt 888 2968)
-	(pt 808 2968)
-)
-(connector
-	(text "BLITTER_DIN[127..0]" (rect 1042 2944 1180 2959)(font "Arial" ))
-	(pt 1144 2960)
-	(pt 1032 2960)
-	(bus)
-)
-(connector
-	(text "BLITTER_DIN[127..0]" (rect 194 2944 332 2959)(font "Arial" ))
-	(pt 296 2960)
-	(pt 184 2960)
-	(bus)
-)
 (connector
 	(text "SR_BLITTER_DACK" (rect 570 2464 703 2479)(font "Arial" ))
 	(pt 664 2480)
@@ -8671,12 +8631,6 @@ applicable agreement for further details.
 	(pt 1168 2192)
 	(bus)
 )
-(connector
-	(text "BLITTER_DACK[4..0]" (rect 202 2864 337 2879)(font "Arial" ))
-	(pt 192 2880)
-	(pt 296 2880)
-	(bus)
-)
 (connector
 	(text "CLK33M" (rect 218 2432 273 2447)(font "Arial" ))
 	(pt 208 2448)
@@ -8971,22 +8925,6 @@ applicable agreement for further details.
 	(pt 1032 2400)
 	(pt 1096 2400)
 )
-(connector
-	(text "SR_BLITTER_DACK" (rect 810 2560 943 2575)(font "Arial" ))
-	(pt 904 2576)
-	(pt 800 2576)
-)
-(connector
-	(text "DDRCLK0" (rect 826 2544 894 2559)(font "Arial" ))
-	(pt 816 2560)
-	(pt 904 2560)
-)
-(connector
-	(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
-	(pt 1048 2576)
-	(pt 1152 2576)
-	(bus)
-)
 (connector
 	(text "DDRCLK2" (rect 1018 2672 1086 2687)(font "Arial" ))
 	(pt 1008 2688)
@@ -10625,6 +10563,78 @@ applicable agreement for further details.
 	(pt 1712 1472)
 	(pt 1632 1472)
 )
+(connector
+	(text "BLITTER_DACK[4..0]" (rect 178 2864 313 2879)(font "Arial" ))
+	(pt 296 2880)
+	(pt 184 2880)
+	(bus)
+)
+(connector
+	(text "VIDEO_RAM_CTR[15..0]" (rect 154 2896 310 2911)(font "Arial" ))
+	(pt 296 2912)
+	(pt 144 2912)
+	(bus)
+)
+(connector
+	(text "BLITTER_ON" (rect 202 2920 289 2935)(font "Arial" ))
+	(pt 296 2936)
+	(pt 192 2936)
+)
+(connector
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diff --git a/FPGA_by_Fredi/Video/altdpram0_wave0.jpg b/FPGA_by_Fredi/Video/altdpram0_wave0.jpg
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diff --git a/FPGA_by_Fredi/altiobuf_bidir0.bsf b/FPGA_by_Fredi/altiobuf_bidir0.bsf
new file mode 100644
index 0000000..c91097e
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 216)
+	(text "altiobuf_bidir0" (rect 65 1 185 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 197 31 212)(font "Arial" ))
+	(port
+		(pt 0 176)
+		(input)
+		(text "datain[0]" (rect 0 0 59 16)(font "Arial" (font_size 8)))
+		(text "datain[0]" (rect 4 160 54 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 100 176)(line_width 3))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "oe[0]" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "oe[0]" (rect 4 128 33 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 105 144)(line_width 3))
+	)
+	(port
+		(pt 232 56)
+		(output)
+		(text "dataout[0]" (rect 0 0 68 16)(font "Arial" (font_size 8)))
+		(text "dataout[0]" (rect 171 40 229 56)(font "Arial" (font_size 8)))
+		(line (pt 232 56)(pt 80 56)(line_width 3))
+	)
+	(port
+		(pt 232 176)
+		(bidir)
+		(text "dataio[0]" (rect 0 0 59 16)(font "Arial" (font_size 8)))
+		(text "dataio[0]" (rect 179 160 229 176)(font "Arial" (font_size 8)))
+		(line (pt 232 176)(pt 131 176)(line_width 3))
+	)
+	(drawing
+		(line (pt 100 160)(pt 100 192)(line_width 1))
+		(line (pt 100 160)(pt 132 176)(line_width 1))
+		(line (pt 100 192)(pt 132 176)(line_width 1))
+		(line (pt 156 176)(pt 156 80)(line_width 3))
+		(line (pt 132 80)(pt 156 80)(line_width 3))
+		(line (pt 105 144)(pt 105 161)(line_width 3))
+		(line (pt 132 64)(pt 132 96)(line_width 1))
+		(line (pt 132 64)(pt 100 80)(line_width 1))
+		(line (pt 132 96)(pt 100 80)(line_width 1))
+		(line (pt 80 56)(pt 80 80)(line_width 3))
+		(line (pt 80 80)(pt 100 80)(line_width 3))
+		(line (pt 0 0)(pt 233 0)(line_width 1))
+		(line (pt 233 0)(pt 233 217)(line_width 1))
+		(line (pt 0 217)(pt 233 217)(line_width 1))
+		(line (pt 0 0)(pt 0 217)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/altiobuf_bidir0.cmp b/FPGA_by_Fredi/altiobuf_bidir0.cmp
new file mode 100644
index 0000000..3731ce8
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0.cmp
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component altiobuf_bidir0
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataio		: INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/altiobuf_bidir0.inc b/FPGA_by_Fredi/altiobuf_bidir0.inc
new file mode 100644
index 0000000..1e7e42f
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altiobuf_bidir0 
+(
+	datain[0..0],
+	oe[0..0]
+)
+
+RETURNS (
+	dataio[0..0],
+	dataout[0..0]
+);
diff --git a/FPGA_by_Fredi/altiobuf_bidir0.qip b/FPGA_by_Fredi/altiobuf_bidir0.qip
new file mode 100644
index 0000000..bfb5ab7
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.cmp"]
diff --git a/FPGA_by_Fredi/altiobuf_bidir0.tdf b/FPGA_by_Fredi/altiobuf_bidir0.tdf
new file mode 100644
index 0000000..f8c0c70
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0.tdf
@@ -0,0 +1,90 @@
+-- megafunction wizard: %ALTIOBUF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altiobuf_bidir 
+
+-- ============================================================
+-- File Name: altiobuf_bidir0.tdf
+-- Megafunction Name(s):
+-- 			altiobuf_bidir
+--
+-- Simulation Library Files(s):
+-- 			cycloneiii
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+-- Clearbox generated function header
+FUNCTION altiobuf_bidir0_iobuf_bidir_quo (datain[0..0], oe[0..0])
+RETURNS ( dataio[0..0], dataout[0..0]);
+
+
+
+
+SUBDESIGN altiobuf_bidir0
+(
+	datain[0..0]	 : INPUT;
+	oe[0..0]	 : INPUT;
+	dataio[0..0]	 : BIDIR;
+	dataout[0..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	altiobuf_bidir0_iobuf_bidir_quo_component : altiobuf_bidir0_iobuf_bidir_quo;
+
+BEGIN
+
+	dataout[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataout[0..0];
+	dataio[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataio[0..0];
+	altiobuf_bidir0_iobuf_bidir_quo_component.datain[0..0] = datain[0..0];
+	altiobuf_bidir0_iobuf_bidir_quo_component.oe[0..0] = oe[0..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
+-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
+-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
+-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
+-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
+-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
+-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
+-- Retrieval info: USED_PORT: dataio 0 0 1 0 BIDIR NODEFVAL "dataio[0..0]"
+-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
+-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
+-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
+-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
+-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: dataio 0 0 1 0 @dataio 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: cycloneiii
diff --git a/FPGA_by_Fredi/altiobuf_bidir0_iobuf_bidir_quo.tdf b/FPGA_by_Fredi/altiobuf_bidir0_iobuf_bidir_quo.tdf
new file mode 100644
index 0000000..92886d3
--- /dev/null
+++ b/FPGA_by_Fredi/altiobuf_bidir0_iobuf_bidir_quo.tdf
@@ -0,0 +1,53 @@
+--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout oe
+--VERSION_BEGIN 9.1SP2 cbx_altiobuf_bidir 2010:03:24:20:43:42:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_io_ibuf (i, ibar)
+WITH ( bus_hold, differential_mode, simulate_z_as)
+RETURNS ( o);
+FUNCTION cycloneiii_io_obuf (i, oe, seriesterminationcontrol[TERM_CTRL_WIDTH-1..0])
+WITH ( bus_hold, open_drain_output, TERM_CTRL_WIDTH = 16)
+RETURNS ( o, obar);
+
+--synthesis_resources = cycloneiii_io_ibuf 1 cycloneiii_io_obuf 1 
+SUBDESIGN altiobuf_bidir0_iobuf_bidir_quo
+( 
+	datain[0..0]	:	input;
+	dataio[0..0]	:	bidir;
+	dataout[0..0]	:	output;
+	oe[0..0]	:	input;
+) 
+VARIABLE 
+	ibufa[0..0] : cycloneiii_io_ibuf
+		WITH (
+			bus_hold = "false"
+		);
+	obufa[0..0] : cycloneiii_io_obuf
+		WITH (
+			bus_hold = "false",
+			open_drain_output = "false"
+		);
+
+BEGIN 
+	ibufa[].i = dataio[];
+	obufa[].i = datain[];
+	obufa[].oe = oe[];
+	dataio[] = obufa[].o;
+	dataout[] = ibufa[].o;
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/altpll1.bsf b/FPGA_by_Fredi/altpll1.bsf
index d1e4a9e..c0cf5ba 100644
--- a/FPGA_by_Fredi/altpll1.bsf
+++ b/FPGA_by_Fredi/altpll1.bsf
@@ -20,81 +20,81 @@ applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 328 216)
-	(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 197 31 212)(font "Arial" ))
+	(rect 0 0 272 184)
+	(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
 	(port
-		(pt 0 72)
+		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64)(line_width 1))
 	)
 	(port
-		(pt 328 72)
+		(pt 272 64)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
-		(line (pt 328 72)(pt 272 72)(line_width 1))
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
+		(line (pt 272 64)(pt 224 64)(line_width 1))
 	)
 	(port
-		(pt 328 96)
+		(pt 272 80)
 		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
-		(line (pt 328 96)(pt 272 96)(line_width 1))
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
+		(line (pt 272 80)(pt 224 80)(line_width 1))
 	)
 	(port
-		(pt 328 120)
+		(pt 272 96)
 		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
-		(line (pt 328 120)(pt 272 120)(line_width 1))
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
+		(line (pt 272 96)(pt 224 96)(line_width 1))
 	)
 	(port
-		(pt 328 144)
+		(pt 272 112)
 		(output)
-		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
-		(line (pt 328 144)(pt 272 144)(line_width 1))
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
+		(line (pt 272 112)(pt 224 112)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
-		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
-		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
-		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
-		(text "1/66" (rect 92 129 113 143)(font "Arial" ))
-		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
-		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
-		(text "67/900" (rect 85 147 118 161)(font "Arial" ))
-		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
-		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
-		(text "67/90" (rect 89 165 116 179)(font "Arial" ))
-		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
-		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
-		(line (pt 0 0)(pt 329 0)(line_width 1))
-		(line (pt 329 0)(pt 329 217)(line_width 1))
-		(line (pt 0 217)(pt 329 217)(line_width 1))
-		(line (pt 0 0)(pt 0 217)(line_width 1))
-		(line (pt 56 108)(pt 215 108)(line_width 1))
-		(line (pt 56 125)(pt 215 125)(line_width 1))
-		(line (pt 56 143)(pt 215 143)(line_width 1))
-		(line (pt 56 161)(pt 215 161)(line_width 1))
-		(line (pt 56 179)(pt 215 179)(line_width 1))
-		(line (pt 56 108)(pt 56 179)(line_width 1))
-		(line (pt 82 108)(pt 82 179)(line_width 3))
-		(line (pt 125 108)(pt 125 179)(line_width 3))
-		(line (pt 170 108)(pt 170 179)(line_width 3))
-		(line (pt 214 108)(pt 214 179)(line_width 1))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
-		(line (pt 272 56)(pt 272 200)(line_width 1))
-		(line (pt 48 200)(pt 272 200)(line_width 1))
-		(line (pt 48 56)(pt 48 200)(line_width 1))
+		(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
+		(text "Clk " (rect 51 96 68 108)(font "Arial" ))
+		(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
+		(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
+		(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
+		(text "c0" (rect 54 111 64 123)(font "Arial" ))
+		(text "16/11" (rect 83 111 106 123)(font "Arial" ))
+		(text "0.00" (rect 127 111 145 123)(font "Arial" ))
+		(text "50.00" (rect 160 111 183 123)(font "Arial" ))
+		(text "c1" (rect 54 126 64 138)(font "Arial" ))
+		(text "16/33" (rect 83 126 106 138)(font "Arial" ))
+		(text "0.00" (rect 127 126 145 138)(font "Arial" ))
+		(text "50.00" (rect 160 126 183 138)(font "Arial" ))
+		(text "c2" (rect 54 141 64 153)(font "Arial" ))
+		(text "1024/1375" (rect 73 141 116 153)(font "Arial" ))
+		(text "0.00" (rect 127 141 145 153)(font "Arial" ))
+		(text "50.00" (rect 160 141 183 153)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0)(line_width 1))
+		(line (pt 273 0)(pt 273 185)(line_width 1))
+		(line (pt 0 185)(pt 273 185)(line_width 1))
+		(line (pt 0 0)(pt 0 185)(line_width 1))
+		(line (pt 48 94)(pt 189 94)(line_width 1))
+		(line (pt 48 108)(pt 189 108)(line_width 1))
+		(line (pt 48 123)(pt 189 123)(line_width 1))
+		(line (pt 48 138)(pt 189 138)(line_width 1))
+		(line (pt 48 153)(pt 189 153)(line_width 1))
+		(line (pt 48 94)(pt 48 153)(line_width 1))
+		(line (pt 70 94)(pt 70 153)(line_width 3))
+		(line (pt 118 94)(pt 118 153)(line_width 3))
+		(line (pt 153 94)(pt 153 153)(line_width 3))
+		(line (pt 188 94)(pt 188 153)(line_width 1))
+		(line (pt 40 48)(pt 224 48)(line_width 1))
+		(line (pt 224 48)(pt 224 168)(line_width 1))
+		(line (pt 40 168)(pt 224 168)(line_width 1))
+		(line (pt 40 48)(pt 40 168)(line_width 1))
 	)
 )
diff --git a/FPGA_by_Fredi/altpll1.vhd b/FPGA_by_Fredi/altpll1.vhd
index ab9bfaf..001d73b 100644
--- a/FPGA_by_Fredi/altpll1.vhd
+++ b/FPGA_by_Fredi/altpll1.vhd
@@ -153,17 +153,17 @@ BEGIN
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
-		clk0_divide_by => 66,
+		clk0_divide_by => 11,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 1,
+		clk0_multiply_by => 16,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 900,
+		clk1_divide_by => 33,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 67,
+		clk1_multiply_by => 16,
 		clk1_phase_shift => "0",
-		clk2_divide_by => 90,
+		clk2_divide_by => 1375,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 67,
+		clk2_multiply_by => 1024,
 		clk2_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 30303,
@@ -244,15 +244,15 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
 -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -272,23 +272,23 @@ END SYN;
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
 -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -298,7 +298,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -338,17 +338,17 @@ END SYN;
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
diff --git a/FPGA_by_Fredi/altpll3.bsf b/FPGA_by_Fredi/altpll3.bsf
index da30b0c..1a61457 100644
--- a/FPGA_by_Fredi/altpll3.bsf
+++ b/FPGA_by_Fredi/altpll3.bsf
@@ -20,86 +20,93 @@ applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 304 232)
-	(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(rect 0 0 272 200)
+	(text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 184 25 196)(font "Arial" ))
 	(port
-		(pt 0 72)
+		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 48 72)(line_width 1))
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64)(line_width 1))
 	)
 	(port
-		(pt 304 72)
+		(pt 272 64)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
-		(line (pt 304 72)(pt 272 72)(line_width 1))
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
+		(line (pt 272 64)(pt 224 64)(line_width 1))
 	)
 	(port
-		(pt 304 96)
+		(pt 272 80)
 		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
-		(line (pt 304 96)(pt 272 96)(line_width 1))
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
+		(line (pt 272 80)(pt 224 80)(line_width 1))
 	)
 	(port
-		(pt 304 120)
+		(pt 272 96)
 		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
-		(line (pt 304 120)(pt 272 120)(line_width 1))
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
+		(line (pt 272 96)(pt 224 96)(line_width 1))
 	)
 	(port
-		(pt 304 144)
+		(pt 272 112)
 		(output)
-		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
-		(line (pt 304 144)(pt 272 144)(line_width 1))
+		(text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c3" (rect 257 99 268 112)(font "Arial" (font_size 8)))
+		(line (pt 272 112)(pt 224 112)(line_width 1))
+	)
+	(port
+		(pt 272 128)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 238 115 268 128)(font "Arial" (font_size 8)))
+		(line (pt 272 128)(pt 224 128)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
-		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
-		(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
-		(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
-		(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
-		(text "c0" (rect 63 129 75 143)(font "Arial" ))
-		(text "2/33" (rect 88 129 109 143)(font "Arial" ))
-		(text "0.00" (rect 129 129 150 143)(font "Arial" ))
-		(text "50.00" (rect 171 129 198 143)(font "Arial" ))
-		(text "c1" (rect 63 147 75 161)(font "Arial" ))
-		(text "16/33" (rect 85 147 112 161)(font "Arial" ))
-		(text "0.00" (rect 129 147 150 161)(font "Arial" ))
-		(text "50.00" (rect 171 147 198 161)(font "Arial" ))
-		(text "c2" (rect 63 165 75 179)(font "Arial" ))
-		(text "25/33" (rect 85 165 112 179)(font "Arial" ))
-		(text "0.00" (rect 129 165 150 179)(font "Arial" ))
-		(text "50.00" (rect 171 165 198 179)(font "Arial" ))
-		(text "c3" (rect 63 183 75 197)(font "Arial" ))
-		(text "16/11" (rect 85 183 112 197)(font "Arial" ))
-		(text "0.00" (rect 129 183 150 197)(font "Arial" ))
-		(text "50.00" (rect 171 183 198 197)(font "Arial" ))
-		(line (pt 0 0)(pt 305 0)(line_width 1))
-		(line (pt 305 0)(pt 305 233)(line_width 1))
-		(line (pt 0 233)(pt 305 233)(line_width 1))
-		(line (pt 0 0)(pt 0 233)(line_width 1))
-		(line (pt 56 108)(pt 208 108)(line_width 1))
-		(line (pt 56 125)(pt 208 125)(line_width 1))
-		(line (pt 56 143)(pt 208 143)(line_width 1))
-		(line (pt 56 161)(pt 208 161)(line_width 1))
-		(line (pt 56 179)(pt 208 179)(line_width 1))
-		(line (pt 56 197)(pt 208 197)(line_width 1))
-		(line (pt 56 108)(pt 56 197)(line_width 1))
-		(line (pt 82 108)(pt 82 197)(line_width 3))
-		(line (pt 118 108)(pt 118 197)(line_width 3))
-		(line (pt 163 108)(pt 163 197)(line_width 3))
-		(line (pt 207 108)(pt 207 197)(line_width 1))
-		(line (pt 48 56)(pt 272 56)(line_width 1))
-		(line (pt 272 56)(pt 272 216)(line_width 1))
-		(line (pt 48 216)(pt 272 216)(line_width 1))
-		(line (pt 48 56)(pt 48 216)(line_width 1))
+		(text "Cyclone III" (rect 211 185 258 197)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
+		(text "Clk " (rect 51 96 68 108)(font "Arial" ))
+		(text "Ratio" (rect 81 96 103 108)(font "Arial" ))
+		(text "Ph (dg)" (rect 116 96 146 108)(font "Arial" ))
+		(text "DC (%)" (rect 151 96 182 108)(font "Arial" ))
+		(text "c0" (rect 54 111 64 123)(font "Arial" ))
+		(text "25/33" (rect 81 111 104 123)(font "Arial" ))
+		(text "0.00" (rect 122 111 140 123)(font "Arial" ))
+		(text "50.00" (rect 155 111 178 123)(font "Arial" ))
+		(text "c1" (rect 54 126 64 138)(font "Arial" ))
+		(text "2/33" (rect 83 126 101 138)(font "Arial" ))
+		(text "0.00" (rect 122 126 140 138)(font "Arial" ))
+		(text "50.00" (rect 155 126 178 138)(font "Arial" ))
+		(text "c2" (rect 54 141 64 153)(font "Arial" ))
+		(text "1/66" (rect 83 141 101 153)(font "Arial" ))
+		(text "0.00" (rect 122 141 140 153)(font "Arial" ))
+		(text "50.00" (rect 155 141 178 153)(font "Arial" ))
+		(text "c3" (rect 54 156 64 168)(font "Arial" ))
+		(text "512/6875" (rect 73 156 111 168)(font "Arial" ))
+		(text "0.00" (rect 122 156 140 168)(font "Arial" ))
+		(text "50.00" (rect 155 156 178 168)(font "Arial" ))
+		(line (pt 0 0)(pt 273 0)(line_width 1))
+		(line (pt 273 0)(pt 273 201)(line_width 1))
+		(line (pt 0 201)(pt 273 201)(line_width 1))
+		(line (pt 0 0)(pt 0 201)(line_width 1))
+		(line (pt 48 94)(pt 184 94)(line_width 1))
+		(line (pt 48 108)(pt 184 108)(line_width 1))
+		(line (pt 48 123)(pt 184 123)(line_width 1))
+		(line (pt 48 138)(pt 184 138)(line_width 1))
+		(line (pt 48 153)(pt 184 153)(line_width 1))
+		(line (pt 48 168)(pt 184 168)(line_width 1))
+		(line (pt 48 94)(pt 48 168)(line_width 1))
+		(line (pt 70 94)(pt 70 168)(line_width 3))
+		(line (pt 113 94)(pt 113 168)(line_width 3))
+		(line (pt 148 94)(pt 148 168)(line_width 3))
+		(line (pt 183 94)(pt 183 168)(line_width 1))
+		(line (pt 40 48)(pt 224 48)(line_width 1))
+		(line (pt 224 48)(pt 224 184)(line_width 1))
+		(line (pt 40 184)(pt 224 184)(line_width 1))
+		(line (pt 40 48)(pt 40 184)(line_width 1))
 	)
 )
diff --git a/FPGA_by_Fredi/altpll3.cmp b/FPGA_by_Fredi/altpll3.cmp
index 44b3f2e..5d2ea75 100644
--- a/FPGA_by_Fredi/altpll3.cmp
+++ b/FPGA_by_Fredi/altpll3.cmp
@@ -20,6 +20,7 @@ component altpll3
 		c0		: OUT STD_LOGIC ;
 		c1		: OUT STD_LOGIC ;
 		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
 	);
 end component;
diff --git a/FPGA_by_Fredi/altpll3.inc b/FPGA_by_Fredi/altpll3.inc
index 160ecad..dd262c4 100644
--- a/FPGA_by_Fredi/altpll3.inc
+++ b/FPGA_by_Fredi/altpll3.inc
@@ -22,5 +22,6 @@ RETURNS (
 	c0,
 	c1,
 	c2,
-	c3
+	c3,
+	locked
 );
diff --git a/FPGA_by_Fredi/altpll3.ppf b/FPGA_by_Fredi/altpll3.ppf
index 2a7b695..1928434 100644
--- a/FPGA_by_Fredi/altpll3.ppf
+++ b/FPGA_by_Fredi/altpll3.ppf
@@ -7,6 +7,7 @@
 <pin name="c1" direction="output" scope="external" source="clock"  />
 <pin name="c2" direction="output" scope="external" source="clock"  />
 <pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
 
 </global>
 </pinplan>
diff --git a/FPGA_by_Fredi/altpll3.vhd b/FPGA_by_Fredi/altpll3.vhd
index 6ead1f5..48ecaf5 100644
--- a/FPGA_by_Fredi/altpll3.vhd
+++ b/FPGA_by_Fredi/altpll3.vhd
@@ -46,7 +46,8 @@ ENTITY altpll3 IS
 		c0		: OUT STD_LOGIC ;
 		c1		: OUT STD_LOGIC ;
 		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
 	);
 END altpll3;
 
@@ -59,9 +60,10 @@ ARCHITECTURE SYN OF altpll3 IS
 	SIGNAL sub_wire3	: STD_LOGIC ;
 	SIGNAL sub_wire4	: STD_LOGIC ;
 	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -131,17 +133,19 @@ ARCHITECTURE SYN OF altpll3 IS
 		port_extclk1		: STRING;
 		port_extclk2		: STRING;
 		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
 		width_clock		: NATURAL
 	);
 	PORT (
 			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC ;
 			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
 	);
 	END COMPONENT;
 
 BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
 	sub_wire4    <= sub_wire0(3);
 	sub_wire3    <= sub_wire0(2);
 	sub_wire2    <= sub_wire0(1);
@@ -150,29 +154,30 @@ BEGIN
 	c1    <= sub_wire2;
 	c2    <= sub_wire3;
 	c3    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+	locked    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 33,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 2,
+		clk0_multiply_by => 25,
 		clk0_phase_shift => "0",
 		clk1_divide_by => 33,
 		clk1_duty_cycle => 50,
-		clk1_multiply_by => 16,
+		clk1_multiply_by => 2,
 		clk1_phase_shift => "0",
-		clk2_divide_by => 33,
+		clk2_divide_by => 66,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 25,
+		clk2_multiply_by => 1,
 		clk2_phase_shift => "0",
-		clk3_divide_by => 11,
+		clk3_divide_by => 6875,
 		clk3_duty_cycle => 50,
-		clk3_multiply_by => 16,
+		clk3_multiply_by => 512,
 		clk3_phase_shift => "0",
-		compensate_clock => "CLK1",
+		compensate_clock => "CLK0",
 		inclk0_input_frequency => 30303,
 		intended_device_family => "Cyclone III",
 		lpm_type => "altpll",
@@ -188,7 +193,7 @@ BEGIN
 		port_fbin => "PORT_UNUSED",
 		port_inclk0 => "PORT_USED",
 		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
+		port_locked => "PORT_USED",
 		port_pfdena => "PORT_UNUSED",
 		port_phasecounterselect => "PORT_UNUSED",
 		port_phasedone => "PORT_UNUSED",
@@ -219,11 +224,13 @@ BEGIN
 		port_extclk1 => "PORT_UNUSED",
 		port_extclk2 => "PORT_UNUSED",
 		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire6,
-		clk => sub_wire0
+		inclk => sub_wire7,
+		clk => sub_wire0,
+		locked => sub_wire5
 	);
 
 
@@ -246,21 +253,21 @@ END SYN;
 -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
 -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
 -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "72"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "906"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3072"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "738"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -276,7 +283,7 @@ END SYN;
 -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
@@ -289,19 +296,19 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -316,7 +323,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -359,21 +366,21 @@ END SYN;
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "66"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6875"
 -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512"
 -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -389,7 +396,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
 -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
@@ -420,6 +427,7 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
 -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
@@ -428,6 +436,8 @@ END SYN;
 -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
diff --git a/FPGA_by_Fredi/firebee1.asm.rpt b/FPGA_by_Fredi/firebee1.asm.rpt
deleted file mode 100644
index 7ffb13e..0000000
--- a/FPGA_by_Fredi/firebee1.asm.rpt
+++ /dev/null
@@ -1,128 +0,0 @@
-Assembler report for firebee1
-Wed Dec 15 02:25:13 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
-  6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
-  7. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Dec 15 02:25:13 2010 ;
-; Revision Name         ; firebee1                              ;
-; Top-level Entity Name ; firebee1                              ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C40F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                       ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Option                                                                      ; Setting    ; Default Value ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Generate Raw Binary File (.rbf) For Target Device                           ; On         ; Off           ;
-; Hexadecimal Output File start address                                       ; 0XE0700000 ; 0             ;
-; Use smart compilation                                                       ; Off        ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On         ; On            ;
-; Enable compact report table                                                 ; Off        ; Off           ;
-; Generate compressed bitstreams                                              ; On         ; On            ;
-; Compression mode                                                            ; Off        ; Off           ;
-; Clock source for configuration device                                       ; Internal   ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ     ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1          ; 1             ;
-; Auto user code                                                              ; Off        ; Off           ;
-; Use configuration device                                                    ; Off        ; Off           ;
-; Configuration device                                                        ; Auto       ; Auto          ;
-; Configuration device auto user code                                         ; Off        ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off        ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off        ; Off           ;
-; Hexadecimal Output File count direction                                     ; Up         ; Up            ;
-; Release clears before tri-states                                            ; Off        ; Off           ;
-; Auto-restart configuration after error                                      ; On         ; On            ;
-; Enable OCT_DONE                                                             ; Off        ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off        ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On         ; On            ;
-+-----------------------------------------------------------------------------+------------+---------------+
-
-
-+------------------------------+
-; Assembler Generated Files    ;
-+------------------------------+
-; File Name                    ;
-+------------------------------+
-; C:/FireBee/FPGA/firebee1.sof ;
-; C:/FireBee/FPGA/firebee1.rbf ;
-+------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
-+----------------+---------------------------------------+
-; Option         ; Setting                               ;
-+----------------+---------------------------------------+
-; Device         ; EP3C40F484C6                          ;
-; JTAG usercode  ; 0xFFFFFFFF                            ;
-; Checksum       ; 0x0085E8C6                            ;
-+----------------+---------------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
-+---------------------+----------------------------------+
-; Option              ; Setting                          ;
-+---------------------+----------------------------------+
-; Raw Binary File     ;                                  ;
-;  Compression Ratio  ; 2                                ;
-+---------------------+----------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II Assembler
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Wed Dec 15 02:25:08 2010
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-Info: Writing out detailed assembly data for power analysis
-Info: Assembler is generating device programming files
-Info: Quartus II Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 291 megabytes
-    Info: Processing ended: Wed Dec 15 02:25:13 2010
-    Info: Elapsed time: 00:00:05
-    Info: Total CPU time (on all processors): 00:00:05
-
-
diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
index 46507a2..8d4f188 100644
--- a/FPGA_by_Fredi/firebee1.bdf
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -26,8 +26,8 @@ applicable agreement for further details.
 (pin
 	(input)
 	(rect 208 1392 376 1408)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_ALE" (rect 9 0 60 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_ALE" (rect 9 0 49 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -37,14 +37,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 136 1408 192 1424))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 160 1408 208 1424))
 )
 (pin
 	(input)
 	(rect 992 936 1160 952)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_WR" (rect 9 0 66 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_WR" (rect 9 0 53 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -54,31 +54,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 952 1000 968))
-)
-(pin
-	(input)
-	(rect 168 296 336 312)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "CLK33M" (rect 9 0 64 15)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 92 12)(pt 117 12)(line_width 1))
-		(line (pt 92 4)(pt 117 4)(line_width 1))
-		(line (pt 121 8)(pt 168 8)(line_width 1))
-		(line (pt 92 12)(pt 92 4)(line_width 1))
-		(line (pt 117 4)(pt 121 8)(line_width 1))
-		(line (pt 117 12)(pt 121 8)(line_width 1))
-	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 104 312 176 328))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 952 992 968))
 )
 (pin
 	(input)
 	(rect 992 960 1160 976)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS1" (rect 5 0 67 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -88,14 +71,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 976 1000 992))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 976 992 992))
 )
 (pin
 	(input)
 	(rect 992 984 1160 1000)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS2" (rect 5 0 67 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS2" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -105,14 +88,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1000 1000 1016))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1000 992 1016))
 )
 (pin
 	(input)
 	(rect 1008 360 1176 376)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS3" (rect 5 0 67 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS3" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -122,14 +105,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 952 376 1008 392))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 960 376 1008 392))
 )
 (pin
 	(input)
 	(rect 992 1008 1160 1024)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_SIZE0" (rect 5 0 69 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE0" (rect 9 0 59 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -139,14 +122,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1024 1000 1040))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1024 992 1040))
 )
 (pin
 	(input)
 	(rect 992 1032 1160 1048)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_SIZE1" (rect 5 0 69 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE1" (rect 9 0 59 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -156,14 +139,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1048 1000 1064))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1048 992 1064))
 )
 (pin
 	(input)
 	(rect 992 1056 1160 1072)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_BURST" (rect 5 0 87 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_BURST" (rect 9 0 71 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -173,14 +156,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 1072 1000 1088))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 1072 992 1088))
 )
 (pin
 	(input)
 	(rect 936 1168 1104 1184)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "LP_BUSY" (rect 5 0 68 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "LP_BUSY" (rect 9 0 58 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -190,14 +173,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1184 952 1200))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1184 936 1200))
 )
 (pin
 	(input)
 	(rect 856 1200 1024 1216)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nACSI_DRQ" (rect 5 0 85 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nACSI_DRQ" (rect 9 0 71 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -207,14 +190,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 808 1216 864 1232))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 808 1216 856 1232))
 )
 (pin
 	(input)
 	(rect 856 1224 1024 1240)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nACSI_INT" (rect 5 0 75 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nACSI_INT" (rect 9 0 64 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -224,14 +207,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 808 1240 864 1256))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 808 1240 856 1256))
 )
 (pin
 	(input)
 	(rect 936 1392 1104 1408)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "RxD" (rect 5 0 32 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "RxD" (rect 9 0 31 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -241,14 +224,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1408 944 1424))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1408 936 1424))
 )
 (pin
 	(input)
 	(rect 936 1416 1104 1432)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "CTS" (rect 5 0 33 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CTS" (rect 9 0 30 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -258,14 +241,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1432 944 1448))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1432 936 1448))
 )
 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "RI" (rect 5 0 19 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "RI" (rect 9 0 20 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -275,14 +258,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1456 944 1472))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1456 936 1472))
 )
 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "DCD" (rect 5 0 36 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "DCD" (rect 9 0 33 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -292,14 +275,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1480 944 1496))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1480 936 1496))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "AMKB_RX" (rect 5 0 69 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "AMKB_RX" (rect 9 0 58 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -309,14 +292,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 560 1504 616 1520))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 560 1504 648 1536))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "PIC_AMKB_RX" (rect 5 0 101 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "PIC_AMKB_RX" (rect 9 0 83 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -326,14 +309,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 560 1528 616 1544))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 560 1528 608 1544))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "IDE_RDY" (rect 5 0 66 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "IDE_RDY" (rect 9 0 58 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -343,14 +326,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1560 944 1576))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1560 936 1576))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "IDE_INT" (rect 5 0 59 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "IDE_INT" (rect 9 0 51 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -360,14 +343,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1584 944 1600))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1584 936 1600))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "WP_CF_CARD" (rect 5 0 102 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "WP_CF_CARD" (rect 9 0 85 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -377,14 +360,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1608 944 1624))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1608 936 1624))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "TRACK00" (rect 5 0 68 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "TRACK00" (rect 9 0 57 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -394,14 +377,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 816 1688 880 1704))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 816 1688 872 1704))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nWP" (rect 5 0 35 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nWP" (rect 9 0 32 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -411,14 +394,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 816 1712 880 1728))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 816 1712 872 1728))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nDCHG" (rect 5 0 55 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nDCHG" (rect 9 0 47 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 92 12)(pt 117 12)(line_width 1))
@@ -428,14 +411,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 816 1760 880 1776))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 816 1760 872 1776))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "SD_DATA0" (rect 5 0 76 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "SD_DATA0" (rect 9 0 64 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -445,14 +428,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1792 944 1808))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1792 936 1808))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "SD_DATA1" (rect 5 0 76 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "SD_DATA1" (rect 9 0 64 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -462,14 +445,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1816 944 1832))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1816 936 1832))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "SD_DATA2" (rect 5 0 76 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "SD_DATA2" (rect 9 0 64 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -479,31 +462,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1840 944 1856))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1840 936 1856))
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 (pin
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-	(text "SD_CARD_DEDECT" (rect 5 0 140 15)(font "Arial" ))
-	(pt 192 8)
-	(drawing
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-		(line (pt 116 4)(pt 141 4)(line_width 1))
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-		(line (pt 141 4)(pt 145 8)(line_width 1))
-		(line (pt 141 12)(pt 145 8)(line_width 1))
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-	(text "VCC" (rect 160 7 184 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1864 952 1880))
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-(pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "MIDI_IN" (rect 5 0 55 15)(font "Arial" ))
+	(rect 936 1848 1104 1864)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "SD_CARD_DEDECT" (rect 9 0 112 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -513,14 +479,14 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 816 1376 880 1392))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1864 936 1880))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_DRQ" (rect 5 0 86 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_DRQ" (rect 9 0 71 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -530,14 +496,14 @@ applicable agreement for further details.
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 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1272 944 1288))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1272 936 1288))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "SD_WP" (rect 5 0 55 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "SD_WP" (rect 9 0 47 12)(font "Arial" ))
 	(pt 168 8)
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@@ -547,14 +513,14 @@ applicable agreement for further details.
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 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 880 1888 952 1904))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 880 1888 936 1904))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nRD_DATA" (rect 5 0 78 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nRD_DATA" (rect 9 0 65 12)(font "Arial" ))
 	(pt 168 8)
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@@ -564,14 +530,14 @@ applicable agreement for further details.
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 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 816 1736 880 1752))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 816 1736 872 1752))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_C_D" (rect 5 0 84 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_C_D" (rect 9 0 69 12)(font "Arial" ))
 	(pt 168 8)
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@@ -581,14 +547,14 @@ applicable agreement for further details.
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 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1296 944 1312))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1296 936 1312))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_I_O" (rect 5 0 76 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_I_O" (rect 9 0 64 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
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@@ -598,14 +564,14 @@ applicable agreement for further details.
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 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1320 944 1336))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1320 936 1336))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_MSG" (rect 5 0 85 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_MSG" (rect 9 0 70 12)(font "Arial" ))
 	(pt 168 8)
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@@ -615,14 +581,14 @@ applicable agreement for further details.
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-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 888 1344 944 1360))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 888 1344 936 1360))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nDACK0" (rect 5 0 60 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nDACK0" (rect 9 0 51 12)(font "Arial" ))
 	(pt 168 8)
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@@ -632,14 +598,14 @@ applicable agreement for further details.
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-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 936 1120 1000 1136))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 936 1120 992 1136))
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 (pin
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "PIC_INT" (rect 5 0 59 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "PIC_INT" (rect 9 0 51 12)(font "Arial" ))
 	(pt 168 8)
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@@ -649,14 +615,14 @@ applicable agreement for further details.
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-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 928 2608 1000 2624))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 928 2608 984 2624))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_OE" (rect 5 0 59 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_OE" (rect 9 0 50 12)(font "Arial" ))
 	(pt 168 8)
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@@ -666,14 +632,14 @@ applicable agreement for further details.
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-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 944 928 1000 944))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 928 992 944))
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-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
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+	(text "TOUT0" (rect 9 0 43 12)(font "Arial" ))
 	(pt 168 8)
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@@ -683,14 +649,14 @@ applicable agreement for further details.
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+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 992 272 1056 288))
 )
 (pin
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 	(rect 1840 1088 2016 1104)
-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "SCSI_PAR" (rect 90 0 159 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "SCSI_PAR" (rect 90 0 144 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2095,14 +2078,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2016 1104 2080 1120))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2016 1104 2064 1120))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_RST" (rect 90 0 167 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_RST" (rect 90 0 149 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2113,14 +2096,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2016 1200 2072 1216))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2016 1200 2064 1216))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_SEL" (rect 90 0 166 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_SEL" (rect 90 0 147 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2131,14 +2114,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2016 1224 2080 1240))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2016 1224 2064 1240))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "nSCSI_BUSY" (rect 90 0 177 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "nSCSI_BUSY" (rect 90 0 158 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2149,14 +2132,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2016 1248 2072 1264))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2016 1248 2064 1264))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "SD_CD_DATA3" (rect 90 0 191 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "SD_CD_DATA3" (rect 90 0 167 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2167,14 +2150,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2032 2008 2096 2024))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2032 2008 2088 2024))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "SD_CMD_D1" (rect 90 0 177 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "SD_CMD_D1" (rect 90 0 156 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
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 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2032 2032 2096 2048))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2032 2032 2088 2048))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "SCSI_D[7..0]" (rect 90 0 172 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "SCSI_D[7..0]" (rect 90 0 156 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2203,14 +2186,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2112 1080 2176 1208))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2112 1080 2160 1192))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "ACSI_D[7..0]" (rect 90 0 171 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "ACSI_D[7..0]" (rect 90 0 156 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2221,14 +2204,14 @@ applicable agreement for further details.
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 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2080 904 2144 1032))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2080 904 2128 1016))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "LP_D[7..0]" (rect 90 0 157 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "LP_D[7..0]" (rect 90 0 143 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2239,14 +2222,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2136 824 2200 952))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2136 824 2224 952))
 )
 (pin
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-	(text "BIDIR" (rect 151 0 182 13)(font "Arial" (font_size 6)))
-	(text "FB_AD[31..0]" (rect 5 0 88 15)(font "Arial" ))
+	(text "BIDIR" (rect 151 0 175 10)(font "Arial" (font_size 6)))
+	(text "FB_AD[31..0]" (rect 19 0 86 12)(font "Arial" ))
 	(pt 176 8)
 	(drawing
 		(line (pt 120 4)(pt 98 4)(line_width 1))
@@ -2258,14 +2241,14 @@ applicable agreement for further details.
 		(line (pt 124 8)(pt 120 12)(line_width 1))
 	)
 	(flipy)
-	(text "VCC" (rect 152 7 176 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 96 840 168 1352))
+	(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 352 1376 416 1824))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "IO[17..0]" (rect 90 0 143 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "IO[17..0]" (rect 90 0 133 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2276,14 +2259,14 @@ applicable agreement for further details.
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 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2280 3248 2344 3536))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2280 3248 2368 3632))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "SRD[15..0]" (rect 90 0 159 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "SRD[15..0]" (rect 90 0 145 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2294,14 +2277,14 @@ applicable agreement for further details.
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 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2120 3272 2184 3528))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2120 3272 2208 3512))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "VDQS[3..0]" (rect 90 0 159 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "VDQS[3..0]" (rect 90 0 146 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2312,14 +2295,14 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2216 552 2288 632))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2216 552 2280 624))
 )
 (pin
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-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "VD[31..0]" (rect 90 0 147 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "VD[31..0]" (rect 90 0 137 12)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 56 4)(pt 78 4)(line_width 1))
@@ -2330,29 +2313,89 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2824 312 2896 840))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2824 312 2888 776))
+)
+(pin
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+	(rect 1960 2200 2136 2216)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "MIDI_IN_PIN" (rect 90 0 156 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4)(line_width 1))
+		(line (pt 0 8)(pt 52 8)(line_width 1))
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+		(line (pt 56 4)(pt 52 8)(line_width 1))
+		(line (pt 52 8)(pt 56 12)(line_width 1))
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+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 2136 2216 2192 2232))
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 (symbol
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-	(text "lpm_counter0" (rect 33 1 148 20)(font "Arial" (font_size 10)))
-	(text "inst18" (rect 8 48 48 63)(font "Arial" ))
+	(rect 464 1336 608 1432)
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst1" (rect 8 80 31 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 62 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
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+	(port
+		(pt 0 48)
+		(input)
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+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
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+	(port
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+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
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+	(port
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+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 131 64)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
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+	(drawing
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+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
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+		(line (pt 22 48)(pt 16 54)(line_width 1))
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+(symbol
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+	(text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10)))
+	(text "inst18" (rect 8 48 37 60)(font "Arial" ))
+	(port
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+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 55 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
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 	(port
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 		(output)
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-		(text "q[17..0]" (rect 89 34 140 50)(font "Arial" (font_size 8)))
+		(text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[17..0]" (rect 89 34 131 48)(font "Arial" (font_size 8)))
 		(line (pt 144 40)(pt 128 40)(line_width 3))
 	)
 	(drawing
-		(text "up counter" (rect 84 17 152 32)(font "Arial" ))
+		(text "up counter" (rect 84 17 135 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 48)(line_width 1))
 		(line (pt 128 48)(pt 16 48)(line_width 1))
@@ -2363,20 +2406,20 @@ applicable agreement for further details.
 )
 (symbol
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-	(text "WIRE" (rect 1 0 31 13)(font "Arial" (font_size 6)))
-	(text "inst3" (rect 3 21 34 36)(font "Arial" ))
+	(text "WIRE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
+	(text "inst3" (rect 3 21 26 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
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 	(port
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 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 32 16)(pt 48 16)(line_width 1))
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 	(drawing
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 		(line (pt 14 25)(pt 32 16)(line_width 1))
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 )
-(symbol
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-	(text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst1" (rect 8 80 39 95)(font "Arial" ))
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-	(text "inst2" (rect 3 69 34 84)(font "Arial" ))
+	(text "NOR4" (rect 1 0 26 10)(font "Arial" (font_size 6)))
+	(text "inst2" (rect 3 69 26 81)(font "Arial" ))
 	(port
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-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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-		(text "IN3" (rect 2 39 26 55)(font "Courier New" (bold))(invisible))
-		(text "IN3" (rect 2 39 26 55)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 39 19 51)(font "Courier New" (bold))(invisible))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "IN4" (rect 2 55 26 71)(font "Courier New" (bold))(invisible))
-		(text "IN4" (rect 2 55 26 71)(font "Courier New" (bold))(invisible))
+		(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
+		(text "IN4" (rect 2 55 19 67)(font "Courier New" (bold))(invisible))
 		(line (pt 0 64)(pt 14 64)(line_width 1))
 	)
 	(port
 		(pt 64 40)
 		(output)
-		(text "OUT" (rect 48 31 72 47)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 31 72 47)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 31 65 43)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 31 65 43)(font "Courier New" (bold))(invisible))
 		(line (pt 56 40)(pt 64 40)(line_width 1))
 	)
 	(drawing
@@ -2479,20 +2480,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 872 2680 904)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst4" (rect 3 21 34 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst4" (rect 3 21 26 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2504,41 +2505,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1896 -88 2128 32)
-	(text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst5" (rect 8 104 39 119)(font "Arial" ))
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst5" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 52 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 47 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8)))
-		(text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 235 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 1))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "low" (rect 92 84 114 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "low" (rect 92 84 107 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -2547,41 +2548,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2464 -104 2696 16)
-	(text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst6" (rect 8 104 39 119)(font "Arial" ))
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst6" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 52 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 47 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8)))
-		(text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 235 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 1))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "low" (rect 92 84 114 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "low" (rect 92 84 107 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -2590,41 +2591,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2464 16 2696 136)
-	(text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst8" (rect 8 104 39 119)(font "Arial" ))
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst8" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 52 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 47 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8)))
-		(text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 235 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 1))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "low" (rect 92 84 114 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "low" (rect 92 84 107 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -2633,41 +2634,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2464 144 2696 264)
-	(text "altddio_out3" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst9" (rect 8 104 39 119)(font "Arial" ))
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst9" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "datain_h" (rect 4 11 61 27)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 52 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "datain_l" (rect 4 27 57 43)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 47 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout" (rect 0 0 50 16)(font "Arial" (font_size 8)))
-		(text "dataout" (rect 193 11 243 27)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 235 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 1))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "low" (rect 92 84 114 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "low" (rect 92 84 107 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -2676,13 +2677,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2368 120 2400 152)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst10" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst10" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2694,13 +2695,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2408 144 2424 176)
-	(text "VCC" (rect 0 7 13 31)(font "Arial" (font_size 6))(vertical))
-	(text "inst11" (rect 5 3 20 43)(font "Arial" )(vertical)(invisible))
+	(text "VCC" (rect 0 7 10 27)(font "Arial" (font_size 6))(vertical))
+	(text "inst11" (rect 5 3 17 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 16 16)
 		(output)
-		(text "1" (rect 19 7 27 23)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 7 19 23 27)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 7 19 19 24)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 16 16)(pt 8 16)(line_width 1))
 	)
 	(drawing
@@ -2710,20 +2711,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1800 1728 1848 1760)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst14" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst14" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2735,20 +2736,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1856 1752 1904 1784)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst15" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst15" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2760,20 +2761,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1800 1776 1848 1808)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst16" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst16" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2785,20 +2786,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1856 1800 1904 1832)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst17" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst17" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2810,20 +2811,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1800 1824 1848 1856)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst19" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst19" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2835,78 +2836,78 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 448 -352 752 -104)
-	(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
-	(text "inst12" (rect 8 229 48 244)(font "Arial" ))
+	(text "altpll2" (rect 132 1 172 17)(font "Arial" (font_size 10)))
+	(text "inst12" (rect 8 229 37 241)(font "Arial" ))
 	(port
 		(pt 0 72)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 35 70)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 48 72)(line_width 1))
 	)
 	(port
 		(pt 304 72)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 287 56 303 72)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 287 56 301 70)(font "Arial" (font_size 8)))
 		(line (pt 304 72)(pt 272 72)(line_width 1))
 	)
 	(port
 		(pt 304 96)
 		(output)
-		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c1" (rect 287 80 303 96)(font "Arial" (font_size 8)))
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 287 80 301 94)(font "Arial" (font_size 8)))
 		(line (pt 304 96)(pt 272 96)(line_width 1))
 	)
 	(port
 		(pt 304 120)
 		(output)
-		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c2" (rect 287 104 303 120)(font "Arial" (font_size 8)))
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 287 104 301 118)(font "Arial" (font_size 8)))
 		(line (pt 304 120)(pt 272 120)(line_width 1))
 	)
 	(port
 		(pt 304 144)
 		(output)
-		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c3" (rect 287 128 303 144)(font "Arial" (font_size 8)))
+		(text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c3" (rect 287 128 301 142)(font "Arial" (font_size 8)))
 		(line (pt 304 144)(pt 272 144)(line_width 1))
 	)
 	(port
 		(pt 304 168)
 		(output)
-		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c4" (rect 287 152 303 168)(font "Arial" (font_size 8)))
+		(text "c4" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c4" (rect 287 152 301 166)(font "Arial" (font_size 8)))
 		(line (pt 304 168)(pt 272 168)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 229 230 295 245)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 244 82)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 58 84 266 99)(font "Arial" ))
-		(text "Clk " (rect 59 111 83 126)(font "Arial" ))
-		(text "Ratio" (rect 85 111 119 126)(font "Arial" ))
-		(text "Ph (dg)" (rect 119 111 166 126)(font "Arial" ))
-		(text "DC (%)" (rect 164 111 211 126)(font "Arial" ))
-		(text "c0" (rect 63 129 78 144)(font "Arial" ))
-		(text "4/1" (rect 91 129 111 144)(font "Arial" ))
-		(text "240.00" (rect 120 129 164 144)(font "Arial" ))
-		(text "50.00" (rect 169 129 205 144)(font "Arial" ))
-		(text "c1" (rect 63 147 78 162)(font "Arial" ))
-		(text "4/1" (rect 91 147 111 162)(font "Arial" ))
-		(text "0.00" (rect 127 147 155 162)(font "Arial" ))
-		(text "50.00" (rect 169 147 205 162)(font "Arial" ))
-		(text "c2" (rect 63 165 78 180)(font "Arial" ))
-		(text "4/1" (rect 91 165 111 180)(font "Arial" ))
-		(text "180.00" (rect 120 165 164 180)(font "Arial" ))
-		(text "50.00" (rect 169 165 205 180)(font "Arial" ))
-		(text "c3" (rect 63 183 78 198)(font "Arial" ))
-		(text "4/1" (rect 91 183 111 198)(font "Arial" ))
-		(text "105.00" (rect 120 183 164 198)(font "Arial" ))
-		(text "50.00" (rect 169 183 205 198)(font "Arial" ))
-		(text "c4" (rect 63 201 78 216)(font "Arial" ))
-		(text "2/1" (rect 91 201 111 216)(font "Arial" ))
-		(text "270.00" (rect 120 201 164 216)(font "Arial" ))
-		(text "50.00" (rect 169 201 205 216)(font "Arial" ))
+		(text "Cyclone III" (rect 229 230 284 242)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 205 79)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 220 96)(font "Arial" ))
+		(text "Clk " (rect 59 111 79 123)(font "Arial" ))
+		(text "Ratio" (rect 85 111 110 123)(font "Arial" ))
+		(text "Ph (dg)" (rect 119 111 154 123)(font "Arial" ))
+		(text "DC (%)" (rect 164 111 200 123)(font "Arial" ))
+		(text "c0" (rect 63 129 74 141)(font "Arial" ))
+		(text "4/1" (rect 91 129 106 141)(font "Arial" ))
+		(text "240.00" (rect 120 129 153 141)(font "Arial" ))
+		(text "50.00" (rect 169 129 196 141)(font "Arial" ))
+		(text "c1" (rect 63 147 74 159)(font "Arial" ))
+		(text "4/1" (rect 91 147 106 159)(font "Arial" ))
+		(text "0.00" (rect 127 147 148 159)(font "Arial" ))
+		(text "50.00" (rect 169 147 196 159)(font "Arial" ))
+		(text "c2" (rect 63 165 74 177)(font "Arial" ))
+		(text "4/1" (rect 91 165 106 177)(font "Arial" ))
+		(text "180.00" (rect 120 165 153 177)(font "Arial" ))
+		(text "50.00" (rect 169 165 196 177)(font "Arial" ))
+		(text "c3" (rect 63 183 74 195)(font "Arial" ))
+		(text "4/1" (rect 91 183 106 195)(font "Arial" ))
+		(text "105.00" (rect 120 183 153 195)(font "Arial" ))
+		(text "50.00" (rect 169 183 196 195)(font "Arial" ))
+		(text "c4" (rect 63 201 74 213)(font "Arial" ))
+		(text "2/1" (rect 91 201 106 213)(font "Arial" ))
+		(text "270.00" (rect 120 201 153 213)(font "Arial" ))
+		(text "50.00" (rect 169 201 196 213)(font "Arial" ))
 		(line (pt 0 0)(pt 305 0)(line_width 1))
 		(line (pt 305 0)(pt 305 249)(line_width 1))
 		(line (pt 0 249)(pt 305 249)(line_width 1))
@@ -2931,20 +2932,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect -16 680 32 712)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst23" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst23" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2956,132 +2957,132 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 192 472 408 768)
-	(text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10)))
-	(text "inst7" (rect 8 277 39 292)(font "Arial" ))
+	(text "altpll_reconfig1" (rect 54 1 155 17)(font "Arial" (font_size 10)))
+	(text "inst7" (rect 8 277 31 289)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "reconfig" (rect 20 32 73 48)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 20 32 67 46)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
-		(text "read_param" (rect 20 48 100 64)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 0 0 68 14)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 20 48 88 62)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
-		(text "write_param" (rect 20 64 102 80)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 20 64 91 78)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
-		(text "data_in[8..0]" (rect 20 88 104 104)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 20 88 89 102)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
-		(text "counter_type[3..0]" (rect 20 104 143 120)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 0 0 103 14)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 20 104 123 118)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 16 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
-		(text "counter_param[2..0]" (rect 20 120 156 136)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 0 0 114 14)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 20 120 134 134)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 16 128)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
-		(text "pll_scandataout" (rect 20 160 127 176)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 20 160 109 174)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 16 168)(line_width 1))
 	)
 	(port
 		(pt 0 184)
 		(input)
-		(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "pll_scandone" (rect 20 176 109 192)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 20 176 95 190)(font "Arial" (font_size 8)))
 		(line (pt 0 184)(pt 16 184)(line_width 1))
 	)
 	(port
 		(pt 0 208)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 20 200 56 216)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 200 49 214)(font "Arial" (font_size 8)))
 		(line (pt 0 208)(pt 16 208)(line_width 1))
 	)
 	(port
 		(pt 0 224)
 		(input)
-		(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
-		(text "reset" (rect 20 216 54 232)(font "Arial" (font_size 8)))
+		(text "reset" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "reset" (rect 20 216 49 230)(font "Arial" (font_size 8)))
 		(line (pt 0 224)(pt 16 224)(line_width 1))
 	)
 	(port
 		(pt 0 248)
 		(input)
-		(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "pll_areset_in" (rect 20 240 106 256)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 20 240 91 254)(font "Arial" (font_size 8)))
 		(line (pt 0 248)(pt 16 248)(line_width 1))
 	)
 	(port
 		(pt 216 40)
 		(output)
-		(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
-		(text "busy" (rect 169 32 202 48)(font "Arial" (font_size 8)))
+		(text "busy" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+		(text "busy" (rect 169 32 197 46)(font "Arial" (font_size 8)))
 		(line (pt 216 40)(pt 200 40)(line_width 1))
 	)
 	(port
 		(pt 216 96)
 		(output)
-		(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
-		(text "data_out[8..0]" (rect 117 88 211 104)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 117 88 194 102)(font "Arial" (font_size 8)))
 		(line (pt 216 96)(pt 200 96)(line_width 3))
 	)
 	(port
 		(pt 216 152)
 		(output)
-		(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "pll_scandata" (rect 124 144 210 160)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 124 144 195 158)(font "Arial" (font_size 8)))
 		(line (pt 216 152)(pt 200 152)(line_width 1))
 	)
 	(port
 		(pt 216 168)
 		(output)
-		(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
-		(text "pll_scanclk" (rect 132 160 208 176)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 0 0 62 14)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 132 160 194 174)(font "Arial" (font_size 8)))
 		(line (pt 216 168)(pt 200 168)(line_width 1))
 	)
 	(port
 		(pt 216 200)
 		(output)
-		(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
-		(text "pll_scanclkena" (rect 111 192 212 208)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 111 192 194 206)(font "Arial" (font_size 8)))
 		(line (pt 216 200)(pt 200 200)(line_width 1))
 	)
 	(port
 		(pt 216 216)
 		(output)
-		(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
-		(text "pll_configupdate" (rect 104 208 213 224)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 0 0 93 14)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 104 208 197 222)(font "Arial" (font_size 8)))
 		(line (pt 216 216)(pt 200 216)(line_width 1))
 	)
 	(port
 		(pt 216 248)
 		(output)
-		(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
-		(text "pll_areset" (rect 141 240 207 256)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 0 0 55 14)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 141 240 196 254)(font "Arial" (font_size 8)))
 		(line (pt 216 248)(pt 200 248)(line_width 1))
 	)
 	(drawing
@@ -3097,90 +3098,90 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 608 496 984 728)
-	(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
-	(text "inst22" (rect 8 213 48 228)(font "Arial" ))
+	(text "altpll4" (rect 168 1 208 17)(font "Arial" (font_size 10)))
+	(text "inst22" (rect 8 213 37 225)(font "Arial" ))
 	(port
 		(pt 0 72)
 		(input)
-		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 56 44 72)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 35 70)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 88 72)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
-		(text "areset" (rect 4 80 46 96)(font "Arial" (font_size 8)))
+		(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 80 40 94)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 88 96)(line_width 1))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "scanclk" (rect 4 104 57 120)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 4 104 47 118)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 88 120)(line_width 1))
 	)
 	(port
 		(pt 0 144)
 		(input)
-		(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
-		(text "scandata" (rect 4 128 66 144)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 4 128 57 142)(font "Arial" (font_size 8)))
 		(line (pt 0 144)(pt 88 144)(line_width 1))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "scanclkena" (rect 4 152 81 168)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 4 152 68 166)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 88 168)(line_width 1))
 	)
 	(port
 		(pt 0 192)
 		(input)
-		(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "configupdate" (rect 4 176 90 192)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 4 176 78 190)(font "Arial" (font_size 8)))
 		(line (pt 0 192)(pt 88 192)(line_width 1))
 	)
 	(port
 		(pt 376 72)
 		(output)
-		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "c0" (rect 359 56 375 72)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 359 56 373 70)(font "Arial" (font_size 8)))
 		(line (pt 376 72)(pt 288 72)(line_width 1))
 	)
 	(port
 		(pt 376 96)
 		(output)
-		(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
-		(text "scandataout" (rect 302 80 385 96)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 302 80 372 94)(font "Arial" (font_size 8)))
 		(line (pt 376 96)(pt 288 96)(line_width 1))
 	)
 	(port
 		(pt 376 120)
 		(output)
-		(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
-		(text "scandone" (rect 317 104 383 120)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 317 104 373 118)(font "Arial" (font_size 8)))
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-		(text "locked" (rect 335 128 379 144)(font "Arial" (font_size 8)))
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+		(text "locked" (rect 335 128 371 142)(font "Arial" (font_size 8)))
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-		(text "0.00" (rect 167 185 195 200)(font "Arial" ))
-		(text "50.00" (rect 209 185 245 200)(font "Arial" ))
+		(text "Cyclone III" (rect 301 214 356 226)(font "Arial" ))
+		(text "inclk0 frequency: 48.000 MHz" (rect 98 123 245 135)(font "Arial" ))
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+		(text "DC (%)" (rect 204 167 240 179)(font "Arial" ))
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 		(line (pt 0 0)(pt 377 0)(line_width 1))
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@@ -3200,203 +3201,285 @@ applicable agreement for further details.
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+		(text "c1" (rect 257 67 271 81)(font "Arial" (font_size 8)))
+		(line (pt 272 80)(pt 224 80)(line_width 1))
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+	(port
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+		(output)
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 271 97)(font "Arial" (font_size 8)))
+		(line (pt 272 96)(pt 224 96)(line_width 1))
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+	(port
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+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 238 99 274 113)(font "Arial" (font_size 8)))
+		(line (pt 272 112)(pt 224 112)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 211 169 266 181)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 197 71)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 73 212 85)(font "Arial" ))
+		(text "Clk " (rect 51 96 71 108)(font "Arial" ))
+		(text "Ratio" (rect 83 96 108 108)(font "Arial" ))
+		(text "Ph (dg)" (rect 121 96 156 108)(font "Arial" ))
+		(text "DC (%)" (rect 156 96 192 108)(font "Arial" ))
+		(text "c0" (rect 54 111 65 123)(font "Arial" ))
+		(text "16/11" (rect 83 111 110 123)(font "Arial" ))
+		(text "0.00" (rect 127 111 148 123)(font "Arial" ))
+		(text "50.00" (rect 160 111 187 123)(font "Arial" ))
+		(text "c1" (rect 54 126 65 138)(font "Arial" ))
+		(text "16/33" (rect 83 126 110 138)(font "Arial" ))
+		(text "0.00" (rect 127 126 148 138)(font "Arial" ))
+		(text "50.00" (rect 160 126 187 138)(font "Arial" ))
+		(text "c2" (rect 54 141 65 153)(font "Arial" ))
+		(text "1024/1375" (rect 73 141 123 153)(font "Arial" ))
+		(text "0.00" (rect 127 141 148 153)(font "Arial" ))
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 	)
 )
 (block
 	(rect 1264 2944 1672 3560)
-	(text "DSP" (rect 5 5 36 21)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 95 617)(font "Arial" ))	(block_io "CLK33M" (input))
+	(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" ))	(block_io "CLK33M" (input))
 	(block_io "MAIN_CLK" (input))
 	(block_io "nFB_OE" (input))
 	(block_io "nFB_WR" (input))
@@ -3507,651 +3590,9 @@ applicable agreement for further details.
 		(bidir)
 		)
 )
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-	(block_io "nPCI_INTC" (input))
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-	(block_io "DSP_INT" (input))
-	(block_io "VSYNC" (input))
-	(block_io "HSYNC" (input))
-	(block_io "DMA_DRQ" (input))
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-	(block_io "CLK2M" (input))
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-	(block_io "DSP_INT" (input))
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-	(block_io "YM_QA" (output))
-	(block_io "YM_QC" (output))
-	(block_io "YM_QB" (output))
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-	(block_io "STEP" (output))
-	(block_io "MOT_ON" (output))
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-	(block_io "nROM3" (output))
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-	(block_io "nCF_CS0" (output))
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-	(block_io "RTS" (output))
-	(block_io "TxD" (output))
-	(block_io "MIDI_OLR" (output))
-	(block_io "MIDI_TLR" (output))
-	(block_io "nDREQ0" (output))
-	(block_io "DSA_D" (output))
-	(block_io "nMFP_INT" (output))
-	(block_io "FALCON_IO_TA" (output))
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-	(block_io "WR_DATA" (output))
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-	(block_io "LP_D[7..0]" (bidir))
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-)
 (block
 	(rect 1264 -48 1672 728)
-	(text "Video" (rect 5 5 43 21)(font "Arial" (font_size 8)))	(text "Fredi_Aschwanden" (rect 5 762 130 777)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
+	(text "Video" (rect 5 5 38 19)(font "Arial" (font_size 8)))	(text "Fredi_Aschwanden" (rect 5 762 97 774)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
 	(block_io "MAIN_CLK" (input))
 	(block_io "nFB_CS1" (input))
 	(block_io "nFB_CS2" (input))
@@ -4362,667 +3803,861 @@ applicable agreement for further details.
 		(bidir)
 		)
 )
-(connector
-	(text "FB_AD[31..0]" (rect 1682 776 1765 791)(font "Arial" ))
-	(pt 1832 792)
-	(pt 1672 792)
-	(bus)
+(block
+	(rect 1264 2344 1672 2904)
+	(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8)))	(text "nobody" (rect 5 546 41 558)(font "Arial" ))	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "PIC_INT" (input))
+	(block_io "E0_INT" (input))
+	(block_io "DVI_INT" (input))
+	(block_io "nPCI_INTA" (input))
+	(block_io "nPCI_INTB" (input))
+	(block_io "nPCI_INTC" (input))
+	(block_io "nPCI_INTD" (input))
+	(block_io "nMFP_INT" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DMA_DRQ" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nIRQ[7..2]" (output))
+	(block_io "INT_HANDLER_TA" (output))
+	(block_io "ACP_CONF[31..0]" (output))
+	(block_io "TIN0" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 408 56)
+		(bidir)
+		)
+	(mapper
+		(pt 408 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 280)
+		(bidir)
+		)
+	(mapper
+		(pt 0 304)
+		(bidir)
+		)
+	(mapper
+		(pt 0 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 400)
+		(bidir)
+		)
+	(mapper
+		(pt 0 328)
+		(bidir)
+		)
+	(mapper
+		(pt 0 352)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 0 480)
+		(bidir)
+		)
+	(mapper
+		(pt 0 504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 504)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 744 1672 2312)
+	(text "FalconIO_SDCard_IDE_CF" (rect 5 5 152 19)(font "Arial" (font_size 8)))	(text "Wolfgang_Foerster_and_Fredi_Aschwanden" (rect 5 1554 220 1566)(font "Arial" ))	(block_io "CLK33M" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "CLK2M" (input))
+	(block_io "CLK500k" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "LP_BUSY" (input))
+	(block_io "nACSI_DRQ" (input))
+	(block_io "nACSI_INT" (input))
+	(block_io "nSCSI_DRQ" (input))
+	(block_io "nSCSI_MSG" (input))
+	(block_io "MIDI_IN" (input))
+	(block_io "RxD" (input))
+	(block_io "CTS" (input))
+	(block_io "RI" (input))
+	(block_io "DCD" (input))
+	(block_io "AMKB_RX" (input))
+	(block_io "PIC_AMKB_RX" (input))
+	(block_io "IDE_RDY" (input))
+	(block_io "IDE_INT" (input))
+	(block_io "WP_CS_CARD" (input))
+	(block_io "nINDEX" (input))
+	(block_io "TRACK00" (input))
+	(block_io "nRD_DATA" (input))
+	(block_io "nDCHG" (input))
+	(block_io "SD_DATA0" (input))
+	(block_io "SD_DATA1" (input))
+	(block_io "SD_DATA2" (input))
+	(block_io "SD_CARD_DEDECT" (input))
+	(block_io "SD_WP" (input))
+	(block_io "nDACK0" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "WP_CF_CARD" (input))
+	(block_io "nWP" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nSCSI_C_D" (input))
+	(block_io "nSCSI_I_O" (input))
+	(block_io "CLK2M4576" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "nBLANK" (input))
+	(block_io "FDC_CLK" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "ACP_CONF[31..24]" (input))
+	(block_io "HD_DD" (input))
+	(block_io "nIDE_CS1" (output))
+	(block_io "nIDE_CS0" (output))
+	(block_io "LP_STR" (output))
+	(block_io "LP_DIR" (output))
+	(block_io "nACSI_ACK" (output))
+	(block_io "nACSI_RESET" (output))
+	(block_io "nACSI_CS" (output))
+	(block_io "ACSI_DIR" (output))
+	(block_io "ACSI_A1" (output))
+	(block_io "nSCSI_ACK" (output))
+	(block_io "nSCSI_ATN" (output))
+	(block_io "SCSI_DIR" (output))
+	(block_io "SD_CLK" (output))
+	(block_io "YM_QA" (output))
+	(block_io "YM_QC" (output))
+	(block_io "YM_QB" (output))
+	(block_io "nSDSEL" (output))
+	(block_io "STEP" (output))
+	(block_io "MOT_ON" (output))
+	(block_io "nRP_LDS" (output))
+	(block_io "nRP_UDS" (output))
+	(block_io "nROM4" (output))
+	(block_io "nROM3" (output))
+	(block_io "nCF_CS1" (output))
+	(block_io "nCF_CS0" (output))
+	(block_io "nIDE_RD" (output))
+	(block_io "nIDE_WR" (output))
+	(block_io "AMKB_TX" (output))
+	(block_io "IDE_RES" (output))
+	(block_io "DTR" (output))
+	(block_io "RTS" (output))
+	(block_io "TxD" (output))
+	(block_io "MIDI_OLR" (output))
+	(block_io "nDREQ0" (output))
+	(block_io "DSA_D" (output))
+	(block_io "nMFP_INT" (output))
+	(block_io "FALCON_IO_TA" (output))
+	(block_io "STEP_DIR" (output))
+	(block_io "WR_DATA" (output))
+	(block_io "WR_GATE" (output))
+	(block_io "DMA_DRQ" (output))
+	(block_io "MIDI_TLR" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "LP_D[7..0]" (bidir))
+	(block_io "ACSI_D[7..0]" (bidir))
+	(block_io "SCSI_D[7..0]" (bidir))
+	(block_io "SCSI_PAR" (bidir))
+	(block_io "nSCSI_SEL" (bidir))
+	(block_io "nSCSI_BUSY" (bidir))
+	(block_io "nSCSI_RST" (bidir))
+	(block_io "SD_CD_DATA3" (bidir))
+	(block_io "SD_CDM_D1" (bidir))
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 96)
+		(bidir)
+		)
+	(mapper
+		(pt 408 120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 352)
+		(bidir)
+		)
+	(mapper
+		(pt 408 328)
+		(bidir)
+		)
+	(mapper
+		(pt 408 448)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 608)
+		(bidir)
+		)
+	(mapper
+		(pt 408 632)
+		(bidir)
+		)
+	(mapper
+		(pt 408 584)
+		(bidir)
+		)
+	(mapper
+		(pt 0 656)
+		(bidir)
+		)
+	(mapper
+		(pt 0 680)
+		(bidir)
+		)
+	(mapper
+		(pt 0 704)
+		(bidir)
+		)
+	(mapper
+		(pt 0 728)
+		(bidir)
+		)
+	(mapper
+		(pt 0 752)
+		(bidir)
+		)
+	(mapper
+		(pt 0 776)
+		(bidir)
+		)
+	(mapper
+		(pt 408 664)
+		(bidir)
+		)
+	(mapper
+		(pt 0 808)
+		(bidir)
+		)
+	(mapper
+		(pt 0 832)
+		(bidir)
+		)
+	(mapper
+		(pt 408 696)
+		(bidir)
+		)
+	(mapper
+		(pt 408 720)
+		(bidir)
+		)
+	(mapper
+		(pt 408 744)
+		(bidir)
+		)
+	(mapper
+		(pt 408 768)
+		(bidir)
+		)
+	(mapper
+		(pt 408 792)
+		(bidir)
+		)
+	(mapper
+		(pt 408 816)
+		(bidir)
+		)
+	(mapper
+		(pt 408 840)
+		(bidir)
+		)
+	(mapper
+		(pt 0 856)
+		(bidir)
+		)
+	(mapper
+		(pt 408 872)
+		(bidir)
+		)
+	(mapper
+		(pt 408 896)
+		(bidir)
+		)
+	(mapper
+		(pt 408 920)
+		(bidir)
+		)
+	(mapper
+		(pt 408 944)
+		(bidir)
+		)
+	(mapper
+		(pt 0 912)
+		(bidir)
+		)
+	(mapper
+		(pt 0 936)
+		(bidir)
+		)
+	(mapper
+		(pt 0 960)
+		(bidir)
+		)
+	(mapper
+		(pt 0 984)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1008)
+		(bidir)
+		)
+	(mapper
+		(pt 408 976)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1000)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1072)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1096)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1040)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1064)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1088)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1112)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1136)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 464)
+		(bidir)
+		)
+	(mapper
+		(pt 0 488)
+		(bidir)
+		)
+	(mapper
+		(pt 0 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 544)
+		(bidir)
+		)
+	(mapper
+		(pt 0 568)
+		(bidir)
+		)
+	(mapper
+		(pt 0 592)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1168)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1192)
+		(bidir)
+		)
+	(mapper
+		(pt 0 368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1216)
+		(bidir)
+		)
+	(mapper
+		(pt 408 48)
+		(bidir)
+		)
+	(mapper
+		(pt 408 16)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1304)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1280)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1048)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1024)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1264)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1336)
+		(bidir)
+		)
+	(mapper
+		(pt 0 888)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1480)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1392)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1544)
+		(bidir)
+		)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 1146 1072 1240 1087)(font "Arial" ))
-	(pt 1112 1088)
-	(pt 1264 1088)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 1162 784 1231 799)(font "Arial" ))
-	(pt 1152 800)
-	(pt 1264 800)
-)
-(connector
-	(text "CLK33M" (rect 1210 760 1265 775)(font "Arial" ))
-	(pt 1200 776)
-	(pt 1264 776)
-)
-(connector
-	(text "CLK2M" (rect 1202 808 1249 823)(font "Arial" ))
-	(pt 1192 824)
-	(pt 1264 824)
-)
-(connector
-	(text "CLK500k" (rect 1202 832 1262 847)(font "Arial" ))
-	(pt 1192 848)
-	(pt 1264 848)
-)
-(connector
-	(text "LP_DIR" (rect 1682 848 1732 863)(font "Arial" ))
-	(pt 1672 864)
-	(pt 1832 864)
-)
-(connector
-	(text "LP_STR" (rect 1682 824 1736 839)(font "Arial" ))
-	(pt 1672 840)
-	(pt 1832 840)
-)
-(connector
-	(text "nACSI_ACK" (rect 1682 928 1758 943)(font "Arial" ))
-	(pt 1672 944)
-	(pt 1832 944)
-)
-(connector
-	(text "nACSI_RESET" (rect 1682 952 1777 967)(font "Arial" ))
-	(pt 1672 968)
-	(pt 1832 968)
-)
-(connector
-	(text "nACSI_CS" (rect 1682 976 1750 991)(font "Arial" ))
-	(pt 1672 992)
-	(pt 1832 992)
-)
-(connector
-	(text "ACSI_DIR" (rect 1682 1000 1746 1015)(font "Arial" ))
-	(pt 1672 1016)
-	(pt 1832 1016)
-)
-(connector
-	(text "ACSI_A1" (rect 1682 1024 1738 1039)(font "Arial" ))
-	(pt 1672 1040)
-	(pt 1832 1040)
-)
-(connector
-	(text "nSCSI_ATN" (rect 1682 1128 1758 1143)(font "Arial" ))
-	(pt 1672 1144)
-	(pt 1840 1144)
-)
-(connector
-	(text "SCSI_DIR" (rect 1682 1152 1748 1167)(font "Arial" ))
-	(pt 1672 1168)
-	(pt 1840 1168)
-)
-(connector
-	(text "nSCSI_DRQ" (rect 1114 1248 1195 1263)(font "Arial" ))
-	(pt 1264 1264)
-	(pt 1104 1264)
-)
-(connector
-	(text "nSCSI_MSG" (rect 1114 1320 1194 1335)(font "Arial" ))
-	(pt 1104 1336)
-	(pt 1264 1336)
-)
-(connector
-	(text "nSCSI_RST" (rect 1682 1176 1759 1191)(font "Arial" ))
-	(pt 1672 1192)
-	(pt 1840 1192)
-)
-(connector
-	(text "nSCSI_SEL" (rect 1680 1200 1756 1215)(font "Arial" ))
-	(pt 1672 1216)
-	(pt 1840 1216)
-)
-(connector
-	(text "nSCSI_BUSY" (rect 1682 1224 1769 1239)(font "Arial" ))
-	(pt 1672 1240)
-	(pt 1840 1240)
-)
-(connector
-	(text "TxD" (rect 1682 1312 1706 1327)(font "Arial" ))
-	(pt 1672 1328)
-	(pt 1840 1328)
-)
-(connector
-	(text "RTS" (rect 1682 1336 1710 1351)(font "Arial" ))
-	(pt 1672 1352)
-	(pt 1840 1352)
-)
-(connector
-	(text "DTR" (rect 1680 1360 1709 1375)(font "Arial" ))
-	(pt 1672 1376)
-	(pt 1848 1376)
-)
-(connector
-	(text "CTS" (rect 1114 1408 1142 1423)(font "Arial" ))
-	(pt 1104 1424)
-	(pt 1264 1424)
-)
-(connector
-	(text "RI" (rect 1114 1432 1128 1447)(font "Arial" ))
-	(pt 1104 1448)
-	(pt 1264 1448)
-)
-(connector
-	(text "DCD" (rect 1114 1456 1145 1471)(font "Arial" ))
-	(pt 1104 1472)
-	(pt 1264 1472)
-)
-(connector
-	(text "IDE_RDY" (rect 1114 1536 1175 1551)(font "Arial" ))
-	(pt 1264 1552)
-	(pt 1104 1552)
-)
-(connector
-	(text "IDE_INT" (rect 1114 1560 1168 1575)(font "Arial" ))
-	(pt 1104 1576)
-	(pt 1264 1576)
-)
-(connector
-	(text "IDE_RES" (rect 1682 1424 1743 1439)(font "Arial" ))
-	(pt 1672 1440)
-	(pt 1848 1440)
-)
-(connector
-	(text "nIDE_CS0" (rect 1682 1448 1750 1463)(font "Arial" ))
-	(pt 1672 1464)
-	(pt 1848 1464)
-)
-(connector
-	(text "nIDE_CS1" (rect 1682 1472 1750 1487)(font "Arial" ))
-	(pt 1672 1488)
-	(pt 1856 1488)
-)
-(connector
-	(text "nIDE_WR" (rect 1682 1496 1745 1511)(font "Arial" ))
-	(pt 1672 1512)
-	(pt 1848 1512)
-)
-(connector
-	(text "nIDE_RD" (rect 1682 1520 1743 1535)(font "Arial" ))
-	(pt 1672 1536)
-	(pt 1848 1536)
-)
-(connector
-	(text "nCF_CS0" (rect 1682 1544 1745 1559)(font "Arial" ))
-	(pt 1672 1560)
-	(pt 1848 1560)
-)
-(connector
-	(text "nCF_CS1" (rect 1682 1568 1745 1583)(font "Arial" ))
-	(pt 1672 1584)
-	(pt 1848 1584)
-)
-(connector
-	(text "WP_CF_CARD" (rect 1112 1584 1209 1599)(font "Arial" ))
-	(pt 1104 1600)
-	(pt 1264 1600)
-)
-(connector
-	(text "nSDSEL" (rect 1682 1848 1737 1863)(font "Arial" ))
-	(pt 1672 1864)
-	(pt 1856 1864)
-)
-(connector
-	(text "nDREQ0" (rect 1682 2152 1739 2167)(font "Arial" ))
-	(pt 1672 2168)
-	(pt 1856 2168)
-)
-(connector
-	(text "SD_CLK" (rect 1682 2032 1738 2047)(font "Arial" ))
-	(pt 1856 2048)
-	(pt 1672 2048)
-)
-(connector
-	(text "SD_DATA0" (rect 1114 1768 1185 1783)(font "Arial" ))
-	(pt 1104 1784)
-	(pt 1264 1784)
-)
-(connector
-	(text "SD_DATA1" (rect 1114 1792 1185 1807)(font "Arial" ))
-	(pt 1104 1808)
-	(pt 1264 1808)
-)
-(connector
-	(text "SD_DATA2" (rect 1114 1816 1185 1831)(font "Arial" ))
-	(pt 1104 1832)
-	(pt 1264 1832)
-)
-(connector
-	(text "SD_WP" (rect 1114 1864 1164 1879)(font "Arial" ))
-	(pt 1104 1880)
-	(pt 1264 1880)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1146 2536 1240 2551)(font "Arial" ))
-	(pt 1112 2552)
-	(pt 1264 2552)
-	(bus)
-)
-(connector
-	(text "nFB_WR" (rect 1162 2416 1219 2431)(font "Arial" ))
-	(pt 1152 2432)
-	(pt 1264 2432)
-)
-(connector
-	(text "nFB_CS1" (rect 1154 2440 1216 2455)(font "Arial" ))
-	(pt 1152 2456)
-	(pt 1264 2456)
-)
-(connector
-	(text "FB_SIZE0" (rect 1154 2488 1218 2503)(font "Arial" ))
-	(pt 1152 2504)
-	(pt 1264 2504)
-)
-(connector
-	(text "FB_SIZE1" (rect 1154 2512 1218 2527)(font "Arial" ))
-	(pt 1152 2528)
-	(pt 1264 2528)
-)
-(connector
-	(text "MAIN_CLK" (rect 1162 2368 1231 2383)(font "Arial" ))
-	(pt 1152 2384)
-	(pt 1264 2384)
-)
-(connector
-	(text "nFB_CS2" (rect 1162 2464 1224 2479)(font "Arial" ))
-	(pt 1152 2480)
-	(pt 1264 2480)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 2384 1765 2399)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 1682 2384 1749 2396)(font "Arial" ))
 	(pt 1832 2400)
 	(pt 1672 2400)
 	(bus)
 )
 (connector
-	(text "nSCSI_ACK" (rect 1682 1104 1759 1119)(font "Arial" ))
-	(pt 1672 1120)
-	(pt 1840 1120)
-)
-(connector
-	(text "SCSI_PAR" (rect 1682 1080 1751 1095)(font "Arial" ))
-	(pt 1672 1096)
-	(pt 1840 1096)
-)
-(connector
-	(text "MIDI_OLR" (rect 1762 1256 1828 1271)(font "Arial" ))
-	(pt 1672 1272)
-	(pt 1920 1272)
-)
-(connector
-	(text "MIDI_TLR" (rect 1770 1280 1833 1295)(font "Arial" ))
-	(pt 1672 1296)
-	(pt 1920 1296)
-)
-(connector
-	(text "nROM3" (rect 1754 1600 1802 1615)(font "Arial" ))
-	(pt 1672 1616)
-	(pt 1920 1616)
-)
-(connector
-	(text "nROM4" (rect 1754 1624 1802 1639)(font "Arial" ))
-	(pt 1672 1640)
-	(pt 1920 1640)
-)
-(connector
-	(text "nRP_UDS" (rect 1744 1648 1811 1663)(font "Arial" ))
-	(pt 1672 1664)
-	(pt 1920 1664)
-)
-(connector
-	(text "nRP_LDS" (rect 1746 1672 1810 1687)(font "Arial" ))
-	(pt 1672 1688)
-	(pt 1920 1688)
-)
-(connector
-	(text "YM_QA" (rect 1762 1904 1808 1919)(font "Arial" ))
-	(pt 1672 1920)
-	(pt 1928 1920)
-)
-(connector
-	(text "YM_QB" (rect 1762 1928 1809 1943)(font "Arial" ))
-	(pt 1672 1944)
-	(pt 1928 1944)
-)
-(connector
-	(text "YM_QC" (rect 1762 1952 1810 1967)(font "Arial" ))
-	(pt 1672 1968)
-	(pt 1928 1968)
-)
-(connector
-	(text "LP_BUSY" (rect 1114 1160 1177 1175)(font "Arial" ))
-	(pt 1264 1176)
-	(pt 1104 1176)
-)
-(connector
-	(text "nACSI_DRQ" (rect 1034 1192 1114 1207)(font "Arial" ))
-	(pt 1024 1208)
-	(pt 1264 1208)
-)
-(connector
-	(text "nACSI_INT" (rect 1034 1216 1104 1231)(font "Arial" ))
-	(pt 1024 1232)
-	(pt 1264 1232)
-)
-(connector
-	(text "MIDI_IN" (rect 1050 1352 1100 1367)(font "Arial" ))
-	(pt 1040 1368)
-	(pt 1264 1368)
-)
-(connector
-	(text "RxD" (rect 1114 1384 1141 1399)(font "Arial" ))
-	(pt 1264 1400)
-	(pt 1104 1400)
-)
-(connector
-	(text "nINDEX" (rect 1050 1640 1100 1655)(font "Arial" ))
-	(pt 1040 1656)
-	(pt 1264 1656)
-)
-(connector
-	(text "TRACK00" (rect 1050 1664 1113 1679)(font "Arial" ))
-	(pt 1040 1680)
-	(pt 1264 1680)
-)
-(connector
-	(text "nWP" (rect 1050 1688 1080 1703)(font "Arial" ))
-	(pt 1040 1704)
-	(pt 1264 1704)
-)
-(connector
-	(text "nRD_DATA" (rect 1050 1712 1123 1727)(font "Arial" ))
-	(pt 1040 1728)
-	(pt 1264 1728)
-)
-(connector
-	(text "nDCHG" (rect 1050 1736 1100 1751)(font "Arial" ))
-	(pt 1040 1752)
-	(pt 1264 1752)
-)
-(connector
-	(text "SD_CARD_DEDECT" (rect 1138 1840 1273 1855)(font "Arial" ))
-	(pt 1264 1856)
-	(pt 1128 1856)
-)
-(connector
-	(text "SD_CD_DATA3" (rect 1682 1984 1783 1999)(font "Arial" ))
-	(pt 1672 2000)
-	(pt 1856 2000)
-)
-(connector
-	(text "SD_CDM_D1" (rect 1682 2008 1769 2023)(font "Arial" ))
-	(pt 1672 2024)
-	(pt 1856 2024)
-)
-(connector
-	(text "nSCSI_C_D" (rect 1114 1272 1193 1287)(font "Arial" ))
-	(pt 1104 1288)
-	(pt 1264 1288)
-)
-(connector
-	(text "nSCSI_I_O" (rect 1114 1296 1185 1311)(font "Arial" ))
-	(pt 1104 1312)
-	(pt 1264 1312)
-)
-(connector
-	(text "DSA_D" (rect 1682 1704 1729 1719)(font "Arial" ))
-	(pt 1672 1720)
-	(pt 1856 1720)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 1682 8 1765 23)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 1682 8 1749 20)(font "Arial" ))
 	(pt 1832 24)
 	(pt 1672 24)
 	(bus)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 1146 328 1240 343)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 1146 328 1221 340)(font "Arial" ))
 	(pt 1112 344)
 	(pt 1264 344)
 	(bus)
 )
 (connector
-	(text "nFB_WR" (rect 1162 184 1219 199)(font "Arial" ))
+	(text "nFB_WR" (rect 1162 184 1206 196)(font "Arial" ))
 	(pt 1152 200)
 	(pt 1264 200)
 )
 (connector
-	(text "nFB_CS1" (rect 1154 208 1216 223)(font "Arial" ))
+	(text "nFB_CS1" (rect 1154 208 1201 220)(font "Arial" ))
 	(pt 1152 224)
 	(pt 1264 224)
 )
 (connector
-	(text "FB_SIZE0" (rect 1154 256 1218 271)(font "Arial" ))
+	(text "FB_SIZE0" (rect 1154 256 1204 268)(font "Arial" ))
 	(pt 1152 272)
 	(pt 1264 272)
 )
 (connector
-	(text "FB_SIZE1" (rect 1154 280 1218 295)(font "Arial" ))
+	(text "FB_SIZE1" (rect 1154 280 1204 292)(font "Arial" ))
 	(pt 1152 296)
 	(pt 1264 296)
 )
 (connector
-	(text "nFB_CS2" (rect 1162 232 1224 247)(font "Arial" ))
+	(text "nFB_CS2" (rect 1162 232 1209 244)(font "Arial" ))
 	(pt 1152 248)
 	(pt 1264 248)
 )
 (connector
-	(text "nBLANK" (rect 1682 184 1736 199)(font "Arial" ))
+	(text "nBLANK" (rect 1682 184 1723 196)(font "Arial" ))
 	(pt 1672 200)
 	(pt 1832 200)
 )
 (connector
-	(text "nSYNC" (rect 1682 208 1729 223)(font "Arial" ))
+	(text "nSYNC" (rect 1682 208 1719 220)(font "Arial" ))
 	(pt 1672 224)
 	(pt 1832 224)
 )
 (connector
-	(text "nFB_CS3" (rect 1186 352 1248 367)(font "Arial" ))
+	(text "nFB_CS3" (rect 1186 352 1233 364)(font "Arial" ))
 	(pt 1264 368)
 	(pt 1176 368)
 )
 (connector
-	(text "nFB_WR" (rect 1170 928 1227 943)(font "Arial" ))
-	(pt 1264 944)
-	(pt 1160 944)
-)
-(connector
-	(text "nFB_CS1" (rect 1162 952 1224 967)(font "Arial" ))
-	(pt 1264 968)
-	(pt 1160 968)
-)
-(connector
-	(text "nFB_CS2" (rect 1170 976 1232 991)(font "Arial" ))
-	(pt 1264 992)
-	(pt 1160 992)
-)
-(connector
-	(text "FB_SIZE0" (rect 1162 1000 1226 1015)(font "Arial" ))
-	(pt 1264 1016)
-	(pt 1160 1016)
-)
-(connector
-	(text "FB_SIZE1" (rect 1162 1024 1226 1039)(font "Arial" ))
-	(pt 1264 1040)
-	(pt 1160 1040)
-)
-(connector
-	(text "nFB_BURST" (rect 1162 1048 1244 1063)(font "Arial" ))
-	(pt 1264 1064)
-	(pt 1160 1064)
-)
-(connector
-	(text "nDACK0" (rect 1250 1096 1305 1111)(font "Arial" ))
-	(pt 1264 1112)
-	(pt 1160 1112)
-)
-(connector
-	(text "nRSTO" (rect 1170 1120 1217 1135)(font "Arial" ))
-	(pt 1264 1136)
-	(pt 1160 1136)
-)
-(connector
-	(text "nPD_VGA" (rect 1682 256 1745 271)(font "Arial" ))
+	(text "nPD_VGA" (rect 1682 256 1731 268)(font "Arial" ))
 	(pt 1672 272)
 	(pt 1832 272)
 )
 (connector
-	(text "PIC_INT" (rect 1162 2584 1216 2599)(font "Arial" ))
+	(text "PIC_INT" (rect 1162 2584 1204 2596)(font "Arial" ))
 	(pt 1152 2600)
 	(pt 1264 2600)
 )
 (connector
-	(text "nIRQ[7..2]" (rect 1682 2408 1745 2423)(font "Arial" ))
+	(text "nIRQ[7..2]" (rect 1682 2408 1733 2420)(font "Arial" ))
 	(pt 1672 2424)
 	(pt 1832 2424)
 	(bus)
 )
 (connector
-	(text "CLK2M4576" (rect 1202 856 1282 871)(font "Arial" ))
-	(pt 1192 872)
-	(pt 1264 872)
-)
-(connector
-	(text "nFB_OE" (rect 1170 904 1224 919)(font "Arial" ))
-	(pt 1264 920)
-	(pt 1160 920)
-)
-(connector
-	(text "nFB_OE" (rect 1170 160 1224 175)(font "Arial" ))
+	(text "nFB_OE" (rect 1170 160 1211 172)(font "Arial" ))
 	(pt 1264 176)
 	(pt 1160 176)
 )
 (connector
-	(text "nFB_OE" (rect 1170 2392 1224 2407)(font "Arial" ))
-	(pt 1264 2408)
-	(pt 1160 2408)
-)
-(connector
-	(text "DVI_INT" (rect 1162 2632 1215 2647)(font "Arial" ))
-	(pt 1152 2648)
-	(pt 1264 2648)
-)
-(connector
-	(text "nPCI_INTA" (rect 1162 2728 1232 2743)(font "Arial" ))
+	(text "nPCI_INTA" (rect 1162 2728 1217 2740)(font "Arial" ))
 	(pt 1152 2744)
 	(pt 1264 2744)
 )
 (connector
-	(text "nPCI_INTB" (rect 1162 2704 1233 2719)(font "Arial" ))
+	(text "nPCI_INTB" (rect 1162 2704 1217 2716)(font "Arial" ))
 	(pt 1152 2720)
 	(pt 1264 2720)
 )
 (connector
-	(text "nPCI_INTC" (rect 1162 2680 1235 2695)(font "Arial" ))
+	(text "nPCI_INTC" (rect 1162 2680 1218 2692)(font "Arial" ))
 	(pt 1152 2696)
 	(pt 1264 2696)
 )
 (connector
-	(text "nPCI_INTD" (rect 1162 2656 1235 2671)(font "Arial" ))
+	(text "nPCI_INTD" (rect 1162 2656 1218 2668)(font "Arial" ))
 	(pt 1152 2672)
 	(pt 1264 2672)
 )
 (connector
-	(text "nMFP_INT" (rect 1162 2760 1229 2775)(font "Arial" ))
+	(text "nMFP_INT" (rect 1162 2760 1213 2772)(font "Arial" ))
 	(pt 1152 2776)
 	(pt 1264 2776)
 )
 (connector
-	(text "nMFP_INT" (rect 1682 2072 1749 2087)(font "Arial" ))
-	(pt 1672 2088)
-	(pt 1784 2088)
-)
-(connector
-	(text "E0_INT" (rect 1162 2608 1210 2623)(font "Arial" ))
+	(text "E0_INT" (rect 1162 2608 1198 2620)(font "Arial" ))
 	(pt 1152 2624)
 	(pt 1264 2624)
 )
 (connector
-	(text "FB_AD[31..0]" (rect 1682 2968 1765 2983)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 1682 2968 1749 2980)(font "Arial" ))
 	(pt 1832 2984)
 	(pt 1672 2984)
 	(bus)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 1146 3224 1240 3239)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 1146 3224 1221 3236)(font "Arial" ))
 	(pt 1112 3240)
 	(pt 1264 3240)
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 1162 3008 1231 3023)(font "Arial" ))
+	(text "MAIN_CLK" (rect 1162 3008 1216 3020)(font "Arial" ))
 	(pt 1152 3024)
 	(pt 1264 3024)
 )
 (connector
-	(text "CLK33M" (rect 1210 2984 1265 2999)(font "Arial" ))
+	(text "CLK33M" (rect 1210 2984 1251 2996)(font "Arial" ))
 	(pt 1200 3000)
 	(pt 1264 3000)
 )
 (connector
-	(text "nFB_WR" (rect 1170 3056 1227 3071)(font "Arial" ))
+	(text "nFB_WR" (rect 1170 3056 1214 3068)(font "Arial" ))
 	(pt 1264 3072)
 	(pt 1160 3072)
 )
 (connector
-	(text "nFB_CS1" (rect 1162 3080 1224 3095)(font "Arial" ))
+	(text "nFB_CS1" (rect 1162 3080 1209 3092)(font "Arial" ))
 	(pt 1264 3096)
 	(pt 1160 3096)
 )
 (connector
-	(text "nFB_CS2" (rect 1170 3104 1232 3119)(font "Arial" ))
+	(text "nFB_CS2" (rect 1170 3104 1217 3116)(font "Arial" ))
 	(pt 1264 3120)
 	(pt 1160 3120)
 )
 (connector
-	(text "FB_SIZE0" (rect 1162 3152 1226 3167)(font "Arial" ))
+	(text "FB_SIZE0" (rect 1162 3152 1212 3164)(font "Arial" ))
 	(pt 1264 3168)
 	(pt 1160 3168)
 )
 (connector
-	(text "FB_SIZE1" (rect 1162 3176 1226 3191)(font "Arial" ))
+	(text "FB_SIZE1" (rect 1162 3176 1212 3188)(font "Arial" ))
 	(pt 1264 3192)
 	(pt 1160 3192)
 )
 (connector
-	(text "nFB_BURST" (rect 1162 3200 1244 3215)(font "Arial" ))
+	(text "nFB_BURST" (rect 1162 3200 1224 3212)(font "Arial" ))
 	(pt 1264 3216)
 	(pt 1160 3216)
 )
 (connector
-	(text "nRSTO" (rect 1170 3248 1217 3263)(font "Arial" ))
+	(text "nRSTO" (rect 1170 3248 1205 3260)(font "Arial" ))
 	(pt 1264 3264)
 	(pt 1160 3264)
 )
 (connector
-	(text "nFB_OE" (rect 1170 3032 1224 3047)(font "Arial" ))
+	(text "nFB_OE" (rect 1170 3032 1211 3044)(font "Arial" ))
 	(pt 1264 3048)
 	(pt 1160 3048)
 )
 (connector
-	(text "nSRCS" (rect 1682 3272 1730 3287)(font "Arial" ))
+	(text "nSRCS" (rect 1682 3272 1718 3284)(font "Arial" ))
 	(pt 1824 3288)
 	(pt 1672 3288)
 )
 (connector
-	(text "nSRBLE" (rect 1682 3296 1737 3311)(font "Arial" ))
+	(text "nSRBLE" (rect 1682 3296 1723 3308)(font "Arial" ))
 	(pt 1824 3312)
 	(pt 1672 3312)
 )
 (connector
-	(text "nSRBHE" (rect 1682 3320 1739 3335)(font "Arial" ))
+	(text "nSRBHE" (rect 1682 3320 1725 3332)(font "Arial" ))
 	(pt 1824 3336)
 	(pt 1672 3336)
 )
 (connector
-	(text "nSRWE" (rect 1682 3344 1732 3359)(font "Arial" ))
+	(text "nSRWE" (rect 1682 3344 1720 3356)(font "Arial" ))
 	(pt 1824 3360)
 	(pt 1672 3360)
 )
 (connector
-	(text "nSROE" (rect 1682 3368 1730 3383)(font "Arial" ))
+	(text "nSROE" (rect 1682 3368 1718 3380)(font "Arial" ))
 	(pt 1824 3384)
 	(pt 1672 3384)
 )
 (connector
-	(text "DSP_INT" (rect 1130 2832 1190 2847)(font "Arial" ))
+	(text "DSP_INT" (rect 1130 2832 1176 2844)(font "Arial" ))
 	(pt 1264 2848)
 	(pt 1120 2848)
 )
 (connector
-	(text "DSP_INT" (rect 1682 3000 1742 3015)(font "Arial" ))
+	(text "DSP_INT" (rect 1682 3000 1728 3012)(font "Arial" ))
 	(pt 1816 3016)
 	(pt 1672 3016)
 )
 (connector
-	(text "CLK500k" (rect 482 2040 542 2055)(font "Arial" ))
+	(text "CLK500k" (rect 482 2040 526 2052)(font "Arial" ))
 	(pt 472 2056)
 	(pt 544 2056)
 )
@@ -5031,198 +4666,155 @@ applicable agreement for further details.
 	(pt 616 2416)
 )
 (connector
-	(text "FB_ALE" (rect 1194 304 1245 319)(font "Arial" ))
+	(text "FB_ALE" (rect 1194 304 1234 316)(font "Arial" ))
 	(pt 1264 320)
 	(pt 1184 320)
 )
 (connector
-	(text "DDRCLK[3..0]" (rect 1162 136 1252 151)(font "Arial" ))
+	(text "DDRCLK[3..0]" (rect 1162 136 1233 148)(font "Arial" ))
 	(pt 1152 152)
 	(pt 1264 152)
 	(bus)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 1178 112 1292 127)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 1178 112 1266 124)(font "Arial" ))
 	(pt 1168 128)
 	(pt 1264 128)
 )
 (connector
-	(text "VD[31..0]" (rect 1682 288 1739 303)(font "Arial" ))
+	(text "VD[31..0]" (rect 1682 288 1729 300)(font "Arial" ))
 	(pt 1672 304)
 	(pt 2648 304)
 	(bus)
 )
 (connector
-	(text "VA[12..0]" (rect 1682 312 1737 327)(font "Arial" ))
+	(text "VA[12..0]" (rect 1682 312 1728 324)(font "Arial" ))
 	(pt 1672 328)
 	(pt 2528 328)
 	(bus)
 )
 (connector
-	(text "nVWE" (rect 1682 336 1720 351)(font "Arial" ))
+	(text "nVWE" (rect 1682 336 1712 348)(font "Arial" ))
 	(pt 1672 352)
 	(pt 2400 352)
 )
 (connector
-	(text "nVCAS" (rect 1690 360 1734 375)(font "Arial" ))
+	(text "nVCAS" (rect 1690 360 1725 372)(font "Arial" ))
 	(pt 1672 376)
 	(pt 2304 376)
 )
 (connector
-	(text "nVRAS" (rect 1690 384 1734 399)(font "Arial" ))
+	(text "nVRAS" (rect 1690 384 1725 396)(font "Arial" ))
 	(pt 1672 400)
 	(pt 2208 400)
 )
 (connector
-	(text "nVCS" (rect 1690 408 1726 423)(font "Arial" ))
+	(text "nVCS" (rect 1690 408 1718 420)(font "Arial" ))
 	(pt 1672 424)
 	(pt 2040 424)
 )
 (connector
-	(text "VCKE" (rect 1690 432 1727 447)(font "Arial" ))
+	(text "VCKE" (rect 1690 432 1719 444)(font "Arial" ))
 	(pt 1672 448)
 	(pt 1944 448)
 )
 (connector
-	(text "VSYNC" (rect 1682 136 1729 151)(font "Arial" ))
+	(text "VSYNC" (rect 1682 136 1720 148)(font "Arial" ))
 	(pt 1672 152)
 	(pt 1832 152)
 )
 (connector
-	(text "HSYNC" (rect 1682 160 1731 175)(font "Arial" ))
+	(text "HSYNC" (rect 1682 160 1722 172)(font "Arial" ))
 	(pt 1672 176)
 	(pt 1832 176)
 )
 (connector
-	(text "VB[7..0]" (rect 1754 112 1802 127)(font "Arial" ))
+	(text "VB[7..0]" (rect 1754 112 1794 124)(font "Arial" ))
 	(pt 1672 128)
 	(pt 1912 128)
 	(bus)
 )
 (connector
-	(text "VG[7..0]" (rect 1842 88 1891 103)(font "Arial" ))
+	(text "VG[7..0]" (rect 1842 88 1883 100)(font "Arial" ))
 	(pt 1672 104)
 	(pt 2000 104)
 	(bus)
 )
 (connector
-	(text "VR[7..0]" (rect 1922 64 1971 79)(font "Arial" ))
+	(text "VR[7..0]" (rect 1922 64 1963 76)(font "Arial" ))
 	(pt 1672 80)
 	(pt 2080 80)
 	(bus)
 )
 (connector
-	(text "IO[17..0]" (rect 1962 3224 2015 3239)(font "Arial" ))
+	(text "IO[17..0]" (rect 1962 3224 2005 3236)(font "Arial" ))
 	(pt 1672 3240)
 	(pt 2104 3240)
 	(bus)
 )
 (connector
-	(text "SRD[15..0]" (rect 1802 3248 1871 3263)(font "Arial" ))
+	(text "SRD[15..0]" (rect 1802 3248 1857 3260)(font "Arial" ))
 	(pt 1672 3264)
 	(pt 1944 3264)
 	(bus)
 )
 (connector
-	(text "SCSI_D[7..0]" (rect 1786 1056 1868 1071)(font "Arial" ))
-	(pt 1672 1072)
-	(pt 1936 1072)
-	(bus)
-)
-(connector
-	(text "ACSI_D[7..0]" (rect 1754 880 1835 895)(font "Arial" ))
-	(pt 1672 896)
-	(pt 1904 896)
-	(bus)
-)
-(connector
-	(text "LP_D[7..0]" (rect 1810 800 1877 815)(font "Arial" ))
-	(pt 1672 816)
-	(pt 1960 816)
-	(bus)
-)
-(connector
-	(text "AMKB_RX" (rect 786 1480 850 1495)(font "Arial" ))
-	(pt 776 1496)
-	(pt 1264 1496)
-)
-(connector
-	(text "CLK33M" (rect 346 288 401 303)(font "Arial" ))
-	(pt 336 304)
-	(pt 400 304)
-)
-(connector
-	(text "CLK25M" (rect 1202 608 1257 623)(font "Arial" ))
+	(text "CLK25M" (rect 1202 608 1243 620)(font "Arial" ))
 	(pt 1192 624)
 	(pt 1264 624)
 )
 (connector
-	(text "TIMEBASE[17]" (rect 354 2120 446 2135)(font "Arial" ))
+	(text "TIMEBASE[17]" (rect 354 2120 425 2132)(font "Arial" ))
 	(pt 440 2136)
 	(pt 344 2136)
 )
 (connector
-	(text "TIMEBASE[17..0]" (rect 706 2048 813 2063)(font "Arial" ))
+	(text "TIMEBASE[17..0]" (rect 706 2048 790 2060)(font "Arial" ))
 	(pt 688 2064)
 	(pt 808 2064)
 	(bus)
 )
 (connector
-	(text "HSYNC" (rect 1130 2784 1179 2799)(font "Arial" ))
+	(text "HSYNC" (rect 1130 2784 1170 2796)(font "Arial" ))
 	(pt 1264 2800)
 	(pt 1120 2800)
 )
 (connector
-	(text "VSYNC" (rect 1130 2808 1177 2823)(font "Arial" ))
+	(text "VSYNC" (rect 1130 2808 1168 2820)(font "Arial" ))
 	(pt 1264 2824)
 	(pt 1120 2824)
 )
-(connector
-	(text "VSYNC" (rect 1130 1920 1177 1935)(font "Arial" ))
-	(pt 1264 1936)
-	(pt 1120 1936)
-)
-(connector
-	(text "HSYNC" (rect 1130 1896 1179 1911)(font "Arial" ))
-	(pt 1264 1912)
-	(pt 1120 1912)
-)
 (connector
 	(pt 488 2136)
 	(pt 608 2136)
 )
 (connector
-	(text "nFB_TA" (rect 1946 720 1996 735)(font "Arial" ))
+	(text "nFB_TA" (rect 1946 720 1984 732)(font "Arial" ))
 	(pt 1944 736)
 	(pt 2056 736)
 )
 (connector
-	(text "INT_HANDLER_TA" (rect 1682 2832 1805 2847)(font "Arial" ))
+	(text "INT_HANDLER_TA" (rect 1682 2832 1777 2844)(font "Arial" ))
 	(pt 1672 2848)
 	(pt 1808 2848)
 )
 (connector
-	(text "DSP_TA" (rect 1682 3504 1736 3519)(font "Arial" ))
+	(text "DSP_TA" (rect 1682 3504 1723 3516)(font "Arial" ))
 	(pt 1672 3520)
 	(pt 1792 3520)
 )
 (connector
-	(text "Video_TA" (rect 1682 696 1743 711)(font "Arial" ))
+	(text "Video_TA" (rect 1682 696 1728 708)(font "Arial" ))
 	(pt 1672 712)
 	(pt 1880 712)
 )
 (connector
-	(text "FALCON_IO_TA" (rect 1682 744 1785 759)(font "Arial" ))
-	(pt 1672 760)
-	(pt 1880 760)
-)
-(connector
-	(text "INT_HANDLER_TA" (rect 1810 728 1933 743)(font "Arial" ))
+	(text "INT_HANDLER_TA" (rect 1810 728 1905 740)(font "Arial" ))
 	(pt 1880 744)
 	(pt 1800 744)
 )
 (connector
-	(text "DSP_TA" (rect 1810 712 1864 727)(font "Arial" ))
+	(text "DSP_TA" (rect 1810 712 1851 724)(font "Arial" ))
 	(pt 1880 728)
 	(pt 1800 728)
 )
@@ -5239,7 +4831,7 @@ applicable agreement for further details.
 	(pt 2504 760)
 )
 (connector
-	(text "DDRCLK[0]" (rect 2450 744 2525 759)(font "Arial" ))
+	(text "DDRCLK[0]" (rect 2450 744 2509 756)(font "Arial" ))
 	(pt 2440 760)
 	(pt 2504 760)
 )
@@ -5248,38 +4840,38 @@ applicable agreement for further details.
 	(pt 2536 760)
 )
 (connector
-	(text "MAIN_CLK" (rect 1186 88 1255 103)(font "Arial" ))
+	(text "MAIN_CLK" (rect 1186 88 1240 100)(font "Arial" ))
 	(pt 1184 104)
 	(pt 1264 104)
 )
 (connector
-	(text "nRSTO" (rect 1194 40 1241 55)(font "Arial" ))
+	(text "nRSTO" (rect 1194 40 1229 52)(font "Arial" ))
 	(pt 1184 56)
 	(pt 1264 56)
 )
 (connector
-	(text "BA[1..0]" (rect 1682 456 1730 471)(font "Arial" ))
+	(text "BA[1..0]" (rect 1682 456 1722 468)(font "Arial" ))
 	(pt 1672 472)
 	(pt 1832 472)
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2394 -64 2469 -49)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2394 -64 2450 -52)(font "Arial" ))
 	(pt 2384 -48)
 	(pt 2464 -48)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2394 56 2469 71)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2394 56 2450 68)(font "Arial" ))
 	(pt 2384 72)
 	(pt 2464 72)
 )
 (connector
-	(text "nBLANK" (rect 2394 24 2448 39)(font "Arial" ))
+	(text "nBLANK" (rect 2394 24 2435 36)(font "Arial" ))
 	(pt 2464 40)
 	(pt 2384 40)
 )
 (connector
-	(text "nBLANK" (rect 2394 40 2448 55)(font "Arial" ))
+	(text "nBLANK" (rect 2394 40 2435 52)(font "Arial" ))
 	(pt 2464 56)
 	(pt 2384 56)
 )
@@ -5292,7 +4884,7 @@ applicable agreement for further details.
 	(pt 2712 40)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1826 -48 1901 -33)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1826 -48 1882 -36)(font "Arial" ))
 	(pt 1816 -32)
 	(pt 1896 -32)
 )
@@ -5301,12 +4893,12 @@ applicable agreement for further details.
 	(pt 2136 -64)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1682 232 1757 247)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1682 232 1738 244)(font "Arial" ))
 	(pt 1744 248)
 	(pt 1672 248)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2394 184 2469 199)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2394 184 2450 196)(font "Arial" ))
 	(pt 2384 200)
 	(pt 2464 200)
 )
@@ -5339,25 +4931,10 @@ applicable agreement for further details.
 	(pt 2440 160)
 )
 (connector
-	(text "nFB_CS3" (rect 1170 3128 1232 3143)(font "Arial" ))
+	(text "nFB_CS3" (rect 1170 3128 1217 3140)(font "Arial" ))
 	(pt 1264 3144)
 	(pt 1160 3144)
 )
-(connector
-	(text "nBLANK" (rect 1154 1968 1208 1983)(font "Arial" ))
-	(pt 1264 1984)
-	(pt 1144 1984)
-)
-(connector
-	(text "DSP_INT" (rect 1154 1944 1214 1959)(font "Arial" ))
-	(pt 1264 1960)
-	(pt 1144 1960)
-)
-(connector
-	(text "STEP_DIR" (rect 1682 1752 1751 1767)(font "Arial" ))
-	(pt 1672 1768)
-	(pt 1856 1768)
-)
 (connector
 	(pt 1904 1768)
 	(pt 2136 1768)
@@ -5367,129 +4944,52 @@ applicable agreement for further details.
 	(pt 2136 1816)
 )
 (connector
-	(text "WR_DATA" (rect 1682 1800 1749 1815)(font "Arial" ))
-	(pt 1672 1816)
-	(pt 1856 1816)
-)
-(connector
-	(text "DMA_DRQ" (rect 1130 2856 1199 2871)(font "Arial" ))
+	(text "DMA_DRQ" (rect 1130 2856 1184 2868)(font "Arial" ))
 	(pt 1264 2872)
 	(pt 1120 2872)
 )
-(connector
-	(text "DMA_DRQ" (rect 1682 2096 1751 2111)(font "Arial" ))
-	(pt 1784 2112)
-	(pt 1672 2112)
-)
-(connector
-	(text "FDC_CLK" (rect 1202 880 1268 895)(font "Arial" ))
-	(pt 1192 896)
-	(pt 1264 896)
-)
-(connector
-	(text "MOT_ON" (rect 1626 1728 1685 1743)(font "Arial" ))
-	(pt 1672 1744)
-	(pt 1800 1744)
-)
 (connector
 	(pt 1848 1744)
 	(pt 2136 1744)
 )
-(connector
-	(text "STEP" (rect 1626 1776 1662 1791)(font "Arial" ))
-	(pt 1672 1792)
-	(pt 1800 1792)
-)
 (connector
 	(pt 1848 1792)
 	(pt 2136 1792)
 )
-(connector
-	(text "WR_GATE" (rect 1690 1824 1758 1839)(font "Arial" ))
-	(pt 1672 1840)
-	(pt 1800 1840)
-)
 (connector
 	(pt 1848 1840)
 	(pt 2136 1840)
 )
 (connector
-	(text "FB_ALE" (rect 1186 1992 1237 2007)(font "Arial" ))
-	(pt 1144 2008)
-	(pt 1264 2008)
-)
-(connector
-	(text "AMKB_TX" (rect 1946 1392 2008 1407)(font "Arial" ))
-	(pt 1672 1408)
-	(pt 2112 1408)
-)
-(connector
-	(text "PIC_AMKB_RX" (rect 786 1504 882 1519)(font "Arial" ))
-	(pt 776 1520)
-	(pt 1264 1520)
-)
-(connector
-	(pt 400 -16)
-	(pt 440 -16)
-)
-(connector
-	(pt 440 248)
-	(pt 400 248)
-)
-(connector
-	(pt 400 -16)
-	(pt 400 248)
-)
-(connector
-	(pt 400 248)
-	(pt 400 304)
-)
-(connector
-	(text "CLK2M" (rect 754 -32 801 -17)(font "Arial" ))
-	(pt 744 -16)
-	(pt 816 -16)
-)
-(connector
-	(text "FDC_CLK" (rect 754 -8 820 7)(font "Arial" ))
-	(pt 744 8)
-	(pt 816 8)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 370 1352 453 1367)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 370 1352 437 1364)(font "Arial" ))
 	(pt 352 1368)
 	(pt 464 1368)
 	(bus)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 642 1376 736 1391)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 642 1376 717 1388)(font "Arial" ))
 	(pt 608 1392)
 	(pt 760 1392)
 	(bus)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 378 1368 492 1383)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 378 1368 466 1380)(font "Arial" ))
 	(pt 368 1384)
 	(pt 464 1384)
 )
 (connector
-	(text "FB_ALE" (rect 386 1384 437 1399)(font "Arial" ))
+	(text "FB_ALE" (rect 386 1384 426 1396)(font "Arial" ))
 	(pt 376 1400)
 	(pt 464 1400)
 )
 (connector
-	(text "ACP_CONF[31..0]" (rect 1682 2568 1797 2583)(font "Arial" ))
+	(text "ACP_CONF[31..0]" (rect 1682 2568 1774 2580)(font "Arial" ))
 	(pt 1672 2584)
 	(pt 1832 2584)
 	(bus)
 )
 (connector
-	(text "ACP_CONF[31..24]" (rect 1146 2064 1269 2079)(font "Arial" ))
-	(pt 1136 2080)
-	(pt 1264 2080)
-	(bus)
-)
-(connector
-	(text "TIN0" (rect 1682 2624 1712 2639)(font "Arial" ))
+	(text "TIN0" (rect 1682 2624 1705 2636)(font "Arial" ))
 	(pt 1832 2640)
 	(pt 1672 2640)
 )
@@ -5514,42 +5014,27 @@ applicable agreement for further details.
 	(pt 2424 -64)
 )
 (connector
-	(text "HD_DD" (rect 1050 1616 1100 1631)(font "Arial" ))
-	(pt 1040 1632)
-	(pt 1264 1632)
-)
-(connector
-	(text "CLK48M" (rect 754 40 809 55)(font "Arial" ))
-	(pt 744 56)
-	(pt 840 56)
-)
-(connector
-	(text "CLK25M" (rect 754 16 809 31)(font "Arial" ))
-	(pt 744 32)
-	(pt 864 32)
-)
-(connector
-	(text "DDRCLK[0]" (rect 762 -296 837 -281)(font "Arial" ))
+	(text "DDRCLK[0]" (rect 762 -296 821 -284)(font "Arial" ))
 	(pt 752 -280)
 	(pt 848 -280)
 )
 (connector
-	(text "DDRCLK[1]" (rect 762 -272 837 -257)(font "Arial" ))
+	(text "DDRCLK[1]" (rect 762 -272 821 -260)(font "Arial" ))
 	(pt 752 -256)
 	(pt 848 -256)
 )
 (connector
-	(text "DDRCLK[2]" (rect 762 -248 837 -233)(font "Arial" ))
+	(text "DDRCLK[2]" (rect 762 -248 821 -236)(font "Arial" ))
 	(pt 752 -232)
 	(pt 848 -232)
 )
 (connector
-	(text "DDRCLK[3]" (rect 762 -224 837 -209)(font "Arial" ))
+	(text "DDRCLK[3]" (rect 762 -224 821 -212)(font "Arial" ))
 	(pt 752 -208)
 	(pt 848 -208)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 762 -200 876 -185)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 762 -200 850 -188)(font "Arial" ))
 	(pt 752 -184)
 	(pt 848 -184)
 )
@@ -5558,15 +5043,10 @@ applicable agreement for further details.
 	(pt 472 672)
 )
 (connector
-	(text "VIDEO_RECONFIG" (rect 74 496 199 511)(font "Arial" ))
+	(text "VIDEO_RECONFIG" (rect 74 496 173 508)(font "Arial" ))
 	(pt 192 512)
 	(pt 64 512)
 )
-(connector
-	(text "MAIN_CLK" (rect 330 -296 399 -281)(font "Arial" ))
-	(pt 264 -280)
-	(pt 448 -280)
-)
 (connector
 	(pt 408 640)
 	(pt 472 640)
@@ -5576,13 +5056,13 @@ applicable agreement for further details.
 	(pt 512 624)
 )
 (connector
-	(text "VR_D[8..0]" (rect 418 552 486 567)(font "Arial" ))
+	(text "VR_D[8..0]" (rect 418 552 473 564)(font "Arial" ))
 	(pt 496 568)
 	(pt 408 568)
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 122 664 191 679)(font "Arial" ))
+	(text "MAIN_CLK" (rect 122 664 176 676)(font "Arial" ))
 	(pt 112 680)
 	(pt 192 680)
 )
@@ -5643,7 +5123,7 @@ applicable agreement for further details.
 	(pt 1064 616)
 )
 (connector
-	(text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" ))
+	(text "FB_ADR[5..2]" (rect 82 568 151 580)(font "Arial" ))
 	(pt 192 584)
 	(pt 72 584)
 	(bus)
@@ -5673,29 +5153,29 @@ applicable agreement for further details.
 	(pt 72 816)
 )
 (connector
-	(text "FB_ADR[8..6]" (rect 82 584 168 599)(font "Arial" ))
+	(text "FB_ADR[8..6]" (rect 82 584 151 596)(font "Arial" ))
 	(pt 192 600)
 	(pt 72 600)
 	(bus)
 )
 (connector
-	(text "VR_RD" (rect 98 512 146 527)(font "Arial" ))
+	(text "VR_RD" (rect 98 512 135 524)(font "Arial" ))
 	(pt 64 528)
 	(pt 192 528)
 )
 (connector
-	(text "VR_WR" (rect 98 528 148 543)(font "Arial" ))
+	(text "VR_WR" (rect 98 528 138 540)(font "Arial" ))
 	(pt 64 544)
 	(pt 192 544)
 )
 (connector
-	(text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" ))
+	(text "VR_D[8..0]" (rect 1170 464 1225 476)(font "Arial" ))
 	(pt 1144 480)
 	(pt 1264 480)
 	(bus)
 )
 (connector
-	(text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" ))
+	(text "VDQS[3..0]" (rect 1674 504 1730 516)(font "Arial" ))
 	(pt 2040 544)
 	(pt 1960 544)
 	(bus)
@@ -5711,7 +5191,7 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" ))
+	(text "VDM[3..0]" (rect 1682 528 1731 540)(font "Arial" ))
 	(pt 1944 568)
 	(pt 1888 568)
 	(bus)
@@ -5727,32 +5207,32 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" ))
+	(text "VIDEO_RECONFIG" (rect 1674 560 1773 572)(font "Arial" ))
 	(pt 1672 576)
 	(pt 1792 576)
 )
 (connector
-	(text "VR_WR" (rect 1698 592 1748 607)(font "Arial" ))
+	(text "VR_WR" (rect 1698 592 1738 604)(font "Arial" ))
 	(pt 1672 608)
 	(pt 1792 608)
 )
 (connector
-	(text "VR_BUSY" (rect 418 496 482 511)(font "Arial" ))
+	(text "VR_BUSY" (rect 418 496 469 508)(font "Arial" ))
 	(pt 408 512)
 	(pt 480 512)
 )
 (connector
-	(text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" ))
+	(text "VR_BUSY" (rect 1170 448 1221 460)(font "Arial" ))
 	(pt 1144 464)
 	(pt 1264 464)
 )
 (connector
-	(text "VR_RD" (rect 1698 576 1746 591)(font "Arial" ))
+	(text "VR_RD" (rect 1698 576 1735 588)(font "Arial" ))
 	(pt 1792 592)
 	(pt 1672 592)
 )
 (connector
-	(text "nRSTO" (rect -86 680 -39 695)(font "Arial" ))
+	(text "nRSTO" (rect -86 680 -51 692)(font "Arial" ))
 	(pt -96 696)
 	(pt -16 696)
 )
@@ -5761,64 +5241,28 @@ applicable agreement for further details.
 	(pt 192 696)
 )
 (connector
-	(text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" ))
+	(text "FB_AD[24..16]" (rect 82 552 155 564)(font "Arial" ))
 	(pt 72 568)
 	(pt 192 568)
 	(bus)
 )
 (connector
-	(text "CLK48M" (rect 538 552 593 567)(font "Arial" ))
+	(text "CLK48M" (rect 538 552 579 564)(font "Arial" ))
 	(pt 528 568)
 	(pt 608 568)
 )
 (connector
-	(text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" ))
+	(text "CLK_VIDEO" (rect 1162 552 1223 564)(font "Arial" ))
 	(pt 984 568)
 	(pt 1264 568)
 )
 (connector
-	(text "CLK33M" (rect 1202 584 1257 599)(font "Arial" ))
+	(text "CLK33M" (rect 1202 584 1243 596)(font "Arial" ))
 	(pt 1264 600)
 	(pt 1192 600)
 )
 (connector
-	(text "CLK500k" (rect 802 232 862 247)(font "Arial" ))
-	(pt 768 248)
-	(pt 864 248)
-)
-(connector
-	(text "CLK2M4576" (rect 802 256 882 271)(font "Arial" ))
-	(pt 768 272)
-	(pt 864 272)
-)
-(connector
-	(text "CLK24M576" (rect 802 280 882 295)(font "Arial" ))
-	(pt 768 296)
-	(pt 864 296)
-)
-(connector
-	(text "nRSTO" (rect 1018 424 1065 439)(font "Arial" ))
-	(pt 1008 440)
-	(pt 1096 440)
-)
-(connector
-	(pt 768 320)
-	(pt 872 320)
-)
-(connector
-	(pt 872 432)
-	(pt 944 432)
-)
-(connector
-	(pt 840 448)
-	(pt 944 448)
-)
-(connector
-	(pt 872 320)
-	(pt 872 432)
-)
-(connector
-	(text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" ))
+	(text "HSYNC" (rect 2314 -96 2354 -84)(font "Arial" ))
 	(pt 2304 -80)
 	(pt 2424 -80)
 )
@@ -5827,11 +5271,729 @@ applicable agreement for further details.
 	(pt 2464 -80)
 )
 (connector
-	(text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" ))
+	(text "VSYNC" (rect 1746 -80 1784 -68)(font "Arial" ))
 	(pt 1736 -64)
 	(pt 1856 -64)
 )
+(connector
+	(text "DVI_INT" (rect 858 2632 900 2644)(font "Arial" ))
+	(pt 848 2648)
+	(pt 1264 2648)
+)
+(connector
+	(text "MAIN_CLK" (rect 330 -296 384 -284)(font "Arial" ))
+	(pt 264 -280)
+	(pt 400 -280)
+)
+(connector
+	(pt 400 -280)
+	(pt 448 -280)
+)
+(connector
+	(text "CLK33MDIR" (rect 234 296 295 308)(font "Arial" ))
+	(pt 224 312)
+	(pt 288 312)
+)
+(connector
+	(pt 800 160)
+	(pt 400 160)
+)
+(connector
+	(text "CLK33M" (rect 858 144 899 156)(font "Arial" ))
+	(pt 848 160)
+	(pt 952 160)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 776 1749 788)(font "Arial" ))
+	(pt 1832 792)
+	(pt 1672 792)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 1072 1221 1084)(font "Arial" ))
+	(pt 1112 1088)
+	(pt 1264 1088)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 784 1216 796)(font "Arial" ))
+	(pt 1152 800)
+	(pt 1264 800)
+)
+(connector
+	(text "CLK33M" (rect 1210 760 1251 772)(font "Arial" ))
+	(pt 1200 776)
+	(pt 1264 776)
+)
+(connector
+	(text "CLK2M" (rect 1202 808 1237 820)(font "Arial" ))
+	(pt 1192 824)
+	(pt 1264 824)
+)
+(connector
+	(text "CLK500k" (rect 1202 832 1246 844)(font "Arial" ))
+	(pt 1192 848)
+	(pt 1264 848)
+)
+(connector
+	(text "nRSTO" (rect 1170 1120 1205 1132)(font "Arial" ))
+	(pt 1264 1136)
+	(pt 1160 1136)
+)
+(connector
+	(text "CLK2M4576" (rect 1202 856 1261 868)(font "Arial" ))
+	(pt 1192 872)
+	(pt 1264 872)
+)
+(connector
+	(text "nMFP_INT" (rect 1682 2072 1733 2084)(font "Arial" ))
+	(pt 1672 2088)
+	(pt 1784 2088)
+)
+(connector
+	(text "VSYNC" (rect 1130 1920 1168 1932)(font "Arial" ))
+	(pt 1264 1936)
+	(pt 1120 1936)
+)
+(connector
+	(text "HSYNC" (rect 1130 1896 1170 1908)(font "Arial" ))
+	(pt 1264 1912)
+	(pt 1120 1912)
+)
+(connector
+	(text "nBLANK" (rect 1154 1968 1195 1980)(font "Arial" ))
+	(pt 1264 1984)
+	(pt 1144 1984)
+)
+(connector
+	(text "DSP_INT" (rect 1154 1944 1200 1956)(font "Arial" ))
+	(pt 1264 1960)
+	(pt 1144 1960)
+)
+(connector
+	(text "DMA_DRQ" (rect 1682 2096 1736 2108)(font "Arial" ))
+	(pt 1784 2112)
+	(pt 1672 2112)
+)
+(connector
+	(text "FDC_CLK" (rect 1202 880 1252 892)(font "Arial" ))
+	(pt 1192 896)
+	(pt 1264 896)
+)
+(connector
+	(text "FB_ALE" (rect 1186 1992 1226 2004)(font "Arial" ))
+	(pt 1144 2008)
+	(pt 1264 2008)
+)
+(connector
+	(text "ACP_CONF[31..24]" (rect 1146 2064 1243 2076)(font "Arial" ))
+	(pt 1136 2080)
+	(pt 1264 2080)
+	(bus)
+)
+(connector
+	(text "LP_STR" (rect 1682 824 1722 836)(font "Arial" ))
+	(pt 1672 840)
+	(pt 1832 840)
+)
+(connector
+	(text "LP_DIR" (rect 1682 848 1720 860)(font "Arial" ))
+	(pt 1672 864)
+	(pt 1832 864)
+)
+(connector
+	(text "nACSI_ACK" (rect 1682 928 1742 940)(font "Arial" ))
+	(pt 1672 944)
+	(pt 1832 944)
+)
+(connector
+	(text "nFB_WR" (rect 1170 928 1214 940)(font "Arial" ))
+	(pt 1160 944)
+	(pt 1264 944)
+)
+(connector
+	(text "nACSI_RESET" (rect 1682 952 1755 964)(font "Arial" ))
+	(pt 1672 968)
+	(pt 1832 968)
+)
+(connector
+	(text "nFB_CS1" (rect 1162 952 1209 964)(font "Arial" ))
+	(pt 1160 968)
+	(pt 1264 968)
+)
+(connector
+	(text "nACSI_CS" (rect 1682 976 1735 988)(font "Arial" ))
+	(pt 1672 992)
+	(pt 1832 992)
+)
+(connector
+	(text "nFB_CS2" (rect 1170 976 1217 988)(font "Arial" ))
+	(pt 1160 992)
+	(pt 1264 992)
+)
+(connector
+	(text "ACSI_DIR" (rect 1682 1000 1733 1012)(font "Arial" ))
+	(pt 1672 1016)
+	(pt 1832 1016)
+)
+(connector
+	(text "FB_SIZE0" (rect 1162 1000 1212 1012)(font "Arial" ))
+	(pt 1160 1016)
+	(pt 1264 1016)
+)
+(connector
+	(text "ACSI_A1" (rect 1682 1024 1726 1036)(font "Arial" ))
+	(pt 1672 1040)
+	(pt 1832 1040)
+)
+(connector
+	(text "FB_SIZE1" (rect 1162 1024 1212 1036)(font "Arial" ))
+	(pt 1160 1040)
+	(pt 1264 1040)
+)
+(connector
+	(text "nFB_BURST" (rect 1162 1048 1224 1060)(font "Arial" ))
+	(pt 1160 1064)
+	(pt 1264 1064)
+)
+(connector
+	(text "SCSI_PAR" (rect 1682 1080 1736 1092)(font "Arial" ))
+	(pt 1672 1096)
+	(pt 1840 1096)
+)
+(connector
+	(text "nDACK0" (rect 1202 1096 1244 1108)(font "Arial" ))
+	(pt 1160 1112)
+	(pt 1264 1112)
+)
+(connector
+	(text "nSCSI_ACK" (rect 1682 1104 1742 1116)(font "Arial" ))
+	(pt 1672 1120)
+	(pt 1840 1120)
+)
+(connector
+	(text "nSCSI_ATN" (rect 1682 1128 1741 1140)(font "Arial" ))
+	(pt 1672 1144)
+	(pt 1840 1144)
+)
+(connector
+	(text "SCSI_DIR" (rect 1682 1152 1733 1164)(font "Arial" ))
+	(pt 1672 1168)
+	(pt 1840 1168)
+)
+(connector
+	(text "LP_BUSY" (rect 1114 1160 1163 1172)(font "Arial" ))
+	(pt 1104 1176)
+	(pt 1264 1176)
+)
+(connector
+	(text "nSCSI_RST" (rect 1682 1176 1741 1188)(font "Arial" ))
+	(pt 1672 1192)
+	(pt 1840 1192)
+)
+(connector
+	(text "nACSI_DRQ" (rect 1034 1192 1096 1204)(font "Arial" ))
+	(pt 1024 1208)
+	(pt 1264 1208)
+)
+(connector
+	(text "nSCSI_SEL" (rect 1680 1200 1737 1212)(font "Arial" ))
+	(pt 1672 1216)
+	(pt 1840 1216)
+)
+(connector
+	(text "nACSI_INT" (rect 1034 1216 1089 1228)(font "Arial" ))
+	(pt 1024 1232)
+	(pt 1264 1232)
+)
+(connector
+	(text "nSCSI_BUSY" (rect 1682 1224 1750 1236)(font "Arial" ))
+	(pt 1672 1240)
+	(pt 1840 1240)
+)
+(connector
+	(text "nSCSI_DRQ" (rect 1114 1248 1176 1260)(font "Arial" ))
+	(pt 1104 1264)
+	(pt 1264 1264)
+)
+(connector
+	(text "nSCSI_C_D" (rect 1114 1272 1174 1284)(font "Arial" ))
+	(pt 1104 1288)
+	(pt 1264 1288)
+)
+(connector
+	(text "nSCSI_I_O" (rect 1114 1296 1169 1308)(font "Arial" ))
+	(pt 1104 1312)
+	(pt 1264 1312)
+)
+(connector
+	(text "TxD" (rect 1682 1312 1702 1324)(font "Arial" ))
+	(pt 1672 1328)
+	(pt 1840 1328)
+)
+(connector
+	(text "nSCSI_MSG" (rect 1114 1320 1175 1332)(font "Arial" ))
+	(pt 1104 1336)
+	(pt 1264 1336)
+)
+(connector
+	(text "RTS" (rect 1682 1336 1703 1348)(font "Arial" ))
+	(pt 1672 1352)
+	(pt 1840 1352)
+)
+(connector
+	(text "DTR" (rect 1680 1360 1702 1372)(font "Arial" ))
+	(pt 1672 1376)
+	(pt 1848 1376)
+)
+(connector
+	(text "RxD" (rect 1114 1384 1136 1396)(font "Arial" ))
+	(pt 1104 1400)
+	(pt 1264 1400)
+)
+(connector
+	(text "AMKB_TX" (rect 1946 1392 1993 1404)(font "Arial" ))
+	(pt 1672 1408)
+	(pt 2112 1408)
+)
+(connector
+	(text "CTS" (rect 1114 1408 1135 1420)(font "Arial" ))
+	(pt 1104 1424)
+	(pt 1264 1424)
+)
+(connector
+	(text "IDE_RES" (rect 1682 1424 1729 1436)(font "Arial" ))
+	(pt 1672 1440)
+	(pt 1848 1440)
+)
+(connector
+	(text "RI" (rect 1114 1432 1125 1444)(font "Arial" ))
+	(pt 1104 1448)
+	(pt 1264 1448)
+)
+(connector
+	(text "nIDE_CS0" (rect 1682 1448 1733 1460)(font "Arial" ))
+	(pt 1672 1464)
+	(pt 1848 1464)
+)
+(connector
+	(text "DCD" (rect 1114 1456 1138 1468)(font "Arial" ))
+	(pt 1104 1472)
+	(pt 1264 1472)
+)
+(connector
+	(text "nIDE_CS1" (rect 1682 1472 1733 1484)(font "Arial" ))
+	(pt 1672 1488)
+	(pt 1856 1488)
+)
+(connector
+	(text "nIDE_WR" (rect 1682 1496 1731 1508)(font "Arial" ))
+	(pt 1672 1512)
+	(pt 1848 1512)
+)
+(connector
+	(text "PIC_AMKB_RX" (rect 786 1504 860 1516)(font "Arial" ))
+	(pt 776 1520)
+	(pt 1264 1520)
+)
+(connector
+	(text "nIDE_RD" (rect 1682 1520 1729 1532)(font "Arial" ))
+	(pt 1672 1536)
+	(pt 1848 1536)
+)
+(connector
+	(text "IDE_RDY" (rect 1114 1536 1163 1548)(font "Arial" ))
+	(pt 1104 1552)
+	(pt 1264 1552)
+)
+(connector
+	(text "nCF_CS0" (rect 1682 1544 1730 1556)(font "Arial" ))
+	(pt 1672 1560)
+	(pt 1848 1560)
+)
+(connector
+	(text "IDE_INT" (rect 1114 1560 1156 1572)(font "Arial" ))
+	(pt 1104 1576)
+	(pt 1264 1576)
+)
+(connector
+	(text "nCF_CS1" (rect 1682 1568 1730 1580)(font "Arial" ))
+	(pt 1672 1584)
+	(pt 1848 1584)
+)
+(connector
+	(text "WP_CF_CARD" (rect 1112 1584 1188 1596)(font "Arial" ))
+	(pt 1104 1600)
+	(pt 1264 1600)
+)
+(connector
+	(text "nROM3" (rect 1754 1600 1790 1612)(font "Arial" ))
+	(pt 1672 1616)
+	(pt 1920 1616)
+)
+(connector
+	(text "nROM4" (rect 1754 1624 1790 1636)(font "Arial" ))
+	(pt 1672 1640)
+	(pt 1920 1640)
+)
+(connector
+	(text "nINDEX" (rect 1050 1640 1088 1652)(font "Arial" ))
+	(pt 1040 1656)
+	(pt 1264 1656)
+)
+(connector
+	(text "nRP_UDS" (rect 1744 1648 1794 1660)(font "Arial" ))
+	(pt 1672 1664)
+	(pt 1920 1664)
+)
+(connector
+	(text "TRACK00" (rect 1050 1664 1098 1676)(font "Arial" ))
+	(pt 1040 1680)
+	(pt 1264 1680)
+)
+(connector
+	(text "nRP_LDS" (rect 1746 1672 1794 1684)(font "Arial" ))
+	(pt 1672 1688)
+	(pt 1920 1688)
+)
+(connector
+	(text "nWP" (rect 1050 1688 1073 1700)(font "Arial" ))
+	(pt 1040 1704)
+	(pt 1264 1704)
+)
+(connector
+	(text "DSA_D" (rect 1682 1704 1718 1716)(font "Arial" ))
+	(pt 1672 1720)
+	(pt 1856 1720)
+)
+(connector
+	(text "nRD_DATA" (rect 1050 1712 1106 1724)(font "Arial" ))
+	(pt 1040 1728)
+	(pt 1264 1728)
+)
+(connector
+	(text "nDCHG" (rect 1050 1736 1088 1748)(font "Arial" ))
+	(pt 1040 1752)
+	(pt 1264 1752)
+)
+(connector
+	(text "SD_DATA0" (rect 1114 1768 1169 1780)(font "Arial" ))
+	(pt 1104 1784)
+	(pt 1264 1784)
+)
+(connector
+	(text "SD_DATA1" (rect 1114 1792 1169 1804)(font "Arial" ))
+	(pt 1104 1808)
+	(pt 1264 1808)
+)
+(connector
+	(text "SD_DATA2" (rect 1114 1816 1169 1828)(font "Arial" ))
+	(pt 1104 1832)
+	(pt 1264 1832)
+)
+(connector
+	(text "WR_GATE" (rect 1690 1824 1743 1836)(font "Arial" ))
+	(pt 1672 1840)
+	(pt 1800 1840)
+)
+(connector
+	(text "SD_CARD_DEDECT" (rect 1138 1840 1241 1852)(font "Arial" ))
+	(pt 1128 1856)
+	(pt 1264 1856)
+)
+(connector
+	(text "nSDSEL" (rect 1682 1848 1723 1860)(font "Arial" ))
+	(pt 1672 1864)
+	(pt 1856 1864)
+)
+(connector
+	(text "SD_WP" (rect 1114 1864 1152 1876)(font "Arial" ))
+	(pt 1104 1880)
+	(pt 1264 1880)
+)
+(connector
+	(text "YM_QA" (rect 1762 1904 1799 1916)(font "Arial" ))
+	(pt 1672 1920)
+	(pt 1928 1920)
+)
+(connector
+	(text "YM_QB" (rect 1762 1928 1799 1940)(font "Arial" ))
+	(pt 1672 1944)
+	(pt 1928 1944)
+)
+(connector
+	(text "YM_QC" (rect 1762 1952 1800 1964)(font "Arial" ))
+	(pt 1672 1968)
+	(pt 1928 1968)
+)
+(connector
+	(text "SD_CD_DATA3" (rect 1682 1984 1759 1996)(font "Arial" ))
+	(pt 1672 2000)
+	(pt 1856 2000)
+)
+(connector
+	(text "SD_CDM_D1" (rect 1682 2008 1748 2020)(font "Arial" ))
+	(pt 1672 2024)
+	(pt 1856 2024)
+)
+(connector
+	(text "SD_CLK" (rect 1682 2032 1724 2044)(font "Arial" ))
+	(pt 1672 2048)
+	(pt 1856 2048)
+)
+(connector
+	(text "nFB_OE" (rect 1170 904 1211 916)(font "Arial" ))
+	(pt 1160 920)
+	(pt 1264 920)
+)
+(connector
+	(text "LP_D[7..0]" (rect 1810 800 1863 812)(font "Arial" ))
+	(pt 1672 816)
+	(pt 1960 816)
+	(bus)
+)
+(connector
+	(text "ACSI_D[7..0]" (rect 1754 880 1820 892)(font "Arial" ))
+	(pt 1672 896)
+	(pt 1904 896)
+	(bus)
+)
+(connector
+	(text "SCSI_D[7..0]" (rect 1786 1056 1852 1068)(font "Arial" ))
+	(pt 1672 1072)
+	(pt 1936 1072)
+	(bus)
+)
+(connector
+	(text "AMKB_RX" (rect 786 1480 835 1492)(font "Arial" ))
+	(pt 776 1496)
+	(pt 1264 1496)
+)
+(connector
+	(text "FALCON_IO_TA" (rect 1682 744 1763 756)(font "Arial" ))
+	(pt 1672 760)
+	(pt 1880 760)
+)
+(connector
+	(text "STEP_DIR" (rect 1682 1752 1735 1764)(font "Arial" ))
+	(pt 1672 1768)
+	(pt 1856 1768)
+)
+(connector
+	(text "WR_DATA" (rect 1682 1800 1735 1812)(font "Arial" ))
+	(pt 1672 1816)
+	(pt 1856 1816)
+)
+(connector
+	(text "MOT_ON" (rect 1626 1728 1670 1740)(font "Arial" ))
+	(pt 1672 1744)
+	(pt 1800 1744)
+)
+(connector
+	(text "STEP" (rect 1626 1776 1653 1788)(font "Arial" ))
+	(pt 1672 1792)
+	(pt 1800 1792)
+)
+(connector
+	(text "HD_DD" (rect 1050 1616 1088 1628)(font "Arial" ))
+	(pt 1040 1632)
+	(pt 1264 1632)
+)
+(connector
+	(pt 400 248)
+	(pt 440 248)
+)
+(connector
+	(pt 400 160)
+	(pt 400 248)
+)
+(connector
+	(text "nRSTO" (rect 1026 424 1061 436)(font "Arial" ))
+	(pt 1016 440)
+	(pt 1104 440)
+)
+(connector
+	(pt 920 432)
+	(pt 952 432)
+)
+(connector
+	(pt 760 448)
+	(pt 952 448)
+)
+(connector
+	(pt 824 440)
+	(pt 952 440)
+)
+(connector
+	(pt 1120 328)
+	(pt 920 328)
+)
+(connector
+	(pt 920 328)
+	(pt 920 432)
+)
+(connector
+	(pt 1888 2192)
+	(pt 1888 2176)
+)
+(connector
+	(pt 1848 2176)
+	(pt 1888 2176)
+)
+(connector
+	(pt 1848 2176)
+	(pt 1848 2208)
+)
+(connector
+	(pt 1848 2208)
+	(pt 1864 2208)
+)
+(connector
+	(text "CLK2M" (rect 1778 2192 1813 2204)(font "Arial" ))
+	(pt 1768 2208)
+	(pt 1848 2208)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 2552 1221 2564)(font "Arial" ))
+	(pt 1112 2568)
+	(pt 1264 2568)
+	(bus)
+)
+(connector
+	(text "nFB_WR" (rect 1162 2432 1206 2444)(font "Arial" ))
+	(pt 1152 2448)
+	(pt 1264 2448)
+)
+(connector
+	(text "nFB_CS1" (rect 1154 2456 1201 2468)(font "Arial" ))
+	(pt 1152 2472)
+	(pt 1264 2472)
+)
+(connector
+	(text "FB_SIZE0" (rect 1154 2504 1204 2516)(font "Arial" ))
+	(pt 1152 2520)
+	(pt 1264 2520)
+)
+(connector
+	(text "FB_SIZE1" (rect 1154 2528 1204 2540)(font "Arial" ))
+	(pt 1152 2544)
+	(pt 1264 2544)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 2384 1216 2396)(font "Arial" ))
+	(pt 1152 2400)
+	(pt 1264 2400)
+)
+(connector
+	(text "nFB_CS2" (rect 1162 2480 1209 2492)(font "Arial" ))
+	(pt 1152 2496)
+	(pt 1264 2496)
+)
+(connector
+	(text "nFB_OE" (rect 1170 2408 1211 2420)(font "Arial" ))
+	(pt 1264 2424)
+	(pt 1160 2424)
+)
+(connector
+	(text "nRSTO" (rect 1170 2360 1205 2372)(font "Arial" ))
+	(pt 1264 2376)
+	(pt 1160 2376)
+)
+(connector
+	(pt 1912 2208)
+	(pt 1960 2208)
+)
+(connector
+	(text "MIDI_IN" (rect 1682 2208 1723 2220)(font "Arial" ))
+	(pt 1672 2224)
+	(pt 1864 2224)
+)
+(connector
+	(text "nDREQ0" (rect 1674 2120 1717 2132)(font "Arial" ))
+	(pt 1672 2136)
+	(pt 1800 2136)
+)
+(connector
+	(text "MIDI_OLR" (rect 1682 2272 1733 2284)(font "Arial" ))
+	(pt 1672 2288)
+	(pt 1920 2288)
+)
+(connector
+	(text "MIDI_TLR" (rect 1682 2232 1731 2244)(font "Arial" ))
+	(pt 1672 2248)
+	(pt 1832 2248)
+)
+(connector
+	(pt 824 440)
+	(pt 824 296)
+)
+(connector
+	(pt 824 296)
+	(pt 712 296)
+)
+(connector
+	(pt 376 -16)
+	(pt 368 -16)
+)
+(connector
+	(pt 1120 328)
+	(pt 1120 48)
+)
+(connector
+	(pt 400 -16)
+	(pt 464 -16)
+)
+(connector
+	(pt 400 -280)
+	(pt 400 -16)
+)
+(connector
+	(pt 400 -16)
+	(pt 400 160)
+)
+(connector
+	(pt 736 48)
+	(pt 1120 48)
+)
+(connector
+	(text "CLK25M" (rect 802 -32 843 -20)(font "Arial" ))
+	(pt 736 -16)
+	(pt 920 -16)
+)
+(connector
+	(text "CLK2M" (rect 810 -8 845 4)(font "Arial" ))
+	(pt 736 0)
+	(pt 808 0)
+)
+(connector
+	(text "CLK500k" (rect 834 8 878 20)(font "Arial" ))
+	(pt 736 16)
+	(pt 832 16)
+)
+(connector
+	(text "CLK2M4576" (rect 810 24 869 36)(font "Arial" ))
+	(pt 736 32)
+	(pt 808 32)
+)
+(connector
+	(text "CLK48M" (rect 722 232 763 244)(font "Arial" ))
+	(pt 712 248)
+	(pt 808 248)
+)
+(connector
+	(text "FDC_CLK" (rect 786 256 836 268)(font "Arial" ))
+	(pt 712 264)
+	(pt 784 264)
+)
+(connector
+	(text "CLK24M576" (rect 722 272 781 284)(font "Arial" ))
+	(pt 816 280)
+	(pt 712 280)
+)
 (junction (pt 2504 760))
-(junction (pt 400 248))
 (junction (pt 1856 -64))
 (junction (pt 2424 -80))
+(junction (pt 400 -280))
+(junction (pt 400 160))
+(junction (pt 1848 2208))
+(junction (pt 400 -16))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index 1674c93..edfa2a3 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Wed Dec 15 02:25:24 2010
+Fri Aug 28 13:39:52 2015
diff --git a/FPGA_by_Fredi/firebee1.fit.rpt b/FPGA_by_Fredi/firebee1.fit.rpt
deleted file mode 100644
index e3df129..0000000
--- a/FPGA_by_Fredi/firebee1.fit.rpt
+++ /dev/null
@@ -1,6866 +0,0 @@
-Fitter report for firebee1
-Wed Dec 15 02:25:03 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Fitter Summary
-  3. Fitter Settings
-  4. Parallel Compilation
-  5. I/O Assignment Warnings
-  6. Fitter Netlist Optimizations
-  7. Ignored Assignments
-  8. Incremental Compilation Preservation Summary
-  9. Incremental Compilation Partition Settings
- 10. Incremental Compilation Placement Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. Input Pins
- 14. Output Pins
- 15. Bidir Pins
- 16. Dual Purpose and Dedicated Pins
- 17. I/O Bank Usage
- 18. All Package Pins
- 19. PLL Summary
- 20. PLL Usage
- 21. Output Pin Default Load For Reported TCO
- 22. Fitter Resource Utilization by Entity
- 23. Delay Chain Summary
- 24. Pad To Core Delay Chain Fanout
- 25. Control Signals
- 26. Global & Other Fast Signals
- 27. Non-Global High Fan-Out Signals
- 28. Fitter RAM Summary
- 29. Fitter DSP Block Usage Summary
- 30. DSP Block Details
- 31. Interconnect Usage Summary
- 32. LAB Logic Elements
- 33. LAB-wide Signals
- 34. LAB Signals Sourced
- 35. LAB Signals Sourced Out
- 36. LAB Distinct Inputs
- 37. I/O Rules Summary
- 38. I/O Rules Details
- 39. I/O Rules Matrix
- 40. Fitter Device Options
- 41. Operating Settings and Conditions
- 42. Estimated Delay Added for Hold Timing
- 43. Fitter Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary                                                                    ;
-+------------------------------------+----------------------------------------------+
-; Fitter Status                      ; Successful - Wed Dec 15 02:25:02 2010        ;
-; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
-; Revision Name                      ; firebee1                                     ;
-; Top-level Entity Name              ; firebee1                                     ;
-; Family                             ; Cyclone III                                  ;
-; Device                             ; EP3C40F484C6                                 ;
-; Timing Models                      ; Final                                        ;
-; Total logic elements               ; 9,526 / 39,600 ( 24 % )                      ;
-;     Total combinational functions  ; 8,061 / 39,600 ( 20 % )                      ;
-;     Dedicated logic registers      ; 4,563 / 39,600 ( 12 % )                      ;
-; Total registers                    ; 4749                                         ;
-; Total pins                         ; 295 / 332 ( 89 % )                           ;
-; Total virtual pins                 ; 0                                            ;
-; Total memory bits                  ; 109,344 / 1,161,216 ( 9 % )                  ;
-; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % )                              ;
-; Total PLLs                         ; 4 / 4 ( 100 % )                              ;
-+------------------------------------+----------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings                                                                                                                                            ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option                                                                     ; Setting                               ; Default Value                         ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device                                                                     ; EP3C40F484C6                          ;                                       ;
-; Use TimeQuest Timing Analyzer                                              ; Off                                   ; On                                    ;
-; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
-; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
-; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
-; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
-; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
-; Perform Physical Synthesis for Combinational Logic for Fitting             ; On                                    ; Off                                   ;
-; Perform Physical Synthesis for Combinational Logic for Performance         ; On                                    ; Off                                   ;
-; Perform Register Duplication for Performance                               ; On                                    ; Off                                   ;
-; Physical Synthesis Effort Level                                            ; Fast                                  ; Normal                                ;
-; Use smart compilation                                                      ; Off                                   ; Off                                   ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
-; Enable compact report table                                                ; Off                                   ; Off                                   ;
-; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
-; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
-; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
-; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
-; Optimize Multi-Corner Timing                                               ; Off                                   ; Off                                   ;
-; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
-; SSN Optimization                                                           ; Off                                   ; Off                                   ;
-; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
-; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
-; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
-; Optimize IOC Register Placement for Timing                                 ; On                                    ; On                                    ;
-; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
-; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
-; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
-; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
-; PCI I/O                                                                    ; Off                                   ; Off                                   ;
-; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
-; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
-; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
-; Auto Delay Chains                                                          ; On                                    ; On                                    ;
-; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
-; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
-; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
-; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
-; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
-; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
-; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
-; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
-; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
-; Auto Global Clock                                                          ; On                                    ; On                                    ;
-; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
-; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Stop After Congestion Map Generation                                       ; Off                                   ; Off                                   ;
-; Save Intermediate Fitting Results                                          ; Off                                   ; Off                                   ;
-; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
-; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
-; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
-; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
-; Use Best Effort Settings for Compilation                                   ; Off                                   ; Off                                   ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+------------------------------------------------------+
-; I/O Assignment Warnings                              ;
-+---------------+--------------------------------------+
-; Pin Name      ; Reason                               ;
-+---------------+--------------------------------------+
-; LP_STR        ; Missing drive strength               ;
-; nACSI_ACK     ; Missing drive strength               ;
-; nACSI_RESET   ; Missing drive strength               ;
-; nACSI_CS      ; Missing drive strength               ;
-; ACSI_DIR      ; Missing drive strength               ;
-; ACSI_A1       ; Missing drive strength               ;
-; nSCSI_ACK     ; Missing drive strength               ;
-; nSCSI_ATN     ; Missing drive strength               ;
-; SCSI_DIR      ; Missing drive strength               ;
-; MIDI_OLR      ; Missing drive strength               ;
-; MIDI_TLR      ; Missing drive strength               ;
-; TxD           ; Missing drive strength               ;
-; RTS           ; Missing drive strength               ;
-; DTR           ; Missing drive strength               ;
-; IDE_RES       ; Missing drive strength               ;
-; nIDE_CS0      ; Missing drive strength               ;
-; nIDE_CS1      ; Missing drive strength               ;
-; nIDE_WR       ; Missing drive strength               ;
-; nIDE_RD       ; Missing drive strength               ;
-; nCF_CS0       ; Missing drive strength               ;
-; nCF_CS1       ; Missing drive strength               ;
-; nROM3         ; Missing drive strength               ;
-; nROM4         ; Missing drive strength               ;
-; nRP_UDS       ; Missing drive strength               ;
-; nRP_LDS       ; Missing drive strength               ;
-; nSDSEL        ; Missing drive strength               ;
-; nWR_GATE      ; Missing drive strength               ;
-; nWR           ; Missing drive strength               ;
-; YM_QA         ; Missing drive strength               ;
-; YM_QB         ; Missing drive strength               ;
-; YM_QC         ; Missing drive strength               ;
-; SD_CLK        ; Missing drive strength               ;
-; DSA_D         ; Missing drive strength               ;
-; nVWE          ; Missing slew rate                    ;
-; nVCAS         ; Missing slew rate                    ;
-; nVRAS         ; Missing slew rate                    ;
-; nVCS          ; Missing slew rate                    ;
-; TIN0          ; Missing drive strength               ;
-; nDREQ1        ; Missing drive strength               ;
-; LED_FPGA_OK   ; Missing slew rate                    ;
-; VCKE          ; Missing slew rate                    ;
-; nFB_TA        ; Missing drive strength               ;
-; nDDR_CLK      ; Missing slew rate                    ;
-; DDR_CLK       ; Missing slew rate                    ;
-; VSYNC_PAD     ; Missing slew rate                    ;
-; HSYNC_PAD     ; Missing slew rate                    ;
-; nBLANK_PAD    ; Missing slew rate                    ;
-; PIXEL_CLK_PAD ; Missing slew rate                    ;
-; nSYNC         ; Missing slew rate                    ;
-; nMOT_ON       ; Missing drive strength               ;
-; nSTEP_DIR     ; Missing drive strength               ;
-; nSTEP         ; Missing drive strength               ;
-; LPDIR         ; Missing drive strength               ;
-; BA[1]         ; Missing slew rate                    ;
-; BA[0]         ; Missing slew rate                    ;
-; nIRQ[7]       ; Missing drive strength               ;
-; nIRQ[6]       ; Missing drive strength               ;
-; nIRQ[5]       ; Missing drive strength               ;
-; nIRQ[4]       ; Missing drive strength and slew rate ;
-; nIRQ[3]       ; Missing drive strength and slew rate ;
-; nIRQ[2]       ; Missing drive strength and slew rate ;
-; VA[12]        ; Missing slew rate                    ;
-; VA[11]        ; Missing slew rate                    ;
-; VA[10]        ; Missing slew rate                    ;
-; VA[9]         ; Missing slew rate                    ;
-; VA[8]         ; Missing slew rate                    ;
-; VA[7]         ; Missing slew rate                    ;
-; VA[6]         ; Missing slew rate                    ;
-; VA[5]         ; Missing slew rate                    ;
-; VA[4]         ; Missing slew rate                    ;
-; VA[3]         ; Missing slew rate                    ;
-; VA[2]         ; Missing slew rate                    ;
-; VA[1]         ; Missing slew rate                    ;
-; VA[0]         ; Missing slew rate                    ;
-; VB[7]         ; Missing slew rate                    ;
-; VB[6]         ; Missing slew rate                    ;
-; VB[5]         ; Missing slew rate                    ;
-; VB[4]         ; Missing slew rate                    ;
-; VB[3]         ; Missing slew rate                    ;
-; VB[2]         ; Missing slew rate                    ;
-; VB[1]         ; Missing slew rate                    ;
-; VB[0]         ; Missing slew rate                    ;
-; VDM[3]        ; Missing slew rate                    ;
-; VDM[2]        ; Missing slew rate                    ;
-; VDM[1]        ; Missing slew rate                    ;
-; VDM[0]        ; Missing slew rate                    ;
-; VG[7]         ; Missing slew rate                    ;
-; VG[6]         ; Missing slew rate                    ;
-; VG[5]         ; Missing slew rate                    ;
-; VG[4]         ; Missing slew rate                    ;
-; VG[3]         ; Missing slew rate                    ;
-; VG[2]         ; Missing slew rate                    ;
-; VG[1]         ; Missing slew rate                    ;
-; VG[0]         ; Missing slew rate                    ;
-; VR[7]         ; Missing slew rate                    ;
-; VR[6]         ; Missing slew rate                    ;
-; VR[5]         ; Missing slew rate                    ;
-; VR[4]         ; Missing slew rate                    ;
-; VR[3]         ; Missing slew rate                    ;
-; VR[2]         ; Missing slew rate                    ;
-; VR[1]         ; Missing slew rate                    ;
-; VR[0]         ; Missing slew rate                    ;
-; VD[31]        ; Missing slew rate                    ;
-; VD[30]        ; Missing slew rate                    ;
-; VD[29]        ; Missing slew rate                    ;
-; VD[28]        ; Missing slew rate                    ;
-; VD[27]        ; Missing slew rate                    ;
-; VD[26]        ; Missing slew rate                    ;
-; VD[25]        ; Missing slew rate                    ;
-; VD[24]        ; Missing slew rate                    ;
-; VD[23]        ; Missing slew rate                    ;
-; VD[22]        ; Missing slew rate                    ;
-; VD[21]        ; Missing slew rate                    ;
-; VD[20]        ; Missing slew rate                    ;
-; VD[19]        ; Missing slew rate                    ;
-; VD[18]        ; Missing slew rate                    ;
-; VD[17]        ; Missing slew rate                    ;
-; VD[16]        ; Missing slew rate                    ;
-; VD[15]        ; Missing slew rate                    ;
-; VD[14]        ; Missing slew rate                    ;
-; VD[13]        ; Missing slew rate                    ;
-; VD[12]        ; Missing slew rate                    ;
-; VD[11]        ; Missing slew rate                    ;
-; VD[10]        ; Missing slew rate                    ;
-; VD[9]         ; Missing slew rate                    ;
-; VD[8]         ; Missing slew rate                    ;
-; VD[7]         ; Missing slew rate                    ;
-; VD[6]         ; Missing slew rate                    ;
-; VD[5]         ; Missing slew rate                    ;
-; VD[4]         ; Missing slew rate                    ;
-; VD[3]         ; Missing slew rate                    ;
-; VD[2]         ; Missing slew rate                    ;
-; VD[1]         ; Missing slew rate                    ;
-; VD[0]         ; Missing slew rate                    ;
-; VDQS[3]       ; Missing slew rate                    ;
-; VDQS[2]       ; Missing slew rate                    ;
-; VDQS[1]       ; Missing slew rate                    ;
-; VDQS[0]       ; Missing slew rate                    ;
-; SCSI_PAR      ; Missing drive strength               ;
-; nSCSI_SEL     ; Missing drive strength               ;
-; nSCSI_BUSY    ; Missing drive strength               ;
-; nSCSI_RST     ; Missing drive strength               ;
-; SD_CD_DATA3   ; Missing drive strength               ;
-; SD_CMD_D1     ; Missing drive strength               ;
-; ACSI_D[7]     ; Missing drive strength               ;
-; ACSI_D[6]     ; Missing drive strength               ;
-; ACSI_D[5]     ; Missing drive strength               ;
-; ACSI_D[4]     ; Missing drive strength               ;
-; ACSI_D[3]     ; Missing drive strength               ;
-; ACSI_D[2]     ; Missing drive strength               ;
-; ACSI_D[1]     ; Missing drive strength               ;
-; ACSI_D[0]     ; Missing drive strength               ;
-; LP_D[7]       ; Missing drive strength               ;
-; LP_D[6]       ; Missing drive strength               ;
-; LP_D[5]       ; Missing drive strength               ;
-; LP_D[4]       ; Missing drive strength               ;
-; LP_D[3]       ; Missing drive strength               ;
-; LP_D[2]       ; Missing drive strength               ;
-; LP_D[1]       ; Missing drive strength               ;
-; LP_D[0]       ; Missing drive strength               ;
-; SCSI_D[7]     ; Missing drive strength               ;
-; SCSI_D[6]     ; Missing drive strength               ;
-; SCSI_D[5]     ; Missing drive strength               ;
-; SCSI_D[4]     ; Missing drive strength               ;
-; SCSI_D[3]     ; Missing drive strength               ;
-; SCSI_D[2]     ; Missing drive strength               ;
-; SCSI_D[1]     ; Missing drive strength               ;
-; SCSI_D[0]     ; Missing drive strength               ;
-+---------------+--------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
-; Node                                                                                                                                                                      ; Action          ; Operation          ; Reason                            ; Node Port ; Node Port Name ; Destination Node                                                                                                                 ; Destination Port ; Destination Port Name ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR~_Duplicate_1 ; Q                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSTEP_DIR~output                                                                                                                 ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                       ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1  ; Q                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nMOT_ON~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                                        ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP                                                      ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSTEP~output                                                                                                                     ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP                                                      ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1  ; Q                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nWR_GATE~output                                                                                                                  ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG                                                        ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In                                             ; Packed Register ; Register Packing   ; PLL Source Synchronous assignment ; Q         ;                ; nRD_DATA~input                                                                                                                   ; O                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nWR~output                                                                                                                       ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSDSEL~output                                                                                                                    ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; DSA_D~output                                                                                                                     ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; RTS~output                                                                                                                       ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; DTR~output                                                                                                                       ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_STR~output                                                                                                                    ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                          ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1                    ; Q                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LPDIR~output                                                                                                                     ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[0]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[1]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[2]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[3]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[4]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[5]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[6]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                          ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; LP_D[7]~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_OUTn                                                     ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nSCSI_BUSY~output                                                                                                                ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0_Duplicate_1                                           ; Q                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; nIDE_RD~output                                                                                                                   ; I                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0SLOAD_MUX                                                                                       ; Created         ; Register Packing   ; Timing optimization               ; COMBOUT   ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                       ; Q                ;                       ;
-; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[3]~output                                                                                                                   ; OE               ;                       ;
-; Video:Fredi_Aschwanden|inst90                                                                                                                                             ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                       ; Q                ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[2]~output                                                                                                                   ; OE               ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                       ; Q                ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[1]~output                                                                                                                   ; OE               ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Duplicated      ; Register Packing   ; Timing optimization               ; Q         ;                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                       ; Q                ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; VDQS[0]~output                                                                                                                   ; OE               ;                       ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                ; Inverted        ; Register Packing   ; Timing optimization               ; Q         ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[28]~input                                                                                                                  ; O                ;                       ;
-; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[29]~input                                                                                                                  ; O                ;                       ;
-; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[30]~input                                                                                                                  ; O                ;                       ;
-; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31]                                                                                                    ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[31]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[0]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[1]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[2]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[3]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[4]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[5]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[6]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[7]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[8]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                             ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[9]~input                                                                                                                   ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[10]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[11]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[12]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[13]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[14]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[15]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[16]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[17]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[18]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[19]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[20]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[21]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[22]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[23]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[24]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[25]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[26]~input                                                                                                                  ; O                ;                       ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                            ; Packed Register ; Register Packing   ; Timing optimization               ; Q         ;                ; FB_AD[27]~input                                                                                                                  ; O                ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0                                                                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0_RESYN24_BDD25                                                                                ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~53                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54_RESYN0_BDD1                                                                                    ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~168                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~177                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~178                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN2_BDD3                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN6_BDD7                                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~368                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369_RESYN18_BDD19                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~358                                                                                               ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN10_BDD11                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN12_BDD13                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_RESYN50_BDD51                                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN16_BDD17                                                                                 ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~0                                                                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~1                                                                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2                                                                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20_BDD21                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22_BDD23                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS                                                                                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS_RESYN56_BDD57                                                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add7~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add8~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT~1                                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~54                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~55                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector96~0                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add2~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~30                                           ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~31                                           ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add0~1                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~2                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]~0                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~0                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~1                                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~16                                           ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_01_STRB~1                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_10_STRB~2                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add1~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add3~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add5~12                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~4                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~17                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~18                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add10~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add11~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_CLK~16                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan6~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan7~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan8~14                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux84~1                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux92~1                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux100~1                                                  ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]~3                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_A[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]~1                            ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~16                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15                                  ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1                                         ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~12                                        ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15                                      ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~162                                                                     ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163                                                                     ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163_RESYN8_BDD9                                                         ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~2                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~2                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~3                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~0                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~2                                                    ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~1                                                    ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~2                                                    ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~0                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~0                                                   ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~1                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~3                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~0                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~1                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~2                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~3                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~1                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~3                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~4                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~1                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~3                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~4                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]~0                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]~2                                              ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[3]~0                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|STRB_LOCK~0          ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:STRB_LOCK~0  ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[6]~1      ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG~13        ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|STRB_LOCK~0         ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:STRB_LOCK~0 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                          ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0_RESYN30_BDD31                                                                                                            ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5                                                                                                                         ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN26_BDD27                                                                                                           ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28_BDD29                                                                                                           ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2                                                                                                                             ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN52_BDD53                                                                                                               ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN54_BDD55                                                                                                               ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START~5                                                                                          ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_END[10]                                                                                           ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[1]~19                                                                                       ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[10]~1                                                                                       ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28                                                                                                   ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28_RESYN32_BDD33                                                                                     ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~29                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~32                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~17                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~1                                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~29                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~32                                                                                                ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_15~1                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~15                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~43                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_26~22                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_27~22                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_28~20                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_30~20                                                                                               ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_31~1                                                                                                ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|_~472                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|_~478                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|_~479                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|_~481                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|_~482                                                                                                                                            ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~10                                                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~11                                                                                 ; Deleted         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42_BDD43                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN44_BDD45                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN46_BDD47                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN48_BDD49                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13                                                                                 ; Modified        ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34_BDD35                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN36_BDD37                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN38_BDD39                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN40_BDD41                                                                   ; Created         ; Physical Synthesis ; Timing optimization               ;           ;                ;                                                                                                                                  ;                  ;                       ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Ignored Assignments                                                                                                                            ;
-+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
-; Name                        ; Ignored Entity ; Ignored From ; Ignored To                 ; Ignored Value          ; Ignored Source             ;
-+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
-; DDIO_INPUT_REGISTER         ; altddio_bidir  ;              ; input_cell_H               ; HIGH                   ; Compiler or HDL Assignment ;
-; DDIO_INPUT_REGISTER         ; altddio_bidir  ;              ; input_cell_L               ; LOW                    ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_0hh1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_3fh1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; rdemp_eq_comp_lsb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; rdemp_eq_comp_msb_aeb      ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; rs_dgwp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-; Synchronizer Identification ; dcfifo_8fi1    ;              ; ws_dgrp_reg                ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ;
-+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+
-
-
-+------------------------------------------------+
-; Incremental Compilation Preservation Summary   ;
-+-------------------------+----------------------+
-; Type                    ; Value                ;
-+-------------------------+----------------------+
-; Netlist                 ;                      ;
-;     -- Requested        ; 0 / 0 ( 0.00 % )     ;
-;     -- Achieved         ; 0 / 0 ( 0.00 % )     ;
-;                         ;                      ;
-; Placement               ;                      ;
-;     -- Requested        ; 0 / 13829 ( 0.00 % ) ;
-;     -- Achieved         ; 0 / 13829 ( 0.00 % ) ;
-;                         ;                      ;
-; Routing (by Connection) ;                      ;
-;     -- Requested        ; 0 / 0 ( 0.00 % )     ;
-;     -- Achieved         ; 0 / 0 ( 0.00 % )     ;
-+-------------------------+----------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings                                                                                                       ;
-+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
-; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
-+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
-
-
-+--------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation                                             ;
-+----------------+---------+-------------------+-------------------------+-------------------+
-; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
-+----------------+---------+-------------------+-------------------------+-------------------+
-; Top            ; 13829   ; 0                 ; N/A                     ; Source File       ;
-+----------------+---------+-------------------+-------------------------+-------------------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in C:/FireBee/FPGA/firebee1.pin.
-
-
-+----------------------------------------------------------------------------+
-; Fitter Resource Usage Summary                                              ;
-+---------------------------------------------+------------------------------+
-; Resource                                    ; Usage                        ;
-+---------------------------------------------+------------------------------+
-; Total logic elements                        ; 9,526 / 39,600 ( 24 % )      ;
-;     -- Combinational with no register       ; 4963                         ;
-;     -- Register only                        ; 1465                         ;
-;     -- Combinational with a register        ; 3098                         ;
-;                                             ;                              ;
-; Logic element usage by number of LUT inputs ;                              ;
-;     -- 4 input functions                    ; 4959                         ;
-;     -- 3 input functions                    ; 1861                         ;
-;     -- <=2 input functions                  ; 1241                         ;
-;     -- Register only                        ; 1465                         ;
-;                                             ;                              ;
-; Logic elements by mode                      ;                              ;
-;     -- normal mode                          ; 7262                         ;
-;     -- arithmetic mode                      ; 799                          ;
-;                                             ;                              ;
-; Total registers*                            ; 4,749 / 41,185 ( 12 % )      ;
-;     -- Dedicated logic registers            ; 4,563 / 39,600 ( 12 % )      ;
-;     -- I/O registers                        ; 186 / 1,585 ( 12 % )         ;
-;                                             ;                              ;
-; Total LABs:  partially or completely used   ; 756 / 2,475 ( 31 % )         ;
-; User inserted logic elements                ; 0                            ;
-; Virtual pins                                ; 0                            ;
-; I/O pins                                    ; 295 / 332 ( 89 % )           ;
-;     -- Clock pins                           ; 7 / 8 ( 88 % )               ;
-;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )                ;
-; Global signals                              ; 20                           ;
-; M9Ks                                        ; 23 / 126 ( 18 % )            ;
-; Total block memory bits                     ; 109,344 / 1,161,216 ( 9 % )  ;
-; Total block memory implementation bits      ; 211,968 / 1,161,216 ( 18 % ) ;
-; Embedded Multiplier 9-bit elements          ; 6 / 252 ( 2 % )              ;
-; PLLs                                        ; 4 / 4 ( 100 % )              ;
-; Global clocks                               ; 20 / 20 ( 100 % )            ;
-; JTAGs                                       ; 0 / 1 ( 0 % )                ;
-; CRC blocks                                  ; 0 / 1 ( 0 % )                ;
-; ASMI blocks                                 ; 0 / 1 ( 0 % )                ;
-; Impedance control blocks                    ; 0 / 4 ( 0 % )                ;
-; Average interconnect usage (total/H/V)      ; 15% / 14% / 16%              ;
-; Peak interconnect usage (total/H/V)         ; 59% / 54% / 65%              ;
-; Maximum fan-out node                        ; MAIN_CLK~input               ;
-; Maximum fan-out                             ; 2272                         ;
-; Highest non-global fan-out signal           ; MAIN_CLK~input               ;
-; Highest non-global fan-out                  ; 2272                         ;
-; Total fan-out                               ; 44654                        ;
-; Average fan-out                             ; 3.02                         ;
-+---------------------------------------------+------------------------------+
-*  Register count does not include registers inside RAM blocks or DSP blocks.
-
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins                                                                                                                                                                                                                                                                          ;
-+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
-+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-; AMKB_RX        ; Y2    ; 2        ; 0            ; 10           ; 21           ; 10                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; CLK33M         ; AB12  ; 4        ; 36           ; 0            ; 0            ; 16                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; CTS            ; H14   ; 7        ; 61           ; 43           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; DCD            ; A19   ; 7        ; 56           ; 43           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; DVI_INT        ; A11   ; 8        ; 34           ; 43           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; E0_INT         ; G21   ; 6        ; 67           ; 22           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; FB_ALE         ; R7    ; 2        ; 0            ; 2            ; 0            ; 33                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; FB_SIZE0       ; U8    ; 3        ; 3            ; 0            ; 21           ; 24                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; FB_SIZE1       ; Y4    ; 3        ; 3            ; 0            ; 14           ; 24                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; HD_DD          ; F16   ; 7        ; 65           ; 43           ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; IDE_INT        ; G22   ; 6        ; 67           ; 22           ; 7            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; IDE_RDY        ; Y1    ; 2        ; 0            ; 9            ; 0            ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; LP_BUSY        ; G7    ; 8        ; 3            ; 43           ; 28           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; MAIN_CLK       ; G2    ; 1        ; 0            ; 21           ; 0            ; 2272                  ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; MIDI_IN        ; E12   ; 7        ; 36           ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; PIC_AMKB_RX    ; L7    ; 2        ; 0            ; 18           ; 7            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; PIC_INT        ; AA2   ; 2        ; 0            ; 7            ; 21           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; RI             ; B19   ; 7        ; 56           ; 43           ; 14           ; 3                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; RxD            ; H15   ; 7        ; 61           ; 43           ; 0            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; SD_CARD_DEDECT ; M20   ; 5        ; 67           ; 19           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; SD_DATA0       ; B16   ; 7        ; 50           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; SD_DATA1       ; A16   ; 7        ; 50           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; SD_DATA2       ; B17   ; 7        ; 50           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; SD_WP          ; M19   ; 5        ; 67           ; 19           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; TOUT0          ; T22   ; 5        ; 67           ; 22           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; TRACK00        ; C19   ; 7        ; 61           ; 43           ; 28           ; 11                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; WP_CF_CARD     ; T1    ; 2        ; 0            ; 21           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nACSI_DRQ      ; K7    ; 1        ; 0            ; 30           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nACSI_INT      ; J4    ; 1        ; 0            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nDACK0         ; B12   ; 7        ; 34           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nDACK1         ; A12   ; 7        ; 34           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nDCHG          ; C17   ; 7        ; 56           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_BURST      ; T3    ; 2        ; 0            ; 7            ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_CS1        ; T8    ; 3        ; 14           ; 0            ; 28           ; 59                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_CS2        ; T9    ; 3        ; 14           ; 0            ; 21           ; 95                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_CS3        ; V6    ; 3        ; 1            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_OE         ; R6    ; 2        ; 0            ; 3            ; 0            ; 101                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nFB_WR         ; T5    ; 2        ; 0            ; 4            ; 0            ; 235                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nINDEX         ; E16   ; 7        ; 65           ; 43           ; 28           ; 14                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nMASTER        ; T21   ; 5        ; 67           ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nPCI_INTA      ; AA1   ; 2        ; 0            ; 6            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nPCI_INTB      ; V4    ; 2        ; 0            ; 5            ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nPCI_INTC      ; V3    ; 2        ; 0            ; 5            ; 7            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nPCI_INTD      ; P6    ; 2        ; 0            ; 5            ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nRD_DATA       ; A20   ; 7        ; 59           ; 43           ; 7            ; 0                     ; 2                  ; no     ; yes            ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nRSTO_MCF      ; B11   ; 8        ; 34           ; 43           ; 21           ; 27                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nSCSI_C_D      ; H1    ; 1        ; 0            ; 28           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nSCSI_DRQ      ; U1    ; 2        ; 0            ; 15           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nSCSI_I_O      ; J3    ; 1        ; 0            ; 28           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nSCSI_MSG      ; H2    ; 1        ; 0            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-; nWP            ; D19   ; 7        ; 59           ; 43           ; 0            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
-+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
-; Name          ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
-; ACSI_A1       ; M6    ; 2        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; ACSI_DIR      ; L6    ; 2        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; AMKB_TX       ; N1    ; 2        ; 0            ; 19           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVCMOS ; 2mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; BA[0]         ; W19   ; 5        ; 67           ; 5            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; BA[1]         ; AA19  ; 4        ; 56           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; CLK24M576     ; AB10  ; 3        ; 34           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; CLK25M        ; T4    ; 2        ; 0            ; 4            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; CLKUSB        ; J1    ; 1        ; 0            ; 28           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; DDR_CLK       ; AB17  ; 4        ; 54           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; DSA_D         ; F15   ; 7        ; 63           ; 43           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; DTR           ; D15   ; 7        ; 54           ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; HSYNC_PAD     ; K21   ; 6        ; 67           ; 27           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; IDE_RES       ; M5    ; 2        ; 0            ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; LED_FPGA_OK   ; N19   ; 5        ; 67           ; 15           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 4mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; LPDIR         ; E5    ; 8        ; 1            ; 43           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; LP_STR        ; E6    ; 8        ; 1            ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; MIDI_OLR      ; H5    ; 1        ; 0            ; 31           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; MIDI_TLR      ; B2    ; 1        ; 0            ; 41           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; PIXEL_CLK_PAD ; F19   ; 6        ; 67           ; 37           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; RTS           ; B18   ; 7        ; 54           ; 43           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; SCSI_DIR      ; J7    ; 1        ; 0            ; 30           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; SD_CLK        ; C15   ; 7        ; 50           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; yes        ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; TIN0          ; R5    ; 2        ; 0            ; 4            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; TxD           ; A18   ; 7        ; 54           ; 43           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[0]         ; W20   ; 5        ; 67           ; 3            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[10]        ; V21   ; 5        ; 67           ; 10           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[11]        ; U19   ; 5        ; 67           ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[12]        ; AA18  ; 4        ; 54           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[1]         ; W22   ; 5        ; 67           ; 7            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[2]         ; W21   ; 5        ; 67           ; 8            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[3]         ; Y22   ; 5        ; 67           ; 6            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[4]         ; AA22  ; 5        ; 67           ; 2            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[5]         ; Y21   ; 5        ; 67           ; 7            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[6]         ; AA21  ; 5        ; 67           ; 2            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[7]         ; AA20  ; 4        ; 61           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[8]         ; AB20  ; 4        ; 61           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VA[9]         ; AB19  ; 4        ; 59           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[0]         ; G18   ; 6        ; 67           ; 37           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[1]         ; H17   ; 6        ; 67           ; 38           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[2]         ; C22   ; 6        ; 67           ; 38           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[3]         ; C21   ; 6        ; 67           ; 38           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[4]         ; B22   ; 6        ; 67           ; 39           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[5]         ; B21   ; 6        ; 67           ; 39           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[6]         ; C20   ; 6        ; 67           ; 39           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VB[7]         ; D20   ; 6        ; 67           ; 40           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VCKE          ; U15   ; 4        ; 50           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VDM[0]        ; AA16  ; 4        ; 45           ; 0            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VDM[1]        ; V16   ; 4        ; 61           ; 0            ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VDM[2]        ; U20   ; 5        ; 67           ; 7            ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VDM[3]        ; T17   ; 5        ; 67           ; 3            ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[0]         ; H19   ; 6        ; 67           ; 34           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[1]         ; E22   ; 6        ; 67           ; 34           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[2]         ; E21   ; 6        ; 67           ; 34           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[3]         ; H18   ; 6        ; 67           ; 35           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[4]         ; J17   ; 6        ; 67           ; 36           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[5]         ; H16   ; 6        ; 67           ; 36           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[6]         ; D22   ; 6        ; 67           ; 36           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VG[7]         ; D21   ; 6        ; 67           ; 36           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[0]         ; J22   ; 6        ; 67           ; 28           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[1]         ; J21   ; 6        ; 67           ; 28           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[2]         ; H22   ; 6        ; 67           ; 28           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[3]         ; H21   ; 6        ; 67           ; 28           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[4]         ; K17   ; 6        ; 67           ; 29           ; 0            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[5]         ; K18   ; 6        ; 67           ; 30           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[6]         ; J18   ; 6        ; 67           ; 31           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VR[7]         ; F22   ; 6        ; 67           ; 31           ; 7            ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; VSYNC_PAD     ; K19   ; 6        ; 67           ; 26           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; YM_QA         ; A17   ; 7        ; 52           ; 43           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; YM_QB         ; G13   ; 7        ; 52           ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; YM_QC         ; E15   ; 7        ; 54           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nACSI_ACK     ; M4    ; 2        ; 0            ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nACSI_CS      ; M2    ; 2        ; 0            ; 20           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nACSI_RESET   ; M1    ; 2        ; 0            ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nBLANK_PAD    ; G17   ; 6        ; 67           ; 41           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVTTL  ; 16mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nCF_CS0       ; W2    ; 2        ; 0            ; 10           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nCF_CS1       ; W1    ; 2        ; 0            ; 10           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nDDR_CLK      ; AA17  ; 4        ; 54           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nDREQ1        ; E11   ; 7        ; 36           ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nFB_TA        ; T7    ; 2        ; 0            ; 2            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIDE_CS0      ; R2    ; 2        ; 0            ; 16           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIDE_CS1      ; R1    ; 2        ; 0            ; 16           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIDE_RD       ; P1    ; 2        ; 0            ; 17           ; 21           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIDE_WR       ; P2    ; 2        ; 0            ; 17           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[2]       ; F21   ; 6        ; 67           ; 31           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[3]       ; H20   ; 6        ; 67           ; 34           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[4]       ; F20   ; 6        ; 67           ; 37           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[5]       ; P5    ; 2        ; 0            ; 12           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[6]       ; P7    ; 2        ; 0            ; 7            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nIRQ[7]       ; N7    ; 2        ; 0            ; 7            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nMOT_ON       ; G16   ; 7        ; 63           ; 43           ; 7            ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nPD_VGA       ; V1    ; 2        ; 0            ; 13           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nROM3         ; P3    ; 2        ; 0            ; 15           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nROM4         ; U2    ; 2        ; 0            ; 15           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nRP_LDS       ; N5    ; 2        ; 0            ; 16           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nRP_UDS       ; P4    ; 2        ; 0            ; 16           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSCSI_ACK     ; N2    ; 2        ; 0            ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSCSI_ATN     ; M3    ; 2        ; 0            ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSDSEL        ; B20   ; 7        ; 59           ; 43           ; 14           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSRBHE        ; B4    ; 8        ; 7            ; 43           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSRBLE        ; A4    ; 8        ; 9            ; 43           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSRCS         ; B8    ; 8        ; 25           ; 43           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSROE         ; F11   ; 7        ; 36           ; 43           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSRWE         ; F8    ; 8        ; 7            ; 43           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSTEP         ; F14   ; 7        ; 63           ; 43           ; 28           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSTEP_DIR     ; G15   ; 7        ; 63           ; 43           ; 21           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nSYNC         ; F17   ; 6        ; 67           ; 41           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.0-V LVCMOS ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nVCAS         ; AB18  ; 4        ; 52           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nVCS          ; T18   ; 5        ; 67           ; 3            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nVRAS         ; W17   ; 4        ; 59           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nVWE          ; Y17   ; 4        ; 61           ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nWR           ; G14   ; 7        ; 54           ; 43           ; 28           ; yes             ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-; nWR_GATE      ; D17   ; 7        ; 61           ; 43           ; 14           ; yes             ; no                     ; yes           ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; 0 pF ; -                    ; -                   ;
-+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
-; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                                                                          ; Output Enable Group ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
-; ACSI_D[0]   ; B1    ; 1        ; 0            ; 40           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[1]   ; G5    ; 1        ; 0            ; 40           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[2]   ; E3    ; 1        ; 0            ; 39           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[3]   ; C2    ; 1        ; 0            ; 38           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[4]   ; C1    ; 1        ; 0            ; 38           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[5]   ; D2    ; 1        ; 0            ; 37           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[6]   ; H7    ; 1        ; 0            ; 37           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; ACSI_D[7]   ; H6    ; 1        ; 0            ; 37           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; FB_AD[0]    ; Y3    ; 3        ; 3            ; 0            ; 7            ; 21                    ; 25                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[10]   ; W7    ; 3        ; 14           ; 0            ; 14           ; 19                    ; 27                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[11]   ; Y7    ; 3        ; 14           ; 0            ; 7            ; 19                    ; 14                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[12]   ; U9    ; 3        ; 16           ; 0            ; 21           ; 21                    ; 8                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[13]   ; V8    ; 3        ; 16           ; 0            ; 14           ; 21                    ; 13                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[14]   ; W8    ; 3        ; 16           ; 0            ; 7            ; 20                    ; 13                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[15]   ; AA7   ; 3        ; 16           ; 0            ; 0            ; 19                    ; 11                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[16]   ; AB7   ; 3        ; 18           ; 0            ; 21           ; 142                   ; 10                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted)                         ; -                   ;
-; FB_AD[17]   ; Y8    ; 3        ; 18           ; 0            ; 14           ; 144                   ; 9                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted)                         ; -                   ;
-; FB_AD[18]   ; V9    ; 3        ; 20           ; 0            ; 21           ; 144                   ; 9                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
-; FB_AD[19]   ; V10   ; 3        ; 20           ; 0            ; 14           ; 142                   ; 5                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted)                        ; -                   ;
-; FB_AD[1]    ; Y6    ; 3        ; 5            ; 0            ; 14           ; 20                    ; 158                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[20]   ; T10   ; 3        ; 18           ; 0            ; 7            ; 143                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
-; FB_AD[21]   ; U10   ; 3        ; 22           ; 0            ; 14           ; 142                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
-; FB_AD[22]   ; AA8   ; 3        ; 22           ; 0            ; 7            ; 139                   ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted)                        ; -                   ;
-; FB_AD[23]   ; AB8   ; 3        ; 22           ; 0            ; 0            ; 136                   ; 2                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted)                        ; -                   ;
-; FB_AD[24]   ; T11   ; 3        ; 18           ; 0            ; 0            ; 62                    ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted)                        ; -                   ;
-; FB_AD[25]   ; AA9   ; 3        ; 27           ; 0            ; 7            ; 58                    ; 3                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted)                        ; -                   ;
-; FB_AD[26]   ; AB9   ; 3        ; 27           ; 0            ; 0            ; 56                    ; 11                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 (inverted)                        ; -                   ;
-; FB_AD[27]   ; U11   ; 3        ; 29           ; 0            ; 28           ; 47                    ; 5                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
-; FB_AD[28]   ; V11   ; 3        ; 34           ; 0            ; 28           ; 36                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
-; FB_AD[29]   ; W10   ; 3        ; 34           ; 0            ; 21           ; 32                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
-; FB_AD[2]    ; AA3   ; 3        ; 7            ; 0            ; 28           ; 20                    ; 120                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[30]   ; Y10   ; 3        ; 34           ; 0            ; 14           ; 36                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
-; FB_AD[31]   ; AA10  ; 3        ; 34           ; 0            ; 7            ; 35                    ; 1                  ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted)                        ; -                   ;
-; FB_AD[3]    ; AB3   ; 3        ; 7            ; 0            ; 21           ; 20                    ; 97                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[4]    ; W6    ; 3        ; 7            ; 0            ; 14           ; 20                    ; 83                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[5]    ; V7    ; 3        ; 7            ; 0            ; 7            ; 20                    ; 161                ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[6]    ; AA4   ; 3        ; 9            ; 0            ; 28           ; 19                    ; 27                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[7]    ; AB4   ; 3        ; 9            ; 0            ; 21           ; 18                    ; 26                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[8]    ; AA5   ; 3        ; 9            ; 0            ; 14           ; 20                    ; 34                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; FB_AD[9]    ; AB5   ; 3        ; 9            ; 0            ; 7            ; 20                    ; 22                 ; no     ; yes            ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted)                        ; -                   ;
-; IO[0]       ; A8    ; 8        ; 25           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[10]      ; B15   ; 7        ; 45           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[11]      ; C13   ; 7        ; 45           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[12]      ; D13   ; 7        ; 45           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[13]      ; E13   ; 7        ; 41           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[14]      ; A14   ; 7        ; 41           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[15]      ; B14   ; 7        ; 38           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[16]      ; A13   ; 7        ; 38           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[17]      ; B13   ; 7        ; 38           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[1]       ; A7    ; 8        ; 25           ; 43           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[2]       ; B7    ; 8        ; 25           ; 43           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[3]       ; A6    ; 8        ; 25           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[4]       ; B6    ; 8        ; 22           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[5]       ; E9    ; 8        ; 22           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[6]       ; C8    ; 8        ; 20           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[7]       ; C7    ; 8        ; 20           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[8]       ; G10   ; 8        ; 11           ; 43           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; IO[9]       ; A15   ; 7        ; 45           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; LP_D[0]     ; F7    ; 8        ; 3            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[1]     ; C4    ; 8        ; 3            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[2]     ; C3    ; 8        ; 5            ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[3]     ; E7    ; 8        ; 5            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[4]     ; D6    ; 8        ; 5            ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[5]     ; B3    ; 8        ; 5            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[6]     ; A3    ; 8        ; 5            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; LP_D[7]     ; G8    ; 8        ; 7            ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; -                   ;
-; SCSI_D[0]   ; J6    ; 1        ; 0            ; 36           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[1]   ; E1    ; 1        ; 0            ; 36           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[2]   ; F2    ; 1        ; 0            ; 35           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[3]   ; F1    ; 1        ; 0            ; 35           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[4]   ; G4    ; 1        ; 0            ; 41           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[5]   ; G3    ; 1        ; 0            ; 41           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[6]   ; L8    ; 1        ; 0            ; 31           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_D[7]   ; K8    ; 1        ; 0            ; 30           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SCSI_PAR    ; M7    ; 2        ; 0            ; 11           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SD_CD_DATA3 ; F13   ; 7        ; 45           ; 43           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SD_CMD_D1   ; E14   ; 7        ; 48           ; 43           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; SRD[0]      ; B5    ; 8        ; 11           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[10]     ; A9    ; 8        ; 32           ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[11]     ; B10   ; 8        ; 32           ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[12]     ; D10   ; 8        ; 32           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[13]     ; F10   ; 8        ; 9            ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[14]     ; G9    ; 8        ; 1            ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[15]     ; H10   ; 8        ; 18           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[1]      ; A5    ; 8        ; 14           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[2]      ; C6    ; 8        ; 9            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[3]      ; G11   ; 8        ; 27           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[4]      ; C10   ; 8        ; 29           ; 43           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[5]      ; F9    ; 8        ; 1            ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[6]      ; E10   ; 8        ; 32           ; 43           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[7]      ; H11   ; 8        ; 20           ; 43           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[8]      ; B9    ; 8        ; 29           ; 43           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; SRD[9]      ; A10   ; 8        ; 32           ; 43           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted)                                                                          ; -                   ;
-; VDQS[0]     ; AA15  ; 4        ; 43           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                    ; -                   ;
-; VDQS[1]     ; W15   ; 4        ; 52           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                    ; -                   ;
-; VDQS[2]     ; U22   ; 5        ; 67           ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                    ; -                   ;
-; VDQS[3]     ; T16   ; 4        ; 63           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; yes                    ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst90                                                                                 ; -                   ;
-; VD[0]       ; M22   ; 5        ; 67           ; 18           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[10]      ; P17   ; 5        ; 67           ; 10           ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[11]      ; R21   ; 5        ; 67           ; 13           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[12]      ; N17   ; 5        ; 67           ; 17           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[13]      ; P20   ; 5        ; 67           ; 14           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[14]      ; R22   ; 5        ; 67           ; 13           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[15]      ; N20   ; 5        ; 67           ; 15           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[16]      ; T12   ; 4        ; 45           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[17]      ; Y13   ; 4        ; 43           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[18]      ; AA13  ; 4        ; 38           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[19]      ; V14   ; 4        ; 50           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[1]       ; M21   ; 5        ; 67           ; 18           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[20]      ; U13   ; 4        ; 50           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[21]      ; V15   ; 4        ; 50           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[22]      ; W14   ; 4        ; 48           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[23]      ; AB16  ; 4        ; 45           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[24]      ; AB15  ; 4        ; 43           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[25]      ; AA14  ; 4        ; 38           ; 0            ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[26]      ; AB14  ; 4        ; 38           ; 0            ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[27]      ; V13   ; 4        ; 48           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[28]      ; W13   ; 4        ; 43           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[29]      ; AB13  ; 4        ; 38           ; 0            ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[2]       ; P22   ; 5        ; 67           ; 14           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[30]      ; V12   ; 4        ; 41           ; 0            ; 28           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[31]      ; U12   ; 4        ; 43           ; 0            ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[3]       ; R20   ; 5        ; 67           ; 11           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[4]       ; P21   ; 5        ; 67           ; 14           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[5]       ; R17   ; 5        ; 67           ; 10           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[6]       ; R19   ; 5        ; 67           ; 12           ; 14           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[7]       ; U21   ; 5        ; 67           ; 11           ; 0            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[8]       ; V22   ; 5        ; 67           ; 10           ; 7            ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; VD[9]       ; R18   ; 5        ; 67           ; 12           ; 21           ; 3                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 2.5 V        ; 12mA             ; Off                ; --                        ; User                 ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted)                                                                      ; -                   ;
-; nSCSI_BUSY  ; N8    ; 2        ; 0            ; 11           ; 14           ; 0                     ; 0                  ; no     ; no             ; yes             ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; nSCSI_RST   ; N6    ; 2        ; 0            ; 12           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-; nSCSI_SEL   ; M8    ; 2        ; 0            ; 11           ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                                                             ; -                   ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Dual Purpose and Dedicated Pins                                                                                                            ;
-+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
-; Location ; Pin Name                                 ; Reserved As                    ; User Signal Name        ; Pin Type                  ;
-+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
-; D1       ; DIFFIO_L8n, DATA1, ASDO                  ; As input tri-stated            ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
-; E2       ; DIFFIO_L10p, FLASH_nCE, nCSO             ; As input tri-stated            ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
-; K6       ; nSTATUS                                  ; -                              ; -                       ; Dedicated Programming Pin ;
-; K2       ; DCLK                                     ; As input tri-stated            ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
-; K1       ; DATA0                                    ; As input tri-stated            ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
-; K5       ; nCONFIG                                  ; -                              ; -                       ; Dedicated Programming Pin ;
-; L3       ; nCE                                      ; -                              ; -                       ; Dedicated Programming Pin ;
-; N22      ; DIFFIO_R32n, DEV_OE                      ; Reserved as secondary function ; ~ALTERA_DEV_OE~         ; Dual Purpose Pin          ;
-; N21      ; DIFFIO_R32p, DEV_CLRn                    ; Reserved as secondary function ; ~ALTERA_DEV_CLRn~       ; Dual Purpose Pin          ;
-; M18      ; CONF_DONE                                ; -                              ; -                       ; Dedicated Programming Pin ;
-; M17      ; MSEL0                                    ; -                              ; -                       ; Dedicated Programming Pin ;
-; L18      ; MSEL1                                    ; -                              ; -                       ; Dedicated Programming Pin ;
-; L17      ; MSEL2                                    ; -                              ; -                       ; Dedicated Programming Pin ;
-; K20      ; MSEL3                                    ; -                              ; -                       ; Dedicated Programming Pin ;
-; K22      ; DIFFIO_R24n, nCEO                        ; Use as programming pin         ; ~ALTERA_nCEO~           ; Dual Purpose Pin          ;
-; K21      ; DIFFIO_R24p, CLKUSR                      ; Use as general purpose IO      ; HSYNC_PAD               ; Dual Purpose Pin          ;
-; E22      ; DIFFIO_R12n, nWE                         ; Use as regular IO              ; VG[1]                   ; Dual Purpose Pin          ;
-; E21      ; DIFFIO_R12p, nOE                         ; Use as regular IO              ; VG[2]                   ; Dual Purpose Pin          ;
-; F20      ; DIFFIO_R8n, nAVD                         ; Use as regular IO              ; nIRQ[4]                 ; Dual Purpose Pin          ;
-; F19      ; DIFFIO_R8n, nAVD                         ; -                              ; PIXEL_CLK_PAD           ; Dual Purpose Pin          ;
-; G18      ; DIFFIO_R7n, PADD23                       ; Use as regular IO              ; VB[0]                   ; Dual Purpose Pin          ;
-; B22      ; DIFFIO_R5n, PADD22                       ; Use as regular IO              ; VB[4]                   ; Dual Purpose Pin          ;
-; B21      ; DIFFIO_R5p, PADD21                       ; Use as regular IO              ; VB[5]                   ; Dual Purpose Pin          ;
-; C20      ; DIFFIO_R4n, PADD20, DQS2R/CQ3R,CDPCLK5   ; Use as regular IO              ; VB[6]                   ; Dual Purpose Pin          ;
-; B18      ; DIFFIO_T45p, PADD0                       ; Use as regular IO              ; RTS                     ; Dual Purpose Pin          ;
-; A17      ; DIFFIO_T41n, PADD1                       ; Use as regular IO              ; YM_QA                   ; Dual Purpose Pin          ;
-; B17      ; DIFFIO_T41p, PADD2                       ; Use as regular IO              ; SD_DATA2                ; Dual Purpose Pin          ;
-; E14      ; DIFFIO_T38n, PADD3                       ; Use as regular IO              ; SD_CMD_D1               ; Dual Purpose Pin          ;
-; F13      ; DIFFIO_T37p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO              ; SD_CD_DATA3             ; Dual Purpose Pin          ;
-; A15      ; DIFFIO_T36n, PADD5                       ; Use as regular IO              ; IO[9]                   ; Dual Purpose Pin          ;
-; B15      ; DIFFIO_T36p, PADD6                       ; Use as regular IO              ; IO[10]                  ; Dual Purpose Pin          ;
-; C13      ; DIFFIO_T35n, PADD7                       ; Use as regular IO              ; IO[11]                  ; Dual Purpose Pin          ;
-; D13      ; DIFFIO_T35p, PADD8                       ; Use as regular IO              ; IO[12]                  ; Dual Purpose Pin          ;
-; A14      ; DIFFIO_T31n, PADD9                       ; Use as regular IO              ; IO[14]                  ; Dual Purpose Pin          ;
-; B14      ; DIFFIO_T31p, PADD10                      ; Use as regular IO              ; IO[15]                  ; Dual Purpose Pin          ;
-; A13      ; DIFFIO_T29n, PADD11                      ; Use as regular IO              ; IO[16]                  ; Dual Purpose Pin          ;
-; B13      ; DIFFIO_T29p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO              ; IO[17]                  ; Dual Purpose Pin          ;
-; E11      ; DIFFIO_T27n, PADD13                      ; Use as regular IO              ; nDREQ1                  ; Dual Purpose Pin          ;
-; F11      ; DIFFIO_T27p, PADD14                      ; Use as regular IO              ; nSROE                   ; Dual Purpose Pin          ;
-; B10      ; DIFFIO_T25p, PADD15                      ; Use as regular IO              ; SRD[11]                 ; Dual Purpose Pin          ;
-; A9       ; DIFFIO_T24n, PADD16                      ; Use as regular IO              ; SRD[10]                 ; Dual Purpose Pin          ;
-; B9       ; DIFFIO_T24p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO              ; SRD[8]                  ; Dual Purpose Pin          ;
-; A8       ; DIFFIO_T20n, DATA2                       ; Use as regular IO              ; IO[0]                   ; Dual Purpose Pin          ;
-; B8       ; DIFFIO_T20p, DATA3                       ; Use as regular IO              ; nSRCS                   ; Dual Purpose Pin          ;
-; A7       ; DIFFIO_T19n, PADD18                      ; Use as regular IO              ; IO[1]                   ; Dual Purpose Pin          ;
-; B7       ; DIFFIO_T19p, DATA4                       ; Use as regular IO              ; IO[2]                   ; Dual Purpose Pin          ;
-; A6       ; DIFFIO_T18n, PADD19                      ; Use as regular IO              ; IO[3]                   ; Dual Purpose Pin          ;
-; B6       ; DIFFIO_T18p, DATA15                      ; Use as regular IO              ; IO[4]                   ; Dual Purpose Pin          ;
-; C8       ; DIFFIO_T16n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO              ; IO[6]                   ; Dual Purpose Pin          ;
-; C7       ; DIFFIO_T16p, DATA13                      ; Use as regular IO              ; IO[7]                   ; Dual Purpose Pin          ;
-; A5       ; DIFFIO_T11p, DATA5                       ; Use as regular IO              ; SRD[1]                  ; Dual Purpose Pin          ;
-; F10      ; DIFFIO_T8p, DATA6                        ; Use as regular IO              ; SRD[13]                 ; Dual Purpose Pin          ;
-; C6       ; DIFFIO_T7n, DATA7                        ; Use as regular IO              ; SRD[2]                  ; Dual Purpose Pin          ;
-; B4       ; DIFFIO_T6p, DATA8                        ; Use as regular IO              ; nSRBHE                  ; Dual Purpose Pin          ;
-; F8       ; DIFFIO_T5n, DATA9                        ; Use as regular IO              ; nSRWE                   ; Dual Purpose Pin          ;
-; A3       ; DIFFIO_T4n, DATA10                       ; Use as regular IO              ; LP_D[6]                 ; Dual Purpose Pin          ;
-; B3       ; DIFFIO_T4p, DATA11                       ; Use as regular IO              ; LP_D[5]                 ; Dual Purpose Pin          ;
-; C4       ; DIFFIO_T3p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO              ; LP_D[1]                 ; Dual Purpose Pin          ;
-+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+
-
-
-+-------------------------------------------------------------+
-; I/O Bank Usage                                              ;
-+----------+-------------------+---------------+--------------+
-; I/O Bank ; Usage             ; VCCIO Voltage ; VREF Voltage ;
-+----------+-------------------+---------------+--------------+
-; 1        ; 30 / 36 ( 83 % )  ; 3.3V          ; --           ;
-; 2        ; 44 / 46 ( 96 % )  ; 3.3V          ; --           ;
-; 3        ; 38 / 42 ( 90 % )  ; 3.3V          ; --           ;
-; 4        ; 33 / 43 ( 77 % )  ; 2.5V          ; --           ;
-; 5        ; 37 / 42 ( 88 % )  ; 2.5V          ; --           ;
-; 6        ; 35 / 37 ( 95 % )  ; 3.0V          ; --           ;
-; 7        ; 43 / 43 ( 100 % ) ; 3.3V          ; --           ;
-; 8        ; 42 / 43 ( 98 % )  ; 3.3V          ; --           ;
-+----------+-------------------+---------------+--------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins                                                                                                                                                         ;
-+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                             ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; A1       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; A2       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; A3       ; 534        ; 8        ; LP_D[6]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A4       ; 529        ; 8        ; nSRBLE                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A5       ; 518        ; 8        ; SRD[1]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A6       ; 501        ; 8        ; IO[3]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A7       ; 499        ; 8        ; IO[1]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A8       ; 497        ; 8        ; IO[0]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A9       ; 487        ; 8        ; SRD[10]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A10      ; 485        ; 8        ; SRD[9]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A11      ; 481        ; 8        ; DVI_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A12      ; 479        ; 7        ; nDACK1                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A13      ; 473        ; 7        ; IO[16]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A14      ; 469        ; 7        ; IO[14]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A15      ; 458        ; 7        ; IO[9]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A16      ; 448        ; 7        ; SD_DATA1                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A17      ; 446        ; 7        ; YM_QA                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A18      ; 437        ; 7        ; TxD                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A19      ; 435        ; 7        ; DCD                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A20      ; 430        ; 7        ; nRD_DATA                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; A21      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; A22      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AA1      ; 125        ; 2        ; nPCI_INTA                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; AA2      ; 124        ; 2        ; PIC_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; AA3      ; 154        ; 3        ; FB_AD[2]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA4      ; 158        ; 3        ; FB_AD[6]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA5      ; 160        ; 3        ; FB_AD[8]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA6      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; AA7      ; 173        ; 3        ; FB_AD[15]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA8      ; 183        ; 3        ; FB_AD[22]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA9      ; 189        ; 3        ; FB_AD[25]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA10     ; 202        ; 3        ; FB_AD[31]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA11     ; 204        ; 3        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA12     ; 206        ; 4        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AA13     ; 208        ; 4        ; VD[18]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA14     ; 210        ; 4        ; VD[25]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA15     ; 220        ; 4        ; VDQS[0]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA16     ; 224        ; 4        ; VDM[0]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA17     ; 243        ; 4        ; nDDR_CLK                                   ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA18     ; 245        ; 4        ; VA[12]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA19     ; 252        ; 4        ; BA[1]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA20     ; 259        ; 4        ; VA[7]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AA21     ; 274        ; 5        ; VA[6]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; AA22     ; 273        ; 5        ; VA[4]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; AB1      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB2      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; AB3      ; 155        ; 3        ; FB_AD[3]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB4      ; 159        ; 3        ; FB_AD[7]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB5      ; 161        ; 3        ; FB_AD[9]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB6      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; AB7      ; 174        ; 3        ; FB_AD[16]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB8      ; 184        ; 3        ; FB_AD[23]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB9      ; 190        ; 3        ; FB_AD[26]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB10     ; 203        ; 3        ; CLK24M576                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB11     ; 205        ; 3        ; GND+                                       ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
-; AB12     ; 207        ; 4        ; CLK33M                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB13     ; 209        ; 4        ; VD[29]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB14     ; 211        ; 4        ; VD[26]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB15     ; 221        ; 4        ; VD[24]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB16     ; 225        ; 4        ; VD[23]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB17     ; 244        ; 4        ; DDR_CLK                                    ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB18     ; 242        ; 4        ; nVCAS                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB19     ; 253        ; 4        ; VA[9]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB20     ; 260        ; 4        ; VA[8]                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; AB21     ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; AB22     ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; B1       ; 4          ; 1        ; ACSI_D[0]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B2       ; 3          ; 1        ; MIDI_TLR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B3       ; 535        ; 8        ; LP_D[5]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B4       ; 530        ; 8        ; nSRBHE                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B5       ; 523        ; 8        ; SRD[0]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B6       ; 502        ; 8        ; IO[4]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B7       ; 500        ; 8        ; IO[2]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B8       ; 498        ; 8        ; nSRCS                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B9       ; 488        ; 8        ; SRD[8]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B10      ; 486        ; 8        ; SRD[11]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B11      ; 482        ; 8        ; nRSTO_MCF                                  ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B12      ; 480        ; 7        ; nDACK0                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B13      ; 474        ; 7        ; IO[17]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B14      ; 470        ; 7        ; IO[15]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B15      ; 459        ; 7        ; IO[10]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B16      ; 449        ; 7        ; SD_DATA0                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B17      ; 447        ; 7        ; SD_DATA2                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B18      ; 438        ; 7        ; RTS                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B19      ; 434        ; 7        ; RI                                         ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B20      ; 431        ; 7        ; nSDSEL                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; B21      ; 404        ; 6        ; VB[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; B22      ; 403        ; 6        ; VB[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C1       ; 15         ; 1        ; ACSI_D[4]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C2       ; 14         ; 1        ; ACSI_D[3]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C3       ; 538        ; 8        ; LP_D[2]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C4       ; 539        ; 8        ; LP_D[1]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C5       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C6       ; 526        ; 8        ; SRD[2]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C7       ; 508        ; 8        ; IO[7]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C8       ; 507        ; 8        ; IO[6]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C10      ; 491        ; 8        ; SRD[4]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C13      ; 460        ; 7        ; IO[11]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C14      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C15      ; 450        ; 7        ; SD_CLK                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C17      ; 433        ; 7        ; nDCHG                                      ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C18      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; C19      ; 428        ; 7        ; TRACK00                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; C20      ; 405        ; 6        ; VB[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C21      ; 401        ; 6        ; VB[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; C22      ; 400        ; 6        ; VB[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D1       ; 17         ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT       ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
-; D2       ; 16         ; 1        ; ACSI_D[5]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D5       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D6       ; 536        ; 8        ; LP_D[4]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D7       ; 527        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; D8       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; D9       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D10      ; 483        ; 8        ; SRD[12]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D11      ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D12      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D13      ; 461        ; 7        ; IO[12]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D14      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D15      ; 439        ; 7        ; DTR                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D16      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D17      ; 426        ; 7        ; nWR_GATE                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D18      ;            ; 7        ; VCCIO7                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; D19      ; 429        ; 7        ; nWP                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; D20      ; 407        ; 6        ; VB[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D21      ; 395        ; 6        ; VG[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; D22      ; 394        ; 6        ; VG[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E1       ; 22         ; 1        ; SCSI_D[1]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E2       ; 21         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
-; E3       ; 9          ; 1        ; ACSI_D[2]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E4       ; 8          ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; E5       ; 546        ; 8        ; LPDIR                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E6       ; 545        ; 8        ; LP_STR                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E7       ; 537        ; 8        ; LP_D[3]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E8       ;            ; 8        ; VCCIO8                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; E9       ; 506        ; 8        ; IO[5]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E10      ; 484        ; 8        ; SRD[6]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E11      ; 477        ; 7        ; nDREQ1                                     ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E12      ; 476        ; 7        ; MIDI_IN                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E13      ; 468        ; 7        ; IO[13]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E14      ; 453        ; 7        ; SD_CMD_D1                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E15      ; 440        ; 7        ; YM_QC                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E16      ; 418        ; 7        ; nINDEX                                     ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; E17      ;            ;          ; VCCD_PLL2                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; E18      ;            ;          ; GNDA2                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
-; E20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; E21      ; 388        ; 6        ; VG[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; E22      ; 387        ; 6        ; VG[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F1       ; 26         ; 1        ; SCSI_D[3]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F2       ; 25         ; 1        ; SCSI_D[2]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; F5       ;            ;          ; GNDA3                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F6       ;            ;          ; VCCD_PLL3                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; F7       ; 542        ; 8        ; LP_D[0]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F8       ; 531        ; 8        ; nSRWE                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F9       ; 544        ; 8        ; SRD[5]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F10      ; 525        ; 8        ; SRD[13]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F11      ; 478        ; 7        ; nSROE                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; F13      ; 457        ; 7        ; SD_CD_DATA3                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F14      ; 423        ; 7        ; nSTEP                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F15      ; 419        ; 7        ; DSA_D                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F16      ; 417        ; 7        ; HD_DD                                      ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; F17      ; 410        ; 6        ; nSYNC                                      ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F18      ;            ; --       ; VCCA2                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; F19      ; 397        ; 6        ; PIXEL_CLK_PAD                              ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F20      ; 396        ; 6        ; nIRQ[4]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F21      ; 376        ; 6        ; nIRQ[2]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; F22      ; 375        ; 6        ; VR[7]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G1       ; 67         ; 1        ; GND+                                       ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; G2       ; 66         ; 1        ; MAIN_CLK                                   ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G3       ; 1          ; 1        ; SCSI_D[5]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G4       ; 0          ; 1        ; SCSI_D[4]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G5       ; 5          ; 1        ; ACSI_D[1]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G6       ;            ; --       ; VCCA3                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; G7       ; 543        ; 8        ; LP_BUSY                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G8       ; 532        ; 8        ; LP_D[7]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G9       ; 547        ; 8        ; SRD[14]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G10      ; 524        ; 8        ; IO[8]                                      ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G11      ; 492        ; 8        ; SRD[3]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; G13      ; 444        ; 7        ; YM_QB                                      ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G14      ; 441        ; 7        ; nWR                                        ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G15      ; 422        ; 7        ; nSTEP_DIR                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G16      ; 420        ; 7        ; nMOT_ON                                    ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; G17      ; 411        ; 6        ; nBLANK_PAD                                 ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G18      ; 398        ; 6        ; VB[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
-; G20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; G21      ; 345        ; 6        ; E0_INT                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; G22      ; 344        ; 6        ; IDE_INT                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H1       ; 52         ; 1        ; nSCSI_C_D                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H2       ; 51         ; 1        ; nSCSI_MSG                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; H5       ; 42         ; 1        ; MIDI_OLR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H6       ; 19         ; 1        ; ACSI_D[7]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H7       ; 18         ; 1        ; ACSI_D[6]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H8       ; 29         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; H9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; H10      ; 512        ; 8        ; SRD[15]                                    ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; H11      ; 511        ; 8        ; SRD[7]                                     ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; H12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; H14      ; 425        ; 7        ; CTS                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; H15      ; 424        ; 7        ; RxD                                        ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; H16      ; 393        ; 6        ; VG[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H17      ; 399        ; 6        ; VB[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H18      ; 391        ; 6        ; VG[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H19      ; 386        ; 6        ; VG[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H20      ; 385        ; 6        ; nIRQ[3]                                    ; output ; 3.0-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H21      ; 365        ; 6        ; VR[3]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; H22      ; 364        ; 6        ; VR[2]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J1       ; 55         ; 1        ; CLKUSB                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J2       ; 54         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J3       ; 53         ; 1        ; nSCSI_I_O                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J4       ; 50         ; 1        ; nACSI_INT                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J5       ; 38         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J6       ; 20         ; 1        ; SCSI_D[0]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J7       ; 45         ; 1        ; SCSI_DIR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J8       ; 30         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; J9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J11      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J13      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J16      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; J17      ; 392        ; 6        ; VG[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J18      ; 374        ; 6        ; VR[6]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J19      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; J20      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
-; J21      ; 363        ; 6        ; VR[1]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; J22      ; 362        ; 6        ; VR[0]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K1       ; 59         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT            ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
-; K2       ; 58         ; 1        ; ~ALTERA_DCLK~ / RESERVED_INPUT             ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
-; K3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K4       ;            ; 1        ; VCCIO1                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; K5       ; 60         ; 1        ; ^nCONFIG                                   ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K6       ; 41         ; 1        ; ^nSTATUS                                   ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K7       ; 46         ; 1        ; nACSI_DRQ                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K8       ; 44         ; 1        ; SCSI_D[7]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K15      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; K16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; K17      ; 369        ; 6        ; VR[4]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K18      ; 370        ; 6        ; VR[5]                                      ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K19      ; 357        ; 6        ; VSYNC_PAD                                  ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K20      ; 350        ; 6        ; ^MSEL3                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; K21      ; 361        ; 6        ; HSYNC_PAD                                  ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; K22      ; 360        ; 6        ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.0-V LVTTL  ;         ; Row I/O    ; N               ; no       ; Off          ;
-; L1       ; 63         ; 1        ; #TMS                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L2       ; 62         ; 1        ; #TCK                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L3       ; 65         ; 1        ; ^nCE                                       ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L4       ; 64         ; 1        ; #TDO                                       ; output ;              ;         ; --         ;                 ; --       ; --           ;
-; L5       ; 61         ; 1        ; #TDI                                       ; input  ;              ;         ; --         ;                 ; --       ; --           ;
-; L6       ; 70         ; 2        ; ACSI_DIR                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; L7       ; 79         ; 2        ; PIC_AMKB_RX                                ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; L8       ; 43         ; 1        ; SCSI_D[6]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; L9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L16      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; L17      ; 349        ; 6        ; ^MSEL2                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L18      ; 348        ; 6        ; ^MSEL1                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; L19      ;            ; 6        ; VCCIO6                                     ; power  ;              ; 3.0V    ; --         ;                 ; --       ; --           ;
-; L20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; L21      ; 354        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; L22      ; 353        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M1       ; 73         ; 2        ; nACSI_RESET                                ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M2       ; 72         ; 2        ; nACSI_CS                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M3       ; 75         ; 2        ; nSCSI_ATN                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M4       ; 74         ; 2        ; nACSI_ACK                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M5       ; 80         ; 2        ; IDE_RES                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M6       ; 71         ; 2        ; ACSI_A1                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M7       ; 105        ; 2        ; SCSI_PAR                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M8       ; 106        ; 2        ; nSCSI_SEL                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; M14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M15      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; M16      ; 337        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; M17      ; 347        ; 6        ; ^MSEL0                                     ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M18      ; 346        ; 6        ; ^CONF_DONE                                 ;        ;              ;         ; --         ;                 ; --       ; --           ;
-; M19      ; 336        ; 5        ; SD_WP                                      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M20      ; 335        ; 5        ; SD_CARD_DEDECT                             ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M21      ; 334        ; 5        ; VD[1]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; M22      ; 333        ; 5        ; VD[0]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N1       ; 77         ; 2        ; AMKB_TX                                    ; output ; 3.3-V LVCMOS ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N2       ; 76         ; 2        ; nSCSI_ACK                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; N5       ; 87         ; 2        ; nRP_LDS                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N6       ; 104        ; 2        ; nSCSI_RST                                  ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N7       ; 122        ; 2        ; nIRQ[7]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N8       ; 107        ; 2        ; nSCSI_BUSY                                 ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N10      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; N15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; N16      ; 314        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N17      ; 329        ; 5        ; VD[12]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N18      ; 330        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; N19      ; 324        ; 5        ; LED_FPGA_OK                                ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N20      ; 323        ; 5        ; VD[15]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; N21      ; 332        ; 5        ; ~ALTERA_DEV_CLRn~ / RESERVED_INPUT         ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; N22      ; 331        ; 5        ; ~ALTERA_DEV_OE~ / RESERVED_INPUT           ; input  ; 2.5 V        ;         ; Row I/O    ; N               ; no       ; Off          ;
-; P1       ; 84         ; 2        ; nIDE_RD                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P2       ; 83         ; 2        ; nIDE_WR                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P3       ; 89         ; 2        ; nROM3                                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P4       ; 88         ; 2        ; nRP_UDS                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P5       ; 103        ; 2        ; nIRQ[5]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P6       ; 131        ; 2        ; nPCI_INTD                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P7       ; 123        ; 2        ; nIRQ[6]                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P8       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P9       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P11      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P13      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P14      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; P15      ; 298        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P16      ; 299        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; P17      ; 302        ; 5        ; VD[10]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P18      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; P19      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; P20      ; 317        ; 5        ; VD[13]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P21      ; 320        ; 5        ; VD[4]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; P22      ; 319        ; 5        ; VD[2]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R1       ; 86         ; 2        ; nIDE_CS1                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R2       ; 85         ; 2        ; nIDE_CS0                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; R5       ; 135        ; 2        ; TIN0                                       ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R6       ; 136        ; 2        ; nFB_OE                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R7       ; 137        ; 2        ; FB_ALE                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R8       ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; R9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R10      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; R11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R12      ;            ;          ; VCCINT                                     ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; R13      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; R14      ; 268        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R15      ; 269        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R16      ; 267        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; R17      ; 301        ; 5        ; VD[5]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R18      ; 309        ; 5        ; VD[9]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R19      ; 310        ; 5        ; VD[6]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R20      ; 305        ; 5        ; VD[3]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R21      ; 316        ; 5        ; VD[11]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; R22      ; 315        ; 5        ; VD[14]                                     ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T1       ; 69         ; 2        ; WP_CF_CARD                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T2       ; 68         ; 2        ; GND+                                       ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
-; T3       ; 121        ; 2        ; nFB_BURST                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T4       ; 134        ; 2        ; CLK25M                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T5       ; 133        ; 2        ; nFB_WR                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T6       ;            ; --       ; VCCA1                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T7       ; 138        ; 2        ; nFB_TA                                     ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T8       ; 166        ; 3        ; nFB_CS1                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T9       ; 167        ; 3        ; nFB_CS2                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T10      ; 176        ; 3        ; FB_AD[20]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T11      ; 177        ; 3        ; FB_AD[24]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T12      ; 226        ; 4        ; VD[16]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T13      ; 227        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T14      ; 240        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T15      ; 241        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; T16      ; 266        ; 4        ; VDQS[3]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; T17      ; 277        ; 5        ; VDM[3]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T18      ; 278        ; 5        ; nVCS                                       ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; T20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; T21      ; 343        ; 5        ; nMASTER                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; T22      ; 342        ; 5        ; TOUT0                                      ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U1       ; 92         ; 2        ; nSCSI_DRQ                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U2       ; 91         ; 2        ; nROM4                                      ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; U5       ;            ;          ; GNDA1                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; U6       ;            ;          ; VCCD_PLL1                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; U7       ; 145        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U8       ; 146        ; 3        ; FB_SIZE0                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U9       ; 170        ; 3        ; FB_AD[12]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U10      ; 182        ; 3        ; FB_AD[21]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U11      ; 191        ; 3        ; FB_AD[27]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U12      ; 222        ; 4        ; VD[31]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U13      ; 233        ; 4        ; VD[20]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U14      ; 235        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U15      ; 236        ; 4        ; VCKE                                       ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; U16      ; 262        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U17      ; 263        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; U18      ;            ; --       ; VCCA4                                      ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; U19      ; 291        ; 5        ; VA[11]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U20      ; 290        ; 5        ; VDM[2]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U21      ; 308        ; 5        ; VD[7]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; U22      ; 307        ; 5        ; VDQS[2]                                    ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; V1       ; 98         ; 2        ; nPD_VGA                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; V2       ; 97         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
-; V3       ; 130        ; 2        ; nPCI_INTC                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; V4       ; 129        ; 2        ; nPCI_INTB                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; V5       ; 142        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP            ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
-; V6       ; 141        ; 3        ; nFB_CS3                                    ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V7       ; 157        ; 3        ; FB_AD[5]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V8       ; 171        ; 3        ; FB_AD[13]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V9       ; 178        ; 3        ; FB_AD[18]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V10      ; 179        ; 3        ; FB_AD[19]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V11      ; 199        ; 3        ; FB_AD[28]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V12      ; 213        ; 4        ; VD[30]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V13      ; 228        ; 4        ; VD[27]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V14      ; 234        ; 4        ; VD[19]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V15      ; 237        ; 4        ; VD[21]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V16      ; 261        ; 4        ; VDM[1]                                     ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; V17      ;            ;          ; VCCD_PLL4                                  ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
-; V18      ;            ;          ; GNDA4                                      ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; V20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; V21      ; 304        ; 5        ; VA[10]                                     ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; V22      ; 303        ; 5        ; VD[8]                                      ; bidir  ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W1       ; 111        ; 2        ; nCF_CS1                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W2       ; 110        ; 2        ; nCF_CS0                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W3       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; W4       ;            ; 2        ; VCCIO2                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; W5       ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; W6       ; 156        ; 3        ; FB_AD[4]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W7       ; 168        ; 3        ; FB_AD[10]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W8       ; 172        ; 3        ; FB_AD[14]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W9       ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; W10      ; 200        ; 3        ; FB_AD[29]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W11      ;            ; 3        ; VCCIO3                                     ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
-; W12      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W13      ; 218        ; 4        ; VD[28]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W14      ; 229        ; 4        ; VD[22]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W15      ; 239        ; 4        ; VDQS[1]                                    ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W16      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W17      ; 257        ; 4        ; nVRAS                                      ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; W18      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; W19      ; 285        ; 5        ; BA[0]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W20      ; 280        ; 5        ; VA[0]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W21      ; 293        ; 5        ; VA[2]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; W22      ; 292        ; 5        ; VA[1]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; Y1       ; 113        ; 2        ; IDE_RDY                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; Y2       ; 112        ; 2        ; AMKB_RX                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; Y3       ; 148        ; 3        ; FB_AD[0]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y4       ; 147        ; 3        ; FB_SIZE1                                   ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y5       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y6       ; 152        ; 3        ; FB_AD[1]                                   ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y7       ; 169        ; 3        ; FB_AD[11]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y8       ; 175        ; 3        ; FB_AD[17]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y9       ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y10      ; 201        ; 3        ; FB_AD[30]                                  ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y11      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y12      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y13      ; 219        ; 4        ; VD[17]                                     ; bidir  ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y14      ;            ; 4        ; VCCIO4                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y15      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y16      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y17      ; 258        ; 4        ; nVWE                                       ; output ; 2.5 V        ;         ; Column I/O ; Y               ; no       ; Off          ;
-; Y18      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y19      ;            ; 5        ; VCCIO5                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
-; Y20      ;            ;          ; GND                                        ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
-; Y21      ; 289        ; 5        ; VA[5]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-; Y22      ; 288        ; 5        ; VA[3]                                      ; output ; 2.5 V        ;         ; Row I/O    ; Y               ; no       ; Off          ;
-+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; PLL Summary                                                                                                                                                                                                                                                                                                                       ;
-+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
-; Name                          ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1   ;
-+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
-; SDC pin name                  ; inst|altpll_component|auto_generated|pll1                            ; inst13|altpll_component|auto_generated|pll1                            ; inst12|altpll_component|auto_generated|pll1                            ; inst22|altpll_component|auto_generated|pll1                              ;
-; PLL mode                      ; Source Synchronous                                                   ; Source Synchronous                                                     ; Source Synchronous                                                     ; Normal                                                                   ;
-; Compensate clock              ; clock0                                                               ; clock1                                                                 ; clock0                                                                 ; clock0                                                                   ;
-; Compensated input/output pins ; --                                                                   ; nRD_DATA                                                               ; MAIN_CLK                                                               ; --                                                                       ;
-; Switchover type               ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-; Input frequency 0             ; 33.0 MHz                                                             ; 33.0 MHz                                                               ; 33.0 MHz                                                               ; 48.0 MHz                                                                 ;
-; Input frequency 1             ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-; Nominal PFD frequency         ; 5.5 MHz                                                              ; 11.0 MHz                                                               ; 33.0 MHz                                                               ; 48.0 MHz                                                                 ;
-; Nominal VCO frequency         ; 368.5 MHz                                                            ; 1199.0 MHz                                                             ; 396.0 MHz                                                              ; 576.0 MHz                                                                ;
-; VCO post scale                ; 2                                                                    ; --                                                                     ; 2                                                                      ; 2                                                                        ;
-; VCO frequency control         ; Auto                                                                 ; Auto                                                                   ; Auto                                                                   ; Auto                                                                     ;
-; VCO phase shift step          ; 339 ps                                                               ; 104 ps                                                                 ; 315 ps                                                                 ; 217 ps                                                                   ;
-; VCO multiply                  ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-; VCO divide                    ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-; Freq min lock                 ; 32.4 MHz                                                             ; 16.8 MHz                                                               ; 25.0 MHz                                                               ; 25.0 MHz                                                                 ;
-; Freq max lock                 ; 58.23 MHz                                                            ; 35.79 MHz                                                              ; 54.18 MHz                                                              ; 54.18 MHz                                                                ;
-; M VCO Tap                     ; 0                                                                    ; 0                                                                      ; 0                                                                      ; 0                                                                        ;
-; M Initial                     ; 1                                                                    ; 1                                                                      ; 1                                                                      ; 1                                                                        ;
-; M value                       ; 67                                                                   ; 109                                                                    ; 12                                                                     ; 12                                                                       ;
-; N value                       ; 6                                                                    ; 3                                                                      ; 1                                                                      ; 1                                                                        ;
-; Charge pump current           ; setting 1                                                            ; setting 1                                                              ; setting 1                                                              ; setting 1                                                                ;
-; Loop filter resistance        ; setting 16                                                           ; setting 19                                                             ; setting 27                                                             ; setting 27                                                               ;
-; Loop filter capacitance       ; setting 0                                                            ; setting 0                                                              ; setting 0                                                              ; setting 0                                                                ;
-; Bandwidth                     ; 340 kHz to 540 kHz                                                   ; 450 kHz to 560 kHz                                                     ; 680 kHz to 980 kHz                                                     ; 680 kHz to 980 kHz                                                       ;
-; Real time reconfigurable      ; Off                                                                  ; Off                                                                    ; Off                                                                    ; On                                                                       ;
-; Scan chain MIF file           ; --                                                                   ; --                                                                     ; --                                                                     ; altpll4.mif                                                              ;
-; Preserve PLL counter order    ; Off                                                                  ; Off                                                                    ; Off                                                                    ; Off                                                                      ;
-; PLL location                  ; PLL_3                                                                ; PLL_4                                                                  ; PLL_1                                                                  ; PLL_2                                                                    ;
-; Inclk0 signal                 ; CLK33M                                                               ; CLK33M                                                                 ; MAIN_CLK                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ;
-; Inclk1 signal                 ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-; Inclk0 signal type            ; Global Clock                                                         ; Dedicated Pin                                                          ; Dedicated Pin                                                          ; Global Clock                                                             ;
-; Inclk1 signal type            ; --                                                                   ; --                                                                     ; --                                                                     ; --                                                                       ;
-+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; PLL Usage                                                                                                                                                                                                                                                                                                              ;
-+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
-; Name                                                                                ; Output Clock ; Mult ; Div  ; Output Frequency ; Phase Shift    ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low   ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                       ;
-+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]              ; clock0       ; 1    ; 66   ; 0.5 MHz          ; 0 (0 ps)       ; 0.67 (339 ps)    ; 50/50      ; C1      ; 67            ; 34/33 Odd    ; C0            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[0]   ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]              ; clock1       ; 67   ; 900  ; 2.46 MHz         ; 0 (0 ps)       ; 0.30 (339 ps)    ; 50/50      ; C2      ; 150           ; 75/75 Even   ; --            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[1]   ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]              ; clock2       ; 67   ; 90   ; 24.57 MHz        ; 0 (0 ps)       ; 3.00 (339 ps)    ; 50/50      ; C3      ; 15            ; 8/7 Odd      ; --            ; 1       ; 0       ; inst|altpll_component|auto_generated|pll1|clk[2]   ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~cascade_in   ; --           ; --   ; --   ; --               ; --             ; --               ; --         ; C0      ; 11            ; 5/6 Odd      ; --            ; 1       ; 0       ;                                                    ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]            ; clock0       ; 109  ; 1800 ; 2.0 MHz          ; 0 (0 ps)       ; 0.15 (104 ps)    ; 50/50      ; C1      ; 300           ; 150/150 Even ; C0            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[0] ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]            ; clock1       ; 109  ; 225  ; 15.99 MHz        ; 0 (0 ps)       ; 0.60 (104 ps)    ; 50/50      ; C2      ; 75            ; 38/37 Odd    ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[1] ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]            ; clock2       ; 109  ; 144  ; 24.98 MHz        ; 0 (0 ps)       ; 0.94 (104 ps)    ; 50/50      ; C3      ; 48            ; 24/24 Even   ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[2] ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]            ; clock3       ; 109  ; 75   ; 47.96 MHz        ; 0 (0 ps)       ; 1.80 (104 ps)    ; 50/50      ; C4      ; 25            ; 13/12 Odd    ; --            ; 1       ; 0       ; inst13|altpll_component|auto_generated|pll1|clk[3] ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~cascade_in ; --           ; --   ; --   ; --               ; --             ; --               ; --         ; C0      ; 2             ; 1/1 Even     ; --            ; 1       ; 0       ;                                                    ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]            ; clock0       ; 4    ; 1    ; 132.0 MHz        ; 240 (5051 ps)  ; 15.00 (315 ps)   ; 50/50      ; C0      ; 3             ; 2/1 Odd      ; --            ; 3       ; 0       ; inst12|altpll_component|auto_generated|pll1|clk[0] ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]            ; clock1       ; 4    ; 1    ; 132.0 MHz        ; 0 (0 ps)       ; 15.00 (315 ps)   ; 50/50      ; C3      ; 3             ; 2/1 Odd      ; --            ; 1       ; 0       ; inst12|altpll_component|auto_generated|pll1|clk[1] ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]            ; clock2       ; 4    ; 1    ; 132.0 MHz        ; 180 (3788 ps)  ; 15.00 (315 ps)   ; 50/50      ; C2      ; 3             ; 2/1 Odd      ; --            ; 2       ; 4       ; inst12|altpll_component|auto_generated|pll1|clk[2] ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]            ; clock3       ; 4    ; 1    ; 132.0 MHz        ; 105 (2210 ps)  ; 15.00 (315 ps)   ; 50/50      ; C4      ; 3             ; 2/1 Odd      ; --            ; 1       ; 7       ; inst12|altpll_component|auto_generated|pll1|clk[3] ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]            ; clock4       ; 2    ; 1    ; 66.0 MHz         ; 270 (11364 ps) ; 7.50 (315 ps)    ; 50/50      ; C1      ; 6             ; 3/3 Even     ; --            ; 5       ; 4       ; inst12|altpll_component|auto_generated|pll1|clk[4] ;
-; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]            ; clock0       ; 2    ; 1    ; 96.0 MHz         ; 0 (0 ps)       ; 7.50 (217 ps)    ; 50/50      ; C0      ; 6             ; 3/3 Even     ; --            ; 1       ; 0       ; inst22|altpll_component|auto_generated|pll1|clk[0] ;
-+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------+
-; Output Pin Default Load For Reported TCO                                      ;
-+----------------------------------+-------+------------------------------------+
-; I/O Standard                     ; Load  ; Termination Resistance             ;
-+----------------------------------+-------+------------------------------------+
-; 3.0-V LVTTL                      ; 0 pF  ; Not Available                      ;
-; 3.3-V LVTTL                      ; 0 pF  ; Not Available                      ;
-; 3.0-V LVCMOS                     ; 0 pF  ; Not Available                      ;
-; 3.3-V LVCMOS                     ; 0 pF  ; Not Available                      ;
-; 3.0-V PCI                        ; 10 pF ; Not Available                      ;
-; 3.0-V PCI-X                      ; 10 pF ; Not Available                      ;
-; 2.5 V                            ; 0 pF  ; Not Available                      ;
-; 1.8 V                            ; 0 pF  ; Not Available                      ;
-; 1.5 V                            ; 0 pF  ; Not Available                      ;
-; 1.2 V                            ; 0 pF  ; Not Available                      ;
-; SSTL-2 Class I                   ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
-; Differential 2.5-V SSTL Class I  ; 0 pF  ; (See SSTL-2)                       ;
-; SSTL-2 Class II                  ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
-; Differential 2.5-V SSTL Class II ; 0 pF  ; (See SSTL-2 Class II)              ;
-; SSTL-18 Class I                  ; 0 pF  ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
-; Differential 1.8-V SSTL Class I  ; 0 pF  ; (See 1.8-V SSTL Class I)           ;
-; SSTL-18 Class II                 ; 0 pF  ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
-; Differential 1.8-V SSTL Class II ; 0 pF  ; (See 1.8-V SSTL Class II)          ;
-; 1.8-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
-; Differential 1.8-V HSTL Class I  ; 0 pF  ; (See 1.8-V HSTL Class I)           ;
-; 1.8-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
-; Differential 1.8-V HSTL Class II ; 0 pF  ; (See 1.8-V HSTL Class II)          ;
-; 1.5-V HSTL Class I               ; 0 pF  ; 50 Ohm (Parallel)                  ;
-; Differential 1.5-V HSTL Class I  ; 0 pF  ; (See 1.5-V HSTL Class I)           ;
-; 1.5-V HSTL Class II              ; 0 pF  ; 25 Ohm (Parallel)                  ;
-; Differential 1.5-V HSTL Class II ; 0 pF  ; (See 1.5-V HSTL Class II)          ;
-; 1.2-V HSTL Class I               ; 0 pF  ; Not Available                      ;
-; Differential 1.2-V HSTL Class I  ; 0 pF  ; Not Available                      ;
-; 1.2-V HSTL Class II              ; 0 pF  ; Not Available                      ;
-; Differential 1.2-V HSTL Class II ; 0 pF  ; Not Available                      ;
-; Differential LVPECL              ; 0 pF  ; 100 Ohm (Differential)             ;
-; LVDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
-; LVDS_E_3R                        ; 0 pF  ; Not Available                      ;
-; RSDS                             ; 0 pF  ; 100 Ohm (Differential)             ;
-; RSDS_E_1R                        ; 0 pF  ; Not Available                      ;
-; RSDS_E_3R                        ; 0 pF  ; Not Available                      ;
-; mini-LVDS                        ; 0 pF  ; 100 Ohm (Differential)             ;
-; mini-LVDS_E_3R                   ; 0 pF  ; Not Available                      ;
-; PPDS                             ; 0 pF  ; Not Available                      ;
-; PPDS_E_3R                        ; 0 pF  ; Not Available                      ;
-; Bus LVDS                         ; 0 pF  ; Not Available                      ;
-+----------------------------------+-------+------------------------------------+
-Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
-+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                                  ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                                               ; Library Name ;
-+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; |firebee1                                                                   ; 9526 (10)   ; 4563 (0)                  ; 186 (186)     ; 109344      ; 23   ; 6            ; 0       ; 3         ; 295  ; 0            ; 4963 (10)    ; 1465 (0)          ; 3098 (0)         ; |firebee1                                                                                                                                                                                                         ; work         ;
-;    |DSP:Mathias_Alles|                                                      ; 10 (10)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; |firebee1|DSP:Mathias_Alles                                                                                                                                                                                       ;              ;
-;    |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|          ; 4093 (640)  ; 1616 (114)                ; 0 (0)         ; 16384       ; 2    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2414 (465)   ; 291 (10)          ; 1388 (177)       ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden                                                                                                                                           ;              ;
-;       |WF1772IP_TOP_SOC:I_FDC|                                              ; 976 (17)    ; 403 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 565 (9)      ; 33 (0)            ; 378 (15)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC                                                                                                                    ;              ;
-;          |WF1772IP_AM_DETECTOR:I_AM_DETECTOR|                               ; 40 (40)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (13)      ; 1 (1)             ; 26 (26)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR                                                                                 ;              ;
-;          |WF1772IP_CONTROL:I_CONTROL|                                       ; 545 (545)   ; 196 (196)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 344 (344)    ; 12 (12)           ; 189 (189)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL                                                                                         ;              ;
-;          |WF1772IP_CRC_LOGIC:I_CRC_LOGIC|                                   ; 51 (51)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 11 (11)           ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC                                                                                     ;              ;
-;          |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|                               ; 103 (103)   ; 37 (37)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 66 (66)      ; 0 (0)             ; 37 (37)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL                                                                                 ;              ;
-;          |WF1772IP_REGISTERS:I_REGISTERS|                                   ; 105 (105)   ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 57 (57)      ; 7 (7)             ; 41 (41)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS                                                                                     ;              ;
-;          |WF1772IP_TRANSCEIVER:I_TRANSCEIVER|                               ; 120 (120)   ; 79 (79)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 2 (2)             ; 77 (77)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER                                                                                 ;              ;
-;       |WF2149IP_TOP_SOC:I_SOUND|                                            ; 490 (36)    ; 197 (16)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 293 (20)     ; 37 (2)            ; 160 (18)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND                                                                                                                  ;              ;
-;          |WF2149IP_WAVE:I_PSG_WAVE|                                         ; 461 (461)   ; 181 (181)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 273 (273)    ; 35 (35)           ; 153 (153)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE                                                                                         ;              ;
-;       |WF5380_TOP_SOC:I_SCSI|                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI                                                                                                                     ;              ;
-;          |WF5380_CONTROL:I_CONTROL|                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL                                                                                            ;              ;
-;       |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|                                    ; 208 (1)     ; 97 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 106 (1)      ; 1 (0)             ; 101 (1)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD                                                                                                          ;              ;
-;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 21 (21)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 1 (1)             ; 10 (10)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                  ;              ;
-;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 101 (101)   ; 47 (47)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 54 (54)      ; 0 (0)             ; 47 (47)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                          ;              ;
-;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)     ; 39 (39)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 0 (0)             ; 46 (46)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                        ;              ;
-;       |WF6850IP_TOP_SOC:I_ACIA_MIDI|                                        ; 218 (2)     ; 97 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 116 (2)      ; 10 (0)            ; 92 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI                                                                                                              ;              ;
-;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 27 (27)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 12 (12)      ; 6 (6)             ; 9 (9)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                      ;              ;
-;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 101 (101)   ; 47 (47)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 53 (53)      ; 3 (3)             ; 45 (45)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                              ;              ;
-;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 88 (88)     ; 39 (39)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 49 (49)      ; 1 (1)             ; 38 (38)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                            ;              ;
-;       |WF68901IP_TOP_SOC:I_MFP|                                             ; 1261 (110)  ; 460 (2)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 797 (107)    ; 70 (0)            ; 394 (71)         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP                                                                                                                   ;              ;
-;          |WF68901IP_GPIO:I_GPIO|                                            ; 49 (49)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (23)      ; 9 (9)             ; 17 (17)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO                                                                                             ;              ;
-;          |WF68901IP_INTERRUPTS:I_INTERRUPTS|                                ; 290 (290)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 159 (159)    ; 5 (5)             ; 126 (126)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS                                                                                 ;              ;
-;          |WF68901IP_TIMERS:I_TIMERS|                                        ; 501 (501)   ; 166 (166)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 332 (332)    ; 44 (44)           ; 125 (125)        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS                                                                                         ;              ;
-;          |WF68901IP_USART_TOP:I_USART|                                      ; 316 (3)     ; 140 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 176 (3)      ; 12 (0)            ; 128 (1)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART                                                                                       ;              ;
-;             |WF68901IP_USART_CTRL:I_USART_CTRL|                             ; 77 (77)     ; 49 (49)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (28)      ; 9 (9)             ; 40 (40)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL                                                     ;              ;
-;             |WF68901IP_USART_RX:I_USART_RECEIVE|                            ; 160 (160)   ; 56 (56)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 100 (100)    ; 2 (2)             ; 58 (58)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE                                                    ;              ;
-;             |WF68901IP_USART_TX:I_USART_TRANSMIT|                           ; 87 (87)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 45 (45)      ; 1 (1)             ; 41 (41)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT                                                   ;              ;
-;       |dcfifo0:RDF|                                                         ; 156 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 60 (0)            ; 66 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF                                                                                                                               ;              ;
-;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 156 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 60 (0)            ; 66 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
-;             |dcfifo_0hh1:auto_generated|                                    ; 156 (55)    ; 124 (42)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (4)       ; 60 (27)           ; 66 (13)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated                                                  ;              ;
-;                |a_gray2bin_lfb:wrptr_g_gray2bin|                            ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin                  ;              ;
-;                |a_gray2bin_lfb:ws_dgrp_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin                  ;              ;
-;                |a_graycounter_fic:wrptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 1 (1)             ; 13 (13)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p                      ;              ;
-;                |a_graycounter_k47:rdptr_g1p|                                ; 18 (18)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p                      ;              ;
-;                |alt_synch_pipe_ikd:rs_dgwp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 4 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp                       ;              ;
-;                   |dffpipe_hd9:dffpipe12|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;              ;
-;                |alt_synch_pipe_jkd:ws_dgrp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (0)            ; 1 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp                       ;              ;
-;                   |dffpipe_id9:dffpipe17|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (17)           ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;              ;
-;                |altsyncram_bi31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram                         ;              ;
-;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
-;                |cmpr_156:wrfull_eq_comp1_msb|                               ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb                     ;              ;
-;                |cntr_t2e:cntr_b|                                            ; 3 (3)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
-;                |dffpipe_gd9:ws_brp|                                         ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp                               ;              ;
-;                |dffpipe_pe9:ws_bwp|                                         ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (10)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp                               ;              ;
-;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
-;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
-;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
-;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
-;       |dcfifo1:WRF|                                                         ; 166 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (0)       ; 70 (0)            ; 54 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF                                                                                                                               ;              ;
-;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 166 (0)     ; 124 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (0)       ; 70 (0)            ; 54 (0)           ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
-;             |dcfifo_3fh1:auto_generated|                                    ; 166 (58)    ; 124 (42)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 42 (6)       ; 70 (34)           ; 54 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated                                                  ;              ;
-;                |a_gray2bin_lfb:rdptr_g_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin                  ;              ;
-;                |a_gray2bin_lfb:rs_dgwp_gray2bin|                            ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 4 (4)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin                  ;              ;
-;                |a_graycounter_gic:wrptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p                      ;              ;
-;                |a_graycounter_j47:rdptr_g1p|                                ; 17 (17)     ; 13 (13)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 12 (12)          ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p                      ;              ;
-;                |alt_synch_pipe_kkd:rs_dgwp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 3 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp                       ;              ;
-;                   |dffpipe_jd9:dffpipe12|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 3 (3)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;              ;
-;                |alt_synch_pipe_lkd:ws_dgrp|                                 ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 2 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp                       ;              ;
-;                   |dffpipe_kd9:dffpipe15|                                   ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;              ;
-;                |altsyncram_ci31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram                         ;              ;
-;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
-;                |cntr_t2e:cntr_b|                                            ; 4 (4)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
-;                |dffpipe_gd9:rs_bwp|                                         ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 6 (6)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp                               ;              ;
-;                |dffpipe_pe9:rs_brp|                                         ; 10 (10)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 9 (9)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp                               ;              ;
-;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 1 (1)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
-;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 3 (3)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
-;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 2 (2)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
-;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 0 (0)            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
-;    |Video:Fredi_Aschwanden|                                                 ; 4088 (14)   ; 2168 (4)                  ; 0 (0)         ; 92816       ; 20   ; 6            ; 0       ; 3         ; 0    ; 0            ; 1920 (10)    ; 916 (4)           ; 1252 (0)         ; |firebee1|Video:Fredi_Aschwanden                                                                                                                                                                                  ;              ;
-;       |DDR_CTR:DDR_CTR|                                                     ; 374 (342)   ; 158 (158)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 211 (180)    ; 20 (20)           ; 143 (140)        ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR                                                                                                                                                                  ;              ;
-;          |lpm_bustri_BYT:$00002|                                            ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002                                                                                                                                            ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
-;          |lpm_bustri_BYT:$00004|                                            ; 31 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 3 (0)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004                                                                                                                                            ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 31 (31)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (28)      ; 0 (0)             ; 3 (3)            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
-;       |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|                         ; 1420 (1292) ; 529 (529)                 ; 0 (0)         ; 0           ; 0    ; 6            ; 0       ; 3         ; 0    ; 0            ; 891 (763)    ; 158 (158)         ; 371 (252)        ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR                                                                                                                                      ;              ;
-;          |lpm_bustri_WORD:$00000|                                           ; 187 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 112 (0)      ; 0 (0)             ; 75 (0)           ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000                                                                                                               ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 187 (187)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 112 (112)    ; 0 (0)             ; 75 (75)          ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component                                                                               ;              ;
-;          |lpm_bustri_WORD:$00002|                                           ; 60 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 44 (0)           ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002                                                                                                               ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 60 (60)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 44 (44)          ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component                                                                               ;              ;
-;          |lpm_mult:op_12|                                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12                                                                                                                       ;              ;
-;             |mult_aat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated                                                                                               ;              ;
-;          |lpm_mult:op_14|                                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14                                                                                                                       ;              ;
-;             |mult_cat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated                                                                                               ;              ;
-;          |lpm_mult:op_6|                                                    ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6                                                                                                                        ;              ;
-;             |mult_aat:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated                                                                                                ;              ;
-;       |altddio_bidir0:inst1|                                                ; 96 (0)      ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1                                                                                                                                                             ;              ;
-;          |altddio_bidir:altddio_bidir_component|                            ; 96 (0)      ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component                                                                                                                       ;              ;
-;             |ddio_bidir_3jl:auto_generated|                                 ; 96 (96)     ; 96 (96)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 96 (96)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated                                                                                         ;              ;
-;       |altddio_out0:inst2|                                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2                                                                                                                                                               ;              ;
-;          |altddio_out:altddio_out_component|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component                                                                                                                             ;              ;
-;             |ddio_out_are:auto_generated|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated                                                                                                 ;              ;
-;       |altddio_out2:inst5|                                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5                                                                                                                                                               ;              ;
-;          |altddio_out:altddio_out_component|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component                                                                                                                             ;              ;
-;             |ddio_out_o2f:auto_generated|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated                                                                                                 ;              ;
-;       |altdpram0:ST_CLUT_BLUE|                                              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE                                                                                                                                                           ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                           ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                            ;              ;
-;       |altdpram0:ST_CLUT_GREEN|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN                                                                                                                                                          ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                          ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                           ;              ;
-;       |altdpram0:ST_CLUT_RED|                                               ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED                                                                                                                                                            ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                                                                                                            ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 48          ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                             ;              ;
-;       |altdpram1:FALCON_CLUT_BLUE|                                          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE                                                                                                                                                       ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                       ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                        ;              ;
-;       |altdpram1:FALCON_CLUT_GREEN|                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN                                                                                                                                                      ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                      ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                       ;              ;
-;       |altdpram1:FALCON_CLUT_RED|                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED                                                                                                                                                        ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                                                                                                        ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 1536        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                         ;              ;
-;       |altdpram2:ACP_CLUT_RAM54|                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54                                                                                                                                                         ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                                                                                                         ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
-;       |altdpram2:ACP_CLUT_RAM55|                                            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55                                                                                                                                                         ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                                                                                                         ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
-;       |altdpram2:ACP_CLUT_RAM|                                              ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM                                                                                                                                                           ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                                                                                                           ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                            ;              ;
-;       |lpm_bustri_LONG:inst119|                                             ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_ff0:inst13|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 23 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 23 (23)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst14|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 31 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 31 (31)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst15|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 25 (0)            ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 25 (25)           ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst16|                                                      ; 28 (0)      ; 28 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (0)            ; 2 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 28 (28)     ; 28 (28)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (26)           ; 2 (2)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst17|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 31 (0)            ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 31 (31)           ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst18|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 30 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 30 (30)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst19|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst12|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (0)            ; 2 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (30)           ; 2 (2)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst20|                                                      ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 28 (0)            ; 4 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 28 (28)           ; 4 (4)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst3|                                                       ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 32 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff1:inst4|                                                       ; 32 (0)      ; 32 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (0)            ; 6 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 32 (32)     ; 32 (32)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 26 (26)           ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff1:inst9|                                                       ; 24 (0)      ; 24 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 12 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 24 (24)     ; 24 (24)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 12 (12)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff3:inst46|                                                      ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst47|                                                      ; 18 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 18 (18)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst49|                                                      ; 9 (0)       ; 9 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst52|                                                      ; 9 (0)       ; 9 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 9 (9)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff4:inst10|                                                      ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 4 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 4 (4)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff5:inst11|                                                      ; 8 (0)       ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 8 (8)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff5:inst97|                                                      ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff6:inst71|                                                      ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 87 (0)            ; 41 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 87 (87)           ; 41 (41)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff6:inst94|                                                      ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 85 (0)            ; 43 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 85 (85)           ; 43 (43)          ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_fifoDZ:inst63|                                                   ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63                                                                                                                                                                ;              ;
-;          |scfifo:scfifo_component|                                          ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component                                                                                                                                        ;              ;
-;             |scfifo_lk21:auto_generated|                                    ; 22 (0)      ; 21 (0)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 21 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated                                                                                                             ;              ;
-;                |a_dpfifo_oq21:dpfifo|                                       ; 22 (9)      ; 21 (8)                    ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 21 (8)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo                                                                                        ;              ;
-;                   |altsyncram_gj81:FIFOram|                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 16384       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram                                                                ;              ;
-;                   |cntr_omb:rd_ptr_msb|                                     ; 6 (6)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb                                                                    ;              ;
-;                   |cntr_pmb:wr_ptr|                                         ; 7 (7)       ; 7 (7)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr                                                                        ;              ;
-;       |lpm_fifo_dc0:inst|                                                   ; 118 (0)     ; 98 (0)                    ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 51 (0)            ; 47 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst                                                                                                                                                                ;              ;
-;          |dcfifo:dcfifo_component|                                          ; 118 (0)     ; 98 (0)                    ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 51 (0)            ; 47 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component                                                                                                                                        ;              ;
-;             |dcfifo_8fi1:auto_generated|                                    ; 118 (31)    ; 98 (20)                   ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (2)       ; 51 (16)           ; 47 (10)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                                                                             ;              ;
-;                |a_gray2bin_tgb:wrptr_g_gray2bin|                            ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 3 (3)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                                                                             ;              ;
-;                |a_gray2bin_tgb:ws_dgrp_gray2bin|                            ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 6 (6)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                                                                             ;              ;
-;                |a_graycounter_njc:wrptr_gp|                                 ; 18 (18)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 13 (13)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp                                                                                  ;              ;
-;                |a_graycounter_s57:rdptr_g1p|                                ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p                                                                                 ;              ;
-;                |alt_synch_pipe_sld:ws_dgrp|                                 ; 30 (0)      ; 30 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (0)            ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp                                                                                  ;              ;
-;                   |dffpipe_re9:dffpipe22|                                   ; 30 (30)     ; 30 (30)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 30 (30)           ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22                                                            ;              ;
-;                |altsyncram_tl31:fifo_ram|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 65536       ; 8    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram                                                                                    ;              ;
-;                |dffpipe_9d9:wraclr|                                         ; 2 (2)       ; 2 (2)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr                                                                                          ;              ;
-;                |dffpipe_oe9:ws_brp|                                         ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp                                                                                          ;              ;
-;                |dffpipe_oe9:ws_bwp|                                         ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp                                                                                          ;              ;
-;       |lpm_latch0:inst27|                                                   ; 32 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (0)       ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27                                                                                                                                                                ;              ;
-;          |lpm_latch:lpm_latch_component|                                    ; 32 (32)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 31 (31)      ; 0 (0)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component                                                                                                                                  ;              ;
-;       |lpm_mux0:inst21|                                                     ; 120 (0)     ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (0)       ; 71 (0)            ; 27 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 120 (0)     ; 96 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (0)       ; 71 (0)            ; 27 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_gpe:auto_generated|                                        ; 120 (120)   ; 96 (96)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 22 (22)      ; 71 (71)           ; 27 (27)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux1:inst24|                                                     ; 113 (0)     ; 81 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (0)       ; 33 (0)            ; 48 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 113 (0)     ; 81 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (0)       ; 33 (0)            ; 48 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_npe:auto_generated|                                        ; 113 (113)   ; 81 (81)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 32 (32)      ; 33 (33)           ; 48 (48)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux2:inst25|                                                     ; 81 (0)      ; 41 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (0)       ; 1 (0)             ; 40 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 81 (0)      ; 41 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (0)       ; 1 (0)             ; 40 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_mpe:auto_generated|                                        ; 81 (81)     ; 41 (41)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (40)      ; 1 (1)             ; 40 (40)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux3:inst102|                                                    ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102                                                                                                                                                                 ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
-;             |mux_96e:auto_generated|                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated                                                                                                                ;              ;
-;       |lpm_mux4:inst81|                                                     ; 7 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 7 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_f6e:auto_generated|                                        ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 7 (7)            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux5:inst22|                                                     ; 64 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 60 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 64 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 60 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_58e:auto_generated|                                        ; 64 (64)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 60 (60)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux6:inst7|                                                      ; 91 (0)      ; 67 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (0)        ; 1 (0)             ; 82 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7                                                                                                                                                                   ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 91 (0)      ; 67 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (0)        ; 1 (0)             ; 82 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component                                                                                                                                         ;              ;
-;             |mux_kpe:auto_generated|                                        ; 91 (91)     ; 67 (67)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 8 (8)        ; 1 (1)             ; 82 (82)          ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated                                                                                                                  ;              ;
-;       |lpm_muxDZ:inst62|                                                    ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (0)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62                                                                                                                                                                 ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 128 (0)     ; 128 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (0)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
-;             |mux_dcf:auto_generated|                                        ; 128 (128)   ; 128 (128)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 128 (128)        ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated                                                                                                                ;              ;
-;       |lpm_muxVDM:inst100|                                                  ; 736 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (0)      ; 0 (0)             ; 96 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100                                                                                                                                                               ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 736 (0)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (0)      ; 0 (0)             ; 96 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component                                                                                                                                     ;              ;
-;             |mux_bbe:auto_generated|                                        ; 736 (736)   ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 640 (640)    ; 0 (0)             ; 96 (96)          ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated                                                                                                              ;              ;
-;       |lpm_shiftreg0:sr0|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr1|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr2|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr3|                                                   ; 17 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 17 (17)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr4|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr5|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (0)             ; 15 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 15 (15)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr6|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr7|                                                   ; 16 (0)      ; 16 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (0)           ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)     ; 16 (16)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 16 (16)          ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg4:inst26|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26                                                                                                                                                             ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
-;       |lpm_shiftreg6:inst92|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (0)             ; 1 (0)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92                                                                                                                                                             ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 4 (4)             ; 1 (1)            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
-;       |mux41:inst40|                                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40                                                                                                                                                                     ;              ;
-;       |mux41:inst41|                                                        ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41                                                                                                                                                                     ;              ;
-;       |mux41:inst42|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42                                                                                                                                                                     ;              ;
-;       |mux41:inst43|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43                                                                                                                                                                     ;              ;
-;       |mux41:inst44|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44                                                                                                                                                                     ;              ;
-;       |mux41:inst45|                                                        ; 2 (2)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45                                                                                                                                                                     ;              ;
-;    |altddio_out3:inst5|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst6|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst8|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst9|                                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9                                                                                                                                                                                      ; work         ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component                                                                                                                                                    ; work         ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ; work         ;
-;    |altpll1:inst|                                                           ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst                                                                                                                                                                                            ;              ;
-;       |altpll:altpll_component|                                             ; 1 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst|altpll:altpll_component                                                                                                                                                                    ;              ;
-;          |altpll_pul2:auto_generated|                                       ; 1 (1)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated                                                                                                                                         ;              ;
-;    |altpll2:inst12|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_isv2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated                                                                                                                                       ;              ;
-;    |altpll3:inst13|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_41p2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated                                                                                                                                       ;              ;
-;    |altpll4:inst22|                                                         ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_c6j2:auto_generated|                                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated                                                                                                                                       ;              ;
-;    |altpll_reconfig1:inst7|                                                 ; 334 (0)     ; 128 (0)                   ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 206 (0)      ; 22 (0)            ; 106 (0)          ; |firebee1|altpll_reconfig1:inst7                                                                                                                                                                                  ;              ;
-;       |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 334 (237)   ; 128 (80)                  ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 206 (157)    ; 22 (22)           ; 106 (57)         ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component                                                                                                              ;              ;
-;          |altsyncram:altsyncram4|                                           ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4                                                                                       ;              ;
-;             |altsyncram_46r:auto_generated|                                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 144         ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated                                                         ;              ;
-;          |lpm_compare:cmpr7|                                                ; 3 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 1 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7                                                                                            ;              ;
-;             |cmpr_tnd:auto_generated|                                       ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 1 (1)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr12|                                               ; 10 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12                                                                                           ;              ;
-;             |cntr_30l:auto_generated|                                       ; 10 (10)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr13|                                               ; 7 (0)       ; 6 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 6 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13                                                                                           ;              ;
-;             |cntr_qij:auto_generated|                                       ; 7 (7)       ; 6 (6)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 6 (6)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr14|                                               ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14                                                                                           ;              ;
-;             |cntr_pij:auto_generated|                                       ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr15|                                               ; 18 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15                                                                                           ;              ;
-;             |cntr_30l:auto_generated|                                       ; 18 (18)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr1|                                                ; 41 (0)      ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1                                                                                            ;              ;
-;             |cntr_30l:auto_generated|                                       ; 41 (41)     ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (33)      ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr2|                                                ; 9 (0)       ; 8 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 0 (0)             ; 8 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2                                                                                            ;              ;
-;             |cntr_9cj:auto_generated|                                       ; 9 (9)       ; 8 (8)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr3|                                                ; 5 (0)       ; 5 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3                                                                                            ;              ;
-;             |cntr_pij:auto_generated|                                       ; 5 (5)       ; 5 (5)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated                                                                    ;              ;
-;    |interrupt_handler:nobody|                                               ; 1037 (999)  ; 633 (633)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 401 (363)    ; 235 (235)         ; 401 (355)        ; |firebee1|interrupt_handler:nobody                                                                                                                                                                                ;              ;
-;       |lpm_bustri_BYT:$00000|                                               ; 14 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 9 (0)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 14 (14)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 9 (9)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00002|                                               ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (0)       ; 0 (0)             ; 8 (0)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 16 (16)      ; 0 (0)             ; 8 (8)            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00004|                                               ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (0)       ; 0 (0)             ; 14 (0)           ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 14 (14)          ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00006|                                               ; 22 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (0)        ; 0 (0)             ; 15 (0)           ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 22 (22)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 15 (15)          ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;    |lpm_counter0:inst18|                                                    ; 19 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 1 (0)             ; 17 (0)           ; |firebee1|lpm_counter0:inst18                                                                                                                                                                                     ;              ;
-;       |lpm_counter:lpm_counter_component|                                   ; 19 (0)      ; 18 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (0)        ; 1 (0)             ; 17 (0)           ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component                                                                                                                                                   ;              ;
-;          |cntr_mph:auto_generated|                                          ; 19 (19)     ; 18 (18)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 17 (17)          ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated                                                                                                                           ;              ;
-;    |lpm_ff0:inst1|                                                          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|lpm_ff0:inst1                                                                                                                                                                                           ;              ;
-;       |lpm_ff:lpm_ff_component|                                             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component                                                                                                                                                                   ;              ;
-+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary                                                                                     ;
-+----------------+----------+---------------+---------------+-----------------------+----------+----------+
-; Name           ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO      ; TCOE     ;
-+----------------+----------+---------------+---------------+-----------------------+----------+----------+
-; CLK24M576      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; LP_STR         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nFB_BURST      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nACSI_DRQ      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nACSI_INT      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_DRQ      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_MSG      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nDCHG          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_DATA0       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_DATA1       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_DATA2       ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_CARD_DEDECT ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_WP          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nDACK0         ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; WP_CF_CARD     ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_C_D      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_I_O      ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nFB_CS3        ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; CLK25M         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nACSI_ACK      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nACSI_RESET    ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nACSI_CS       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_DIR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_A1        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_ACK      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_ATN      ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_DIR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; MIDI_OLR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; MIDI_TLR       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; TxD            ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; RTS            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; DTR            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; AMKB_TX        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; IDE_RES        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIDE_CS0       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIDE_CS1       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIDE_WR        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIDE_RD        ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nCF_CS0        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nCF_CS1        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nROM3          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nROM4          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nRP_UDS        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nRP_LDS        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSDSEL         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nWR_GATE       ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nWR            ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; YM_QA          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; YM_QB          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; YM_QC          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; SD_CLK         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; DSA_D          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nVWE           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nVCAS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nVRAS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nVCS           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nPD_VGA        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; TIN0           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSRCS          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSRBLE         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSRBHE         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSRWE          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nDREQ1         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; LED_FPGA_OK    ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nSROE          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VCKE           ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nFB_TA         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nDDR_CLK       ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; DDR_CLK        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VSYNC_PAD      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; HSYNC_PAD      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nBLANK_PAD     ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; PIXEL_CLK_PAD  ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nSYNC          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nMOT_ON        ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nSTEP_DIR      ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nSTEP          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; CLKUSB         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; LPDIR          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; BA[1]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; BA[0]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[7]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[6]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[5]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[4]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[3]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; nIRQ[2]        ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[12]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[11]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[10]         ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[9]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[8]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[7]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[6]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[5]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[4]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[3]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[2]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[1]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VA[0]          ; Output   ; --            ; --            ; --                    ; --       ; --       ;
-; VB[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VB[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VDM[3]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VDM[2]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VDM[1]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VDM[0]         ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VG[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[7]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[6]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[5]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[4]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[3]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[2]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[1]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; VR[0]          ; Output   ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; TOUT0          ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; nMASTER        ; Input    ; --            ; --            ; --                    ; --       ; --       ;
-; FB_AD[31]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[30]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[29]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[28]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[27]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[26]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[25]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[24]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[23]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[22]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[21]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[20]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[19]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[18]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[17]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[16]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[15]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[14]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[13]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[12]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[11]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[10]      ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[9]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[8]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[7]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[6]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[5]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[4]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[3]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[2]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[1]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; FB_AD[0]       ; Bidir    ; --            ; (0) 0 ps      ; (0) 0 ps              ; --       ; --       ;
-; VD[31]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[30]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[29]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[28]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[27]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[26]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[25]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[24]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[23]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[22]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[21]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[20]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[19]         ; Bidir    ; (1) 634 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[18]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[17]         ; Bidir    ; (0) 0 ps      ; (1) 634 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[16]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[15]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[14]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[13]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[12]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[11]         ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[10]         ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[9]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[8]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[7]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[6]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[5]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[4]          ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; VD[3]          ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[2]          ; Bidir    ; (0) 0 ps      ; (2) 952 ps    ; --                    ; (0) 0 ps ; --       ;
-; VD[1]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VD[0]          ; Bidir    ; (2) 952 ps    ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; VDQS[3]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
-; VDQS[2]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
-; VDQS[1]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
-; VDQS[0]        ; Bidir    ; --            ; --            ; --                    ; --       ; (0) 0 ps ;
-; IO[17]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[16]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[15]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[14]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[13]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[12]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[11]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[10]         ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[9]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[8]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[7]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[6]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[5]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[4]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[3]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[2]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[1]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; IO[0]          ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SRD[15]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[14]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[13]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[12]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[11]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[10]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[9]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[8]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[7]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[6]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[5]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[4]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[3]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[2]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SRD[1]         ; Bidir    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; SRD[0]         ; Bidir    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; SCSI_PAR       ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_SEL      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; nSCSI_BUSY     ; Bidir    ; --            ; --            ; --                    ; (0) 0 ps ; --       ;
-; nSCSI_RST      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_CD_DATA3    ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SD_CMD_D1      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[7]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[6]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[5]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[4]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; ACSI_D[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; LP_D[7]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; LP_D[6]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; LP_D[5]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; LP_D[4]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; LP_D[3]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; LP_D[2]        ; Bidir    ; --            ; (0) 0 ps      ; --                    ; (0) 0 ps ; --       ;
-; LP_D[1]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; LP_D[0]        ; Bidir    ; (0) 0 ps      ; --            ; --                    ; (0) 0 ps ; --       ;
-; SCSI_D[7]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[6]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[5]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[4]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[3]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[2]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[1]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; SCSI_D[0]      ; Bidir    ; --            ; --            ; --                    ; --       ; --       ;
-; nRSTO_MCF      ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; nFB_WR         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nFB_CS1        ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; FB_SIZE1       ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; FB_SIZE0       ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; FB_ALE         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nFB_CS2        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; MAIN_CLK       ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; nDACK1         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; nFB_OE         ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; IDE_RDY        ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; CLK33M         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; HD_DD          ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nINDEX         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; RxD            ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; nWP            ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; LP_BUSY        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; DCD            ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; CTS            ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; TRACK00        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; IDE_INT        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; RI             ; Input    ; --            ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nPCI_INTD      ; Input    ; (6) 2223 ps   ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nPCI_INTC      ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
-; nPCI_INTB      ; Input    ; (6) 2223 ps   ; (0) 0 ps      ; --                    ; --       ; --       ;
-; nPCI_INTA      ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
-; DVI_INT        ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; E0_INT         ; Input    ; (0) 0 ps      ; --            ; --                    ; --       ; --       ;
-; PIC_INT        ; Input    ; (0) 0 ps      ; (6) 2223 ps   ; --                    ; --       ; --       ;
-; PIC_AMKB_RX    ; Input    ; (1) 663 ps    ; --            ; --                    ; --       ; --       ;
-; MIDI_IN        ; Input    ; --            ; (1) 634 ps    ; --                    ; --       ; --       ;
-; nRD_DATA       ; Input    ; --            ; --            ; (0) 0 ps              ; --       ; --       ;
-; AMKB_RX        ; Input    ; (0) 0 ps      ; (0) 0 ps      ; --                    ; --       ; --       ;
-+----------------+----------+---------------+---------------+-----------------------+----------+----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout                                                                                                                                                                                                     ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout                                                                                                                                                                                  ; Pad To Core Index ; Setting ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; nFB_BURST                                                                                                                                                                                            ;                   ;         ;
-; nACSI_DRQ                                                                                                                                                                                            ;                   ;         ;
-; nACSI_INT                                                                                                                                                                                            ;                   ;         ;
-; nSCSI_DRQ                                                                                                                                                                                            ;                   ;         ;
-; nSCSI_MSG                                                                                                                                                                                            ;                   ;         ;
-; nDCHG                                                                                                                                                                                                ;                   ;         ;
-; SD_DATA0                                                                                                                                                                                             ;                   ;         ;
-; SD_DATA1                                                                                                                                                                                             ;                   ;         ;
-; SD_DATA2                                                                                                                                                                                             ;                   ;         ;
-; SD_CARD_DEDECT                                                                                                                                                                                       ;                   ;         ;
-; SD_WP                                                                                                                                                                                                ;                   ;         ;
-; nDACK0                                                                                                                                                                                               ;                   ;         ;
-; WP_CF_CARD                                                                                                                                                                                           ;                   ;         ;
-; nSCSI_C_D                                                                                                                                                                                            ;                   ;         ;
-; nSCSI_I_O                                                                                                                                                                                            ;                   ;         ;
-; nFB_CS3                                                                                                                                                                                              ;                   ;         ;
-; TOUT0                                                                                                                                                                                                ;                   ;         ;
-; nMASTER                                                                                                                                                                                              ;                   ;         ;
-; FB_AD[31]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[15]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[7]                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~32                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7]                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[31]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[7]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[15]                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~1                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28                                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[31]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~feeder                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[30]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[14]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[30]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[6]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[30]~0                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[14]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6]                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[6]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[14]                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[30]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[30]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[14]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[30]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[30]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~7                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28                                                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1feeder                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[14]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[30]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[6]~feeder                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[6]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[29]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[13]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                                                                            ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[29]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[29]~2                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[5]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[13]                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[29]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[13]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[29]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~6                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]~feeder                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[29]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[13]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[29]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[28]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[12]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[28]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[4]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[28]~3                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~4                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[12]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[4]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[12]                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[28]                                                                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[28]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[28]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[28]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[12]                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[28]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]~feeder                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[4]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[12]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[28]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[28]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[27]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[11]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[3]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[3]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[3]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[27]~4                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~5                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[3]                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[3]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[11]                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[11]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[27]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[27]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[11]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]~feeder                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]~feeder                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[27]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~feeder                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[11]~feeder                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[26]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                  ; 1                 ; 0       ;
-;      - SRD[10]~output                                                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[2]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[2]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                                                                            ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[26]                                                                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[12]~53                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[26]~5                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~3                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[2]                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[26]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[26]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[2]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[10]                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[26]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[26]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]~feeder                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[10]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]~feeder                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[2]~feeder                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~feeder                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
-; FB_AD[25]                                                                                                                                                                                            ;                   ;         ;
-;      - SRD[9]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[1]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[1]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[1]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1]                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[11]~55                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[1]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[9]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[1]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[25]~6                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~2                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[1]                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[1]                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[25]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[25]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[9]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[25]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[9]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[9]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]~feeder                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[25]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[9]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[9]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
-; FB_AD[24]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                      ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]~22                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - SRD[8]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[0]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[0]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[0]                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[10]~58                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[0]                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0]                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[24]~7                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~0                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[0]                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[24]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[24]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[24]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[8]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0]                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0]                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                        ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]~29                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]~feeder                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]~feeder                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[8]~feeder                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[24]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~feeder                                                                                                               ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]~feeder                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[24]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[8]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[8]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[24]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[24]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]~feeder                                                                                                                 ; 1                 ; 0       ;
-; FB_AD[23]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]~20                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[7]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[7]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[7]~0                                                            ; 1                 ; 0       ;
-;      - SRD[7]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[7]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[7]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[9]~60                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~4                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[7]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~10                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[23]~8                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~1                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~1                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[7]                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]                                                                                                                 ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[23]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[23]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][10]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][20]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][21]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][23]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][26]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][34]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][35]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][37]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][42]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][46]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][45]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][50]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][54]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][58]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][57]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][61]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[7]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[7]                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[7]                                                                            ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][0]~73                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][2]~74                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][4]~75                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~10                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[7]                                                                       ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]~5                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[7]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[7]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~24                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~24                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[7]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~feeder                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][19]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[23]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]~feeder                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[7]~feeder                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[22]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]~18                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[6]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[6]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[6]~0                                                             ; 1                 ; 0       ;
-;      - SRD[6]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[6]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[6]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[8]~62                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~2                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[6]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~8                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]~9                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[6]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~2                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~2                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[6]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[22]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[6]                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[22]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[22]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][7]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][11]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][17]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][21]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][23]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][25]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][33]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][38]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][41]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][46]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][47]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][50]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][53]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][55]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][58]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][57]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][61]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][62]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[6]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[6]                                                                           ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][0]~78                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][2]~79                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][4]~80                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[6]~12                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[6]                                                                       ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]~9                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[6]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~30                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~30                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[6]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][63]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][32]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][56]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[6][18]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]~feeder                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[6]~feeder                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[6]~feeder                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[6]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[22]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]~feeder                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[6]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[5]~feeder                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[6]~feeder                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[6]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[6]~feeder                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[21]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]~16                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[5]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[5]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[5]~1                                                             ; 1                 ; 0       ;
-;      - SRD[5]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[5]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[7]~64                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[5]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[5]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~6                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~14                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]~10                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[5]                                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[5]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~3                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~3                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[5]                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[21]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5]                                                                                                                 ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[21]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[21]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[21]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][17]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][40]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][43]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][35]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][47]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][7]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][15]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][58]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][55]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][51]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][60]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[5]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[5]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[5]                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[5]                                                                            ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][2]~82                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][4]~83                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][0]~85                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[5]~15                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[5]                                                                       ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]~12                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[5]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~36                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~36                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[5]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[5]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[5]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[5]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]~feeder                                                                            ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][9]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[5]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[5]~feeder                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5]~feeder                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]~feeder                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]~feeder                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[5]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[5][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[20]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]~14                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[4]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[4]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]~2                                                             ; 1                 ; 0       ;
-;      - SRD[4]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[4]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[6]~66                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[4]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[4]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[4]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[4]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~8                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~12                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]~11                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[4]                                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[4]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~4                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~4                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[4]                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[20]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4]                                                                                                                 ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[20]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[20]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[20]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][40]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][43]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][35]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][47]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][17]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][7]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][15]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][55]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][51]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][60]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[4]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[4]                                                                           ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][2]~86                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][4]~87                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][0]~89                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[4]~18                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[4]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[4]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~42                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[4]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~42                                                                    ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12]                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]~27                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[4]                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[4]~feeder                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[4]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4]~feeder                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[4]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[3]~feeder                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[20]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[4]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[20]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[4]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[4]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]~feeder                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[4][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[4]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[19]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]~12                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[3]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[3]~3                                                             ; 1                 ; 0       ;
-;      - SRD[3]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[3]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[5]~68                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[3]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[3]                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~10                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[3]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~16                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]~12                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[3]                                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[3]                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~7                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~5                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[3]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[3]                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[3]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[3]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3]                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[3]                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[19]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[19]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][17]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][40]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][43]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][35]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][47]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][10]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][8]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][7]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][15]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][55]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][51]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][60]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[3]                                                                                                                     ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[3]~21                                 ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][2]~90                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][4]~91                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][0]~93                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[3]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~47                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[3]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~47                                                                    ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]~24                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3]                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]~feeder                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[3]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[19]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[3]~feeder                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[19]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[3]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][61]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][27]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][26]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][46]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][11]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][5]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][9]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[3][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[3]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[3]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[3]~feeder                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[3]~feeder                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[18]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0                                                                 ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]~10                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[2]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[2]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[2]~4                                                             ; 1                 ; 0       ;
-;      - SRD[2]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~4                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[2]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[2]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[4]~70                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[2]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[18]                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~4                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[2]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~12                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]~13                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[2]                                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[2]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[2]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[18]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[18]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][21]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][24]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][26]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][27]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][33]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][35]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][37]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][39]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][41]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][46]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][50]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][49]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][51]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][54]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][57]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][59]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][61]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[2]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[2]                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[2]                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[2]                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~8                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~6                                                                ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][0]~69                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][2]~70                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][4]~71                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[2]~9                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[2]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[2]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~18                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[2]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~18                                                                    ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]~21                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[2]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][60]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][40]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[2]~feeder                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][58]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][34]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][6]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][36]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][42]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][52]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[2][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[2]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]~feeder                                                        ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]~feeder                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]~feeder                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]~feeder                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[2]~feeder                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[17]                                                                                                                                                                                            ;                   ;         ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[1]~5                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[1]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[1]                                                                    ; 1                 ; 0       ;
-;      - SRD[1]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~0                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[1]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[1]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[3]~72                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[1]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[1]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~2                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~14                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]~14                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[1]                                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[1]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[17]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[17]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[1]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[1]                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[17]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[17]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[17]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][15]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][19]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][21]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][23]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][26]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][27]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][29]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][31]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][34]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][37]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][40]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][42]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][43]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][46]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][47]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][49]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][51]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][53]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][55]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][58]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][60]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][61]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][62]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[1]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[1]                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~6                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~7                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][0]~65                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][2]~66                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][4]~67                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[1]~6                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[1]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~12                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[1]                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~12                                                                    ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]~18                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[1]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[1]~feeder                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][59]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][50]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][48]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][30]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[1]~feeder                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][20]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][22]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[1]~feeder                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[1]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[1]~feeder                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[1]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][56]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][63]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][44]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][54]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][52]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][38]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][10]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][14]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][32]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][24]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][39]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[1][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[17]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[1]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[17]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]~feeder                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]~feeder                                                                                                           ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]~feeder                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]~feeder                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[16]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[0]~6                                                             ; 1                 ; 0       ;
-;      - SRD[0]~output                                                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VWE                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[16]                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[2]~74                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~6                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~16                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[0]                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[0]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[0]                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[16]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[0]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][10]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][16]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][18]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][20]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][22]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][24]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][26]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][27]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][28]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][30]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][32]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][34]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][36]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][38]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][40]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][42]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][44]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][46]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][48]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][50]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][52]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][54]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][56]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][58]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][60]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][61]                                                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][63]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[0]                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[0]                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0]                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[0]                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~5                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~8                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]~2                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][0]~0                                                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][2]~3                                                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][4]~6                                                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][13]~12                                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~6                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~6                                                                     ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~15                                                                                   ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8]                                                                                    ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][59]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][12]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][51]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][17]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][7]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][37]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][25]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][29]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][41]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][35]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][15]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[16]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][31]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][57]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][43]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][47]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][23]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][39]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][49]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][33]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][45]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][62]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][53]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][55]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~feeder                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[16]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]~feeder                                                                                                          ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]~feeder                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][21]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][8]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][19]~feeder                                                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~feeder                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~feeder                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~feeder                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[0]~feeder                                                                                                          ; 1                 ; 0       ;
-; FB_AD[15]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[1]~76                                                                                                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[15]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[15]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[15]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[14]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[0]~78                                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]~0                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[14]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[14]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[14]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[14]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[13]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[1]~9                                                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~5                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[13]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[13]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[13]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[13]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[13]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[13]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[13]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[13]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[12]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[0]~11                                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]~1                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[12]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[12]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[12]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[12]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[12]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[12]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[12]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[11]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]~2                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[11]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[11]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[11]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[11]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[11]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[11]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[11]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[11]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[10]                                                                                                                                                                                            ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~4                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[10]                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10]                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[10]                                                                                                                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[10]                                                                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]~feeder                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]~feeder                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[10]~feeder                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]~feeder                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[9]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]~8                                                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[9]~0                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[9]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[9]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[9]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[9]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[9]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-; FB_AD[8]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]~13                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]~23                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[8]~1                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[8]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[8]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[8]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[8]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[8]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-; FB_AD[7]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~16                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]~24                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[7]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[7]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[7]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[6]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]~23                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[6]~25                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[6]~2                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[6]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[6]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[6]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[6]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[6]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[5]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]~26                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[5]~26                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[5]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[5]~3                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[5]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[5]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[5]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[5]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[5]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[4]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]~29                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[4]~27                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[4]~4                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[4]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[4]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4]                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[4]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[4]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[4]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[3]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]~32                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[3]~28                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[3]~5                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[3]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[3]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[3]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[2]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]~35                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[2]~29                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[2]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[2]~6                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[2]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[2]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[2]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[2]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[1]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]~41                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]~30                                                                                                               ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[1]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[1]~7                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[1]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[1]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[1]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[1]                                                                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[1]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]~feeder                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-; FB_AD[0]                                                                                                                                                                                             ;                   ;         ;
-;      - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]~43                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[0]~31                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[0]~8                                                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[0]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0]                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[0]                                                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~5                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                         ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[0]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[0]~feeder                                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]~feeder                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]~feeder                                                                                                                  ; 1                 ; 0       ;
-; VD[31]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]~feeder                                                       ; 0                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]~feeder                                                       ; 0                 ; 1       ;
-; VD[30]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]~feeder                                                       ; 1                 ; 1       ;
-; VD[29]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]~feeder                                                       ; 1                 ; 1       ;
-; VD[28]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]~feeder                                                       ; 1                 ; 1       ;
-; VD[27]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]~feeder                                                       ; 1                 ; 1       ;
-; VD[26]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]~feeder                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]~feeder                                                       ; 1                 ; 0       ;
-; VD[25]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]~feeder                                                       ; 0                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]~feeder                                                       ; 0                 ; 1       ;
-; VD[24]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]~feeder                                                       ; 1                 ; 1       ;
-; VD[23]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]~feeder                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]~feeder                                                       ; 0                 ; 0       ;
-; VD[22]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]~feeder                                                       ; 1                 ; 1       ;
-; VD[21]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]~feeder                                                       ; 1                 ; 1       ;
-; VD[20]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]~feeder                                                       ; 1                 ; 1       ;
-; VD[19]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]~feeder                                                       ; 0                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]~feeder                                                       ; 0                 ; 1       ;
-; VD[18]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]~feeder                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]~feeder                                                       ; 0                 ; 0       ;
-; VD[17]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]~feeder                                                       ; 1                 ; 1       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]~feeder                                                       ; 1                 ; 1       ;
-; VD[16]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]~feeder                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]~feeder                                                       ; 0                 ; 0       ;
-; VD[15]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]~feeder                                                       ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]~feeder                                                       ; 0                 ; 2       ;
-; VD[14]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]~feeder                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]~feeder                                                       ; 1                 ; 0       ;
-; VD[13]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]~feeder                                                       ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]~feeder                                                       ; 0                 ; 2       ;
-; VD[12]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]~feeder                                                       ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]~feeder                                                       ; 0                 ; 2       ;
-; VD[11]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]~feeder                                                       ; 1                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]~feeder                                                       ; 1                 ; 2       ;
-; VD[10]                                                                                                                                                                                               ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]~feeder                                                       ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]~feeder                                                       ; 0                 ; 2       ;
-; VD[9]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]~feeder                                                        ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]~feeder                                                        ; 0                 ; 2       ;
-; VD[8]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]~feeder                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]~feeder                                                        ; 0                 ; 0       ;
-; VD[7]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]~feeder                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]~feeder                                                        ; 0                 ; 0       ;
-; VD[6]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]~feeder                                                        ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]~feeder                                                        ; 0                 ; 2       ;
-; VD[5]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]~feeder                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]~feeder                                                        ; 0                 ; 0       ;
-; VD[4]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]~feeder                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]~feeder                                                        ; 0                 ; 0       ;
-; VD[3]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]~feeder                                                        ; 1                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]~feeder                                                        ; 1                 ; 2       ;
-; VD[2]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]~feeder                                                        ; 1                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]~feeder                                                        ; 1                 ; 2       ;
-; VD[1]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]~feeder                                                        ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]~feeder                                                        ; 0                 ; 2       ;
-; VD[0]                                                                                                                                                                                                ;                   ;         ;
-;      - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]~feeder                                                        ; 0                 ; 2       ;
-;      - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]~feeder                                                        ; 0                 ; 2       ;
-; VDQS[3]                                                                                                                                                                                              ;                   ;         ;
-; VDQS[2]                                                                                                                                                                                              ;                   ;         ;
-; VDQS[1]                                                                                                                                                                                              ;                   ;         ;
-; VDQS[0]                                                                                                                                                                                              ;                   ;         ;
-; IO[17]                                                                                                                                                                                               ;                   ;         ;
-; IO[16]                                                                                                                                                                                               ;                   ;         ;
-; IO[15]                                                                                                                                                                                               ;                   ;         ;
-; IO[14]                                                                                                                                                                                               ;                   ;         ;
-; IO[13]                                                                                                                                                                                               ;                   ;         ;
-; IO[12]                                                                                                                                                                                               ;                   ;         ;
-; IO[11]                                                                                                                                                                                               ;                   ;         ;
-; IO[10]                                                                                                                                                                                               ;                   ;         ;
-; IO[9]                                                                                                                                                                                                ;                   ;         ;
-; IO[8]                                                                                                                                                                                                ;                   ;         ;
-; IO[7]                                                                                                                                                                                                ;                   ;         ;
-; IO[6]                                                                                                                                                                                                ;                   ;         ;
-; IO[5]                                                                                                                                                                                                ;                   ;         ;
-; IO[4]                                                                                                                                                                                                ;                   ;         ;
-; IO[3]                                                                                                                                                                                                ;                   ;         ;
-; IO[2]                                                                                                                                                                                                ;                   ;         ;
-; IO[1]                                                                                                                                                                                                ;                   ;         ;
-; IO[0]                                                                                                                                                                                                ;                   ;         ;
-; SRD[15]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~156                                                                                                                   ; 1                 ; 0       ;
-; SRD[14]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~131                                                                                                                   ; 1                 ; 0       ;
-; SRD[13]                                                                                                                                                                                              ;                   ;         ;
-;      - DSP:Mathias_Alles|FB_AD[29]~3                                                                                                                                                                 ; 0                 ; 0       ;
-; SRD[12]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369                                                                                                                   ; 0                 ; 0       ;
-; SRD[11]                                                                                                                                                                                              ;                   ;         ;
-;      - DSP:Mathias_Alles|FB_AD[27]~4                                                                                                                                                                 ; 0                 ; 0       ;
-; SRD[10]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~197                                                                                                                   ; 1                 ; 0       ;
-; SRD[9]                                                                                                                                                                                               ;                   ;         ;
-;      - DSP:Mathias_Alles|FB_AD[25]~0                                                                                                                                                                 ; 1                 ; 0       ;
-; SRD[8]                                                                                                                                                                                               ;                   ;         ;
-;      - DSP:Mathias_Alles|FB_AD[24]~1                                                                                                                                                                 ; 1                 ; 0       ;
-; SRD[7]                                                                                                                                                                                               ;                   ;         ;
-;      - DSP:Mathias_Alles|FB_AD[23]~2                                                                                                                                                                 ; 0                 ; 0       ;
-; SRD[6]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~269                                                                                                                   ; 1                 ; 0       ;
-; SRD[5]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~285                                                                                                                   ; 0                 ; 0       ;
-; SRD[4]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~301                                                                                                                   ; 1                 ; 0       ;
-; SRD[3]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~319                                                                                                                   ; 1                 ; 0       ;
-; SRD[2]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~172                                                                                                                   ; 0                 ; 0       ;
-; SRD[1]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~86                                                                                                                    ; 1                 ; 0       ;
-; SRD[0]                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54                                                                                                                    ; 0                 ; 0       ;
-; SCSI_PAR                                                                                                                                                                                             ;                   ;         ;
-; nSCSI_SEL                                                                                                                                                                                            ;                   ;         ;
-; nSCSI_BUSY                                                                                                                                                                                           ;                   ;         ;
-; nSCSI_RST                                                                                                                                                                                            ;                   ;         ;
-; SD_CD_DATA3                                                                                                                                                                                          ;                   ;         ;
-; SD_CMD_D1                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[7]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[6]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[5]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[4]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[3]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[2]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[1]                                                                                                                                                                                            ;                   ;         ;
-; ACSI_D[0]                                                                                                                                                                                            ;                   ;         ;
-; LP_D[7]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~142                                                                                                                   ; 1                 ; 0       ;
-; LP_D[6]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~112                                                                                                                   ; 0                 ; 0       ;
-; LP_D[5]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~339                                                                                                                   ; 0                 ; 0       ;
-; LP_D[4]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~378                                                                                                                   ; 0                 ; 0       ;
-; LP_D[3]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~383                                                                                                                   ; 1                 ; 0       ;
-; LP_D[2]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~186                                                                                                                   ; 1                 ; 0       ;
-; LP_D[1]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~206                                                                                                                   ; 0                 ; 0       ;
-; LP_D[0]                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~227                                                                                                                   ; 0                 ; 0       ;
-; SCSI_D[7]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[6]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[5]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[4]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[3]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[2]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[1]                                                                                                                                                                                            ;                   ;         ;
-; SCSI_D[0]                                                                                                                                                                                            ;                   ;         ;
-; nRSTO_MCF                                                                                                                                                                                            ;                   ;         ;
-; nFB_WR                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS                                                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SUB_BUS~0                                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|TIN0~0                                                                                                                                                               ; 1                 ; 0       ;
-;      - DSP:Mathias_Alles|nSRWE~0                                                                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPIO_REGISTERS~0                                                                  ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~1                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector0~0                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0                                                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~11                                                                                                                                                   ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~0                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~0                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~1                                                                                                                                              ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[31]~0                                                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|Selector1~4                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~1                                                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0                                                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~1                                                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[7]~0                                                                                                                                                         ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~19                                                                                                                                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0                                                                                         ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~1                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1                                                                                                               ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CONTROL~0                                              ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE~1                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0                                                               ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0                                                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1                                                              ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0                                                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~0                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~0                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~1                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~5                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~11                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~15                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT_EN~1                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~0                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR_READ~0                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~1                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR_READ~0                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~1                                                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~0                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_EN~1                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|Mux1~0                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~2                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~3                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DATA_EN~0                                              ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0                                                          ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~1                                                                                                              ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~0                                                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~0                                                                ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0                                                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[9]~0                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[8]~1                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[6]~2                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[5]~3                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[4]~4                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[3]~5                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[2]~6                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[1]~7                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR[0]~8                                                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~4                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~5                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~6                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT~5                                                                                               ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~9                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~10                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~14                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~15                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~17                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~218                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~42                                                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~238                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~1                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~35                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~37                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~40                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~350                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[3]~1                                                                                      ; 0                 ; 0       ;
-;      - DSP:Mathias_Alles|nSRWE~1                                                                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]~1                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~0                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nFDC_WR~0                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[23]~1                                                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[23]~1                                                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|RTC_ADR[5]~0                                                                                                                                                         ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~491                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[0][0]~1                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][1]~2                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~492                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][3]~5                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~496                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][5]~9                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~503                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~504                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|_~505                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|_~506                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][10]~10                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][12]~11                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][13]~13                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][14]~15                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][15]~16                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][16]~17                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][17]~18                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][18]~19                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][19]~20                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][20]~21                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][21]~22                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][22]~23                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][23]~24                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][24]~25                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][25]~26                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][26]~27                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][27]~28                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][28]~29                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][29]~30                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][30]~31                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][31]~32                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][32]~33                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][33]~34                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][34]~35                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][35]~36                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][36]~37                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][37]~38                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][38]~39                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][39]~40                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][40]~41                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][41]~42                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][42]~43                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][43]~44                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][44]~45                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][45]~46                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][46]~47                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][47]~48                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][48]~49                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][49]~50                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][50]~51                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][51]~52                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][52]~53                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][53]~54                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][54]~55                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][55]~56                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][56]~57                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][57]~58                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][58]~59                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][59]~60                                                                                                                                                      ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][60]~61                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][61]~62                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][62]~63                                                                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][63]~64                                                                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0                                                                         ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0                                                                          ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~2                                                                                                    ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[15]~2                                                                                                                                                       ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0                                                                                                                    ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0]                                                                                                          ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1                                                                                                              ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[31]~3                                                                                                                                                        ; 0                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~0                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~4                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7                                                                                                              ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[7]~3                                                                                                                                                         ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]~0                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_WR~0                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                                         ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_RECONFIG~0                                                                                                           ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|WERTE[7][11]~77                                                                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3                                                                                                              ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0                                                                                            ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_2~0                                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3]                                                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2                                                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3                                                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4                                                                                                                                             ; 0                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state~2                                                                          ; 1                 ; 0       ;
-;      - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state~0                                                                                  ; 1                 ; 0       ;
-; nFB_CS1                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS                                                                                                                          ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_CS                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|TIN0~0                                                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE_CS                                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~2                                                                                                             ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT_CS~2                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF_CS                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW_CS~0                                                                                                                    ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|UHR_DS~3                                                                                                                                                             ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|MFP_CS~1                                                                                                                        ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|_~3                                                                                                                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|NEXT_CMD_STATE.T1~0                                                                                                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector2~0                                                                                                                     ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~28                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~32                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~7                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_M                                                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_H                                                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~6                                                                                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~8                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~36                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~37                                                                                                                                                   ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~38                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~39                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~27                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~40                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~41                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[9]~81                                                          ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~43                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~38                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~44                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~45                                                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|TIN0~1                                                                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_L                                                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~46                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~47                                                                                                                                                   ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~48                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~49                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~50                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~51                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~52                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~53                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~54                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~55                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0                                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1                                                                                                     ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7                                                                                                              ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                                         ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~34                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~35                                                                                       ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59                                                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[2]~36                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0                                                                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS                                                                                                                           ; 1                 ; 0       ;
-; FB_SIZE1                                                                                                                                                                                             ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1                                                                                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|FB_B[0]~0                                                                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1                                                                                                                  ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|_~22                                                                                                                                                                 ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20                                                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|UHR_AS~0                                                                                                                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|UHR_DS~6                                                                                                                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~194                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|FB_B[2]~1                                                                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2]                                                                                                                    ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0]                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0                                                                                                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                                              ; 1                 ; 0       ;
-; FB_SIZE0                                                                                                                                                                                             ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0                                                                                                                                                 ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3                                                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1                                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0                                                                                                                     ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|FB_B[0]~0                                                                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1                                                                                                                  ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~22                                                                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20                                                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0                                                                                                                    ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|UHR_AS~0                                                                                                                                                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|UHR_DS~6                                                                                                                                                             ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|_~194                                                                                                                                                                ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|FB_B[2]~1                                                                                                                                                            ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2]                                                                                                                    ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0]                                                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0                                                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22                                                                                                               ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0                                                                                                                                              ; 0                 ; 0       ;
-; FB_ALE                                                                                                                                                                                               ;                   ;         ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                                                                                 ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL                                                                                                                                                ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5                                                                                                                                                    ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                                                                                 ; 1                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                                                                                ; 0                 ; 0       ;
-;      - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5                                                                                                                                             ; 1                 ; 0       ;
-; nFB_CS2                                                                                                                                                                                              ;                   ;         ;
-;      - DSP:Mathias_Alles|nSRCS~0                                                                                                                                                                     ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~4                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_RECONFIG_CS~0                                                                                                    ; 0                 ; 0       ;
-;      - inst2~3                                                                                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0                                                                                                             ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1                                                                                                              ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_CONFIG_CS~0                                                                                                      ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA_CS                                                                                                                                                           ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR_CS                                                                                                                                                           ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~23                                                                                                                                                                 ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF_CS                                                                                                                                                          ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~25                                                                                                                                                                 ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH_CS                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH_CS                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL_CS                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL_CS                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~2                                                                                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~3                                                                                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR_CS                                                                                                                     ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~13                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~14                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~147                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~148                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR_CS                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CLEAR_CS                                                                                                                                                         ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~195                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~196                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~198                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~199                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2                                                                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~200                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~201                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~24                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~25                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~246                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~247                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~35                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~41                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~42                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~248                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~46                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~47                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~295                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~53                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~54                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~338                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~339                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~60                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~61                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~382                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~383                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~67                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~68                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~426                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~427                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~470                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~471                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~473                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~474                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~71                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~475                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~476                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~73                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~74                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~477                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~75                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~76                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~480                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~77                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~78                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~79                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~80                                                                                                                       ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~483                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~484                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~485                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~486                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~487                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~488                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~489                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~490                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0                                                                                                                  ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1                                                                                                                  ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3                                                                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_CTR[15]~2                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|INT_ENA[15]~2                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~508                                                                                                                                                                ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34                                                                                             ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42                                                                                             ; 0                 ; 0       ;
-; MAIN_CLK                                                                                                                                                                                             ;                   ;         ;
-; nDACK1                                                                                                                                                                                               ;                   ;         ;
-; nFB_OE                                                                                                                                                                                               ;                   ;         ;
-;      - DSP:Mathias_Alles|nSROE~0                                                                                                                                                                     ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31                                                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~39                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~40                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~43                                                                                                                        ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[0]~0                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~45                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~47                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~48                                                                                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_RD                                                                                                                 ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_RD                                                                                                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~51                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[3]~2                                                                                                                                           ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[0]~3                                                                                                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~55                                                                                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~56                                                                                                                        ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[1]~4                                                                                                                                           ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[2]~5                                                                                                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~59                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~60                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~61                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~65                                                                                                                    ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~10                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~67                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~70                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~72                                                                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~77                                                                                                                    ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[3]~28                                                          ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[1]~3                                                                                                      ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~85                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~89                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~94                                                                                                                        ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19                                                                                                                       ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~111                                                                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~124                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~127                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~129                                                                                                                   ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDH                                                                                                            ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[14]~34                                                         ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[15]~40                                                         ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~154                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~160                                                                                                                   ; 1                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[2]~6                                                                                                      ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDL~0                                                                                                          ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~170                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~175                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~176                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~179                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~181                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~182                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~193                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~195                                                                                                                   ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~211                                                                                                                   ; 0                 ; 0       ;
-;      - DSP:Mathias_Alles|FB_AD[25]~0                                                                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~215                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~220                                                                                                                   ; 0                 ; 0       ;
-;      - DSP:Mathias_Alles|FB_AD[24]~1                                                                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~235                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~240                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[7]~9                                                                                                      ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~250                                                                                                                   ; 0                 ; 0       ;
-;      - DSP:Mathias_Alles|FB_AD[23]~2                                                                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~255                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[6]~12                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~267                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~272                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[5]~15                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~283                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~288                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[4]~18                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~299                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~304                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~308                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~312                                                                                                                   ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[3]~21                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~317                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[15]~327                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~352                                                                                                                   ; 0                 ; 0       ;
-;      - DSP:Mathias_Alles|FB_AD[29]~3                                                                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~356                                                                                                                   ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[13]~173                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~366                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~375                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~388                                                                                                                   ; 1                 ; 0       ;
-;      - DSP:Mathias_Alles|FB_AD[27]~4                                                                                                                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~392                                                                                                                   ; 1                 ; 0       ;
-;      - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[11]~186                                                        ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~411                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~415                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~420                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~424                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[7]~432                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[6]~437                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[5]~445                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[4]~453                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[3]~461                                                                                                                    ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[2]~469                                                                                                                    ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|_~508                                                                                                                                                                ; 0                 ; 0       ;
-;      - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59                                                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~490                                                                                                                   ; 1                 ; 0       ;
-; IDE_RDY                                                                                                                                                                                              ;                   ;         ;
-;      - inst2~1                                                                                                                                                                                       ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~0                                                                                                                     ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_TA~0                                                                                                                     ; 1                 ; 0       ;
-; CLK33M                                                                                                                                                                                               ;                   ;         ;
-; HD_DD                                                                                                                                                                                                ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|HD_DD_OUT~0                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~62                                                                                                                    ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PHASE_DECODER~0                                                       ; 1                 ; 0       ;
-; nINDEX                                                                                                                                                                                               ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~1                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~2                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~78                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOCK~0                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK~1                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~113                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~173                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_COUNTER~2                                                               ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ~4                                                                       ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~205                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK~0                                                         ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DRQ_IPn~0                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_INDEX_MARK:LOCK~0                                                          ; 0                 ; 0       ;
-;      - nINDEX~_wirecell                                                                                                                                                                              ; 0                 ; 0       ;
-; RxD                                                                                                                                                                                                  ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|SDATA_IN_I~1                                                                ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SDATA_IN_I~2                             ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_SAMPLE~6                               ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_START_BIT~0                            ; 0                 ; 0       ;
-; nWP                                                                                                                                                                                                  ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~85                                                                  ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~168                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~176                                                                 ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR~0                                                                       ; 1                 ; 0       ;
-; LP_BUSY                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[0]~20                                                                                          ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~15                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~15                                                               ; 0                 ; 0       ;
-; DCD                                                                                                                                                                                                  ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[1]~43                                                                                          ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~10                                                           ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~10                                                               ; 0                 ; 0       ;
-; CTS                                                                                                                                                                                                  ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[2]~63                                                                                          ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~9                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~9                                                                ; 1                 ; 0       ;
-; TRACK00                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TR_CLR                                                                        ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~18                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~20                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~22                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~24                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~26                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~28                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~103                                                                 ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~2                                                              ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~3                                                              ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30                                                                   ; 0                 ; 0       ;
-; IDE_INT                                                                                                                                                                                              ;                   ;         ;
-; RI                                                                                                                                                                                                   ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~11                                                           ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT~104                                                                                            ; 1                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~11                                                               ; 1                 ; 0       ;
-; nPCI_INTD                                                                                                                                                                                            ;                   ;         ;
-;      - interrupt_handler:nobody|INT_LATCH[6]~11                                                                                                                                                      ; 0                 ; 6       ;
-;      - interrupt_handler:nobody|_~484                                                                                                                                                                ; 1                 ; 0       ;
-; nPCI_INTC                                                                                                                                                                                            ;                   ;         ;
-;      - interrupt_handler:nobody|INT_LATCH[5]~12                                                                                                                                                      ; 1                 ; 6       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[5]~5                                                                                                      ; 0                 ; 0       ;
-; nPCI_INTB                                                                                                                                                                                            ;                   ;         ;
-;      - interrupt_handler:nobody|INT_LATCH[4]~13                                                                                                                                                      ; 0                 ; 6       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[4]~8                                                                                                      ; 1                 ; 0       ;
-; nPCI_INTA                                                                                                                                                                                            ;                   ;         ;
-;      - interrupt_handler:nobody|INT_LATCH[3]~14                                                                                                                                                      ; 1                 ; 6       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[3]~11                                                                                                     ; 0                 ; 0       ;
-; DVI_INT                                                                                                                                                                                              ;                   ;         ;
-; E0_INT                                                                                                                                                                                               ;                   ;         ;
-; PIC_INT                                                                                                                                                                                              ;                   ;         ;
-;      - interrupt_handler:nobody|INT_LATCH[0]~17                                                                                                                                                      ; 1                 ; 6       ;
-;      - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[0]~20                                                                                                     ; 0                 ; 0       ;
-;      - interrupt_handler:nobody|PIC_INT_SYNC[0]                                                                                                                                                      ; 0                 ; 0       ;
-; PIC_AMKB_RX                                                                                                                                                                                          ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|KEYB_RxD                                                                                                                        ; 0                 ; 1       ;
-; MIDI_IN                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_I~feeder                                                    ; 1                 ; 1       ;
-; nRD_DATA                                                                                                                                                                                             ;                   ;         ;
-; AMKB_RX                                                                                                                                                                                              ;                   ;         ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~11                                                                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14                                                                                                                  ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]~9                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]~7                                                                                                                   ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]                                                                                                                     ; 0                 ; 0       ;
-;      - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13                                                                                                                  ; 1                 ; 0       ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals                                                                                                                                                                                                                                                                                                                        ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
-; Name                                                                                                                                                                         ; Location               ; Fan-Out ; Usage                                 ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
-; CLK33M                                                                                                                                                                       ; PIN_AB12               ; 12      ; Clock                                 ; yes    ; Global Clock         ; GCLK15           ; --                        ;
-; CLK33M                                                                                                                                                                       ; PIN_AB12               ; 5       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; DSP:Mathias_Alles|nSRWE~1                                                                                                                                                    ; LCCOMB_X23_Y8_N20      ; 16      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FB_ALE                                                                                                                                                                       ; PIN_R7                 ; 33      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13                                                                                                 ; LCCOMB_X1_Y10_N14      ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO                                                                                                       ; LCCOMB_X26_Y22_N16     ; 250     ; Async. clear                          ; yes    ; Global Clock         ; GCLK7            ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1                                                                                              ; LCCOMB_X18_Y17_N18     ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1                                                                                                   ; LCCOMB_X22_Y14_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1                                                                                                   ; LCCOMB_X22_Y14_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~0                                                                                                 ; LCCOMB_X16_Y14_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]~1                                                                                                 ; LCCOMB_X16_Y14_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104                                                                                                  ; LCCOMB_X21_Y12_N8      ; 16      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78                                                                                                   ; LCCOMB_X22_Y13_N12     ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183                                                                                                  ; LCCOMB_X22_Y13_N30     ; 4       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259                                                                                                  ; LCCOMB_X22_Y13_N4      ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203                                                                                                  ; LCCOMB_X22_Y13_N16     ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224                                                                                                  ; LCCOMB_X22_Y13_N10     ; 2       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141                                                                                                  ; LCCOMB_X33_Y1_N4       ; 5       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector4~1                                                                                                    ; LCCOMB_X23_Y18_N0      ; 20      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~1                                                                                                   ; LCCOMB_X22_Y13_N2      ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|Equal0~4                                             ; LCCOMB_X22_Y28_N30     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]~1                                           ; LCCOMB_X21_Y28_N6      ; 16      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]~3                               ; LCCOMB_X21_Y28_N12     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SHFT                                       ; FF_X34_Y29_N7          ; 26      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SHFT_LOAD_ND~0                                               ; LCCOMB_X28_Y27_N8      ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47                                                ; LCCOMB_X35_Y25_N2      ; 88      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector78~0                                                 ; LCCOMB_X32_Y25_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor2~5                                                   ; LCCOMB_X36_Y28_N0      ; 33      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor8                                                     ; LCCOMB_X28_Y27_N6      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]~1                                  ; LCCOMB_X32_Y27_N4      ; 8       ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]~37                                          ; LCCOMB_X27_Y26_N22     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT~27                                           ; LCCOMB_X30_Y30_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE                                             ; FF_X30_Y32_N13         ; 18      ; Clock enable, Sync. load              ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]~1                     ; LCCOMB_X27_Y32_N24     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]                                           ; FF_X32_Y25_N31         ; 20      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]~1                                         ; LCCOMB_X32_Y25_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Equal3~2                                                 ; LCCOMB_X27_Y25_N14     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~1                                              ; LCCOMB_X29_Y25_N2      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]~9                                           ; LCCOMB_X28_Y27_N26     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG~8                                              ; LCCOMB_X30_Y28_N22     ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~1                                               ; LCCOMB_X30_Y26_N20     ; 9       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]~3                                           ; LCCOMB_X30_Y26_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT~1                                            ; LCCOMB_X28_Y30_N28     ; 31      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT~12                                            ; LCCOMB_X36_Y29_N10     ; 4       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK~0                                     ; LCCOMB_X25_Y29_N26     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]~0                             ; LCCOMB_X25_Y27_N6      ; 23      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1                                                                        ; LCCOMB_X18_Y19_N22     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0                                                                           ; LCCOMB_X15_Y14_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1                                                                ; FF_X4_Y41_N5           ; 8       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0                                                                           ; LCCOMB_X7_Y39_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0                                                                          ; LCCOMB_X19_Y23_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WAV_STRB                                                                              ; FF_X9_Y21_N23          ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0                                                ; LCCOMB_X17_Y22_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET                                                    ; FF_X18_Y22_N21         ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0                                                  ; LCCOMB_X18_Y22_N20     ; 9       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0                                               ; LCCOMB_X18_Y24_N0      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB~1                                                   ; LCCOMB_X18_Y23_N8      ; 19      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal14~3                                                    ; LCCOMB_X20_Y21_N28     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal16~3                                                    ; LCCOMB_X19_Y24_N20     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal18~3                                                    ; LCCOMB_X18_Y20_N28     ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0                                            ; LCCOMB_X15_Y14_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1                                             ; LCCOMB_X20_Y23_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0                                            ; LCCOMB_X19_Y24_N30     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1                                             ; LCCOMB_X20_Y20_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0                                            ; LCCOMB_X18_Y20_N2      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1                                             ; LCCOMB_X17_Y18_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0                                                 ; LCCOMB_X17_Y25_N18     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0                                                 ; LCCOMB_X20_Y22_N6      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0                                                 ; LCCOMB_X21_Y27_N0      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0                                              ; LCCOMB_X17_Y19_N26     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT~1                                                  ; LCCOMB_X17_Y25_N24     ; 39      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]~12                                                ; LCCOMB_X18_Y25_N10     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]~0                                 ; LCCOMB_X16_Y24_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]~0                               ; LCCOMB_X16_Y24_N6      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]~2                                 ; LCCOMB_X16_Y24_N24     ; 17      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]~0                         ; LCCOMB_X6_Y18_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1                                      ; LCCOMB_X4_Y19_N12      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]~1                                 ; LCCOMB_X5_Y18_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0                              ; LCCOMB_X2_Y21_N28      ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]~1                                ; LCCOMB_X5_Y17_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]~1                       ; LCCOMB_X1_Y18_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1                                    ; LCCOMB_X1_Y19_N30      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]~1                               ; LCCOMB_X3_Y19_N4       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]~1                              ; LCCOMB_X2_Y19_N2       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE                               ; FF_X1_Y20_N15          ; 13      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]~3                     ; LCCOMB_X1_Y20_N26      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]~1                             ; LCCOMB_X7_Y18_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1                                          ; LCCOMB_X4_Y19_N18      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]~1                                     ; LCCOMB_X5_Y16_N14      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0                                  ; LCCOMB_X3_Y17_N26      ; 6       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]~1                                    ; LCCOMB_X4_Y17_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]~1                           ; LCCOMB_X3_Y17_N22      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1                                        ; LCCOMB_X5_Y20_N0       ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]~1                                   ; LCCOMB_X4_Y21_N6       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]~1                                  ; LCCOMB_X5_Y21_N16      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE                                   ; FF_X6_Y19_N27          ; 12      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]~1                         ; LCCOMB_X6_Y19_N28      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0                                                         ; LCCOMB_X14_Y18_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0                                                         ; LCCOMB_X14_Y14_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0                                                        ; LCCOMB_X14_Y15_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0                                            ; LCCOMB_X14_Y16_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0                                            ; LCCOMB_X14_Y16_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0                                            ; LCCOMB_X16_Y19_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0                                            ; LCCOMB_X16_Y19_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[9]~5                                        ; LCCOMB_X17_Y21_N4      ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST                                    ; FF_X16_Y17_N3          ; 23      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[0]~7                                     ; LCCOMB_X17_Y17_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]~0                                              ; LCCOMB_X16_Y16_N4      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_A~0                                                 ; LCCOMB_X6_Y20_N18      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_B~0                                                 ; LCCOMB_X6_Y20_N8       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_C~0                                                 ; LCCOMB_X3_Y20_N0       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_D~0                                                 ; LCCOMB_X9_Y17_N6       ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0                                                    ; LCCOMB_X12_Y16_N22     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~0                                                    ; LCCOMB_X8_Y20_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0                                                    ; LCCOMB_X10_Y18_N30     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~0                                                    ; LCCOMB_X7_Y17_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0                                                   ; LCCOMB_X12_Y18_N10     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~0                                                    ; LCCOMB_X10_Y15_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]~0                                                    ; LCCOMB_X4_Y15_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERC~1                                                     ; LCCOMB_X10_Y15_N2      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERD~1                                                     ; LCCOMB_X3_Y15_N4       ; 9       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[0]~0                                               ; LCCOMB_X10_Y18_N16     ; 10      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[0]~3                                               ; LCCOMB_X12_Y17_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[0]~1                                               ; LCCOMB_X11_Y18_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[0]~1                                               ; LCCOMB_X11_Y18_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL_STRB                                                    ; FF_X3_Y20_N7           ; 44      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]~0                 ; LCCOMB_X14_Y19_N26     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]~0                 ; LCCOMB_X14_Y22_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]~1                 ; LCCOMB_X14_Y19_N24     ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]~0                 ; LCCOMB_X12_Y16_N8      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7]                   ; FF_X14_Y20_N1          ; 19      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~3                 ; LCCOMB_X11_Y19_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]~2             ; LCCOMB_X10_Y24_N14     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]~1          ; LCCOMB_X10_Y22_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[0]~0 ; LCCOMB_X3_Y27_N20      ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT~1               ; LCCOMB_X14_Y23_N6      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|CLK_STRB               ; FF_X2_Y27_N7           ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFTREG~0             ; LCCOMB_X12_Y21_N12     ; 7       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]~8         ; LCCOMB_X12_Y23_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TX_END                 ; FF_X12_Y23_N17         ; 17      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|_~0                   ; LCCOMB_X21_Y9_N28      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1         ; LCCOMB_X23_Y7_N18      ; 20      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_wrreq~1         ; LCCOMB_X18_Y18_N20     ; 18      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|_~0                   ; LCCOMB_X22_Y22_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_rdreq~1         ; LCCOMB_X22_Y22_N4      ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_wrreq~0         ; LCCOMB_X26_Y24_N4      ; 22      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0                                                                                                   ; LCCOMB_X20_Y16_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0                                                                                                   ; LCCOMB_X20_Y16_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2                                                                                                    ; LCCOMB_X26_Y22_N14     ; 32      ; Async. clear                          ; yes    ; Global Clock         ; GCLK5            ; --                        ;
-; MAIN_CLK                                                                                                                                                                     ; PIN_G2                 ; 2272    ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT                                                                                                                        ; FF_X23_Y12_N17         ; 26      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]~1                                                                                                                  ; LCCOMB_X27_Y6_N0       ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4                                                                                                                            ; LCCOMB_X22_Y2_N22      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2                                                                                                                            ; LCCOMB_X34_Y2_N8       ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3                                                                                                                            ; LCCOMB_X21_Y4_N10      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3]                                                                                                                              ; LCCOMB_X34_Y2_N24      ; 32      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]~40                                                                                                                  ; LCCOMB_X26_Y8_N24      ; 23      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0                                                                                                                   ; LCCOMB_X26_Y11_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0                                                                                                                   ; LCCOMB_X26_Y11_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0                                                                                                                   ; LCCOMB_X25_Y11_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0                                                                                                                   ; LCCOMB_X23_Y11_N24     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[1]                                                                                            ; LCCOMB_X25_Y16_N22     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[2]                                                                                            ; LCCOMB_X25_Y14_N26     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[3]                                                                                            ; LCCOMB_X25_Y16_N0      ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3                                                                                            ; LCCOMB_X22_Y19_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0                                                                                            ; LCCOMB_X23_Y12_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2                                                                                            ; LCCOMB_X27_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1                                                                                             ; LCCOMB_X23_Y18_N22     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6                                                                                             ; LCCOMB_X28_Y18_N22     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1                                                                                            ; LCCOMB_X21_Y19_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0                                                                                            ; LCCOMB_X29_Y14_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2                                                                                            ; LCCOMB_X23_Y14_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3                                                                                             ; LCCOMB_X23_Y14_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1                                                                                            ; LCCOMB_X23_Y19_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0                                                                                            ; LCCOMB_X28_Y15_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2                                                                                            ; LCCOMB_X25_Y17_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3                                                                                             ; LCCOMB_X22_Y17_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1                                                                                            ; LCCOMB_X21_Y19_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0                                                                                            ; LCCOMB_X28_Y15_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2                                                                                            ; LCCOMB_X28_Y17_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3                                                                                             ; LCCOMB_X28_Y17_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1                                                                                            ; LCCOMB_X23_Y19_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0                                                                                            ; LCCOMB_X29_Y12_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2                                                                                            ; LCCOMB_X25_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3                                                                                             ; LCCOMB_X25_Y17_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1                                                                                                 ; LCCOMB_X22_Y18_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0                                                                                                 ; LCCOMB_X29_Y18_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2                                                                                                  ; LCCOMB_X23_Y18_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                                  ; FF_X33_Y18_N13         ; 54      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                                  ; FF_X33_Y18_N15         ; 54      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                                                                                  ; FF_X29_Y21_N3          ; 34      ; Async. clear                          ; yes    ; Global Clock         ; GCLK11           ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_FIFO_CLR                                                                                              ; FF_X36_Y17_N25         ; 21      ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0]                                                                                         ; LCCOMB_X23_Y16_N24     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[1]                                                                                         ; LCCOMB_X23_Y16_N8      ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[3]                                                                                         ; LCCOMB_X23_Y16_N18     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3                                                                                   ; LCCOMB_X28_Y16_N22     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1                                                                                    ; LCCOMB_X28_Y16_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                                  ; FF_X37_Y20_N27         ; 141     ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                      ; FF_X33_Y12_N25         ; 30      ; Clock enable, Sync. clear             ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                                                                                 ; LCCOMB_X26_Y18_N4      ; 3       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                                                                                 ; LCCOMB_X26_Y18_N4      ; 850     ; Clock                                 ; yes    ; Global Clock         ; GCLK6            ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]                                                                                             ; LCCOMB_X26_Y13_N18     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[1]                                                                                             ; LCCOMB_X21_Y13_N14     ; 1       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0                                                                                        ; LCCOMB_X29_Y17_N18     ; 2       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[6]~7                                                                                        ; LCCOMB_X35_Y17_N16     ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX                                                                                                  ; FF_X34_Y14_N13         ; 10      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0                                                                                              ; LCCOMB_X26_Y16_N6      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]~1                                                                                             ; LCCOMB_X30_Y13_N14     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]~0                                                                                              ; LCCOMB_X30_Y13_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~1                                                                                             ; LCCOMB_X30_Y10_N2      ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]~0                                                                                              ; LCCOMB_X29_Y10_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]~1                                                                                             ; LCCOMB_X30_Y10_N12     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]~0                                                                                              ; LCCOMB_X29_Y10_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]~1                                                                                             ; LCCOMB_X33_Y13_N12     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]~0                                                                                              ; LCCOMB_X33_Y13_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]~1                                                                                             ; LCCOMB_X30_Y12_N28     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]~0                                                                                              ; LCCOMB_X30_Y12_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]~1                                                                                             ; LCCOMB_X29_Y14_N22     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]~0                                                                                              ; LCCOMB_X26_Y12_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1                                                                                             ; LCCOMB_X26_Y17_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0                                                                                              ; LCCOMB_X27_Y15_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3                                                                                             ; LCCOMB_X26_Y17_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2                                                                                              ; LCCOMB_X26_Y15_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]~1                                                                                             ; LCCOMB_X30_Y15_N4      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~0                                                                                              ; LCCOMB_X29_Y15_N14     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]~1                                                                                             ; LCCOMB_X25_Y13_N18     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~0                                                                                              ; LCCOMB_X30_Y13_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0                                                                                              ; LCCOMB_X26_Y18_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1                                                                                              ; LCCOMB_X26_Y13_N20     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]~1                                                                                             ; LCCOMB_X29_Y14_N20     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]~0                                                                                              ; LCCOMB_X29_Y13_N4      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]~1                                                                                             ; LCCOMB_X30_Y15_N30     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]~0                                                                                              ; LCCOMB_X29_Y16_N18     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]~1                                                                                             ; LCCOMB_X26_Y14_N6      ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]~0                                                                                              ; LCCOMB_X27_Y16_N2      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0                                                                                              ; LCCOMB_X25_Y18_N26     ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1                                                                                             ; LCCOMB_X27_Y18_N20     ; 3       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0                                                                                              ; LCCOMB_X26_Y16_N0      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~3                                                                                               ; LCCOMB_X27_Y18_N6      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~92                                                                                                      ; LCCOMB_X28_Y20_N4      ; 10      ; Sync. clear                           ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst37                                                                                                                                                ; LCCOMB_X66_Y4_N2       ; 32      ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst65~0                                                                                                                                              ; LCCOMB_X37_Y20_N28     ; 34      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst67                                                                                                                                                ; LCCOMB_X37_Y17_N12     ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst90                                                                                                                                                ; DDIOOECELL_X63_Y0_N12  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                                                                   ; DDIOOECELL_X67_Y11_N12 ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                                                                   ; DDIOOECELL_X52_Y0_N26  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                                                                   ; DDIOOECELL_X43_Y0_N19  ; 1       ; Output enable                         ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|inst95                                                                                                                                                ; FF_X39_Y18_N21         ; 128     ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|_~0                                                         ; LCCOMB_X36_Y20_N2      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0]                                                    ; FF_X57_Y17_N21         ; 72      ; Async. clear                          ; yes    ; Global Clock         ; GCLK9            ; --                        ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0                                                                    ; LCCOMB_X57_Y17_N14     ; 14      ; Clock enable, Write enable            ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                                      ; FF_X45_Y15_N1          ; 258     ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                                      ; FF_X18_Y13_N29         ; 64      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                      ; FF_X18_Y13_N3          ; 33      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]                                                                                                       ; PLL_3                  ; 52      ; Clock                                 ; yes    ; Global Clock         ; GCLK14           ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]                                                                                                     ; PLL_1                  ; 691     ; Clock                                 ; yes    ; Global Clock         ; GCLK3            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]                                                                                                     ; PLL_1                  ; 96      ; Clock                                 ; yes    ; Global Clock         ; GCLK1            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]                                                                                                     ; PLL_1                  ; 5       ; Clock                                 ; yes    ; Global Clock         ; GCLK0            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]                                                                                                     ; PLL_1                  ; 41      ; Clock                                 ; yes    ; Global Clock         ; GCLK2            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]                                                                                                     ; PLL_1                  ; 189     ; Clock, Latch enable                   ; yes    ; Global Clock         ; GCLK4            ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]                                                                                                     ; PLL_4                  ; 7       ; Clock                                 ; yes    ; Global Clock         ; GCLK16           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]                                                                                                     ; PLL_4                  ; 585     ; Clock                                 ; yes    ; Global Clock         ; GCLK17           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]                                                                                                     ; PLL_4                  ; 4       ; Clock                                 ; yes    ; Global Clock         ; GCLK18           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]                                                                                                     ; PLL_4                  ; 2       ; Clock                                 ; yes    ; Global Clock         ; GCLK19           ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~1                                                                               ; LCCOMB_X23_Y26_N8      ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|busy                                                                              ; LCCOMB_X22_Y25_N2      ; 15      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|input_latch_enable~0                                                              ; LCCOMB_X22_Y26_N10     ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7]~0                   ; LCCOMB_X14_Y25_N0      ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|_~0                                    ; LCCOMB_X19_Y28_N4      ; 14      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7]~0                   ; LCCOMB_X21_Y29_N18     ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|_~9                                     ; LCCOMB_X21_Y27_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]~0                    ; LCCOMB_X18_Y29_N18     ; 8       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|_~0                                     ; LCCOMB_X21_Y26_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~4                                                                        ; LCCOMB_X21_Y26_N10     ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~5                                                                        ; LCCOMB_X21_Y27_N12     ; 5       ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~0                                                          ; LCCOMB_X21_Y29_N6      ; 16      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~1                                                          ; LCCOMB_X18_Y29_N24     ; 13      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state                                                            ; FF_X22_Y29_N31         ; 13      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|scan_cache_write_enable~0                                                         ; LCCOMB_X20_Y26_N4      ; 3       ; Write enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~3                                                                   ; LCCOMB_X22_Y23_N2      ; 18      ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg_clear~0                                                                 ; LCCOMB_X22_Y27_N28     ; 35      ; Sync. clear, Sync. load               ; no     ; --                   ; --               ; --                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state                                                        ; FF_X21_Y25_N29         ; 10      ; Sync. load                            ; no     ; --                   ; --               ; --                        ;
-; inst25                                                                                                                                                                       ; LCCOMB_X15_Y23_N20     ; 1027    ; Async. clear, Async. load             ; yes    ; Global Clock         ; GCLK10           ; --                        ;
-; inst25                                                                                                                                                                       ; LCCOMB_X15_Y23_N20     ; 119     ; Clock enable, Sync. clear, Sync. load ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|ACHTELSEKUNDEN[2]~0                                                                                                                                 ; LCCOMB_X1_Y13_N6       ; 4       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|ACP_CONF[15]~3                                                                                                                                      ; LCCOMB_X16_Y11_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|ACP_CONF[23]~1                                                                                                                                      ; LCCOMB_X11_Y13_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|ACP_CONF[31]~0                                                                                                                                      ; LCCOMB_X16_Y11_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|ACP_CONF[7]~4                                                                                                                                       ; LCCOMB_X15_Y11_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[0]                                                                                                                                        ; FF_X17_Y10_N9          ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[1]                                                                                                                                        ; FF_X17_Y10_N31         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[2]                                                                                                                                        ; FF_X17_Y10_N1          ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[3]                                                                                                                                        ; FF_X17_Y10_N23         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[4]                                                                                                                                        ; FF_X17_Y10_N21         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[5]                                                                                                                                        ; FF_X17_Y10_N11         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[6]                                                                                                                                        ; FF_X17_Y10_N25         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[8]                                                                                                                                        ; FF_X17_Y10_N15         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CLEAR[9]                                                                                                                                        ; FF_X17_Y10_N29         ; 1       ; Async. clear                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CTR[15]~2                                                                                                                                       ; LCCOMB_X15_Y15_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CTR[23]~1                                                                                                                                       ; LCCOMB_X12_Y11_N10     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CTR[31]~3                                                                                                                                       ; LCCOMB_X18_Y12_N8      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_CTR[7]~0                                                                                                                                        ; LCCOMB_X15_Y13_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_ENA[15]~2                                                                                                                                       ; LCCOMB_X15_Y15_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_ENA[23]~1                                                                                                                                       ; LCCOMB_X12_Y13_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_ENA[31]~0                                                                                                                                       ; LCCOMB_X16_Y13_N24     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_ENA[7]~3                                                                                                                                        ; LCCOMB_X15_Y13_N6      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[0]~26                                                                                                                                     ; LCCOMB_X14_Y13_N30     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[1]~25                                                                                                                                     ; LCCOMB_X15_Y11_N22     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[2]~24                                                                                                                                     ; LCCOMB_X15_Y11_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[3]~23                                                                                                                                     ; LCCOMB_X15_Y10_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[4]~22                                                                                                                                     ; LCCOMB_X14_Y13_N20     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[5]~21                                                                                                                                     ; LCCOMB_X15_Y11_N0      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[6]~20                                                                                                                                     ; LCCOMB_X15_Y12_N26     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[8]~19                                                                                                                                     ; LCCOMB_X15_Y15_N6      ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|INT_LATCH[9]~18                                                                                                                                     ; LCCOMB_X15_Y15_N16     ; 1       ; Clock                                 ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|RTC_ADR[5]~0                                                                                                                                        ; LCCOMB_X8_Y12_N24      ; 6       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[0][0]~1                                                                                                                                       ; LCCOMB_X6_Y15_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[0][13]~14                                                                                                                                     ; LCCOMB_X4_Y14_N22      ; 1       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[0][2]~4                                                                                                                                       ; LCCOMB_X7_Y15_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][10]~10                                                                                                                                     ; LCCOMB_X7_Y14_N4       ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][11]~77                                                                                                                                     ; LCCOMB_X1_Y13_N26      ; 5       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][12]~11                                                                                                                                     ; LCCOMB_X8_Y13_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][13]~13                                                                                                                                     ; LCCOMB_X6_Y14_N18      ; 7       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][14]~15                                                                                                                                     ; LCCOMB_X7_Y14_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][15]~16                                                                                                                                     ; LCCOMB_X11_Y13_N30     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][16]~17                                                                                                                                     ; LCCOMB_X4_Y13_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][17]~18                                                                                                                                     ; LCCOMB_X3_Y11_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][18]~19                                                                                                                                     ; LCCOMB_X2_Y14_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][19]~20                                                                                                                                     ; LCCOMB_X2_Y13_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][1]~2                                                                                                                                       ; LCCOMB_X7_Y13_N28      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][20]~21                                                                                                                                     ; LCCOMB_X2_Y13_N16      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][21]~22                                                                                                                                     ; LCCOMB_X3_Y14_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][22]~23                                                                                                                                     ; LCCOMB_X2_Y14_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][23]~24                                                                                                                                     ; LCCOMB_X3_Y10_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][24]~25                                                                                                                                     ; LCCOMB_X3_Y10_N14      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][25]~26                                                                                                                                     ; LCCOMB_X2_Y12_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][26]~27                                                                                                                                     ; LCCOMB_X2_Y12_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][27]~28                                                                                                                                     ; LCCOMB_X4_Y9_N24       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][28]~29                                                                                                                                     ; LCCOMB_X4_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][29]~30                                                                                                                                     ; LCCOMB_X3_Y11_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][30]~31                                                                                                                                     ; LCCOMB_X3_Y12_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][31]~32                                                                                                                                     ; LCCOMB_X5_Y12_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][32]~33                                                                                                                                     ; LCCOMB_X4_Y10_N6       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][33]~34                                                                                                                                     ; LCCOMB_X8_Y10_N20      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][34]~35                                                                                                                                     ; LCCOMB_X8_Y10_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][35]~36                                                                                                                                     ; LCCOMB_X4_Y10_N0       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][36]~37                                                                                                                                     ; LCCOMB_X2_Y10_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][37]~38                                                                                                                                     ; LCCOMB_X2_Y10_N24      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][38]~39                                                                                                                                     ; LCCOMB_X7_Y10_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][39]~40                                                                                                                                     ; LCCOMB_X4_Y10_N2       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][3]~5                                                                                                                                       ; LCCOMB_X6_Y13_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][40]~41                                                                                                                                     ; LCCOMB_X6_Y9_N24       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][41]~42                                                                                                                                     ; LCCOMB_X5_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][42]~43                                                                                                                                     ; LCCOMB_X6_Y9_N6        ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][43]~44                                                                                                                                     ; LCCOMB_X9_Y11_N30      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][44]~45                                                                                                                                     ; LCCOMB_X10_Y11_N22     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][45]~46                                                                                                                                     ; LCCOMB_X10_Y10_N28     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][46]~47                                                                                                                                     ; LCCOMB_X10_Y10_N26     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][47]~48                                                                                                                                     ; LCCOMB_X9_Y13_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][48]~49                                                                                                                                     ; LCCOMB_X9_Y13_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][49]~50                                                                                                                                     ; LCCOMB_X9_Y10_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][50]~51                                                                                                                                     ; LCCOMB_X9_Y10_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][51]~52                                                                                                                                     ; LCCOMB_X8_Y9_N10       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][52]~53                                                                                                                                     ; LCCOMB_X7_Y9_N26       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][53]~54                                                                                                                                     ; LCCOMB_X11_Y9_N14      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][54]~55                                                                                                                                     ; LCCOMB_X10_Y9_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][55]~56                                                                                                                                     ; LCCOMB_X10_Y11_N20     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][56]~57                                                                                                                                     ; LCCOMB_X10_Y9_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][57]~58                                                                                                                                     ; LCCOMB_X8_Y12_N8       ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][58]~59                                                                                                                                     ; LCCOMB_X8_Y12_N10      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][59]~60                                                                                                                                     ; LCCOMB_X9_Y12_N24      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][5]~9                                                                                                                                       ; LCCOMB_X6_Y14_N12      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][60]~61                                                                                                                                     ; LCCOMB_X5_Y12_N26      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][61]~62                                                                                                                                     ; LCCOMB_X5_Y12_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][62]~63                                                                                                                                     ; LCCOMB_X12_Y12_N16     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|WERTE[7][63]~64                                                                                                                                     ; LCCOMB_X11_Y12_N12     ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|_~503                                                                                                                                               ; LCCOMB_X6_Y11_N18      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|_~504                                                                                                                                               ; LCCOMB_X5_Y11_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|_~505                                                                                                                                               ; LCCOMB_X4_Y14_N28      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-; interrupt_handler:nobody|_~506                                                                                                                                               ; LCCOMB_X7_Y13_N22      ; 8       ; Clock enable                          ; no     ; --                   ; --               ; --                        ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals                                                                                                                                                                                                                                           ;
-+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; Name                                                                                                                      ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-; CLK33M                                                                                                                    ; PIN_AB12           ; 12      ; 0                                    ; Global Clock         ; GCLK15           ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO                                                    ; LCCOMB_X26_Y22_N16 ; 250     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2                                                 ; LCCOMB_X26_Y22_N14 ; 32      ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                               ; FF_X29_Y21_N3      ; 34      ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK                                              ; LCCOMB_X26_Y18_N4  ; 850     ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21     ; 72      ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]                                                    ; PLL_3              ; 52      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]                                                    ; PLL_3              ; 1       ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]                                                    ; PLL_3              ; 1       ; 0                                    ; Global Clock         ; GCLK13           ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]                                                  ; PLL_1              ; 691     ; 0                                    ; Global Clock         ; GCLK3            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]                                                  ; PLL_1              ; 96      ; 0                                    ; Global Clock         ; GCLK1            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]                                                  ; PLL_1              ; 5       ; 0                                    ; Global Clock         ; GCLK0            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]                                                  ; PLL_1              ; 41      ; 0                                    ; Global Clock         ; GCLK2            ; --                        ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]                                                  ; PLL_1              ; 189     ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]                                                  ; PLL_4              ; 7       ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]                                                  ; PLL_4              ; 585     ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]                                                  ; PLL_4              ; 4       ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]                                                  ; PLL_4              ; 2       ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
-; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]                                                  ; PLL_2              ; 1       ; 0                                    ; Global Clock         ; GCLK8            ; --                        ;
-; inst25                                                                                                                    ; LCCOMB_X15_Y23_N20 ; 1027    ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
-+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals                                                                                                             ;
-+-----------------------------------------------------------------------------------------------------------------------------------+---------+
-; Name                                                                                                                              ; Fan-Out ;
-+-----------------------------------------------------------------------------------------------------------------------------------+---------+
-; MAIN_CLK~input                                                                                                                    ; 2272    ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; 385     ;
-; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                           ; 258     ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; 257     ;
-; nFB_WR~input                                                                                                                      ; 235     ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; 225     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                    ; 208     ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; 161     ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; 158     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                   ; 156     ;
-; FB_AD[17]~input                                                                                                                   ; 145     ;
-; FB_AD[18]~input                                                                                                                   ; 145     ;
-; FB_AD[20]~input                                                                                                                   ; 144     ;
-; FB_AD[16]~input                                                                                                                   ; 143     ;
-; FB_AD[19]~input                                                                                                                   ; 143     ;
-; FB_AD[21]~input                                                                                                                   ; 143     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                       ; 141     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                      ; 141     ;
-; FB_AD[22]~input                                                                                                                   ; 140     ;
-; FB_AD[23]~input                                                                                                                   ; 137     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                ; 132     ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                ; 132     ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; 129     ;
-; Video:Fredi_Aschwanden|inst95                                                                                                     ; 128     ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; 120     ;
-; inst25                                                                                                                            ; 118     ;
-; nFB_OE~input                                                                                                                      ; 101     ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; 97      ;
-; nFB_CS2~input                                                                                                                     ; 95      ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47     ; 88      ;
-; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; 83      ;
-; interrupt_handler:nobody|RTC_ADR[4]                                                                                               ; 80      ;
-; interrupt_handler:nobody|RTC_ADR[5]                                                                                               ; 79      ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ROLL_OVER ; 78      ;
-; interrupt_handler:nobody|UHR_DS~5                                                                                                 ; 71      ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1                                                   ; 68      ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                     ; 66      ;
-; interrupt_handler:nobody|UHR_DS~6                                                                                                 ; 66      ;
-; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                        ; 65      ;
-; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                           ; 64      ;
-; FB_AD[24]~input                                                                                                                   ; 63      ;
-; interrupt_handler:nobody|RTC_ADR[3]                                                                                               ; 62      ;
-; interrupt_handler:nobody|RTC_ADR[2]                                                                                               ; 62      ;
-; interrupt_handler:nobody|RTC_ADR[1]                                                                                               ; 62      ;
-; interrupt_handler:nobody|RTC_ADR[0]                                                                                               ; 62      ;
-; ~GND                                                                                                                              ; 61      ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; 60      ;
-; nFB_CS1~input                                                                                                                     ; 59      ;
-; FB_AD[25]~input                                                                                                                   ; 59      ;
-; FB_AD[26]~input                                                                                                                   ; 57      ;
-+-----------------------------------------------------------------------------------------------------------------------------------+---------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
-; Name                                                                                                                                                                                       ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                       ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 1024         ; 8            ; 256          ; 32           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 1024                        ; 8                           ; 256                         ; 32                          ; 8192                ; 1    ; None ; M9K_X24_Y11_N0                                                                                                                 ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 256          ; 32           ; 1024         ; 8            ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 256                         ; 32                          ; 1024                        ; 8                           ; 8192                ; 1    ; None ; M9K_X24_Y21_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y15_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                   ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y15_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                     ; AUTO ; True Dual Port   ; Dual Clocks  ; 16           ; 3            ; 16           ; 3            ; yes                    ; yes                     ; yes                    ; yes                     ; 48    ; 16                          ; 3                           ; 16                          ; 3                           ; 48                  ; 1    ; None ; M9K_X24_Y13_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y20_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                               ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y19_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                 ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 6            ; 256          ; 6            ; yes                    ; yes                     ; yes                    ; yes                     ; 1536  ; 256                         ; 6                           ; 256                         ; 6                           ; 1536                ; 1    ; None ; M9K_X24_Y17_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y14_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y16_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; Dual Clocks  ; 256          ; 8            ; 256          ; 8            ; yes                    ; yes                     ; yes                    ; yes                     ; 2048  ; 256                         ; 8                           ; 256                         ; 8                           ; 2048                ; 1    ; None ; M9K_X24_Y18_N0                                                                                                                 ;
-; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM                                        ; AUTO ; Simple Dual Port ; Dual Clocks  ; 128          ; 128          ; 128          ; 128          ; yes                    ; no                      ; yes                    ; no                      ; 16384 ; 128                         ; 128                         ; 128                         ; 128                         ; 16384               ; 4    ; None ; M9K_X40_Y19_N0, M9K_X40_Y20_N0, M9K_X40_Y21_N0, M9K_X40_Y22_N0                                                                 ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM                                                            ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 128          ; 512          ; 128          ; yes                    ; no                      ; yes                    ; yes                     ; 65536 ; 512                         ; 128                         ; 512                         ; 128                         ; 65536               ; 8    ; None ; M9K_X40_Y16_N0, M9K_X40_Y15_N0, M9K_X58_Y16_N0, M9K_X58_Y17_N0, M9K_X40_Y17_N0, M9K_X40_Y14_N0, M9K_X40_Y13_N0, M9K_X40_Y18_N0 ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM                                 ; AUTO ; Single Port      ; Single Clock ; 144          ; 1            ; --           ; --           ; yes                    ; no                      ; --                     ; --                      ; 144   ; 144                         ; 1                           ; --                          ; --                          ; 144                 ; 1    ; None ; M9K_X24_Y25_N0                                                                                                                 ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+
-Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-
-
-+-----------------------------------------------------------------------------------------------+
-; Fitter DSP Block Usage Summary                                                                ;
-+---------------------------------------+-------------+---------------------+-------------------+
-; Statistic                             ; Number Used ; Available per Block ; Maximum Available ;
-+---------------------------------------+-------------+---------------------+-------------------+
-; Simple Multipliers (9-bit)            ; 0           ; 2                   ; 252               ;
-; Simple Multipliers (18-bit)           ; 3           ; 1                   ; 126               ;
-; Embedded Multiplier Blocks            ; 3           ; --                  ; 126               ;
-; Embedded Multiplier 9-bit elements    ; 6           ; 2                   ; 252               ;
-; Signed Embedded Multipliers           ; 0           ; --                  ; --                ;
-; Unsigned Embedded Multipliers         ; 3           ; --                  ; --                ;
-; Mixed Sign Embedded Multipliers       ; 0           ; --                  ; --                ;
-; Variable Sign Embedded Multipliers    ; 0           ; --                  ; --                ;
-; Dedicated Input Shift Register Chains ; 0           ; --                  ; --                ;
-+---------------------------------------+-------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; DSP Block Details                                                                                                                                                                                                                                                                                                     ;
-+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
-; Name                                                                                                                   ; Mode                       ; Location           ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ;
-+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2     ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y14_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
-;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1 ;                            ; DSPMULT_X31_Y14_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2      ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y10_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
-;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_mult1  ;                            ; DSPMULT_X31_Y10_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2     ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y12_N2  ;                     ; No                             ;                       ;                       ;                   ; no              ;
-;    Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_mult1 ;                            ; DSPMULT_X31_Y12_N0 ; Unsigned            ;                                ; no                    ; no                    ; no                ;                 ;
-+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+
-
-
-+--------------------------------------------------------+
-; Interconnect Usage Summary                             ;
-+----------------------------+---------------------------+
-; Interconnect Resource Type ; Usage                     ;
-+----------------------------+---------------------------+
-; Block interconnects        ; 16,358 / 116,715 ( 14 % ) ;
-; C16 interconnects          ; 749 / 3,886 ( 19 % )      ;
-; C4 interconnects           ; 10,626 / 73,752 ( 14 % )  ;
-; Direct links               ; 2,046 / 116,715 ( 2 % )   ;
-; Global clocks              ; 20 / 20 ( 100 % )         ;
-; Local interconnects        ; 4,734 / 39,600 ( 12 % )   ;
-; R24 interconnects          ; 882 / 3,777 ( 23 % )      ;
-; R4 interconnects           ; 11,442 / 99,858 ( 11 % )  ;
-+----------------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; LAB Logic Elements                                                          ;
-+---------------------------------------------+-------------------------------+
-; Number of Logic Elements  (Average = 12.60) ; Number of LABs  (Total = 756) ;
-+---------------------------------------------+-------------------------------+
-; 1                                           ; 41                            ;
-; 2                                           ; 20                            ;
-; 3                                           ; 22                            ;
-; 4                                           ; 11                            ;
-; 5                                           ; 13                            ;
-; 6                                           ; 12                            ;
-; 7                                           ; 15                            ;
-; 8                                           ; 13                            ;
-; 9                                           ; 13                            ;
-; 10                                          ; 30                            ;
-; 11                                          ; 23                            ;
-; 12                                          ; 32                            ;
-; 13                                          ; 29                            ;
-; 14                                          ; 47                            ;
-; 15                                          ; 59                            ;
-; 16                                          ; 376                           ;
-+---------------------------------------------+-------------------------------+
-
-
-+--------------------------------------------------------------------+
-; LAB-wide Signals                                                   ;
-+------------------------------------+-------------------------------+
-; LAB-wide Signals  (Average = 1.78) ; Number of LABs  (Total = 756) ;
-+------------------------------------+-------------------------------+
-; 1 Async. clear                     ; 239                           ;
-; 1 Clock                            ; 631                           ;
-; 1 Clock enable                     ; 289                           ;
-; 1 Sync. clear                      ; 20                            ;
-; 1 Sync. load                       ; 26                            ;
-; 2 Async. clears                    ; 12                            ;
-; 2 Clock enables                    ; 84                            ;
-; 2 Clocks                           ; 41                            ;
-+------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Signals Sourced                                                          ;
-+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced  (Average = 18.19) ; Number of LABs  (Total = 756) ;
-+----------------------------------------------+-------------------------------+
-; 0                                            ; 0                             ;
-; 1                                            ; 19                            ;
-; 2                                            ; 26                            ;
-; 3                                            ; 12                            ;
-; 4                                            ; 16                            ;
-; 5                                            ; 8                             ;
-; 6                                            ; 14                            ;
-; 7                                            ; 5                             ;
-; 8                                            ; 11                            ;
-; 9                                            ; 8                             ;
-; 10                                           ; 14                            ;
-; 11                                           ; 9                             ;
-; 12                                           ; 20                            ;
-; 13                                           ; 17                            ;
-; 14                                           ; 15                            ;
-; 15                                           ; 30                            ;
-; 16                                           ; 49                            ;
-; 17                                           ; 41                            ;
-; 18                                           ; 43                            ;
-; 19                                           ; 30                            ;
-; 20                                           ; 42                            ;
-; 21                                           ; 35                            ;
-; 22                                           ; 49                            ;
-; 23                                           ; 45                            ;
-; 24                                           ; 31                            ;
-; 25                                           ; 31                            ;
-; 26                                           ; 27                            ;
-; 27                                           ; 28                            ;
-; 28                                           ; 20                            ;
-; 29                                           ; 17                            ;
-; 30                                           ; 18                            ;
-; 31                                           ; 10                            ;
-; 32                                           ; 16                            ;
-+----------------------------------------------+-------------------------------+
-
-
-+---------------------------------------------------------------------------------+
-; LAB Signals Sourced Out                                                         ;
-+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out  (Average = 8.27) ; Number of LABs  (Total = 756) ;
-+-------------------------------------------------+-------------------------------+
-; 0                                               ; 1                             ;
-; 1                                               ; 61                            ;
-; 2                                               ; 48                            ;
-; 3                                               ; 47                            ;
-; 4                                               ; 43                            ;
-; 5                                               ; 40                            ;
-; 6                                               ; 51                            ;
-; 7                                               ; 50                            ;
-; 8                                               ; 53                            ;
-; 9                                               ; 71                            ;
-; 10                                              ; 46                            ;
-; 11                                              ; 45                            ;
-; 12                                              ; 51                            ;
-; 13                                              ; 46                            ;
-; 14                                              ; 26                            ;
-; 15                                              ; 25                            ;
-; 16                                              ; 19                            ;
-; 17                                              ; 5                             ;
-; 18                                              ; 9                             ;
-; 19                                              ; 6                             ;
-; 20                                              ; 4                             ;
-; 21                                              ; 1                             ;
-; 22                                              ; 2                             ;
-; 23                                              ; 0                             ;
-; 24                                              ; 3                             ;
-; 25                                              ; 2                             ;
-; 26                                              ; 0                             ;
-; 27                                              ; 1                             ;
-+-------------------------------------------------+-------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; LAB Distinct Inputs                                                          ;
-+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs  (Average = 18.51) ; Number of LABs  (Total = 756) ;
-+----------------------------------------------+-------------------------------+
-; 0                                            ; 0                             ;
-; 1                                            ; 1                             ;
-; 2                                            ; 22                            ;
-; 3                                            ; 24                            ;
-; 4                                            ; 30                            ;
-; 5                                            ; 15                            ;
-; 6                                            ; 15                            ;
-; 7                                            ; 23                            ;
-; 8                                            ; 16                            ;
-; 9                                            ; 20                            ;
-; 10                                           ; 17                            ;
-; 11                                           ; 19                            ;
-; 12                                           ; 16                            ;
-; 13                                           ; 20                            ;
-; 14                                           ; 18                            ;
-; 15                                           ; 17                            ;
-; 16                                           ; 19                            ;
-; 17                                           ; 34                            ;
-; 18                                           ; 26                            ;
-; 19                                           ; 19                            ;
-; 20                                           ; 27                            ;
-; 21                                           ; 33                            ;
-; 22                                           ; 35                            ;
-; 23                                           ; 33                            ;
-; 24                                           ; 33                            ;
-; 25                                           ; 30                            ;
-; 26                                           ; 30                            ;
-; 27                                           ; 21                            ;
-; 28                                           ; 15                            ;
-; 29                                           ; 16                            ;
-; 30                                           ; 26                            ;
-; 31                                           ; 28                            ;
-; 32                                           ; 29                            ;
-; 33                                           ; 25                            ;
-; 34                                           ; 4                             ;
-+----------------------------------------------+-------------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary                        ;
-+----------------------------------+-------+
-; I/O Rules Statistic              ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules                  ; 30    ;
-; Number of I/O Rules Passed       ; 17    ;
-; Number of I/O Rules Failed       ; 0     ;
-; Number of I/O Rules Unchecked    ; 0     ;
-; Number of I/O Rules Inapplicable ; 13    ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
-; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
-; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Pass         ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
-; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
-; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
-; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Pin/Rules          ; IO_000001 ; IO_000002    ; IO_000003 ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007 ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-; Total Pass         ; 295       ; 121          ; 295       ; 0            ; 0            ; 295       ; 295       ; 0            ; 295       ; 295       ; 168          ; 3            ; 0            ; 0            ; 183          ; 168          ; 3            ; 183          ; 0            ; 0            ; 11           ; 3            ; 171          ; 0            ; 0            ; 0            ; 0            ; 295       ; 0            ; 0            ;
-; Total Unchecked    ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; Total Inapplicable ; 0         ; 174          ; 0         ; 295          ; 295          ; 0         ; 0         ; 295          ; 0         ; 0         ; 127          ; 292          ; 295          ; 295          ; 112          ; 127          ; 292          ; 112          ; 295          ; 295          ; 284          ; 292          ; 124          ; 295          ; 295          ; 295          ; 295          ; 0         ; 295          ; 295          ;
-; Total Fail         ; 0         ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
-; CLK24M576          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_STR             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_BURST          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nACSI_DRQ          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nACSI_INT          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_DRQ          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_MSG          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nDCHG              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_DATA0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_DATA1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_DATA2           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_CARD_DEDECT     ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_WP              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nDACK0             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; WP_CF_CARD         ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_C_D          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_I_O          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_CS3            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; CLK25M             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nACSI_ACK          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nACSI_RESET        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nACSI_CS           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_DIR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_A1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_ACK          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_ATN          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_DIR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; MIDI_OLR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; MIDI_TLR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; TxD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; RTS                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; DTR                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; AMKB_TX            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IDE_RES            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIDE_CS0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIDE_CS1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIDE_WR            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIDE_RD            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nCF_CS0            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nCF_CS1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nROM3              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nROM4              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nRP_UDS            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nRP_LDS            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSDSEL             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nWR_GATE           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nWR                ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; YM_QA              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; YM_QB              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; YM_QC              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_CLK             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; DSA_D              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nVWE               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nVCAS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nVRAS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nVCS               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nPD_VGA            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; TIN0               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSRCS              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSRBLE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSRBHE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSRWE              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nDREQ1             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LED_FPGA_OK        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSROE              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VCKE               ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_TA             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nDDR_CLK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; DDR_CLK            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VSYNC_PAD          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; HSYNC_PAD          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nBLANK_PAD         ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; PIXEL_CLK_PAD      ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSYNC              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nMOT_ON            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSTEP_DIR          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSTEP              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; CLKUSB             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LPDIR              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; BA[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; BA[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[7]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[6]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[5]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[4]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[3]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nIRQ[2]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[12]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[11]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[10]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VA[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VB[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDM[3]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDM[2]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDM[1]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDM[0]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VG[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VR[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; TOUT0              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nMASTER            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[31]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[30]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[29]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[28]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[27]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[26]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[25]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[24]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[23]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[22]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[21]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[20]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[19]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[18]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[17]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[16]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[15]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[14]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[13]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[12]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[11]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[10]          ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[9]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[8]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[7]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[6]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[5]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[4]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[3]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[2]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[1]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_AD[0]           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[31]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[30]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[29]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[28]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[27]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[26]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[25]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[24]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[23]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[22]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[21]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[20]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[19]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[18]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[17]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[16]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[15]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[14]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[13]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[12]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[11]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[10]             ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[9]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[8]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[7]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[6]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[5]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[4]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[3]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[2]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[1]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VD[0]              ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDQS[3]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDQS[2]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDQS[1]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; VDQS[0]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[17]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[16]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[15]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[14]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[13]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[12]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[11]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[10]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[9]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[8]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[7]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[6]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[5]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[4]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[3]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[2]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[1]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IO[0]              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[15]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[14]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[13]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[12]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[11]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[10]            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[9]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[8]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[7]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[6]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[5]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[4]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[3]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[2]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[1]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SRD[0]             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_PAR           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_SEL          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_BUSY         ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nSCSI_RST          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_CD_DATA3        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SD_CMD_D1          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; ACSI_D[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[7]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[6]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[5]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[4]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[3]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[2]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[1]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_D[0]            ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[7]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[6]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[5]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[4]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[3]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[2]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[1]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; SCSI_D[0]          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nRSTO_MCF          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_WR             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_CS1            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_SIZE1           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_SIZE0           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; FB_ALE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_CS2            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; MAIN_CLK           ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nDACK1             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nFB_OE             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IDE_RDY            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; CLK33M             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; HD_DD              ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nINDEX             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; RxD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nWP                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; LP_BUSY            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; DCD                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; CTS                ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; TRACK00            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; IDE_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; RI                 ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nPCI_INTD          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nPCI_INTC          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nPCI_INTB          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nPCI_INTA          ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; DVI_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; E0_INT             ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; PIC_INT            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; PIC_AMKB_RX        ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; MIDI_IN            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; nRD_DATA           ; Pass      ; Pass         ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-; AMKB_RX            ; Pass      ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
-+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
-
-
-+-------------------------------------------------------------------------+
-; Fitter Device Options                                                   ;
-+----------------------------------------------+--------------------------+
-; Option                                       ; Setting                  ;
-+----------------------------------------------+--------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
-; Enable device-wide reset (DEV_CLRn)          ; On                       ;
-; Enable device-wide output enable (DEV_OE)    ; On                       ;
-; Enable INIT_DONE output                      ; Off                      ;
-; Configuration scheme                         ; Passive Serial           ;
-; Error detection CRC                          ; Off                      ;
-; Enable Open Drain on CRC Error pin           ; Off                      ;
-; Configuration Voltage Level                  ; Auto                     ;
-; Force Configuration Voltage Level            ; On                       ;
-; nCEO                                         ; As output driving ground ;
-; Data[0]                                      ; As input tri-stated      ;
-; Data[1]/ASDO                                 ; As input tri-stated      ;
-; Data[7..2]                                   ; Unreserved               ;
-; FLASH_nCE/nCSO                               ; As input tri-stated      ;
-; Other Active Parallel pins                   ; Unreserved               ;
-; DCLK                                         ; As input tri-stated      ;
-; Base pin-out file on sameframe device        ; Off                      ;
-+----------------------------------------------+--------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions  ;
-+---------------------------+--------+
-; Setting                   ; Value  ;
-+---------------------------+--------+
-; Nominal Core Voltage      ; 1.20 V ;
-; Low Junction Temperature  ; 0 °C   ;
-; High Junction Temperature ; 85 °C  ;
-+---------------------------+--------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing                                                                                                                                                                                                                                                                                                                     ;
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
-; Source Clock(s)                                                                                                                                                   ; Destination Clock(s)                                                                                                                                              ; Delay Added in ns ;
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
-; I/O                                                                                                                                                               ; MAIN_CLK                                                                                                                                                          ; 245.886           ;
-; MAIN_CLK                                                                                                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 444.109           ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 1092.93           ;
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Info: *******************************************************************
-Info: Running Quartus II Fitter
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Wed Dec 15 02:21:57 2010
-Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-Info: Selected device EP3C40F484C6 for design "firebee1"
-Info: Core supply voltage is 1.2V
-Info: Low junction temperature is 0 degrees C
-Info: High junction temperature is 85 degrees C
-Info: Implemented PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" as Cyclone III PLL type
-    Info: Implementing clock multiplication of 1, clock division of 66, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] port
-    Info: Implementing clock multiplication of 67, clock division of 900, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] port
-    Info: Implementing clock multiplication of 67, clock division of 90, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] port
-Info: None of the inputs fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input
-    Info: Input "nRD_DATA" that is fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input
-Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings
-    Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109
-    Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75
-    Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port
-    Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port
-    Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port
-    Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port
-Info: None of the inputs fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input
-    Info: Input "MAIN_CLK" that is fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input
-Info: Implemented PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" as Cyclone III PLL type
-    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 240 degrees (5051 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] port
-    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] port
-    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 180 degrees (3788 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] port
-    Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 105 degrees (2210 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] port
-    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 270 degrees (11364 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] port
-Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type
-    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port
-Critical Warning: The input clock frequency specification of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is different from the output clock frequency specification of the source PLLs that are driving it
-    Critical Warning: Input port inclk[0] of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" and its source clk[3] (the output port of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1") have different specified frequencies, 48.0 MHz and 48.0 MHz respectively
-Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
-Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
-    Info: Device EP3C16F484C6 is compatible
-    Info: Device EP3C55F484C6 is compatible
-    Info: Device EP3C80F484C6 is compatible
-Info: Fitter converted 7 user pins into dedicated programming pins
-    Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
-    Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
-    Info: Pin ~ALTERA_DCLK~ is reserved at location K2
-    Info: Pin ~ALTERA_DATA0~ is reserved at location K1
-    Info: Pin ~ALTERA_DEV_OE~ is reserved at location N22
-    Info: Pin ~ALTERA_DEV_CLRn~ is reserved at location N21
-    Info: Pin ~ALTERA_nCEO~ is reserved at location K22
-Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Warning: The parameters of the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 and the PLL altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged
-    Info: The values of the parameter "M" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "M" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 67
-        Info: The value of the parameter "M" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 109
-    Info: The values of the parameter "N" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "N" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 6
-        Info: The value of the parameter "N" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 3
-    Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 12000
-        Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 10000
-    Info: The values of the parameter "VCO POST SCALE" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 2
-        Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1
-    Info: The values of the parameter "Min VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Min VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538
-        Info: The value of the parameter "Min VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769
-    Info: The values of the parameter "Max VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Max VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 3333
-        Info: The value of the parameter "Max VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1666
-    Info: The values of the parameter "Center VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Center VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538
-        Info: The value of the parameter "Center VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769
-    Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Min Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 17174
-        Info: The value of the parameter "Min Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 27940
-    Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Max Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 30864
-        Info: The value of the parameter "Max Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 59523
-    Info: The values of the parameter "Compensate Clock" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1
-        Info: The value of the parameter "Compensate Clock" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is clock0
-        Info: The value of the parameter "Compensate Clock" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is clock1
-Warning: The input ports of the PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 and the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 are mismatched, preventing the PLLs to be merged
-    Warning: Input clock frequency of PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 differs from input clock frequency of PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1
-Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings
-    Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109
-    Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75
-    Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port
-    Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port
-    Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port
-    Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port
-Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type
-    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port
-Critical Warning: Input pin "CLK33M" feeds inclk port of PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" by global clock - I/O timing will be affected
-Info: Timing-driven compilation is using the Classic Timing Analyzer
-Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
-Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] (placed in counter C1 of PLL_3)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14
-Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] (placed in counter C2 of PLL_3)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12
-Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] (placed in counter C3 of PLL_3)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G13
-Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] (placed in counter C0 of PLL_1)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
-Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] (placed in counter C3 of PLL_1)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
-Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] (placed in counter C2 of PLL_1)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0
-Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] (placed in counter C4 of PLL_1)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
-Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] (placed in counter C1 of PLL_1)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4
-Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] (placed in counter C1 of PLL_4)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16
-Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] (placed in counter C2 of PLL_4)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17
-Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] (placed in counter C3 of PLL_4)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18
-Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] (placed in counter C4 of PLL_4)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
-Info: Automatically promoted node altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
-Info: Automatically promoted node CLK33M~input (placed in PIN AB12 (CLK12, DIFFCLK_7n))
-    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15
-    Info: Following destination nodes may be non-global or may not use global or regional clocks
-        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0
-        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3
-        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M
-Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-    Info: Following destination nodes may be non-global or may not use global or regional clocks
-        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC
-        Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC
-Info: Automatically promoted node inst25 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-    Info: Following destination nodes may be non-global or may not use global or regional clocks
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_WR~reg0
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[10]
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[14]
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[15]
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[12]
-        Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[13]
-        Info: Non-global destination nodes limited to 10 nodes
-Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-    Info: Following destination nodes may be non-global or may not use global or regional clocks
-        Info: Destination node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
-Info: Automatically promoted node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-    Info: Following destination nodes may be non-global or may not use global or regional clocks
-        Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|_~0
-        Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0
-Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 
-    Info: Automatically promoted destinations to use location or clock signal Global Clock
-Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "VD[31]~input" is constrained to location IOIBUF_X43_Y0_N1 to improve DDIO timing
-    Info: Node "VD[31]" is constrained to location PIN U12 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing
-    Info: Node "VD[30]~input" is constrained to location IOIBUF_X41_Y0_N29 to improve DDIO timing
-    Info: Node "VD[30]" is constrained to location PIN V12 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "VD[29]~input" is constrained to location IOIBUF_X38_Y0_N22 to improve DDIO timing
-    Info: Node "VD[29]" is constrained to location PIN AB13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "VD[28]~input" is constrained to location IOIBUF_X43_Y0_N29 to improve DDIO timing
-    Info: Node "VD[28]" is constrained to location PIN W13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "VD[27]~input" is constrained to location IOIBUF_X48_Y0_N29 to improve DDIO timing
-    Info: Node "VD[27]" is constrained to location PIN V13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "VD[26]~input" is constrained to location IOIBUF_X38_Y0_N8 to improve DDIO timing
-    Info: Node "VD[26]" is constrained to location PIN AB14 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "VD[25]~input" is constrained to location IOIBUF_X38_Y0_N15 to improve DDIO timing
-    Info: Node "VD[25]" is constrained to location PIN AA14 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "VD[24]~input" is constrained to location IOIBUF_X43_Y0_N8 to improve DDIO timing
-    Info: Node "VD[24]" is constrained to location PIN AB15 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "VD[23]~input" is constrained to location IOIBUF_X45_Y0_N15 to improve DDIO timing
-    Info: Node "VD[23]" is constrained to location PIN AB16 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing
-    Info: Node "VD[22]~input" is constrained to location IOIBUF_X48_Y0_N22 to improve DDIO timing
-    Info: Node "VD[22]" is constrained to location PIN W14 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "VD[21]~input" is constrained to location IOIBUF_X50_Y0_N1 to improve DDIO timing
-    Info: Node "VD[21]" is constrained to location PIN V15 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "VD[20]~input" is constrained to location IOIBUF_X50_Y0_N29 to improve DDIO timing
-    Info: Node "VD[20]" is constrained to location PIN U13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing
-    Info: Node "VD[19]~input" is constrained to location IOIBUF_X50_Y0_N22 to improve DDIO timing
-    Info: Node "VD[19]" is constrained to location PIN V14 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing
-    Info: Node "VD[18]~input" is constrained to location IOIBUF_X38_Y0_N29 to improve DDIO timing
-    Info: Node "VD[18]" is constrained to location PIN AA13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing
-    Info: Node "VD[17]~input" is constrained to location IOIBUF_X43_Y0_N22 to improve DDIO timing
-    Info: Node "VD[17]" is constrained to location PIN Y13 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing
-    Info: Node "VD[16]~input" is constrained to location IOIBUF_X45_Y0_N8 to improve DDIO timing
-    Info: Node "VD[16]" is constrained to location PIN T12 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing
-    Info: Node "VD[15]~input" is constrained to location IOIBUF_X67_Y15_N8 to improve DDIO timing
-    Info: Node "VD[15]" is constrained to location PIN N20 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "VD[14]~input" is constrained to location IOIBUF_X67_Y13_N8 to improve DDIO timing
-    Info: Node "VD[14]" is constrained to location PIN R22 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "VD[13]~input" is constrained to location IOIBUF_X67_Y14_N22 to improve DDIO timing
-    Info: Node "VD[13]" is constrained to location PIN P20 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing
-    Info: Node "VD[12]~input" is constrained to location IOIBUF_X67_Y17_N22 to improve DDIO timing
-    Info: Node "VD[12]" is constrained to location PIN N17 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing
-    Info: Node "VD[11]~input" is constrained to location IOIBUF_X67_Y13_N1 to improve DDIO timing
-    Info: Node "VD[11]" is constrained to location PIN R21 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "VD[10]~input" is constrained to location IOIBUF_X67_Y10_N15 to improve DDIO timing
-    Info: Node "VD[10]" is constrained to location PIN P17 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "VD[9]~input" is constrained to location IOIBUF_X67_Y12_N22 to improve DDIO timing
-    Info: Node "VD[9]" is constrained to location PIN R18 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "VD[8]~input" is constrained to location IOIBUF_X67_Y10_N8 to improve DDIO timing
-    Info: Node "VD[8]" is constrained to location PIN V22 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "VD[7]~input" is constrained to location IOIBUF_X67_Y11_N1 to improve DDIO timing
-    Info: Node "VD[7]" is constrained to location PIN U21 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing
-    Info: Node "VD[6]~input" is constrained to location IOIBUF_X67_Y12_N15 to improve DDIO timing
-    Info: Node "VD[6]" is constrained to location PIN R19 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing
-    Info: Node "VD[5]~input" is constrained to location IOIBUF_X67_Y10_N22 to improve DDIO timing
-    Info: Node "VD[5]" is constrained to location PIN R17 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "VD[4]~input" is constrained to location IOIBUF_X67_Y14_N1 to improve DDIO timing
-    Info: Node "VD[4]" is constrained to location PIN P21 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing
-    Info: Node "VD[3]~input" is constrained to location IOIBUF_X67_Y11_N22 to improve DDIO timing
-    Info: Node "VD[3]" is constrained to location PIN R20 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing
-    Info: Node "VD[2]~input" is constrained to location IOIBUF_X67_Y14_N8 to improve DDIO timing
-    Info: Node "VD[2]" is constrained to location PIN P22 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "VD[1]~input" is constrained to location IOIBUF_X67_Y18_N1 to improve DDIO timing
-    Info: Node "VD[1]" is constrained to location PIN M21 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing
-    Info: Node "VD[0]~input" is constrained to location IOIBUF_X67_Y18_N8 to improve DDIO timing
-    Info: Node "VD[0]" is constrained to location PIN M22 to improve DDIO timing
-Info: Starting register packing
-Extra Info: Performing register packing on registers with non-logic cell location assignments
-Extra Info: Completed register packing on registers with non-logic cell location assignments
-Extra Info: Started Fast Input/Output/OE register processing
-Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] to I/O pin
-    Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] and I/O node MAIN_CLK -- I/O node is a dedicated I/O pin
-Extra Info: Finished Fast Input/Output/OE register processing
-Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
-Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
-Info: Finished register packing
-    Extra Info: Packed 33 registers into blocks of type I/O Input Buffer
-    Extra Info: Packed 25 registers into blocks of type I/O Output Buffer
-    Extra Info: Created 9 register duplicates
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
-    Info: Input port INCLK[0] of node "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" is driven by CLK33M~inputclkctrl which is OUTCLK output port of Clock control block type node CLK33M~inputclkctrl
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" output port clk[2] feeds output pin "CLK24M576~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[2] feeds output pin "CLK25M~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[3] feeds output pin "CLKUSB~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[3]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[2]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "nDDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "DDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
-Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
-    Info: Input port INCLK[0] of node "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is driven by altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl
-Info: Starting physical synthesis optimizations for speed
-Info: Starting physical synthesis algorithm combinational resynthesis using boolean division
-Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2208 ps
-Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:23
-Info: Fitter preparation operations ending: elapsed time is 00:00:47
-Info: Fitter placement preparation operations beginning
-Info: Fitter placement preparation operations ending: elapsed time is 00:00:18
-Info: Fitter placement operations beginning
-Info: Fitter placement was successful
-Info: Fitter placement operations ending: elapsed time is 00:01:10
-Info: Starting physical synthesis optimizations for speed
-Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:05
-Info: Estimated most critical path is register to pin delay of 5.130 ns
-    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12_N0; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[9]'
-    Info: 2: + IC(0.161 ns) + CELL(0.369 ns) = 0.530 ns; Loc. = LAB_X16_Y12_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15'
-    Info: 3: + IC(0.528 ns) + CELL(0.243 ns) = 1.301 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359'
-    Info: 4: + IC(0.172 ns) + CELL(0.130 ns) = 1.603 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~360'
-    Info: 5: + IC(1.521 ns) + CELL(2.006 ns) = 5.130 ns; Loc. = IOOBUF_X34_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[29]~output'
-    Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 5.130 ns; Loc. = PIN_W10; Fanout = 0; PIN Node = 'FB_AD[29]'
-    Info: Total cell delay = 2.748 ns ( 53.57 % )
-    Info: Total interconnect delay = 2.382 ns ( 46.43 % )
-Info: Fitter routing operations beginning
-Info: 2 (of 32134) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Fitter report for a summary of the relevant clock transfers. Also, check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks.
-Info: Average interconnect usage is 13% of the available device resources
-    Info: Peak interconnect usage is 51% of the available device resources in the region that extends from location X22_Y11 to location X33_Y21
-Info: Fitter routing operations ending: elapsed time is 00:01:18
-Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
-    Info: Optimizations that may affect the design's routability were skipped
-Info: Started post-fitting delay annotation
-Info: Delay annotation completed successfully
-Info: Auto delay chain can't change the delay chain setting on I/O pin nRD_DATA since it's a PLL compensated pin
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register
-Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Warning: Total number of single-ended output or bi-directional pins in bank 4 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
-    Info: There are 32 output pin(s) with I/O standard 2.5 V and current strength 12mA
-        Info: Location AA13 (pad PAD_208): Pin VD[18] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AB13 (pad PAD_209): Pin VD[29] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AA14 (pad PAD_210): Pin VD[25] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AB14 (pad PAD_211): Pin VD[26] of type bi-directional uses 2.5 V I/O standard
-        Info: Location V12 (pad PAD_213): Pin VD[30] of type bi-directional uses 2.5 V I/O standard
-        Info: Location W13 (pad PAD_218): Pin VD[28] of type bi-directional uses 2.5 V I/O standard
-        Info: Location Y13 (pad PAD_219): Pin VD[17] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AA15 (pad PAD_220): Pin VDQS[0] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AB15 (pad PAD_221): Pin VD[24] of type bi-directional uses 2.5 V I/O standard
-        Info: Location U12 (pad PAD_222): Pin VD[31] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AA16 (pad PAD_224): Pin VDM[0] of type output uses 2.5 V I/O standard
-        Info: Location AB16 (pad PAD_225): Pin VD[23] of type bi-directional uses 2.5 V I/O standard
-        Info: Location T12 (pad PAD_226): Pin VD[16] of type bi-directional uses 2.5 V I/O standard
-        Info: Location V13 (pad PAD_228): Pin VD[27] of type bi-directional uses 2.5 V I/O standard
-        Info: Location W14 (pad PAD_229): Pin VD[22] of type bi-directional uses 2.5 V I/O standard
-        Info: Location U13 (pad PAD_233): Pin VD[20] of type bi-directional uses 2.5 V I/O standard
-        Info: Location V14 (pad PAD_234): Pin VD[19] of type bi-directional uses 2.5 V I/O standard
-        Info: Location U15 (pad PAD_236): Pin VCKE of type output uses 2.5 V I/O standard
-        Info: Location V15 (pad PAD_237): Pin VD[21] of type bi-directional uses 2.5 V I/O standard
-        Info: Location W15 (pad PAD_239): Pin VDQS[1] of type bi-directional uses 2.5 V I/O standard
-        Info: Location AB18 (pad PAD_242): Pin nVCAS of type output uses 2.5 V I/O standard
-        Info: Location AA17 (pad PAD_243): Pin nDDR_CLK of type output uses 2.5 V I/O standard
-        Info: Location AB17 (pad PAD_244): Pin DDR_CLK of type output uses 2.5 V I/O standard
-        Info: Location AA18 (pad PAD_245): Pin VA[12] of type output uses 2.5 V I/O standard
-        Info: Location AA19 (pad PAD_252): Pin BA[1] of type output uses 2.5 V I/O standard
-        Info: Location AB19 (pad PAD_253): Pin VA[9] of type output uses 2.5 V I/O standard
-        Info: Location W17 (pad PAD_257): Pin nVRAS of type output uses 2.5 V I/O standard
-        Info: Location Y17 (pad PAD_258): Pin nVWE of type output uses 2.5 V I/O standard
-        Info: Location AA20 (pad PAD_259): Pin VA[7] of type output uses 2.5 V I/O standard
-        Info: Location AB20 (pad PAD_260): Pin VA[8] of type output uses 2.5 V I/O standard
-        Info: Location V16 (pad PAD_261): Pin VDM[1] of type output uses 2.5 V I/O standard
-        Info: Location T16 (pad PAD_266): Pin VDQS[3] of type bi-directional uses 2.5 V I/O standard
-Warning: Total number of single-ended output or bi-directional pins in bank 5 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition.
-    Info: There are 30 output pin(s) with I/O standard 2.5 V and current strength 12mA
-        Info: Location AA22 (pad PAD_273): Pin VA[4] of type output uses 2.5 V I/O standard
-        Info: Location AA21 (pad PAD_274): Pin VA[6] of type output uses 2.5 V I/O standard
-        Info: Location T17 (pad PAD_277): Pin VDM[3] of type output uses 2.5 V I/O standard
-        Info: Location T18 (pad PAD_278): Pin nVCS of type output uses 2.5 V I/O standard
-        Info: Location W20 (pad PAD_280): Pin VA[0] of type output uses 2.5 V I/O standard
-        Info: Location W19 (pad PAD_285): Pin BA[0] of type output uses 2.5 V I/O standard
-        Info: Location Y22 (pad PAD_288): Pin VA[3] of type output uses 2.5 V I/O standard
-        Info: Location Y21 (pad PAD_289): Pin VA[5] of type output uses 2.5 V I/O standard
-        Info: Location U20 (pad PAD_290): Pin VDM[2] of type output uses 2.5 V I/O standard
-        Info: Location U19 (pad PAD_291): Pin VA[11] of type output uses 2.5 V I/O standard
-        Info: Location W22 (pad PAD_292): Pin VA[1] of type output uses 2.5 V I/O standard
-        Info: Location W21 (pad PAD_293): Pin VA[2] of type output uses 2.5 V I/O standard
-        Info: Location R17 (pad PAD_301): Pin VD[5] of type bi-directional uses 2.5 V I/O standard
-        Info: Location P17 (pad PAD_302): Pin VD[10] of type bi-directional uses 2.5 V I/O standard
-        Info: Location V22 (pad PAD_303): Pin VD[8] of type bi-directional uses 2.5 V I/O standard
-        Info: Location V21 (pad PAD_304): Pin VA[10] of type output uses 2.5 V I/O standard
-        Info: Location R20 (pad PAD_305): Pin VD[3] of type bi-directional uses 2.5 V I/O standard
-        Info: Location U22 (pad PAD_307): Pin VDQS[2] of type bi-directional uses 2.5 V I/O standard
-        Info: Location U21 (pad PAD_308): Pin VD[7] of type bi-directional uses 2.5 V I/O standard
-        Info: Location R18 (pad PAD_309): Pin VD[9] of type bi-directional uses 2.5 V I/O standard
-        Info: Location R19 (pad PAD_310): Pin VD[6] of type bi-directional uses 2.5 V I/O standard
-        Info: Location R22 (pad PAD_315): Pin VD[14] of type bi-directional uses 2.5 V I/O standard
-        Info: Location R21 (pad PAD_316): Pin VD[11] of type bi-directional uses 2.5 V I/O standard
-        Info: Location P20 (pad PAD_317): Pin VD[13] of type bi-directional uses 2.5 V I/O standard
-        Info: Location P22 (pad PAD_319): Pin VD[2] of type bi-directional uses 2.5 V I/O standard
-        Info: Location P21 (pad PAD_320): Pin VD[4] of type bi-directional uses 2.5 V I/O standard
-        Info: Location N20 (pad PAD_323): Pin VD[15] of type bi-directional uses 2.5 V I/O standard
-        Info: Location N17 (pad PAD_329): Pin VD[12] of type bi-directional uses 2.5 V I/O standard
-        Info: Location M22 (pad PAD_333): Pin VD[0] of type bi-directional uses 2.5 V I/O standard
-        Info: Location M21 (pad PAD_334): Pin VD[1] of type bi-directional uses 2.5 V I/O standard
-Warning: 145 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone&nbsp;III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems).
-    Info: Pin nFB_BURST uses I/O standard 3.3-V LVTTL at T3
-    Info: Pin nACSI_DRQ uses I/O standard 3.3-V LVTTL at K7
-    Info: Pin nACSI_INT uses I/O standard 3.3-V LVTTL at J4
-    Info: Pin nSCSI_DRQ uses I/O standard 3.3-V LVTTL at U1
-    Info: Pin nSCSI_MSG uses I/O standard 3.3-V LVTTL at H2
-    Info: Pin nDCHG uses I/O standard 3.3-V LVTTL at C17
-    Info: Pin SD_DATA0 uses I/O standard 3.3-V LVTTL at B16
-    Info: Pin SD_DATA1 uses I/O standard 3.3-V LVTTL at A16
-    Info: Pin SD_DATA2 uses I/O standard 3.3-V LVTTL at B17
-    Info: Pin SD_CARD_DEDECT uses I/O standard 3.3-V LVTTL at M20
-    Info: Pin SD_WP uses I/O standard 3.3-V LVTTL at M19
-    Info: Pin nDACK0 uses I/O standard 3.3-V LVTTL at B12
-    Info: Pin WP_CF_CARD uses I/O standard 3.3-V LVTTL at T1
-    Info: Pin nSCSI_C_D uses I/O standard 3.3-V LVTTL at H1
-    Info: Pin nSCSI_I_O uses I/O standard 3.3-V LVTTL at J3
-    Info: Pin nFB_CS3 uses I/O standard 3.3-V LVTTL at V6
-    Info: Pin TOUT0 uses I/O standard 3.3-V LVTTL at T22
-    Info: Pin nMASTER uses I/O standard 3.3-V LVTTL at T21
-    Info: Pin FB_AD[31] uses I/O standard 3.3-V LVTTL at AA10
-    Info: Pin FB_AD[30] uses I/O standard 3.3-V LVTTL at Y10
-    Info: Pin FB_AD[29] uses I/O standard 3.3-V LVTTL at W10
-    Info: Pin FB_AD[28] uses I/O standard 3.3-V LVTTL at V11
-    Info: Pin FB_AD[27] uses I/O standard 3.3-V LVTTL at U11
-    Info: Pin FB_AD[26] uses I/O standard 3.3-V LVTTL at AB9
-    Info: Pin FB_AD[25] uses I/O standard 3.3-V LVTTL at AA9
-    Info: Pin FB_AD[24] uses I/O standard 3.3-V LVTTL at T11
-    Info: Pin FB_AD[23] uses I/O standard 3.3-V LVTTL at AB8
-    Info: Pin FB_AD[22] uses I/O standard 3.3-V LVTTL at AA8
-    Info: Pin FB_AD[21] uses I/O standard 3.3-V LVTTL at U10
-    Info: Pin FB_AD[20] uses I/O standard 3.3-V LVTTL at T10
-    Info: Pin FB_AD[19] uses I/O standard 3.3-V LVTTL at V10
-    Info: Pin FB_AD[18] uses I/O standard 3.3-V LVTTL at V9
-    Info: Pin FB_AD[17] uses I/O standard 3.3-V LVTTL at Y8
-    Info: Pin FB_AD[16] uses I/O standard 3.3-V LVTTL at AB7
-    Info: Pin FB_AD[15] uses I/O standard 3.3-V LVTTL at AA7
-    Info: Pin FB_AD[14] uses I/O standard 3.3-V LVTTL at W8
-    Info: Pin FB_AD[13] uses I/O standard 3.3-V LVTTL at V8
-    Info: Pin FB_AD[12] uses I/O standard 3.3-V LVTTL at U9
-    Info: Pin FB_AD[11] uses I/O standard 3.3-V LVTTL at Y7
-    Info: Pin FB_AD[10] uses I/O standard 3.3-V LVTTL at W7
-    Info: Pin FB_AD[9] uses I/O standard 3.3-V LVTTL at AB5
-    Info: Pin FB_AD[8] uses I/O standard 3.3-V LVTTL at AA5
-    Info: Pin FB_AD[7] uses I/O standard 3.3-V LVTTL at AB4
-    Info: Pin FB_AD[6] uses I/O standard 3.3-V LVTTL at AA4
-    Info: Pin FB_AD[5] uses I/O standard 3.3-V LVTTL at V7
-    Info: Pin FB_AD[4] uses I/O standard 3.3-V LVTTL at W6
-    Info: Pin FB_AD[3] uses I/O standard 3.3-V LVTTL at AB3
-    Info: Pin FB_AD[2] uses I/O standard 3.3-V LVTTL at AA3
-    Info: Pin FB_AD[1] uses I/O standard 3.3-V LVTTL at Y6
-    Info: Pin FB_AD[0] uses I/O standard 3.3-V LVTTL at Y3
-    Info: Pin IO[17] uses I/O standard 3.3-V LVTTL at B13
-    Info: Pin IO[16] uses I/O standard 3.3-V LVTTL at A13
-    Info: Pin IO[15] uses I/O standard 3.3-V LVTTL at B14
-    Info: Pin IO[14] uses I/O standard 3.3-V LVTTL at A14
-    Info: Pin IO[13] uses I/O standard 3.3-V LVTTL at E13
-    Info: Pin IO[12] uses I/O standard 3.3-V LVTTL at D13
-    Info: Pin IO[11] uses I/O standard 3.3-V LVTTL at C13
-    Info: Pin IO[10] uses I/O standard 3.3-V LVTTL at B15
-    Info: Pin IO[9] uses I/O standard 3.3-V LVTTL at A15
-    Info: Pin IO[8] uses I/O standard 3.3-V LVTTL at G10
-    Info: Pin IO[7] uses I/O standard 3.3-V LVTTL at C7
-    Info: Pin IO[6] uses I/O standard 3.3-V LVTTL at C8
-    Info: Pin IO[5] uses I/O standard 3.3-V LVTTL at E9
-    Info: Pin IO[4] uses I/O standard 3.3-V LVTTL at B6
-    Info: Pin IO[3] uses I/O standard 3.3-V LVTTL at A6
-    Info: Pin IO[2] uses I/O standard 3.3-V LVTTL at B7
-    Info: Pin IO[1] uses I/O standard 3.3-V LVTTL at A7
-    Info: Pin IO[0] uses I/O standard 3.3-V LVTTL at A8
-    Info: Pin SRD[15] uses I/O standard 3.3-V LVTTL at H10
-    Info: Pin SRD[14] uses I/O standard 3.3-V LVTTL at G9
-    Info: Pin SRD[13] uses I/O standard 3.3-V LVTTL at F10
-    Info: Pin SRD[12] uses I/O standard 3.3-V LVTTL at D10
-    Info: Pin SRD[11] uses I/O standard 3.3-V LVTTL at B10
-    Info: Pin SRD[10] uses I/O standard 3.3-V LVTTL at A9
-    Info: Pin SRD[9] uses I/O standard 3.3-V LVTTL at A10
-    Info: Pin SRD[8] uses I/O standard 3.3-V LVTTL at B9
-    Info: Pin SRD[7] uses I/O standard 3.3-V LVTTL at H11
-    Info: Pin SRD[6] uses I/O standard 3.3-V LVTTL at E10
-    Info: Pin SRD[5] uses I/O standard 3.3-V LVTTL at F9
-    Info: Pin SRD[4] uses I/O standard 3.3-V LVTTL at C10
-    Info: Pin SRD[3] uses I/O standard 3.3-V LVTTL at G11
-    Info: Pin SRD[2] uses I/O standard 3.3-V LVTTL at C6
-    Info: Pin SRD[1] uses I/O standard 3.3-V LVTTL at A5
-    Info: Pin SRD[0] uses I/O standard 3.3-V LVTTL at B5
-    Info: Pin SCSI_PAR uses I/O standard 3.3-V LVTTL at M7
-    Info: Pin nSCSI_SEL uses I/O standard 3.3-V LVTTL at M8
-    Info: Pin nSCSI_BUSY uses I/O standard 3.3-V LVTTL at N8
-    Info: Pin nSCSI_RST uses I/O standard 3.3-V LVTTL at N6
-    Info: Pin SD_CD_DATA3 uses I/O standard 3.3-V LVTTL at F13
-    Info: Pin SD_CMD_D1 uses I/O standard 3.3-V LVTTL at E14
-    Info: Pin ACSI_D[7] uses I/O standard 3.3-V LVTTL at H6
-    Info: Pin ACSI_D[6] uses I/O standard 3.3-V LVTTL at H7
-    Info: Pin ACSI_D[5] uses I/O standard 3.3-V LVTTL at D2
-    Info: Pin ACSI_D[4] uses I/O standard 3.3-V LVTTL at C1
-    Info: Pin ACSI_D[3] uses I/O standard 3.3-V LVTTL at C2
-    Info: Pin ACSI_D[2] uses I/O standard 3.3-V LVTTL at E3
-    Info: Pin ACSI_D[1] uses I/O standard 3.3-V LVTTL at G5
-    Info: Pin ACSI_D[0] uses I/O standard 3.3-V LVTTL at B1
-    Info: Pin LP_D[7] uses I/O standard 3.3-V LVTTL at G8
-    Info: Pin LP_D[6] uses I/O standard 3.3-V LVTTL at A3
-    Info: Pin LP_D[5] uses I/O standard 3.3-V LVTTL at B3
-    Info: Pin LP_D[4] uses I/O standard 3.3-V LVTTL at D6
-    Info: Pin LP_D[3] uses I/O standard 3.3-V LVTTL at E7
-    Info: Pin LP_D[2] uses I/O standard 3.3-V LVTTL at C3
-    Info: Pin LP_D[1] uses I/O standard 3.3-V LVTTL at C4
-    Info: Pin LP_D[0] uses I/O standard 3.3-V LVTTL at F7
-    Info: Pin SCSI_D[7] uses I/O standard 3.3-V LVTTL at K8
-    Info: Pin SCSI_D[6] uses I/O standard 3.3-V LVTTL at L8
-    Info: Pin SCSI_D[5] uses I/O standard 3.3-V LVTTL at G3
-    Info: Pin SCSI_D[4] uses I/O standard 3.3-V LVTTL at G4
-    Info: Pin SCSI_D[3] uses I/O standard 3.3-V LVTTL at F1
-    Info: Pin SCSI_D[2] uses I/O standard 3.3-V LVTTL at F2
-    Info: Pin SCSI_D[1] uses I/O standard 3.3-V LVTTL at E1
-    Info: Pin SCSI_D[0] uses I/O standard 3.3-V LVTTL at J6
-    Info: Pin nRSTO_MCF uses I/O standard 3.3-V LVTTL at B11
-    Info: Pin nFB_WR uses I/O standard 3.3-V LVTTL at T5
-    Info: Pin nFB_CS1 uses I/O standard 3.3-V LVTTL at T8
-    Info: Pin FB_SIZE1 uses I/O standard 3.3-V LVTTL at Y4
-    Info: Pin FB_SIZE0 uses I/O standard 3.3-V LVTTL at U8
-    Info: Pin FB_ALE uses I/O standard 3.3-V LVTTL at R7
-    Info: Pin nFB_CS2 uses I/O standard 3.3-V LVTTL at T9
-    Info: Pin MAIN_CLK uses I/O standard 3.3-V LVTTL at G2
-    Info: Pin nDACK1 uses I/O standard 3.3-V LVTTL at A12
-    Info: Pin nFB_OE uses I/O standard 3.3-V LVTTL at R6
-    Info: Pin IDE_RDY uses I/O standard 3.3-V LVTTL at Y1
-    Info: Pin CLK33M uses I/O standard 3.3-V LVTTL at AB12
-    Info: Pin HD_DD uses I/O standard 3.3-V LVTTL at F16
-    Info: Pin nINDEX uses I/O standard 3.3-V LVTTL at E16
-    Info: Pin RxD uses I/O standard 3.3-V LVTTL at H15
-    Info: Pin nWP uses I/O standard 3.3-V LVTTL at D19
-    Info: Pin LP_BUSY uses I/O standard 3.3-V LVTTL at G7
-    Info: Pin DCD uses I/O standard 3.3-V LVTTL at A19
-    Info: Pin CTS uses I/O standard 3.3-V LVTTL at H14
-    Info: Pin TRACK00 uses I/O standard 3.3-V LVTTL at C19
-    Info: Pin RI uses I/O standard 3.3-V LVTTL at B19
-    Info: Pin nPCI_INTD uses I/O standard 3.3-V LVTTL at P6
-    Info: Pin nPCI_INTC uses I/O standard 3.3-V LVTTL at V3
-    Info: Pin nPCI_INTB uses I/O standard 3.3-V LVTTL at V4
-    Info: Pin nPCI_INTA uses I/O standard 3.3-V LVTTL at AA1
-    Info: Pin DVI_INT uses I/O standard 3.3-V LVTTL at A11
-    Info: Pin PIC_INT uses I/O standard 3.3-V LVTTL at AA2
-    Info: Pin PIC_AMKB_RX uses I/O standard 3.3-V LVTTL at L7
-    Info: Pin MIDI_IN uses I/O standard 3.3-V LVTTL at E12
-    Info: Pin nRD_DATA uses I/O standard 3.3-V LVTTL at A20
-    Info: Pin AMKB_RX uses I/O standard 3.3-V LVTTL at Y2
-Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
-    Info: Pin IO[17] has a permanently enabled output enable
-    Info: Pin IO[16] has a permanently enabled output enable
-    Info: Pin IO[15] has a permanently enabled output enable
-    Info: Pin IO[14] has a permanently enabled output enable
-    Info: Pin IO[13] has a permanently enabled output enable
-    Info: Pin IO[12] has a permanently enabled output enable
-    Info: Pin IO[11] has a permanently enabled output enable
-    Info: Pin IO[10] has a permanently enabled output enable
-    Info: Pin IO[9] has a permanently enabled output enable
-    Info: Pin IO[8] has a permanently enabled output enable
-    Info: Pin IO[7] has a permanently enabled output enable
-    Info: Pin IO[6] has a permanently enabled output enable
-    Info: Pin IO[5] has a permanently enabled output enable
-    Info: Pin IO[4] has a permanently enabled output enable
-    Info: Pin IO[3] has a permanently enabled output enable
-    Info: Pin IO[2] has a permanently enabled output enable
-    Info: Pin IO[1] has a permanently enabled output enable
-    Info: Pin IO[0] has a permanently enabled output enable
-    Info: Pin SCSI_PAR has a permanently disabled output enable
-    Info: Pin nSCSI_SEL has a permanently enabled output enable
-    Info: Pin nSCSI_BUSY has a permanently enabled output enable
-    Info: Pin nSCSI_RST has a permanently disabled output enable
-    Info: Pin SD_CD_DATA3 has a permanently disabled output enable
-    Info: Pin SD_CMD_D1 has a permanently disabled output enable
-    Info: Pin ACSI_D[7] has a permanently disabled output enable
-    Info: Pin ACSI_D[6] has a permanently disabled output enable
-    Info: Pin ACSI_D[5] has a permanently disabled output enable
-    Info: Pin ACSI_D[4] has a permanently disabled output enable
-    Info: Pin ACSI_D[3] has a permanently disabled output enable
-    Info: Pin ACSI_D[2] has a permanently disabled output enable
-    Info: Pin ACSI_D[1] has a permanently disabled output enable
-    Info: Pin ACSI_D[0] has a permanently disabled output enable
-    Info: Pin SCSI_D[7] has a permanently disabled output enable
-    Info: Pin SCSI_D[6] has a permanently disabled output enable
-    Info: Pin SCSI_D[5] has a permanently disabled output enable
-    Info: Pin SCSI_D[4] has a permanently disabled output enable
-    Info: Pin SCSI_D[3] has a permanently disabled output enable
-    Info: Pin SCSI_D[2] has a permanently disabled output enable
-    Info: Pin SCSI_D[1] has a permanently disabled output enable
-    Info: Pin SCSI_D[0] has a permanently disabled output enable
-Info: Quartus II Fitter was successful. 0 errors, 34 warnings
-    Info: Peak virtual memory: 334 megabytes
-    Info: Processing ended: Wed Dec 15 02:25:07 2010
-    Info: Elapsed time: 00:03:10
-    Info: Total CPU time (on all processors): 00:03:11
-
-
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
index f177099..f4ccea5 100644
--- a/FPGA_by_Fredi/firebee1.fit.summary
+++ b/FPGA_by_Fredi/firebee1.fit.summary
@@ -1,16 +1,16 @@
-Fitter Status : Successful - Wed Dec 15 02:25:02 2010
+Fitter Status : Successful - Fri Aug 28 13:39:32 2015
 Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
 Revision Name : firebee1
 Top-level Entity Name : firebee1
 Family : Cyclone III
 Device : EP3C40F484C6
 Timing Models : Final
-Total logic elements : 9,526 / 39,600 ( 24 % )
-    Total combinational functions : 8,061 / 39,600 ( 20 % )
-    Dedicated logic registers : 4,563 / 39,600 ( 12 % )
-Total registers : 4749
+Total logic elements : 10,207 / 39,600 ( 26 % )
+    Total combinational functions : 8,661 / 39,600 ( 22 % )
+    Dedicated logic registers : 5,025 / 39,600 ( 13 % )
+Total registers : 5162
 Total pins : 295 / 332 ( 89 % )
 Total virtual pins : 0
-Total memory bits : 109,344 / 1,161,216 ( 9 % )
+Total memory bits : 109,600 / 1,161,216 ( 9 % )
 Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % )
 Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.flow.rpt b/FPGA_by_Fredi/firebee1.flow.rpt
deleted file mode 100644
index 297d7a0..0000000
--- a/FPGA_by_Fredi/firebee1.flow.rpt
+++ /dev/null
@@ -1,380 +0,0 @@
-Flow report for firebee1
-Wed Dec 15 02:25:22 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary                                                                      ;
-+------------------------------------+----------------------------------------------+
-; Flow Status                        ; Successful - Wed Dec 15 02:25:21 2010        ;
-; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
-; Revision Name                      ; firebee1                                     ;
-; Top-level Entity Name              ; firebee1                                     ;
-; Family                             ; Cyclone III                                  ;
-; Device                             ; EP3C40F484C6                                 ;
-; Timing Models                      ; Final                                        ;
-; Met timing requirements            ; No                                           ;
-; Total logic elements               ; 9,526 / 39,600 ( 24 % )                      ;
-;     Total combinational functions  ; 8,061 / 39,600 ( 20 % )                      ;
-;     Dedicated logic registers      ; 4,563 / 39,600 ( 12 % )                      ;
-; Total registers                    ; 4749                                         ;
-; Total pins                         ; 295 / 332 ( 89 % )                           ;
-; Total virtual pins                 ; 0                                            ;
-; Total memory bits                  ; 109,344 / 1,161,216 ( 9 % )                  ;
-; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % )                              ;
-; Total PLLs                         ; 4 / 4 ( 100 % )                              ;
-+------------------------------------+----------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 12/15/2010 02:20:37 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; firebee1            ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                            ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; Assignment Name                         ; Value                              ; Default Value ; Entity Name ; Section Id     ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID                   ; 150661768621.129237603704664       ; --            ; --          ; --             ;
-; CYCLONEII_OPTIMIZATION_TECHNIQUE        ; Speed                              ; Balanced      ; --          ; --             ;
-; FMAX_REQUIREMENT                        ; 30 ns                              ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_LATCH                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COMPARE                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_BIDIR                      ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL_RECONFIG                    ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP                  ; 85                                 ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP                  ; 0                                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/firebee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.bsf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.inc           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.cmp           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.ppf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.inc                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.ppf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/FireBee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.tdf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.inc               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.tdf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.ppf                        ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE             ; 1.2V                               ; --            ; --          ; --             ;
-; PARTITION_COLOR                         ; 16764057                           ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE                  ; SOURCE                             ; --            ; --          ; Top            ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC          ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_EFFORT               ; Fast                               ; Normal        ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On                                 ; Off           ; --          ; --             ;
-; STATE_MACHINE_PROCESSING                ; One-Hot                            ; Auto          ; --          ; --             ;
-; TCO_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TH_REQUIREMENT                          ; 1 ns                               ; --            ; --          ; --             ;
-; TPD_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TSU_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS      ; Off                                ; --            ; --          ; eda_blast_fpga ;
-; USE_TIMEQUEST_TIMING_ANALYZER           ; Off                                ; On            ; --          ; --             ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                           ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name             ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis    ; 00:01:16     ; 1.0                     ; 347 MB              ; 00:01:17                           ;
-; Fitter                  ; 00:03:05     ; 1.0                     ; 334 MB              ; 00:03:07                           ;
-; Assembler               ; 00:00:05     ; 1.0                     ; 291 MB              ; 00:00:04                           ;
-; Classic Timing Analyzer ; 00:00:07     ; 1.0                     ; 227 MB              ; 00:00:09                           ;
-; Total                   ; 00:04:33     ; --                      ; --                  ; 00:04:37                           ;
-+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+------------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                          ;
-+-------------------------+------------------+---------------+------------+----------------+
-; Module Name             ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
-+-------------------------+------------------+---------------+------------+----------------+
-; Analysis & Synthesis    ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Fitter                  ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Assembler               ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-; Classic Timing Analyzer ; envy15           ; Windows Vista ; 6.1        ; x86_64         ;
-+-------------------------+------------------+---------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
-quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only
-
-
-
diff --git a/FPGA_by_Fredi/firebee1.map.rpt b/FPGA_by_Fredi/firebee1.map.rpt
deleted file mode 100644
index 11a1ac1..0000000
--- a/FPGA_by_Fredi/firebee1.map.rpt
+++ /dev/null
@@ -1,8590 +0,0 @@
-Analysis & Synthesis report for firebee1
-Wed Dec 15 02:21:56 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Analysis & Synthesis Summary
-  3. Analysis & Synthesis Settings
-  4. Parallel Compilation
-  5. Analysis & Synthesis Source Files Read
-  6. Analysis & Synthesis Resource Usage Summary
-  7. Analysis & Synthesis Resource Utilization by Entity
-  8. Analysis & Synthesis RAM Summary
-  9. Analysis & Synthesis DSP Block Usage Summary
- 10. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR
- 11. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM
- 12. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE
- 13. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE
- 14. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE
- 15. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE
- 16. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE
- 17. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE
- 18. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE
- 19. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE
- 20. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE
- 21. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE
- 22. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE
- 23. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP
- 24. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE
- 25. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE
- 26. Registers Protected by Synthesis
- 27. User-Specified and Inferred Latches
- 28. Registers Removed During Synthesis
- 29. Removed Registers Triggering Further Register Optimizations
- 30. General Register Statistics
- 31. Inverted Register Statistics
- 32. Multiplexer Restructuring Statistics (Restructuring Performed)
- 33. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated
- 34. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p
- 35. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p
- 36. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram
- 37. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp
- 38. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12
- 39. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp
- 40. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp
- 41. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp
- 42. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17
- 43. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated
- 44. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p
- 45. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p
- 46. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram
- 47. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp
- 48. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp
- 49. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp
- 50. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12
- 51. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp
- 52. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15
- 53. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component
- 54. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated
- 55. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p
- 56. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p
- 57. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp
- 58. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram
- 59. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp
- 60. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15
- 61. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr
- 62. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp
- 63. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp
- 64. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp
- 65. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22
- 66. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component
- 67. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated
- 68. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
- 69. Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram
- 70. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
- 71. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated
- 72. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
- 73. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
- 74. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated
- 75. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
- 76. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
- 77. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated
- 78. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component
- 79. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated
- 80. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component
- 81. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated
- 82. Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated
- 83. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component
- 84. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated
- 85. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1
- 86. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12
- 87. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13
- 88. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14
- 89. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15
- 90. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2
- 91. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3
- 92. Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component
- 93. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component
- 94. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
- 95. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component
- 96. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
- 97. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component
- 98. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
- 99. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component
-100. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated
-101. Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component
-102. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component
-103. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component
-104. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL
-105. Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component
-106. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component
-107. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component
-108. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component
-109. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component
-110. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component
-111. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component
-112. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component
-113. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component
-114. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component
-115. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component
-116. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component
-117. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component
-118. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component
-119. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component
-120. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component
-121. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component
-122. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component
-123. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component
-124. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component
-125. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component
-126. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component
-127. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component
-128. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component
-129. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component
-130. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component
-131. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component
-132. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component
-133. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component
-134. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component
-135. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component
-136. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component
-137. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component
-138. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component
-139. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component
-140. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component
-141. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component
-142. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component
-143. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component
-144. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component
-145. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component
-146. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component
-147. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component
-148. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component
-149. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component
-150. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component
-151. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component
-152. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component
-153. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component
-154. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component
-155. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component
-156. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component
-157. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component
-158. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component
-159. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component
-160. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component
-161. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component
-162. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component
-163. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component
-164. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component
-165. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component
-166. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component
-167. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component
-168. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component
-169. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component
-170. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component
-171. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component
-172. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component
-173. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component
-174. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component
-175. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component
-176. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component
-177. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component
-178. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component
-179. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component
-180. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component
-181. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component
-182. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component
-183. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component
-184. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component
-185. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component
-186. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component
-187. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component
-188. Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component
-189. Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component
-190. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component
-191. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4
-192. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5
-193. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6
-194. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7
-195. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1
-196. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12
-197. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13
-198. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14
-199. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15
-200. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2
-201. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3
-202. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11
-203. Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component
-204. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component
-205. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component
-206. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component
-207. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component
-208. Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component
-209. Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component
-210. Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component
-211. Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component
-212. Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component
-213. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14
-214. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6
-215. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12
-216. altpll Parameter Settings by Entity Instance
-217. lpm_shiftreg Parameter Settings by Entity Instance
-218. dcfifo Parameter Settings by Entity Instance
-219. scfifo Parameter Settings by Entity Instance
-220. altsyncram Parameter Settings by Entity Instance
-221. lpm_mult Parameter Settings by Entity Instance
-222. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"
-223. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"
-224. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI"
-225. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD"
-226. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS"
-227. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"
-228. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"
-229. Analysis & Synthesis Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary                                                      ;
-+------------------------------------+----------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Wed Dec 15 02:21:55 2010        ;
-; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
-; Revision Name                      ; firebee1                                     ;
-; Top-level Entity Name              ; firebee1                                     ;
-; Family                             ; Cyclone III                                  ;
-; Total logic elements               ; 10,706                                       ;
-;     Total combinational functions  ; 8,060                                        ;
-;     Dedicated logic registers      ; 4,612                                        ;
-; Total registers                    ; 4740                                         ;
-; Total pins                         ; 295                                          ;
-; Total virtual pins                 ; 0                                            ;
-; Total memory bits                  ; 109,344                                      ;
-; Embedded Multiplier 9-bit elements ; 6                                            ;
-; Total PLLs                         ; 4                                            ;
-+------------------------------------+----------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings                                                                                        ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Option                                                                     ; Setting            ; Default Value      ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device                                                                     ; EP3C40F484C6       ;                    ;
-; Top-level entity name                                                      ; firebee1           ; firebee1           ;
-; Family name                                                                ; Cyclone III        ; Stratix II         ;
-; State Machine Processing                                                   ; One-Hot            ; Auto               ;
-; Optimization Technique                                                     ; Speed              ; Balanced           ;
-; Use Generated Physical Constraints File                                    ; Off                ;                    ;
-; Use smart compilation                                                      ; Off                ; Off                ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
-; Enable compact report table                                                ; Off                ; Off                ;
-; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
-; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
-; Preserve fewer node names                                                  ; On                 ; On                 ;
-; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
-; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
-; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
-; Safe State Machine                                                         ; Off                ; Off                ;
-; Extract Verilog State Machines                                             ; On                 ; On                 ;
-; Extract VHDL State Machines                                                ; On                 ; On                 ;
-; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
-; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
-; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
-; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
-; Parallel Synthesis                                                         ; On                 ; On                 ;
-; DSP Block Balancing                                                        ; Auto               ; Auto               ;
-; NOT Gate Push-Back                                                         ; On                 ; On                 ;
-; Power-Up Don't Care                                                        ; On                 ; On                 ;
-; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
-; Remove Duplicate Registers                                                 ; On                 ; On                 ;
-; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
-; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
-; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
-; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
-; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
-; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
-; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
-; Carry Chain Length                                                         ; 70                 ; 70                 ;
-; Auto Carry Chains                                                          ; On                 ; On                 ;
-; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
-; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
-; Auto ROM Replacement                                                       ; On                 ; On                 ;
-; Auto RAM Replacement                                                       ; On                 ; On                 ;
-; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
-; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
-; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
-; Strict RAM Replacement                                                     ; Off                ; Off                ;
-; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
-; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
-; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
-; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
-; Auto Resource Sharing                                                      ; Off                ; Off                ;
-; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
-; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
-; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
-; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
-; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
-; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
-; Show Parameter Settings Tables in Synthesis Report                         ; On                 ; On                 ;
-; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
-; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
-; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
-; HDL message level                                                          ; Level2             ; Level2             ;
-; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
-; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
-; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
-; Clock MUX Protection                                                       ; On                 ; On                 ;
-; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
-; Block Design Naming                                                        ; Auto               ; Auto               ;
-; SDC constraint protection                                                  ; Off                ; Off                ;
-; Synthesis Effort                                                           ; Auto               ; Auto               ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
-; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
-; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
-; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
-+----------------------------------------------------------------------------+--------------------+--------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read                                                                                                                                                                 ;
-+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
-; File Name with User-Entered Path                               ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                   ;
-+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
-; FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd               ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd               ;
-; FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd                   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd                   ;
-; FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd             ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd             ;
-; FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd               ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd               ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd  ;
-; FalconIO_SDCard_IDE_CF/dcfifo0.vhd                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo0.vhd                             ;
-; Video/DDR_CTR.tdf                                              ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Video/DDR_CTR.tdf                                              ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd      ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd    ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd  ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd          ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd    ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd      ;
-; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd  ;
-; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ;
-; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd     ;
-; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd     ;
-; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd    ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd       ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd       ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd        ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd        ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd     ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd     ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd    ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd   ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd  ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd  ;
-; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd   ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd   ;
-; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd          ;
-; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd      ;
-; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd         ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd         ;
-; lpm_latch0.vhd                                                 ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_latch0.vhd                                                 ;
-; altpll1.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll1.vhd                                                    ;
-; Video/lpm_fifoDZ.vhd                                           ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_fifoDZ.vhd                                           ;
-; altpll2.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll2.vhd                                                    ;
-; altpll3.vhd                                                    ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altpll3.vhd                                                    ;
-; Video/altdpram0.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram0.vhd                                            ;
-; Video/lpm_muxDZ.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_muxDZ.vhd                                            ;
-; Video/lpm_bustri3.vhd                                          ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_bustri3.vhd                                          ;
-; Video/lpm_ff0.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff0.vhd                                              ;
-; Video/lpm_ff1.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff1.vhd                                              ;
-; Video/lpm_ff3.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff3.vhd                                              ;
-; Video/VIDEO_MOD_MUX_CLUTCTR.tdf                                ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Video/VIDEO_MOD_MUX_CLUTCTR.tdf                                ;
-; Video/lpm_fifo_dc0.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_fifo_dc0.vhd                                         ;
-; Video/Video.bdf                                                ; yes             ; User Block Diagram/Schematic File  ; C:/FireBee/FPGA/Video/Video.bdf                                                ;
-; firebee1.bdf                                                   ; yes             ; User Block Diagram/Schematic File  ; C:/FireBee/FPGA/firebee1.bdf                                                   ;
-; lpm_counter0.vhd                                               ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_counter0.vhd                                               ;
-; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd              ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd              ;
-; DSP/DSP.vhd                                                    ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/DSP/DSP.vhd                                                    ;
-; Video/lpm_shiftreg0.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg0.vhd                                        ;
-; Video/lpm_bustri1.vhd                                          ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_bustri1.vhd                                          ;
-; Video/altdpram1.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram1.vhd                                            ;
-; Video/lpm_constant0.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant0.vhd                                        ;
-; Video/lpm_constant1.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant1.vhd                                        ;
-; Video/lpm_mux0.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux0.vhd                                             ;
-; Video/lpm_mux1.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux1.vhd                                             ;
-; Video/lpm_mux2.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux2.vhd                                             ;
-; Video/lpm_constant2.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant2.vhd                                        ;
-; Video/altdpram2.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altdpram2.vhd                                            ;
-; Video/lpm_mux3.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux3.vhd                                             ;
-; Video/lpm_mux4.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux4.vhd                                             ;
-; Video/lpm_constant3.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_constant3.vhd                                        ;
-; Interrupt_Handler/interrupt_handler.tdf                        ; yes             ; User AHDL File                     ; C:/FireBee/FPGA/Interrupt_Handler/interrupt_handler.tdf                        ;
-; lpm_bustri_LONG.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_LONG.vhd                                            ;
-; lpm_bustri_BYT.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_BYT.vhd                                             ;
-; lpm_bustri_WORD.vhd                                            ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/lpm_bustri_WORD.vhd                                            ;
-; Video/lpm_ff4.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff4.vhd                                              ;
-; Video/lpm_ff5.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff5.vhd                                              ;
-; Video/lpm_ff6.vhd                                              ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_ff6.vhd                                              ;
-; Video/altddio_bidir0.vhd                                       ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_bidir0.vhd                                       ;
-; Video/altddio_out0.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_out0.vhd                                         ;
-; Video/lpm_mux5.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux5.vhd                                             ;
-; Video/BLITTER/BLITTER.vhd                                      ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/Video/BLITTER/BLITTER.vhd                                      ;
-; Video/lpm_shiftreg6.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg6.vhd                                        ;
-; Video/lpm_shiftreg4.vhd                                        ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_shiftreg4.vhd                                        ;
-; Video/altddio_out2.vhd                                         ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/altddio_out2.vhd                                         ;
-; altddio_out3.vhd                                               ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/altddio_out3.vhd                                               ;
-; Video/lpm_mux6.vhd                                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_mux6.vhd                                             ;
-; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd          ; yes             ; User VHDL File                     ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd          ;
-; FalconIO_SDCard_IDE_CF/dcfifo1.vhd                             ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo1.vhd                             ;
-; Video/lpm_muxVDM.vhd                                           ; yes             ; User Wizard-Generated File         ; C:/FireBee/FPGA/Video/lpm_muxVDM.vhd                                           ;
-; lpm_bustri_byt.inc                                             ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_byt.inc                                             ;
-; lpm_bustri_word.inc                                            ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_word.inc                                            ;
-; lpm_bustri_long.inc                                            ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/lpm_bustri_long.inc                                            ;
-; altpll.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.tdf                     ;
-; db/altpll_pul2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_pul2.tdf                                             ;
-; dcfifo_mixed_widths.tdf                                        ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf        ;
-; db/dcfifo_0hh1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_0hh1.tdf                                             ;
-; db/a_gray2bin_lfb.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_gray2bin_lfb.tdf                                          ;
-; db/a_graycounter_k47.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_k47.tdf                                       ;
-; db/a_graycounter_fic.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_fic.tdf                                       ;
-; db/altsyncram_bi31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_bi31.tdf                                         ;
-; db/alt_synch_pipe_ikd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_ikd.tdf                                      ;
-; db/dffpipe_hd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_hd9.tdf                                             ;
-; db/dffpipe_gd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_gd9.tdf                                             ;
-; db/dffpipe_pe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_pe9.tdf                                             ;
-; db/alt_synch_pipe_jkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_jkd.tdf                                      ;
-; db/dffpipe_id9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_id9.tdf                                             ;
-; db/cmpr_256.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_256.tdf                                                ;
-; db/cmpr_156.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_156.tdf                                                ;
-; db/cntr_t2e.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_t2e.tdf                                                ;
-; db/mux_a18.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_a18.tdf                                                 ;
-; db/dcfifo_3fh1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_3fh1.tdf                                             ;
-; db/a_graycounter_j47.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_j47.tdf                                       ;
-; db/a_graycounter_gic.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_gic.tdf                                       ;
-; db/altsyncram_ci31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_ci31.tdf                                         ;
-; db/alt_synch_pipe_kkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_kkd.tdf                                      ;
-; db/dffpipe_jd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_jd9.tdf                                             ;
-; db/alt_synch_pipe_lkd.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_lkd.tdf                                      ;
-; db/dffpipe_kd9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_kd9.tdf                                             ;
-; db/altpll_41p2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_41p2.tdf                                             ;
-; lpm_bustri.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_bustri.tdf                 ;
-; lpm_shiftreg.tdf                                               ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf               ;
-; dcfifo.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo.tdf                     ;
-; db/dcfifo_8fi1.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dcfifo_8fi1.tdf                                             ;
-; db/a_gray2bin_tgb.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_gray2bin_tgb.tdf                                          ;
-; db/a_graycounter_s57.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_s57.tdf                                       ;
-; db/a_graycounter_ojc.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_ojc.tdf                                       ;
-; db/a_graycounter_njc.tdf                                       ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_graycounter_njc.tdf                                       ;
-; db/altsyncram_tl31.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_tl31.tdf                                         ;
-; db/alt_synch_pipe_rld.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_rld.tdf                                      ;
-; db/dffpipe_qe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_qe9.tdf                                             ;
-; db/dffpipe_9d9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_9d9.tdf                                             ;
-; db/dffpipe_oe9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_oe9.tdf                                             ;
-; db/alt_synch_pipe_sld.tdf                                      ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/alt_synch_pipe_sld.tdf                                      ;
-; db/dffpipe_re9.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/dffpipe_re9.tdf                                             ;
-; lpm_mux.tdf                                                    ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf                    ;
-; db/mux_bbe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_bbe.tdf                                                 ;
-; lpm_ff.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_ff.tdf                     ;
-; altddio_bidir.tdf                                              ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_bidir.tdf              ;
-; db/ddio_bidir_3jl.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_bidir_3jl.tdf                                          ;
-; db/mux_58e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_58e.tdf                                                 ;
-; lpm_latch.tdf                                                  ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_latch.tdf                  ;
-; altsyncram.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf                 ;
-; db/altsyncram_lf92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_lf92.tdf                                         ;
-; mux41.bdf                                                      ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/others/maxplus2/mux41.bdf                    ;
-; db/mux_dcf.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_dcf.tdf                                                 ;
-; scfifo.tdf                                                     ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/scfifo.tdf                     ;
-; db/scfifo_lk21.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/scfifo_lk21.tdf                                             ;
-; db/a_dpfifo_oq21.tdf                                           ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/a_dpfifo_oq21.tdf                                           ;
-; db/altsyncram_gj81.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_gj81.tdf                                         ;
-; db/cmpr_br8.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_br8.tdf                                                ;
-; db/cntr_omb.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_omb.tdf                                                ;
-; db/cntr_5n7.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_5n7.tdf                                                ;
-; db/cntr_pmb.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_pmb.tdf                                                ;
-; db/altsyncram_rb92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_rb92.tdf                                         ;
-; db/altsyncram_pf92.tdf                                         ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_pf92.tdf                                         ;
-; db/mux_96e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_96e.tdf                                                 ;
-; db/mux_mpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_mpe.tdf                                                 ;
-; db/mux_f6e.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_f6e.tdf                                                 ;
-; lpm_constant.tdf                                               ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_constant.tdf               ;
-; altddio_out.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_out.tdf                ;
-; db/ddio_out_o2f.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_o2f.tdf                                            ;
-; db/mux_kpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_kpe.tdf                                                 ;
-; db/mux_npe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_npe.tdf                                                 ;
-; db/mux_gpe.tdf                                                 ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mux_gpe.tdf                                                 ;
-; db/ddio_out_are.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_are.tdf                                            ;
-; db/altpll_isv2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_isv2.tdf                                             ;
-; altpll4.tdf                                                    ; yes             ; Auto-Found Wizard-Generated File   ; C:/FireBee/FPGA/altpll4.tdf                                                    ;
-; altpll.inc                                                     ; yes             ; Auto-Found AHDL File               ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.inc                     ;
-; db/altpll_c6j2.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altpll_c6j2.tdf                                             ;
-; altpll_reconfig1.tdf                                           ; yes             ; Auto-Found Wizard-Generated File   ; C:/FireBee/FPGA/altpll_reconfig1.tdf                                           ;
-; altpll_reconfig1_pllrcfg_t4q.tdf                               ; yes             ; Auto-Found AHDL File               ; C:/FireBee/FPGA/altpll_reconfig1_pllrcfg_t4q.tdf                               ;
-; altsyncram.inc                                                 ; yes             ; Auto-Found AHDL File               ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.inc                 ;
-; db/altsyncram_46r.tdf                                          ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/altsyncram_46r.tdf                                          ;
-; lpm_add_sub.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf                ;
-; db/add_sub_hpa.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/add_sub_hpa.tdf                                             ;
-; db/add_sub_k8a.tdf                                             ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/add_sub_k8a.tdf                                             ;
-; lpm_compare.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_compare.tdf                ;
-; db/cmpr_tnd.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cmpr_tnd.tdf                                                ;
-; lpm_counter.tdf                                                ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf                ;
-; db/cntr_30l.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_30l.tdf                                                ;
-; db/cntr_qij.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_qij.tdf                                                ;
-; db/cntr_pij.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_pij.tdf                                                ;
-; db/cntr_9cj.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_9cj.tdf                                                ;
-; lpm_decode.tdf                                                 ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf                 ;
-; db/decode_2af.tdf                                              ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/decode_2af.tdf                                              ;
-; db/cntr_mph.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/cntr_mph.tdf                                                ;
-; db/ddio_out_31f.tdf                                            ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/ddio_out_31f.tdf                                            ;
-; lpm_mult.tdf                                                   ; yes             ; Megafunction                       ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mult.tdf                   ;
-; db/mult_cat.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mult_cat.tdf                                                ;
-; db/mult_aat.tdf                                                ; yes             ; Auto-Generated Megafunction        ; C:/FireBee/FPGA/db/mult_aat.tdf                                                ;
-+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary                  ;
-+---------------------------------------------+----------------+
-; Resource                                    ; Usage          ;
-+---------------------------------------------+----------------+
-; Estimated Total logic elements              ; 10,706         ;
-;                                             ;                ;
-; Total combinational functions               ; 8060           ;
-; Logic element usage by number of LUT inputs ;                ;
-;     -- 4 input functions                    ; 4947           ;
-;     -- 3 input functions                    ; 1867           ;
-;     -- <=2 input functions                  ; 1246           ;
-;                                             ;                ;
-; Logic elements by mode                      ;                ;
-;     -- normal mode                          ; 7261           ;
-;     -- arithmetic mode                      ; 799            ;
-;                                             ;                ;
-; Total registers                             ; 4740           ;
-;     -- Dedicated logic registers            ; 4612           ;
-;     -- I/O registers                        ; 256            ;
-;                                             ;                ;
-; I/O pins                                    ; 295            ;
-; Total memory bits                           ; 109344         ;
-; Embedded Multiplier 9-bit elements          ; 6              ;
-; Total PLLs                                  ; 4              ;
-; Maximum fan-out node                        ; MAIN_CLK~input ;
-; Maximum fan-out                             ; 2327           ;
-; Total fan-out                               ; 49317          ;
-; Average fan-out                             ; 3.57           ;
-+---------------------------------------------+----------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                        ;
-+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node                                                  ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                               ; Library Name ;
-+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; |firebee1                                                                   ; 8060 (10)         ; 4612 (0)     ; 109344      ; 6            ; 0       ; 3         ; 295  ; 0            ; |firebee1                                                                                                                                                                                                         ; work         ;
-;    |DSP:Mathias_Alles|                                                      ; 10 (10)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|DSP:Mathias_Alles                                                                                                                                                                                       ;              ;
-;    |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|          ; 3814 (634)        ; 1633 (114)   ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden                                                                                                                                           ;              ;
-;       |WF1772IP_TOP_SOC:I_FDC|                                              ; 944 (24)          ; 406 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC                                                                                                                    ;              ;
-;          |WF1772IP_AM_DETECTOR:I_AM_DETECTOR|                               ; 39 (39)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR                                                                                 ;              ;
-;          |WF1772IP_CONTROL:I_CONTROL|                                       ; 533 (533)         ; 197 (197)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL                                                                                         ;              ;
-;          |WF1772IP_CRC_LOGIC:I_CRC_LOGIC|                                   ; 40 (40)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC                                                                                     ;              ;
-;          |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|                               ; 104 (104)         ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL                                                                                 ;              ;
-;          |WF1772IP_REGISTERS:I_REGISTERS|                                   ; 86 (86)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS                                                                                     ;              ;
-;          |WF1772IP_TRANSCEIVER:I_TRANSCEIVER|                               ; 118 (118)         ; 80 (80)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER                                                                                 ;              ;
-;       |WF2149IP_TOP_SOC:I_SOUND|                                            ; 445 (32)          ; 210 (29)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND                                                                                                                  ;              ;
-;          |WF2149IP_WAVE:I_PSG_WAVE|                                         ; 413 (413)         ; 181 (181)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE                                                                                         ;              ;
-;       |WF5380_TOP_SOC:I_SCSI|                                               ; 0 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI                                                                                                                     ;              ;
-;          |WF5380_CONTROL:I_CONTROL|                                         ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL                                                                                            ;              ;
-;       |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|                                    ; 199 (2)           ; 97 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD                                                                                                          ;              ;
-;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 16 (16)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                  ;              ;
-;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 94 (94)           ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                          ;              ;
-;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)           ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                        ;              ;
-;       |WF6850IP_TOP_SOC:I_ACIA_MIDI|                                        ; 203 (2)           ; 97 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI                                                                                                              ;              ;
-;          |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|                          ; 20 (20)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS                                                                      ;              ;
-;          |WF6850IP_RECEIVE:I_UART_RECEIVE|                                  ; 94 (94)           ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE                                                                              ;              ;
-;          |WF6850IP_TRANSMIT:I_UART_TRANSMIT|                                ; 87 (87)           ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT                                                                            ;              ;
-;       |WF68901IP_TOP_SOC:I_MFP|                                             ; 1199 (178)        ; 460 (2)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP                                                                                                                   ;              ;
-;          |WF68901IP_GPIO:I_GPIO|                                            ; 25 (25)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO                                                                                             ;              ;
-;          |WF68901IP_INTERRUPTS:I_INTERRUPTS|                                ; 273 (273)         ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS                                                                                 ;              ;
-;          |WF68901IP_TIMERS:I_TIMERS|                                        ; 434 (434)         ; 166 (166)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS                                                                                         ;              ;
-;          |WF68901IP_USART_TOP:I_USART|                                      ; 289 (4)           ; 140 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART                                                                                       ;              ;
-;             |WF68901IP_USART_CTRL:I_USART_CTRL|                             ; 38 (38)           ; 49 (49)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL                                                     ;              ;
-;             |WF68901IP_USART_RX:I_USART_RECEIVE|                            ; 159 (159)         ; 56 (56)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE                                                    ;              ;
-;             |WF68901IP_USART_TX:I_USART_TRANSMIT|                           ; 88 (88)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT                                                   ;              ;
-;       |dcfifo0:RDF|                                                         ; 94 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF                                                                                                                               ;              ;
-;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 94 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
-;             |dcfifo_0hh1:auto_generated|                                    ; 94 (17)           ; 124 (42)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated                                                  ;              ;
-;                |a_gray2bin_lfb:wrptr_g_gray2bin|                            ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin                  ;              ;
-;                |a_gray2bin_lfb:ws_dgrp_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin                  ;              ;
-;                |a_graycounter_fic:wrptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p                      ;              ;
-;                |a_graycounter_k47:rdptr_g1p|                                ; 17 (17)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p                      ;              ;
-;                |alt_synch_pipe_ikd:rs_dgwp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp                       ;              ;
-;                   |dffpipe_hd9:dffpipe12|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;              ;
-;                |alt_synch_pipe_jkd:ws_dgrp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp                       ;              ;
-;                   |dffpipe_id9:dffpipe17|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;              ;
-;                |altsyncram_bi31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram                         ;              ;
-;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
-;                |cmpr_156:wrfull_eq_comp1_msb|                               ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb                     ;              ;
-;                |cntr_t2e:cntr_b|                                            ; 3 (3)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
-;                |dffpipe_gd9:ws_brp|                                         ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp                               ;              ;
-;                |dffpipe_pe9:ws_bwp|                                         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp                               ;              ;
-;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
-;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
-;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
-;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
-;       |dcfifo1:WRF|                                                         ; 96 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF                                                                                                                               ;              ;
-;          |dcfifo_mixed_widths:dcfifo_mixed_widths_component|                ; 96 (0)            ; 124 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component                                                                             ;              ;
-;             |dcfifo_3fh1:auto_generated|                                    ; 96 (18)           ; 124 (42)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated                                                  ;              ;
-;                |a_gray2bin_lfb:rdptr_g_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin                  ;              ;
-;                |a_gray2bin_lfb:rs_dgwp_gray2bin|                            ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin                  ;              ;
-;                |a_graycounter_gic:wrptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p                      ;              ;
-;                |a_graycounter_j47:rdptr_g1p|                                ; 16 (16)           ; 13 (13)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p                      ;              ;
-;                |alt_synch_pipe_kkd:rs_dgwp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp                       ;              ;
-;                   |dffpipe_jd9:dffpipe12|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;              ;
-;                |alt_synch_pipe_lkd:ws_dgrp|                                 ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp                       ;              ;
-;                   |dffpipe_kd9:dffpipe15|                                   ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;              ;
-;                |altsyncram_ci31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram                         ;              ;
-;                |cmpr_156:rdempty_eq_comp1_msb|                              ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb                    ;              ;
-;                |cntr_t2e:cntr_b|                                            ; 4 (4)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b                                  ;              ;
-;                |dffpipe_gd9:rs_bwp|                                         ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp                               ;              ;
-;                |dffpipe_pe9:rs_brp|                                         ; 0 (0)             ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp                               ;              ;
-;                |mux_a18:rdemp_eq_comp_lsb_mux|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux                    ;              ;
-;                |mux_a18:rdemp_eq_comp_msb_mux|                              ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux                    ;              ;
-;                |mux_a18:wrfull_eq_comp_lsb_mux|                             ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux                   ;              ;
-;                |mux_a18:wrfull_eq_comp_msb_mux|                             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux                   ;              ;
-;    |Video:Fredi_Aschwanden|                                                 ; 3109 (10)         ; 2172 (4)     ; 92816       ; 6            ; 0       ; 3         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden                                                                                                                                                                                  ;              ;
-;       |DDR_CTR:DDR_CTR|                                                     ; 348 (314)         ; 158 (158)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR                                                                                                                                                                  ;              ;
-;          |lpm_bustri_BYT:$00002|                                            ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002                                                                                                                                            ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
-;          |lpm_bustri_BYT:$00004|                                            ; 31 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004                                                                                                                                            ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 31 (31)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                            ;              ;
-;       |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|                         ; 1260 (1013)       ; 529 (529)    ; 0           ; 6            ; 0       ; 3         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR                                                                                                                                      ;              ;
-;          |lpm_bustri_WORD:$00000|                                           ; 187 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000                                                                                                               ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 187 (187)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component                                                                               ;              ;
-;          |lpm_bustri_WORD:$00002|                                           ; 60 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002                                                                                                               ;              ;
-;             |lpm_bustri:lpm_bustri_component|                               ; 60 (60)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component                                                                               ;              ;
-;          |lpm_mult:op_12|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12                                                                                                                       ;              ;
-;             |mult_aat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated                                                                                               ;              ;
-;          |lpm_mult:op_14|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14                                                                                                                       ;              ;
-;             |mult_cat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated                                                                                               ;              ;
-;          |lpm_mult:op_6|                                                    ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6                                                                                                                        ;              ;
-;             |mult_aat:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 2            ; 0       ; 1         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated                                                                                                ;              ;
-;       |altddio_bidir0:inst1|                                                ; 0 (0)             ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1                                                                                                                                                             ;              ;
-;          |altddio_bidir:altddio_bidir_component|                            ; 0 (0)             ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component                                                                                                                       ;              ;
-;             |ddio_bidir_3jl:auto_generated|                                 ; 0 (0)             ; 96 (96)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated                                                                                         ;              ;
-;       |altddio_out0:inst2|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2                                                                                                                                                               ;              ;
-;          |altddio_out:altddio_out_component|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component                                                                                                                             ;              ;
-;             |ddio_out_are:auto_generated|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated                                                                                                 ;              ;
-;       |altddio_out2:inst5|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5                                                                                                                                                               ;              ;
-;          |altddio_out:altddio_out_component|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component                                                                                                                             ;              ;
-;             |ddio_out_o2f:auto_generated|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated                                                                                                 ;              ;
-;       |altdpram0:ST_CLUT_BLUE|                                              ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE                                                                                                                                                           ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                           ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                            ;              ;
-;       |altdpram0:ST_CLUT_GREEN|                                             ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN                                                                                                                                                          ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                          ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                           ;              ;
-;       |altdpram0:ST_CLUT_RED|                                               ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED                                                                                                                                                            ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                                                                                                            ;              ;
-;             |altsyncram_rb92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 48          ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated                                                                                             ;              ;
-;       |altdpram1:FALCON_CLUT_BLUE|                                          ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE                                                                                                                                                       ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                                                                                                       ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                        ;              ;
-;       |altdpram1:FALCON_CLUT_GREEN|                                         ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN                                                                                                                                                      ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                                                                                                      ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                       ;              ;
-;       |altdpram1:FALCON_CLUT_RED|                                           ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED                                                                                                                                                        ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                                                                                                        ;              ;
-;             |altsyncram_lf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 1536        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated                                                                                         ;              ;
-;       |altdpram2:ACP_CLUT_RAM54|                                            ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54                                                                                                                                                         ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                                                                                                         ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
-;       |altdpram2:ACP_CLUT_RAM55|                                            ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55                                                                                                                                                         ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                                                                                                         ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                          ;              ;
-;       |altdpram2:ACP_CLUT_RAM|                                              ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM                                                                                                                                                           ;              ;
-;          |altsyncram:altsyncram_component|                                  ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                                                                                                           ;              ;
-;             |altsyncram_pf92:auto_generated|                                ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated                                                                                            ;              ;
-;       |lpm_bustri_LONG:inst119|                                             ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_ff0:inst13|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst14|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst15|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst16|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst17|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst18|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff0:inst19|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst12|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst20|                                                      ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff1:inst3|                                                       ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff1:inst4|                                                       ; 0 (0)             ; 32 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 32 (32)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff1:inst9|                                                       ; 0 (0)             ; 24 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9                                                                                                                                                                    ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component                                                                                                                                            ;              ;
-;       |lpm_ff3:inst46|                                                      ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst47|                                                      ; 0 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst49|                                                      ; 0 (0)             ; 9 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff3:inst52|                                                      ; 0 (0)             ; 9 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff4:inst10|                                                      ; 0 (0)             ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff5:inst11|                                                      ; 0 (0)             ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff5:inst97|                                                      ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff6:inst71|                                                      ; 0 (0)             ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_ff6:inst94|                                                      ; 0 (0)             ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94                                                                                                                                                                   ;              ;
-;          |lpm_ff:lpm_ff_component|                                          ; 0 (0)             ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component                                                                                                                                           ;              ;
-;       |lpm_fifoDZ:inst63|                                                   ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63                                                                                                                                                                ;              ;
-;          |scfifo:scfifo_component|                                          ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component                                                                                                                                        ;              ;
-;             |scfifo_lk21:auto_generated|                                    ; 22 (0)            ; 21 (0)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated                                                                                                             ;              ;
-;                |a_dpfifo_oq21:dpfifo|                                       ; 22 (9)            ; 21 (8)       ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo                                                                                        ;              ;
-;                   |altsyncram_gj81:FIFOram|                                 ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram                                                                ;              ;
-;                   |cntr_omb:rd_ptr_msb|                                     ; 6 (6)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb                                                                    ;              ;
-;                   |cntr_pmb:wr_ptr|                                         ; 7 (7)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr                                                                        ;              ;
-;       |lpm_fifo_dc0:inst|                                                   ; 66 (0)            ; 98 (0)       ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst                                                                                                                                                                ;              ;
-;          |dcfifo:dcfifo_component|                                          ; 66 (0)            ; 98 (0)       ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component                                                                                                                                        ;              ;
-;             |dcfifo_8fi1:auto_generated|                                    ; 66 (12)           ; 98 (20)      ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                                                                             ;              ;
-;                |a_gray2bin_tgb:wrptr_g_gray2bin|                            ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                                                                             ;              ;
-;                |a_gray2bin_tgb:ws_dgrp_gray2bin|                            ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                                                                             ;              ;
-;                |a_graycounter_njc:wrptr_gp|                                 ; 17 (17)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp                                                                                  ;              ;
-;                |a_graycounter_s57:rdptr_g1p|                                ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p                                                                                 ;              ;
-;                |alt_synch_pipe_sld:ws_dgrp|                                 ; 0 (0)             ; 30 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp                                                                                  ;              ;
-;                   |dffpipe_re9:dffpipe22|                                   ; 0 (0)             ; 30 (30)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22                                                            ;              ;
-;                |altsyncram_tl31:fifo_ram|                                   ; 0 (0)             ; 0 (0)        ; 65536       ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram                                                                                    ;              ;
-;                |dffpipe_9d9:wraclr|                                         ; 0 (0)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr                                                                                          ;              ;
-;                |dffpipe_oe9:ws_brp|                                         ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp                                                                                          ;              ;
-;                |dffpipe_oe9:ws_bwp|                                         ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp                                                                                          ;              ;
-;       |lpm_latch0:inst27|                                                   ; 32 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27                                                                                                                                                                ;              ;
-;          |lpm_latch:lpm_latch_component|                                    ; 32 (32)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component                                                                                                                                  ;              ;
-;       |lpm_mux0:inst21|                                                     ; 48 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 48 (0)            ; 96 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_gpe:auto_generated|                                        ; 48 (48)           ; 96 (96)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux1:inst24|                                                     ; 80 (0)            ; 81 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 80 (0)            ; 81 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_npe:auto_generated|                                        ; 80 (80)           ; 81 (81)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux2:inst25|                                                     ; 80 (0)            ; 41 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 80 (0)            ; 41 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_mpe:auto_generated|                                        ; 80 (80)           ; 41 (41)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux3:inst102|                                                    ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102                                                                                                                                                                 ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
-;             |mux_96e:auto_generated|                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated                                                                                                                ;              ;
-;       |lpm_mux4:inst81|                                                     ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_f6e:auto_generated|                                        ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux5:inst22|                                                     ; 64 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22                                                                                                                                                                  ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 64 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component                                                                                                                                        ;              ;
-;             |mux_58e:auto_generated|                                        ; 64 (64)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated                                                                                                                 ;              ;
-;       |lpm_mux6:inst7|                                                      ; 90 (0)            ; 67 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7                                                                                                                                                                   ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 90 (0)            ; 67 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component                                                                                                                                         ;              ;
-;             |mux_kpe:auto_generated|                                        ; 90 (90)           ; 67 (67)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated                                                                                                                  ;              ;
-;       |lpm_muxDZ:inst62|                                                    ; 128 (0)           ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62                                                                                                                                                                 ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 128 (0)           ; 128 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component                                                                                                                                       ;              ;
-;             |mux_dcf:auto_generated|                                        ; 128 (128)         ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated                                                                                                                ;              ;
-;       |lpm_muxVDM:inst100|                                                  ; 736 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100                                                                                                                                                               ;              ;
-;          |lpm_mux:lpm_mux_component|                                        ; 736 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component                                                                                                                                     ;              ;
-;             |mux_bbe:auto_generated|                                        ; 736 (736)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated                                                                                                              ;              ;
-;       |lpm_shiftreg0:sr0|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr1|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr2|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr3|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr4|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr5|                                                   ; 15 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 15 (15)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr6|                                                   ; 16 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg0:sr7|                                                   ; 16 (0)            ; 16 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7                                                                                                                                                                ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component                                                                                                                            ;              ;
-;       |lpm_shiftreg4:inst26|                                                ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26                                                                                                                                                             ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
-;       |lpm_shiftreg6:inst92|                                                ; 0 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92                                                                                                                                                             ;              ;
-;          |lpm_shiftreg:lpm_shiftreg_component|                              ; 0 (0)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component                                                                                                                         ;              ;
-;       |mux41:inst40|                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40                                                                                                                                                                     ;              ;
-;       |mux41:inst41|                                                        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41                                                                                                                                                                     ;              ;
-;       |mux41:inst42|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42                                                                                                                                                                     ;              ;
-;       |mux41:inst43|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43                                                                                                                                                                     ;              ;
-;       |mux41:inst44|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44                                                                                                                                                                     ;              ;
-;       |mux41:inst45|                                                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45                                                                                                                                                                     ;              ;
-;    |altddio_out3:inst5|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst6|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst8|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8                                                                                                                                                                                      ;              ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component                                                                                                                                                    ;              ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ;              ;
-;    |altddio_out3:inst9|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9                                                                                                                                                                                      ; work         ;
-;       |altddio_out:altddio_out_component|                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component                                                                                                                                                    ; work         ;
-;          |ddio_out_31f:auto_generated|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated                                                                                                                        ; work         ;
-;    |altpll1:inst|                                                           ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst                                                                                                                                                                                            ;              ;
-;       |altpll:altpll_component|                                             ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst|altpll:altpll_component                                                                                                                                                                    ;              ;
-;          |altpll_pul2:auto_generated|                                       ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated                                                                                                                                         ;              ;
-;    |altpll2:inst12|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_isv2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated                                                                                                                                       ;              ;
-;    |altpll3:inst13|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_41p2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated                                                                                                                                       ;              ;
-;    |altpll4:inst22|                                                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22                                                                                                                                                                                          ;              ;
-;       |altpll:altpll_component|                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22|altpll:altpll_component                                                                                                                                                                  ;              ;
-;          |altpll_c6j2:auto_generated|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated                                                                                                                                       ;              ;
-;    |altpll_reconfig1:inst7|                                                 ; 309 (0)           ; 128 (0)      ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7                                                                                                                                                                                  ;              ;
-;       |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 309 (211)         ; 128 (80)     ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component                                                                                                              ;              ;
-;          |altsyncram:altsyncram4|                                           ; 0 (0)             ; 0 (0)        ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4                                                                                       ;              ;
-;             |altsyncram_46r:auto_generated|                                 ; 0 (0)             ; 0 (0)        ; 144         ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated                                                         ;              ;
-;          |lpm_compare:cmpr7|                                                ; 3 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7                                                                                            ;              ;
-;             |cmpr_tnd:auto_generated|                                       ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr12|                                               ; 10 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12                                                                                           ;              ;
-;             |cntr_30l:auto_generated|                                       ; 10 (10)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr13|                                               ; 7 (0)             ; 6 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13                                                                                           ;              ;
-;             |cntr_qij:auto_generated|                                       ; 7 (7)             ; 6 (6)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr14|                                               ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14                                                                                           ;              ;
-;             |cntr_pij:auto_generated|                                       ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr15|                                               ; 18 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15                                                                                           ;              ;
-;             |cntr_30l:auto_generated|                                       ; 18 (18)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated                                                                   ;              ;
-;          |lpm_counter:cntr1|                                                ; 41 (0)            ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1                                                                                            ;              ;
-;             |cntr_30l:auto_generated|                                       ; 41 (41)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr2|                                                ; 9 (0)             ; 8 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2                                                                                            ;              ;
-;             |cntr_9cj:auto_generated|                                       ; 9 (9)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated                                                                    ;              ;
-;          |lpm_counter:cntr3|                                                ; 5 (0)             ; 5 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3                                                                                            ;              ;
-;             |cntr_pij:auto_generated|                                       ; 5 (5)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated                                                                    ;              ;
-;    |interrupt_handler:nobody|                                               ; 789 (711)         ; 633 (633)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody                                                                                                                                                                                ;              ;
-;       |lpm_bustri_BYT:$00000|                                               ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00002|                                               ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 24 (24)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00004|                                               ; 16 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;       |lpm_bustri_BYT:$00006|                                               ; 22 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006                                                                                                                                                          ;              ;
-;          |lpm_bustri:lpm_bustri_component|                                  ; 22 (22)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component                                                                                                                          ;              ;
-;    |lpm_counter0:inst18|                                                    ; 18 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18                                                                                                                                                                                     ;              ;
-;       |lpm_counter:lpm_counter_component|                                   ; 18 (0)            ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component                                                                                                                                                   ;              ;
-;          |cntr_mph:auto_generated|                                          ; 18 (18)           ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated                                                                                                                           ;              ;
-;    |lpm_ff0:inst1|                                                          ; 0 (0)             ; 28 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_ff0:inst1                                                                                                                                                                                           ;              ;
-;       |lpm_ff:lpm_ff_component|                                             ; 0 (0)             ; 28 (28)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component                                                                                                                                                                   ;              ;
-+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
-; Name                                                                                                                                                                                       ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024         ; 8            ; 256          ; 32           ; 8192  ; None ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256          ; 32           ; 1024         ; 8            ; 8192  ; None ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                   ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
-; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM                                                                     ; AUTO ; True Dual Port   ; 16           ; 3            ; 16           ; 3            ; 48    ; None ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                               ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
-; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM                                                                 ; AUTO ; True Dual Port   ; 256          ; 6            ; 256          ; 6            ; 1536  ; None ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                  ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
-; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM                                                                    ; AUTO ; True Dual Port   ; 256          ; 8            ; 256          ; 8            ; 2048  ; None ;
-; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM                                        ; AUTO ; Simple Dual Port ; 128          ; 128          ; 128          ; 128          ; 16384 ; None ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM                                                            ; AUTO ; Simple Dual Port ; 512          ; 128          ; 512          ; 128          ; 65536 ; None ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM                                 ; AUTO ; Single Port      ; 144          ; 1            ; --           ; --           ; 144   ; None ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
-
-
-+-----------------------------------------------------+
-; Analysis & Synthesis DSP Block Usage Summary        ;
-+---------------------------------------+-------------+
-; Statistic                             ; Number Used ;
-+---------------------------------------+-------------+
-; Simple Multipliers (9-bit)            ; 0           ;
-; Simple Multipliers (18-bit)           ; 3           ;
-; Embedded Multiplier Blocks            ; --          ;
-; Embedded Multiplier 9-bit elements    ; 6           ;
-; Signed Embedded Multipliers           ; 0           ;
-; Unsigned Embedded Multipliers         ; 3           ;
-; Mixed Sign Embedded Multipliers       ; 0           ;
-; Variable Sign Embedded Multipliers    ; 0           ;
-; Dedicated Input Shift Register Chains ; 0           ;
-+---------------------------------------+-------------+
-Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
-
-
-Encoding Type:  One-Hot
-+----------------------------------------------------------------------------+
-; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR ;
-+---------+-------+-------+-------+-------+----------------------------------+
-; Name    ; FR_S3 ; FR_S2 ; FR_S1 ; FR_S0 ; FR_WAIT                          ;
-+---------+-------+-------+-------+-------+----------------------------------+
-; FR_WAIT ; 0     ; 0     ; 0     ; 0     ; 0                                ;
-; FR_S0   ; 0     ; 0     ; 0     ; 1     ; 1                                ;
-; FR_S1   ; 0     ; 0     ; 1     ; 0     ; 1                                ;
-; FR_S2   ; 0     ; 1     ; 0     ; 0     ; 1                                ;
-; FR_S3   ; 1     ; 0     ; 0     ; 0     ; 1                                ;
-+---------+-------+-------+-------+-------+----------------------------------+
-
-
-Encoding Type:  One-Hot
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM                                                                                                                                                                                                                                                     ;
-+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
-; Name    ; DS_R6 ; DS_R5 ; DS_R4 ; DS_R3 ; DS_R2 ; DS_CB8 ; DS_CB6 ; DS_T10F ; DS_T9F ; DS_T8F ; DS_T7F ; DS_T6F ; DS_T5F ; DS_T4F ; DS_T9W ; DS_T8W ; DS_T7W ; DS_T6W ; DS_T5W ; DS_T4W ; DS_T5R ; DS_T4R ; DS_C7 ; DS_C6 ; DS_C5 ; DS_C4 ; DS_C3 ; DS_C2 ; DS_N8 ; DS_N7 ; DS_N6 ; DS_N5 ; DS_T3 ; DS_T2B ; DS_T2A ; DS_T1 ;
-+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
-; DS_T1   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0     ;
-; DS_T2A  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 1      ; 1     ;
-; DS_T2B  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1      ; 0      ; 1     ;
-; DS_T3   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0      ; 0      ; 1     ;
-; DS_N5   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0      ; 0      ; 1     ;
-; DS_N6   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_N7   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_N8   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C2   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C3   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C4   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C5   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C6   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_C7   ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T4R  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T5R  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T4W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T5W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T6W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T7W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T8W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T9W  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T4F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T5F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T6F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T7F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T8F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T9F  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 1      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_T10F ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_CB6  ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 1      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_CB8  ; 0     ; 0     ; 0     ; 0     ; 0     ; 1      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_R2   ; 0     ; 0     ; 0     ; 0     ; 1     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_R3   ; 0     ; 0     ; 0     ; 1     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_R4   ; 0     ; 0     ; 1     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_R5   ; 0     ; 1     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-; DS_R6   ; 1     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 0       ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0      ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0     ; 0      ; 0      ; 1     ;
-+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+
-
-
-Encoding Type:  One-Hot
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE                                                         ;
-+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
-; Name               ; FCF_STATE.FCF_T7 ; FCF_STATE.FCF_T6 ; FCF_STATE.FCF_T3 ; FCF_STATE.FCF_T2 ; FCF_STATE.FCF_T1 ; FCF_STATE.FCF_T0 ; FCF_STATE.FCF_IDLE ;
-+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
-; FCF_STATE.FCF_IDLE ; 0                ; 0                ; 0                ; 0                ; 0                ; 0                ; 0                  ;
-; FCF_STATE.FCF_T0   ; 0                ; 0                ; 0                ; 0                ; 0                ; 1                ; 1                  ;
-; FCF_STATE.FCF_T1   ; 0                ; 0                ; 0                ; 0                ; 1                ; 0                ; 1                  ;
-; FCF_STATE.FCF_T2   ; 0                ; 0                ; 0                ; 1                ; 0                ; 0                ; 1                  ;
-; FCF_STATE.FCF_T3   ; 0                ; 0                ; 1                ; 0                ; 0                ; 0                ; 1                  ;
-; FCF_STATE.FCF_T6   ; 0                ; 1                ; 0                ; 0                ; 0                ; 0                ; 1                  ;
-; FCF_STATE.FCF_T7   ; 1                ; 0                ; 0                ; 0                ; 0                ; 0                ; 1                  ;
-+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+
-
-
-Encoding Type:  One-Hot
-+---------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE ;
-+----------------+--------------+--------------+--------------+-------------------------------------+
-; Name           ; CMD_STATE.T7 ; CMD_STATE.T6 ; CMD_STATE.T1 ; CMD_STATE.IDLE                      ;
-+----------------+--------------+--------------+--------------+-------------------------------------+
-; CMD_STATE.IDLE ; 0            ; 0            ; 0            ; 0                                   ;
-; CMD_STATE.T1   ; 0            ; 0            ; 1            ; 1                                   ;
-; CMD_STATE.T6   ; 0            ; 1            ; 0            ; 1                                   ;
-; CMD_STATE.T7   ; 1            ; 0            ; 0            ; 1                                   ;
-+----------------+--------------+--------------+--------------+-------------------------------------+
-
-
-Encoding Type:  One-Hot
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE ;
-+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
-; Name                 ; INT_STATE.VECTOR_OUT ; INT_STATE.REQUEST ; INT_STATE.SCAN                                                                            ;
-+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
-; INT_STATE.SCAN       ; 0                    ; 0                 ; 0                                                                                         ;
-; INT_STATE.REQUEST    ; 0                    ; 1                 ; 1                                                                                         ;
-; INT_STATE.VECTOR_OUT ; 1                    ; 0                 ; 1                                                                                         ;
-+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+
-
-
-Encoding Type:  One-Hot
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE ;
-+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
-; Name                 ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.CHECK_BREAK ; TR_STATE.IDLE                ;
-+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
-; TR_STATE.IDLE        ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 0                            ;
-; TR_STATE.CHECK_BREAK ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                    ; 1                            ;
-; TR_STATE.LOAD_SHFT   ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 0                    ; 1                            ;
-; TR_STATE.START       ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 0                    ; 1                            ;
-; TR_STATE.SHIFTOUT    ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 0                    ; 1                            ;
-; TR_STATE.PARITY      ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
-; TR_STATE.STOP1       ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
-; TR_STATE.STOP2       ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                    ; 1                            ;
-+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+
-
-
-Encoding Type:  One-Hot
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
-; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE                                  ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
-; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                                               ;
-; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                                               ;
-; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                                               ;
-; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                                               ;
-; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                                               ;
-; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                                               ;
-; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                                               ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+
-
-
-Encoding Type:  One-Hot
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
-; Name               ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE                ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
-; TR_STATE.IDLE      ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                            ;
-; TR_STATE.LOAD_SHFT ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 1                            ;
-; TR_STATE.START     ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 1                            ;
-; TR_STATE.SHIFTOUT  ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 1                            ;
-; TR_STATE.PARITY    ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 1                            ;
-; TR_STATE.STOP1     ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 1                            ;
-; TR_STATE.STOP2     ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                            ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+
-
-
-Encoding Type:  One-Hot
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
-; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE        ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
-; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                     ;
-; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                     ;
-; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                     ;
-; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                     ;
-; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                     ;
-; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                     ;
-; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                     ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+
-
-
-Encoding Type:  One-Hot
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
-; Name               ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE                    ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
-; TR_STATE.IDLE      ; 0              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 0                                ;
-; TR_STATE.LOAD_SHFT ; 0              ; 0              ; 0               ; 0                 ; 0              ; 1                  ; 1                                ;
-; TR_STATE.START     ; 0              ; 0              ; 0               ; 0                 ; 1              ; 0                  ; 1                                ;
-; TR_STATE.SHIFTOUT  ; 0              ; 0              ; 0               ; 1                 ; 0              ; 0                  ; 1                                ;
-; TR_STATE.PARITY    ; 0              ; 0              ; 1               ; 0                 ; 0              ; 0                  ; 1                                ;
-; TR_STATE.STOP1     ; 0              ; 1              ; 0               ; 0                 ; 0              ; 0                  ; 1                                ;
-; TR_STATE.STOP2     ; 1              ; 0              ; 0               ; 0                 ; 0              ; 0                  ; 1                                ;
-+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
-; Name                 ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE            ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
-; RCV_STATE.IDLE       ; 0              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 0                         ;
-; RCV_STATE.WAIT_START ; 0              ; 0               ; 0               ; 0                ; 0                ; 1                    ; 1                         ;
-; RCV_STATE.SAMPLE     ; 0              ; 0               ; 0               ; 0                ; 1                ; 0                    ; 1                         ;
-; RCV_STATE.PARITY     ; 0              ; 0               ; 0               ; 1                ; 0                ; 0                    ; 1                         ;
-; RCV_STATE.STOP1      ; 0              ; 0               ; 1               ; 0                ; 0                ; 0                    ; 1                         ;
-; RCV_STATE.STOP2      ; 0              ; 1               ; 0               ; 0                ; 0                ; 0                    ; 1                         ;
-; RCV_STATE.SYNC       ; 1              ; 0               ; 0               ; 0                ; 0                ; 0                    ; 1                         ;
-+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+
-
-
-Encoding Type:  One-Hot
-+--------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE ;
-+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
-; Name                 ; DMA_STATE.DMA_STEP_4 ; DMA_STATE.DMA_STEP_3 ; DMA_STATE.DMA_STEP_2 ; DMA_STATE.DMA_STEP_1 ; DMA_STATE.IDLE                ;
-+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
-; DMA_STATE.IDLE       ; 0                    ; 0                    ; 0                    ; 0                    ; 0                             ;
-; DMA_STATE.DMA_STEP_1 ; 0                    ; 0                    ; 0                    ; 1                    ; 1                             ;
-; DMA_STATE.DMA_STEP_2 ; 0                    ; 0                    ; 1                    ; 0                    ; 1                             ;
-; DMA_STATE.DMA_STEP_3 ; 0                    ; 1                    ; 0                    ; 0                    ; 1                             ;
-; DMA_STATE.DMA_STEP_4 ; 1                    ; 0                    ; 0                    ; 0                    ; 1                             ;
-+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+
-
-
-Encoding Type:  One-Hot
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE                    ;
-+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
-; Name                    ; CTRL_STATE.DMA_INIT_RCV ; CTRL_STATE.DMA_TARG_RCV ; CTRL_STATE.DMA_SEND ; CTRL_STATE.WAIT_2200ns ; CTRL_STATE.WAIT_800ns ; CTRL_STATE.IDLE ;
-+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
-; CTRL_STATE.IDLE         ; 0                       ; 0                       ; 0                   ; 0                      ; 0                     ; 0               ;
-; CTRL_STATE.WAIT_800ns   ; 0                       ; 0                       ; 0                   ; 0                      ; 1                     ; 1               ;
-; CTRL_STATE.WAIT_2200ns  ; 0                       ; 0                       ; 0                   ; 1                      ; 0                     ; 1               ;
-; CTRL_STATE.DMA_SEND     ; 0                       ; 0                       ; 1                   ; 0                      ; 0                     ; 1               ;
-; CTRL_STATE.DMA_TARG_RCV ; 0                       ; 1                       ; 0                   ; 0                      ; 0                     ; 1               ;
-; CTRL_STATE.DMA_INIT_RCV ; 1                       ; 0                       ; 0                   ; 0                      ; 0                     ; 1               ;
-+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+
-
-
-Encoding Type:  One-Hot
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP ;
-+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
-; Name            ; PRECOMP.LATE ; PRECOMP.EARLY ; PRECOMP.NOMINAL                                                                                          ;
-+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
-; PRECOMP.NOMINAL ; 0            ; 0             ; 0                                                                                                        ;
-; PRECOMP.EARLY   ; 0            ; 1             ; 1                                                                                                        ;
-; PRECOMP.LATE    ; 1            ; 0             ; 1                                                                                                        ;
-+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+
-
-
-Encoding Type:  One-Hot
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE ;
-+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
-; Name           ; MFM_STATE.C_10 ; MFM_STATE.B_01 ; MFM_STATE.A_00                                                                                           ;
-+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
-; MFM_STATE.A_00 ; 0              ; 0              ; 0                                                                                                        ;
-; MFM_STATE.B_01 ; 0              ; 1              ; 1                                                                                                        ;
-; MFM_STATE.C_10 ; 1              ; 0              ; 1                                                                                                        ;
-+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+
-
-
-Encoding Type:  One-Hot
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
-; Name                       ; CMD_STATE.T3_VERIFY_CRC ; CMD_STATE.T3_LOAD_SR ; CMD_STATE.T3_CHECK_RD ; CMD_STATE.T3_SET_DRQ_2 ; CMD_STATE.T3_LOAD_DATA_2 ; CMD_STATE.T3_SHIFT_ADR ; CMD_STATE.T3_VERIFY_AM ; CMD_STATE.T3_RD_ADR ; CMD_STATE.T3_SET_DRQ_1 ; CMD_STATE.T3_LOAD_DATA_1 ; CMD_STATE.T3_CHECK_DR ; CMD_STATE.T3_CHECK_BYTE ; CMD_STATE.T3_DETECT_AM ; CMD_STATE.T3_CHECK_INDEX_3 ; CMD_STATE.T3_SHIFT ; CMD_STATE.T3_RD_TRACK ; CMD_STATE.T3_DATALOST ; CMD_STATE.T3_CHECK_INDEX_2 ; CMD_STATE.T3_WR_DATA ; CMD_STATE.T3_LOAD_SHFT ; CMD_STATE.T3_CHECK_INDEX_1 ; CMD_STATE.T3_VERIFY_DRQ ; CMD_STATE.T3_DELAY_B3 ; CMD_STATE.T3_WR ; CMD_STATE.T2_WR_FF ; CMD_STATE.T2_WR_CRC ; CMD_STATE.T2_WRSTAT ; CMD_STATE.T2_DATALOST ; CMD_STATE.T2_VERIFY_DRQ_3 ; CMD_STATE.T2_WR_BYTE ; CMD_STATE.T2_LOAD_SHFT ; CMD_STATE.T2_WR_AM ; CMD_STATE.T2_WR_LEADIN ; CMD_STATE.T2_DELAY_B11 ; CMD_STATE.T2_CHECK_MODE ; CMD_STATE.T2_DELAY_B1 ; CMD_STATE.T2_VERIFY_DRQ_2 ; CMD_STATE.T2_DELAY_B8 ; CMD_STATE.T2_SET_DRQ ; CMD_STATE.T2_DELAY_B2 ; CMD_STATE.T2_MULTISECT ; CMD_STATE.T2_VERIFY_CRC_2 ; CMD_STATE.T2_RDSTAT ; CMD_STATE.T2_VERIFY_DRQ_1 ; CMD_STATE.T2_NEXTBYTE ; CMD_STATE.T2_LOAD_DATA ; CMD_STATE.T2_FIRSTBYTE ; CMD_STATE.T2_VERIFY_AM ; CMD_STATE.T2_VERIFY_CRC_1 ; CMD_STATE.T2_SCAN_LEN ; CMD_STATE.T2_SCAN_SECT ; CMD_STATE.T2_SCAN_TRACK ; CMD_STATE.T2_INIT ; CMD_STATE.T2_RD_WR_SECT ; CMD_STATE.T1_VERIFY_CRC ; CMD_STATE.T1_VERIFY_DELAY ; CMD_STATE.T1_SCAN_CRC ; CMD_STATE.T1_SCAN_TRACK ; CMD_STATE.T1_SPINDOWN ; CMD_STATE.T1_STEP_DELAY ; CMD_STATE.T1_TRAP ; CMD_STATE.T1_STEP ; CMD_STATE.T1_HEAD_CTRL ; CMD_STATE.T1_CHECK_DIR ; CMD_STATE.T1_COMP_TR_DSR ; CMD_STATE.T1_LOAD_SHFT ; CMD_STATE.T1_STEPPING ; CMD_STATE.T1_SEEK_RESTORE ; CMD_STATE.DECODE ; CMD_STATE.DELAY_15MS ; CMD_STATE.SPINUP ; CMD_STATE.INIT ; CMD_STATE.IDLE ;
-+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
-; CMD_STATE.IDLE             ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 0              ;
-; CMD_STATE.INIT             ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 1              ; 1              ;
-; CMD_STATE.SPINUP           ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 1                ; 0              ; 1              ;
-; CMD_STATE.DELAY_15MS       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 1                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.DECODE           ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 1                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_SEEK_RESTORE  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 1                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_STEPPING      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 1                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 1                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_COMP_TR_DSR   ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 1                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_CHECK_DIR     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 1                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_HEAD_CTRL     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 1                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_STEP          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 1                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_TRAP          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 1                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_STEP_DELAY    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 1                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_SPINDOWN      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 1                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_SCAN_TRACK    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 1                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_SCAN_CRC      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 1                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_VERIFY_DELAY  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 1                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T1_VERIFY_CRC    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 1                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_RD_WR_SECT    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 1                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_INIT          ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 1                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_SCAN_TRACK    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 1                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_SCAN_SECT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 1                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_SCAN_LEN      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 1                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_CRC_1  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 1                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 1                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_FIRSTBYTE     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 1                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_LOAD_DATA     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 1                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_NEXTBYTE      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 1                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_DRQ_1  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 1                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_RDSTAT        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 1                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_CRC_2  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 1                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_MULTISECT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 1                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_DELAY_B2      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 1                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_SET_DRQ       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 1                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_DELAY_B8      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 1                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_DRQ_2  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 1                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_DELAY_B1      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 1                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_CHECK_MODE    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 1                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_DELAY_B11     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 1                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WR_LEADIN     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 1                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WR_AM         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 1                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 1                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WR_BYTE       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 1                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_VERIFY_DRQ_3  ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 1                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_DATALOST      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 1                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WRSTAT        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 1                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WR_CRC        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 1                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T2_WR_FF         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 1                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_WR            ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 1               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_DELAY_B3      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 1                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_VERIFY_DRQ    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 1                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_INDEX_1 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 1                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_LOAD_SHFT     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 1                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_WR_DATA       ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 1                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_INDEX_2 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 1                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_DATALOST      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 1                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_RD_TRACK      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 1                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_SHIFT         ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 1                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_INDEX_3 ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 1                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_DETECT_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 1                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_BYTE    ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 1                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_DR      ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 1                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_LOAD_DATA_1   ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 1                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_SET_DRQ_1     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 1                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_RD_ADR        ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 1                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_VERIFY_AM     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 1                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_SHIFT_ADR     ; 0                       ; 0                    ; 0                     ; 0                      ; 0                        ; 1                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_LOAD_DATA_2   ; 0                       ; 0                    ; 0                     ; 0                      ; 1                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_SET_DRQ_2     ; 0                       ; 0                    ; 0                     ; 1                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_CHECK_RD      ; 0                       ; 0                    ; 1                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_LOAD_SR       ; 0                       ; 1                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-; CMD_STATE.T3_VERIFY_CRC    ; 1                       ; 0                    ; 0                     ; 0                      ; 0                        ; 0                      ; 0                      ; 0                   ; 0                      ; 0                        ; 0                     ; 0                       ; 0                      ; 0                          ; 0                  ; 0                     ; 0                     ; 0                          ; 0                    ; 0                      ; 0                          ; 0                       ; 0                     ; 0               ; 0                  ; 0                   ; 0                   ; 0                     ; 0                         ; 0                    ; 0                      ; 0                  ; 0                      ; 0                      ; 0                       ; 0                     ; 0                         ; 0                     ; 0                    ; 0                     ; 0                      ; 0                         ; 0                   ; 0                         ; 0                     ; 0                      ; 0                      ; 0                      ; 0                         ; 0                     ; 0                      ; 0                       ; 0                 ; 0                       ; 0                       ; 0                         ; 0                     ; 0                       ; 0                     ; 0                       ; 0                 ; 0                 ; 0                      ; 0                      ; 0                        ; 0                      ; 0                     ; 0                         ; 0                ; 0                    ; 0                ; 0              ; 1              ;
-+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Protected by Synthesis                                                                                                                                                                                                                                         ;
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
-; Register Name                                                                                                                                            ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                    ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[1]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[0]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state                                    ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_data_state                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_nominal_state                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_nominal_state                                       ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_state                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state                                                   ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[2]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]                                                 ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[3]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_data_state                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_data_state                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_data_state                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_data_state                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_data_state                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_data_state                                       ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate3_state                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate_state                                            ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[8]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[7]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[6]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[5]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]                                                 ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[4]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]                                                 ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]                         ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_state                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_nominal_state                                       ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state                                       ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[17]                                              ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]                         ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[2]                                    ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[1]                                    ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[0]                                    ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[3]                                     ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[2]                                     ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[1]                                     ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_nominal_state                                      ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_state                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_state                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[0]                                     ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_nominal_state                                      ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state                                        ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_init_state                                           ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state                                        ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]                         ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]                                               ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]                         ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_ena_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_ena_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_ena_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_ena_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_ena_state                                                  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[0]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[0] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[1]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[1] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[2]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[2] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[3]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[3] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[4]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[4] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[5]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[5]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[5] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[6]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[6]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[6] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[6] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[7]  ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7] ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate2_state                                           ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]                         ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]                                              ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]                                               ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]                         ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]                          ; no                                                               ; yes                                        ;
-; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]                          ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8]                                               ; no                                                               ; yes                                        ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_seq_ena_state                                             ; no                                                               ; yes                                        ;
-+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; User-Specified and Inferred Latches                                                                                                                                                    ;
-+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
-; Latch Name                                                                         ; Latch Enable Signal                                                      ; Free of Timing Hazards ;
-+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes                    ;
-; Number of user-specified and inferred latches = 32                                 ;                                                                          ;                        ;
-+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+
-Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                           ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Register name                                                                                                                                                                         ; Reason for Removal                                                                                                                                                                   ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; interrupt_handler:nobody|INT_LATCH[31]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[31]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[30]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[30]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[29]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[29]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[28]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[28]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[27]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[27]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[26]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[26]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[25]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[25]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[24]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[24]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[23]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[23]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[22]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[22]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[21]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[21]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[20]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[20]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[19]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[19]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[18]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[18]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[17]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[17]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[16]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[16]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[15]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[15]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[14]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[14]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[13]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[13]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[12]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[12]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[11]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[11]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[10]                                                                                                                                                ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[10]                                                                                                                                                ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|INT_LATCH[7]                                                                                                                                                 ; Stuck at GND due to stuck port clock                                                                                                                                                 ;
-; interrupt_handler:nobody|INT_CLEAR[7]                                                                                                                                                 ; Lost fanout                                                                                                                                                                          ;
-; interrupt_handler:nobody|WERTE[7][13]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
-; interrupt_handler:nobody|WERTE[6][10]                                                                                                                                                 ; Stuck at GND due to stuck port clear                                                                                                                                                 ;
-; interrupt_handler:nobody|WERTE[2][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
-; interrupt_handler:nobody|WERTE[1][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
-; interrupt_handler:nobody|WERTE[0][11]                                                                                                                                                 ; Stuck at VCC due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17]                                                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20]                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20]                                                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_REQ                                                                                                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In                                                         ; Lost fanout                                                                                                                                                                          ;
-; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0..6]                         ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP                                                                                 ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS                                   ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS                               ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP                                                                      ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA                                                                       ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR                                                                  ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]                                                               ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0..5]                                                            ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK                                                         ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0..7]                                         ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[6]                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0,2..5,7]                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[0..2]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[0..7]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SPER                                                                 ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE                                                                 ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK                                                  ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0..2]                                                     ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6..7]                                                            ; Lost fanout                                                                                                                                                                          ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]                                                             ; Lost fanout                                                                                                                                                                          ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]                                                             ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]  ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10] ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10] ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]  ; Lost fanout                                                                                                                                                                          ;
-; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[2]                                                                                     ; Merged with Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                                        ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_OUT                                                             ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|OE                               ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\OVERRUN:FIRST_READ ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                                        ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ                           ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR                                                    ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ                       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[6]                                                               ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[7]                                                  ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[0..3]                                                            ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]                                                  ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_DRQ:LOCK                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_ACTIVE_I                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4,7]                                                             ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[1]                                                               ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe18                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe2                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe20                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe34                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe36                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe4                                                                                          ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|INT                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DRQ                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[0..7]                                                            ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDRWR_D_SEL                                                                                                                                 ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                                                                                                                         ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[0..2]                                                                                                                                  ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]                                                                                                                        ;
-; Video:Fredi_Aschwanden|inst88                                                                                                                                                         ; Merged with Video:Fredi_Aschwanden|inst90                                                                                                                                            ;
-; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[0..2]                                                                                                              ; Merged with Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]                                                                                                    ;
-; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_AC                                                                                                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[2]                                                                                                         ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE                                                           ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1                                                     ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2                                                     ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3                                                     ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4                                                     ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE                                                          ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND                                                      ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV                                                  ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV                                                  ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns                                                   ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00                                                ; Lost fanout                                                                                                                                                                          ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns                                                    ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN                                                                  ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DELAY_800ns                                                              ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[0..3]                                                     ; Stuck at GND due to stuck port data_in                                                                                                                                               ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[0]                          ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                   ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]                                         ; Lost fanout                                                                                                                                                                          ;
-; Total Number of Removed Registers = 223                                                                                                                                               ;                                                                                                                                                                                      ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                                                                                         ;
-+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Register name                                                                                                                                 ; Reason for Removal        ; Registers Removed due to This Register                                                                                                                  ;
-+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns            ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN,                                   ;
-;                                                                                                                                               ; due to stuck port data_in ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[2]                          ;
-; interrupt_handler:nobody|INT_LATCH[30]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[30]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[29]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[29]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[28]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[28]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[27]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[27]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[26]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[26]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[25]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[25]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[24]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[24]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[23]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[23]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[22]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[22]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[21]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[21]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[20]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[20]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[19]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[19]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[18]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[18]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[17]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[17]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[16]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[16]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[15]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[15]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[14]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[14]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[13]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[13]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[12]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[12]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[11]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[11]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[10]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[10]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[7]                                                                                                         ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[7]                                                                                                                   ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[17]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[16]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[9]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[8]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[1]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[20]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[20]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[19]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[18]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[17]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[16]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[12]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[11]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[10]                                                                        ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[9]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; interrupt_handler:nobody|INT_LATCH[31]                                                                                                        ; Stuck at GND              ; interrupt_handler:nobody|INT_CLEAR[31]                                                                                                                  ;
-;                                                                                                                                               ; due to stuck port clock   ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[4]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[3]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[2]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[1]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[8]                                                                         ; Stuck at GND              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In     ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]                                 ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2]                       ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]                                 ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0]                       ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE                                   ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn  ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[2]                                 ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In     ; Stuck at GND              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS     ;
-;                                                                                                                                               ; due to stuck port data_in ;                                                                                                                                                         ;
-+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics                          ;
-+----------------------------------------------+-------+
-; Statistic                                    ; Value ;
-+----------------------------------------------+-------+
-; Total registers                              ; 4612  ;
-; Number of registers using Synchronous Clear  ; 156   ;
-; Number of registers using Synchronous Load   ; 204   ;
-; Number of registers using Asynchronous Clear ; 1431  ;
-; Number of registers using Asynchronous Load  ; 0     ;
-; Number of registers using Clock Enable       ; 2735  ;
-; Number of registers using Preset             ; 0     ;
-+----------------------------------------------+-------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Inverted Register Statistics                                                                                                                                                                               ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
-; Inverted Register                                                                                                                                                                                ; Fan out ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                ; 4       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[2]                                                                ; 5       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[1]                                                                ; 5       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0]                                                                ; 4       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT[7]                                                               ; 7       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE                                                                ; 7       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE                                                            ; 7       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IRQ_ACIAn                                                                                                                          ; 2       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb                     ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb                     ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0    ; 8       ;
-; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state                                                                                           ; 2       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_lsb_aeb                     ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_msb_aeb                     ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6       ; 4       ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                                                            ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|counter8a0    ; 8       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|parity9       ; 4       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; 1       ;
-; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; 1       ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                                               ; 7       ;
-; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                                                  ; 3       ;
-; Total number of inverted registers = 22                                                                                                                                                          ;         ;
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                      ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                            ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[7]                                           ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]                                  ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[0]    ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]           ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]                              ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                             ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]                                     ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]                          ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0]                         ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]                                 ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]                                          ;
-; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]                                            ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[4]                                     ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[4]                                     ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[7]                                     ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[6]                                     ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]                  ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]                                   ;
-; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                            ;
-; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]                                            ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]                                   ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2]                                      ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT[0]             ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]                               ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[0]                                  ;
-; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:CLK_DIVCNT[0] ;
-; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_START_BIT:TMP[0]    ;
-; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:LOW_FLT[0]   ;
-; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[3]  ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[0]                                        ;
-; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1]                                    ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]                                    ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]                                ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]                                  ;
-; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]                                      ;
-; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]                                                                                                   ;
-; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]              ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[7]                                                 ;
-; 5:1                ; 21 bits   ; 63 LEs        ; 42 LEs               ; 21 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                              ;
-; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[19]                             ;
-; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]          ;
-; 5:1                ; 5 bits    ; 15 LEs        ; 10 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]                                ;
-; 4:1                ; 31 bits   ; 62 LEs        ; 62 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                         ;
-; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:TIMER[1]     ;
-; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]                                             ;
-; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[5]                                     ;
-; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[2]                                     ;
-; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[1]                                     ;
-; 10:1               ; 4 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[5]                                     ;
-; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3]                                                  ;
-; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]                                                  ;
-; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]                          ;
-; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]                            ;
-; 7:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]                      ;
-; 7:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]                        ;
-; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]                                            ;
-; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0                                                                                                  ;
-; 7:1                ; 13 bits   ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[10]                                           ;
-; 6:1                ; 20 bits   ; 80 LEs        ; 20 LEs               ; 60 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]                                          ;
-; 11:1               ; 2 bits    ; 14 LEs        ; 10 LEs               ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]                      ;
-; 8:1                ; 5 bits    ; 25 LEs        ; 20 LEs               ; 5 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]                  ;
-; 9:1                ; 2 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]                                            ;
-; 14:1               ; 5 bits    ; 45 LEs        ; 10 LEs               ; 35 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]                                                  ;
-; 11:1               ; 8 bits    ; 56 LEs        ; 16 LEs               ; 40 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B[1]                                                  ;
-; 11:1               ; 8 bits    ; 56 LEs        ; 16 LEs               ; 40 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A[1]                                                  ;
-; 17:1               ; 4 bits    ; 44 LEs        ; 40 LEs               ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[2]                                      ;
-; 17:1               ; 4 bits    ; 44 LEs        ; 0 LEs                ; 44 LEs                 ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7]                                      ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]                                                                                                    ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]                                                                                                    ;
-; 3:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]                                                                                                ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                               ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0]                                           ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                   ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_NEXT_STATE         ;
-; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE                                                   ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEXCNT                                                    ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]                                                                                                     ;
-; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|DATA_OUT[4]                                                                  ;
-; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[1]                                                                      ;
-; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT                                                         ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE                                   ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE                               ;
-; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|NEXT_CMD_STATE                                              ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_A[1]                                              ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_B[2]                                              ;
-; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_C[1]                                              ;
-; 16:1               ; 8 bits    ; 80 LEs        ; 24 LEs               ; 56 LEs                 ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|DATA_OUT[2]                                                                            ;
-; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ADDER_IN[1]                                         ;
-; 64:1               ; 3 bits    ; 126 LEs       ; 126 LEs              ; 0 LEs                  ; No         ; |firebee1|interrupt_handler:nobody|_                                                                                                                                                  ;
-; 17:1               ; 3 bits    ; 33 LEs        ; 18 LEs               ; 15 LEs                 ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[7]                                                                            ;
-; 18:1               ; 4 bits    ; 48 LEs        ; 44 LEs               ; 4 LEs                  ; No         ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[2]                                                                            ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-; Assignment                            ; Value                                                                               ; From            ; To                            ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                             ;
-; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                             ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                             ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                             ;
-; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                             ;
-; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                                                                                   ; -               ; -                             ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb         ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb         ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb         ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb         ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                   ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg    ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg    ;
-; SUPPRESS_DA_RULE_INTERNAL             ; S102                                                                                ; -               ; wrptr_g                       ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                   ;
-; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe17|dffe18a     ;
-; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*          ; -               ; -                             ;
-; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a     ;
-; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*  ; -               ; -                             ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment     ; Value ; From ; To                                                                                                                                                                        ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                                                                ;
-; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                                                                   ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                                                                                             ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                                                                              ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; sub_parity9a0                                                                                                                                                  ;
-; POWER_UP_LEVEL            ; LOW   ; -    ; parity8                                                                                                                                                        ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                                                                                       ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                        ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                              ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                              ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-; Assignment                            ; Value                                                                               ; From            ; To                            ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                             ;
-; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                             ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                             ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                             ;
-; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                             ;
-; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3                                                                                   ; -               ; -                             ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb         ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb         ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb         ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb         ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                   ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg    ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg    ;
-; SUPPRESS_DA_RULE_INTERNAL             ; S102                                                                                ; -               ; wrptr_g                       ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                   ;
-; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe15|dffe16a     ;
-; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*          ; -               ; -                             ;
-; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a     ;
-; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*  ; -               ; -                             ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment     ; Value ; From ; To                                                                                                                                                                        ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; POWER_UP_LEVEL ; HIGH  ; -    ; sub_parity6a0                                                                                                                                                             ;
-; POWER_UP_LEVEL ; LOW   ; -    ; parity5                                                                                                                                                                   ;
-+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                                                                                             ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                                                                              ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; counter8a0                                                                                                                                                     ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; parity9                                                                                                                                                        ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                                                                                       ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                        ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                              ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                              ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                               ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                                                                                         ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                                                          ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                                                          ;
-+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                                                                            ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                                             ;
-+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
-+---------------------------------+-------+------+----------------------------------------+
-; Assignment                      ; Value ; From ; To                                     ;
-+---------------------------------+-------+------+----------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                      ;
-+---------------------------------+-------+------+----------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated                                                         ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
-; Assignment                            ; Value                                                                               ; From            ; To                         ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF                                                                                 ; -               ; -                          ;
-; REMOVE_DUPLICATE_REGISTERS            ; OFF                                                                                 ; -               ; -                          ;
-; SYNCHRONIZER_IDENTIFICATION           ; OFF                                                                                 ; -               ; -                          ;
-; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 4                                                                                   ; -               ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d101                                                                                ; -               ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL             ; d102                                                                                ; -               ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL             ; R105                                                                                ; -               ; -                          ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_lsb_aeb      ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_lsb_aeb      ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rdemp_eq_comp_msb_aeb      ;
-; POWER_UP_LEVEL                        ; HIGH                                                                                ; -               ; rdemp_eq_comp_msb_aeb      ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; rs_dgwp_reg                ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_lsb_mux_reg ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; wrfull_eq_comp_msb_mux_reg ;
-; SYNCHRONIZER_IDENTIFICATION           ; FORCED_IF_ASYNCHRONOUS                                                              ; -               ; ws_dgrp_reg                ;
-; CUT                                   ; ON                                                                                  ; rdptr_g         ; ws_dgrp|dffpipe22|dffe23a  ;
-; SDC_STATEMENT                         ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe22|dffe23a*          ; -               ; -                          ;
-; CUT                                   ; ON                                                                                  ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a  ;
-; SDC_STATEMENT                         ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe15|dffe16a*  ; -               ; -                          ;
-+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ;
-+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
-; Assignment     ; Value ; From ; To                                                                                                             ;
-+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
-; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                     ;
-; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                        ;
-+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
-+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                                  ;
-+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                   ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; counter8a0                                                                                          ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; parity9                                                                                             ;
-+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                                 ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; S102  ; -    ; -                                                                                                  ;
-; POWER_UP_LEVEL            ; HIGH  ; -    ; sub_parity12a0                                                                                     ;
-; POWER_UP_LEVEL            ; LOW   ; -    ; parity11                                                                                           ;
-+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                            ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                             ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                              ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                               ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                               ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                 ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                  ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                   ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                   ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                   ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                    ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-; Assignment                  ; Value                  ; From ; To                                                                              ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                               ;
-; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                               ;
-+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value ; From ; To                                                                                                                 ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                  ;
-+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ;
-+---------------------------+-------------+------+---------------------------------------------------------+
-; Assignment                ; Value       ; From ; To                                                      ;
-+---------------------------+-------------+------+---------------------------------------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                       ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                           ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                           ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                                     ;
-; DDIO_INPUT_REGISTER       ; LOW         ; -    ; input_cell_L                                            ;
-; DDIO_INPUT_REGISTER       ; HIGH        ; -    ; input_cell_H                                            ;
-; SUPPRESS_DA_RULE_INTERNAL ; D101        ; -    ; -                                                       ;
-; SUPPRESS_DA_RULE_INTERNAL ; D103        ; -    ; -                                                       ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                       ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                       ;
-; SUPPRESS_DA_RULE_INTERNAL ; D102        ; -    ; -                                                       ;
-+---------------------------+-------------+------+---------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ;
-+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                                                        ;
-+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL   ; C106  ; -    ; -                                                                                         ;
-; DDIO_INPUT_REGISTER         ; HIGH  ; -    ; input_cell_h                                                                              ;
-; DDIO_INPUT_REGISTER         ; LOW   ; -    ; input_cell_l                                                                              ;
-; MEGAFUNCTION_GENERATED_TRI  ; ON    ; -    ; tri_buf1a                                                                                 ;
-+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
-+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                       ;
-+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                        ;
-+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                                                ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                 ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                         ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                          ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                        ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                         ;
-+---------------------------------+--------------------+------+---------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                   ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                    ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                     ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
-+---------------------------------+--------------------+------+------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                    ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                      ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                      ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                       ;
-+---------------------------------+--------------------+------+-------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                    ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                     ;
-+---------------------------------+--------------------+------+-----------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+---------------------------------------------------+
-; Assignment                ; Value       ; From ; To                                                ;
-+---------------------------+-------------+------+---------------------------------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                 ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                     ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                     ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                               ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                 ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                 ;
-+---------------------------+-------------+------+---------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                                                ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                 ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+---------------------------------------------------+
-; Assignment                ; Value       ; From ; To                                                ;
-+---------------------------+-------------+------+---------------------------------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                                                 ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L                                     ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L                                     ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                                               ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                                                 ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                                                 ;
-+---------------------------+-------------+------+---------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                                                ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                                                 ;
-+-----------------------------+-------+------+-----------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------+
-; Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ;
-+---------------------------+-------+------+-----------------------------------------------+
-; Assignment                ; Value ; From ; To                                            ;
-+---------------------------+-------+------+-----------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; C104  ; -    ; -                                             ;
-+---------------------------+-------+------+-----------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ;
-+---------------------------------------+-------------+------+------------------------------------------------------+
-; Assignment                            ; Value       ; From ; To                                                   ;
-+---------------------------------------+-------------+------+------------------------------------------------------+
-; ADV_NETLIST_OPT_ALLOWED               ; NEVER_ALLOW ; -    ; -                                                    ;
-; SUPPRESS_DA_RULE_INTERNAL             ; C106        ; -    ; -                                                    ;
-; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 2           ; -    ; le_comb10                                            ;
-; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 0           ; -    ; le_comb8                                             ;
-; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 1           ; -    ; le_comb9                                             ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; idle_state                                           ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_data_nominal_state                              ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_data_state                                      ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_first_nominal_state                             ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_first_state                                     ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_init_nominal_state                              ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_init_state                                      ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_last_nominal_state                              ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; read_last_state                                      ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_counter_state                               ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_init_state                                  ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_post_state                                  ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_seq_data_state                              ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_seq_ena_state                               ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; reconfig_wait_state                                  ;
-; POWER_UP_LEVEL                        ; HIGH        ; -    ; reset_state                                          ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; write_data_state                                     ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; write_init_nominal_state                             ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; write_init_state                                     ;
-; POWER_UP_LEVEL                        ; LOW         ; -    ; write_nominal_state                                  ;
-+---------------------------------------+-------------+------+------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
-; Assignment                      ; Value              ; From ; To                                                                                                       ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                        ;
-+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                       ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                        ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                        ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                        ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                        ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                         ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                         ;
-+---------------------------+-------+------+-------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                       ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; Assignment                ; Value ; From ; To                                                                                       ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                                                                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                                                                        ;
-+---------------------------+-------+------+------------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------+
-; Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component ;
-+---------------------------+-------+------+-----------------------------------+
-; Assignment                ; Value ; From ; To                                ;
-+---------------------------+-------+------+-----------------------------------+
-; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -                                 ;
-; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -                                 ;
-; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -                                 ;
-+---------------------------+-------+------+-----------------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+----------------------------+
-; Assignment                ; Value       ; From ; To                         ;
-+---------------------------+-------------+------+----------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
-+---------------------------+-------------+------+----------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                         ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+----------------------------+
-; Assignment                ; Value       ; From ; To                         ;
-+---------------------------+-------------+------+----------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
-+---------------------------+-------------+------+----------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                         ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+----------------------------+
-; Assignment                ; Value       ; From ; To                         ;
-+---------------------------+-------------+------+----------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
-+---------------------------+-------------+------+----------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                         ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component ;
-+---------------------------+-------------+------+----------------------------+
-; Assignment                ; Value       ; From ; To                         ;
-+---------------------------+-------------+------+----------------------------+
-; ADV_NETLIST_OPT_ALLOWED   ; NEVER_ALLOW ; -    ; -                          ;
-; PRESERVE_REGISTER         ; ON          ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; LOW         ; -    ; output_cell_L              ;
-; DDIO_OUTPUT_REGISTER      ; HIGH        ; -    ; mux                        ;
-; SUPPRESS_DA_RULE_INTERNAL ; C104        ; -    ; -                          ;
-; SUPPRESS_DA_RULE_INTERNAL ; C106        ; -    ; -                          ;
-+---------------------------+-------------+------+----------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; Assignment                  ; Value ; From ; To                                                         ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-; SYNCHRONIZER_IDENTIFICATION ; OFF   ; -    ; -                                                          ;
-+-----------------------------+-------+------+------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component ;
-+-------------------------------+--------------------+------------------------------+
-; Parameter Name                ; Value              ; Type                         ;
-+-------------------------------+--------------------+------------------------------+
-; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                      ;
-; PLL_TYPE                      ; AUTO               ; Untyped                      ;
-; QUALIFY_CONF_DONE             ; OFF                ; Untyped                      ;
-; COMPENSATE_CLOCK              ; CLK0               ; Untyped                      ;
-; SCAN_CHAIN                    ; LONG               ; Untyped                      ;
-; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                      ;
-; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer               ;
-; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                      ;
-; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                      ;
-; GATE_LOCK_COUNTER             ; 0                  ; Untyped                      ;
-; LOCK_HIGH                     ; 1                  ; Untyped                      ;
-; LOCK_LOW                      ; 1                  ; Untyped                      ;
-; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                      ;
-; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                      ;
-; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                      ;
-; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                      ;
-; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                      ;
-; SKIP_VCO                      ; OFF                ; Untyped                      ;
-; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                      ;
-; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                      ;
-; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                      ;
-; BANDWIDTH                     ; 0                  ; Untyped                      ;
-; BANDWIDTH_TYPE                ; AUTO               ; Untyped                      ;
-; SPREAD_FREQUENCY              ; 0                  ; Untyped                      ;
-; DOWN_SPREAD                   ; 0                  ; Untyped                      ;
-; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                      ;
-; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                      ;
-; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                      ;
-; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                      ;
-; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                      ;
-; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                      ;
-; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                      ;
-; CLK4_MULTIPLY_BY              ; 1                  ; Untyped                      ;
-; CLK3_MULTIPLY_BY              ; 1                  ; Untyped                      ;
-; CLK2_MULTIPLY_BY              ; 67                 ; Signed Integer               ;
-; CLK1_MULTIPLY_BY              ; 67                 ; Signed Integer               ;
-; CLK0_MULTIPLY_BY              ; 1                  ; Signed Integer               ;
-; CLK9_DIVIDE_BY                ; 0                  ; Untyped                      ;
-; CLK8_DIVIDE_BY                ; 0                  ; Untyped                      ;
-; CLK7_DIVIDE_BY                ; 0                  ; Untyped                      ;
-; CLK6_DIVIDE_BY                ; 0                  ; Untyped                      ;
-; CLK5_DIVIDE_BY                ; 1                  ; Untyped                      ;
-; CLK4_DIVIDE_BY                ; 1                  ; Untyped                      ;
-; CLK3_DIVIDE_BY                ; 1                  ; Untyped                      ;
-; CLK2_DIVIDE_BY                ; 90                 ; Signed Integer               ;
-; CLK1_DIVIDE_BY                ; 900                ; Signed Integer               ;
-; CLK0_DIVIDE_BY                ; 66                 ; Signed Integer               ;
-; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK4_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK3_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK2_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK0_PHASE_SHIFT              ; 0                  ; Untyped                      ;
-; CLK5_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK4_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK3_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK2_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK1_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK0_TIME_DELAY               ; 0                  ; Untyped                      ;
-; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK4_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK3_DUTY_CYCLE               ; 50                 ; Untyped                      ;
-; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
-; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
-; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer               ;
-; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                      ;
-; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                      ;
-; LOCK_WINDOW_UI                ;  0.05              ; Untyped                      ;
-; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                      ;
-; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                      ;
-; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                      ;
-; DPA_MULTIPLY_BY               ; 0                  ; Untyped                      ;
-; DPA_DIVIDE_BY                 ; 1                  ; Untyped                      ;
-; DPA_DIVIDER                   ; 0                  ; Untyped                      ;
-; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                      ;
-; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                      ;
-; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                      ;
-; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                      ;
-; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                      ;
-; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                      ;
-; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                      ;
-; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                      ;
-; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                      ;
-; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                      ;
-; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                      ;
-; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                      ;
-; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                      ;
-; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                      ;
-; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                      ;
-; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                      ;
-; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                      ;
-; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                      ;
-; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                      ;
-; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                      ;
-; VCO_MULTIPLY_BY               ; 0                  ; Untyped                      ;
-; VCO_DIVIDE_BY                 ; 0                  ; Untyped                      ;
-; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                      ;
-; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                      ;
-; VCO_MIN                       ; 0                  ; Untyped                      ;
-; VCO_MAX                       ; 0                  ; Untyped                      ;
-; VCO_CENTER                    ; 0                  ; Untyped                      ;
-; PFD_MIN                       ; 0                  ; Untyped                      ;
-; PFD_MAX                       ; 0                  ; Untyped                      ;
-; M_INITIAL                     ; 0                  ; Untyped                      ;
-; M                             ; 0                  ; Untyped                      ;
-; N                             ; 1                  ; Untyped                      ;
-; M2                            ; 1                  ; Untyped                      ;
-; N2                            ; 1                  ; Untyped                      ;
-; SS                            ; 1                  ; Untyped                      ;
-; C0_HIGH                       ; 0                  ; Untyped                      ;
-; C1_HIGH                       ; 0                  ; Untyped                      ;
-; C2_HIGH                       ; 0                  ; Untyped                      ;
-; C3_HIGH                       ; 0                  ; Untyped                      ;
-; C4_HIGH                       ; 0                  ; Untyped                      ;
-; C5_HIGH                       ; 0                  ; Untyped                      ;
-; C6_HIGH                       ; 0                  ; Untyped                      ;
-; C7_HIGH                       ; 0                  ; Untyped                      ;
-; C8_HIGH                       ; 0                  ; Untyped                      ;
-; C9_HIGH                       ; 0                  ; Untyped                      ;
-; C0_LOW                        ; 0                  ; Untyped                      ;
-; C1_LOW                        ; 0                  ; Untyped                      ;
-; C2_LOW                        ; 0                  ; Untyped                      ;
-; C3_LOW                        ; 0                  ; Untyped                      ;
-; C4_LOW                        ; 0                  ; Untyped                      ;
-; C5_LOW                        ; 0                  ; Untyped                      ;
-; C6_LOW                        ; 0                  ; Untyped                      ;
-; C7_LOW                        ; 0                  ; Untyped                      ;
-; C8_LOW                        ; 0                  ; Untyped                      ;
-; C9_LOW                        ; 0                  ; Untyped                      ;
-; C0_INITIAL                    ; 0                  ; Untyped                      ;
-; C1_INITIAL                    ; 0                  ; Untyped                      ;
-; C2_INITIAL                    ; 0                  ; Untyped                      ;
-; C3_INITIAL                    ; 0                  ; Untyped                      ;
-; C4_INITIAL                    ; 0                  ; Untyped                      ;
-; C5_INITIAL                    ; 0                  ; Untyped                      ;
-; C6_INITIAL                    ; 0                  ; Untyped                      ;
-; C7_INITIAL                    ; 0                  ; Untyped                      ;
-; C8_INITIAL                    ; 0                  ; Untyped                      ;
-; C9_INITIAL                    ; 0                  ; Untyped                      ;
-; C0_MODE                       ; BYPASS             ; Untyped                      ;
-; C1_MODE                       ; BYPASS             ; Untyped                      ;
-; C2_MODE                       ; BYPASS             ; Untyped                      ;
-; C3_MODE                       ; BYPASS             ; Untyped                      ;
-; C4_MODE                       ; BYPASS             ; Untyped                      ;
-; C5_MODE                       ; BYPASS             ; Untyped                      ;
-; C6_MODE                       ; BYPASS             ; Untyped                      ;
-; C7_MODE                       ; BYPASS             ; Untyped                      ;
-; C8_MODE                       ; BYPASS             ; Untyped                      ;
-; C9_MODE                       ; BYPASS             ; Untyped                      ;
-; C0_PH                         ; 0                  ; Untyped                      ;
-; C1_PH                         ; 0                  ; Untyped                      ;
-; C2_PH                         ; 0                  ; Untyped                      ;
-; C3_PH                         ; 0                  ; Untyped                      ;
-; C4_PH                         ; 0                  ; Untyped                      ;
-; C5_PH                         ; 0                  ; Untyped                      ;
-; C6_PH                         ; 0                  ; Untyped                      ;
-; C7_PH                         ; 0                  ; Untyped                      ;
-; C8_PH                         ; 0                  ; Untyped                      ;
-; C9_PH                         ; 0                  ; Untyped                      ;
-; L0_HIGH                       ; 1                  ; Untyped                      ;
-; L1_HIGH                       ; 1                  ; Untyped                      ;
-; G0_HIGH                       ; 1                  ; Untyped                      ;
-; G1_HIGH                       ; 1                  ; Untyped                      ;
-; G2_HIGH                       ; 1                  ; Untyped                      ;
-; G3_HIGH                       ; 1                  ; Untyped                      ;
-; E0_HIGH                       ; 1                  ; Untyped                      ;
-; E1_HIGH                       ; 1                  ; Untyped                      ;
-; E2_HIGH                       ; 1                  ; Untyped                      ;
-; E3_HIGH                       ; 1                  ; Untyped                      ;
-; L0_LOW                        ; 1                  ; Untyped                      ;
-; L1_LOW                        ; 1                  ; Untyped                      ;
-; G0_LOW                        ; 1                  ; Untyped                      ;
-; G1_LOW                        ; 1                  ; Untyped                      ;
-; G2_LOW                        ; 1                  ; Untyped                      ;
-; G3_LOW                        ; 1                  ; Untyped                      ;
-; E0_LOW                        ; 1                  ; Untyped                      ;
-; E1_LOW                        ; 1                  ; Untyped                      ;
-; E2_LOW                        ; 1                  ; Untyped                      ;
-; E3_LOW                        ; 1                  ; Untyped                      ;
-; L0_INITIAL                    ; 1                  ; Untyped                      ;
-; L1_INITIAL                    ; 1                  ; Untyped                      ;
-; G0_INITIAL                    ; 1                  ; Untyped                      ;
-; G1_INITIAL                    ; 1                  ; Untyped                      ;
-; G2_INITIAL                    ; 1                  ; Untyped                      ;
-; G3_INITIAL                    ; 1                  ; Untyped                      ;
-; E0_INITIAL                    ; 1                  ; Untyped                      ;
-; E1_INITIAL                    ; 1                  ; Untyped                      ;
-; E2_INITIAL                    ; 1                  ; Untyped                      ;
-; E3_INITIAL                    ; 1                  ; Untyped                      ;
-; L0_MODE                       ; BYPASS             ; Untyped                      ;
-; L1_MODE                       ; BYPASS             ; Untyped                      ;
-; G0_MODE                       ; BYPASS             ; Untyped                      ;
-; G1_MODE                       ; BYPASS             ; Untyped                      ;
-; G2_MODE                       ; BYPASS             ; Untyped                      ;
-; G3_MODE                       ; BYPASS             ; Untyped                      ;
-; E0_MODE                       ; BYPASS             ; Untyped                      ;
-; E1_MODE                       ; BYPASS             ; Untyped                      ;
-; E2_MODE                       ; BYPASS             ; Untyped                      ;
-; E3_MODE                       ; BYPASS             ; Untyped                      ;
-; L0_PH                         ; 0                  ; Untyped                      ;
-; L1_PH                         ; 0                  ; Untyped                      ;
-; G0_PH                         ; 0                  ; Untyped                      ;
-; G1_PH                         ; 0                  ; Untyped                      ;
-; G2_PH                         ; 0                  ; Untyped                      ;
-; G3_PH                         ; 0                  ; Untyped                      ;
-; E0_PH                         ; 0                  ; Untyped                      ;
-; E1_PH                         ; 0                  ; Untyped                      ;
-; E2_PH                         ; 0                  ; Untyped                      ;
-; E3_PH                         ; 0                  ; Untyped                      ;
-; M_PH                          ; 0                  ; Untyped                      ;
-; C1_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C2_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C3_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C4_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C5_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C6_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C7_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C8_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; C9_USE_CASC_IN                ; OFF                ; Untyped                      ;
-; CLK0_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK1_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK2_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK3_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK4_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK5_COUNTER                  ; G0                 ; Untyped                      ;
-; CLK6_COUNTER                  ; E0                 ; Untyped                      ;
-; CLK7_COUNTER                  ; E1                 ; Untyped                      ;
-; CLK8_COUNTER                  ; E2                 ; Untyped                      ;
-; CLK9_COUNTER                  ; E3                 ; Untyped                      ;
-; L0_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; L1_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; G0_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; G1_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; G2_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; G3_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; E0_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; E1_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; E2_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; E3_TIME_DELAY                 ; 0                  ; Untyped                      ;
-; M_TIME_DELAY                  ; 0                  ; Untyped                      ;
-; N_TIME_DELAY                  ; 0                  ; Untyped                      ;
-; EXTCLK3_COUNTER               ; E3                 ; Untyped                      ;
-; EXTCLK2_COUNTER               ; E2                 ; Untyped                      ;
-; EXTCLK1_COUNTER               ; E1                 ; Untyped                      ;
-; EXTCLK0_COUNTER               ; E0                 ; Untyped                      ;
-; ENABLE0_COUNTER               ; L0                 ; Untyped                      ;
-; ENABLE1_COUNTER               ; L0                 ; Untyped                      ;
-; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                      ;
-; LOOP_FILTER_R                 ;  1.000000          ; Untyped                      ;
-; LOOP_FILTER_C                 ; 5                  ; Untyped                      ;
-; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                      ;
-; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                      ;
-; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                      ;
-; VCO_POST_SCALE                ; 0                  ; Untyped                      ;
-; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
-; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
-; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                      ;
-; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                      ;
-; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK0                     ; PORT_USED          ; Untyped                      ;
-; PORT_CLK1                     ; PORT_USED          ; Untyped                      ;
-; PORT_CLK2                     ; PORT_USED          ; Untyped                      ;
-; PORT_CLK3                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK4                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                      ;
-; PORT_INCLK0                   ; PORT_USED          ; Untyped                      ;
-; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                      ;
-; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                      ;
-; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                      ;
-; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                      ;
-; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                      ;
-; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_LOCKED                   ; PORT_USED          ; Untyped                      ;
-; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                      ;
-; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                      ;
-; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                      ;
-; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                      ;
-; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                      ;
-; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                      ;
-; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                      ;
-; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                      ;
-; M_TEST_SOURCE                 ; 5                  ; Untyped                      ;
-; C0_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C1_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C2_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C3_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C4_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C5_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C6_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C7_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C8_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; C9_TEST_SOURCE                ; 5                  ; Untyped                      ;
-; CBXI_PARAMETER                ; altpll_pul2        ; Untyped                      ;
-; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                      ;
-; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                      ;
-; WIDTH_CLOCK                   ; 5                  ; Signed Integer               ;
-; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                      ;
-; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                      ;
-; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                      ;
-; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                      ;
-; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                      ;
-; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                   ;
-; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                 ;
-; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                 ;
-; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE               ;
-+-------------------------------+--------------------+------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Name           ; Value       ; Type                                                                                                                            ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-; ACF_DISABLE_MLAB_RAM_USE ; FALSE       ; Untyped                                                                                                                         ;
-; ADD_RAM_OUTPUT_REGISTER  ; OFF         ; Untyped                                                                                                                         ;
-; ADD_USEDW_MSB_BIT        ; OFF         ; Untyped                                                                                                                         ;
-; CLOCKS_ARE_SYNCHRONIZED  ; FALSE       ; Untyped                                                                                                                         ;
-; DELAY_RDUSEDW            ; 1           ; Untyped                                                                                                                         ;
-; DELAY_WRUSEDW            ; 1           ; Untyped                                                                                                                         ;
-; LPM_NUMWORDS             ; 1024        ; Signed Integer                                                                                                                  ;
-; LPM_SHOWAHEAD            ; OFF         ; Untyped                                                                                                                         ;
-; LPM_WIDTH                ; 8           ; Signed Integer                                                                                                                  ;
-; LPM_WIDTH_R              ; 32          ; Signed Integer                                                                                                                  ;
-; LPM_WIDTHU               ; 10          ; Signed Integer                                                                                                                  ;
-; LPM_WIDTHU_R             ; 8           ; Signed Integer                                                                                                                  ;
-; MAXIMIZE_SPEED           ; 5           ; Untyped                                                                                                                         ;
-; OVERFLOW_CHECKING        ; ON          ; Untyped                                                                                                                         ;
-; RAM_BLOCK_TYPE           ; AUTO        ; Untyped                                                                                                                         ;
-; RDSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
-; UNDERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                         ;
-; USE_EAB                  ; ON          ; Untyped                                                                                                                         ;
-; WRITE_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                         ;
-; WRSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
-; CBXI_PARAMETER           ; dcfifo_0hh1 ; Untyped                                                                                                                         ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Name           ; Value       ; Type                                                                                                                            ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-; ACF_DISABLE_MLAB_RAM_USE ; FALSE       ; Untyped                                                                                                                         ;
-; ADD_RAM_OUTPUT_REGISTER  ; OFF         ; Untyped                                                                                                                         ;
-; ADD_USEDW_MSB_BIT        ; OFF         ; Untyped                                                                                                                         ;
-; CLOCKS_ARE_SYNCHRONIZED  ; FALSE       ; Untyped                                                                                                                         ;
-; DELAY_RDUSEDW            ; 1           ; Untyped                                                                                                                         ;
-; DELAY_WRUSEDW            ; 1           ; Untyped                                                                                                                         ;
-; LPM_NUMWORDS             ; 256         ; Signed Integer                                                                                                                  ;
-; LPM_SHOWAHEAD            ; OFF         ; Untyped                                                                                                                         ;
-; LPM_WIDTH                ; 32          ; Signed Integer                                                                                                                  ;
-; LPM_WIDTH_R              ; 8           ; Signed Integer                                                                                                                  ;
-; LPM_WIDTHU               ; 8           ; Signed Integer                                                                                                                  ;
-; LPM_WIDTHU_R             ; 10          ; Signed Integer                                                                                                                  ;
-; MAXIMIZE_SPEED           ; 5           ; Untyped                                                                                                                         ;
-; OVERFLOW_CHECKING        ; ON          ; Untyped                                                                                                                         ;
-; RAM_BLOCK_TYPE           ; AUTO        ; Untyped                                                                                                                         ;
-; RDSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
-; UNDERFLOW_CHECKING       ; ON          ; Untyped                                                                                                                         ;
-; USE_EAB                  ; ON          ; Untyped                                                                                                                         ;
-; WRITE_ACLR_SYNCH         ; OFF         ; Untyped                                                                                                                         ;
-; WRSYNC_DELAYPIPE         ; 5           ; Signed Integer                                                                                                                  ;
-; CBXI_PARAMETER           ; dcfifo_3fh1 ; Untyped                                                                                                                         ;
-+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ;
-+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                                                                        ;
-+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
-; TOP            ; 152   ; Signed Integer                                                                                                                              ;
-; BOTTOM         ; 104   ; Signed Integer                                                                                                                              ;
-; PHASE_CORR     ; 75    ; Signed Integer                                                                                                                              ;
-+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component ;
-+-------------------------------+--------------------+--------------------------------+
-; Parameter Name                ; Value              ; Type                           ;
-+-------------------------------+--------------------+--------------------------------+
-; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                        ;
-; PLL_TYPE                      ; AUTO               ; Untyped                        ;
-; QUALIFY_CONF_DONE             ; OFF                ; Untyped                        ;
-; COMPENSATE_CLOCK              ; CLK1               ; Untyped                        ;
-; SCAN_CHAIN                    ; LONG               ; Untyped                        ;
-; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                        ;
-; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer                 ;
-; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                        ;
-; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                        ;
-; GATE_LOCK_COUNTER             ; 0                  ; Untyped                        ;
-; LOCK_HIGH                     ; 1                  ; Untyped                        ;
-; LOCK_LOW                      ; 1                  ; Untyped                        ;
-; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                        ;
-; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                        ;
-; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                        ;
-; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                        ;
-; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                        ;
-; SKIP_VCO                      ; OFF                ; Untyped                        ;
-; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                        ;
-; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                        ;
-; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                        ;
-; BANDWIDTH                     ; 0                  ; Untyped                        ;
-; BANDWIDTH_TYPE                ; AUTO               ; Untyped                        ;
-; SPREAD_FREQUENCY              ; 0                  ; Untyped                        ;
-; DOWN_SPREAD                   ; 0                  ; Untyped                        ;
-; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                        ;
-; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                        ;
-; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                        ;
-; CLK4_MULTIPLY_BY              ; 1                  ; Untyped                        ;
-; CLK3_MULTIPLY_BY              ; 16                 ; Signed Integer                 ;
-; CLK2_MULTIPLY_BY              ; 25                 ; Signed Integer                 ;
-; CLK1_MULTIPLY_BY              ; 16                 ; Signed Integer                 ;
-; CLK0_MULTIPLY_BY              ; 2                  ; Signed Integer                 ;
-; CLK9_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK8_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK7_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK6_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK5_DIVIDE_BY                ; 1                  ; Untyped                        ;
-; CLK4_DIVIDE_BY                ; 1                  ; Untyped                        ;
-; CLK3_DIVIDE_BY                ; 11                 ; Signed Integer                 ;
-; CLK2_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
-; CLK1_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
-; CLK0_DIVIDE_BY                ; 33                 ; Signed Integer                 ;
-; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK4_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK3_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK2_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK0_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK5_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK4_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK3_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK2_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK1_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK0_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK4_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK3_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; LOCK_WINDOW_UI                ;  0.05              ; Untyped                        ;
-; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                        ;
-; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                        ;
-; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                        ;
-; DPA_MULTIPLY_BY               ; 0                  ; Untyped                        ;
-; DPA_DIVIDE_BY                 ; 1                  ; Untyped                        ;
-; DPA_DIVIDER                   ; 0                  ; Untyped                        ;
-; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; VCO_MULTIPLY_BY               ; 0                  ; Untyped                        ;
-; VCO_DIVIDE_BY                 ; 0                  ; Untyped                        ;
-; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                        ;
-; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                        ;
-; VCO_MIN                       ; 0                  ; Untyped                        ;
-; VCO_MAX                       ; 0                  ; Untyped                        ;
-; VCO_CENTER                    ; 0                  ; Untyped                        ;
-; PFD_MIN                       ; 0                  ; Untyped                        ;
-; PFD_MAX                       ; 0                  ; Untyped                        ;
-; M_INITIAL                     ; 0                  ; Untyped                        ;
-; M                             ; 0                  ; Untyped                        ;
-; N                             ; 1                  ; Untyped                        ;
-; M2                            ; 1                  ; Untyped                        ;
-; N2                            ; 1                  ; Untyped                        ;
-; SS                            ; 1                  ; Untyped                        ;
-; C0_HIGH                       ; 0                  ; Untyped                        ;
-; C1_HIGH                       ; 0                  ; Untyped                        ;
-; C2_HIGH                       ; 0                  ; Untyped                        ;
-; C3_HIGH                       ; 0                  ; Untyped                        ;
-; C4_HIGH                       ; 0                  ; Untyped                        ;
-; C5_HIGH                       ; 0                  ; Untyped                        ;
-; C6_HIGH                       ; 0                  ; Untyped                        ;
-; C7_HIGH                       ; 0                  ; Untyped                        ;
-; C8_HIGH                       ; 0                  ; Untyped                        ;
-; C9_HIGH                       ; 0                  ; Untyped                        ;
-; C0_LOW                        ; 0                  ; Untyped                        ;
-; C1_LOW                        ; 0                  ; Untyped                        ;
-; C2_LOW                        ; 0                  ; Untyped                        ;
-; C3_LOW                        ; 0                  ; Untyped                        ;
-; C4_LOW                        ; 0                  ; Untyped                        ;
-; C5_LOW                        ; 0                  ; Untyped                        ;
-; C6_LOW                        ; 0                  ; Untyped                        ;
-; C7_LOW                        ; 0                  ; Untyped                        ;
-; C8_LOW                        ; 0                  ; Untyped                        ;
-; C9_LOW                        ; 0                  ; Untyped                        ;
-; C0_INITIAL                    ; 0                  ; Untyped                        ;
-; C1_INITIAL                    ; 0                  ; Untyped                        ;
-; C2_INITIAL                    ; 0                  ; Untyped                        ;
-; C3_INITIAL                    ; 0                  ; Untyped                        ;
-; C4_INITIAL                    ; 0                  ; Untyped                        ;
-; C5_INITIAL                    ; 0                  ; Untyped                        ;
-; C6_INITIAL                    ; 0                  ; Untyped                        ;
-; C7_INITIAL                    ; 0                  ; Untyped                        ;
-; C8_INITIAL                    ; 0                  ; Untyped                        ;
-; C9_INITIAL                    ; 0                  ; Untyped                        ;
-; C0_MODE                       ; BYPASS             ; Untyped                        ;
-; C1_MODE                       ; BYPASS             ; Untyped                        ;
-; C2_MODE                       ; BYPASS             ; Untyped                        ;
-; C3_MODE                       ; BYPASS             ; Untyped                        ;
-; C4_MODE                       ; BYPASS             ; Untyped                        ;
-; C5_MODE                       ; BYPASS             ; Untyped                        ;
-; C6_MODE                       ; BYPASS             ; Untyped                        ;
-; C7_MODE                       ; BYPASS             ; Untyped                        ;
-; C8_MODE                       ; BYPASS             ; Untyped                        ;
-; C9_MODE                       ; BYPASS             ; Untyped                        ;
-; C0_PH                         ; 0                  ; Untyped                        ;
-; C1_PH                         ; 0                  ; Untyped                        ;
-; C2_PH                         ; 0                  ; Untyped                        ;
-; C3_PH                         ; 0                  ; Untyped                        ;
-; C4_PH                         ; 0                  ; Untyped                        ;
-; C5_PH                         ; 0                  ; Untyped                        ;
-; C6_PH                         ; 0                  ; Untyped                        ;
-; C7_PH                         ; 0                  ; Untyped                        ;
-; C8_PH                         ; 0                  ; Untyped                        ;
-; C9_PH                         ; 0                  ; Untyped                        ;
-; L0_HIGH                       ; 1                  ; Untyped                        ;
-; L1_HIGH                       ; 1                  ; Untyped                        ;
-; G0_HIGH                       ; 1                  ; Untyped                        ;
-; G1_HIGH                       ; 1                  ; Untyped                        ;
-; G2_HIGH                       ; 1                  ; Untyped                        ;
-; G3_HIGH                       ; 1                  ; Untyped                        ;
-; E0_HIGH                       ; 1                  ; Untyped                        ;
-; E1_HIGH                       ; 1                  ; Untyped                        ;
-; E2_HIGH                       ; 1                  ; Untyped                        ;
-; E3_HIGH                       ; 1                  ; Untyped                        ;
-; L0_LOW                        ; 1                  ; Untyped                        ;
-; L1_LOW                        ; 1                  ; Untyped                        ;
-; G0_LOW                        ; 1                  ; Untyped                        ;
-; G1_LOW                        ; 1                  ; Untyped                        ;
-; G2_LOW                        ; 1                  ; Untyped                        ;
-; G3_LOW                        ; 1                  ; Untyped                        ;
-; E0_LOW                        ; 1                  ; Untyped                        ;
-; E1_LOW                        ; 1                  ; Untyped                        ;
-; E2_LOW                        ; 1                  ; Untyped                        ;
-; E3_LOW                        ; 1                  ; Untyped                        ;
-; L0_INITIAL                    ; 1                  ; Untyped                        ;
-; L1_INITIAL                    ; 1                  ; Untyped                        ;
-; G0_INITIAL                    ; 1                  ; Untyped                        ;
-; G1_INITIAL                    ; 1                  ; Untyped                        ;
-; G2_INITIAL                    ; 1                  ; Untyped                        ;
-; G3_INITIAL                    ; 1                  ; Untyped                        ;
-; E0_INITIAL                    ; 1                  ; Untyped                        ;
-; E1_INITIAL                    ; 1                  ; Untyped                        ;
-; E2_INITIAL                    ; 1                  ; Untyped                        ;
-; E3_INITIAL                    ; 1                  ; Untyped                        ;
-; L0_MODE                       ; BYPASS             ; Untyped                        ;
-; L1_MODE                       ; BYPASS             ; Untyped                        ;
-; G0_MODE                       ; BYPASS             ; Untyped                        ;
-; G1_MODE                       ; BYPASS             ; Untyped                        ;
-; G2_MODE                       ; BYPASS             ; Untyped                        ;
-; G3_MODE                       ; BYPASS             ; Untyped                        ;
-; E0_MODE                       ; BYPASS             ; Untyped                        ;
-; E1_MODE                       ; BYPASS             ; Untyped                        ;
-; E2_MODE                       ; BYPASS             ; Untyped                        ;
-; E3_MODE                       ; BYPASS             ; Untyped                        ;
-; L0_PH                         ; 0                  ; Untyped                        ;
-; L1_PH                         ; 0                  ; Untyped                        ;
-; G0_PH                         ; 0                  ; Untyped                        ;
-; G1_PH                         ; 0                  ; Untyped                        ;
-; G2_PH                         ; 0                  ; Untyped                        ;
-; G3_PH                         ; 0                  ; Untyped                        ;
-; E0_PH                         ; 0                  ; Untyped                        ;
-; E1_PH                         ; 0                  ; Untyped                        ;
-; E2_PH                         ; 0                  ; Untyped                        ;
-; E3_PH                         ; 0                  ; Untyped                        ;
-; M_PH                          ; 0                  ; Untyped                        ;
-; C1_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C2_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C3_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C4_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C5_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C6_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C7_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C8_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C9_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; CLK0_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK1_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK2_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK3_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK4_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK5_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK6_COUNTER                  ; E0                 ; Untyped                        ;
-; CLK7_COUNTER                  ; E1                 ; Untyped                        ;
-; CLK8_COUNTER                  ; E2                 ; Untyped                        ;
-; CLK9_COUNTER                  ; E3                 ; Untyped                        ;
-; L0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; L1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G2_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G3_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E2_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E3_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; M_TIME_DELAY                  ; 0                  ; Untyped                        ;
-; N_TIME_DELAY                  ; 0                  ; Untyped                        ;
-; EXTCLK3_COUNTER               ; E3                 ; Untyped                        ;
-; EXTCLK2_COUNTER               ; E2                 ; Untyped                        ;
-; EXTCLK1_COUNTER               ; E1                 ; Untyped                        ;
-; EXTCLK0_COUNTER               ; E0                 ; Untyped                        ;
-; ENABLE0_COUNTER               ; L0                 ; Untyped                        ;
-; ENABLE1_COUNTER               ; L0                 ; Untyped                        ;
-; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                        ;
-; LOOP_FILTER_R                 ;  1.000000          ; Untyped                        ;
-; LOOP_FILTER_C                 ; 5                  ; Untyped                        ;
-; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                        ;
-; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                        ;
-; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                        ;
-; VCO_POST_SCALE                ; 0                  ; Untyped                        ;
-; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                        ;
-; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK0                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK1                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK2                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK3                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK4                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_INCLK0                   ; PORT_USED          ; Untyped                        ;
-; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_LOCKED                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                        ;
-; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                        ;
-; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                        ;
-; M_TEST_SOURCE                 ; 5                  ; Untyped                        ;
-; C0_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C1_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C2_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C3_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C4_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C5_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C6_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C7_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C8_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C9_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; CBXI_PARAMETER                ; altpll_41p2        ; Untyped                        ;
-; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                        ;
-; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                        ;
-; WIDTH_CLOCK                   ; 5                  ; Signed Integer                 ;
-; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                        ;
-; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                        ;
-; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                        ;
-; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                        ;
-; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                        ;
-; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                     ;
-; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                   ;
-; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                   ;
-; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE                 ;
-+-------------------------------+--------------------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 16    ; Signed Integer                                                                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 16    ; Signed Integer                                                                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                  ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
-; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                                             ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                                   ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                                             ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                                   ;
-+----------------+-------+------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-; Parameter Name          ; Value       ; Type                                                                  ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-; WIDTH_BYTEENA           ; 1           ; Untyped                                                               ;
-; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                            ;
-; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                          ;
-; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                          ;
-; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                        ;
-; LPM_WIDTH               ; 128         ; Signed Integer                                                        ;
-; LPM_NUMWORDS            ; 512         ; Signed Integer                                                        ;
-; LPM_WIDTHU              ; 9           ; Signed Integer                                                        ;
-; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                               ;
-; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                               ;
-; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                               ;
-; USE_EAB                 ; ON          ; Untyped                                                               ;
-; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                               ;
-; DELAY_RDUSEDW           ; 1           ; Untyped                                                               ;
-; DELAY_WRUSEDW           ; 1           ; Untyped                                                               ;
-; RDSYNC_DELAYPIPE        ; 6           ; Signed Integer                                                        ;
-; WRSYNC_DELAYPIPE        ; 6           ; Signed Integer                                                        ;
-; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                               ;
-; MAXIMIZE_SPEED          ; 5           ; Untyped                                                               ;
-; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                               ;
-; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                               ;
-; WRITE_ACLR_SYNCH        ; ON          ; Untyped                                                               ;
-; CBXI_PARAMETER          ; dcfifo_8fi1 ; Untyped                                                               ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                  ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
-; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+---------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                              ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                              ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                            ;
-; LPM_WIDTH              ; 128         ; Signed Integer                                                            ;
-; LPM_SIZE               ; 16          ; Signed Integer                                                            ;
-; LPM_WIDTHS             ; 4           ; Signed Integer                                                            ;
-; LPM_PIPELINE           ; 0           ; Signed Integer                                                            ;
-; CBXI_PARAMETER         ; mux_bbe     ; Untyped                                                                   ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                   ;
-+------------------------+-------------+---------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
-+------------------------+-------------+--------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
-+------------------------+-------------+--------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ;
-+--------------------------+----------------+------------------------------------------------------------------------------------+
-; Parameter Name           ; Value          ; Type                                                                               ;
-+--------------------------+----------------+------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS        ; ON             ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS     ; OFF            ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS      ; ON             ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS   ; OFF            ; IGNORE_CASCADE                                                                     ;
-; WIDTH                    ; 32             ; Signed Integer                                                                     ;
-; POWER_UP_HIGH            ; OFF            ; Untyped                                                                            ;
-; OE_REG                   ; UNUSED         ; Untyped                                                                            ;
-; extend_oe_disable        ; UNUSED         ; Untyped                                                                            ;
-; IMPLEMENT_INPUT_IN_LCELL ; ON             ; Untyped                                                                            ;
-; INTENDED_DEVICE_FAMILY   ; Cyclone III    ; Untyped                                                                            ;
-; DEVICE_FAMILY            ; Cyclone III    ; Untyped                                                                            ;
-; CBXI_PARAMETER           ; ddio_bidir_3jl ; Untyped                                                                            ;
-+--------------------------+----------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                   ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
-; LPM_WIDTH              ; 64          ; Signed Integer                                                         ;
-; LPM_SIZE               ; 4           ; Signed Integer                                                         ;
-; LPM_WIDTHS             ; 2           ; Signed Integer                                                         ;
-; LPM_PIPELINE           ; 0           ; Signed Integer                                                         ;
-; CBXI_PARAMETER         ; mux_58e     ; Untyped                                                                ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
-+------------------------+-------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 128         ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ;
-+----------------+--------+-------------------------------------------------------------------------------------------+
-; Parameter Name ; Value  ; Type                                                                                      ;
-+----------------+--------+-------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 32     ; Signed Integer                                                                            ;
-; LPM_AVALUE     ; UNUSED ; Untyped                                                                                   ;
-+----------------+--------+-------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                  ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 5           ; Signed Integer                                                                        ;
-; LPM_DIRECTION          ; RIGHT       ; Untyped                                                                               ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                               ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                               ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                               ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                        ;
-+------------------------+-------------+---------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 32    ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+------------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                   ;
-+------------------------------------+-----------------+------------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                         ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                ;
-; WIDTH_A                            ; 6               ; Signed Integer                                                         ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                         ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                         ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                ;
-; WIDTH_B                            ; 6               ; Signed Integer                                                         ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                         ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                         ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                         ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                         ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                                ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                                ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                                ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                ;
-; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                ;
-+------------------------------------+-----------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                    ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                              ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                            ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                            ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                          ;
-; LPM_WIDTH              ; 128         ; Signed Integer                                                          ;
-; LPM_SIZE               ; 2           ; Signed Integer                                                          ;
-; LPM_WIDTHS             ; 1           ; Signed Integer                                                          ;
-; LPM_PIPELINE           ; 1           ; Signed Integer                                                          ;
-; CBXI_PARAMETER         ; mux_dcf     ; Untyped                                                                 ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                 ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-; Parameter Name          ; Value       ; Type                                                                  ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                            ;
-; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                          ;
-; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                          ;
-; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                        ;
-; lpm_width               ; 128         ; Signed Integer                                                        ;
-; LPM_NUMWORDS            ; 128         ; Signed Integer                                                        ;
-; LPM_WIDTHU              ; 7           ; Signed Integer                                                        ;
-; LPM_SHOWAHEAD           ; ON          ; Untyped                                                               ;
-; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                               ;
-; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                               ;
-; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                               ;
-; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                               ;
-; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                               ;
-; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                               ;
-; USE_EAB                 ; ON          ; Untyped                                                               ;
-; MAXIMIZE_SPEED          ; 5           ; Untyped                                                               ;
-; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                               ;
-; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                               ;
-; CBXI_PARAMETER          ; scfifo_lk21 ; Untyped                                                               ;
-+-------------------------+-------------+-----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                               ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                                     ;
-; LPM_DIRECTION          ; LEFT        ; Untyped                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                     ;
-+------------------------+-------------+------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+--------------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                     ;
-+------------------------------------+-----------------+--------------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                  ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                               ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                             ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                             ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                           ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                  ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                  ;
-; WIDTH_A                            ; 6               ; Signed Integer                                                           ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                           ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                           ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                  ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                  ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                  ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                  ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                  ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                  ;
-; WIDTH_B                            ; 6               ; Signed Integer                                                           ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                           ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                           ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                  ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                  ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                  ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                  ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                  ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                  ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                  ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                  ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                  ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                  ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                           ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                           ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                  ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                                  ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                  ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                  ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                  ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                                  ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                  ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                  ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                  ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                  ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                  ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                  ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                  ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                  ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                                  ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                  ;
-; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                  ;
-+------------------------------------+-----------------+--------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 6     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+-------------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                    ;
-+------------------------------------+-----------------+-------------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                 ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                              ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                            ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                            ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                          ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                                 ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                 ;
-; WIDTH_A                            ; 6               ; Signed Integer                                                          ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                          ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                          ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                                 ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                 ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                 ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                 ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                 ;
-; WIDTH_B                            ; 6               ; Signed Integer                                                          ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                          ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                          ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                 ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                 ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                 ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                 ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                 ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                 ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                 ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                 ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                          ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                          ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                 ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                                 ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                 ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                                 ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                                 ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                                 ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                 ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                 ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                                 ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                                 ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                                 ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                                 ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                                 ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                                 ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                                 ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                                 ;
-; CBXI_PARAMETER                     ; altsyncram_lf92 ; Untyped                                                                 ;
-+------------------------------------+-----------------+-------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+--------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                               ;
-+------------------------------------+-----------------+--------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                            ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                         ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                       ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                       ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                     ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                            ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                            ;
-; WIDTH_A                            ; 3               ; Signed Integer                                                     ;
-; WIDTHAD_A                          ; 4               ; Signed Integer                                                     ;
-; NUMWORDS_A                         ; 16              ; Signed Integer                                                     ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                            ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                            ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                            ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                            ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                            ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                            ;
-; WIDTH_B                            ; 3               ; Signed Integer                                                     ;
-; WIDTHAD_B                          ; 4               ; Signed Integer                                                     ;
-; NUMWORDS_B                         ; 16              ; Signed Integer                                                     ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                            ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                            ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                            ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                            ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                            ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                            ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                            ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                            ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                            ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                            ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                            ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                            ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                     ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                     ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                            ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                            ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                            ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                            ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                            ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                            ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                            ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                            ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                            ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                            ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                            ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                            ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                            ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                            ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                            ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                            ;
-; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                            ;
-+------------------------------------+-----------------+--------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+----------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                 ;
-+------------------------------------+-----------------+----------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                              ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                           ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                         ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                         ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                       ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                              ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                              ;
-; WIDTH_A                            ; 3               ; Signed Integer                                                       ;
-; WIDTHAD_A                          ; 4               ; Signed Integer                                                       ;
-; NUMWORDS_A                         ; 16              ; Signed Integer                                                       ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                              ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                              ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                              ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                              ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                              ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                              ;
-; WIDTH_B                            ; 3               ; Signed Integer                                                       ;
-; WIDTHAD_B                          ; 4               ; Signed Integer                                                       ;
-; NUMWORDS_B                         ; 16              ; Signed Integer                                                       ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                              ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                              ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                              ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                              ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                              ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                              ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                              ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                              ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                              ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                              ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                              ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                              ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                       ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                       ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                              ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                              ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                              ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                              ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                              ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                              ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                              ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                              ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                              ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                              ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                              ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                              ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                              ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                              ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                              ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                              ;
-; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                              ;
-+------------------------------------+-----------------+----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                          ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 3     ; Signed Integer                                                                                ;
-+----------------+-------+-----------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                      ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                             ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                             ;
-; WIDTH_A                            ; 3               ; Signed Integer                                                      ;
-; WIDTHAD_A                          ; 4               ; Signed Integer                                                      ;
-; NUMWORDS_A                         ; 16              ; Signed Integer                                                      ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                             ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                             ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                             ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; WIDTH_B                            ; 3               ; Signed Integer                                                      ;
-; WIDTHAD_B                          ; 4               ; Signed Integer                                                      ;
-; NUMWORDS_B                         ; 16              ; Signed Integer                                                      ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                             ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                             ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                             ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                             ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                      ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                      ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                             ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                             ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                             ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                             ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                             ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                             ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                             ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                             ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                             ;
-; CBXI_PARAMETER                     ; altsyncram_rb92 ; Untyped                                                             ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                             ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                  ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                               ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                            ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                          ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                          ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                        ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                               ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                               ;
-; WIDTH_A                            ; 8               ; Signed Integer                                                        ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                        ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                        ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                               ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                               ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                               ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; WIDTH_B                            ; 8               ; Signed Integer                                                        ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                        ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                        ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                               ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                               ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                               ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                               ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                        ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                        ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                               ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                               ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                               ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                               ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                               ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                               ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                               ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                               ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                               ;
-; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                               ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                    ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                              ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                            ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                            ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                          ;
-; LPM_WIDTH              ; 1           ; Signed Integer                                                          ;
-; LPM_SIZE               ; 2           ; Signed Integer                                                          ;
-; LPM_WIDTHS             ; 1           ; Signed Integer                                                          ;
-; LPM_PIPELINE           ; 0           ; Signed Integer                                                          ;
-; CBXI_PARAMETER         ; mux_96e     ; Untyped                                                                 ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                 ;
-+------------------------+-------------+-------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 8           ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                   ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
-; LPM_WIDTH              ; 8           ; Signed Integer                                                         ;
-; LPM_SIZE               ; 16          ; Signed Integer                                                         ;
-; LPM_WIDTHS             ; 4           ; Signed Integer                                                         ;
-; LPM_PIPELINE           ; 2           ; Signed Integer                                                         ;
-; CBXI_PARAMETER         ; mux_mpe     ; Untyped                                                                ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
-+------------------------+-------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                   ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
-; LPM_WIDTH              ; 7           ; Signed Integer                                                         ;
-; LPM_SIZE               ; 2           ; Signed Integer                                                         ;
-; LPM_WIDTHS             ; 1           ; Signed Integer                                                         ;
-; LPM_PIPELINE           ; 0           ; Signed Integer                                                         ;
-; CBXI_PARAMETER         ; mux_f6e     ; Untyped                                                                ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
-+------------------------+-------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 7                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_pf6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                             ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                  ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                               ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                            ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                          ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                          ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                        ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                               ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                               ;
-; WIDTH_A                            ; 8               ; Signed Integer                                                        ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                        ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                        ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                               ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                               ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                               ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                               ;
-; WIDTH_B                            ; 8               ; Signed Integer                                                        ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                        ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                        ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                               ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                               ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                               ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                               ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                               ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                               ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                               ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                        ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                        ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                               ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                               ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                               ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                               ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                               ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                               ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                               ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                               ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                               ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                               ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                               ;
-; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                               ;
-+------------------------------------+-----------------+-----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                             ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                   ;
-+----------------+-------+--------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-; Parameter Name                     ; Value           ; Type                                                                ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                      ;
-; WIDTH_BYTEENA                      ; 1               ; Untyped                                                             ;
-; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                             ;
-; WIDTH_A                            ; 8               ; Signed Integer                                                      ;
-; WIDTHAD_A                          ; 8               ; Signed Integer                                                      ;
-; NUMWORDS_A                         ; 256             ; Signed Integer                                                      ;
-; OUTDATA_REG_A                      ; CLOCK0          ; Untyped                                                             ;
-; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                             ;
-; INDATA_ACLR_A                      ; NONE            ; Untyped                                                             ;
-; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                             ;
-; WIDTH_B                            ; 8               ; Signed Integer                                                      ;
-; WIDTHAD_B                          ; 8               ; Signed Integer                                                      ;
-; NUMWORDS_B                         ; 256             ; Signed Integer                                                      ;
-; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                             ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                             ;
-; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                             ;
-; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; OUTDATA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                             ;
-; INDATA_ACLR_B                      ; NONE            ; Untyped                                                             ;
-; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
-; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                             ;
-; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                             ;
-; WIDTH_BYTEENA_A                    ; 1               ; Signed Integer                                                      ;
-; WIDTH_BYTEENA_B                    ; 1               ; Signed Integer                                                      ;
-; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                             ;
-; BYTE_SIZE                          ; 8               ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_PORT_A      ; OLD_DATA        ; Untyped                                                             ;
-; READ_DURING_WRITE_MODE_PORT_B      ; OLD_DATA        ; Untyped                                                             ;
-; INIT_FILE                          ; UNUSED          ; Untyped                                                             ;
-; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                             ;
-; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                             ;
-; CLOCK_ENABLE_INPUT_A               ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_INPUT_B               ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_OUTPUT_A              ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_OUTPUT_B              ; BYPASS          ; Untyped                                                             ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN ; Untyped                                                             ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN ; Untyped                                                             ;
-; ENABLE_ECC                         ; FALSE           ; Untyped                                                             ;
-; DEVICE_FAMILY                      ; Cyclone III     ; Untyped                                                             ;
-; CBXI_PARAMETER                     ; altsyncram_pf92 ; Untyped                                                             ;
-+------------------------------------+-----------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                                             ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                       ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                     ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                     ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                   ;
-; WIDTH                  ; 24           ; Signed Integer                                                                   ;
-; POWER_UP_HIGH          ; OFF          ; Untyped                                                                          ;
-; OE_REG                 ; UNUSED       ; Untyped                                                                          ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                                          ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                                          ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                                          ;
-; CBXI_PARAMETER         ; ddio_out_o2f ; Untyped                                                                          ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+-----------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                  ;
-+------------------------+-------------+-----------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                        ;
-; LPM_WIDTH              ; 24          ; Signed Integer                                                        ;
-; LPM_SIZE               ; 8           ; Signed Integer                                                        ;
-; LPM_WIDTHS             ; 3           ; Signed Integer                                                        ;
-; LPM_PIPELINE           ; 2           ; Signed Integer                                                        ;
-; CBXI_PARAMETER         ; mux_kpe     ; Untyped                                                               ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                               ;
-+------------------------+-------------+-----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 5                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_nf6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 24          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 2                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_4e6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 16          ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                   ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
-; LPM_WIDTH              ; 16          ; Signed Integer                                                         ;
-; LPM_SIZE               ; 8           ; Signed Integer                                                         ;
-; LPM_WIDTHS             ; 3           ; Signed Integer                                                         ;
-; LPM_PIPELINE           ; 4           ; Signed Integer                                                         ;
-; CBXI_PARAMETER         ; mux_npe     ; Untyped                                                                ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
-+------------------------+-------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; Parameter Name     ; Value            ; Type                                                                                 ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-; LPM_WIDTH          ; 8                ; Signed Integer                                                                       ;
-; LPM_CVALUE         ; 0                ; Signed Integer                                                                       ;
-; ENABLE_RUNTIME_MOD ; NO               ; Untyped                                                                              ;
-; CBXI_PARAMETER     ; lpm_constant_qf6 ; Untyped                                                                              ;
-+--------------------+------------------+--------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                                                     ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                            ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                            ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                     ;
-+------------------------+-------------+--------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                   ;
-+------------------------+-------------+------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                             ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                           ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                           ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                         ;
-; LPM_WIDTH              ; 32          ; Signed Integer                                                         ;
-; LPM_SIZE               ; 4           ; Signed Integer                                                         ;
-; LPM_WIDTHS             ; 2           ; Signed Integer                                                         ;
-; LPM_PIPELINE           ; 4           ; Signed Integer                                                         ;
-; CBXI_PARAMETER         ; mux_gpe     ; Untyped                                                                ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                ;
-+------------------------+-------------+------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                                             ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                                       ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                                                     ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                                                     ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                                                   ;
-; WIDTH                  ; 4            ; Signed Integer                                                                   ;
-; POWER_UP_HIGH          ; ON           ; Untyped                                                                          ;
-; OE_REG                 ; UNUSED       ; Untyped                                                                          ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                                          ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                                          ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                                          ;
-; CBXI_PARAMETER         ; ddio_out_are ; Untyped                                                                          ;
-+------------------------+--------------+----------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------+
-; LPM_WIDTH              ; 8           ; Signed Integer                                                      ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                             ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                             ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                                             ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                      ;
-+------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component ;
-+-------------------------------+--------------------+--------------------------------+
-; Parameter Name                ; Value              ; Type                           ;
-+-------------------------------+--------------------+--------------------------------+
-; OPERATION_MODE                ; SOURCE_SYNCHRONOUS ; Untyped                        ;
-; PLL_TYPE                      ; AUTO               ; Untyped                        ;
-; QUALIFY_CONF_DONE             ; OFF                ; Untyped                        ;
-; COMPENSATE_CLOCK              ; CLK0               ; Untyped                        ;
-; SCAN_CHAIN                    ; LONG               ; Untyped                        ;
-; PRIMARY_CLOCK                 ; INCLK0             ; Untyped                        ;
-; INCLK0_INPUT_FREQUENCY        ; 30303              ; Signed Integer                 ;
-; INCLK1_INPUT_FREQUENCY        ; 0                  ; Untyped                        ;
-; GATE_LOCK_SIGNAL              ; NO                 ; Untyped                        ;
-; GATE_LOCK_COUNTER             ; 0                  ; Untyped                        ;
-; LOCK_HIGH                     ; 1                  ; Untyped                        ;
-; LOCK_LOW                      ; 1                  ; Untyped                        ;
-; VALID_LOCK_MULTIPLIER         ; 1                  ; Untyped                        ;
-; INVALID_LOCK_MULTIPLIER       ; 5                  ; Untyped                        ;
-; SWITCH_OVER_ON_LOSSCLK        ; OFF                ; Untyped                        ;
-; SWITCH_OVER_ON_GATED_LOCK     ; OFF                ; Untyped                        ;
-; ENABLE_SWITCH_OVER_COUNTER    ; OFF                ; Untyped                        ;
-; SKIP_VCO                      ; OFF                ; Untyped                        ;
-; SWITCH_OVER_COUNTER           ; 0                  ; Untyped                        ;
-; SWITCH_OVER_TYPE              ; AUTO               ; Untyped                        ;
-; FEEDBACK_SOURCE               ; EXTCLK0            ; Untyped                        ;
-; BANDWIDTH                     ; 0                  ; Untyped                        ;
-; BANDWIDTH_TYPE                ; AUTO               ; Untyped                        ;
-; SPREAD_FREQUENCY              ; 0                  ; Untyped                        ;
-; DOWN_SPREAD                   ; 0                  ; Untyped                        ;
-; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                ; Untyped                        ;
-; SELF_RESET_ON_LOSS_LOCK       ; OFF                ; Untyped                        ;
-; CLK9_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK8_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK7_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK6_MULTIPLY_BY              ; 0                  ; Untyped                        ;
-; CLK5_MULTIPLY_BY              ; 1                  ; Untyped                        ;
-; CLK4_MULTIPLY_BY              ; 2                  ; Signed Integer                 ;
-; CLK3_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
-; CLK2_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
-; CLK1_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
-; CLK0_MULTIPLY_BY              ; 4                  ; Signed Integer                 ;
-; CLK9_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK8_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK7_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK6_DIVIDE_BY                ; 0                  ; Untyped                        ;
-; CLK5_DIVIDE_BY                ; 1                  ; Untyped                        ;
-; CLK4_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
-; CLK3_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
-; CLK2_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
-; CLK1_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
-; CLK0_DIVIDE_BY                ; 1                  ; Signed Integer                 ;
-; CLK9_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK8_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK7_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK6_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK5_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK4_PHASE_SHIFT              ; 11364              ; Untyped                        ;
-; CLK3_PHASE_SHIFT              ; 2210               ; Untyped                        ;
-; CLK2_PHASE_SHIFT              ; 3788               ; Untyped                        ;
-; CLK1_PHASE_SHIFT              ; 0                  ; Untyped                        ;
-; CLK0_PHASE_SHIFT              ; 5051               ; Untyped                        ;
-; CLK5_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK4_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK3_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK2_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK1_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK0_TIME_DELAY               ; 0                  ; Untyped                        ;
-; CLK9_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK8_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK7_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK6_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK5_DUTY_CYCLE               ; 50                 ; Untyped                        ;
-; CLK4_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK3_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK2_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK1_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK0_DUTY_CYCLE               ; 50                 ; Signed Integer                 ;
-; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                ; Untyped                        ;
-; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                ; Untyped                        ;
-; LOCK_WINDOW_UI                ;  0.05              ; Untyped                        ;
-; LOCK_WINDOW_UI_BITS           ; UNUSED             ; Untyped                        ;
-; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED             ; Untyped                        ;
-; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED             ; Untyped                        ;
-; DPA_MULTIPLY_BY               ; 0                  ; Untyped                        ;
-; DPA_DIVIDE_BY                 ; 1                  ; Untyped                        ;
-; DPA_DIVIDER                   ; 0                  ; Untyped                        ;
-; EXTCLK3_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK2_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK1_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK0_MULTIPLY_BY           ; 1                  ; Untyped                        ;
-; EXTCLK3_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK2_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK1_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK0_DIVIDE_BY             ; 1                  ; Untyped                        ;
-; EXTCLK3_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK2_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK1_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK0_PHASE_SHIFT           ; 0                  ; Untyped                        ;
-; EXTCLK3_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK2_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK1_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK0_TIME_DELAY            ; 0                  ; Untyped                        ;
-; EXTCLK3_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK2_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK1_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; EXTCLK0_DUTY_CYCLE            ; 50                 ; Untyped                        ;
-; VCO_MULTIPLY_BY               ; 0                  ; Untyped                        ;
-; VCO_DIVIDE_BY                 ; 0                  ; Untyped                        ;
-; SCLKOUT0_PHASE_SHIFT          ; 0                  ; Untyped                        ;
-; SCLKOUT1_PHASE_SHIFT          ; 0                  ; Untyped                        ;
-; VCO_MIN                       ; 0                  ; Untyped                        ;
-; VCO_MAX                       ; 0                  ; Untyped                        ;
-; VCO_CENTER                    ; 0                  ; Untyped                        ;
-; PFD_MIN                       ; 0                  ; Untyped                        ;
-; PFD_MAX                       ; 0                  ; Untyped                        ;
-; M_INITIAL                     ; 0                  ; Untyped                        ;
-; M                             ; 0                  ; Untyped                        ;
-; N                             ; 1                  ; Untyped                        ;
-; M2                            ; 1                  ; Untyped                        ;
-; N2                            ; 1                  ; Untyped                        ;
-; SS                            ; 1                  ; Untyped                        ;
-; C0_HIGH                       ; 0                  ; Untyped                        ;
-; C1_HIGH                       ; 0                  ; Untyped                        ;
-; C2_HIGH                       ; 0                  ; Untyped                        ;
-; C3_HIGH                       ; 0                  ; Untyped                        ;
-; C4_HIGH                       ; 0                  ; Untyped                        ;
-; C5_HIGH                       ; 0                  ; Untyped                        ;
-; C6_HIGH                       ; 0                  ; Untyped                        ;
-; C7_HIGH                       ; 0                  ; Untyped                        ;
-; C8_HIGH                       ; 0                  ; Untyped                        ;
-; C9_HIGH                       ; 0                  ; Untyped                        ;
-; C0_LOW                        ; 0                  ; Untyped                        ;
-; C1_LOW                        ; 0                  ; Untyped                        ;
-; C2_LOW                        ; 0                  ; Untyped                        ;
-; C3_LOW                        ; 0                  ; Untyped                        ;
-; C4_LOW                        ; 0                  ; Untyped                        ;
-; C5_LOW                        ; 0                  ; Untyped                        ;
-; C6_LOW                        ; 0                  ; Untyped                        ;
-; C7_LOW                        ; 0                  ; Untyped                        ;
-; C8_LOW                        ; 0                  ; Untyped                        ;
-; C9_LOW                        ; 0                  ; Untyped                        ;
-; C0_INITIAL                    ; 0                  ; Untyped                        ;
-; C1_INITIAL                    ; 0                  ; Untyped                        ;
-; C2_INITIAL                    ; 0                  ; Untyped                        ;
-; C3_INITIAL                    ; 0                  ; Untyped                        ;
-; C4_INITIAL                    ; 0                  ; Untyped                        ;
-; C5_INITIAL                    ; 0                  ; Untyped                        ;
-; C6_INITIAL                    ; 0                  ; Untyped                        ;
-; C7_INITIAL                    ; 0                  ; Untyped                        ;
-; C8_INITIAL                    ; 0                  ; Untyped                        ;
-; C9_INITIAL                    ; 0                  ; Untyped                        ;
-; C0_MODE                       ; BYPASS             ; Untyped                        ;
-; C1_MODE                       ; BYPASS             ; Untyped                        ;
-; C2_MODE                       ; BYPASS             ; Untyped                        ;
-; C3_MODE                       ; BYPASS             ; Untyped                        ;
-; C4_MODE                       ; BYPASS             ; Untyped                        ;
-; C5_MODE                       ; BYPASS             ; Untyped                        ;
-; C6_MODE                       ; BYPASS             ; Untyped                        ;
-; C7_MODE                       ; BYPASS             ; Untyped                        ;
-; C8_MODE                       ; BYPASS             ; Untyped                        ;
-; C9_MODE                       ; BYPASS             ; Untyped                        ;
-; C0_PH                         ; 0                  ; Untyped                        ;
-; C1_PH                         ; 0                  ; Untyped                        ;
-; C2_PH                         ; 0                  ; Untyped                        ;
-; C3_PH                         ; 0                  ; Untyped                        ;
-; C4_PH                         ; 0                  ; Untyped                        ;
-; C5_PH                         ; 0                  ; Untyped                        ;
-; C6_PH                         ; 0                  ; Untyped                        ;
-; C7_PH                         ; 0                  ; Untyped                        ;
-; C8_PH                         ; 0                  ; Untyped                        ;
-; C9_PH                         ; 0                  ; Untyped                        ;
-; L0_HIGH                       ; 1                  ; Untyped                        ;
-; L1_HIGH                       ; 1                  ; Untyped                        ;
-; G0_HIGH                       ; 1                  ; Untyped                        ;
-; G1_HIGH                       ; 1                  ; Untyped                        ;
-; G2_HIGH                       ; 1                  ; Untyped                        ;
-; G3_HIGH                       ; 1                  ; Untyped                        ;
-; E0_HIGH                       ; 1                  ; Untyped                        ;
-; E1_HIGH                       ; 1                  ; Untyped                        ;
-; E2_HIGH                       ; 1                  ; Untyped                        ;
-; E3_HIGH                       ; 1                  ; Untyped                        ;
-; L0_LOW                        ; 1                  ; Untyped                        ;
-; L1_LOW                        ; 1                  ; Untyped                        ;
-; G0_LOW                        ; 1                  ; Untyped                        ;
-; G1_LOW                        ; 1                  ; Untyped                        ;
-; G2_LOW                        ; 1                  ; Untyped                        ;
-; G3_LOW                        ; 1                  ; Untyped                        ;
-; E0_LOW                        ; 1                  ; Untyped                        ;
-; E1_LOW                        ; 1                  ; Untyped                        ;
-; E2_LOW                        ; 1                  ; Untyped                        ;
-; E3_LOW                        ; 1                  ; Untyped                        ;
-; L0_INITIAL                    ; 1                  ; Untyped                        ;
-; L1_INITIAL                    ; 1                  ; Untyped                        ;
-; G0_INITIAL                    ; 1                  ; Untyped                        ;
-; G1_INITIAL                    ; 1                  ; Untyped                        ;
-; G2_INITIAL                    ; 1                  ; Untyped                        ;
-; G3_INITIAL                    ; 1                  ; Untyped                        ;
-; E0_INITIAL                    ; 1                  ; Untyped                        ;
-; E1_INITIAL                    ; 1                  ; Untyped                        ;
-; E2_INITIAL                    ; 1                  ; Untyped                        ;
-; E3_INITIAL                    ; 1                  ; Untyped                        ;
-; L0_MODE                       ; BYPASS             ; Untyped                        ;
-; L1_MODE                       ; BYPASS             ; Untyped                        ;
-; G0_MODE                       ; BYPASS             ; Untyped                        ;
-; G1_MODE                       ; BYPASS             ; Untyped                        ;
-; G2_MODE                       ; BYPASS             ; Untyped                        ;
-; G3_MODE                       ; BYPASS             ; Untyped                        ;
-; E0_MODE                       ; BYPASS             ; Untyped                        ;
-; E1_MODE                       ; BYPASS             ; Untyped                        ;
-; E2_MODE                       ; BYPASS             ; Untyped                        ;
-; E3_MODE                       ; BYPASS             ; Untyped                        ;
-; L0_PH                         ; 0                  ; Untyped                        ;
-; L1_PH                         ; 0                  ; Untyped                        ;
-; G0_PH                         ; 0                  ; Untyped                        ;
-; G1_PH                         ; 0                  ; Untyped                        ;
-; G2_PH                         ; 0                  ; Untyped                        ;
-; G3_PH                         ; 0                  ; Untyped                        ;
-; E0_PH                         ; 0                  ; Untyped                        ;
-; E1_PH                         ; 0                  ; Untyped                        ;
-; E2_PH                         ; 0                  ; Untyped                        ;
-; E3_PH                         ; 0                  ; Untyped                        ;
-; M_PH                          ; 0                  ; Untyped                        ;
-; C1_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C2_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C3_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C4_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C5_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C6_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C7_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C8_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; C9_USE_CASC_IN                ; OFF                ; Untyped                        ;
-; CLK0_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK1_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK2_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK3_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK4_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK5_COUNTER                  ; G0                 ; Untyped                        ;
-; CLK6_COUNTER                  ; E0                 ; Untyped                        ;
-; CLK7_COUNTER                  ; E1                 ; Untyped                        ;
-; CLK8_COUNTER                  ; E2                 ; Untyped                        ;
-; CLK9_COUNTER                  ; E3                 ; Untyped                        ;
-; L0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; L1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G2_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; G3_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E0_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E1_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E2_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; E3_TIME_DELAY                 ; 0                  ; Untyped                        ;
-; M_TIME_DELAY                  ; 0                  ; Untyped                        ;
-; N_TIME_DELAY                  ; 0                  ; Untyped                        ;
-; EXTCLK3_COUNTER               ; E3                 ; Untyped                        ;
-; EXTCLK2_COUNTER               ; E2                 ; Untyped                        ;
-; EXTCLK1_COUNTER               ; E1                 ; Untyped                        ;
-; EXTCLK0_COUNTER               ; E0                 ; Untyped                        ;
-; ENABLE0_COUNTER               ; L0                 ; Untyped                        ;
-; ENABLE1_COUNTER               ; L0                 ; Untyped                        ;
-; CHARGE_PUMP_CURRENT           ; 2                  ; Untyped                        ;
-; LOOP_FILTER_R                 ;  1.000000          ; Untyped                        ;
-; LOOP_FILTER_C                 ; 5                  ; Untyped                        ;
-; CHARGE_PUMP_CURRENT_BITS      ; 9999               ; Untyped                        ;
-; LOOP_FILTER_R_BITS            ; 9999               ; Untyped                        ;
-; LOOP_FILTER_C_BITS            ; 9999               ; Untyped                        ;
-; VCO_POST_SCALE                ; 0                  ; Untyped                        ;
-; CLK2_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; CLK1_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; CLK0_OUTPUT_FREQUENCY         ; 0                  ; Untyped                        ;
-; INTENDED_DEVICE_FAMILY        ; Cyclone III        ; Untyped                        ;
-; PORT_CLKENA0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA2                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA3                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA4                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKENA5                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_EXTCLK0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK2                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_EXTCLK3                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKBAD0                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKBAD1                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK0                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK1                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK2                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK3                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK4                     ; PORT_USED          ; Untyped                        ;
-; PORT_CLK5                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK6                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK7                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK8                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLK9                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDATA                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDATAOUT              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANDONE                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_ACTIVECLOCK              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKLOSS                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_INCLK1                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_INCLK0                   ; PORT_USED          ; Untyped                        ;
-; PORT_FBIN                     ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PLLENA                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CLKSWITCH                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_ARESET                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PFDENA                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANCLK                  ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANACLR                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANREAD                 ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANWRITE                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_ENABLE0                  ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_ENABLE1                  ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_LOCKED                   ; PORT_UNUSED        ; Untyped                        ;
-; PORT_CONFIGUPDATE             ; PORT_UNUSED        ; Untyped                        ;
-; PORT_FBOUT                    ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_PHASEDONE                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASESTEP                ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASEUPDOWN              ; PORT_UNUSED        ; Untyped                        ;
-; PORT_SCANCLKENA               ; PORT_UNUSED        ; Untyped                        ;
-; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED        ; Untyped                        ;
-; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY  ; Untyped                        ;
-; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY  ; Untyped                        ;
-; M_TEST_SOURCE                 ; 5                  ; Untyped                        ;
-; C0_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C1_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C2_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C3_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C4_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C5_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C6_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C7_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C8_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; C9_TEST_SOURCE                ; 5                  ; Untyped                        ;
-; CBXI_PARAMETER                ; altpll_isv2        ; Untyped                        ;
-; VCO_FREQUENCY_CONTROL         ; AUTO               ; Untyped                        ;
-; VCO_PHASE_SHIFT_STEP          ; 0                  ; Untyped                        ;
-; WIDTH_CLOCK                   ; 5                  ; Signed Integer                 ;
-; WIDTH_PHASECOUNTERSELECT      ; 4                  ; Untyped                        ;
-; USING_FBMIMICBIDIR_PORT       ; OFF                ; Untyped                        ;
-; DEVICE_FAMILY                 ; Cyclone III        ; Untyped                        ;
-; SCAN_CHAIN_MIF_FILE           ; UNUSED             ; Untyped                        ;
-; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                ; Untyped                        ;
-; AUTO_CARRY_CHAINS             ; ON                 ; AUTO_CARRY                     ;
-; IGNORE_CARRY_BUFFERS          ; OFF                ; IGNORE_CARRY                   ;
-; AUTO_CASCADE_CHAINS           ; ON                 ; AUTO_CASCADE                   ;
-; IGNORE_CASCADE_BUFFERS        ; OFF                ; IGNORE_CASCADE                 ;
-+-------------------------------+--------------------+--------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component ;
-+-------------------------------+-------------------+---------------------------------+
-; Parameter Name                ; Value             ; Type                            ;
-+-------------------------------+-------------------+---------------------------------+
-; OPERATION_MODE                ; NORMAL            ; Untyped                         ;
-; PLL_TYPE                      ; AUTO              ; Untyped                         ;
-; QUALIFY_CONF_DONE             ; OFF               ; Untyped                         ;
-; COMPENSATE_CLOCK              ; CLK0              ; Untyped                         ;
-; SCAN_CHAIN                    ; LONG              ; Untyped                         ;
-; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                         ;
-; INCLK0_INPUT_FREQUENCY        ; 20833             ; Untyped                         ;
-; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                         ;
-; GATE_LOCK_SIGNAL              ; NO                ; Untyped                         ;
-; GATE_LOCK_COUNTER             ; 0                 ; Untyped                         ;
-; LOCK_HIGH                     ; 1                 ; Untyped                         ;
-; LOCK_LOW                      ; 1                 ; Untyped                         ;
-; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                         ;
-; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                         ;
-; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                         ;
-; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                         ;
-; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                         ;
-; SKIP_VCO                      ; OFF               ; Untyped                         ;
-; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                         ;
-; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                         ;
-; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                         ;
-; BANDWIDTH                     ; 0                 ; Untyped                         ;
-; BANDWIDTH_TYPE                ; AUTO              ; Untyped                         ;
-; SPREAD_FREQUENCY              ; 0                 ; Untyped                         ;
-; DOWN_SPREAD                   ; 0                 ; Untyped                         ;
-; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                         ;
-; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                         ;
-; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                         ;
-; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                         ;
-; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                         ;
-; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                         ;
-; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                         ;
-; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                         ;
-; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                         ;
-; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                         ;
-; CLK1_MULTIPLY_BY              ; 1                 ; Untyped                         ;
-; CLK0_MULTIPLY_BY              ; 2                 ; Untyped                         ;
-; CLK9_DIVIDE_BY                ; 0                 ; Untyped                         ;
-; CLK8_DIVIDE_BY                ; 0                 ; Untyped                         ;
-; CLK7_DIVIDE_BY                ; 0                 ; Untyped                         ;
-; CLK6_DIVIDE_BY                ; 0                 ; Untyped                         ;
-; CLK5_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK4_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK3_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK2_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK1_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK0_DIVIDE_BY                ; 1                 ; Untyped                         ;
-; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK1_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                         ;
-; CLK5_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK4_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK3_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK2_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK1_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK0_TIME_DELAY               ; 0                 ; Untyped                         ;
-; CLK9_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK8_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK7_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK6_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK5_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK4_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK3_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK2_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK1_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK0_DUTY_CYCLE               ; 50                ; Untyped                         ;
-; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                         ;
-; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                         ;
-; LOCK_WINDOW_UI                ;  0.05             ; Untyped                         ;
-; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                         ;
-; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                         ;
-; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                         ;
-; DPA_MULTIPLY_BY               ; 0                 ; Untyped                         ;
-; DPA_DIVIDE_BY                 ; 1                 ; Untyped                         ;
-; DPA_DIVIDER                   ; 0                 ; Untyped                         ;
-; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                         ;
-; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                         ;
-; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                         ;
-; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                         ;
-; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                         ;
-; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                         ;
-; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                         ;
-; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                         ;
-; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                         ;
-; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                         ;
-; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                         ;
-; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                         ;
-; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                         ;
-; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                         ;
-; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                         ;
-; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                         ;
-; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                         ;
-; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                         ;
-; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                         ;
-; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                         ;
-; VCO_MULTIPLY_BY               ; 0                 ; Untyped                         ;
-; VCO_DIVIDE_BY                 ; 0                 ; Untyped                         ;
-; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                         ;
-; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                         ;
-; VCO_MIN                       ; 0                 ; Untyped                         ;
-; VCO_MAX                       ; 0                 ; Untyped                         ;
-; VCO_CENTER                    ; 0                 ; Untyped                         ;
-; PFD_MIN                       ; 0                 ; Untyped                         ;
-; PFD_MAX                       ; 0                 ; Untyped                         ;
-; M_INITIAL                     ; 0                 ; Untyped                         ;
-; M                             ; 0                 ; Untyped                         ;
-; N                             ; 1                 ; Untyped                         ;
-; M2                            ; 1                 ; Untyped                         ;
-; N2                            ; 1                 ; Untyped                         ;
-; SS                            ; 1                 ; Untyped                         ;
-; C0_HIGH                       ; 0                 ; Untyped                         ;
-; C1_HIGH                       ; 0                 ; Untyped                         ;
-; C2_HIGH                       ; 0                 ; Untyped                         ;
-; C3_HIGH                       ; 0                 ; Untyped                         ;
-; C4_HIGH                       ; 0                 ; Untyped                         ;
-; C5_HIGH                       ; 0                 ; Untyped                         ;
-; C6_HIGH                       ; 0                 ; Untyped                         ;
-; C7_HIGH                       ; 0                 ; Untyped                         ;
-; C8_HIGH                       ; 0                 ; Untyped                         ;
-; C9_HIGH                       ; 0                 ; Untyped                         ;
-; C0_LOW                        ; 0                 ; Untyped                         ;
-; C1_LOW                        ; 0                 ; Untyped                         ;
-; C2_LOW                        ; 0                 ; Untyped                         ;
-; C3_LOW                        ; 0                 ; Untyped                         ;
-; C4_LOW                        ; 0                 ; Untyped                         ;
-; C5_LOW                        ; 0                 ; Untyped                         ;
-; C6_LOW                        ; 0                 ; Untyped                         ;
-; C7_LOW                        ; 0                 ; Untyped                         ;
-; C8_LOW                        ; 0                 ; Untyped                         ;
-; C9_LOW                        ; 0                 ; Untyped                         ;
-; C0_INITIAL                    ; 0                 ; Untyped                         ;
-; C1_INITIAL                    ; 0                 ; Untyped                         ;
-; C2_INITIAL                    ; 0                 ; Untyped                         ;
-; C3_INITIAL                    ; 0                 ; Untyped                         ;
-; C4_INITIAL                    ; 0                 ; Untyped                         ;
-; C5_INITIAL                    ; 0                 ; Untyped                         ;
-; C6_INITIAL                    ; 0                 ; Untyped                         ;
-; C7_INITIAL                    ; 0                 ; Untyped                         ;
-; C8_INITIAL                    ; 0                 ; Untyped                         ;
-; C9_INITIAL                    ; 0                 ; Untyped                         ;
-; C0_MODE                       ; BYPASS            ; Untyped                         ;
-; C1_MODE                       ; BYPASS            ; Untyped                         ;
-; C2_MODE                       ; BYPASS            ; Untyped                         ;
-; C3_MODE                       ; BYPASS            ; Untyped                         ;
-; C4_MODE                       ; BYPASS            ; Untyped                         ;
-; C5_MODE                       ; BYPASS            ; Untyped                         ;
-; C6_MODE                       ; BYPASS            ; Untyped                         ;
-; C7_MODE                       ; BYPASS            ; Untyped                         ;
-; C8_MODE                       ; BYPASS            ; Untyped                         ;
-; C9_MODE                       ; BYPASS            ; Untyped                         ;
-; C0_PH                         ; 0                 ; Untyped                         ;
-; C1_PH                         ; 0                 ; Untyped                         ;
-; C2_PH                         ; 0                 ; Untyped                         ;
-; C3_PH                         ; 0                 ; Untyped                         ;
-; C4_PH                         ; 0                 ; Untyped                         ;
-; C5_PH                         ; 0                 ; Untyped                         ;
-; C6_PH                         ; 0                 ; Untyped                         ;
-; C7_PH                         ; 0                 ; Untyped                         ;
-; C8_PH                         ; 0                 ; Untyped                         ;
-; C9_PH                         ; 0                 ; Untyped                         ;
-; L0_HIGH                       ; 1                 ; Untyped                         ;
-; L1_HIGH                       ; 1                 ; Untyped                         ;
-; G0_HIGH                       ; 1                 ; Untyped                         ;
-; G1_HIGH                       ; 1                 ; Untyped                         ;
-; G2_HIGH                       ; 1                 ; Untyped                         ;
-; G3_HIGH                       ; 1                 ; Untyped                         ;
-; E0_HIGH                       ; 1                 ; Untyped                         ;
-; E1_HIGH                       ; 1                 ; Untyped                         ;
-; E2_HIGH                       ; 1                 ; Untyped                         ;
-; E3_HIGH                       ; 1                 ; Untyped                         ;
-; L0_LOW                        ; 1                 ; Untyped                         ;
-; L1_LOW                        ; 1                 ; Untyped                         ;
-; G0_LOW                        ; 1                 ; Untyped                         ;
-; G1_LOW                        ; 1                 ; Untyped                         ;
-; G2_LOW                        ; 1                 ; Untyped                         ;
-; G3_LOW                        ; 1                 ; Untyped                         ;
-; E0_LOW                        ; 1                 ; Untyped                         ;
-; E1_LOW                        ; 1                 ; Untyped                         ;
-; E2_LOW                        ; 1                 ; Untyped                         ;
-; E3_LOW                        ; 1                 ; Untyped                         ;
-; L0_INITIAL                    ; 1                 ; Untyped                         ;
-; L1_INITIAL                    ; 1                 ; Untyped                         ;
-; G0_INITIAL                    ; 1                 ; Untyped                         ;
-; G1_INITIAL                    ; 1                 ; Untyped                         ;
-; G2_INITIAL                    ; 1                 ; Untyped                         ;
-; G3_INITIAL                    ; 1                 ; Untyped                         ;
-; E0_INITIAL                    ; 1                 ; Untyped                         ;
-; E1_INITIAL                    ; 1                 ; Untyped                         ;
-; E2_INITIAL                    ; 1                 ; Untyped                         ;
-; E3_INITIAL                    ; 1                 ; Untyped                         ;
-; L0_MODE                       ; BYPASS            ; Untyped                         ;
-; L1_MODE                       ; BYPASS            ; Untyped                         ;
-; G0_MODE                       ; BYPASS            ; Untyped                         ;
-; G1_MODE                       ; BYPASS            ; Untyped                         ;
-; G2_MODE                       ; BYPASS            ; Untyped                         ;
-; G3_MODE                       ; BYPASS            ; Untyped                         ;
-; E0_MODE                       ; BYPASS            ; Untyped                         ;
-; E1_MODE                       ; BYPASS            ; Untyped                         ;
-; E2_MODE                       ; BYPASS            ; Untyped                         ;
-; E3_MODE                       ; BYPASS            ; Untyped                         ;
-; L0_PH                         ; 0                 ; Untyped                         ;
-; L1_PH                         ; 0                 ; Untyped                         ;
-; G0_PH                         ; 0                 ; Untyped                         ;
-; G1_PH                         ; 0                 ; Untyped                         ;
-; G2_PH                         ; 0                 ; Untyped                         ;
-; G3_PH                         ; 0                 ; Untyped                         ;
-; E0_PH                         ; 0                 ; Untyped                         ;
-; E1_PH                         ; 0                 ; Untyped                         ;
-; E2_PH                         ; 0                 ; Untyped                         ;
-; E3_PH                         ; 0                 ; Untyped                         ;
-; M_PH                          ; 0                 ; Untyped                         ;
-; C1_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C2_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C3_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C4_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C5_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C6_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C7_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C8_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; C9_USE_CASC_IN                ; OFF               ; Untyped                         ;
-; CLK0_COUNTER                  ; G0                ; Untyped                         ;
-; CLK1_COUNTER                  ; G0                ; Untyped                         ;
-; CLK2_COUNTER                  ; G0                ; Untyped                         ;
-; CLK3_COUNTER                  ; G0                ; Untyped                         ;
-; CLK4_COUNTER                  ; G0                ; Untyped                         ;
-; CLK5_COUNTER                  ; G0                ; Untyped                         ;
-; CLK6_COUNTER                  ; E0                ; Untyped                         ;
-; CLK7_COUNTER                  ; E1                ; Untyped                         ;
-; CLK8_COUNTER                  ; E2                ; Untyped                         ;
-; CLK9_COUNTER                  ; E3                ; Untyped                         ;
-; L0_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; L1_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; G0_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; G1_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; G2_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; G3_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; E0_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; E1_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; E2_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; E3_TIME_DELAY                 ; 0                 ; Untyped                         ;
-; M_TIME_DELAY                  ; 0                 ; Untyped                         ;
-; N_TIME_DELAY                  ; 0                 ; Untyped                         ;
-; EXTCLK3_COUNTER               ; E3                ; Untyped                         ;
-; EXTCLK2_COUNTER               ; E2                ; Untyped                         ;
-; EXTCLK1_COUNTER               ; E1                ; Untyped                         ;
-; EXTCLK0_COUNTER               ; E0                ; Untyped                         ;
-; ENABLE0_COUNTER               ; L0                ; Untyped                         ;
-; ENABLE1_COUNTER               ; L0                ; Untyped                         ;
-; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                         ;
-; LOOP_FILTER_R                 ;  1.000000         ; Untyped                         ;
-; LOOP_FILTER_C                 ; 5                 ; Untyped                         ;
-; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                         ;
-; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                         ;
-; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                         ;
-; VCO_POST_SCALE                ; 0                 ; Untyped                         ;
-; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
-; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
-; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                         ;
-; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                         ;
-; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK0                     ; PORT_USED         ; Untyped                         ;
-; PORT_CLK1                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_SCANDATA                 ; PORT_USED         ; Untyped                         ;
-; PORT_SCANDATAOUT              ; PORT_USED         ; Untyped                         ;
-; PORT_SCANDONE                 ; PORT_USED         ; Untyped                         ;
-; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                         ;
-; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                         ;
-; PORT_INCLK0                   ; PORT_USED         ; Untyped                         ;
-; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                         ;
-; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                         ;
-; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                         ;
-; PORT_ARESET                   ; PORT_USED         ; Untyped                         ;
-; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                         ;
-; PORT_SCANCLK                  ; PORT_USED         ; Untyped                         ;
-; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                         ;
-; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                         ;
-; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                         ;
-; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_LOCKED                   ; PORT_USED         ; Untyped                         ;
-; PORT_CONFIGUPDATE             ; PORT_USED         ; Untyped                         ;
-; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                         ;
-; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                         ;
-; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                         ;
-; PORT_SCANCLKENA               ; PORT_USED         ; Untyped                         ;
-; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                         ;
-; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                         ;
-; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                         ;
-; M_TEST_SOURCE                 ; 5                 ; Untyped                         ;
-; C0_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C1_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C2_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C3_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C4_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C5_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C6_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C7_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C8_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; C9_TEST_SOURCE                ; 5                 ; Untyped                         ;
-; CBXI_PARAMETER                ; altpll_c6j2       ; Untyped                         ;
-; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                         ;
-; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                         ;
-; WIDTH_CLOCK                   ; 5                 ; Untyped                         ;
-; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                         ;
-; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                         ;
-; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                         ;
-; SCAN_CHAIN_MIF_FILE           ; altpll4.mif       ; Untyped                         ;
-; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                         ;
-; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                      ;
-; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                    ;
-; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                    ;
-; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                  ;
-+-------------------------------+-------------------+---------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ;
-+-----------------+-------+---------------------------------------------------------------------------------------------------------------+
-; Parameter Name  ; Value ; Type                                                                                                          ;
-+-----------------+-------+---------------------------------------------------------------------------------------------------------------+
-; WIDTH_BYTEENA_A ; 1     ; Untyped                                                                                                       ;
-; WIDTH_BYTEENA_B ; 1     ; Untyped                                                                                                       ;
-+-----------------+-------+---------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ;
-+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
-; Parameter Name                     ; Value                ; Type                                                                                               ;
-+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
-; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                                            ;
-; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                                                         ;
-; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                                                       ;
-; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                                                       ;
-; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                                                     ;
-; WIDTH_BYTEENA                      ; 1                    ; Untyped                                                                                            ;
-; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                                                                                            ;
-; WIDTH_A                            ; 1                    ; Untyped                                                                                            ;
-; WIDTHAD_A                          ; 8                    ; Untyped                                                                                            ;
-; NUMWORDS_A                         ; 144                  ; Untyped                                                                                            ;
-; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                                            ;
-; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
-; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
-; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                                            ;
-; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                                            ;
-; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                                            ;
-; WIDTH_B                            ; 1                    ; Untyped                                                                                            ;
-; WIDTHAD_B                          ; 1                    ; Untyped                                                                                            ;
-; NUMWORDS_B                         ; 1                    ; Untyped                                                                                            ;
-; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                                            ;
-; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                                            ;
-; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                                            ;
-; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                                            ;
-; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                                            ;
-; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                                            ;
-; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                                            ;
-; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                            ;
-; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
-; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
-; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                                            ;
-; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                                            ;
-; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                                            ;
-; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                                            ;
-; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                                            ;
-; BYTE_SIZE                          ; 8                    ; Untyped                                                                                            ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                                                                                            ;
-; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                            ;
-; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                                                                                            ;
-; INIT_FILE                          ; UNUSED               ; Untyped                                                                                            ;
-; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                                            ;
-; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                                            ;
-; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                                            ;
-; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                                            ;
-; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                                            ;
-; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                                            ;
-; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                                                                                            ;
-; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                                                                                            ;
-; ENABLE_ECC                         ; FALSE                ; Untyped                                                                                            ;
-; DEVICE_FAMILY                      ; Cyclone III          ; Untyped                                                                                            ;
-; CBXI_PARAMETER                     ; altsyncram_46r       ; Untyped                                                                                            ;
-+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                  ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 9           ; Untyped                                                                                                               ;
-; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                               ;
-; LPM_DIRECTION          ; DEFAULT     ; Untyped                                                                                                               ;
-; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                               ;
-; LPM_PIPELINE           ; 0           ; Untyped                                                                                                               ;
-; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                               ;
-; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                               ;
-; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                                                                                               ;
-; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                               ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                               ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                    ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                               ;
-; USE_WYS                ; OFF         ; Untyped                                                                                                               ;
-; STYLE                  ; FAST        ; Untyped                                                                                                               ;
-; CBXI_PARAMETER         ; add_sub_hpa ; Untyped                                                                                                               ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                        ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                  ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 8           ; Untyped                                                                                                               ;
-; LPM_REPRESENTATION     ; SIGNED      ; Untyped                                                                                                               ;
-; LPM_DIRECTION          ; DEFAULT     ; Untyped                                                                                                               ;
-; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                               ;
-; LPM_PIPELINE           ; 0           ; Untyped                                                                                                               ;
-; MAXIMIZE_SPEED         ; 5           ; Untyped                                                                                                               ;
-; REGISTERED_AT_END      ; 0           ; Untyped                                                                                                               ;
-; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                                                                                                               ;
-; USE_CS_BUFFERS         ; 1           ; Untyped                                                                                                               ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                               ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                    ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                               ;
-; USE_WYS                ; OFF         ; Untyped                                                                                                               ;
-; STYLE                  ; FAST        ; Untyped                                                                                                               ;
-; CBXI_PARAMETER         ; add_sub_k8a ; Untyped                                                                                                               ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                            ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                          ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                          ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                        ;
-+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; lpm_width              ; 8           ; Untyped                                                                                                            ;
-; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                                                                                            ;
-; LPM_PIPELINE           ; 0           ; Untyped                                                                                                            ;
-; CHAIN_SIZE             ; 8           ; Untyped                                                                                                            ;
-; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                                                                                            ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
-; CASCADE_CHAIN          ; MANUAL      ; Untyped                                                                                                            ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
-; CASCADE_CHAIN_LENGTH   ; 2           ; CASCADE_CHAIN_LENGTH                                                                                               ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
-; CBXI_PARAMETER         ; cmpr_tnd    ; Untyped                                                                                                            ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
-; LPM_WIDTH              ; 8           ; Untyped                                                                                                            ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                            ;
-; LPM_MODULUS            ; 144         ; Untyped                                                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
-; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                            ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
-; LPM_WIDTH              ; 8           ; Untyped                                                                                                             ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
-; LPM_MODULUS            ; 144         ; Untyped                                                                                                             ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
-; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                             ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
-; LPM_WIDTH              ; 6           ; Untyped                                                                                                             ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
-; LPM_MODULUS            ; 0           ; Untyped                                                                                                             ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
-; CBXI_PARAMETER         ; cntr_qij    ; Untyped                                                                                                             ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
-; LPM_WIDTH              ; 5           ; Untyped                                                                                                             ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
-; LPM_MODULUS            ; 0           ; Untyped                                                                                                             ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
-; CBXI_PARAMETER         ; cntr_pij    ; Untyped                                                                                                             ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                          ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                        ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                        ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                      ;
-; LPM_WIDTH              ; 8           ; Untyped                                                                                                             ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                             ;
-; LPM_MODULUS            ; 144         ; Untyped                                                                                                             ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                             ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                             ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                             ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                             ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                  ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                  ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                             ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                             ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                             ;
-; CBXI_PARAMETER         ; cntr_30l    ; Untyped                                                                                                             ;
-+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
-; LPM_WIDTH              ; 8           ; Untyped                                                                                                            ;
-; LPM_DIRECTION          ; UP          ; Untyped                                                                                                            ;
-; LPM_MODULUS            ; 0           ; Untyped                                                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
-; CBXI_PARAMETER         ; cntr_9cj    ; Untyped                                                                                                            ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                               ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                         ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                       ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                       ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                     ;
-; LPM_WIDTH              ; 5           ; Untyped                                                                                                            ;
-; LPM_DIRECTION          ; DOWN        ; Untyped                                                                                                            ;
-; LPM_MODULUS            ; 0           ; Untyped                                                                                                            ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                                                                            ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                                                                            ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                            ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                                                                            ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                                                                                 ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                                                                                 ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                                                                            ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                                                                            ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                                                                            ;
-; CBXI_PARAMETER         ; cntr_pij    ; Untyped                                                                                                            ;
-+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 ;
-+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                                                                                 ;
-+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
-; LPM_WIDTH              ; 3           ; Untyped                                                                                                              ;
-; LPM_DECODES            ; 5           ; Untyped                                                                                                              ;
-; LPM_PIPELINE           ; 0           ; Untyped                                                                                                              ;
-; CASCADE_CHAIN          ; MANUAL      ; Untyped                                                                                                              ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                                                                              ;
-; CBXI_PARAMETER         ; decode_2af  ; Untyped                                                                                                              ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                                                                           ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                                                                         ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                                                                         ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                                                                                       ;
-+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component ;
-+------------------------+-------------+---------------------------------------------+
-; Parameter Name         ; Value       ; Type                                        ;
-+------------------------+-------------+---------------------------------------------+
-; LPM_WIDTH              ; 32          ; Signed Integer                              ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                     ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                     ;
-; LPM_FFTYPE             ; DFF         ; Untyped                                     ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                     ;
-; CBXI_PARAMETER         ; NOTHING     ; Untyped                                     ;
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                  ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
-+------------------------+-------------+---------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; Parameter Name ; Value ; Type                                                                                               ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-; LPM_WIDTH      ; 8     ; Signed Integer                                                                                     ;
-+----------------+-------+----------------------------------------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+----------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component ;
-+------------------------+-------------+-------------------------------------------------------------+
-; Parameter Name         ; Value       ; Type                                                        ;
-+------------------------+-------------+-------------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                  ;
-; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                                ;
-; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                                ;
-; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                              ;
-; LPM_WIDTH              ; 18          ; Signed Integer                                              ;
-; LPM_DIRECTION          ; UP          ; Untyped                                                     ;
-; LPM_MODULUS            ; 0           ; Untyped                                                     ;
-; LPM_AVALUE             ; UNUSED      ; Untyped                                                     ;
-; LPM_SVALUE             ; UNUSED      ; Untyped                                                     ;
-; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                     ;
-; DEVICE_FAMILY          ; Cyclone III ; Untyped                                                     ;
-; CARRY_CHAIN            ; MANUAL      ; Untyped                                                     ;
-; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                          ;
-; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                          ;
-; CARRY_CNT_EN           ; SMART       ; Untyped                                                     ;
-; LABWIDE_SCLR           ; ON          ; Untyped                                                     ;
-; USE_NEW_VERSION        ; TRUE        ; Untyped                                                     ;
-; CBXI_PARAMETER         ; cntr_mph    ; Untyped                                                     ;
-+------------------------+-------------+-------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component ;
-+------------------------+--------------+-----------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                      ;
-+------------------------+--------------+-----------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
-; WIDTH                  ; 1            ; Signed Integer                                            ;
-; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
-; OE_REG                 ; UNUSED       ; Untyped                                                   ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
-; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
-+------------------------+--------------+-----------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component ;
-+------------------------+--------------+-----------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                      ;
-+------------------------+--------------+-----------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
-; WIDTH                  ; 1            ; Signed Integer                                            ;
-; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
-; OE_REG                 ; UNUSED       ; Untyped                                                   ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
-; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
-+------------------------+--------------+-----------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component ;
-+------------------------+--------------+-----------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                      ;
-+------------------------+--------------+-----------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
-; WIDTH                  ; 1            ; Signed Integer                                            ;
-; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
-; OE_REG                 ; UNUSED       ; Untyped                                                   ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
-; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
-+------------------------+--------------+-----------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component ;
-+------------------------+--------------+-----------------------------------------------------------+
-; Parameter Name         ; Value        ; Type                                                      ;
-+------------------------+--------------+-----------------------------------------------------------+
-; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                                ;
-; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                              ;
-; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                              ;
-; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                            ;
-; WIDTH                  ; 1            ; Signed Integer                                            ;
-; POWER_UP_HIGH          ; OFF          ; Untyped                                                   ;
-; OE_REG                 ; UNUSED       ; Untyped                                                   ;
-; extend_oe_disable      ; UNUSED       ; Untyped                                                   ;
-; INTENDED_DEVICE_FAMILY ; Cyclone III  ; Untyped                                                   ;
-; DEVICE_FAMILY          ; Cyclone III  ; Untyped                                                   ;
-; CBXI_PARAMETER         ; ddio_out_31f ; Untyped                                                   ;
-+------------------------+--------------+-----------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name                                 ; Value       ; Type                                                                ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                      ;
-; LPM_WIDTHA                                     ; 12          ; Untyped                                                             ;
-; LPM_WIDTHB                                     ; 6           ; Untyped                                                             ;
-; LPM_WIDTHP                                     ; 18          ; Untyped                                                             ;
-; LPM_WIDTHR                                     ; 18          ; Untyped                                                             ;
-; LPM_WIDTHS                                     ; 1           ; Untyped                                                             ;
-; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                             ;
-; LPM_PIPELINE                                   ; 0           ; Untyped                                                             ;
-; LATENCY                                        ; 0           ; Untyped                                                             ;
-; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
-; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
-; USE_EAB                                        ; OFF         ; Untyped                                                             ;
-; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                             ;
-; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                             ;
-; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                             ;
-; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                 ;
-; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                             ;
-; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                             ;
-; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                             ;
-; CBXI_PARAMETER                                 ; mult_cat    ; Untyped                                                             ;
-; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
-; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
-; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                             ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ;
-+------------------------------------------------+-------------+--------------------------------------------------------------------+
-; Parameter Name                                 ; Value       ; Type                                                               ;
-+------------------------------------------------+-------------+--------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                         ;
-; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                       ;
-; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                       ;
-; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                     ;
-; LPM_WIDTHA                                     ; 12          ; Untyped                                                            ;
-; LPM_WIDTHB                                     ; 5           ; Untyped                                                            ;
-; LPM_WIDTHP                                     ; 17          ; Untyped                                                            ;
-; LPM_WIDTHR                                     ; 17          ; Untyped                                                            ;
-; LPM_WIDTHS                                     ; 1           ; Untyped                                                            ;
-; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                            ;
-; LPM_PIPELINE                                   ; 0           ; Untyped                                                            ;
-; LATENCY                                        ; 0           ; Untyped                                                            ;
-; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                            ;
-; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                            ;
-; USE_EAB                                        ; OFF         ; Untyped                                                            ;
-; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                            ;
-; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                            ;
-; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                            ;
-; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                ;
-; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                            ;
-; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                            ;
-; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                            ;
-; CBXI_PARAMETER                                 ; mult_aat    ; Untyped                                                            ;
-; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                            ;
-; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                            ;
-; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                            ;
-+------------------------------------------------+-------------+--------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-; Parameter Name                                 ; Value       ; Type                                                                ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                          ;
-; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                        ;
-; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                        ;
-; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                      ;
-; LPM_WIDTHA                                     ; 12          ; Untyped                                                             ;
-; LPM_WIDTHB                                     ; 5           ; Untyped                                                             ;
-; LPM_WIDTHP                                     ; 17          ; Untyped                                                             ;
-; LPM_WIDTHR                                     ; 17          ; Untyped                                                             ;
-; LPM_WIDTHS                                     ; 1           ; Untyped                                                             ;
-; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                             ;
-; LPM_PIPELINE                                   ; 0           ; Untyped                                                             ;
-; LATENCY                                        ; 0           ; Untyped                                                             ;
-; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
-; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                             ;
-; USE_EAB                                        ; OFF         ; Untyped                                                             ;
-; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                             ;
-; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                             ;
-; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                             ;
-; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                                 ;
-; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                             ;
-; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                             ;
-; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                             ;
-; CBXI_PARAMETER                                 ; mult_aat    ; Untyped                                                             ;
-; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
-; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                             ;
-; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                             ;
-+------------------------------------------------+-------------+---------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------+
-; altpll Parameter Settings by Entity Instance                           ;
-+-------------------------------+----------------------------------------+
-; Name                          ; Value                                  ;
-+-------------------------------+----------------------------------------+
-; Number of entity instances    ; 4                                      ;
-; Entity Instance               ; altpll1:inst|altpll:altpll_component   ;
-;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
-;     -- PLL_TYPE               ; AUTO                                   ;
-;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
-;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
-;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
-;     -- VCO_MULTIPLY_BY        ; 0                                      ;
-;     -- VCO_DIVIDE_BY          ; 0                                      ;
-; Entity Instance               ; altpll3:inst13|altpll:altpll_component ;
-;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
-;     -- PLL_TYPE               ; AUTO                                   ;
-;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
-;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
-;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
-;     -- VCO_MULTIPLY_BY        ; 0                                      ;
-;     -- VCO_DIVIDE_BY          ; 0                                      ;
-; Entity Instance               ; altpll2:inst12|altpll:altpll_component ;
-;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                     ;
-;     -- PLL_TYPE               ; AUTO                                   ;
-;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
-;     -- INCLK0_INPUT_FREQUENCY ; 30303                                  ;
-;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
-;     -- VCO_MULTIPLY_BY        ; 0                                      ;
-;     -- VCO_DIVIDE_BY          ; 0                                      ;
-; Entity Instance               ; altpll4:inst22|altpll:altpll_component ;
-;     -- OPERATION_MODE         ; NORMAL                                 ;
-;     -- PLL_TYPE               ; AUTO                                   ;
-;     -- PRIMARY_CLOCK          ; INCLK0                                 ;
-;     -- INCLK0_INPUT_FREQUENCY ; 20833                                  ;
-;     -- INCLK1_INPUT_FREQUENCY ; 0                                      ;
-;     -- VCO_MULTIPLY_BY        ; 0                                      ;
-;     -- VCO_DIVIDE_BY          ; 0                                      ;
-+-------------------------------+----------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------+
-; lpm_shiftreg Parameter Settings by Entity Instance                                                           ;
-+----------------------------+---------------------------------------------------------------------------------+
-; Name                       ; Value                                                                           ;
-+----------------------------+---------------------------------------------------------------------------------+
-; Number of entity instances ; 11                                                                              ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ;
-;     -- LPM_WIDTH           ; 5                                                                               ;
-;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ;
-;     -- LPM_WIDTH           ; 5                                                                               ;
-;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ;
-;     -- LPM_WIDTH           ; 5                                                                               ;
-;     -- LPM_DIRECTION       ; RIGHT                                                                           ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component    ;
-;     -- LPM_WIDTH           ; 16                                                                              ;
-;     -- LPM_DIRECTION       ; LEFT                                                                            ;
-+----------------------------+---------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; dcfifo Parameter Settings by Entity Instance                                                  ;
-+----------------------------+------------------------------------------------------------------+
-; Name                       ; Value                                                            ;
-+----------------------------+------------------------------------------------------------------+
-; Number of entity instances ; 1                                                                ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ;
-;     -- FIFO Type           ; Dual Clock                                                       ;
-;     -- LPM_WIDTH           ; 128                                                              ;
-;     -- LPM_NUMWORDS        ; 512                                                              ;
-;     -- LPM_SHOWAHEAD       ; OFF                                                              ;
-;     -- USE_EAB             ; ON                                                               ;
-+----------------------------+------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; scfifo Parameter Settings by Entity Instance                                                  ;
-+----------------------------+------------------------------------------------------------------+
-; Name                       ; Value                                                            ;
-+----------------------------+------------------------------------------------------------------+
-; Number of entity instances ; 1                                                                ;
-; Entity Instance            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ;
-;     -- FIFO Type           ; Single Clock                                                     ;
-;     -- lpm_width           ; 128                                                              ;
-;     -- LPM_NUMWORDS        ; 128                                                              ;
-;     -- LPM_SHOWAHEAD       ; ON                                                               ;
-;     -- USE_EAB             ; ON                                                               ;
-+----------------------------+------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; altsyncram Parameter Settings by Entity Instance                                                                                                              ;
-+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
-; Name                                      ; Value                                                                                                             ;
-+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
-; Number of entity instances                ; 10                                                                                                                ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component                                  ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component                                ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component                                 ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 6                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component                                      ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 16                                                                                                                ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 16                                                                                                                ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component                                    ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 16                                                                                                                ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 16                                                                                                                ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component                                     ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 16                                                                                                                ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 3                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 16                                                                                                                ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component                                   ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component                                   ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component                                     ;
-;     -- OPERATION_MODE                     ; BIDIR_DUAL_PORT                                                                                                   ;
-;     -- WIDTH_A                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 256                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; CLOCK0                                                                                                            ;
-;     -- WIDTH_B                            ; 8                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 256                                                                                                               ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-; Entity Instance                           ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ;
-;     -- OPERATION_MODE                     ; SINGLE_PORT                                                                                                       ;
-;     -- WIDTH_A                            ; 1                                                                                                                 ;
-;     -- NUMWORDS_A                         ; 144                                                                                                               ;
-;     -- OUTDATA_REG_A                      ; UNREGISTERED                                                                                                      ;
-;     -- WIDTH_B                            ; 1                                                                                                                 ;
-;     -- NUMWORDS_B                         ; 1                                                                                                                 ;
-;     -- ADDRESS_REG_B                      ; CLOCK1                                                                                                            ;
-;     -- OUTDATA_REG_B                      ; UNREGISTERED                                                                                                      ;
-;     -- RAM_BLOCK_TYPE                     ; AUTO                                                                                                              ;
-;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                                                                                         ;
-+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; lpm_mult Parameter Settings by Entity Instance                                                                            ;
-+---------------------------------------+-----------------------------------------------------------------------------------+
-; Name                                  ; Value                                                                             ;
-+---------------------------------------+-----------------------------------------------------------------------------------+
-; Number of entity instances            ; 3                                                                                 ;
-; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ;
-;     -- LPM_WIDTHA                     ; 12                                                                                ;
-;     -- LPM_WIDTHB                     ; 6                                                                                 ;
-;     -- LPM_WIDTHP                     ; 18                                                                                ;
-;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
-;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
-;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
-;     -- USE_EAB                        ; OFF                                                                               ;
-;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
-;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
-;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
-; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6  ;
-;     -- LPM_WIDTHA                     ; 12                                                                                ;
-;     -- LPM_WIDTHB                     ; 5                                                                                 ;
-;     -- LPM_WIDTHP                     ; 17                                                                                ;
-;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
-;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
-;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
-;     -- USE_EAB                        ; OFF                                                                               ;
-;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
-;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
-;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
-; Entity Instance                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ;
-;     -- LPM_WIDTHA                     ; 12                                                                                ;
-;     -- LPM_WIDTHB                     ; 5                                                                                 ;
-;     -- LPM_WIDTHP                     ; 17                                                                                ;
-;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                          ;
-;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                ;
-;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                ;
-;     -- USE_EAB                        ; OFF                                                                               ;
-;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                              ;
-;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                ;
-;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                ;
-+---------------------------------------+-----------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"    ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port        ; Type   ; Severity ; Details                                                                             ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; seln        ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; bc2         ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; a9n         ; Input  ; Info     ; Stuck at GND                                                                        ;
-; a8          ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; da_en       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; io_a_in     ; Input  ; Info     ; Stuck at GND                                                                        ;
-; io_a_out[2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; io_a_en     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; io_b_en     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"  ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; Port     ; Type   ; Severity ; Details                                                                             ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; data_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; gpip_out ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; gpip_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; iein     ; Input  ; Info     ; Stuck at GND                                                                        ;
-; ieon     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; tai      ; Input  ; Info     ; Stuck at GND                                                                        ;
-; tao      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; tbo      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; tco      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; so_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rrn      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; trn      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" ;
-+---------+--------+----------+------------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                                  ;
-+---------+--------+----------+------------------------------------------------------------------------------------------+
-; cs2n    ; Input  ; Info     ; Stuck at GND                                                                             ;
-; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.      ;
-; ctsn    ; Input  ; Info     ; Stuck at GND                                                                             ;
-; dcdn    ; Input  ; Info     ; Stuck at GND                                                                             ;
-; rtsn    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.      ;
-+---------+--------+----------+------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" ;
-+---------+--------+----------+----------------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                                      ;
-+---------+--------+----------+----------------------------------------------------------------------------------------------+
-; cs1     ; Input  ; Info     ; Stuck at VCC                                                                                 ;
-; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.          ;
-; ctsn    ; Input  ; Info     ; Stuck at GND                                                                                 ;
-; dcdn    ; Input  ; Info     ; Stuck at GND                                                                                 ;
-; rtsn    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.          ;
-+---------+--------+----------+----------------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
-; Port       ; Type   ; Severity ; Details                                                                                                     ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
-; icr_out[7] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
-; icr_out[5] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"    ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; Port     ; Type   ; Severity ; Details                                                                             ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; data_en  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; csn      ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; eopn     ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; ready    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; ack_inn  ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; ack_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; atn_inn  ; Input  ; Info     ; Stuck at VCC                                                                        ;
-; atn_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; req_outn ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; req_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; ion_out  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; io_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; cdn_out  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; cd_en    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; msg_outn ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; msg_en   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"  ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; Port    ; Type   ; Severity ; Details                                                                             ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-; data_en ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; dden    ; Input  ; Info     ; Stuck at GND                                                                        ;
-+---------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II Analysis & Synthesis
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Wed Dec 15 02:20:37 2010
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_control.vhd
-    Info: Found design unit 1: WF5380_CONTROL-BEHAVIOUR
-    Info: Found entity 1: WF5380_CONTROL
-Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_pkg.vhd
-    Info: Found design unit 1: WF5380_PKG
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_registers.vhd
-    Info: Found design unit 1: WF5380_REGISTERS-BEHAVIOUR
-    Info: Found entity 1: WF5380_REGISTERS
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_soc_top.vhd
-    Info: Found design unit 1: WF5380_TOP_SOC-STRUCTURE
-    Info: Found entity 1: WF5380_TOP_SOC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_top.vhd
-    Info: Found design unit 1: WF5380_TOP-STRUCTURE
-    Info: Found entity 1: WF5380_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_am_detector.vhd
-    Info: Found design unit 1: WF1772IP_AM_DETECTOR-BEHAVIOR
-    Info: Found entity 1: WF1772IP_AM_DETECTOR
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo0.vhd
-    Info: Found design unit 1: dcfifo0-SYN
-    Info: Found entity 1: dcfifo0
-Info: Found 1 design units, including 1 entities, in source file video/ddr_ctr.tdf
-    Info: Found entity 1: DDR_CTR
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri0.vhd
-    Info: Found design unit 1: lpm_bustri0-SYN
-    Info: Found entity 1: lpm_bustri0
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_control.vhd
-    Info: Found design unit 1: WF1772IP_CONTROL-BEHAVIOR
-    Info: Found entity 1: WF1772IP_CONTROL
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_crc_logic.vhd
-    Info: Found design unit 1: WF1772IP_CRC_LOGIC-BEHAVIOR
-    Info: Found entity 1: WF1772IP_CRC_LOGIC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_digital_pll.vhd
-    Info: Found design unit 1: WF1772IP_DIGITAL_PLL-BEHAVIOR
-    Info: Found entity 1: WF1772IP_DIGITAL_PLL
-Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_pkg.vhd
-    Info: Found design unit 1: WF1772IP_PKG
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_registers.vhd
-    Info: Found design unit 1: WF1772IP_REGISTERS-BEHAVIOR
-    Info: Found entity 1: WF1772IP_REGISTERS
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top.vhd
-    Info: Found design unit 1: WF1772IP_TOP-STRUCTURE
-    Info: Found entity 1: WF1772IP_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top_soc.vhd
-    Info: Found design unit 1: WF1772IP_TOP_SOC-STRUCTURE
-    Info: Found entity 1: WF1772IP_TOP_SOC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_transceiver.vhd
-    Info: Found design unit 1: WF1772IP_TRANSCEIVER-BEHAVIOR
-    Info: Found entity 1: WF1772IP_TRANSCEIVER
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri5.vhd
-    Info: Found design unit 1: lpm_bustri5-SYN
-    Info: Found entity 1: lpm_bustri5
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_ctrl_status.vhd
-    Info: Found design unit 1: WF6850IP_CTRL_STATUS-BEHAVIOR
-    Info: Found entity 1: WF6850IP_CTRL_STATUS
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri7.vhd
-    Info: Found design unit 1: lpm_bustri7-SYN
-    Info: Found entity 1: lpm_bustri7
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_receive.vhd
-    Info: Found design unit 1: WF6850IP_RECEIVE-BEHAVIOR
-    Info: Found entity 1: WF6850IP_RECEIVE
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top.vhd
-    Info: Found design unit 1: WF6850IP_TOP-STRUCTURE
-    Info: Found entity 1: WF6850IP_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top_soc.vhd
-    Info: Found design unit 1: WF6850IP_TOP_SOC-STRUCTURE
-    Info: Found entity 1: WF6850IP_TOP_SOC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_transmit.vhd
-    Info: Found design unit 1: WF6850IP_TRANSMIT-BEHAVIOR
-    Info: Found entity 1: WF6850IP_TRANSMIT
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_gpio.vhd
-    Info: Found design unit 1: WF68901IP_GPIO-BEHAVIOR
-    Info: Found entity 1: WF68901IP_GPIO
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_interrupts.vhd
-    Info: Found design unit 1: WF68901IP_INTERRUPTS-BEHAVIOR
-    Info: Found entity 1: WF68901IP_INTERRUPTS
-Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_pkg.vhd
-    Info: Found design unit 1: WF68901IP_PKG
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_timers.vhd
-    Info: Found design unit 1: WF68901IP_TIMERS-BEHAVIOR
-    Info: Found entity 1: WF68901IP_TIMERS
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top.vhd
-    Info: Found design unit 1: WF68901IP_TOP-STRUCTURE
-    Info: Found entity 1: WF68901IP_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top_soc.vhd
-    Info: Found design unit 1: WF68901IP_TOP_SOC-STRUCTURE
-    Info: Found entity 1: WF68901IP_TOP_SOC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_ctrl.vhd
-    Info: Found design unit 1: WF68901IP_USART_CTRL-BEHAVIOR
-    Info: Found entity 1: WF68901IP_USART_CTRL
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_rx.vhd
-    Info: Found design unit 1: WF68901IP_USART_RX-BEHAVIOR
-    Info: Found entity 1: WF68901IP_USART_RX
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_top.vhd
-    Info: Found design unit 1: WF68901IP_USART_TOP-STRUCTURE
-    Info: Found entity 1: WF68901IP_USART_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_tx.vhd
-    Info: Found design unit 1: WF68901IP_USART_TX-BEHAVIOR
-    Info: Found entity 1: WF68901IP_USART_TX
-Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_pkg.vhd
-    Info: Found design unit 1: WF2149IP_PKG
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top.vhd
-    Info: Found design unit 1: WF2149IP_TOP-STRUCTURE
-    Info: Found entity 1: WF2149IP_TOP
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top_soc.vhd
-    Info: Found design unit 1: WF2149IP_TOP_SOC-STRUCTURE
-    Info: Found entity 1: WF2149IP_TOP_SOC
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_wave.vhd
-    Info: Found design unit 1: WF2149IP_WAVE-BEHAVIOR
-    Info: Found entity 1: WF2149IP_WAVE
-Info: Found 2 design units, including 1 entities, in source file lpm_latch0.vhd
-    Info: Found design unit 1: lpm_latch0-SYN
-    Info: Found entity 1: lpm_latch0
-Info: Found 2 design units, including 1 entities, in source file altpll1.vhd
-    Info: Found design unit 1: altpll1-SYN
-    Info: Found entity 1: altpll1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_fifodz.vhd
-    Info: Found design unit 1: lpm_fifodz-SYN
-    Info: Found entity 1: lpm_fifoDZ
-Info: Found 2 design units, including 1 entities, in source file altpll2.vhd
-    Info: Found design unit 1: altpll2-SYN
-    Info: Found entity 1: altpll2
-Info: Found 2 design units, including 1 entities, in source file altpll3.vhd
-    Info: Found design unit 1: altpll3-SYN
-    Info: Found entity 1: altpll3
-Info: Found 2 design units, including 1 entities, in source file video/altdpram0.vhd
-    Info: Found design unit 1: altdpram0-SYN
-    Info: Found entity 1: altdpram0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz2.vhd
-    Info: Found design unit 1: lpm_muxdz2-SYN
-    Info: Found entity 1: lpm_muxDZ2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz.vhd
-    Info: Found design unit 1: lpm_muxdz-SYN
-    Info: Found entity 1: lpm_muxDZ
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri3.vhd
-    Info: Found design unit 1: lpm_bustri3-SYN
-    Info: Found entity 1: lpm_bustri3
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff0.vhd
-    Info: Found design unit 1: lpm_ff0-SYN
-    Info: Found entity 1: lpm_ff0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff1.vhd
-    Info: Found design unit 1: lpm_ff1-SYN
-    Info: Found entity 1: lpm_ff1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff3.vhd
-    Info: Found design unit 1: lpm_ff3-SYN
-    Info: Found entity 1: lpm_ff3
-Info: Found 1 design units, including 1 entities, in source file video/video_mod_mux_clutctr.tdf
-    Info: Found entity 1: VIDEO_MOD_MUX_CLUTCTR
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff2.vhd
-    Info: Found design unit 1: lpm_ff2-SYN
-    Info: Found entity 1: lpm_ff2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_fifo_dc0.vhd
-    Info: Found design unit 1: lpm_fifo_dc0-SYN
-    Info: Found entity 1: lpm_fifo_dc0
-Info: Found 1 design units, including 1 entities, in source file video/video.bdf
-    Info: Found entity 1: Video
-Info: Found 1 design units, including 1 entities, in source file firebee1.bdf
-    Info: Found entity 1: firebee1
-Info: Found 2 design units, including 1 entities, in source file altpll0.vhd
-    Info: Found design unit 1: altpll0-SYN
-    Info: Found entity 1: altpll0
-Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd
-    Info: Found design unit 1: lpm_counter0-SYN
-    Info: Found entity 1: lpm_counter0
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf.vhd
-    Info: Found design unit 1: FalconIO_SDCard_IDE_CF-FalconIO_SDCard_IDE_CF_architecture
-    Info: Found entity 1: FalconIO_SDCard_IDE_CF
-Info: Found 2 design units, including 1 entities, in source file dsp/dsp.vhd
-    Info: Found design unit 1: DSP-DSP_architecture
-    Info: Found entity 1: DSP
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg0.vhd
-    Info: Found design unit 1: lpm_shiftreg0-SYN
-    Info: Found entity 1: lpm_shiftreg0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri1.vhd
-    Info: Found design unit 1: lpm_bustri1-SYN
-    Info: Found entity 1: lpm_bustri1
-Info: Found 2 design units, including 1 entities, in source file video/altdpram1.vhd
-    Info: Found design unit 1: altdpram1-SYN
-    Info: Found entity 1: altdpram1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri2.vhd
-    Info: Found design unit 1: lpm_bustri2-SYN
-    Info: Found entity 1: lpm_bustri2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri4.vhd
-    Info: Found design unit 1: lpm_bustri4-SYN
-    Info: Found entity 1: lpm_bustri4
-Info: Found 2 design units, including 1 entities, in source file video/lpm_constant0.vhd
-    Info: Found design unit 1: lpm_constant0-SYN
-    Info: Found entity 1: lpm_constant0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_constant1.vhd
-    Info: Found design unit 1: lpm_constant1-SYN
-    Info: Found entity 1: lpm_constant1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux0.vhd
-    Info: Found design unit 1: lpm_mux0-SYN
-    Info: Found entity 1: lpm_mux0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux1.vhd
-    Info: Found design unit 1: lpm_mux1-SYN
-    Info: Found entity 1: lpm_mux1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux2.vhd
-    Info: Found design unit 1: lpm_mux2-SYN
-    Info: Found entity 1: lpm_mux2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_constant2.vhd
-    Info: Found design unit 1: lpm_constant2-SYN
-    Info: Found entity 1: lpm_constant2
-Info: Found 2 design units, including 1 entities, in source file video/altdpram2.vhd
-    Info: Found design unit 1: altdpram2-SYN
-    Info: Found entity 1: altdpram2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri6.vhd
-    Info: Found design unit 1: lpm_bustri6-SYN
-    Info: Found entity 1: lpm_bustri6
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux3.vhd
-    Info: Found design unit 1: lpm_mux3-SYN
-    Info: Found entity 1: lpm_mux3
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux4.vhd
-    Info: Found design unit 1: lpm_mux4-SYN
-    Info: Found entity 1: lpm_mux4
-Info: Found 2 design units, including 1 entities, in source file video/lpm_constant3.vhd
-    Info: Found design unit 1: lpm_constant3-SYN
-    Info: Found entity 1: lpm_constant3
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg1.vhd
-    Info: Found design unit 1: lpm_shiftreg1-SYN
-    Info: Found entity 1: lpm_shiftreg1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_latch1.vhd
-    Info: Found design unit 1: lpm_latch1-SYN
-    Info: Found entity 1: lpm_latch1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_constant4.vhd
-    Info: Found design unit 1: lpm_constant4-SYN
-    Info: Found entity 1: lpm_constant4
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg2.vhd
-    Info: Found design unit 1: lpm_shiftreg2-SYN
-    Info: Found entity 1: lpm_shiftreg2
-Info: Found 2 design units, including 1 entities, in source file video/lpm_compare1.vhd
-    Info: Found design unit 1: lpm_compare1-SYN
-    Info: Found entity 1: lpm_compare1
-Info: Found 1 design units, including 1 entities, in source file interrupt_handler/interrupt_handler.tdf
-    Info: Found entity 1: interrupt_handler
-Info: Found 2 design units, including 1 entities, in source file lpm_bustri_long.vhd
-    Info: Found design unit 1: lpm_bustri_long-SYN
-    Info: Found entity 1: lpm_bustri_LONG
-Info: Found 2 design units, including 1 entities, in source file lpm_bustri_byt.vhd
-    Info: Found design unit 1: lpm_bustri_byt-SYN
-    Info: Found entity 1: lpm_bustri_BYT
-Info: Found 2 design units, including 1 entities, in source file lpm_bustri_word.vhd
-    Info: Found design unit 1: lpm_bustri_word-SYN
-    Info: Found entity 1: lpm_bustri_WORD
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff4.vhd
-    Info: Found design unit 1: lpm_ff4-SYN
-    Info: Found entity 1: lpm_ff4
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff5.vhd
-    Info: Found design unit 1: lpm_ff5-SYN
-    Info: Found entity 1: lpm_ff5
-Info: Found 2 design units, including 1 entities, in source file video/lpm_ff6.vhd
-    Info: Found design unit 1: lpm_ff6-SYN
-    Info: Found entity 1: lpm_ff6
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg3.vhd
-    Info: Found design unit 1: lpm_shiftreg3-SYN
-    Info: Found entity 1: lpm_shiftreg3
-Info: Found 2 design units, including 1 entities, in source file video/altddio_bidir0.vhd
-    Info: Found design unit 1: altddio_bidir0-SYN
-    Info: Found entity 1: altddio_bidir0
-Info: Found 2 design units, including 1 entities, in source file video/altddio_out0.vhd
-    Info: Found design unit 1: altddio_out0-SYN
-    Info: Found entity 1: altddio_out0
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux5.vhd
-    Info: Found design unit 1: lpm_mux5-SYN
-    Info: Found entity 1: lpm_mux5
-Info: Found 2 design units, including 1 entities, in source file video/blitter/blitter.vhd
-    Info: Found design unit 1: BLITTER-BLITTER_architecture
-    Info: Found entity 1: BLITTER
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg5.vhd
-    Info: Found design unit 1: lpm_shiftreg5-SYN
-    Info: Found entity 1: lpm_shiftreg5
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg6.vhd
-    Info: Found design unit 1: lpm_shiftreg6-SYN
-    Info: Found entity 1: lpm_shiftreg6
-Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg4.vhd
-    Info: Found design unit 1: lpm_shiftreg4-SYN
-    Info: Found entity 1: lpm_shiftreg4
-Info: Found 2 design units, including 1 entities, in source file video/altddio_out1.vhd
-    Info: Found design unit 1: altddio_out1-SYN
-    Info: Found entity 1: altddio_out1
-Info: Found 2 design units, including 1 entities, in source file video/altddio_out2.vhd
-    Info: Found design unit 1: altddio_out2-SYN
-    Info: Found entity 1: altddio_out2
-Info: Found 2 design units, including 1 entities, in source file altddio_out3.vhd
-    Info: Found design unit 1: altddio_out3-SYN
-    Info: Found entity 1: altddio_out3
-Info: Found 2 design units, including 1 entities, in source file video/lpm_mux6.vhd
-    Info: Found design unit 1: lpm_mux6-SYN
-    Info: Found entity 1: lpm_mux6
-Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf_pgk.vhd
-    Info: Found design unit 1: FalconIO_SDCard_IDE_CF_PKG
-Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo1.vhd
-    Info: Found design unit 1: dcfifo1-SYN
-    Info: Found entity 1: dcfifo1
-Info: Found 2 design units, including 1 entities, in source file video/lpm_muxvdm.vhd
-    Info: Found design unit 1: lpm_muxvdm-SYN
-    Info: Found entity 1: lpm_muxVDM
-Info: Elaborating entity "firebee1" for the top level hierarchy
-Warning: Pin "TOUT0" not connected
-Warning: Pin "nMASTER" not connected
-Info: Elaborating entity "altpll1" for hierarchy "altpll1:inst"
-Info: Elaborating entity "altpll" for hierarchy "altpll1:inst|altpll:altpll_component"
-Info: Elaborated megafunction instantiation "altpll1:inst|altpll:altpll_component"
-Info: Instantiated megafunction "altpll1:inst|altpll:altpll_component" with the following parameter:
-    Info: Parameter "bandwidth_type" = "AUTO"
-    Info: Parameter "clk0_divide_by" = "66"
-    Info: Parameter "clk0_duty_cycle" = "50"
-    Info: Parameter "clk0_multiply_by" = "1"
-    Info: Parameter "clk0_phase_shift" = "0"
-    Info: Parameter "clk1_divide_by" = "900"
-    Info: Parameter "clk1_duty_cycle" = "50"
-    Info: Parameter "clk1_multiply_by" = "67"
-    Info: Parameter "clk1_phase_shift" = "0"
-    Info: Parameter "clk2_divide_by" = "90"
-    Info: Parameter "clk2_duty_cycle" = "50"
-    Info: Parameter "clk2_multiply_by" = "67"
-    Info: Parameter "clk2_phase_shift" = "0"
-    Info: Parameter "compensate_clock" = "CLK0"
-    Info: Parameter "inclk0_input_frequency" = "30303"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altpll"
-    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
-    Info: Parameter "pll_type" = "AUTO"
-    Info: Parameter "port_activeclock" = "PORT_UNUSED"
-    Info: Parameter "port_areset" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
-    Info: Parameter "port_clkloss" = "PORT_UNUSED"
-    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
-    Info: Parameter "port_configupdate" = "PORT_UNUSED"
-    Info: Parameter "port_fbin" = "PORT_UNUSED"
-    Info: Parameter "port_inclk0" = "PORT_USED"
-    Info: Parameter "port_inclk1" = "PORT_UNUSED"
-    Info: Parameter "port_locked" = "PORT_USED"
-    Info: Parameter "port_pfdena" = "PORT_UNUSED"
-    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
-    Info: Parameter "port_phasedone" = "PORT_UNUSED"
-    Info: Parameter "port_phasestep" = "PORT_UNUSED"
-    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
-    Info: Parameter "port_pllena" = "PORT_UNUSED"
-    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
-    Info: Parameter "port_scanclk" = "PORT_UNUSED"
-    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
-    Info: Parameter "port_scandata" = "PORT_UNUSED"
-    Info: Parameter "port_scandataout" = "PORT_UNUSED"
-    Info: Parameter "port_scandone" = "PORT_UNUSED"
-    Info: Parameter "port_scanread" = "PORT_UNUSED"
-    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
-    Info: Parameter "port_clk0" = "PORT_USED"
-    Info: Parameter "port_clk1" = "PORT_USED"
-    Info: Parameter "port_clk2" = "PORT_USED"
-    Info: Parameter "port_clk3" = "PORT_UNUSED"
-    Info: Parameter "port_clk4" = "PORT_UNUSED"
-    Info: Parameter "port_clk5" = "PORT_UNUSED"
-    Info: Parameter "port_clkena0" = "PORT_UNUSED"
-    Info: Parameter "port_clkena1" = "PORT_UNUSED"
-    Info: Parameter "port_clkena2" = "PORT_UNUSED"
-    Info: Parameter "port_clkena3" = "PORT_UNUSED"
-    Info: Parameter "port_clkena4" = "PORT_UNUSED"
-    Info: Parameter "port_clkena5" = "PORT_UNUSED"
-    Info: Parameter "port_extclk0" = "PORT_UNUSED"
-    Info: Parameter "port_extclk1" = "PORT_UNUSED"
-    Info: Parameter "port_extclk2" = "PORT_UNUSED"
-    Info: Parameter "port_extclk3" = "PORT_UNUSED"
-    Info: Parameter "self_reset_on_loss_lock" = "OFF"
-    Info: Parameter "width_clock" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/altpll_pul2.tdf
-    Info: Found entity 1: altpll_pul2
-Info: Elaborating entity "altpll_pul2" for hierarchy "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated"
-Info: Elaborating entity "FalconIO_SDCard_IDE_CF" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden"
-Warning (10036): Verilog HDL or VHDL warning at FalconIO_SDCard_IDE_CF.vhd(244): object "SCSI_CSn" assigned a value but never read
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(303): signal "nIDE_RD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(304): signal "nIDE_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(313): signal "IDE_CF_CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(314): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(315): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(324): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(325): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(335): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(336): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
-Critical Warning (10920): VHDL Incomplete Partial Association warning at FalconIO_SDCard_IDE_CF.vhd(928): port or argument "IO_A_OUT" has 1/8 unassociated elements
-Info: Elaborating entity "dcfifo0" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF"
-Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
-Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
-Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter:
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_numwords" = "1024"
-    Info: Parameter "lpm_showahead" = "OFF"
-    Info: Parameter "lpm_type" = "dcfifo"
-    Info: Parameter "lpm_width" = "8"
-    Info: Parameter "lpm_widthu" = "10"
-    Info: Parameter "lpm_widthu_r" = "8"
-    Info: Parameter "lpm_width_r" = "32"
-    Info: Parameter "overflow_checking" = "ON"
-    Info: Parameter "rdsync_delaypipe" = "5"
-    Info: Parameter "underflow_checking" = "ON"
-    Info: Parameter "use_eab" = "ON"
-    Info: Parameter "write_aclr_synch" = "OFF"
-    Info: Parameter "wrsync_delaypipe" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/dcfifo_0hh1.tdf
-    Info: Found entity 1: dcfifo_0hh1
-Info: Elaborating entity "dcfifo_0hh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated"
-Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_lfb.tdf
-    Info: Found entity 1: a_gray2bin_lfb
-Info: Elaborating entity "a_gray2bin_lfb" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_k47.tdf
-    Info: Found entity 1: a_graycounter_k47
-Info: Elaborating entity "a_graycounter_k47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fic.tdf
-    Info: Found entity 1: a_graycounter_fic
-Info: Elaborating entity "a_graycounter_fic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bi31.tdf
-    Info: Found entity 1: altsyncram_bi31
-Info: Elaborating entity "altsyncram_bi31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf
-    Info: Found entity 1: alt_synch_pipe_ikd
-Info: Elaborating entity "alt_synch_pipe_ikd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf
-    Info: Found entity 1: dffpipe_hd9
-Info: Elaborating entity "dffpipe_hd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf
-    Info: Found entity 1: dffpipe_gd9
-Info: Elaborating entity "dffpipe_gd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
-    Info: Found entity 1: dffpipe_pe9
-Info: Elaborating entity "dffpipe_pe9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jkd.tdf
-    Info: Found entity 1: alt_synch_pipe_jkd
-Info: Elaborating entity "alt_synch_pipe_jkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf
-    Info: Found entity 1: dffpipe_id9
-Info: Elaborating entity "dffpipe_id9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17"
-Info: Found 1 design units, including 1 entities, in source file db/cmpr_256.tdf
-    Info: Found entity 1: cmpr_256
-Info: Elaborating entity "cmpr_256" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_256:rdempty_eq_comp1_lsb"
-Info: Found 1 design units, including 1 entities, in source file db/cmpr_156.tdf
-    Info: Found entity 1: cmpr_156
-Info: Elaborating entity "cmpr_156" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_t2e.tdf
-    Info: Found entity 1: cntr_t2e
-Info: Elaborating entity "cntr_t2e" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b"
-Info: Found 1 design units, including 1 entities, in source file db/mux_a18.tdf
-    Info: Found entity 1: mux_a18
-Info: Elaborating entity "mux_a18" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux"
-Info: Elaborating entity "dcfifo1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF"
-Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
-Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component"
-Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter:
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_numwords" = "256"
-    Info: Parameter "lpm_showahead" = "OFF"
-    Info: Parameter "lpm_type" = "dcfifo"
-    Info: Parameter "lpm_width" = "32"
-    Info: Parameter "lpm_widthu" = "8"
-    Info: Parameter "lpm_widthu_r" = "10"
-    Info: Parameter "lpm_width_r" = "8"
-    Info: Parameter "overflow_checking" = "ON"
-    Info: Parameter "rdsync_delaypipe" = "5"
-    Info: Parameter "underflow_checking" = "ON"
-    Info: Parameter "use_eab" = "ON"
-    Info: Parameter "write_aclr_synch" = "OFF"
-    Info: Parameter "wrsync_delaypipe" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/dcfifo_3fh1.tdf
-    Info: Found entity 1: dcfifo_3fh1
-Info: Elaborating entity "dcfifo_3fh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j47.tdf
-    Info: Found entity 1: a_graycounter_j47
-Info: Elaborating entity "a_graycounter_j47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_gic.tdf
-    Info: Found entity 1: a_graycounter_gic
-Info: Elaborating entity "a_graycounter_gic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ci31.tdf
-    Info: Found entity 1: altsyncram_ci31
-Info: Elaborating entity "altsyncram_ci31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_kkd.tdf
-    Info: Found entity 1: alt_synch_pipe_kkd
-Info: Elaborating entity "alt_synch_pipe_kkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf
-    Info: Found entity 1: dffpipe_jd9
-Info: Elaborating entity "dffpipe_jd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lkd.tdf
-    Info: Found entity 1: alt_synch_pipe_lkd
-Info: Elaborating entity "alt_synch_pipe_lkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_kd9.tdf
-    Info: Found entity 1: dffpipe_kd9
-Info: Elaborating entity "dffpipe_kd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15"
-Info: Elaborating entity "WF1772IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC"
-Info: Elaborating entity "WF1772IP_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL"
-Info: Elaborating entity "WF1772IP_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS"
-Info: Elaborating entity "WF1772IP_DIGITAL_PLL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL"
-Info: Elaborating entity "WF1772IP_AM_DETECTOR" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR"
-Info: Elaborating entity "WF1772IP_CRC_LOGIC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC"
-Info: Elaborating entity "WF1772IP_TRANSCEIVER" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER"
-Info: Elaborating entity "WF5380_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI"
-Info: Elaborating entity "WF5380_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS"
-Info: Elaborating entity "WF5380_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL"
-Info: Elaborating entity "WF6850IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD"
-Info: Elaborating entity "WF6850IP_CTRL_STATUS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS"
-Info: Elaborating entity "WF6850IP_RECEIVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE"
-Info: Elaborating entity "WF6850IP_TRANSMIT" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT"
-Info: Elaborating entity "WF68901IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP"
-Info: Elaborating entity "WF68901IP_USART_TOP" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART"
-Info: Elaborating entity "WF68901IP_USART_CTRL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL"
-Info: Elaborating entity "WF68901IP_USART_RX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE"
-Info: Elaborating entity "WF68901IP_USART_TX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT"
-Info: Elaborating entity "WF68901IP_INTERRUPTS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS"
-Info: Elaborating entity "WF68901IP_GPIO" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO"
-Info: Elaborating entity "WF68901IP_TIMERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS"
-Info: Elaborating entity "WF2149IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND"
-Info: Elaborating entity "WF2149IP_WAVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE"
-Info: Elaborating entity "altpll3" for hierarchy "altpll3:inst13"
-Info: Elaborating entity "altpll" for hierarchy "altpll3:inst13|altpll:altpll_component"
-Info: Elaborated megafunction instantiation "altpll3:inst13|altpll:altpll_component"
-Info: Instantiated megafunction "altpll3:inst13|altpll:altpll_component" with the following parameter:
-    Info: Parameter "bandwidth_type" = "AUTO"
-    Info: Parameter "clk0_divide_by" = "33"
-    Info: Parameter "clk0_duty_cycle" = "50"
-    Info: Parameter "clk0_multiply_by" = "2"
-    Info: Parameter "clk0_phase_shift" = "0"
-    Info: Parameter "clk1_divide_by" = "33"
-    Info: Parameter "clk1_duty_cycle" = "50"
-    Info: Parameter "clk1_multiply_by" = "16"
-    Info: Parameter "clk1_phase_shift" = "0"
-    Info: Parameter "clk2_divide_by" = "33"
-    Info: Parameter "clk2_duty_cycle" = "50"
-    Info: Parameter "clk2_multiply_by" = "25"
-    Info: Parameter "clk2_phase_shift" = "0"
-    Info: Parameter "clk3_divide_by" = "11"
-    Info: Parameter "clk3_duty_cycle" = "50"
-    Info: Parameter "clk3_multiply_by" = "16"
-    Info: Parameter "clk3_phase_shift" = "0"
-    Info: Parameter "compensate_clock" = "CLK1"
-    Info: Parameter "inclk0_input_frequency" = "30303"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altpll"
-    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
-    Info: Parameter "pll_type" = "AUTO"
-    Info: Parameter "port_activeclock" = "PORT_UNUSED"
-    Info: Parameter "port_areset" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
-    Info: Parameter "port_clkloss" = "PORT_UNUSED"
-    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
-    Info: Parameter "port_configupdate" = "PORT_UNUSED"
-    Info: Parameter "port_fbin" = "PORT_UNUSED"
-    Info: Parameter "port_inclk0" = "PORT_USED"
-    Info: Parameter "port_inclk1" = "PORT_UNUSED"
-    Info: Parameter "port_locked" = "PORT_UNUSED"
-    Info: Parameter "port_pfdena" = "PORT_UNUSED"
-    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
-    Info: Parameter "port_phasedone" = "PORT_UNUSED"
-    Info: Parameter "port_phasestep" = "PORT_UNUSED"
-    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
-    Info: Parameter "port_pllena" = "PORT_UNUSED"
-    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
-    Info: Parameter "port_scanclk" = "PORT_UNUSED"
-    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
-    Info: Parameter "port_scandata" = "PORT_UNUSED"
-    Info: Parameter "port_scandataout" = "PORT_UNUSED"
-    Info: Parameter "port_scandone" = "PORT_UNUSED"
-    Info: Parameter "port_scanread" = "PORT_UNUSED"
-    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
-    Info: Parameter "port_clk0" = "PORT_USED"
-    Info: Parameter "port_clk1" = "PORT_USED"
-    Info: Parameter "port_clk2" = "PORT_USED"
-    Info: Parameter "port_clk3" = "PORT_USED"
-    Info: Parameter "port_clk4" = "PORT_UNUSED"
-    Info: Parameter "port_clk5" = "PORT_UNUSED"
-    Info: Parameter "port_clkena0" = "PORT_UNUSED"
-    Info: Parameter "port_clkena1" = "PORT_UNUSED"
-    Info: Parameter "port_clkena2" = "PORT_UNUSED"
-    Info: Parameter "port_clkena3" = "PORT_UNUSED"
-    Info: Parameter "port_clkena4" = "PORT_UNUSED"
-    Info: Parameter "port_clkena5" = "PORT_UNUSED"
-    Info: Parameter "port_extclk0" = "PORT_UNUSED"
-    Info: Parameter "port_extclk1" = "PORT_UNUSED"
-    Info: Parameter "port_extclk2" = "PORT_UNUSED"
-    Info: Parameter "port_extclk3" = "PORT_UNUSED"
-    Info: Parameter "width_clock" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/altpll_41p2.tdf
-    Info: Found entity 1: altpll_41p2
-Info: Elaborating entity "altpll_41p2" for hierarchy "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated"
-Info: Elaborating entity "Video" for hierarchy "Video:Fredi_Aschwanden"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ADR[31..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "MAIN_CLK"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS1"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS2"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS3"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_WR"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE0"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE1"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nRSTO"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_OE"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ALE"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDRCLK[3..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDR_SYNC_66M"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK33M"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK25M"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK_VIDEO"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_D[8..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_BUSY"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VG[7..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VB[7..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR[7..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nBLANK"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VA[12..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVWE"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCAS"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVRAS"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCS"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDM[3..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nPD_VGA"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VCKE"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VSYNC"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "HSYNC"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nSYNC"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_TA"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "PIXEL_CLK"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "BA[1..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_RECONFIG"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_WR"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_RD"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDQS[3..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_AD[31..0]"
-Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VD[31..0]"
-Info: Elaborating entity "VIDEO_MOD_MUX_CLUTCTR" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR"
-Warning: Variable or input pin "nRSTO" is defined but never used
-Warning: Variable or input pin "nFB_CS3" is defined but never used
-Warning: Variable or input pin "nFB_BURST" is defined but never used
-Info: Elaborating entity "lpm_bustri_WORD" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000"
-Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_BUSTRI"
-    Info: Parameter "lpm_width" = "16"
-Info: Elaborating entity "BLITTER" for hierarchy "Video:Fredi_Aschwanden|BLITTER:BLITTER"
-Info: Elaborating entity "lpm_shiftreg6" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89"
-Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
-    Info: Parameter "lpm_direction" = "RIGHT"
-    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
-    Info: Parameter "lpm_width" = "5"
-Info: Elaborating entity "DDR_CTR" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR"
-Warning: Variable or input pin "nFB_CS2" is defined but never used
-Warning: Variable or input pin "nFB_CS3" is defined but never used
-Warning: Variable or input pin "nRSTO" is defined but never used
-Info: Elaborating entity "lpm_bustri_BYT" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002"
-Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_BUSTRI"
-    Info: Parameter "lpm_width" = "8"
-Info: Elaborating entity "lpm_fifo_dc0" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst"
-Info: Elaborating entity "dcfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" with the following parameter:
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_numwords" = "512"
-    Info: Parameter "lpm_showahead" = "OFF"
-    Info: Parameter "lpm_type" = "dcfifo"
-    Info: Parameter "lpm_width" = "128"
-    Info: Parameter "lpm_widthu" = "9"
-    Info: Parameter "overflow_checking" = "OFF"
-    Info: Parameter "rdsync_delaypipe" = "6"
-    Info: Parameter "underflow_checking" = "OFF"
-    Info: Parameter "use_eab" = "ON"
-    Info: Parameter "write_aclr_synch" = "ON"
-    Info: Parameter "wrsync_delaypipe" = "6"
-Info: Found 1 design units, including 1 entities, in source file db/dcfifo_8fi1.tdf
-    Info: Found entity 1: dcfifo_8fi1
-Info: Elaborating entity "dcfifo_8fi1" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated"
-Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
-    Info: Found entity 1: a_gray2bin_tgb
-Info: Elaborating entity "a_gray2bin_tgb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
-    Info: Found entity 1: a_graycounter_s57
-Info: Elaborating entity "a_graycounter_s57" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
-    Info: Found entity 1: a_graycounter_ojc
-Info: Elaborating entity "a_graycounter_ojc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p"
-Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_njc.tdf
-    Info: Found entity 1: a_graycounter_njc
-Info: Elaborating entity "a_graycounter_njc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tl31.tdf
-    Info: Found entity 1: altsyncram_tl31
-Info: Elaborating entity "altsyncram_tl31" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
-    Info: Found entity 1: alt_synch_pipe_rld
-Info: Elaborating entity "alt_synch_pipe_rld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
-    Info: Found entity 1: dffpipe_qe9
-Info: Elaborating entity "dffpipe_qe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_9d9.tdf
-    Info: Found entity 1: dffpipe_9d9
-Info: Elaborating entity "dffpipe_9d9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
-    Info: Found entity 1: dffpipe_oe9
-Info: Elaborating entity "dffpipe_oe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp"
-Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf
-    Info: Found entity 1: alt_synch_pipe_sld
-Info: Elaborating entity "alt_synch_pipe_sld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp"
-Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf
-    Info: Found entity 1: dffpipe_re9
-Info: Elaborating entity "dffpipe_re9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22"
-Info: Elaborating entity "lpm_shiftreg4" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26"
-Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
-    Info: Parameter "lpm_direction" = "RIGHT"
-    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
-    Info: Parameter "lpm_width" = "5"
-Info: Elaborating entity "lpm_muxVDM" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "128"
-    Info: Parameter "LPM_SIZE" = "16"
-    Info: Parameter "LPM_WIDTHS" = "4"
-    Info: Parameter "LPM_PIPELINE" = "0"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_bbe.tdf
-    Info: Found entity 1: mux_bbe
-Info: Elaborating entity "mux_bbe" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component|mux_bbe:auto_generated"
-Info: Elaborating entity "lpm_ff6" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "128"
-Info: Elaborating entity "lpm_ff1" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "32"
-Info: Elaborating entity "altddio_bidir0" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1"
-Info: Elaborating entity "altddio_bidir" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" with the following parameter:
-    Info: Parameter "extend_oe_disable" = "UNUSED"
-    Info: Parameter "implement_input_in_lcell" = "ON"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "invert_output" = "OFF"
-    Info: Parameter "lpm_type" = "altddio_bidir"
-    Info: Parameter "oe_reg" = "UNUSED"
-    Info: Parameter "power_up_high" = "OFF"
-    Info: Parameter "width" = "32"
-Info: Found 1 design units, including 1 entities, in source file db/ddio_bidir_3jl.tdf
-    Info: Found entity 1: ddio_bidir_3jl
-Info: Elaborating entity "ddio_bidir_3jl" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated"
-Info: Elaborating entity "lpm_mux5" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "64"
-    Info: Parameter "LPM_SIZE" = "4"
-    Info: Parameter "LPM_WIDTHS" = "2"
-    Info: Parameter "LPM_PIPELINE" = "0"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_58e.tdf
-    Info: Found entity 1: mux_58e
-Info: Elaborating entity "mux_58e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component|mux_58e:auto_generated"
-Info: Elaborating entity "lpm_ff0" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "32"
-Info: Elaborating entity "lpm_bustri_LONG" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108"
-Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_BUSTRI"
-    Info: Parameter "lpm_width" = "32"
-Info: Elaborating entity "lpm_latch0" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27"
-Info: Elaborating entity "lpm_latch" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_LATCH"
-    Info: Parameter "lpm_width" = "32"
-Info: Elaborating entity "lpm_bustri3" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66"
-Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_BUSTRI"
-    Info: Parameter "lpm_width" = "6"
-Info: Elaborating entity "altdpram1" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED"
-Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" with the following parameter:
-    Info: Parameter "address_reg_b" = "CLOCK1"
-    Info: Parameter "clock_enable_input_a" = "BYPASS"
-    Info: Parameter "clock_enable_input_b" = "BYPASS"
-    Info: Parameter "clock_enable_output_a" = "BYPASS"
-    Info: Parameter "clock_enable_output_b" = "BYPASS"
-    Info: Parameter "indata_reg_b" = "CLOCK1"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altsyncram"
-    Info: Parameter "numwords_a" = "256"
-    Info: Parameter "numwords_b" = "256"
-    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
-    Info: Parameter "outdata_aclr_a" = "NONE"
-    Info: Parameter "outdata_aclr_b" = "NONE"
-    Info: Parameter "outdata_reg_a" = "CLOCK0"
-    Info: Parameter "outdata_reg_b" = "CLOCK1"
-    Info: Parameter "power_up_uninitialized" = "FALSE"
-    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
-    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
-    Info: Parameter "widthad_a" = "8"
-    Info: Parameter "widthad_b" = "8"
-    Info: Parameter "width_a" = "6"
-    Info: Parameter "width_b" = "6"
-    Info: Parameter "width_byteena_a" = "1"
-    Info: Parameter "width_byteena_b" = "1"
-    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lf92.tdf
-    Info: Found entity 1: altsyncram_lf92
-Info: Elaborating entity "altsyncram_lf92" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated"
-Info: Elaborating entity "lpm_shiftreg0" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0"
-Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" with the following parameter:
-    Info: Parameter "lpm_direction" = "LEFT"
-    Info: Parameter "lpm_type" = "LPM_SHIFTREG"
-    Info: Parameter "lpm_width" = "16"
-Info: Elaborating entity "MUX41" for hierarchy "Video:Fredi_Aschwanden|MUX41:inst45"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|MUX41:inst45"
-Info: Elaborating entity "lpm_muxDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "128"
-    Info: Parameter "LPM_SIZE" = "2"
-    Info: Parameter "LPM_WIDTHS" = "1"
-    Info: Parameter "LPM_PIPELINE" = "1"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_dcf.tdf
-    Info: Found entity 1: mux_dcf
-Info: Elaborating entity "mux_dcf" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component|mux_dcf:auto_generated"
-Info: Elaborating entity "lpm_fifoDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63"
-Info: Elaborating entity "scfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" with the following parameter:
-    Info: Parameter "add_ram_output_register" = "OFF"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_numwords" = "128"
-    Info: Parameter "lpm_showahead" = "ON"
-    Info: Parameter "lpm_type" = "scfifo"
-    Info: Parameter "lpm_width" = "128"
-    Info: Parameter "lpm_widthu" = "7"
-    Info: Parameter "overflow_checking" = "OFF"
-    Info: Parameter "underflow_checking" = "OFF"
-    Info: Parameter "use_eab" = "ON"
-Info: Found 1 design units, including 1 entities, in source file db/scfifo_lk21.tdf
-    Info: Found entity 1: scfifo_lk21
-Info: Elaborating entity "scfifo_lk21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated"
-Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oq21.tdf
-    Info: Found entity 1: a_dpfifo_oq21
-Info: Elaborating entity "a_dpfifo_oq21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gj81.tdf
-    Info: Found entity 1: altsyncram_gj81
-Info: Elaborating entity "altsyncram_gj81" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram"
-Info: Found 1 design units, including 1 entities, in source file db/cmpr_br8.tdf
-    Info: Found entity 1: cmpr_br8
-Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:almost_full_comparer"
-Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:three_comparison"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf
-    Info: Found entity 1: cntr_omb
-Info: Elaborating entity "cntr_omb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_5n7.tdf
-    Info: Found entity 1: cntr_5n7
-Info: Elaborating entity "cntr_5n7" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_pmb.tdf
-    Info: Found entity 1: cntr_pmb
-Info: Elaborating entity "cntr_pmb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr"
-Info: Elaborating entity "lpm_bustri1" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51"
-Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" with the following parameter:
-    Info: Parameter "lpm_type" = "LPM_BUSTRI"
-    Info: Parameter "lpm_width" = "3"
-Info: Elaborating entity "altdpram0" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED"
-Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" with the following parameter:
-    Info: Parameter "address_reg_b" = "CLOCK1"
-    Info: Parameter "clock_enable_input_a" = "BYPASS"
-    Info: Parameter "clock_enable_input_b" = "BYPASS"
-    Info: Parameter "clock_enable_output_a" = "BYPASS"
-    Info: Parameter "clock_enable_output_b" = "BYPASS"
-    Info: Parameter "indata_reg_b" = "CLOCK1"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altsyncram"
-    Info: Parameter "numwords_a" = "16"
-    Info: Parameter "numwords_b" = "16"
-    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
-    Info: Parameter "outdata_aclr_a" = "NONE"
-    Info: Parameter "outdata_aclr_b" = "NONE"
-    Info: Parameter "outdata_reg_a" = "CLOCK0"
-    Info: Parameter "outdata_reg_b" = "CLOCK1"
-    Info: Parameter "power_up_uninitialized" = "FALSE"
-    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
-    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
-    Info: Parameter "widthad_a" = "4"
-    Info: Parameter "widthad_b" = "4"
-    Info: Parameter "width_a" = "3"
-    Info: Parameter "width_b" = "3"
-    Info: Parameter "width_byteena_a" = "1"
-    Info: Parameter "width_byteena_b" = "1"
-    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rb92.tdf
-    Info: Found entity 1: altsyncram_rb92
-Info: Elaborating entity "altsyncram_rb92" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated"
-Info: Elaborating entity "altdpram2" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55"
-Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" with the following parameter:
-    Info: Parameter "address_reg_b" = "CLOCK1"
-    Info: Parameter "clock_enable_input_a" = "BYPASS"
-    Info: Parameter "clock_enable_input_b" = "BYPASS"
-    Info: Parameter "clock_enable_output_a" = "BYPASS"
-    Info: Parameter "clock_enable_output_b" = "BYPASS"
-    Info: Parameter "indata_reg_b" = "CLOCK1"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altsyncram"
-    Info: Parameter "numwords_a" = "256"
-    Info: Parameter "numwords_b" = "256"
-    Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT"
-    Info: Parameter "outdata_aclr_a" = "NONE"
-    Info: Parameter "outdata_aclr_b" = "NONE"
-    Info: Parameter "outdata_reg_a" = "CLOCK0"
-    Info: Parameter "outdata_reg_b" = "CLOCK1"
-    Info: Parameter "power_up_uninitialized" = "FALSE"
-    Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA"
-    Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA"
-    Info: Parameter "widthad_a" = "8"
-    Info: Parameter "widthad_b" = "8"
-    Info: Parameter "width_a" = "8"
-    Info: Parameter "width_b" = "8"
-    Info: Parameter "width_byteena_a" = "1"
-    Info: Parameter "width_byteena_b" = "1"
-    Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pf92.tdf
-    Info: Found entity 1: altsyncram_pf92
-Info: Elaborating entity "altsyncram_pf92" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated"
-Info: Elaborating entity "lpm_mux3" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "1"
-    Info: Parameter "LPM_SIZE" = "2"
-    Info: Parameter "LPM_WIDTHS" = "1"
-    Info: Parameter "LPM_PIPELINE" = "0"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_96e.tdf
-    Info: Found entity 1: mux_96e
-Info: Elaborating entity "mux_96e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component|mux_96e:auto_generated"
-Info: Elaborating entity "lpm_ff5" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "8"
-Info: Elaborating entity "lpm_mux2" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "8"
-    Info: Parameter "LPM_SIZE" = "16"
-    Info: Parameter "LPM_WIDTHS" = "4"
-    Info: Parameter "LPM_PIPELINE" = "2"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_mpe.tdf
-    Info: Found entity 1: mux_mpe
-Info: Elaborating entity "mux_mpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component|mux_mpe:auto_generated"
-Info: Elaborating entity "lpm_mux4" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "7"
-    Info: Parameter "LPM_SIZE" = "2"
-    Info: Parameter "LPM_WIDTHS" = "1"
-    Info: Parameter "LPM_PIPELINE" = "0"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_f6e.tdf
-    Info: Found entity 1: mux_f6e
-Info: Elaborating entity "mux_f6e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component|mux_f6e:auto_generated"
-Info: Elaborating entity "lpm_constant3" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82"
-Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" with the following parameter:
-    Info: Parameter "lpm_cvalue" = "0"
-    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
-    Info: Parameter "lpm_type" = "LPM_CONSTANT"
-    Info: Parameter "lpm_width" = "7"
-Info: Elaborating entity "altddio_out2" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5"
-Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" with the following parameter:
-    Info: Parameter "extend_oe_disable" = "UNUSED"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "invert_output" = "OFF"
-    Info: Parameter "lpm_type" = "altddio_out"
-    Info: Parameter "oe_reg" = "UNUSED"
-    Info: Parameter "power_up_high" = "OFF"
-    Info: Parameter "width" = "24"
-Info: Found 1 design units, including 1 entities, in source file db/ddio_out_o2f.tdf
-    Info: Found entity 1: ddio_out_o2f
-Info: Elaborating entity "ddio_out_o2f" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated"
-Info: Elaborating entity "lpm_mux6" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "24"
-    Info: Parameter "LPM_SIZE" = "8"
-    Info: Parameter "LPM_WIDTHS" = "3"
-    Info: Parameter "LPM_PIPELINE" = "2"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_kpe.tdf
-    Info: Found entity 1: mux_kpe
-Info: Elaborating entity "mux_kpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component|mux_kpe:auto_generated"
-Info: Elaborating entity "lpm_ff3" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "24"
-Info: Elaborating entity "lpm_constant0" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59"
-Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" with the following parameter:
-    Info: Parameter "lpm_cvalue" = "0"
-    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
-    Info: Parameter "lpm_type" = "LPM_CONSTANT"
-    Info: Parameter "lpm_width" = "5"
-Info: Elaborating entity "lpm_constant1" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77"
-Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" with the following parameter:
-    Info: Parameter "lpm_cvalue" = "0"
-    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
-    Info: Parameter "lpm_type" = "LPM_CONSTANT"
-    Info: Parameter "lpm_width" = "2"
-Info: Elaborating entity "lpm_ff4" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10"
-Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" with the following parameter:
-    Info: Parameter "lpm_fftype" = "DFF"
-    Info: Parameter "lpm_type" = "LPM_FF"
-    Info: Parameter "lpm_width" = "16"
-Info: Elaborating entity "lpm_mux1" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component"
-Info: Assertion information: Value of LPM_PIPELINE parameter (4) should be lower -- use 1 for best performance/utilization
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "16"
-    Info: Parameter "LPM_SIZE" = "8"
-    Info: Parameter "LPM_WIDTHS" = "3"
-    Info: Parameter "LPM_PIPELINE" = "4"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Assertion information: Value of LPM_PIPELINE parameter 4 should be lower -- use 1 for best performance/utilization
-Info: Found 1 design units, including 1 entities, in source file db/mux_npe.tdf
-    Info: Found entity 1: mux_npe
-Info: Elaborating entity "mux_npe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component|mux_npe:auto_generated"
-Info: Elaborating entity "lpm_constant2" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23"
-Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" with the following parameter:
-    Info: Parameter "lpm_cvalue" = "0"
-    Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
-    Info: Parameter "lpm_type" = "LPM_CONSTANT"
-    Info: Parameter "lpm_width" = "8"
-Info: Elaborating entity "lpm_mux0" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21"
-Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "32"
-    Info: Parameter "LPM_SIZE" = "4"
-    Info: Parameter "LPM_WIDTHS" = "2"
-    Info: Parameter "LPM_PIPELINE" = "4"
-    Info: Parameter "LPM_TYPE" = "LPM_MUX"
-    Info: Parameter "LPM_HINT" = "UNUSED"
-Info: Found 1 design units, including 1 entities, in source file db/mux_gpe.tdf
-    Info: Found entity 1: mux_gpe
-Info: Elaborating entity "mux_gpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component|mux_gpe:auto_generated"
-Info: Elaborating entity "altddio_out0" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2"
-Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" with the following parameter:
-    Info: Parameter "extend_oe_disable" = "UNUSED"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "invert_output" = "ON"
-    Info: Parameter "lpm_type" = "altddio_out"
-    Info: Parameter "oe_reg" = "UNUSED"
-    Info: Parameter "power_up_high" = "ON"
-    Info: Parameter "width" = "4"
-Info: Found 1 design units, including 1 entities, in source file db/ddio_out_are.tdf
-    Info: Found entity 1: ddio_out_are
-Info: Elaborating entity "ddio_out_are" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated"
-Info: Elaborating entity "altpll2" for hierarchy "altpll2:inst12"
-Info: Elaborating entity "altpll" for hierarchy "altpll2:inst12|altpll:altpll_component"
-Info: Elaborated megafunction instantiation "altpll2:inst12|altpll:altpll_component"
-Info: Instantiated megafunction "altpll2:inst12|altpll:altpll_component" with the following parameter:
-    Info: Parameter "bandwidth_type" = "AUTO"
-    Info: Parameter "clk0_divide_by" = "1"
-    Info: Parameter "clk0_duty_cycle" = "50"
-    Info: Parameter "clk0_multiply_by" = "4"
-    Info: Parameter "clk0_phase_shift" = "5051"
-    Info: Parameter "clk1_divide_by" = "1"
-    Info: Parameter "clk1_duty_cycle" = "50"
-    Info: Parameter "clk1_multiply_by" = "4"
-    Info: Parameter "clk1_phase_shift" = "0"
-    Info: Parameter "clk2_divide_by" = "1"
-    Info: Parameter "clk2_duty_cycle" = "50"
-    Info: Parameter "clk2_multiply_by" = "4"
-    Info: Parameter "clk2_phase_shift" = "3788"
-    Info: Parameter "clk3_divide_by" = "1"
-    Info: Parameter "clk3_duty_cycle" = "50"
-    Info: Parameter "clk3_multiply_by" = "4"
-    Info: Parameter "clk3_phase_shift" = "2210"
-    Info: Parameter "clk4_divide_by" = "1"
-    Info: Parameter "clk4_duty_cycle" = "50"
-    Info: Parameter "clk4_multiply_by" = "2"
-    Info: Parameter "clk4_phase_shift" = "11364"
-    Info: Parameter "compensate_clock" = "CLK0"
-    Info: Parameter "inclk0_input_frequency" = "30303"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altpll"
-    Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
-    Info: Parameter "pll_type" = "AUTO"
-    Info: Parameter "port_activeclock" = "PORT_UNUSED"
-    Info: Parameter "port_areset" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
-    Info: Parameter "port_clkloss" = "PORT_UNUSED"
-    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
-    Info: Parameter "port_configupdate" = "PORT_UNUSED"
-    Info: Parameter "port_fbin" = "PORT_UNUSED"
-    Info: Parameter "port_inclk0" = "PORT_USED"
-    Info: Parameter "port_inclk1" = "PORT_UNUSED"
-    Info: Parameter "port_locked" = "PORT_UNUSED"
-    Info: Parameter "port_pfdena" = "PORT_UNUSED"
-    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
-    Info: Parameter "port_phasedone" = "PORT_UNUSED"
-    Info: Parameter "port_phasestep" = "PORT_UNUSED"
-    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
-    Info: Parameter "port_pllena" = "PORT_UNUSED"
-    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
-    Info: Parameter "port_scanclk" = "PORT_UNUSED"
-    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
-    Info: Parameter "port_scandata" = "PORT_UNUSED"
-    Info: Parameter "port_scandataout" = "PORT_UNUSED"
-    Info: Parameter "port_scandone" = "PORT_UNUSED"
-    Info: Parameter "port_scanread" = "PORT_UNUSED"
-    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
-    Info: Parameter "port_clk0" = "PORT_USED"
-    Info: Parameter "port_clk1" = "PORT_USED"
-    Info: Parameter "port_clk2" = "PORT_USED"
-    Info: Parameter "port_clk3" = "PORT_USED"
-    Info: Parameter "port_clk4" = "PORT_USED"
-    Info: Parameter "port_clk5" = "PORT_UNUSED"
-    Info: Parameter "port_clkena0" = "PORT_UNUSED"
-    Info: Parameter "port_clkena1" = "PORT_UNUSED"
-    Info: Parameter "port_clkena2" = "PORT_UNUSED"
-    Info: Parameter "port_clkena3" = "PORT_UNUSED"
-    Info: Parameter "port_clkena4" = "PORT_UNUSED"
-    Info: Parameter "port_clkena5" = "PORT_UNUSED"
-    Info: Parameter "port_extclk0" = "PORT_UNUSED"
-    Info: Parameter "port_extclk1" = "PORT_UNUSED"
-    Info: Parameter "port_extclk2" = "PORT_UNUSED"
-    Info: Parameter "port_extclk3" = "PORT_UNUSED"
-    Info: Parameter "width_clock" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/altpll_isv2.tdf
-    Info: Found entity 1: altpll_isv2
-Info: Elaborating entity "altpll_isv2" for hierarchy "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated"
-Warning: Using design file altpll4.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
-    Info: Found entity 1: altpll4
-Info: Elaborating entity "altpll4" for hierarchy "altpll4:inst22"
-Info: Elaborating entity "altpll" for hierarchy "altpll4:inst22|altpll:altpll_component"
-Info: Elaborated megafunction instantiation "altpll4:inst22|altpll:altpll_component"
-Info: Instantiated megafunction "altpll4:inst22|altpll:altpll_component" with the following parameter:
-    Info: Parameter "bandwidth_type" = "AUTO"
-    Info: Parameter "clk0_divide_by" = "1"
-    Info: Parameter "clk0_duty_cycle" = "50"
-    Info: Parameter "clk0_multiply_by" = "2"
-    Info: Parameter "clk0_phase_shift" = "0"
-    Info: Parameter "compensate_clock" = "CLK0"
-    Info: Parameter "inclk0_input_frequency" = "20833"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "lpm_type" = "altpll"
-    Info: Parameter "operation_mode" = "NORMAL"
-    Info: Parameter "pll_type" = "AUTO"
-    Info: Parameter "port_activeclock" = "PORT_UNUSED"
-    Info: Parameter "port_areset" = "PORT_USED"
-    Info: Parameter "port_clk0" = "PORT_USED"
-    Info: Parameter "port_clk1" = "PORT_UNUSED"
-    Info: Parameter "port_clk2" = "PORT_UNUSED"
-    Info: Parameter "port_clk3" = "PORT_UNUSED"
-    Info: Parameter "port_clk4" = "PORT_UNUSED"
-    Info: Parameter "port_clk5" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
-    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
-    Info: Parameter "port_clkena0" = "PORT_UNUSED"
-    Info: Parameter "port_clkena1" = "PORT_UNUSED"
-    Info: Parameter "port_clkena2" = "PORT_UNUSED"
-    Info: Parameter "port_clkena3" = "PORT_UNUSED"
-    Info: Parameter "port_clkena4" = "PORT_UNUSED"
-    Info: Parameter "port_clkena5" = "PORT_UNUSED"
-    Info: Parameter "port_clkloss" = "PORT_UNUSED"
-    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
-    Info: Parameter "port_configupdate" = "PORT_USED"
-    Info: Parameter "port_extclk0" = "PORT_UNUSED"
-    Info: Parameter "port_extclk1" = "PORT_UNUSED"
-    Info: Parameter "port_extclk2" = "PORT_UNUSED"
-    Info: Parameter "port_extclk3" = "PORT_UNUSED"
-    Info: Parameter "port_fbin" = "PORT_UNUSED"
-    Info: Parameter "port_inclk0" = "PORT_USED"
-    Info: Parameter "port_inclk1" = "PORT_UNUSED"
-    Info: Parameter "port_locked" = "PORT_USED"
-    Info: Parameter "port_pfdena" = "PORT_UNUSED"
-    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
-    Info: Parameter "port_phasedone" = "PORT_UNUSED"
-    Info: Parameter "port_phasestep" = "PORT_UNUSED"
-    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
-    Info: Parameter "port_pllena" = "PORT_UNUSED"
-    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
-    Info: Parameter "port_scanclk" = "PORT_USED"
-    Info: Parameter "port_scanclkena" = "PORT_USED"
-    Info: Parameter "port_scandata" = "PORT_USED"
-    Info: Parameter "port_scandataout" = "PORT_USED"
-    Info: Parameter "port_scandone" = "PORT_USED"
-    Info: Parameter "port_scanread" = "PORT_UNUSED"
-    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
-    Info: Parameter "scan_chain_mif_file" = "altpll4.mif"
-    Info: Parameter "self_reset_on_loss_lock" = "OFF"
-    Info: Parameter "width_clock" = "5"
-    Info: Parameter "width_phasecounterselect" = "4"
-Info: Found 1 design units, including 1 entities, in source file db/altpll_c6j2.tdf
-    Info: Found entity 1: altpll_c6j2
-Info: Elaborating entity "altpll_c6j2" for hierarchy "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated"
-Warning: Using design file altpll_reconfig1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
-    Info: Found entity 1: altpll_reconfig1
-Info: Elaborating entity "altpll_reconfig1" for hierarchy "altpll_reconfig1:inst7"
-Warning: Using design file altpll_reconfig1_pllrcfg_t4q.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
-    Info: Found entity 1: altpll_reconfig1_pllrcfg_t4q
-Info: Elaborating entity "altpll_reconfig1_pllrcfg_t4q" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component"
-Info: Elaborating entity "altsyncram" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" with the following parameter:
-    Info: Parameter "OPERATION_MODE" = "SINGLE_PORT"
-    Info: Parameter "WIDTH_A" = "1"
-    Info: Parameter "WIDTHAD_A" = "8"
-    Info: Parameter "NUMWORDS_A" = "144"
-    Info: Parameter "WIDTH_BYTEENA_A" = "1"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46r.tdf
-    Info: Found entity 1: altsyncram_46r
-Info: Elaborating entity "altsyncram_46r" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated"
-Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "9"
-Info: Found 1 design units, including 1 entities, in source file db/add_sub_hpa.tdf
-    Info: Found entity 1: add_sub_hpa
-Info: Elaborating entity "add_sub_hpa" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5|add_sub_hpa:auto_generated"
-Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "8"
-Info: Found 1 design units, including 1 entities, in source file db/add_sub_k8a.tdf
-    Info: Found entity 1: add_sub_k8a
-Info: Elaborating entity "add_sub_k8a" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6|add_sub_k8a:auto_generated"
-Info: Elaborating entity "lpm_compare" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" with the following parameter:
-    Info: Parameter "LPM_WIDTH" = "8"
-Info: Found 1 design units, including 1 entities, in source file db/cmpr_tnd.tdf
-    Info: Found entity 1: cmpr_tnd
-Info: Elaborating entity "cmpr_tnd" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated"
-Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" with the following parameter:
-    Info: Parameter "LPM_DIRECTION" = "DOWN"
-    Info: Parameter "lpm_modulus" = "144"
-    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
-    Info: Parameter "LPM_WIDTH" = "8"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_30l.tdf
-    Info: Found entity 1: cntr_30l
-Info: Elaborating entity "cntr_30l" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated"
-Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" with the following parameter:
-    Info: Parameter "LPM_DIRECTION" = "DOWN"
-    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
-    Info: Parameter "LPM_WIDTH" = "6"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_qij.tdf
-    Info: Found entity 1: cntr_qij
-Info: Elaborating entity "cntr_qij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated"
-Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" with the following parameter:
-    Info: Parameter "LPM_DIRECTION" = "DOWN"
-    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
-    Info: Parameter "LPM_WIDTH" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_pij.tdf
-    Info: Found entity 1: cntr_pij
-Info: Elaborating entity "cntr_pij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated"
-Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" with the following parameter:
-    Info: Parameter "LPM_DIRECTION" = "UP"
-    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
-    Info: Parameter "LPM_WIDTH" = "8"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_9cj.tdf
-    Info: Found entity 1: cntr_9cj
-Info: Elaborating entity "cntr_9cj" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated"
-Info: Elaborating entity "lpm_decode" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11"
-Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11"
-Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" with the following parameter:
-    Info: Parameter "LPM_DECODES" = "5"
-    Info: Parameter "LPM_WIDTH" = "3"
-Info: Found 1 design units, including 1 entities, in source file db/decode_2af.tdf
-    Info: Found entity 1: decode_2af
-Info: Elaborating entity "decode_2af" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11|decode_2af:auto_generated"
-Info: Elaborating entity "DSP" for hierarchy "DSP:Mathias_Alles"
-Info: Elaborating entity "interrupt_handler" for hierarchy "interrupt_handler:nobody"
-Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst18"
-Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component"
-Info: Elaborated megafunction instantiation "lpm_counter0:inst18|lpm_counter:lpm_counter_component"
-Info: Instantiated megafunction "lpm_counter0:inst18|lpm_counter:lpm_counter_component" with the following parameter:
-    Info: Parameter "lpm_direction" = "UP"
-    Info: Parameter "lpm_port_updown" = "PORT_UNUSED"
-    Info: Parameter "lpm_type" = "LPM_COUNTER"
-    Info: Parameter "lpm_width" = "18"
-Info: Found 1 design units, including 1 entities, in source file db/cntr_mph.tdf
-    Info: Found entity 1: cntr_mph
-Info: Elaborating entity "cntr_mph" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated"
-Info: Elaborating entity "altddio_out3" for hierarchy "altddio_out3:inst5"
-Info: Elaborating entity "altddio_out" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component"
-Info: Elaborated megafunction instantiation "altddio_out3:inst5|altddio_out:altddio_out_component"
-Info: Instantiated megafunction "altddio_out3:inst5|altddio_out:altddio_out_component" with the following parameter:
-    Info: Parameter "extend_oe_disable" = "UNUSED"
-    Info: Parameter "intended_device_family" = "Cyclone III"
-    Info: Parameter "invert_output" = "OFF"
-    Info: Parameter "lpm_type" = "altddio_out"
-    Info: Parameter "oe_reg" = "UNUSED"
-    Info: Parameter "power_up_high" = "OFF"
-    Info: Parameter "width" = "1"
-Info: Found 1 design units, including 1 entities, in source file db/ddio_out_31f.tdf
-    Info: Found entity 1: ddio_out_31f
-Info: Elaborating entity "ddio_out_31f" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated"
-Warning: Timing-Driven Synthesis is skipped because the Classic Timing Analyzer is turned on
-Info: Inferred 3 megafunctions from design logic
-    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_14"
-    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_6"
-    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_12"
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" with the following parameter:
-    Info: Parameter "LPM_WIDTHA" = "12"
-    Info: Parameter "LPM_WIDTHB" = "6"
-    Info: Parameter "LPM_WIDTHP" = "18"
-    Info: Parameter "LPM_WIDTHR" = "18"
-    Info: Parameter "LPM_WIDTHS" = "1"
-    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
-    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
-    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
-    Info: Parameter "MAXIMIZE_SPEED" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/mult_cat.tdf
-    Info: Found entity 1: mult_cat
-Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6"
-Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" with the following parameter:
-    Info: Parameter "LPM_WIDTHA" = "12"
-    Info: Parameter "LPM_WIDTHB" = "5"
-    Info: Parameter "LPM_WIDTHP" = "17"
-    Info: Parameter "LPM_WIDTHR" = "17"
-    Info: Parameter "LPM_WIDTHS" = "1"
-    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
-    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
-    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
-    Info: Parameter "MAXIMIZE_SPEED" = "5"
-Info: Found 1 design units, including 1 entities, in source file db/mult_aat.tdf
-    Info: Found entity 1: mult_aat
-Warning: The following nodes have both tri-state and non-tri-state drivers
-    Warning: Inserted always-enabled tri-state buffer between "IO[17]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[16]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[15]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[14]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[13]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[12]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[11]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[10]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[9]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[8]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[7]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[6]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[5]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[4]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[3]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[2]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[1]" and its non-tri-state driver.
-    Warning: Inserted always-enabled tri-state buffer between "IO[0]" and its non-tri-state driver.
-Info: Registers with preset signals will power-up high
-Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
-Warning: TRI or OPNDRN buffers permanently disabled
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_PAR~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_RST~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[7]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[6]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[5]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[4]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[3]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[2]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[1]~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[0]~synth"
-Warning: TRI or OPNDRN buffers permanently enabled
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "IO~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_SEL~synth"
-    Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_BUSY~synth"
-Warning: Output pins are stuck at VCC or GND
-    Warning (13410): Pin "nACSI_ACK" is stuck at VCC
-    Warning (13410): Pin "nACSI_CS" is stuck at VCC
-    Warning (13410): Pin "ACSI_DIR" is stuck at GND
-    Warning (13410): Pin "nSCSI_ACK" is stuck at VCC
-    Warning (13410): Pin "nSCSI_ATN" is stuck at VCC
-    Warning (13410): Pin "SCSI_DIR" is stuck at VCC
-    Warning (13410): Pin "nSYNC" is stuck at GND
-Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[31]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[30]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[29]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[28]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[27]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[26]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[25]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[24]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[23]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[22]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[21]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[20]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[19]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[18]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[17]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[16]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[15]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[14]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[13]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[12]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[11]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[10]" lost all its fanouts during netlist optimizations.
-    Info: Register "interrupt_handler:nobody|INT_CLEAR[7]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[6]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[5]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[4]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[3]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[2]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[1]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[5]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[4]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[3]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[2]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[1]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[7]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[6]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[5]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[4]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[3]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[2]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[1]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[2]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[1]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[7]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]" lost all its fanouts during netlist optimizations.
-    Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" lost all its fanouts during netlist optimizations.
-    Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]" lost all its fanouts during netlist optimizations.
-Info: Found the following redundant logic cells in design
-    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[0]"
-    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[1]"
-    Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[2]"
-Warning: Design contains 18 input pin(s) that do not drive logic
-    Warning (15610): No output dependent on input pin "nFB_BURST"
-    Warning (15610): No output dependent on input pin "nACSI_DRQ"
-    Warning (15610): No output dependent on input pin "nACSI_INT"
-    Warning (15610): No output dependent on input pin "nSCSI_DRQ"
-    Warning (15610): No output dependent on input pin "nSCSI_MSG"
-    Warning (15610): No output dependent on input pin "nDCHG"
-    Warning (15610): No output dependent on input pin "SD_DATA0"
-    Warning (15610): No output dependent on input pin "SD_DATA1"
-    Warning (15610): No output dependent on input pin "SD_DATA2"
-    Warning (15610): No output dependent on input pin "SD_CARD_DEDECT"
-    Warning (15610): No output dependent on input pin "SD_WP"
-    Warning (15610): No output dependent on input pin "nDACK0"
-    Warning (15610): No output dependent on input pin "WP_CF_CARD"
-    Warning (15610): No output dependent on input pin "nSCSI_C_D"
-    Warning (15610): No output dependent on input pin "nSCSI_I_O"
-    Warning (15610): No output dependent on input pin "nFB_CS3"
-    Warning (15610): No output dependent on input pin "TOUT0"
-    Warning (15610): No output dependent on input pin "nMASTER"
-Info: Implemented 11489 device resources after synthesis - the final resource count might be different
-    Info: Implemented 51 input pins
-    Info: Implemented 112 output pins
-    Info: Implemented 132 bidirectional pins
-    Info: Implemented 10796 logic cells
-    Info: Implemented 324 RAM segments
-    Info: Implemented 4 PLLs
-    Info: Implemented 6 DSP elements
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 143 warnings
-    Info: Peak virtual memory: 347 megabytes
-    Info: Processing ended: Wed Dec 15 02:21:56 2010
-    Info: Elapsed time: 00:01:19
-    Info: Total CPU time (on all processors): 00:01:20
-
-
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
index f8da91e..7a93fd1 100644
--- a/FPGA_by_Fredi/firebee1.map.summary
+++ b/FPGA_by_Fredi/firebee1.map.summary
@@ -1,14 +1,14 @@
-Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010
+Analysis & Synthesis Status : Successful - Fri Aug 28 13:35:56 2015
 Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
 Revision Name : firebee1
 Top-level Entity Name : firebee1
 Family : Cyclone III
-Total logic elements : 10,706
-    Total combinational functions : 8,060
-    Dedicated logic registers : 4,612
-Total registers : 4740
+Total logic elements : 11,642
+    Total combinational functions : 8,656
+    Dedicated logic registers : 5,028
+Total registers : 5156
 Total pins : 295
 Total virtual pins : 0
-Total memory bits : 109,344
+Total memory bits : 109,600
 Embedded Multiplier 9-bit elements : 6
 Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.pin b/FPGA_by_Fredi/firebee1.pin
index 50b8dd7..9f213b1 100644
--- a/FPGA_by_Fredi/firebee1.pin
+++ b/FPGA_by_Fredi/firebee1.pin
@@ -33,7 +33,7 @@
  --					Bank 5:		2.5V
  --					Bank 6:		3.0V
  --					Bank 7:		3.3V
- --					Bank 8:		3.3V
+ --					Bank 8:		3.0V
  -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
  --					It can also be used to report unused dedicated pins. The connection
  --					on the board for unused dedicated pins depends on whether this will
@@ -72,15 +72,15 @@ CHIP  "firebee1"  ASSIGNED TO AN: EP3C40F484C6
 Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
 -------------------------------------------------------------------------------------------------------------
 GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
-LP_D[6]                      : A3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRBLE                       : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[1]                       : A5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[3]                        : A6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[1]                        : A7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[0]                        : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[10]                      : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[9]                       : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : A2        : power  :                   : 3.0V    : 8         :                
+LP_D[6]                      : A3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+nSRBLE                       : A4        : output : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[1]                       : A5        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[3]                        : A6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[1]                        : A7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[0]                        : A8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[10]                      : A9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[9]                       : A10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 DVI_INT                      : A11       : input  : 3.3-V LVTTL       :         : 8         : Y              
 nDACK1                       : A12       : input  : 3.3-V LVTTL       :         : 7         : Y              
 IO[16]                       : A13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
@@ -126,7 +126,7 @@ FB_AD[23]                    : AB8       : bidir  : 3.3-V LVTTL       :
 FB_AD[26]                    : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 CLK24M576                    : AB10      : output : 3.3-V LVTTL       :         : 3         : Y              
 GND+                         : AB11      :        :                   :         : 3         :                
-CLK33M                       : AB12      : input  : 3.3-V LVTTL       :         : 4         : Y              
+CLK33MDIR                    : AB12      : input  : 3.3-V LVTTL       :         : 4         : Y              
 VD[29]                       : AB13      : bidir  : 2.5 V             :         : 4         : Y              
 VD[26]                       : AB14      : bidir  : 2.5 V             :         : 4         : Y              
 VD[24]                       : AB15      : bidir  : 2.5 V             :         : 4         : Y              
@@ -139,14 +139,14 @@ VCCIO4                       : AB21      : power  :                   : 2.5V
 GND                          : AB22      : gnd    :                   :         :           :                
 ACSI_D[0]                    : B1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 MIDI_TLR                     : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[5]                      : B3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRBHE                       : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[0]                       : B5        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[4]                        : B6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[2]                        : B7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRCS                        : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[8]                       : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[11]                      : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[5]                      : B3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+nSRBHE                       : B4        : output : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[0]                       : B5        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[4]                        : B6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[2]                        : B7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+nSRCS                        : B8        : output : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[8]                       : B9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[11]                      : B10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 nRSTO_MCF                    : B11       : input  : 3.3-V LVTTL       :         : 8         : Y              
 nDACK0                       : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
 IO[17]                       : B13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
@@ -161,14 +161,14 @@ VB[5]                        : B21       : output : 3.0-V LVTTL       :
 VB[4]                        : B22       : output : 3.0-V LVTTL       :         : 6         : Y              
 ACSI_D[4]                    : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 ACSI_D[3]                    : C2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[2]                      : C3        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[1]                      : C4        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[2]                      : C3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+LP_D[1]                      : C4        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 GND                          : C5        : gnd    :                   :         :           :                
-SRD[2]                       : C6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[7]                        : C7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[6]                        : C8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[2]                       : C6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[7]                        : C7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[6]                        : C8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 GND                          : C9        : gnd    :                   :         :           :                
-SRD[4]                       : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[4]                       : C10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 GND                          : C11       : gnd    :                   :         :           :                
 GND                          : C12       : gnd    :                   :         :           :                
 IO[11]                       : C13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
@@ -185,13 +185,13 @@ VB[2]                        : C22       : output : 3.0-V LVTTL       :
 ACSI_D[5]                    : D2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 GND                          : D3        : gnd    :                   :         :           :                
 VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
-LP_D[4]                      : D6        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D5        : power  :                   : 3.0V    : 8         :                
+LP_D[4]                      : D6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8         :                
 GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
-SRD[12]                      : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO8                       : D9        : power  :                   : 3.0V    : 8         :                
+SRD[12]                      : D10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.0V    : 8         :                
 VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
 IO[12]                       : D13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
 VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
@@ -207,14 +207,14 @@ SCSI_D[1]                    : E1        : bidir  : 3.3-V LVTTL       :
 ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
 ACSI_D[2]                    : E3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
-LPDIR                        : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
-LP_STR                       : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[3]                      : E7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
-IO[5]                        : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[6]                       : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LPDIR                        : E5        : output : 3.0-V LVCMOS      :         : 8         : Y              
+LP_STR                       : E6        : output : 3.0-V LVCMOS      :         : 8         : Y              
+LP_D[3]                      : E7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.0V    : 8         :                
+IO[5]                        : E9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[6]                       : E10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 nDREQ1                       : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
-MIDI_IN                      : E12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+MIDI_IN_PIN                  : E12       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
 IO[13]                       : E13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
 SD_CMD_D1                    : E14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
 YM_QC                        : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
@@ -231,10 +231,10 @@ GND                          : F3        : gnd    :                   :
 VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
 GNDA3                        : F5        : gnd    :                   :         :           :                
 VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-LP_D[0]                      : F7        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-nSRWE                        : F8        : output : 3.3-V LVTTL       :         : 8         : Y              
-SRD[5]                       : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[13]                      : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[0]                      : F7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+nSRWE                        : F8        : output : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[5]                       : F9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[13]                      : F10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 nSROE                        : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
 GND                          : F12       : gnd    :                   :         :           :                
 SD_CD_DATA3                  : F13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
@@ -254,10 +254,10 @@ SCSI_D[4]                    : G4        : bidir  : 3.3-V LVTTL       :
 ACSI_D[1]                    : G5        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 VCCA3                        : G6        : power  :                   : 2.5V    :           :                
 LP_BUSY                      : G7        : input  : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[7]                      : G8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[14]                      : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-IO[8]                        : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[3]                       : G11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+LP_D[7]                      : G8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[14]                      : G9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+IO[8]                        : G10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[3]                       : G11       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 VCCINT                       : G12       : power  :                   : 1.2V    :           :                
 YM_QB                        : G13       : output : 3.3-V LVTTL       :         : 7         : Y              
 nWR                          : G14       : output : 3.3-V LVTTL       :         : 7         : Y              
@@ -278,8 +278,8 @@ ACSI_D[7]                    : H6        : bidir  : 3.3-V LVTTL       :
 ACSI_D[6]                    : H7        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 1         :                
 VCCINT                       : H9        : power  :                   : 1.2V    :           :                
-SRD[15]                      : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
-SRD[7]                       : H11       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+SRD[15]                      : H10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
+SRD[7]                       : H11       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
 GND                          : H12       : gnd    :                   :         :           :                
 GND                          : H13       : gnd    :                   :         :           :                
 CTS                          : H14       : input  : 3.3-V LVTTL       :         : 7         : Y              
@@ -534,7 +534,7 @@ VA[0]                        : W20       : output : 2.5 V             :
 VA[2]                        : W21       : output : 2.5 V             :         : 5         : Y              
 VA[1]                        : W22       : output : 2.5 V             :         : 5         : Y              
 IDE_RDY                      : Y1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-AMKB_RX                      : Y2        : input  : 3.3-V LVTTL       :         : 2         : Y              
+AMKB_RX                      : Y2        : input  : 3.3-V LVCMOS      :         : 2         : Y              
 FB_AD[0]                     : Y3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
 FB_SIZE1                     : Y4        : input  : 3.3-V LVTTL       :         : 3         : Y              
 GND                          : Y5        : gnd    :                   :         :           :                
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index 86e8842..a1993e9 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -43,175 +43,9 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
 set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
-set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
-set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
-set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
-set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
-set_global_assignment -name VHDL_FILE lpm_latch0.vhd
-set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
-set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
-set_global_assignment -name QIP_FILE altpll2.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
-set_global_assignment -name QIP_FILE altpll3.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
-set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
-set_global_assignment -name SOURCE_FILE altpll0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
-set_global_assignment -name SOURCE_FILE altpll2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
-set_global_assignment -name VHDL_FILE altpll2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
-set_global_assignment -name SOURCE_FILE altpll3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
-set_global_assignment -name VHDL_FILE altpll3.vhd
-set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
-set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
-set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
-set_global_assignment -name BDF_FILE Video/Video.bdf
-set_global_assignment -name VHDL_FILE altpll1.vhd
-set_global_assignment -name SOURCE_FILE altpll1.cmp
-set_global_assignment -name BDF_FILE firebee1.bdf
-set_global_assignment -name QIP_FILE altpll0.qip
-set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
-set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE Video/altdpram0.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
-set_global_assignment -name QIP_FILE Video/altdpram1.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
-set_global_assignment -name QIP_FILE Video/altdpram2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
-set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
-set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
-set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
-set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
-set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
-set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
-set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
-set_global_assignment -name QIP_FILE Video/altddio_out0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
-set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd"
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
-set_global_assignment -name QIP_FILE Video/altddio_out1.qip
-set_global_assignment -name QIP_FILE Video/altddio_out2.qip
-set_global_assignment -name QIP_FILE altddio_out3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
 
 # Pin & Location Assignments
 # ==========================
-set_location_assignment PIN_AB12 -to CLK33M
 set_location_assignment PIN_G2 -to MAIN_CLK
 set_location_assignment PIN_Y3 -to FB_AD[0]
 set_location_assignment PIN_Y6 -to FB_AD[1]
@@ -485,7 +319,6 @@ set_location_assignment PIN_A20 -to nRD_DATA
 set_location_assignment PIN_C17 -to nDCHG
 set_location_assignment PIN_J4 -to nACSI_INT
 set_location_assignment PIN_K7 -to nACSI_DRQ
-set_location_assignment PIN_E12 -to MIDI_IN
 set_location_assignment PIN_G7 -to LP_BUSY
 set_location_assignment PIN_Y1 -to IDE_RDY
 set_location_assignment PIN_G22 -to IDE_INT
@@ -662,7 +495,7 @@ set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
 set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
@@ -680,15 +513,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
 set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
 set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
 set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
@@ -733,8 +565,268 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 # end ENTITY(firebee1)
 # --------------------
 set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
-set_global_assignment -name QIP_FILE altpll_reconfig1.qip
-set_global_assignment -name QIP_FILE altpll4.qip
 set_location_assignment PIN_E5 -to LPDIR
 set_location_assignment PIN_B11 -to nRSTO_MCF
+set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_clshift0.cmp
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift0.tdf
+set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
+set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
+set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name BDF_FILE Video/Video.bdf
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name BDF_FILE firebee1.bdf
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
+set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
+set_global_assignment -name QIP_FILE altpll_reconfig1.qip
+set_global_assignment -name QIP_FILE altpll4.qip
+set_global_assignment -name QIP_FILE lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
+set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
+set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE lpm_counter1.qip
+set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.rbf b/FPGA_by_Fredi/firebee1.rbf
deleted file mode 100644
index 63c16f1d687e91f02187b06b1c5e3ecfe12b2e04..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/FPGA_by_Fredi/firebee1.sta.summary b/FPGA_by_Fredi/firebee1.sta.summary
new file mode 100644
index 0000000..08274d1
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.sta.summary
@@ -0,0 +1,857 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -17.450
+TNS   : -16147.437
+
+Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -7.331
+TNS   : -4287.365
+
+Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -4.994
+TNS   : -47.649
+
+Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -4.588
+TNS   : -478.150
+
+Type  : Slow 1200mV 85C Model Setup 'MAIN_CLK'
+Slack : -4.230
+TNS   : -5479.268
+
+Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 2.377
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 2.892
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 3.750
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
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+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 497.531
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 1997.881
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -11.047
+TNS   : -9871.573
+
+Type  : Slow 1200mV 85C Model Hold 'MAIN_CLK'
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+TNS   : -9731.628
+
+Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -5.940
+TNS   : -5.940
+
+Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.283
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.342
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.376
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 0.389
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.541
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 2.366
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
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+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
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+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
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+TNS   : -2798.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -8.406
+TNS   : -16.812
+
+Type  : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -4.536
+TNS   : -782.022
+
+Type  : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -4.460
+TNS   : -652.825
+
+Type  : Slow 1200mV 85C Model Recovery 'MAIN_CLK'
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+TNS   : -646.634
+
+Type  : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -2.802
+TNS   : -2.802
+
+Type  : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -1.533
+TNS   : -1.533
+
+Type  : Slow 1200mV 85C Model Recovery 'DVI_INT'
+Slack : -0.826
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+
+Type  : Slow 1200mV 85C Model Recovery 'E0_INT'
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+
+Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTA'
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+
+Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTD'
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+
+Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTC'
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+
+Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTB'
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+
+Type  : Slow 1200mV 85C Model Recovery 'PIC_INT'
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+TNS   : -0.038
+
+Type  : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
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+TNS   : -1430.734
+
+Type  : Slow 1200mV 85C Model Removal 'MAIN_CLK'
+Slack : -10.188
+TNS   : -1400.869
+
+Type  : Slow 1200mV 85C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -2.755
+TNS   : -5.510
+
+Type  : Slow 1200mV 85C Model Removal 'PIC_INT'
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+
+Type  : Slow 1200mV 85C Model Removal 'nPCI_INTB'
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+
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+
+Type  : Slow 1200mV 85C Model Removal 'nPCI_INTD'
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+
+Type  : Slow 1200mV 85C Model Removal 'nPCI_INTA'
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+
+Type  : Slow 1200mV 85C Model Removal 'E0_INT'
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+
+Type  : Slow 1200mV 85C Model Removal 'DVI_INT'
+Slack : 0.299
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : 1.026
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.036
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : 2.350
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
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+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'PIC_INT'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTB'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTD'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTC'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTA'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'DVI_INT'
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+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'E0_INT'
+Slack : -3.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.527
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.533
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 3.533
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 3.533
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.811
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 7.320
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 10.398
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'MAIN_CLK'
+Slack : 13.528
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 18.585
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 30.973
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 249.617
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 999.882
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -15.403
+TNS   : -14377.209
+
+Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -6.421
+TNS   : -3676.693
+
+Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -4.520
+TNS   : -37.132
+
+Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -4.094
+TNS   : -426.105
+
+Type  : Slow 1200mV 0C Model Setup 'MAIN_CLK'
+Slack : -3.696
+TNS   : -4132.088
+
+Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 2.718
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 2.995
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 3.994
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 5.426
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 497.772
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 1998.168
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -9.832
+TNS   : -8727.393
+
+Type  : Slow 1200mV 0C Model Hold 'MAIN_CLK'
+Slack : -9.617
+TNS   : -8529.400
+
+Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -5.065
+TNS   : -5.065
+
+Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.254
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.297
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.335
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 0.346
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.517
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 2.163
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 2.766
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 4.082
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -13.902
+TNS   : -2482.848
+
+Type  : Slow 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -7.532
+TNS   : -15.064
+
+Type  : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -3.927
+TNS   : -573.408
+
+Type  : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -3.851
+TNS   : -663.617
+
+Type  : Slow 1200mV 0C Model Recovery 'MAIN_CLK'
+Slack : -3.223
+TNS   : -549.949
+
+Type  : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -2.555
+TNS   : -2.555
+
+Type  : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -1.377
+TNS   : -1.377
+
+Type  : Slow 1200mV 0C Model Recovery 'DVI_INT'
+Slack : -0.706
+TNS   : -0.706
+
+Type  : Slow 1200mV 0C Model Recovery 'E0_INT'
+Slack : -0.653
+TNS   : -0.653
+
+Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTA'
+Slack : -0.192
+TNS   : -0.192
+
+Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTD'
+Slack : -0.190
+TNS   : -0.190
+
+Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTC'
+Slack : -0.180
+TNS   : -0.180
+
+Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTB'
+Slack : -0.104
+TNS   : -0.104
+
+Type  : Slow 1200mV 0C Model Recovery 'PIC_INT'
+Slack : 0.013
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -9.193
+TNS   : -1262.369
+
+Type  : Slow 1200mV 0C Model Removal 'MAIN_CLK'
+Slack : -8.978
+TNS   : -1223.454
+
+Type  : Slow 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -2.195
+TNS   : -4.390
+
+Type  : Slow 1200mV 0C Model Removal 'PIC_INT'
+Slack : -0.527
+TNS   : -0.527
+
+Type  : Slow 1200mV 0C Model Removal 'nPCI_INTB'
+Slack : -0.384
+TNS   : -0.384
+
+Type  : Slow 1200mV 0C Model Removal 'nPCI_INTC'
+Slack : -0.316
+TNS   : -0.316
+
+Type  : Slow 1200mV 0C Model Removal 'nPCI_INTD'
+Slack : -0.288
+TNS   : -0.288
+
+Type  : Slow 1200mV 0C Model Removal 'nPCI_INTA'
+Slack : -0.283
+TNS   : -0.283
+
+Type  : Slow 1200mV 0C Model Removal 'E0_INT'
+Slack : 0.170
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'DVI_INT'
+Slack : 0.223
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : 0.914
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.936
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : 2.150
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 2.663
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
+Slack : -3.000
+TNS   : -4.036
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
+Slack : -3.000
+TNS   : -4.036
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
+Slack : -3.000
+TNS   : -4.012
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
+Slack : -3.000
+TNS   : -4.002
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
+Slack : -3.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'E0_INT'
+Slack : -3.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
+Slack : -3.000
+TNS   : -4.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.517
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 3.528
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.529
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 3.529
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.909
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 7.316
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 10.392
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
+Slack : 13.634
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 18.774
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 30.967
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 249.612
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 999.877
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -9.748
+TNS   : -9757.013
+
+Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -3.484
+TNS   : -1911.267
+
+Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -2.773
+TNS   : -9.357
+
+Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -2.483
+TNS   : -260.497
+
+Type  : Fast 1200mV 0C Model Setup 'MAIN_CLK'
+Slack : -1.767
+TNS   : -1399.694
+
+Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.283
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 3.689
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 4.868
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 5.744
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 498.517
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 1998.908
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -6.775
+TNS   : -6188.069
+
+Type  : Fast 1200mV 0C Model Hold 'MAIN_CLK'
+Slack : -6.521
+TNS   : -5940.597
+
+Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -3.440
+TNS   : -3.440
+
+Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 0.136
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.178
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.197
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 0.204
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 1.296
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 1.392
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 1.655
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.971
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -9.449
+TNS   : -1688.035
+
+Type  : Fast 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -4.842
+TNS   : -9.684
+
+Type  : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : -2.521
+TNS   : -370.829
+
+Type  : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -2.077
+TNS   : -353.703
+
+Type  : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -1.593
+TNS   : -1.593
+
+Type  : Fast 1200mV 0C Model Recovery 'MAIN_CLK'
+Slack : -1.560
+TNS   : -261.778
+
+Type  : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -0.866
+TNS   : -0.866
+
+Type  : Fast 1200mV 0C Model Recovery 'DVI_INT'
+Slack : -0.475
+TNS   : -0.475
+
+Type  : Fast 1200mV 0C Model Recovery 'E0_INT'
+Slack : -0.438
+TNS   : -0.438
+
+Type  : Fast 1200mV 0C Model Recovery 'PIC_INT'
+Slack : -0.086
+TNS   : -0.086
+
+Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTA'
+Slack : 0.253
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTC'
+Slack : 0.262
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTD'
+Slack : 0.263
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTB'
+Slack : 0.294
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : -6.385
+TNS   : -890.317
+
+Type  : Fast 1200mV 0C Model Removal 'MAIN_CLK'
+Slack : -6.131
+TNS   : -844.343
+
+Type  : Fast 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.544
+TNS   : -3.088
+
+Type  : Fast 1200mV 0C Model Removal 'nPCI_INTB'
+Slack : -0.648
+TNS   : -0.648
+
+Type  : Fast 1200mV 0C Model Removal 'nPCI_INTD'
+Slack : -0.607
+TNS   : -0.607
+
+Type  : Fast 1200mV 0C Model Removal 'nPCI_INTA'
+Slack : -0.603
+TNS   : -0.603
+
+Type  : Fast 1200mV 0C Model Removal 'nPCI_INTC'
+Slack : -0.601
+TNS   : -0.601
+
+Type  : Fast 1200mV 0C Model Removal 'PIC_INT'
+Slack : -0.261
+TNS   : -0.261
+
+Type  : Fast 1200mV 0C Model Removal 'E0_INT'
+Slack : 0.109
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'DVI_INT'
+Slack : 0.148
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : 0.560
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.568
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : 1.306
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 1.739
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
+Slack : -3.000
+TNS   : -5.254
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
+Slack : -3.000
+TNS   : -5.059
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
+Slack : -3.000
+TNS   : -5.025
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
+Slack : -3.000
+TNS   : -5.003
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
+Slack : -3.000
+TNS   : -4.993
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'E0_INT'
+Slack : -3.000
+TNS   : -4.216
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
+Slack : -3.000
+TNS   : -4.207
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
+Slack : -1.000
+TNS   : -1.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.538
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 3.563
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 3.567
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 3.568
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.773
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
+Slack : 7.355
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 10.398
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
+Slack : 13.572
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
+Slack : 18.964
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
+Slack : 30.983
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 249.649
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
+Slack : 999.914
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/FPGA_by_Fredi/firebee1.tan.rpt b/FPGA_by_Fredi/firebee1.tan.rpt
deleted file mode 100644
index b84e104..0000000
--- a/FPGA_by_Fredi/firebee1.tan.rpt
+++ /dev/null
@@ -1,6936 +0,0 @@
-Classic Timing Analyzer report for firebee1
-Wed Dec 15 02:25:22 2010
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Timing Analyzer Summary
-  3. Timing Analyzer Settings
-  4. Clock Settings Summary
-  5. Parallel Compilation
-  6. Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-  7. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-  8. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-  9. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
- 10. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
- 11. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
- 12. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
- 13. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
- 14. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
- 15. Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
- 16. Clock Setup: 'CLK33M'
- 17. Clock Setup: 'MAIN_CLK'
- 18. Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
- 19. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
- 20. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
- 21. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
- 22. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
- 23. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
- 24. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
- 25. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
- 26. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
- 27. Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
- 28. Clock Hold: 'CLK33M'
- 29. Clock Hold: 'MAIN_CLK'
- 30. tsu
- 31. tco
- 32. tpd
- 33. th
- 34. Board Trace Model Assignments
- 35. Input Transition Times
- 36. Slow Corner Signal Integrity Metrics
- 37. Fast Corner Signal Integrity Metrics
- 38. Ignored Timing Assignments
- 39. Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
-+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
-; Type                                                                                    ; Slack       ; Required Time                     ; Actual Time                                    ; From                                                                                                                                                                     ; To                                                                                                                                                                                            ; From Clock                                                               ; To Clock                                                                 ; Failed Paths ;
-+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
-; Worst-case tsu                                                                          ; -4.528 ns   ; 1.000 ns                          ; 5.528 ns                                       ; MAIN_CLK                                                                                                                                                                 ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                                                         ; --                                                                       ; MAIN_CLK                                                                 ; 6867         ;
-; Worst-case tco                                                                          ; -14.840 ns  ; 1.000 ns                          ; 15.840 ns                                      ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                                                    ; nIRQ[5]                                                                                                                                                                                       ; MAIN_CLK                                                                 ; --                                                                       ; 4976         ;
-; Worst-case tpd                                                                          ; -11.944 ns  ; 1.000 ns                          ; 12.944 ns                                      ; nFB_CS1                                                                                                                                                                  ; FB_AD[18]                                                                                                                                                                                     ; --                                                                       ; --                                                                       ; 514          ;
-; Worst-case th                                                                           ; -0.401 ns   ; 1.000 ns                          ; 1.401 ns                                       ; FB_AD[25]                                                                                                                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                                                                 ; --                                                                       ; MAIN_CLK                                                                 ; 117          ;
-; Clock Setup: 'CLK33M'                                                                   ; -5.966 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M                                                                   ; 3741         ;
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -4.615 ns   ; 24.98 MHz ( period = 40.033 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 3741         ;
-; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -4.294 ns   ; 95.92 MHz ( period = 10.425 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 3741         ;
-; Clock Setup: 'MAIN_CLK'                                                                 ; -4.261 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK                                                                 ; 27347        ;
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -2.673 ns   ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 86           ;
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -1.712 ns   ; 66.00 MHz ( period = 15.151 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 29           ;
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 1.672 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]                                                                                                    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0            ;
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 2.965 ns    ; 132.01 MHz ( period = 7.575 ns )  ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]                                          ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]                                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0            ;
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 5.299 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]                                                                                                                        ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0            ;
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 28.590 ns   ; 15.99 MHz ( period = 62.552 ns )  ; 186.15 MHz ( period = 5.372 ns )               ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0            ;
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 498.663 ns  ; 2.00 MHz ( period = 500.416 ns )  ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0            ;
-; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'   ; 1997.239 ns ; 0.50 MHz ( period = 1999.998 ns ) ; 362.45 MHz ( period = 2.759 ns )               ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]                                                                         ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]                                                                                             ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; 0            ;
-; Clock Hold: 'MAIN_CLK'                                                                  ; -3.786 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                                            ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                                                 ; MAIN_CLK                                                                 ; MAIN_CLK                                                                 ; 108          ;
-; Clock Hold: 'CLK33M'                                                                    ; -0.687 ns   ; 33.00 MHz ( period = 30.303 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; CLK33M                                                                   ; CLK33M                                                                   ; 26           ;
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'  ; -0.454 ns   ; 24.98 MHz ( period = 40.033 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 26           ;
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'  ; 0.502 ns    ; 15.99 MHz ( period = 62.552 ns )  ; N/A                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0            ;
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'  ; 0.502 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                                     ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0            ;
-; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'  ; 0.502 ns    ; 95.92 MHz ( period = 10.425 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0            ;
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'  ; 0.564 ns    ; 2.00 MHz ( period = 500.416 ns )  ; N/A                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0            ;
-; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'    ; 0.825 ns    ; 0.50 MHz ( period = 1999.998 ns ) ; N/A                                            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]                                                                        ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]                                                                                             ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ; 0            ;
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'  ; 1.825 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                                        ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0            ;
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'  ; 2.664 ns    ; 66.00 MHz ( period = 15.151 ns )  ; N/A                                            ; FB_ALE                                                                                                                                                                   ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0            ;
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'  ; 3.263 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                                   ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0            ;
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'  ; 4.336 ns    ; 132.01 MHz ( period = 7.575 ns )  ; N/A                                            ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]                                          ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]                                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0            ;
-; Total number of failed paths                                                            ;             ;                                   ;                                                ;                                                                                                                                                                          ;                                                                                                                                                                                               ;                                                                          ;                                                                          ; 51319        ;
-+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Settings                                                                                                                                                              ;
-+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
-; Option                                                                                               ; Setting            ; From            ; To                        ; Entity Name ;
-+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
-; Device Name                                                                                          ; EP3C40F484C6       ;                 ;                           ;             ;
-; Timing Models                                                                                        ; Final              ;                 ;                           ;             ;
-; Default hold multicycle                                                                              ; Same as Multicycle ;                 ;                           ;             ;
-; Cut paths between unrelated clock domains                                                            ; On                 ;                 ;                           ;             ;
-; Cut off read during write signal paths                                                               ; On                 ;                 ;                           ;             ;
-; Cut off feedback from I/O pins                                                                       ; On                 ;                 ;                           ;             ;
-; Report Combined Fast/Slow Timing                                                                     ; Off                ;                 ;                           ;             ;
-; tpd Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
-; th Requirement                                                                                       ; 1 ns               ;                 ;                           ;             ;
-; tsu Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
-; tco Requirement                                                                                      ; 1 ns               ;                 ;                           ;             ;
-; fmax Requirement                                                                                     ; 30 ns              ;                 ;                           ;             ;
-; Ignore Clock Settings                                                                                ; Off                ;                 ;                           ;             ;
-; Analyze latches as synchronous elements                                                              ; On                 ;                 ;                           ;             ;
-; Enable Recovery/Removal analysis                                                                     ; Off                ;                 ;                           ;             ;
-; Enable Clock Latency                                                                                 ; Off                ;                 ;                           ;             ;
-; Use TimeQuest Timing Analyzer                                                                        ; Off                ;                 ;                           ;             ;
-; Nominal Core Supply Voltage                                                                          ; 1.2V               ;                 ;                           ;             ;
-; Minimum Core Junction Temperature                                                                    ; 0                  ;                 ;                           ;             ;
-; Maximum Core Junction Temperature                                                                    ; 85                 ;                 ;                           ;             ;
-; Number of source nodes to report per destination node                                                ; 10                 ;                 ;                           ;             ;
-; Number of destination nodes to report                                                                ; 10                 ;                 ;                           ;             ;
-; Number of paths to report                                                                            ; 200                ;                 ;                           ;             ;
-; Report Minimum Timing Checks                                                                         ; Off                ;                 ;                           ;             ;
-; Use Fast Timing Models                                                                               ; Off                ;                 ;                           ;             ;
-; Report IO Paths Separately                                                                           ; Off                ;                 ;                           ;             ;
-; Perform Multicorner Analysis                                                                         ; On                 ;                 ;                           ;             ;
-; Reports the worst-case path for each clock domain and analysis                                       ; Off                ;                 ;                           ;             ;
-; Reports worst-case timing paths for each clock domain and analysis                                   ; On                 ;                 ;                           ;             ;
-; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100                ;                 ;                           ;             ;
-; Removes common clock path pessimism (CCPP) during slack computation                                  ; On                 ;                 ;                           ;             ;
-; Output I/O Timing Endpoint                                                                           ; Near End           ;                 ;                           ;             ;
-; Cut Timing Path                                                                                      ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_0hh1 ;
-; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe17|dffe18a ; dcfifo_0hh1 ;
-; Cut Timing Path                                                                                      ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_3fh1 ;
-; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe15|dffe16a ; dcfifo_3fh1 ;
-; Cut Timing Path                                                                                      ; On                 ; rdptr_g         ; ws_dgrp|dffpipe22|dffe23a ; dcfifo_8fi1 ;
-; Input Maximum Delay                                                                                  ; 4 ns               ; *               ; FB_ALE                    ;             ;
-; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; BA                        ;             ;
-; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; VA                        ;             ;
-; Maximum Delay                                                                                        ; 5 ns               ; FB_AD           ; nVRAS                     ;             ;
-+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Settings Summary                                                                                                                                                                                                                           ;
-+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
-; Clock Node Name                                                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
-+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]   ;                    ; PLL output ; 0.5 MHz          ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 1                     ; 66                  ; -9.578 ns ;              ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]   ;                    ; PLL output ; 2.46 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 67                    ; 900                 ; -9.578 ns ;              ;
-; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]   ;                    ; PLL output ; 24.57 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 67                    ; 90                  ; -9.578 ns ;              ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ;                    ; PLL output ; 2.0 MHz          ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 1800                ; -1.864 ns ;              ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ;                    ; PLL output ; 15.99 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 225                 ; -1.864 ns ;              ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ;                    ; PLL output ; 24.98 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 144                 ; -1.864 ns ;              ;
-; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ;                    ; PLL output ; 47.96 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 109                   ; 75                  ; -1.864 ns ;              ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; -3.620 ns ;              ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; -1.094 ns ;              ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; 2.693 ns  ;              ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ;                    ; PLL output ; 132.01 MHz       ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 4                     ; 1                   ; 1.115 ns  ;              ;
-; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ;                    ; PLL output ; 66.0 MHz         ; 0.000 ns      ; 0.000 ns     ; MAIN_CLK ; 2                     ; 1                   ; -4.884 ns ;              ;
-; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ;                    ; PLL output ; 95.92 MHz        ; 0.000 ns      ; 0.000 ns     ; CLK33M   ; 218                   ; 75                  ; -2.843 ns ;              ;
-; CLK33M                                                                   ;                    ; User Pin   ; 33.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
-; MAIN_CLK                                                                 ;                    ; User Pin   ; 33.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
-+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation                ;
-+----------------------------+--------+
-; Processors                 ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 4      ;
-; Maximum allowed            ; 1      ;
-+----------------------------+--------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                   ;
-+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack       ; Actual fmax (period)                        ; From                                                                                              ; To                                                                                                ; From Clock                                                             ; To Clock                                                               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 1997.239 ns ; 362.45 MHz ( period = 2.759 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.574 ns                ;
-; 1997.297 ns ; 370.23 MHz ( period = 2.701 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.516 ns                ;
-; 1997.355 ns ; 378.36 MHz ( period = 2.643 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.458 ns                ;
-; 1997.413 ns ; 386.85 MHz ( period = 2.585 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.400 ns                ;
-; 1997.476 ns ; 396.51 MHz ( period = 2.522 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.337 ns                ;
-; 1997.531 ns ; 405.35 MHz ( period = 2.467 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.282 ns                ;
-; 1997.593 ns ; 415.80 MHz ( period = 2.405 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.220 ns                ;
-; 1997.626 ns ; 421.59 MHz ( period = 2.372 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.187 ns                ;
-; 1997.647 ns ; 425.35 MHz ( period = 2.351 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.166 ns                ;
-; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.129 ns                ;
-; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.129 ns                ;
-; 1997.709 ns ; 436.87 MHz ( period = 2.289 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.104 ns                ;
-; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
-; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
-; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.071 ns                ;
-; 1997.765 ns ; 447.83 MHz ( period = 2.233 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 2.049 ns                ;
-; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
-; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
-; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
-; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 2.013 ns                ;
-; 1997.822 ns ; 459.56 MHz ( period = 2.176 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.992 ns                ;
-; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
-; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
-; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
-; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.955 ns                ;
-; 1997.863 ns ; 468.38 MHz ( period = 2.135 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.950 ns                ;
-; 1997.880 ns ; 472.14 MHz ( period = 2.118 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.934 ns                ;
-; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
-; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
-; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
-; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.897 ns                ;
-; 1997.918 ns ; 480.77 MHz ( period = 2.080 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.895 ns                ;
-; 1997.921 ns ; 481.46 MHz ( period = 2.077 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.892 ns                ;
-; 1997.941 ns ; 486.14 MHz ( period = 2.057 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.873 ns                ;
-; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
-; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
-; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
-; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.839 ns                ;
-; 1997.976 ns ; 494.56 MHz ( period = 2.022 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.837 ns                ;
-; 1997.979 ns ; 495.29 MHz ( period = 2.019 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.834 ns                ;
-; 1997.980 ns ; 495.54 MHz ( period = 2.018 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.833 ns                ;
-; 1997.995 ns ; 499.25 MHz ( period = 2.003 ns )            ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.819 ns                ;
-; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
-; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
-; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
-; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.781 ns                ;
-; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.779 ns                ;
-; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.779 ns                ;
-; 1998.037 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.776 ns                ;
-; 1998.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.775 ns                ;
-; 1998.055 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.759 ns                ;
-; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
-; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
-; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.723 ns                ;
-; 1998.091 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.723 ns                ;
-; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.721 ns                ;
-; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.721 ns                ;
-; 1998.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.718 ns                ;
-; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.717 ns                ;
-; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.717 ns                ;
-; 1998.113 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.701 ns                ;
-; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.665 ns                ;
-; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.665 ns                ;
-; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.665 ns                ;
-; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.665 ns                ;
-; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.663 ns                ;
-; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.663 ns                ;
-; 1998.152 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.662 ns                ;
-; 1998.153 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.660 ns                ;
-; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.659 ns                ;
-; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.659 ns                ;
-; 1998.167 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.647 ns                ;
-; 1998.206 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.607 ns                ;
-; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
-; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
-; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.607 ns                ;
-; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.605 ns                ;
-; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.605 ns                ;
-; 1998.209 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.605 ns                ;
-; 1998.210 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.604 ns                ;
-; 1998.211 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.602 ns                ;
-; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.601 ns                ;
-; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.601 ns                ;
-; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
-; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
-; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
-; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.549 ns                ;
-; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.547 ns                ;
-; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.547 ns                ;
-; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.547 ns                ;
-; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.547 ns                ;
-; 1998.268 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.546 ns                ;
-; 1998.269 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.544 ns                ;
-; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.543 ns                ;
-; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.543 ns                ;
-; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
-; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
-; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
-; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.491 ns                ;
-; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.489 ns                ;
-; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.489 ns                ;
-; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.489 ns                ;
-; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.489 ns                ;
-; 1998.326 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.488 ns                ;
-; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.486 ns                ;
-; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.485 ns                ;
-; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.485 ns                ;
-; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.486 ns                ;
-; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
-; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
-; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
-; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.433 ns                ;
-; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.432 ns                ;
-; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.431 ns                ;
-; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
-; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
-; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.431 ns                ;
-; 1998.384 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.430 ns                ;
-; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.428 ns                ;
-; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.427 ns                ;
-; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.427 ns                ;
-; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.428 ns                ;
-; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
-; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
-; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
-; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.375 ns                ;
-; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.374 ns                ;
-; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.373 ns                ;
-; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
-; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
-; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.373 ns                ;
-; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.372 ns                ;
-; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.372 ns                ;
-; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.370 ns                ;
-; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.369 ns                ;
-; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.370 ns                ;
-; 1998.445 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.369 ns                ;
-; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
-; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
-; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
-; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.317 ns                ;
-; 1998.498 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.316 ns                ;
-; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
-; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
-; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
-; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.315 ns                ;
-; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
-; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
-; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.314 ns                ;
-; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.312 ns                ;
-; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.813 ns               ; 1.311 ns                ;
-; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.312 ns                ;
-; 1998.503 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.311 ns                ;
-; 1998.671 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 1.143 ns                ;
-; 1999.023 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.791 ns                ;
-; 1999.024 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.790 ns                ;
-; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.789 ns                ;
-; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.789 ns                ;
-; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
-; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
-; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.788 ns                ;
-; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
-; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
-; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
-; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
-; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.787 ns                ;
-; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.786 ns                ;
-; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.786 ns                ;
-; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.785 ns                ;
-; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.785 ns                ;
-; 1999.031 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns                 ; 1999.814 ns               ; 0.783 ns                ;
-+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                    ;
-+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack      ; Actual fmax (period)                        ; From                                                                      ; To                                                                        ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
-; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
-; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
-; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
-; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.569 ns                ;
-; 498.729 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.503 ns                ;
-; 498.743 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.489 ns                ;
-; 498.787 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.445 ns                ;
-; 498.800 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.432 ns                ;
-; 498.801 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.431 ns                ;
-; 498.858 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.374 ns                ;
-; 498.859 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.373 ns                ;
-; 498.894 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.338 ns                ;
-; 498.916 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.316 ns                ;
-; 498.917 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 1.315 ns                ;
-; 499.319 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.913 ns                ;
-; 499.422 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.810 ns                ;
-; 499.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.788 ns                ;
-; 499.449 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns                  ; 500.232 ns                ; 0.783 ns                ;
-+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                ; To                                                                                                                                                                                                              ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 28.590 ns                               ; 186.15 MHz ( period = 5.372 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns                   ; 31.135 ns                 ; 2.545 ns                ;
-; 28.759 ns                               ; 198.65 MHz ( period = 5.034 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns                   ; 31.135 ns                 ; 2.376 ns                ;
-; 54.429 ns                               ; 123.11 MHz ( period = 8.123 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.941 ns                ;
-; 54.452 ns                               ; 123.46 MHz ( period = 8.100 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.920 ns                ;
-; 54.563 ns                               ; 125.17 MHz ( period = 7.989 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.803 ns                ;
-; 54.586 ns                               ; 125.53 MHz ( period = 7.966 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.782 ns                ;
-; 54.600 ns                               ; 125.75 MHz ( period = 7.952 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.766 ns                ;
-; 54.623 ns                               ; 126.12 MHz ( period = 7.929 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.745 ns                ;
-; 54.812 ns                               ; 129.20 MHz ( period = 7.740 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.551 ns                ;
-; 54.822 ns                               ; 129.37 MHz ( period = 7.730 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.550 ns                ;
-; 54.835 ns                               ; 129.58 MHz ( period = 7.717 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.530 ns                ;
-; 54.845 ns                               ; 129.75 MHz ( period = 7.707 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.374 ns                 ; 7.529 ns                ;
-; 54.868 ns                               ; 130.14 MHz ( period = 7.684 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.491 ns                ;
-; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.474 ns                ;
-; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
-; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
-; 54.889 ns                               ; 130.50 MHz ( period = 7.663 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.481 ns                ;
-; 54.910 ns                               ; 130.86 MHz ( period = 7.642 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.456 ns                ;
-; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.453 ns                ;
-; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
-; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
-; 54.912 ns                               ; 130.89 MHz ( period = 7.640 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.460 ns                ;
-; 54.933 ns                               ; 131.25 MHz ( period = 7.619 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.435 ns                ;
-; 54.944 ns                               ; 131.44 MHz ( period = 7.608 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.417 ns                ;
-; 54.947 ns                               ; 131.49 MHz ( period = 7.605 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.414 ns                ;
-; 54.948 ns                               ; 131.51 MHz ( period = 7.604 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.413 ns                ;
-; 54.948 ns                               ; 131.51 MHz ( period = 7.604 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.413 ns                ;
-; 54.967 ns                               ; 131.84 MHz ( period = 7.585 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.396 ns                ;
-; 54.970 ns                               ; 131.89 MHz ( period = 7.582 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.393 ns                ;
-; 54.971 ns                               ; 131.91 MHz ( period = 7.581 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.392 ns                ;
-; 54.971 ns                               ; 131.91 MHz ( period = 7.581 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.392 ns                ;
-; 54.979 ns                               ; 132.05 MHz ( period = 7.573 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.382 ns                ;
-; 54.981 ns                               ; 132.08 MHz ( period = 7.571 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.387 ns                ;
-; 54.996 ns                               ; 132.35 MHz ( period = 7.556 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.374 ns                ;
-; 55.002 ns                               ; 132.45 MHz ( period = 7.550 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.361 ns                ;
-; 55.002 ns                               ; 132.45 MHz ( period = 7.550 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.353 ns                ;
-; 55.010 ns                               ; 132.59 MHz ( period = 7.542 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.362 ns                ;
-; 55.035 ns                               ; 133.03 MHz ( period = 7.517 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.326 ns                ;
-; 55.039 ns                               ; 133.10 MHz ( period = 7.513 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.316 ns                ;
-; 55.047 ns                               ; 133.24 MHz ( period = 7.505 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.312 ns                ;
-; 55.078 ns                               ; 133.80 MHz ( period = 7.474 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.291 ns                ;
-; 55.090 ns                               ; 134.01 MHz ( period = 7.462 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.270 ns                ;
-; 55.094 ns                               ; 134.08 MHz ( period = 7.458 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.266 ns                ;
-; 55.101 ns                               ; 134.21 MHz ( period = 7.451 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.371 ns                 ; 7.270 ns                ;
-; 55.102 ns                               ; 134.23 MHz ( period = 7.450 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.259 ns                ;
-; 55.104 ns                               ; 134.26 MHz ( period = 7.448 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.257 ns                ;
-; 55.113 ns                               ; 134.43 MHz ( period = 7.439 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.249 ns                ;
-; 55.113 ns                               ; 134.43 MHz ( period = 7.439 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.248 ns                ;
-; 55.115 ns                               ; 134.46 MHz ( period = 7.437 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.249 ns                ;
-; 55.117 ns                               ; 134.50 MHz ( period = 7.435 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.245 ns                ;
-; 55.125 ns                               ; 134.64 MHz ( period = 7.427 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.238 ns                ;
-; 55.127 ns                               ; 134.68 MHz ( period = 7.425 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.236 ns                ;
-; 55.127 ns                               ; 134.68 MHz ( period = 7.425 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.243 ns                ;
-; 55.130 ns                               ; 134.73 MHz ( period = 7.422 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.236 ns                ;
-; 55.136 ns                               ; 134.84 MHz ( period = 7.416 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.227 ns                ;
-; 55.140 ns                               ; 134.92 MHz ( period = 7.412 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.232 ns                ;
-; 55.144 ns                               ; 134.99 MHz ( period = 7.408 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.224 ns                ;
-; 55.152 ns                               ; 135.14 MHz ( period = 7.400 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.212 ns                ;
-; 55.152 ns                               ; 135.14 MHz ( period = 7.400 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.218 ns                ;
-; 55.161 ns                               ; 135.30 MHz ( period = 7.391 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.208 ns                ;
-; 55.167 ns                               ; 135.41 MHz ( period = 7.385 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.199 ns                ;
-; 55.169 ns                               ; 135.45 MHz ( period = 7.383 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.357 ns                 ; 7.188 ns                ;
-; 55.181 ns                               ; 135.67 MHz ( period = 7.371 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.174 ns                ;
-; 55.181 ns                               ; 135.67 MHz ( period = 7.371 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.187 ns                ;
-; 55.190 ns                               ; 135.83 MHz ( period = 7.362 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.169 ns                ;
-; 55.204 ns                               ; 136.09 MHz ( period = 7.348 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.166 ns                ;
-; 55.206 ns                               ; 136.13 MHz ( period = 7.346 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.357 ns                 ; 7.151 ns                ;
-; 55.218 ns                               ; 136.35 MHz ( period = 7.334 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.137 ns                ;
-; 55.227 ns                               ; 136.52 MHz ( period = 7.325 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.145 ns                ;
-; 55.251 ns                               ; 136.97 MHz ( period = 7.301 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 7.101 ns                ;
-; 55.261 ns                               ; 137.16 MHz ( period = 7.291 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.105 ns                ;
-; 55.261 ns                               ; 137.16 MHz ( period = 7.291 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.100 ns                ;
-; 55.272 ns                               ; 137.36 MHz ( period = 7.280 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.369 ns                 ; 7.097 ns                ;
-; 55.274 ns                               ; 137.40 MHz ( period = 7.278 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.094 ns                ;
-; 55.278 ns                               ; 137.48 MHz ( period = 7.274 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[2]    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.274 ns                 ; 6.996 ns                ;
-; 55.286 ns                               ; 137.63 MHz ( period = 7.266 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.080 ns                ;
-; 55.288 ns                               ; 137.67 MHz ( period = 7.264 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 7.084 ns                ;
-; 55.294 ns                               ; 137.78 MHz ( period = 7.258 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.076 ns                ;
-; 55.295 ns                               ; 137.80 MHz ( period = 7.257 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.070 ns                ;
-; 55.298 ns                               ; 137.85 MHz ( period = 7.254 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.068 ns                ;
-; 55.299 ns                               ; 137.87 MHz ( period = 7.253 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.065 ns                ;
-; 55.300 ns                               ; 137.89 MHz ( period = 7.252 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.068 ns                ;
-; 55.303 ns                               ; 137.95 MHz ( period = 7.249 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 7.061 ns                ;
-; 55.311 ns                               ; 138.10 MHz ( period = 7.241 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.057 ns                ;
-; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.045 ns                ;
-; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.045 ns                ;
-; 55.316 ns                               ; 138.20 MHz ( period = 7.236 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.052 ns                ;
-; 55.317 ns                               ; 138.22 MHz ( period = 7.235 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.044 ns                ;
-; 55.319 ns                               ; 138.26 MHz ( period = 7.233 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 7.042 ns                ;
-; 55.322 ns                               ; 138.31 MHz ( period = 7.230 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.044 ns                ;
-; 55.323 ns                               ; 138.33 MHz ( period = 7.229 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.043 ns                ;
-; 55.323 ns                               ; 138.33 MHz ( period = 7.229 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.047 ns                ;
-; 55.324 ns                               ; 138.35 MHz ( period = 7.228 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.031 ns                ;
-; 55.326 ns                               ; 138.39 MHz ( period = 7.226 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.040 ns                ;
-; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 7.024 ns                ;
-; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
-; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
-; 55.328 ns                               ; 138.43 MHz ( period = 7.224 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 7.031 ns                ;
-; 55.331 ns                               ; 138.48 MHz ( period = 7.221 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.032 ns                ;
-; 55.331 ns                               ; 138.48 MHz ( period = 7.221 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.029 ns                ;
-; 55.332 ns                               ; 138.50 MHz ( period = 7.220 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.028 ns                ;
-; 55.332 ns                               ; 138.50 MHz ( period = 7.220 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.033 ns                ;
-; 55.333 ns                               ; 138.52 MHz ( period = 7.219 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.027 ns                ;
-; 55.333 ns                               ; 138.52 MHz ( period = 7.219 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.027 ns                ;
-; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.024 ns                ;
-; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.024 ns                ;
-; 55.339 ns                               ; 138.64 MHz ( period = 7.213 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 7.031 ns                ;
-; 55.340 ns                               ; 138.66 MHz ( period = 7.212 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.023 ns                ;
-; 55.341 ns                               ; 138.68 MHz ( period = 7.211 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.019 ns                ;
-; 55.342 ns                               ; 138.70 MHz ( period = 7.210 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 7.021 ns                ;
-; 55.344 ns                               ; 138.73 MHz ( period = 7.208 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.360 ns                 ; 7.016 ns                ;
-; 55.344 ns                               ; 138.73 MHz ( period = 7.208 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 7.022 ns                ;
-; 55.349 ns                               ; 138.83 MHz ( period = 7.203 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 7.006 ns                ;
-; 55.354 ns                               ; 138.93 MHz ( period = 7.198 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 7.011 ns                ;
-; 55.354 ns                               ; 138.93 MHz ( period = 7.198 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.008 ns                ;
-; 55.355 ns                               ; 138.95 MHz ( period = 7.197 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.007 ns                ;
-; 55.356 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.006 ns                ;
-; 55.356 ns                               ; 138.97 MHz ( period = 7.196 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 7.006 ns                ;
-; 55.361 ns                               ; 139.06 MHz ( period = 7.191 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.355 ns                 ; 6.994 ns                ;
-; 55.364 ns                               ; 139.12 MHz ( period = 7.188 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.997 ns                ;
-; 55.364 ns                               ; 139.12 MHz ( period = 7.188 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 6.998 ns                ;
-; 55.367 ns                               ; 139.18 MHz ( period = 7.185 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.362 ns                 ; 6.995 ns                ;
-; 55.367 ns                               ; 139.18 MHz ( period = 7.185 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 7.001 ns                ;
-; 55.374 ns                               ; 139.31 MHz ( period = 7.178 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.996 ns                ;
-; 55.376 ns                               ; 139.35 MHz ( period = 7.176 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.987 ns                ;
-; 55.379 ns                               ; 139.41 MHz ( period = 7.173 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.984 ns                ;
-; 55.383 ns                               ; 139.49 MHz ( period = 7.169 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.980 ns                ;
-; 55.383 ns                               ; 139.49 MHz ( period = 7.169 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.967 ns                ;
-; 55.384 ns                               ; 139.51 MHz ( period = 7.168 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.986 ns                ;
-; 55.386 ns                               ; 139.55 MHz ( period = 7.166 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.964 ns                ;
-; 55.386 ns                               ; 139.55 MHz ( period = 7.166 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.982 ns                ;
-; 55.387 ns                               ; 139.57 MHz ( period = 7.165 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.963 ns                ;
-; 55.387 ns                               ; 139.57 MHz ( period = 7.165 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.963 ns                ;
-; 55.389 ns                               ; 139.61 MHz ( period = 7.163 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.983 ns                ;
-; 55.393 ns                               ; 139.68 MHz ( period = 7.159 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.972 ns                ;
-; 55.399 ns                               ; 139.80 MHz ( period = 7.153 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.966 ns                ;
-; 55.403 ns                               ; 139.88 MHz ( period = 7.149 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.374 ns                 ; 6.971 ns                ;
-; 55.406 ns                               ; 139.94 MHz ( period = 7.146 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.959 ns                ;
-; 55.406 ns                               ; 139.94 MHz ( period = 7.146 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.959 ns                ;
-; 55.408 ns                               ; 139.98 MHz ( period = 7.144 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.739 ns                 ; 7.331 ns                ;
-; 55.409 ns                               ; 140.00 MHz ( period = 7.143 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.961 ns                ;
-; 55.415 ns                               ; 140.11 MHz ( period = 7.137 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.944 ns                ;
-; 55.418 ns                               ; 140.17 MHz ( period = 7.134 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.354 ns                 ; 6.936 ns                ;
-; 55.418 ns                               ; 140.17 MHz ( period = 7.134 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.350 ns                 ; 6.932 ns                ;
-; 55.422 ns                               ; 140.25 MHz ( period = 7.130 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.946 ns                ;
-; 55.428 ns                               ; 140.37 MHz ( period = 7.124 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.938 ns                ;
-; 55.428 ns                               ; 140.37 MHz ( period = 7.124 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.935 ns                ;
-; 55.430 ns                               ; 140.41 MHz ( period = 7.122 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 6.922 ns                ;
-; 55.440 ns                               ; 140.61 MHz ( period = 7.112 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.921 ns                ;
-; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.920 ns                ;
-; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
-; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
-; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.927 ns                ;
-; 55.441 ns                               ; 140.63 MHz ( period = 7.111 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.918 ns                ;
-; 55.443 ns                               ; 140.67 MHz ( period = 7.109 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.922 ns                ;
-; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.907 ns                ;
-; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
-; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
-; 55.456 ns                               ; 140.92 MHz ( period = 7.096 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.914 ns                ;
-; 55.459 ns                               ; 140.98 MHz ( period = 7.093 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.909 ns                ;
-; 55.462 ns                               ; 141.04 MHz ( period = 7.090 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.902 ns                ;
-; 55.463 ns                               ; 141.06 MHz ( period = 7.089 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.901 ns                ;
-; 55.465 ns                               ; 141.10 MHz ( period = 7.087 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.901 ns                ;
-; 55.467 ns                               ; 141.14 MHz ( period = 7.085 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.897 ns                ;
-; 55.469 ns                               ; 141.18 MHz ( period = 7.083 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.895 ns                ;
-; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.365 ns                 ; 6.895 ns                ;
-; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
-; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
-; 55.470 ns                               ; 141.20 MHz ( period = 7.082 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.372 ns                 ; 6.902 ns                ;
-; 55.471 ns                               ; 141.22 MHz ( period = 7.081 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.364 ns                 ; 6.893 ns                ;
-; 55.477 ns                               ; 141.34 MHz ( period = 7.075 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.889 ns                ;
-; 55.478 ns                               ; 141.36 MHz ( period = 7.074 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.890 ns                ;
-; 55.480 ns                               ; 141.40 MHz ( period = 7.072 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.888 ns                ;
-; 55.483 ns                               ; 141.46 MHz ( period = 7.069 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.885 ns                ;
-; 55.486 ns                               ; 141.52 MHz ( period = 7.066 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.880 ns                ;
-; 55.487 ns                               ; 141.54 MHz ( period = 7.065 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.883 ns                ;
-; 55.490 ns                               ; 141.60 MHz ( period = 7.062 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.278 ns                 ; 6.788 ns                ;
-; 55.490 ns                               ; 141.60 MHz ( period = 7.062 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.876 ns                ;
-; 55.491 ns                               ; 141.62 MHz ( period = 7.061 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.368 ns                 ; 6.877 ns                ;
-; 55.492 ns                               ; 141.64 MHz ( period = 7.060 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.874 ns                ;
-; 55.494 ns                               ; 141.68 MHz ( period = 7.058 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.366 ns                 ; 6.872 ns                ;
-; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.354 ns                 ; 6.859 ns                ;
-; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
-; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
-; 55.495 ns                               ; 141.70 MHz ( period = 7.057 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.866 ns                ;
-; 55.496 ns                               ; 141.72 MHz ( period = 7.056 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.863 ns                ;
-; 55.497 ns                               ; 141.74 MHz ( period = 7.055 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.866 ns                ;
-; 55.499 ns                               ; 141.78 MHz ( period = 7.053 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.860 ns                ;
-; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.859 ns                ;
-; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.361 ns                 ; 6.861 ns                ;
-; 55.500 ns                               ; 141.80 MHz ( period = 7.052 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.859 ns                ;
-; 55.501 ns                               ; 141.82 MHz ( period = 7.051 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9]                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.869 ns                ;
-; 55.503 ns                               ; 141.86 MHz ( period = 7.049 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.867 ns                ;
-; 55.506 ns                               ; 141.92 MHz ( period = 7.046 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.370 ns                 ; 6.864 ns                ;
-; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.352 ns                 ; 6.845 ns                ;
-; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
-; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
-; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_CRC                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.856 ns                ;
-; 55.507 ns                               ; 141.94 MHz ( period = 7.045 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.359 ns                 ; 6.852 ns                ;
-; 55.508 ns                               ; 141.96 MHz ( period = 7.044 ns )                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_TRACK                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns                   ; 62.363 ns                 ; 6.855 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                     ;                                                                                                                                                                                                                 ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; -4.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.928 ns                 ; 3.687 ns                ;
-; -4.573 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.921 ns                 ; 3.652 ns                ;
-; -4.568 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.642 ns                ;
-; -4.562 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.915 ns                 ; 3.647 ns                ;
-; -4.553 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.635 ns                ;
-; -4.549 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.631 ns                ;
-; -4.541 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.928 ns                 ; 3.613 ns                ;
-; -4.533 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.610 ns                ;
-; -4.526 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.918 ns                 ; 3.608 ns                ;
-; -4.479 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.898 ns                ;
-; -4.440 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.141 ns                ;
-; -4.440 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.517 ns                ;
-; -4.413 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.114 ns                ;
-; -4.409 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.486 ns                ;
-; -4.407 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.916 ns                 ; 3.491 ns                ;
-; -4.406 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.914 ns                 ; 3.492 ns                ;
-; -4.394 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.468 ns                ;
-; -4.391 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.465 ns                ;
-; -4.391 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.466 ns                ;
-; -4.386 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.461 ns                ;
-; -4.381 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.458 ns                ;
-; -4.378 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.455 ns                ;
-; -4.372 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.447 ns                ;
-; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.447 ns                ;
-; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.447 ns                ;
-; -4.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.445 ns                ;
-; -4.369 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 4.068 ns                ;
-; -4.367 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.444 ns                ;
-; -4.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.441 ns                ;
-; -4.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.441 ns                ;
-; -4.364 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.441 ns                ;
-; -4.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 4.063 ns                ;
-; -4.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.440 ns                ;
-; -4.361 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.436 ns                ;
-; -4.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.434 ns                ;
-; -4.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.435 ns                ;
-; -4.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.431 ns                ;
-; -4.356 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.433 ns                ;
-; -4.353 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.428 ns                ;
-; -4.353 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.428 ns                ;
-; -4.351 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.931 ns                 ; 3.420 ns                ;
-; -4.348 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.426 ns                ;
-; -4.318 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.916 ns                 ; 3.402 ns                ;
-; -4.316 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.919 ns                 ; 3.397 ns                ;
-; -4.308 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 4.008 ns                ;
-; -4.306 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.725 ns                ;
-; -4.305 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.379 ns                ;
-; -4.301 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 4.002 ns                ;
-; -4.299 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.376 ns                ;
-; -4.298 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.924 ns                 ; 3.374 ns                ;
-; -4.297 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.374 ns                ;
-; -4.294 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.372 ns                ;
-; -4.293 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.370 ns                ;
-; -4.293 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.922 ns                 ; 3.371 ns                ;
-; -4.290 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.365 ns                ;
-; -4.289 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.366 ns                ;
-; -4.289 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.364 ns                ;
-; -4.288 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.363 ns                ;
-; -4.279 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.356 ns                ;
-; -4.278 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.355 ns                ;
-; -4.277 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.354 ns                ;
-; -4.273 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.347 ns                ;
-; -4.271 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.972 ns                ;
-; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.970 ns                ;
-; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.343 ns                ;
-; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.346 ns                ;
-; -4.269 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.346 ns                ;
-; -4.268 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.345 ns                ;
-; -4.268 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.345 ns                ;
-; -4.267 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.344 ns                ;
-; -4.266 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.343 ns                ;
-; -4.264 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.341 ns                ;
-; -4.264 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.341 ns                ;
-; -4.262 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.339 ns                ;
-; -4.262 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.339 ns                ;
-; -4.259 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.960 ns                ;
-; -4.259 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.334 ns                ;
-; -4.258 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.332 ns                ;
-; -4.256 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.333 ns                ;
-; -4.256 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.333 ns                ;
-; -4.255 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.329 ns                ;
-; -4.255 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.330 ns                ;
-; -4.253 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.330 ns                ;
-; -4.253 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.327 ns                ;
-; -4.251 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.328 ns                ;
-; -4.248 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.325 ns                ;
-; -4.247 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.324 ns                ;
-; -4.246 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.323 ns                ;
-; -4.245 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.319 ns                ;
-; -4.243 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.944 ns                ;
-; -4.241 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.316 ns                ;
-; -4.236 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.310 ns                ;
-; -4.230 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.929 ns                ;
-; -4.229 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.928 ns                ;
-; -4.219 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.919 ns                ;
-; -4.217 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.292 ns                ;
-; -4.215 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.916 ns                ;
-; -4.203 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.904 ns                ;
-; -4.199 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.899 ns                ;
-; -4.195 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.614 ns                ;
-; -4.194 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.269 ns                ;
-; -4.190 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.257 ns                ;
-; -4.188 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.887 ns                ;
-; -4.188 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.624 ns                 ; 3.564 ns                ;
-; -4.179 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.931 ns                 ; 3.248 ns                ;
-; -4.175 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.876 ns                ;
-; -4.172 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.591 ns                ;
-; -4.156 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.855 ns                ;
-; -4.154 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.551 ns                ;
-; -4.149 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.850 ns                ;
-; -4.148 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.847 ns                ;
-; -4.143 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.540 ns                ;
-; -4.142 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.612 ns                 ; 3.530 ns                ;
-; -4.140 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.624 ns                 ; 3.516 ns                ;
-; -4.139 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.216 ns                ;
-; -4.138 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.838 ns                ;
-; -4.137 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.211 ns                ;
-; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
-; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
-; -4.135 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.212 ns                ;
-; -4.134 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.211 ns                ;
-; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.210 ns                ;
-; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.208 ns                ;
-; -4.133 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.208 ns                ;
-; -4.130 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.204 ns                ;
-; -4.130 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.205 ns                ;
-; -4.128 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.205 ns                ;
-; -4.127 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.202 ns                ;
-; -4.125 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.199 ns                ;
-; -4.124 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.191 ns                ;
-; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.190 ns                ;
-; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.190 ns                ;
-; -4.113 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.616 ns                 ; 3.497 ns                ;
-; -4.109 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.186 ns                ;
-; -4.108 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.505 ns                ;
-; -4.104 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.171 ns                ;
-; -4.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.176 ns                ;
-; -4.101 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.802 ns                ;
-; -4.100 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.519 ns                ;
-; -4.098 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.936 ns                 ; 3.162 ns                ;
-; -4.098 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.495 ns                ;
-; -4.097 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.796 ns                ;
-; -4.092 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.793 ns                ;
-; -4.088 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.507 ns                ;
-; -4.083 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.480 ns                ;
-; -4.078 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.779 ns                ;
-; -4.069 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.306 ns                 ; 3.763 ns                ;
-; -4.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.612 ns                 ; 3.456 ns                ;
-; -4.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.306 ns                 ; 3.762 ns                ;
-; -4.064 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.307 ns                 ; 3.757 ns                ;
-; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.613 ns                 ; 3.436 ns                ;
-; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.442 ns                ;
-; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.442 ns                ;
-; -4.041 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.308 ns                 ; 3.733 ns                ;
-; -4.038 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.615 ns                 ; 3.423 ns                ;
-; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.938 ns                 ; 3.096 ns                ;
-; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.943 ns                 ; 3.091 ns                ;
-; -4.034 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.734 ns                ;
-; -4.024 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.613 ns                 ; 3.411 ns                ;
-; -4.019 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.438 ns                ;
-; -4.016 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.093 ns                ;
-; -4.015 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.092 ns                ;
-; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.091 ns                ;
-; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.091 ns                ;
-; -4.014 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.089 ns                ;
-; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
-; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
-; -4.012 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.089 ns                ;
-; -4.011 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.088 ns                ;
-; -4.011 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.085 ns                ;
-; -4.009 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.084 ns                ;
-; -4.006 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.080 ns                ;
-; -4.006 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.403 ns                ;
-; -4.005 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.080 ns                ;
-; -4.004 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.301 ns                 ; 3.703 ns                ;
-; -4.000 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.581 ns                 ; 3.419 ns                ;
-; -3.998 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.075 ns                ;
-; -3.998 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.299 ns                 ; 3.699 ns                ;
-; -3.996 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.073 ns                ;
-; -3.995 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.392 ns                ;
-; -3.993 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.070 ns                ;
-; -3.991 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.068 ns                ;
-; -3.989 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.938 ns                 ; 3.051 ns                ;
-; -3.989 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.610 ns                 ; 3.379 ns                ;
-; -3.988 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.923 ns                 ; 3.065 ns                ;
-; -3.986 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.061 ns                ;
-; -3.986 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.061 ns                ;
-; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.060 ns                ;
-; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.059 ns                ;
-; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.059 ns                ;
-; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.060 ns                ;
-; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.058 ns                ;
-; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.925 ns                 ; 3.059 ns                ;
-; -3.983 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.057 ns                ;
-; -3.982 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.056 ns                ;
-; -3.981 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.926 ns                 ; 3.055 ns                ;
-; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.603 ns                 ; 3.369 ns                ;
-; -3.970 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.933 ns                 ; 3.037 ns                ;
-; -3.966 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.300 ns                 ; 3.666 ns                ;
-; -3.954 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns                    ; -0.935 ns                 ; 3.019 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                              ; To                                                                                                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; -2.673 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.814 ns                  ; 3.487 ns                ;
-; -2.447 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 3.530 ns                ;
-; -2.348 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_BANK_OK                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.155 ns                ;
-; -2.346 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.153 ns                ;
-; -2.275 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.082 ns                ;
-; -2.254 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 3.061 ns                ;
-; -2.243 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.138 ns                  ; 3.381 ns                ;
-; -2.194 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.100 ns                  ; 3.294 ns                ;
-; -2.187 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 3.262 ns                ;
-; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.239 ns                ;
-; -2.024 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.169 ns                ;
-; -2.006 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 3.151 ns                ;
-; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.132 ns                  ; 3.125 ns                ;
-; -1.990 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_FIFO_WRE                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.797 ns                ;
-; -1.911 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.140 ns                  ; 3.051 ns                ;
-; -1.896 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 2.986 ns                ;
-; -1.895 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 2.985 ns                ;
-; -1.873 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7F                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.680 ns                ;
-; -1.871 ns                               ; None                                                ; FB_ALE                                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T3                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns                    ; 0.807 ns                  ; 2.678 ns                ;
-; -1.838 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO                                                       ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC                                                                                                  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; -1.306 ns                 ; 0.532 ns                ;
-; -1.834 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.131 ns                  ; 2.965 ns                ;
-; -1.828 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.907 ns                ;
-; -1.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.906 ns                ;
-; -1.824 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.903 ns                ;
-; -1.800 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.131 ns                  ; 2.931 ns                ;
-; -1.800 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.879 ns                ;
-; -1.765 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.910 ns                ;
-; -1.763 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.132 ns                  ; 2.895 ns                ;
-; -1.755 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.136 ns                  ; 2.891 ns                ;
-; -1.647 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.133 ns                  ; 2.780 ns                ;
-; -1.646 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.133 ns                  ; 2.779 ns                ;
-; -1.641 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.770 ns                ;
-; -1.610 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.739 ns                ;
-; -1.593 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.152 ns                  ; 2.745 ns                ;
-; -1.556 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.134 ns                  ; 2.690 ns                ;
-; -1.553 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.682 ns                ;
-; -1.470 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.612 ns                ;
-; -1.465 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.129 ns                  ; 2.594 ns                ;
-; -1.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.127 ns                  ; 2.590 ns                ;
-; -1.451 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.596 ns                ;
-; -1.441 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.586 ns                ;
-; -1.436 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.136 ns                  ; 2.572 ns                ;
-; -1.413 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.555 ns                ;
-; -1.361 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.506 ns                ;
-; -1.341 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.145 ns                  ; 2.486 ns                ;
-; -1.329 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.404 ns                ;
-; -1.327 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.410 ns                ;
-; -1.326 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.410 ns                ;
-; -1.302 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.385 ns                ;
-; -1.298 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.126 ns                  ; 2.424 ns                ;
-; -1.271 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 2.348 ns                ;
-; -1.252 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.335 ns                ;
-; -1.216 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.142 ns                  ; 2.358 ns                ;
-; -1.202 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.277 ns                ;
-; -1.202 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.075 ns                  ; 2.277 ns                ;
-; -1.181 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.083 ns                  ; 2.264 ns                ;
-; -1.167 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_CB8                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.246 ns                ;
-; -1.162 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8F                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.079 ns                  ; 2.241 ns                ;
-; -1.139 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.130 ns                  ; 2.269 ns                ;
-; -1.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.186 ns                ;
-; -1.077 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.140 ns                  ; 2.217 ns                ;
-; -1.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.151 ns                  ; 2.199 ns                ;
-; -1.047 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.084 ns                  ; 2.131 ns                ;
-; -0.910 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.123 ns                  ; 2.033 ns                ;
-; -0.901 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.992 ns                ;
-; -0.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.917 ns                ;
-; -0.750 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.841 ns                ;
-; -0.750 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.841 ns                ;
-; -0.741 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.832 ns                ;
-; -0.642 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.730 ns                ;
-; -0.623 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.711 ns                ;
-; -0.616 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.704 ns                ;
-; -0.600 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.088 ns                  ; 1.688 ns                ;
-; -0.596 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.087 ns                  ; 1.683 ns                ;
-; -0.413 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 1.490 ns                ;
-; -0.410 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.077 ns                  ; 1.487 ns                ;
-; -0.199 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.289 ns                ;
-; -0.193 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2B                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.090 ns                  ; 1.283 ns                ;
-; -0.191 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.282 ns                ;
-; -0.186 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.175 ns                  ; 4.361 ns                ;
-; -0.183 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.274 ns                ;
-; -0.102 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 3.040 ns                  ; 3.142 ns                ;
-; -0.068 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.171 ns                  ; 4.239 ns                ;
-; -0.062 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.175 ns                  ; 4.237 ns                ;
-; -0.041 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.162 ns                  ; 4.203 ns                ;
-; -0.024 ns                               ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.181 ns                  ; 4.205 ns                ;
-; 0.003 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.168 ns                  ; 4.165 ns                ;
-; 0.039 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.173 ns                  ; 4.134 ns                ;
-; 0.059 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[0]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns                    ; 1.091 ns                  ; 1.032 ns                ;
-; 0.073 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.171 ns                  ; 4.098 ns                ;
-; 0.080 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.167 ns                  ; 4.087 ns                ;
-; 0.108 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.181 ns                  ; 4.073 ns                ;
-; 0.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.168 ns                  ; 4.045 ns                ;
-; 0.165 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.182 ns                  ; 4.017 ns                ;
-; 0.166 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.173 ns                  ; 4.007 ns                ;
-; 0.194 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.167 ns                  ; 3.973 ns                ;
-; 0.201 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.162 ns                  ; 3.961 ns                ;
-; 0.250 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.464 ns                  ; 4.214 ns                ;
-; 0.301 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.522 ns                  ; 4.221 ns                ;
-; 0.306 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.483 ns                  ; 4.177 ns                ;
-; 0.375 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.514 ns                  ; 4.139 ns                ;
-; 0.401 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.475 ns                  ; 4.074 ns                ;
-; 0.451 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.182 ns                  ; 3.731 ns                ;
-; 0.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.477 ns                  ; 4.023 ns                ;
-; 0.467 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.473 ns                  ; 4.006 ns                ;
-; 0.509 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.503 ns                  ; 3.994 ns                ;
-; 0.514 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.469 ns                  ; 3.955 ns                ;
-; 0.539 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.484 ns                  ; 3.945 ns                ;
-; 0.568 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.823 ns                ;
-; 0.576 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.470 ns                  ; 3.894 ns                ;
-; 0.579 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.804 ns                ;
-; 0.580 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.408 ns                  ; 3.828 ns                ;
-; 0.619 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.768 ns                ;
-; 0.677 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.516 ns                  ; 3.839 ns                ;
-; 0.695 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.508 ns                  ; 3.813 ns                ;
-; 0.773 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.512 ns                  ; 3.739 ns                ;
-; 0.800 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.587 ns                ;
-; 0.805 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.582 ns                ;
-; 0.810 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.509 ns                  ; 3.699 ns                ;
-; 0.818 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2]                                                                          ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.523 ns                  ; 3.705 ns                ;
-; 0.834 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                     ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.212 ns                  ; 3.378 ns                ;
-; 0.838 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.545 ns                ;
-; 0.840 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.551 ns                ;
-; 0.841 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.551 ns                ;
-; 0.933 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.387 ns                  ; 3.454 ns                ;
-; 0.965 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.418 ns                ;
-; 0.965 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.383 ns                  ; 3.418 ns                ;
-; 1.026 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.365 ns                ;
-; 1.038 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 3.347 ns                ;
-; 1.057 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.334 ns                ;
-; 1.110 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.057 ns                  ; 2.947 ns                ;
-; 1.120 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.272 ns                ;
-; 1.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.391 ns                  ; 3.244 ns                ;
-; 1.153 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 3.245 ns                ;
-; 1.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.392 ns                  ; 3.185 ns                ;
-; 1.266 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 3.133 ns                ;
-; 1.344 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.057 ns                  ; 2.713 ns                ;
-; 1.374 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 3.024 ns                ;
-; 1.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.982 ns                ;
-; 1.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A                                                                                                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.982 ns                ;
-; 1.426 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.973 ns                ;
-; 1.426 ns                                ; 162.63 MHz ( period = 6.149 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.936 ns                ;
-; 1.427 ns                                ; 162.65 MHz ( period = 6.148 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.935 ns                ;
-; 1.481 ns                                ; 164.10 MHz ( period = 6.094 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.881 ns                ;
-; 1.482 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 2.916 ns                ;
-; 1.484 ns                                ; 164.18 MHz ( period = 6.091 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.878 ns                ;
-; 1.526 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT                                                                                                 ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 3.055 ns                  ; 1.529 ns                ;
-; 1.527 ns                                ; 165.34 MHz ( period = 6.048 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.835 ns                ;
-; 1.540 ns                                ; 165.70 MHz ( period = 6.035 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.822 ns                ;
-; 1.543 ns                                ; 165.78 MHz ( period = 6.032 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.819 ns                ;
-; 1.582 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[16]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.858 ns                  ; 3.276 ns                ;
-; 1.589 ns                                ; 167.06 MHz ( period = 5.986 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.773 ns                ;
-; 1.598 ns                                ; 167.31 MHz ( period = 5.977 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.764 ns                ;
-; 1.601 ns                                ; 167.39 MHz ( period = 5.974 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.761 ns                ;
-; 1.656 ns                                ; 168.95 MHz ( period = 5.919 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.706 ns                ;
-; 1.676 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.850 ns                  ; 3.174 ns                ;
-; 1.677 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.147 ns                ;
-; 1.679 ns                                ; 169.61 MHz ( period = 5.896 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.700 ns                ;
-; 1.680 ns                                ; 169.64 MHz ( period = 5.895 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.699 ns                ;
-; 1.686 ns                                ; 169.81 MHz ( period = 5.889 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.668 ns                ;
-; 1.687 ns                                ; 169.84 MHz ( period = 5.888 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.667 ns                ;
-; 1.714 ns                                ; 170.62 MHz ( period = 5.861 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.648 ns                ;
-; 1.734 ns                                ; 171.20 MHz ( period = 5.841 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.645 ns                ;
-; 1.737 ns                                ; 171.29 MHz ( period = 5.838 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.642 ns                ;
-; 1.738 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[21]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.841 ns                  ; 3.103 ns                ;
-; 1.741 ns                                ; 171.41 MHz ( period = 5.834 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.613 ns                ;
-; 1.744 ns                                ; 171.50 MHz ( period = 5.831 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.610 ns                ;
-; 1.746 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[21]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.841 ns                  ; 3.095 ns                ;
-; 1.747 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]   ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[1]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.865 ns                  ; 3.118 ns                ;
-; 1.750 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]  ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[26]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.866 ns                  ; 3.116 ns                ;
-; 1.756 ns                                ; 171.85 MHz ( period = 5.819 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[6]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.362 ns                  ; 5.606 ns                ;
-; 1.760 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]   ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[1]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.865 ns                  ; 3.105 ns                ;
-; 1.779 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.045 ns                ;
-; 1.780 ns                                ; 172.56 MHz ( period = 5.795 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.599 ns                ;
-; 1.787 ns                                ; 172.77 MHz ( period = 5.788 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.567 ns                ;
-; 1.792 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[24]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 3.032 ns                ;
-; 1.793 ns                                ; 172.95 MHz ( period = 5.782 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.586 ns                ;
-; 1.796 ns                                ; 173.04 MHz ( period = 5.779 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.583 ns                ;
-; 1.800 ns                                ; 173.16 MHz ( period = 5.775 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.554 ns                ;
-; 1.803 ns                                ; 173.25 MHz ( period = 5.772 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.551 ns                ;
-; 1.805 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 2.580 ns                ;
-; 1.808 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11]                                                                                                       ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.385 ns                  ; 2.577 ns                ;
-; 1.812 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[23]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.831 ns                  ; 3.019 ns                ;
-; 1.829 ns                                ; 174.03 MHz ( period = 5.746 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.525 ns                ;
-; 1.830 ns                                ; 174.06 MHz ( period = 5.745 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.524 ns                ;
-; 1.840 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.559 ns                ;
-; 1.842 ns                                ; 174.43 MHz ( period = 5.733 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.537 ns                ;
-; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.399 ns                  ; 2.557 ns                ;
-; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[28]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.824 ns                  ; 2.982 ns                ;
-; 1.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[31]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.847 ns                  ; 3.002 ns                ;
-; 1.847 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[23]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.847 ns                  ; 3.000 ns                ;
-; 1.849 ns                                ; 174.64 MHz ( period = 5.726 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.505 ns                ;
-; 1.851 ns                                ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                   ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]                                                                                                        ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns                    ; 4.398 ns                  ; 2.547 ns                ;
-; 1.851 ns                                ; 174.70 MHz ( period = 5.724 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.528 ns                ;
-; 1.854 ns                                ; 174.79 MHz ( period = 5.721 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.379 ns                  ; 5.525 ns                ;
-; 1.858 ns                                ; 174.92 MHz ( period = 5.717 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.496 ns                ;
-; 1.861 ns                                ; 175.01 MHz ( period = 5.714 ns )                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3]         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]                                                                                                        ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns                    ; 7.354 ns                  ; 5.493 ns                ;
-; 1.865 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[16]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.826 ns                  ; 2.961 ns                ;
-; 1.873 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]  ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.829 ns                  ; 2.956 ns                ;
-; 1.881 ns                                ; None                                                ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]  ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[17]                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns                    ; 4.829 ns                  ; 2.948 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                   ;                                                                                                                                                       ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
-+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack    ; Actual fmax (period)                        ; From                                                                                                                             ; To                                                                                                                                ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 2.965 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.639 ns                ;
-; 2.966 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.638 ns                ;
-; 2.967 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.637 ns                ;
-; 2.968 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.636 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.511 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.510 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.509 ns                ;
-; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
-; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
-; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.508 ns                ;
-; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
-; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
-; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
-; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
-; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns                    ; 3.604 ns                  ; 0.507 ns                ;
-+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                               ;
-+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack    ; Actual fmax (period) ; From                                              ; To                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 5.299 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.118 ns                  ; 0.819 ns                ;
-; 5.479 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.637 ns                ;
-; 5.480 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.636 ns                ;
-; 5.606 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.510 ns                ;
-; 5.608 ns ; None                 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns                    ; 6.116 ns                  ; 0.508 ns                ;
-+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                   ; To                                                                                                                                  ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; 1.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 3.636 ns                ;
-; 1.683 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.304 ns                  ; 3.621 ns                ;
-; 1.703 ns                                ; 170.30 MHz ( period = 5.872 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 5.190 ns                ;
-; 1.806 ns                                ; 173.34 MHz ( period = 5.769 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.887 ns                  ; 5.081 ns                ;
-; 1.842 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.327 ns                  ; 3.485 ns                ;
-; 1.881 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.428 ns                ;
-; 1.904 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.325 ns                  ; 3.421 ns                ;
-; 1.914 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.395 ns                ;
-; 1.923 ns                                ; 176.93 MHz ( period = 5.652 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 4.970 ns                ;
-; 2.000 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 3.308 ns                ;
-; 2.018 ns                                ; 179.95 MHz ( period = 5.557 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.883 ns                  ; 4.865 ns                ;
-; 2.034 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.321 ns                  ; 3.287 ns                ;
-; 2.040 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 3.253 ns                ;
-; 2.068 ns                                ; 181.59 MHz ( period = 5.507 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.887 ns                  ; 4.819 ns                ;
-; 2.105 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.302 ns                  ; 3.197 ns                ;
-; 2.112 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_2                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.488 ns                  ; 2.376 ns                ;
-; 2.131 ns                                ; 183.69 MHz ( period = 5.444 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.896 ns                  ; 4.765 ns                ;
-; 2.141 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 3.175 ns                ;
-; 2.151 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.307 ns                  ; 3.156 ns                ;
-; 2.155 ns                                ; 184.50 MHz ( period = 5.420 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.900 ns                  ; 4.745 ns                ;
-; 2.159 ns                                ; 184.64 MHz ( period = 5.416 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.891 ns                  ; 4.732 ns                ;
-; 2.166 ns                                ; 184.88 MHz ( period = 5.409 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.712 ns                ;
-; 2.178 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.309 ns                  ; 3.131 ns                ;
-; 2.202 ns                                ; 186.12 MHz ( period = 5.373 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.893 ns                  ; 4.691 ns                ;
-; 2.203 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 3.109 ns                ;
-; 2.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.335 ns                  ; 3.128 ns                ;
-; 2.238 ns                                ; 187.37 MHz ( period = 5.337 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.640 ns                ;
-; 2.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.317 ns                  ; 3.075 ns                ;
-; 2.260 ns                                ; 188.15 MHz ( period = 5.315 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.891 ns                  ; 4.631 ns                ;
-; 2.265 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.428 ns                  ; 2.163 ns                ;
-; 2.273 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.492 ns                  ; 2.219 ns                ;
-; 2.298 ns                                ; 189.50 MHz ( period = 5.277 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.901 ns                  ; 4.603 ns                ;
-; 2.325 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.991 ns                ;
-; 2.338 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.383 ns                  ; 3.045 ns                ;
-; 2.357 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.321 ns                  ; 2.964 ns                ;
-; 2.370 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.302 ns                  ; 2.932 ns                ;
-; 2.376 ns                                ; 192.34 MHz ( period = 5.199 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.883 ns                  ; 4.507 ns                ;
-; 2.385 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 3.250 ns                ;
-; 2.410 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.906 ns                ;
-; 2.417 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.307 ns                  ; 2.890 ns                ;
-; 2.434 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.373 ns                  ; 2.939 ns                ;
-; 2.445 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.495 ns                  ; 2.050 ns                ;
-; 2.447 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 2.865 ns                ;
-; 2.470 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.175 ns                ;
-; 2.502 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.652 ns                  ; 3.150 ns                ;
-; 2.509 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 3.134 ns                ;
-; 2.516 ns                                ; 197.67 MHz ( period = 5.059 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.725 ns                ;
-; 2.517 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.308 ns                  ; 2.791 ns                ;
-; 2.520 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 2.773 ns                ;
-; 2.523 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.122 ns                ;
-; 2.531 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 3.108 ns                ;
-; 2.548 ns                                ; 198.93 MHz ( period = 5.027 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.248 ns                  ; 4.700 ns                ;
-; 2.549 ns                                ; 198.97 MHz ( period = 5.026 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.878 ns                  ; 4.329 ns                ;
-; 2.550 ns                                ; 199.00 MHz ( period = 5.025 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.901 ns                  ; 4.351 ns                ;
-; 2.550 ns                                ; 199.00 MHz ( period = 5.025 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.239 ns                  ; 4.689 ns                ;
-; 2.561 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 2.814 ns                ;
-; 2.567 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.290 ns                  ; 2.723 ns                ;
-; 2.569 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.317 ns                  ; 2.748 ns                ;
-; 2.569 ns                                ; 199.76 MHz ( period = 5.006 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.231 ns                  ; 4.662 ns                ;
-; 2.570 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 2.805 ns                ;
-; 2.571 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 3.072 ns                ;
-; 2.572 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.306 ns                  ; 2.734 ns                ;
-; 2.597 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.719 ns                ;
-; 2.603 ns                                ; 201.13 MHz ( period = 4.972 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.638 ns                ;
-; 2.614 ns                                ; 201.57 MHz ( period = 4.961 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.239 ns                  ; 4.625 ns                ;
-; 2.616 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.377 ns                  ; 2.761 ns                ;
-; 2.622 ns                                ; 201.90 MHz ( period = 4.953 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 4.325 ns                ;
-; 2.641 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 3.004 ns                ;
-; 2.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.330 ns                  ; 2.645 ns                ;
-; 2.690 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.949 ns                ;
-; 2.695 ns                                ; 204.92 MHz ( period = 4.880 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.254 ns                ;
-; 2.697 ns                                ; 205.00 MHz ( period = 4.878 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.529 ns                ;
-; 2.708 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.648 ns                  ; 2.940 ns                ;
-; 2.716 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.312 ns                  ; 2.596 ns                ;
-; 2.717 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.913 ns                ;
-; 2.718 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.912 ns                ;
-; 2.724 ns                                ; 206.14 MHz ( period = 4.851 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.241 ns                  ; 4.517 ns                ;
-; 2.733 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.356 ns                  ; 2.623 ns                ;
-; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.911 ns                ;
-; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.381 ns                  ; 2.647 ns                ;
-; 2.734 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns                    ; 4.559 ns                  ; 1.825 ns                ;
-; 2.751 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.377 ns                  ; 2.626 ns                ;
-; 2.758 ns                                ; 207.60 MHz ( period = 4.817 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.244 ns                  ; 4.486 ns                ;
-; 2.761 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.874 ns                ;
-; 2.761 ns                                ; 207.73 MHz ( period = 4.814 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.188 ns                ;
-; 2.764 ns                                ; 207.86 MHz ( period = 4.811 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 4.185 ns                ;
-; 2.768 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.652 ns                  ; 2.884 ns                ;
-; 2.771 ns                                ; 208.16 MHz ( period = 4.804 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.235 ns                  ; 4.464 ns                ;
-; 2.776 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 2.867 ns                ;
-; 2.778 ns                                ; 208.46 MHz ( period = 4.797 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.948 ns                  ; 4.170 ns                ;
-; 2.780 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.855 ns                ;
-; 2.793 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.852 ns                ;
-; 2.793 ns                                ; 209.12 MHz ( period = 4.782 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.433 ns                ;
-; 2.797 ns                                ; 209.29 MHz ( period = 4.778 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.226 ns                  ; 4.429 ns                ;
-; 2.798 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.378 ns                  ; 2.580 ns                ;
-; 2.807 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.779 ns                  ; 2.972 ns                ;
-; 2.808 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.374 ns                  ; 2.566 ns                ;
-; 2.815 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.373 ns                  ; 2.558 ns                ;
-; 2.821 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.818 ns                ;
-; 2.838 ns                                ; 211.10 MHz ( period = 4.737 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.231 ns                  ; 4.393 ns                ;
-; 2.839 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.643 ns                  ; 2.804 ns                ;
-; 2.846 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.293 ns                  ; 2.447 ns                ;
-; 2.851 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.334 ns                  ; 2.483 ns                ;
-; 2.862 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.316 ns                  ; 2.454 ns                ;
-; 2.909 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.645 ns                  ; 2.736 ns                ;
-; 2.935 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.423 ns                ;
-; 2.937 ns                                ; 215.61 MHz ( period = 4.638 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 4.006 ns                ;
-; 2.951 ns                                ; 216.26 MHz ( period = 4.624 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.949 ns                  ; 3.998 ns                ;
-; 2.954 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.639 ns                  ; 2.685 ns                ;
-; 2.960 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.655 ns                  ; 2.695 ns                ;
-; 2.963 ns                                ; 216.83 MHz ( period = 4.612 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 3.980 ns                ;
-; 2.969 ns                                ; 217.11 MHz ( period = 4.606 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.978 ns                ;
-; 2.977 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.648 ns                  ; 2.671 ns                ;
-; 2.983 ns                                ; 217.77 MHz ( period = 4.592 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.235 ns                  ; 4.252 ns                ;
-; 2.984 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.646 ns                ;
-; 2.985 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.645 ns                ;
-; 2.988 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.779 ns                  ; 2.791 ns                ;
-; 3.004 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 2.358 ns                ;
-; 3.005 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.364 ns                  ; 2.359 ns                ;
-; 3.010 ns                                ; 219.06 MHz ( period = 4.565 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.292 ns                  ; 4.282 ns                ;
-; 3.018 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.653 ns                  ; 2.635 ns                ;
-; 3.027 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.635 ns                  ; 2.608 ns                ;
-; 3.042 ns                                ; 220.60 MHz ( period = 4.533 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.294 ns                  ; 4.252 ns                ;
-; 3.047 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.729 ns                  ; 2.682 ns                ;
-; 3.051 ns                                ; 221.04 MHz ( period = 4.524 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.249 ns                  ; 4.198 ns                ;
-; 3.058 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.354 ns                  ; 2.296 ns                ;
-; 3.061 ns                                ; 221.53 MHz ( period = 4.514 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.249 ns                  ; 4.188 ns                ;
-; 3.074 ns                                ; 222.17 MHz ( period = 4.501 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.946 ns                  ; 3.872 ns                ;
-; 3.096 ns                                ; 223.26 MHz ( period = 4.479 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.851 ns                ;
-; 3.115 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.246 ns                ;
-; 3.127 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.234 ns                ;
-; 3.131 ns                                ; 225.02 MHz ( period = 4.444 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.943 ns                  ; 3.812 ns                ;
-; 3.141 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.325 ns                  ; 2.184 ns                ;
-; 3.143 ns                                ; 225.63 MHz ( period = 4.432 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 4.152 ns                ;
-; 3.151 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.479 ns                ;
-; 3.158 ns                                ; 226.40 MHz ( period = 4.417 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.292 ns                  ; 4.134 ns                ;
-; 3.159 ns                                ; 226.45 MHz ( period = 4.416 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.132 ns                ;
-; 3.162 ns                                ; 226.60 MHz ( period = 4.413 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 4.133 ns                ;
-; 3.163 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.780 ns                  ; 2.617 ns                ;
-; 3.173 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.680 ns                  ; 2.507 ns                ;
-; 3.181 ns                                ; 227.58 MHz ( period = 4.394 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.944 ns                  ; 3.763 ns                ;
-; 3.192 ns                                ; 228.15 MHz ( period = 4.383 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.947 ns                  ; 3.755 ns                ;
-; 3.199 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.630 ns                  ; 2.431 ns                ;
-; 3.207 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.671 ns                  ; 2.464 ns                ;
-; 3.208 ns                                ; 228.99 MHz ( period = 4.367 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.946 ns                  ; 3.738 ns                ;
-; 3.209 ns                                ; 229.04 MHz ( period = 4.366 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 6.944 ns                  ; 3.735 ns                ;
-; 3.225 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.470 ns                ;
-; 3.226 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.655 ns                  ; 2.429 ns                ;
-; 3.233 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 2.126 ns                ;
-; 3.236 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 2.125 ns                ;
-; 3.251 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.107 ns                ;
-; 3.253 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.355 ns                  ; 2.102 ns                ;
-; 3.261 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 2.097 ns                ;
-; 3.262 ns                                ; 231.86 MHz ( period = 4.313 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 4.035 ns                ;
-; 3.263 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.363 ns                  ; 2.100 ns                ;
-; 3.266 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.363 ns                  ; 2.097 ns                ;
-; 3.271 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 2.091 ns                ;
-; 3.277 ns                                ; 232.67 MHz ( period = 4.298 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.014 ns                ;
-; 3.279 ns                                ; 232.77 MHz ( period = 4.296 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.291 ns                  ; 4.012 ns                ;
-; 3.282 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.653 ns                  ; 2.371 ns                ;
-; 3.307 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.383 ns                  ; 2.076 ns                ;
-; 3.346 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.352 ns                ;
-; 3.351 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.344 ns                ;
-; 3.365 ns                                ; 237.53 MHz ( period = 4.210 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.296 ns                  ; 3.931 ns                ;
-; 3.387 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 1.974 ns                ;
-; 3.390 ns                                ; 238.95 MHz ( period = 4.185 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.294 ns                  ; 3.904 ns                ;
-; 3.410 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.362 ns                  ; 1.952 ns                ;
-; 3.415 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.283 ns                ;
-; 3.429 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.358 ns                  ; 1.929 ns                ;
-; 3.438 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.375 ns                  ; 1.937 ns                ;
-; 3.450 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.700 ns                  ; 2.250 ns                ;
-; 3.458 ns                                ; 242.90 MHz ( period = 4.117 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 3.837 ns                ;
-; 3.459 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.239 ns                ;
-; 3.461 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.781 ns                  ; 2.320 ns                ;
-; 3.474 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.380 ns                  ; 1.906 ns                ;
-; 3.477 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 1.882 ns                ;
-; 3.492 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.695 ns                  ; 2.203 ns                ;
-; 3.495 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.700 ns                  ; 2.205 ns                ;
-; 3.499 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.359 ns                  ; 1.860 ns                ;
-; 3.504 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.361 ns                  ; 1.857 ns                ;
-; 3.558 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.141 ns                ;
-; 3.575 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 2.122 ns                ;
-; 3.602 ns                                ; 251.70 MHz ( period = 3.973 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.295 ns                  ; 3.693 ns                ;
-; 3.610 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.089 ns                ;
-; 3.614 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.698 ns                  ; 2.084 ns                ;
-; 3.616 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.701 ns                  ; 2.085 ns                ;
-; 3.617 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.696 ns                  ; 2.079 ns                ;
-; 3.620 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 2.077 ns                ;
-; 3.625 ns                                ; 253.16 MHz ( period = 3.950 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 3.672 ns                ;
-; 3.640 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.059 ns                ;
-; 3.649 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns                    ; 5.726 ns                  ; 2.077 ns                ;
-; 3.657 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.042 ns                ;
-; 3.663 ns                                ; 255.62 MHz ( period = 3.912 ns )                    ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns                    ; 7.297 ns                  ; 3.634 ns                ;
-; 3.664 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.696 ns                  ; 2.032 ns                ;
-; 3.673 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.703 ns                  ; 2.030 ns                ;
-; 3.675 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 2.024 ns                ;
-; 3.708 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.702 ns                  ; 1.994 ns                ;
-; 3.720 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.703 ns                  ; 1.983 ns                ;
-; 3.738 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.697 ns                  ; 1.959 ns                ;
-; 3.825 ns                                ; None                                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns                    ; 5.699 ns                  ; 1.874 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                        ;                                                                                                                                     ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'                                                                                                                                                                                                                                                                                                                                                                           ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                           ; To                                                                     ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; -1.712 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 1.118 ns                  ; 2.830 ns                ;
-; -1.664 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.656 ns                ;
-; -1.597 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.589 ns                ;
-; -1.597 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.992 ns                  ; 2.589 ns                ;
-; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
-; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
-; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
-; -1.358 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.985 ns                  ; 2.343 ns                ;
-; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
-; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
-; -1.354 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.987 ns                  ; 2.341 ns                ;
-; -1.333 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.319 ns                ;
-; -1.333 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.319 ns                ;
-; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
-; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
-; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
-; -1.280 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.266 ns                ;
-; -1.278 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.264 ns                ;
-; -1.278 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.986 ns                  ; 2.264 ns                ;
-; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
-; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
-; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
-; -1.250 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.238 ns                ;
-; -1.248 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.989 ns                  ; 2.237 ns                ;
-; -1.243 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.989 ns                  ; 2.232 ns                ;
-; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
-; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
-; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
-; -1.228 ns                               ; None                                                ; FB_ALE                                         ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns                    ; 0.988 ns                  ; 2.216 ns                ;
-; 4.485 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 6.311 ns                    ; 6.117 ns                  ; 1.632 ns                ;
-; 6.612 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.393 ns                 ; 3.781 ns                ;
-; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
-; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
-; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
-; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
-; 6.644 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.392 ns                 ; 3.748 ns                ;
-; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
-; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
-; 6.665 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.873 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.672 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.527 ns                 ; 3.855 ns                ;
-; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
-; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
-; 6.685 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.852 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.727 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.811 ns                ;
-; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
-; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
-; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
-; 6.788 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.234 ns                 ; 3.446 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.826 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.568 ns                ;
-; 6.843 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.545 ns                 ; 3.702 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.845 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.549 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.849 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.394 ns                 ; 3.545 ns                ;
-; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
-; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
-; 6.955 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.564 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 6.969 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.519 ns                 ; 3.550 ns                ;
-; 7.011 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.390 ns                 ; 3.379 ns                ;
-; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
-; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
-; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
-; 7.016 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.546 ns                 ; 3.530 ns                ;
-; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
-; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
-; 7.074 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.537 ns                 ; 3.463 ns                ;
-; 7.111 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.514 ns                 ; 3.403 ns                ;
-; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
-; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
-; 7.123 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.364 ns                 ; 3.241 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.147 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.656 ns                 ; 3.509 ns                ;
-; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
-; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
-; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
-; 7.184 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.391 ns                 ; 3.207 ns                ;
-; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
-; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
-; 7.242 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.382 ns                 ; 3.140 ns                ;
-; 7.264 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.548 ns                 ; 3.284 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.286 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.252 ns                ;
-; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
-; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
-; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
-; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
-; 7.296 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.251 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.297 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.361 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.298 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.547 ns                 ; 3.249 ns                ;
-; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
-; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
-; 7.323 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.539 ns                 ; 3.216 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.334 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.324 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.380 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.658 ns                 ; 3.278 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.411 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.538 ns                 ; 3.127 ns                ;
-; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
-; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
-; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
-; 7.440 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.389 ns                 ; 2.949 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.448 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.549 ns                 ; 3.101 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; 7.454 ns                                ; None                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns                   ; 10.383 ns                 ; 2.929 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                ;                                                                        ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-; -4.294 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.607 ns                 ; 3.687 ns                ;
-; -4.252 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.600 ns                 ; 3.652 ns                ;
-; -4.247 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.642 ns                ;
-; -4.241 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.594 ns                 ; 3.647 ns                ;
-; -4.232 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.635 ns                ;
-; -4.228 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.631 ns                ;
-; -4.220 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.607 ns                 ; 3.613 ns                ;
-; -4.212 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.610 ns                ;
-; -4.205 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.597 ns                 ; 3.608 ns                ;
-; -4.158 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.898 ns                ;
-; -4.119 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.141 ns                ;
-; -4.119 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.517 ns                ;
-; -4.092 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.114 ns                ;
-; -4.088 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.486 ns                ;
-; -4.086 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.595 ns                 ; 3.491 ns                ;
-; -4.085 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.593 ns                 ; 3.492 ns                ;
-; -4.073 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.468 ns                ;
-; -4.070 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.465 ns                ;
-; -4.070 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.466 ns                ;
-; -4.065 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.461 ns                ;
-; -4.060 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.458 ns                ;
-; -4.057 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.455 ns                ;
-; -4.051 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.447 ns                ;
-; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.447 ns                ;
-; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.447 ns                ;
-; -4.049 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.445 ns                ;
-; -4.048 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 4.068 ns                ;
-; -4.046 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.444 ns                ;
-; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.441 ns                ;
-; -4.045 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.441 ns                ;
-; -4.043 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.441 ns                ;
-; -4.042 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 4.063 ns                ;
-; -4.042 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.440 ns                ;
-; -4.040 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.436 ns                ;
-; -4.039 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.434 ns                ;
-; -4.039 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.435 ns                ;
-; -4.036 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.431 ns                ;
-; -4.035 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.433 ns                ;
-; -4.032 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.428 ns                ;
-; -4.032 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.428 ns                ;
-; -4.030 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.610 ns                 ; 3.420 ns                ;
-; -4.027 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.426 ns                ;
-; -3.997 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.595 ns                 ; 3.402 ns                ;
-; -3.995 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.598 ns                 ; 3.397 ns                ;
-; -3.987 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 4.008 ns                ;
-; -3.985 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.725 ns                ;
-; -3.984 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.379 ns                ;
-; -3.980 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 4.002 ns                ;
-; -3.978 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.376 ns                ;
-; -3.977 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.603 ns                 ; 3.374 ns                ;
-; -3.976 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.374 ns                ;
-; -3.973 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.372 ns                ;
-; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.370 ns                ;
-; -3.972 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.601 ns                 ; 3.371 ns                ;
-; -3.969 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.365 ns                ;
-; -3.968 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.366 ns                ;
-; -3.968 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.364 ns                ;
-; -3.967 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.363 ns                ;
-; -3.958 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.356 ns                ;
-; -3.957 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.355 ns                ;
-; -3.956 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.354 ns                ;
-; -3.952 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.347 ns                ;
-; -3.950 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.972 ns                ;
-; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.970 ns                ;
-; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.343 ns                ;
-; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.346 ns                ;
-; -3.948 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.346 ns                ;
-; -3.947 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.345 ns                ;
-; -3.947 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.345 ns                ;
-; -3.946 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.344 ns                ;
-; -3.945 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.343 ns                ;
-; -3.943 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.341 ns                ;
-; -3.943 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.341 ns                ;
-; -3.941 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.339 ns                ;
-; -3.941 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.339 ns                ;
-; -3.938 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.960 ns                ;
-; -3.938 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.334 ns                ;
-; -3.937 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.332 ns                ;
-; -3.935 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.333 ns                ;
-; -3.935 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.333 ns                ;
-; -3.934 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.329 ns                ;
-; -3.934 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.330 ns                ;
-; -3.932 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.330 ns                ;
-; -3.932 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.327 ns                ;
-; -3.930 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.328 ns                ;
-; -3.927 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.325 ns                ;
-; -3.926 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.324 ns                ;
-; -3.925 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.323 ns                ;
-; -3.924 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.319 ns                ;
-; -3.922 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.944 ns                ;
-; -3.920 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.316 ns                ;
-; -3.915 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.310 ns                ;
-; -3.909 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.929 ns                ;
-; -3.908 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.928 ns                ;
-; -3.898 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.919 ns                ;
-; -3.896 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.292 ns                ;
-; -3.894 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.916 ns                ;
-; -3.882 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.904 ns                ;
-; -3.878 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.899 ns                ;
-; -3.874 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.614 ns                ;
-; -3.873 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.269 ns                ;
-; -3.869 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.257 ns                ;
-; -3.867 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.887 ns                ;
-; -3.867 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.303 ns                 ; 3.564 ns                ;
-; -3.858 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.610 ns                 ; 3.248 ns                ;
-; -3.854 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.876 ns                ;
-; -3.851 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.591 ns                ;
-; -3.835 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.855 ns                ;
-; -3.833 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.551 ns                ;
-; -3.828 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.850 ns                ;
-; -3.827 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.847 ns                ;
-; -3.822 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.540 ns                ;
-; -3.821 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.291 ns                 ; 3.530 ns                ;
-; -3.819 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.303 ns                 ; 3.516 ns                ;
-; -3.818 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.216 ns                ;
-; -3.817 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.838 ns                ;
-; -3.816 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.211 ns                ;
-; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
-; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
-; -3.814 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.212 ns                ;
-; -3.813 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.211 ns                ;
-; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.210 ns                ;
-; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.208 ns                ;
-; -3.812 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.208 ns                ;
-; -3.809 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.204 ns                ;
-; -3.809 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.205 ns                ;
-; -3.807 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.205 ns                ;
-; -3.806 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.202 ns                ;
-; -3.804 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.199 ns                ;
-; -3.803 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.191 ns                ;
-; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.190 ns                ;
-; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.190 ns                ;
-; -3.792 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.295 ns                 ; 3.497 ns                ;
-; -3.788 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.186 ns                ;
-; -3.787 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.505 ns                ;
-; -3.783 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.171 ns                ;
-; -3.781 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.176 ns                ;
-; -3.780 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.802 ns                ;
-; -3.779 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.519 ns                ;
-; -3.777 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.615 ns                 ; 3.162 ns                ;
-; -3.777 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.495 ns                ;
-; -3.776 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.796 ns                ;
-; -3.771 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.793 ns                ;
-; -3.767 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.507 ns                ;
-; -3.762 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.480 ns                ;
-; -3.757 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.779 ns                ;
-; -3.748 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.015 ns                  ; 3.763 ns                ;
-; -3.747 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.291 ns                 ; 3.456 ns                ;
-; -3.747 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.015 ns                  ; 3.762 ns                ;
-; -3.743 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.014 ns                  ; 3.757 ns                ;
-; -3.728 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.292 ns                 ; 3.436 ns                ;
-; -3.724 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.442 ns                ;
-; -3.724 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.442 ns                ;
-; -3.720 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.013 ns                  ; 3.733 ns                ;
-; -3.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.294 ns                 ; 3.423 ns                ;
-; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.617 ns                 ; 3.096 ns                ;
-; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.622 ns                 ; 3.091 ns                ;
-; -3.713 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.734 ns                ;
-; -3.703 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.292 ns                 ; 3.411 ns                ;
-; -3.698 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.438 ns                ;
-; -3.695 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.093 ns                ;
-; -3.694 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.092 ns                ;
-; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.091 ns                ;
-; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.091 ns                ;
-; -3.693 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.089 ns                ;
-; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
-; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
-; -3.691 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.089 ns                ;
-; -3.690 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.088 ns                ;
-; -3.690 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.085 ns                ;
-; -3.688 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.084 ns                ;
-; -3.685 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.080 ns                ;
-; -3.685 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.403 ns                ;
-; -3.684 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.080 ns                ;
-; -3.683 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.020 ns                  ; 3.703 ns                ;
-; -3.679 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.260 ns                 ; 3.419 ns                ;
-; -3.677 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.075 ns                ;
-; -3.677 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.022 ns                  ; 3.699 ns                ;
-; -3.675 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.073 ns                ;
-; -3.674 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.392 ns                ;
-; -3.672 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.070 ns                ;
-; -3.670 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.068 ns                ;
-; -3.668 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.617 ns                 ; 3.051 ns                ;
-; -3.668 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.289 ns                 ; 3.379 ns                ;
-; -3.667 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.602 ns                 ; 3.065 ns                ;
-; -3.665 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.061 ns                ;
-; -3.665 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.061 ns                ;
-; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.060 ns                ;
-; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.059 ns                ;
-; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.059 ns                ;
-; -3.664 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.060 ns                ;
-; -3.663 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.058 ns                ;
-; -3.663 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.604 ns                 ; 3.059 ns                ;
-; -3.662 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.057 ns                ;
-; -3.661 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.056 ns                ;
-; -3.660 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.605 ns                 ; 3.055 ns                ;
-; -3.651 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.282 ns                 ; 3.369 ns                ;
-; -3.649 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.612 ns                 ; 3.037 ns                ;
-; -3.645 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; 0.021 ns                  ; 3.666 ns                ;
-; -3.633 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns                    ; -0.614 ns                 ; 3.019 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'CLK33M'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                     ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-; -5.966 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.279 ns                 ; 3.687 ns                ;
-; -5.924 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.272 ns                 ; 3.652 ns                ;
-; -5.919 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.642 ns                ;
-; -5.913 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.266 ns                 ; 3.647 ns                ;
-; -5.904 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.635 ns                ;
-; -5.900 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.631 ns                ;
-; -5.892 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.279 ns                 ; 3.613 ns                ;
-; -5.884 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.610 ns                ;
-; -5.877 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.269 ns                 ; 3.608 ns                ;
-; -5.830 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.898 ns                ;
-; -5.791 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.141 ns                ;
-; -5.791 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.517 ns                ;
-; -5.764 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.114 ns                ;
-; -5.760 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.486 ns                ;
-; -5.758 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.267 ns                 ; 3.491 ns                ;
-; -5.757 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.265 ns                 ; 3.492 ns                ;
-; -5.745 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.468 ns                ;
-; -5.742 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.465 ns                ;
-; -5.742 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.466 ns                ;
-; -5.737 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.461 ns                ;
-; -5.732 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.458 ns                ;
-; -5.729 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.455 ns                ;
-; -5.723 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.447 ns                ;
-; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.447 ns                ;
-; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.447 ns                ;
-; -5.721 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.445 ns                ;
-; -5.720 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 4.068 ns                ;
-; -5.718 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.444 ns                ;
-; -5.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.441 ns                ;
-; -5.717 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.441 ns                ;
-; -5.715 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.441 ns                ;
-; -5.714 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 4.063 ns                ;
-; -5.714 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.440 ns                ;
-; -5.712 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.436 ns                ;
-; -5.711 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.434 ns                ;
-; -5.711 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.435 ns                ;
-; -5.708 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.431 ns                ;
-; -5.707 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.433 ns                ;
-; -5.704 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.428 ns                ;
-; -5.704 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.428 ns                ;
-; -5.702 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.282 ns                 ; 3.420 ns                ;
-; -5.699 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.426 ns                ;
-; -5.669 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.267 ns                 ; 3.402 ns                ;
-; -5.667 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.270 ns                 ; 3.397 ns                ;
-; -5.659 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 4.008 ns                ;
-; -5.657 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.725 ns                ;
-; -5.656 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.379 ns                ;
-; -5.652 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 4.002 ns                ;
-; -5.650 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.376 ns                ;
-; -5.649 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.275 ns                 ; 3.374 ns                ;
-; -5.648 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.374 ns                ;
-; -5.645 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.372 ns                ;
-; -5.644 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.370 ns                ;
-; -5.644 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.273 ns                 ; 3.371 ns                ;
-; -5.641 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.365 ns                ;
-; -5.640 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.366 ns                ;
-; -5.640 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.364 ns                ;
-; -5.639 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.363 ns                ;
-; -5.630 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.356 ns                ;
-; -5.629 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.355 ns                ;
-; -5.628 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.354 ns                ;
-; -5.624 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.347 ns                ;
-; -5.622 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.972 ns                ;
-; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.970 ns                ;
-; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.343 ns                ;
-; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.346 ns                ;
-; -5.620 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.346 ns                ;
-; -5.619 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.345 ns                ;
-; -5.619 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.345 ns                ;
-; -5.618 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.344 ns                ;
-; -5.617 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.343 ns                ;
-; -5.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.341 ns                ;
-; -5.615 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.341 ns                ;
-; -5.613 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.339 ns                ;
-; -5.613 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.339 ns                ;
-; -5.610 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.960 ns                ;
-; -5.610 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.334 ns                ;
-; -5.609 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.332 ns                ;
-; -5.607 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.333 ns                ;
-; -5.607 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.333 ns                ;
-; -5.606 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.329 ns                ;
-; -5.606 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.330 ns                ;
-; -5.604 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.330 ns                ;
-; -5.604 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.327 ns                ;
-; -5.602 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.328 ns                ;
-; -5.599 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.325 ns                ;
-; -5.598 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.324 ns                ;
-; -5.597 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.323 ns                ;
-; -5.596 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.319 ns                ;
-; -5.594 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.944 ns                ;
-; -5.592 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.316 ns                ;
-; -5.587 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.310 ns                ;
-; -5.581 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.929 ns                ;
-; -5.580 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.928 ns                ;
-; -5.570 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.919 ns                ;
-; -5.568 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.292 ns                ;
-; -5.566 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.916 ns                ;
-; -5.554 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.904 ns                ;
-; -5.550 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.899 ns                ;
-; -5.546 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.614 ns                ;
-; -5.545 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.269 ns                ;
-; -5.541 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.257 ns                ;
-; -5.539 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.887 ns                ;
-; -5.539 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.975 ns                 ; 3.564 ns                ;
-; -5.530 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.282 ns                 ; 3.248 ns                ;
-; -5.526 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.876 ns                ;
-; -5.523 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.591 ns                ;
-; -5.507 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.855 ns                ;
-; -5.505 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.551 ns                ;
-; -5.500 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.850 ns                ;
-; -5.499 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.847 ns                ;
-; -5.494 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.540 ns                ;
-; -5.493 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.963 ns                 ; 3.530 ns                ;
-; -5.491 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.975 ns                 ; 3.516 ns                ;
-; -5.490 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.216 ns                ;
-; -5.489 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.838 ns                ;
-; -5.488 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.211 ns                ;
-; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
-; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
-; -5.486 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.212 ns                ;
-; -5.485 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.211 ns                ;
-; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.210 ns                ;
-; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.208 ns                ;
-; -5.484 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.208 ns                ;
-; -5.481 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.204 ns                ;
-; -5.481 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.205 ns                ;
-; -5.479 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.205 ns                ;
-; -5.478 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.202 ns                ;
-; -5.476 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.199 ns                ;
-; -5.475 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.191 ns                ;
-; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.190 ns                ;
-; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.190 ns                ;
-; -5.464 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.967 ns                 ; 3.497 ns                ;
-; -5.460 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.186 ns                ;
-; -5.459 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.505 ns                ;
-; -5.455 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.171 ns                ;
-; -5.453 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.176 ns                ;
-; -5.452 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.802 ns                ;
-; -5.451 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.519 ns                ;
-; -5.449 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.287 ns                 ; 3.162 ns                ;
-; -5.449 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.495 ns                ;
-; -5.448 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.796 ns                ;
-; -5.443 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.793 ns                ;
-; -5.439 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.507 ns                ;
-; -5.434 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.480 ns                ;
-; -5.429 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.779 ns                ;
-; -5.420 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.657 ns                 ; 3.763 ns                ;
-; -5.419 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.963 ns                 ; 3.456 ns                ;
-; -5.419 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.657 ns                 ; 3.762 ns                ;
-; -5.415 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.658 ns                 ; 3.757 ns                ;
-; -5.400 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.964 ns                 ; 3.436 ns                ;
-; -5.396 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.442 ns                ;
-; -5.396 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.442 ns                ;
-; -5.392 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.659 ns                 ; 3.733 ns                ;
-; -5.389 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110]                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.966 ns                 ; 3.423 ns                ;
-; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.289 ns                 ; 3.096 ns                ;
-; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.294 ns                 ; 3.091 ns                ;
-; -5.385 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.734 ns                ;
-; -5.375 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.964 ns                 ; 3.411 ns                ;
-; -5.370 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.438 ns                ;
-; -5.367 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.093 ns                ;
-; -5.366 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.092 ns                ;
-; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.091 ns                ;
-; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.091 ns                ;
-; -5.365 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.089 ns                ;
-; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
-; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
-; -5.363 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.089 ns                ;
-; -5.362 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.088 ns                ;
-; -5.362 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.085 ns                ;
-; -5.360 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.084 ns                ;
-; -5.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.080 ns                ;
-; -5.357 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.403 ns                ;
-; -5.356 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.080 ns                ;
-; -5.355 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.652 ns                 ; 3.703 ns                ;
-; -5.351 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.932 ns                 ; 3.419 ns                ;
-; -5.349 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.075 ns                ;
-; -5.349 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.650 ns                 ; 3.699 ns                ;
-; -5.347 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.073 ns                ;
-; -5.346 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.392 ns                ;
-; -5.344 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.070 ns                ;
-; -5.342 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.068 ns                ;
-; -5.340 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.289 ns                 ; 3.051 ns                ;
-; -5.340 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.961 ns                 ; 3.379 ns                ;
-; -5.339 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.274 ns                 ; 3.065 ns                ;
-; -5.337 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.061 ns                ;
-; -5.337 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.061 ns                ;
-; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.060 ns                ;
-; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.059 ns                ;
-; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.059 ns                ;
-; -5.336 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.060 ns                ;
-; -5.335 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.058 ns                ;
-; -5.335 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.276 ns                 ; 3.059 ns                ;
-; -5.334 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.057 ns                ;
-; -5.333 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.056 ns                ;
-; -5.332 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.277 ns                 ; 3.055 ns                ;
-; -5.323 ns                               ; None                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6]                                                                                              ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.954 ns                 ; 3.369 ns                ;
-; -5.321 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                    ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.284 ns                 ; 3.037 ns                ;
-; -5.317 ns                               ; None                                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5]                  ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -1.651 ns                 ; 3.666 ns                ;
-; -5.305 ns                               ; None                                                ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3]                                                      ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M   ; 0.196 ns                    ; -2.286 ns                 ; 3.019 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                                                                                                                                          ;                                                                                                                                                                          ;                                                                          ;          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'MAIN_CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-; Slack                                   ; Actual fmax (period)                                ; From                                           ; To                                                                                                                                                                                                               ; From Clock                                                               ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-; -4.261 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.318 ns                ;
-; -4.260 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a8                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.317 ns                ;
-; -4.258 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a6                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.315 ns                ;
-; -4.239 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a5                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 4.296 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[31]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[30]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[29]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[28]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[27]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[26]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[25]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[24]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[23]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[22]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[21]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[20]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[19]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[18]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[17]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[16]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[15]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[14]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[13]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[12]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[11]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[10]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[9]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.204 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0]                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.122 ns                  ; 4.326 ns                ;
-; -4.071 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~portb_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.225 ns                  ; 4.296 ns                ;
-; -4.023 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.012 ns                  ; 4.035 ns                ;
-; -4.023 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[4]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.012 ns                  ; 4.035 ns                ;
-; -3.979 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a2                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.272 ns                  ; 4.251 ns                ;
-; -3.910 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a4                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.967 ns                ;
-; -3.907 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a3                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.964 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[1]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[2]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[0]               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[0]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[1]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[6]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[2]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[7]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[8]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[3]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.784 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[5]                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.055 ns                  ; 3.839 ns                ;
-; -3.546 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a1                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.603 ns                ;
-; -3.544 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.057 ns                  ; 3.601 ns                ;
-; -3.541 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.096 ns                  ; 3.637 ns                ;
-; -3.426 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; -0.013 ns                 ; 3.413 ns                ;
-; -3.055 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.360 ns                  ; 3.415 ns                ;
-; -3.039 ns                               ; None                                                ; FB_ALE                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WRF_WRE                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; -0.013 ns                 ; 3.026 ns                ;
-; -2.598 ns                               ; None                                                ; FB_ALE                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns                    ; 0.205 ns                  ; 2.803 ns                ;
-; -2.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.530 ns                ;
-; -2.463 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.530 ns                ;
-; -2.375 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 7.143 ns                ;
-; -2.355 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.341 ns                ;
-; -2.320 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.304 ns                ;
-; -2.317 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.384 ns                ;
-; -2.317 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.384 ns                ;
-; -2.290 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 7.056 ns                ;
-; -2.250 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.317 ns                ;
-; -2.250 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.067 ns                  ; 6.317 ns                ;
-; -2.246 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 6.245 ns                ;
-; -2.239 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.307 ns                ;
-; -2.239 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.307 ns                ;
-; -2.229 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.997 ns                ;
-; -2.209 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.195 ns                ;
-; -2.199 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.317 ns                ;
-; -2.199 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.317 ns                ;
-; -2.183 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.129 ns                  ; 6.312 ns                ;
-; -2.177 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.390 ns                ;
-; -2.177 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.390 ns                ;
-; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.769 ns                  ; 6.920 ns                ;
-; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.270 ns                ;
-; -2.151 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.270 ns                ;
-; -2.147 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.265 ns                ;
-; -2.147 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.265 ns                ;
-; -2.146 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.120 ns                  ; 6.266 ns                ;
-; -2.146 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.120 ns                  ; 6.266 ns                ;
-; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.260 ns                ;
-; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.261 ns                ;
-; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.118 ns                  ; 6.260 ns                ;
-; -2.142 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.261 ns                ;
-; -2.139 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 6.905 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.135 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.957 ns                ;
-; -2.133 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.986 ns                  ; 6.119 ns                ;
-; -2.132 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.116 ns                ;
-; -2.131 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.987 ns                  ; 6.118 ns                ;
-; -2.129 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.248 ns                ;
-; -2.129 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.248 ns                ;
-; -2.122 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.187 ns                ;
-; -2.122 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.187 ns                ;
-; -2.118 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.186 ns                ;
-; -2.118 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.068 ns                  ; 6.186 ns                ;
-; -2.100 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 6.099 ns                ;
-; -2.098 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.215 ns                ;
-; -2.098 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.215 ns                ;
-; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.159 ns                ;
-; -2.094 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.065 ns                  ; 6.159 ns                ;
-; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
-; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
-; -2.084 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.238 ns                  ; 6.322 ns                ;
-; -2.083 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.620 ns                ;
-; -2.062 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.830 ns                ;
-; -2.060 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.768 ns                  ; 6.828 ns                ;
-; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
-; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
-; -2.048 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.176 ns                  ; 6.224 ns                ;
-; -2.045 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.766 ns                  ; 6.811 ns                ;
-; -2.045 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|UE                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.701 ns                  ; 5.746 ns                ;
-; -2.037 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]                                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.129 ns                  ; 6.166 ns                ;
-; -2.035 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.573 ns                ;
-; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[3][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
-; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[4][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
-; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[5][19]                                                                                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.251 ns                  ; 6.284 ns                ;
-; -2.033 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 6.017 ns                ;
-; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.568 ns                ;
-; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.244 ns                ;
-; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.213 ns                  ; 6.244 ns                ;
-; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.144 ns                ;
-; -2.031 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.144 ns                ;
-; -2.030 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA                                                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.769 ns                  ; 6.799 ns                ;
-; -2.030 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.539 ns                  ; 6.569 ns                ;
-; -2.026 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.537 ns                  ; 6.563 ns                ;
-; -2.026 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.564 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.000 ns                  ; 6.022 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.022 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.841 ns                ;
-; -2.013 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.538 ns                  ; 6.551 ns                ;
-; -2.010 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.987 ns                  ; 5.997 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.005 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.819 ns                  ; 5.824 ns                ;
-; -2.002 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.986 ns                ;
-; -2.001 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.985 ns                ;
-; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[4]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
-; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[5]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
-; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[6]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
-; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7]                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.013 ns                  ; 6.011 ns                ;
-; -1.998 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.999 ns                  ; 5.997 ns                ;
-; -1.997 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn                                                                      ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.984 ns                  ; 5.981 ns                ;
-; -1.996 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.064 ns                  ; 6.060 ns                ;
-; -1.996 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]                                                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.064 ns                  ; 6.060 ns                ;
-; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.106 ns                ;
-; -1.993 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.113 ns                  ; 6.106 ns                ;
-; -1.991 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.050 ns                  ; 6.041 ns                ;
-; -1.991 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.050 ns                  ; 6.041 ns                ;
-; -1.990 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.109 ns                ;
-; -1.990 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.119 ns                  ; 6.109 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.106 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]                                                                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 4.117 ns                  ; 6.106 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]                                                                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; -1.989 ns                               ; None                                                ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]                                                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns                    ; 3.822 ns                  ; 5.811 ns                ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                                                ;                                                                                                                                                                                                                  ;                                                                          ;          ;                             ;                           ;                         ;
-+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                         ;
-+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack ; From                                                                                              ; To                                                                                                ; From Clock                                                             ; To Clock                                                               ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 0.825 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.783 ns                 ;
-; 0.827 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.785 ns                 ;
-; 0.827 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.785 ns                 ;
-; 0.828 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.786 ns                 ;
-; 0.828 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.786 ns                 ;
-; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
-; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
-; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
-; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
-; 0.829 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.787 ns                 ;
-; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
-; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
-; 0.830 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
-; 0.831 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.789 ns                 ;
-; 0.831 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.789 ns                 ;
-; 0.832 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.790 ns                 ;
-; 0.833 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.791 ns                 ;
-; 1.185 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.143 ns                 ;
-; 1.353 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.311 ns                 ;
-; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.312 ns                 ;
-; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.311 ns                 ;
-; 1.354 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.312 ns                 ;
-; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
-; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
-; 1.356 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.314 ns                 ;
-; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
-; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
-; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
-; 1.357 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
-; 1.358 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.316 ns                 ;
-; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
-; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
-; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
-; 1.359 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.317 ns                 ;
-; 1.411 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.369 ns                 ;
-; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.370 ns                 ;
-; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.369 ns                 ;
-; 1.412 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.370 ns                 ;
-; 1.414 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.372 ns                 ;
-; 1.414 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.372 ns                 ;
-; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
-; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
-; 1.415 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
-; 1.416 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.374 ns                 ;
-; 1.416 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.373 ns                 ;
-; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
-; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
-; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
-; 1.417 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.375 ns                 ;
-; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.428 ns                 ;
-; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.427 ns                 ;
-; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.427 ns                 ;
-; 1.470 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.428 ns                 ;
-; 1.472 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.430 ns                 ;
-; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
-; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
-; 1.473 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
-; 1.474 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.432 ns                 ;
-; 1.474 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.431 ns                 ;
-; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
-; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
-; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
-; 1.475 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.433 ns                 ;
-; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.486 ns                 ;
-; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.485 ns                 ;
-; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.485 ns                 ;
-; 1.528 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.486 ns                 ;
-; 1.530 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.488 ns                 ;
-; 1.531 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
-; 1.531 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
-; 1.532 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.489 ns                 ;
-; 1.532 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.489 ns                 ;
-; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
-; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
-; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
-; 1.533 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.491 ns                 ;
-; 1.586 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.543 ns                 ;
-; 1.586 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.543 ns                 ;
-; 1.587 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.544 ns                 ;
-; 1.588 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.546 ns                 ;
-; 1.589 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.547 ns                 ;
-; 1.589 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.547 ns                 ;
-; 1.590 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.547 ns                 ;
-; 1.590 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.547 ns                 ;
-; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
-; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
-; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
-; 1.591 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.549 ns                 ;
-; 1.644 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.601 ns                 ;
-; 1.644 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.601 ns                 ;
-; 1.645 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.602 ns                 ;
-; 1.646 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.604 ns                 ;
-; 1.647 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.605 ns                 ;
-; 1.648 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.605 ns                 ;
-; 1.648 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.605 ns                 ;
-; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
-; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
-; 1.649 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.607 ns                 ;
-; 1.650 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.607 ns                 ;
-; 1.689 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.647 ns                 ;
-; 1.702 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.659 ns                 ;
-; 1.702 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.659 ns                 ;
-; 1.703 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.660 ns                 ;
-; 1.704 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.662 ns                 ;
-; 1.706 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.663 ns                 ;
-; 1.706 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.663 ns                 ;
-; 1.707 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.665 ns                 ;
-; 1.707 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.665 ns                 ;
-; 1.708 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.665 ns                 ;
-; 1.708 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.665 ns                 ;
-; 1.743 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.701 ns                 ;
-; 1.760 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.717 ns                 ;
-; 1.760 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.717 ns                 ;
-; 1.761 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.718 ns                 ;
-; 1.764 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.721 ns                 ;
-; 1.764 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.721 ns                 ;
-; 1.765 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.723 ns                 ;
-; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
-; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
-; 1.766 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.723 ns                 ;
-; 1.801 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.759 ns                 ;
-; 1.818 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.775 ns                 ;
-; 1.819 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.776 ns                 ;
-; 1.822 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.779 ns                 ;
-; 1.822 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.779 ns                 ;
-; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
-; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
-; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
-; 1.824 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.781 ns                 ;
-; 1.861 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.819 ns                 ;
-; 1.876 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.833 ns                 ;
-; 1.877 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.834 ns                 ;
-; 1.880 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.837 ns                 ;
-; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
-; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
-; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
-; 1.882 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.839 ns                 ;
-; 1.915 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.873 ns                 ;
-; 1.935 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.892 ns                 ;
-; 1.938 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.895 ns                 ;
-; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
-; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
-; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
-; 1.940 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.897 ns                 ;
-; 1.976 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.934 ns                 ;
-; 1.993 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.950 ns                 ;
-; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
-; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
-; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
-; 1.998 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.955 ns                 ;
-; 2.034 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.992 ns                 ;
-; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
-; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
-; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
-; 2.056 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.013 ns                 ;
-; 2.091 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 2.049 ns                 ;
-; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
-; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
-; 2.114 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.071 ns                 ;
-; 2.147 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.104 ns                 ;
-; 2.172 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.129 ns                 ;
-; 2.172 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.129 ns                 ;
-; 2.209 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.166 ns                 ;
-; 2.230 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.187 ns                 ;
-; 2.263 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.220 ns                 ;
-; 2.325 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.282 ns                 ;
-; 2.380 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.337 ns                 ;
-; 2.443 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.400 ns                 ;
-; 2.501 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.458 ns                 ;
-; 2.559 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.516 ns                 ;
-; 2.617 ns      ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]  ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 2.574 ns                 ;
-+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                           ;
-+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack ; From                                                                      ; To                                                                        ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 0.564 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.522 ns                 ;
-; 0.825 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.783 ns                 ;
-; 0.830 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.788 ns                 ;
-; 0.852 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.810 ns                 ;
-; 0.955 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.913 ns                 ;
-; 1.357 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.315 ns                 ;
-; 1.358 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.316 ns                 ;
-; 1.380 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.338 ns                 ;
-; 1.415 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.373 ns                 ;
-; 1.416 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.374 ns                 ;
-; 1.473 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.431 ns                 ;
-; 1.474 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.432 ns                 ;
-; 1.487 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.445 ns                 ;
-; 1.531 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.489 ns                 ;
-; 1.545 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.503 ns                 ;
-; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
-; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
-; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
-; 1.611 ns      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.569 ns                 ;
-+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                                                                               ; To                                                                                                                                                                                                                 ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR                                                                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3]                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3]                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1                                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5]                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5]                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2]                                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK                                                                                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK                                                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                                                                      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D                                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                                                                                                            ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV                                                                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY                                                                                               ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0]                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0]                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.547 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.505 ns                 ;
-; 0.549 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[19]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[3]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[3]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[12]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[13]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1]                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[7]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[6]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[18]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[21]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[1]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\ADRMARK_STROBES:DDATA_AM_LOCK                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|DDATA_AM                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[31]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.559 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7]                                                                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7]                                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
-; 0.562 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD                                                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
-; 0.563 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
-; 0.569 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                                                       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
-; 0.569 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11]                                                                      ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11]                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
-; 0.571 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
-; 0.572 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_ADR                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_AM                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
-; 0.572 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[5]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
-; 0.573 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[0]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.577 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[3]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.535 ns                 ;
-; 0.580 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a2                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.538 ns                 ;
-; 0.582 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.540 ns                 ;
-; 0.584 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1]                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.542 ns                 ;
-; 0.591 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.549 ns                 ;
-; 0.592 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a2                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.550 ns                 ;
-; 0.593 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.551 ns                 ;
-; 0.608 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.566 ns                 ;
-; 0.609 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.567 ns                 ;
-; 0.610 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.568 ns                 ;
-; 0.610 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.568 ns                 ;
-; 0.614 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.572 ns                 ;
-; 0.614 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.572 ns                 ;
-; 0.616 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.574 ns                 ;
-; 0.616 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.574 ns                 ;
-; 0.625 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.583 ns                 ;
-; 0.626 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.584 ns                 ;
-; 0.627 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6]                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.585 ns                 ;
-; 0.667 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[23]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.625 ns                 ;
-; 0.668 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[9]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.626 ns                 ;
-; 0.669 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[15]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.627 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[12]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[21]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.670 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[23]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.628 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[6]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[10]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[11]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[16]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[17]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[4]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[4]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.671 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7]                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8]                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
-; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13]                                                                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14]                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
-; 0.672 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.630 ns                 ;
-; 0.673 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.631 ns                 ;
-; 0.675 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.633 ns                 ;
-; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
-; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
-; 0.677 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3]                                                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4]                                                                                 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
-; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T1                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.679 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
-; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[4]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.639 ns                 ;
-; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
-; 0.680 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3                                                                                                                                     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T6                                                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
-; 0.681 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15]                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.639 ns                 ;
-; 0.683 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[14]                                                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[15]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.641 ns                 ;
-; 0.683 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[6]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.641 ns                 ;
-; 0.689 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[2]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.689 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1]                                                                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[0]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.649 ns                 ;
-; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.691 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.693 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2]                                              ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[1]                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.652 ns                 ;
-; 0.698 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; 0.330 ns                   ; 1.028 ns                 ;
-; 0.699 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[5]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
-; 0.700 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[1]                                                                                        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[1]                                                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[5]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[8]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.704 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.662 ns                 ;
-; 0.704 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.662 ns                 ;
-; 0.706 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[1]                                                                             ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[0]                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.664 ns                 ;
-; 0.708 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[7]                                                                                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.666 ns                 ;
-; 0.711 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1]                          ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[1]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.669 ns                 ;
-; 0.712 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.043 ns                  ; 0.669 ns                 ;
-; 0.712 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.670 ns                 ;
-; 0.714 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[6]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.673 ns                 ;
-; 0.715 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[3]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.673 ns                 ;
-; 0.715 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[2]                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.673 ns                 ;
-; 0.720 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_PRES                                                                                           ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[1]                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.678 ns                 ;
-; 0.724 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.682 ns                 ;
-; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7]                                                  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; 0.330 ns                   ; 1.056 ns                 ;
-; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[10]                                                 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[8]                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.041 ns                  ; 0.685 ns                 ;
-; 0.726 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8]                    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_g[8]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.684 ns                 ;
-; 0.728 ns                                ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2]                   ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[4]                                                  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns                   ; -0.042 ns                  ; 0.686 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                                                                                ;                                                                                                                                                                                                                    ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; -0.454 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.531 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.443 ns                 ;
-; 0.536 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.403 ns                   ; 2.939 ns                 ;
-; 0.538 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.450 ns                 ;
-; 0.538 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.450 ns                 ;
-; 0.541 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.453 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.908 ns                   ; 1.459 ns                 ;
-; 0.556 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.503 ns                 ;
-; 0.557 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.960 ns                   ; 1.517 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.471 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.935 ns                   ; 1.494 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.583 ns                   ; 1.143 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.476 ns                 ;
-; 0.561 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.478 ns                 ;
-; 0.564 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.570 ns                   ; 1.134 ns                 ;
-; 0.567 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.514 ns                 ;
-; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.486 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.905 ns                   ; 1.478 ns                 ;
-; 0.576 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.929 ns                   ; 1.505 ns                 ;
-; 0.578 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.490 ns                 ;
-; 0.579 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.493 ns                 ;
-; 0.580 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.864 ns                 ;
-; 0.583 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.919 ns                   ; 1.502 ns                 ;
-; 0.583 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.584 ns                   ; 1.167 ns                 ;
-; 0.583 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.494 ns                 ;
-; 0.584 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.551 ns                 ;
-; 0.585 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.496 ns                 ;
-; 0.586 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.500 ns                 ;
-; 0.588 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.504 ns                 ;
-; 0.589 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.495 ns                 ;
-; 0.589 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.909 ns                   ; 1.498 ns                 ;
-; 0.590 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.504 ns                 ;
-; 0.591 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.875 ns                 ;
-; 0.592 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.507 ns                 ;
-; 0.592 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.929 ns                   ; 1.521 ns                 ;
-; 0.597 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.511 ns                 ;
-; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.517 ns                 ;
-; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.524 ns                 ;
-; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.521 ns                 ;
-; 0.600 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.282 ns                   ; 1.882 ns                 ;
-; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.513 ns                 ;
-; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.926 ns                   ; 1.527 ns                 ;
-; 0.604 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.551 ns                 ;
-; 0.608 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.524 ns                 ;
-; 0.608 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.522 ns                 ;
-; 0.609 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.401 ns                   ; 3.010 ns                 ;
-; 0.610 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.894 ns                 ;
-; 0.611 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.528 ns                 ;
-; 0.613 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.527 ns                 ;
-; 0.613 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.530 ns                 ;
-; 0.613 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.580 ns                 ;
-; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.526 ns                 ;
-; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.526 ns                 ;
-; 0.614 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.531 ns                 ;
-; 0.614 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.561 ns                 ;
-; 0.614 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.531 ns                 ;
-; 0.617 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.534 ns                 ;
-; 0.618 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.962 ns                   ; 1.580 ns                 ;
-; 0.619 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.540 ns                 ;
-; 0.620 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.541 ns                 ;
-; 0.620 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.534 ns                 ;
-; 0.620 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.541 ns                 ;
-; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.542 ns                 ;
-; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.539 ns                 ;
-; 0.622 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.546 ns                 ;
-; 0.622 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.597 ns                   ; 1.219 ns                 ;
-; 0.622 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.528 ns                 ;
-; 0.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.537 ns                 ;
-; 0.623 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.544 ns                 ;
-; 0.623 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.283 ns                   ; 1.906 ns                 ;
-; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.547 ns                 ;
-; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.550 ns                 ;
-; 0.626 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.550 ns                 ;
-; 0.627 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.548 ns                 ;
-; 0.627 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.551 ns                 ;
-; 0.627 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.544 ns                 ;
-; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.543 ns                 ;
-; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.543 ns                 ;
-; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.912 ns                 ;
-; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.545 ns                 ;
-; 0.628 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.541 ns                 ;
-; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.550 ns                 ;
-; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.921 ns                   ; 1.550 ns                 ;
-; 0.629 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.553 ns                 ;
-; 0.630 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.544 ns                 ;
-; 0.630 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.554 ns                 ;
-; 0.631 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.545 ns                 ;
-; 0.632 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.588 ns                   ; 1.220 ns                 ;
-; 0.633 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.546 ns                 ;
-; 0.633 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.549 ns                 ;
-; 0.636 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.909 ns                   ; 1.545 ns                 ;
-; 0.637 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.551 ns                 ;
-; 0.637 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.551 ns                 ;
-; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.555 ns                 ;
-; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.549 ns                 ;
-; 0.638 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.552 ns                 ;
-; 0.639 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.556 ns                 ;
-; 0.639 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.555 ns                 ;
-; 0.641 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.558 ns                 ;
-; 0.641 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.555 ns                 ;
-; 0.642 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.558 ns                 ;
-; 0.643 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.557 ns                 ;
-; 0.644 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.558 ns                 ;
-; 0.644 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.611 ns                 ;
-; 0.645 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.557 ns                 ;
-; 0.646 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.560 ns                 ;
-; 0.646 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.586 ns                   ; 1.232 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.561 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.910 ns                   ; 1.557 ns                 ;
-; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.907 ns                   ; 1.555 ns                 ;
-; 0.648 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.577 ns                   ; 1.225 ns                 ;
-; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.560 ns                 ;
-; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.907 ns                   ; 1.555 ns                 ;
-; 0.648 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.562 ns                 ;
-; 0.649 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.566 ns                 ;
-; 0.649 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.567 ns                 ;
-; 0.649 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.563 ns                 ;
-; 0.650 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.568 ns                 ;
-; 0.650 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.570 ns                   ; 1.220 ns                 ;
-; 0.651 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.577 ns                   ; 1.228 ns                 ;
-; 0.651 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 2.404 ns                   ; 3.055 ns                 ;
-; 0.652 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.576 ns                 ;
-; 0.653 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.567 ns                 ;
-; 0.653 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.567 ns                 ;
-; 0.655 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.602 ns                 ;
-; 0.656 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.585 ns                   ; 1.241 ns                 ;
-; 0.656 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.282 ns                   ; 1.938 ns                 ;
-; 0.657 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.924 ns                   ; 1.581 ns                 ;
-; 0.657 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.571 ns                 ;
-; 0.658 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.905 ns                   ; 1.563 ns                 ;
-; 0.658 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.572 ns                 ;
-; 0.659 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.565 ns                 ;
-; 0.660 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.627 ns                 ;
-; 0.661 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.608 ns                 ;
-; 0.661 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.575 ns                 ;
-; 0.662 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.577 ns                 ;
-; 0.662 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.912 ns                   ; 1.574 ns                 ;
-; 0.662 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.576 ns                 ;
-; 0.662 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.918 ns                   ; 1.580 ns                 ;
-; 0.663 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.916 ns                   ; 1.579 ns                 ;
-; 0.663 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.947 ns                   ; 1.610 ns                 ;
-; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.911 ns                   ; 1.575 ns                 ;
-; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.930 ns                   ; 1.594 ns                 ;
-; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.906 ns                   ; 1.570 ns                 ;
-; 0.664 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.584 ns                 ;
-; 0.665 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.582 ns                 ;
-; 0.665 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.579 ns                 ;
-; 0.665 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.578 ns                 ;
-; 0.666 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.580 ns                 ;
-; 0.666 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.580 ns                 ;
-; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.581 ns                 ;
-; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.581 ns                 ;
-; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.920 ns                   ; 1.587 ns                 ;
-; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.580 ns                 ;
-; 0.667 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.634 ns                 ;
-; 0.669 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.585 ns                   ; 1.254 ns                 ;
-; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.913 ns                   ; 1.582 ns                 ;
-; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 1.284 ns                   ; 1.953 ns                 ;
-; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.967 ns                   ; 1.636 ns                 ;
-; 0.669 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.583 ns                 ;
-; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.914 ns                   ; 1.584 ns                 ;
-; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.917 ns                   ; 1.587 ns                 ;
-; 0.671 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.915 ns                   ; 1.586 ns                 ;
-; 0.671 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns                   ; 0.908 ns                   ; 1.579 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
-+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                    ; To                                                                                                                                                      ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1]                                                                                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                          ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC                                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                         ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ                                                                                                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[75]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[99]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[65]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[81]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.549 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[5]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.507 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[87]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[105]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[110]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[94]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.550 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.508 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[28]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[124]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[123]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[66]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[126]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[4]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[7]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.551 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe19a[0]                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0]                               ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.509 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[6]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[102]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[22]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[86]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[118]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[4]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[67]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[83]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C6                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.552 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.510 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[125]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[92]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[73]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[121]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.553 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[1]                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_DDR_SYNC                                                                                                     ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.511 ns                 ;
-; 0.554 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[120]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.512 ns                 ;
-; 0.554 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.512 ns                 ;
-; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
-; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
-; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
-; 0.558 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.516 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[42]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
-; 0.559 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[56]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.517 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[32]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
-; 0.560 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.518 ns                 ;
-; 0.561 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[39]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.519 ns                 ;
-; 0.561 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.519 ns                 ;
-; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
-; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[7]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
-; 0.562 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[8]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.520 ns                 ;
-; 0.563 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[52]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
-; 0.563 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[57]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.521 ns                 ;
-; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
-; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[31]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[31]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
-; 0.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.527 ns                 ;
-; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[8]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.528 ns                 ;
-; 0.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[16]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.528 ns                 ;
-; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
-; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[10]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
-; 0.571 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.529 ns                 ;
-; 0.572 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]                                                                                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]                                                                                                ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.530 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[84]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[84]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[95]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[95]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.573 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11                         ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.531 ns                 ;
-; 0.574 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.532 ns                 ;
-; 0.582 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[70]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[70]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.540 ns                 ;
-; 0.583 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]                                                                                               ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.541 ns                 ;
-; 0.592 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.550 ns                 ;
-; 0.593 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a1                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.551 ns                 ;
-; 0.595 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.553 ns                 ;
-; 0.601 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.559 ns                 ;
-; 0.604 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.562 ns                 ;
-; 0.605 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.563 ns                 ;
-; 0.605 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8]                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.563 ns                 ;
-; 0.643 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.340 ns                   ; 0.983 ns                 ;
-; 0.647 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.332 ns                   ; 0.979 ns                 ;
-; 0.654 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 0.988 ns                 ;
-; 0.670 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.332 ns                   ; 1.002 ns                 ;
-; 0.671 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.629 ns                 ;
-; 0.673 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 1.007 ns                 ;
-; 0.675 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[26]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[90]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.633 ns                 ;
-; 0.676 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C2                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.634 ns                 ;
-; 0.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[13]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
-; 0.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[24]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[88]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.635 ns                 ;
-; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[97]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.678 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                 ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.636 ns                 ;
-; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[21]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[85]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
-; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[4]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[100]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
-; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
-; 0.679 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.637 ns                 ;
-; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[29]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[93]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
-; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[18]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[114]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
-; 0.680 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[3]                                              ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.638 ns                 ;
-; 0.681 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[2]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[98]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.639 ns                 ;
-; 0.687 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.645 ns                 ;
-; 0.687 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.645 ns                 ;
-; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
-; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
-; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
-; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
-; 0.688 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[9]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.646 ns                 ;
-; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[41]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.689 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[49]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.647 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[44]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[3]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[33]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[61]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.690 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.648 ns                 ;
-; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[12]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[43]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[1]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.691 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[17]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.649 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[5]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1]                                                                                    ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[54]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[91]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.649 ns                 ;
-; 0.692 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_N5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.650 ns                 ;
-; 0.693 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.651 ns                 ;
-; 0.694 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.334 ns                   ; 1.028 ns                 ;
-; 0.695 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[106]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[23]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[13]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[45]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[77]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[15]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[15]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[13]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[109]                                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.655 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[12]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[27]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[14]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[14]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.656 ns                 ;
-; 0.698 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 0.657 ns                 ;
-; 0.699 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
-; 0.699 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[78]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[78]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.657 ns                 ;
-; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[28]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[21]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[53]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.700 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[82]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.700 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7W                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8W                                                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.658 ns                 ;
-; 0.701 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[15]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1                                                                                                            ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R2                                                                                                            ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.701 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T4W                                                                                                           ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T5W                                                                                                           ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.659 ns                 ;
-; 0.703 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.661 ns                 ;
-; 0.703 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.661 ns                 ;
-; 0.704 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.031 ns                 ;
-; 0.705 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.341 ns                   ; 1.046 ns                 ;
-; 0.706 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]                    ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.033 ns                 ;
-; 0.707 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[51]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.665 ns                 ;
-; 0.710 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[0]                                                                                   ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 0.669 ns                 ;
-; 0.712 ns                                ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[40]                                                                                  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 0.669 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                     ;                                                                                                                                                         ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
-+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack ; From                                                                                                                             ; To                                                                                                                                ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
-; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
-; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
-; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
-; 4.336 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.507 ns                 ;
-; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
-; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
-; 4.337 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.508 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.338 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.509 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.339 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.510 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.340 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.511 ns                 ;
-; 4.465 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.636 ns                 ;
-; 4.466 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.637 ns                 ;
-; 4.467 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.638 ns                 ;
-; 4.468 ns      ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns                  ; -3.829 ns                  ; 0.639 ns                 ;
-+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'                                                                                                                                                                                                                                                                                               ;
-+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack ; From                                              ; To                                                                    ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 1.825 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.508 ns                 ;
-; 1.827 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.510 ns                 ;
-; 1.953 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.636 ns                 ;
-; 1.954 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.317 ns                  ; 0.637 ns                 ;
-; 2.134 ns      ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns                  ; -1.315 ns                  ; 0.819 ns                 ;
-+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'                                                                                                                                                                                                                                                                                                                                                                                                            ;
-+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                   ; To                                                                                                                                  ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 3.263 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.570 ns                 ;
-; 3.273 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.580 ns                 ;
-; 3.460 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.363 ns                 ;
-; 3.511 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 1.818 ns                 ;
-; 3.539 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 1.845 ns                 ;
-; 3.543 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 1.857 ns                 ;
-; 3.548 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 1.860 ns                 ;
-; 3.569 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 1.874 ns                 ;
-; 3.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 1.882 ns                 ;
-; 3.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.667 ns                  ; 1.906 ns                 ;
-; 3.609 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 1.937 ns                 ;
-; 3.618 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 1.929 ns                 ;
-; 3.637 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 1.952 ns                 ;
-; 3.656 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 1.959 ns                 ;
-; 3.660 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 1.974 ns                 ;
-; 3.674 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 1.983 ns                 ;
-; 3.686 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.692 ns                  ; 1.994 ns                 ;
-; 3.719 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.024 ns                 ;
-; 3.721 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 2.030 ns                 ;
-; 3.730 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.698 ns                  ; 2.032 ns                 ;
-; 3.731 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.634 ns                 ;
-; 3.737 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.042 ns                 ;
-; 3.740 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.664 ns                  ; 2.076 ns                 ;
-; 3.745 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.668 ns                  ; 2.077 ns                 ;
-; 3.754 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.059 ns                 ;
-; 3.769 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 3.672 ns                 ;
-; 3.774 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 2.077 ns                 ;
-; 3.776 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 2.091 ns                 ;
-; 3.777 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.698 ns                  ; 2.079 ns                 ;
-; 3.778 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 2.085 ns                 ;
-; 3.780 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.084 ns                 ;
-; 3.781 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.684 ns                  ; 2.097 ns                 ;
-; 3.784 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.089 ns                 ;
-; 3.784 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.684 ns                  ; 2.100 ns                 ;
-; 3.786 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.097 ns                 ;
-; 3.792 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 3.693 ns                 ;
-; 3.794 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.692 ns                  ; 2.102 ns                 ;
-; 3.796 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.107 ns                 ;
-; 3.811 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.125 ns                 ;
-; 3.814 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.688 ns                  ; 2.126 ns                 ;
-; 3.819 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.697 ns                  ; 2.122 ns                 ;
-; 3.836 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.695 ns                  ; 2.141 ns                 ;
-; 3.838 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 3.735 ns                 ;
-; 3.839 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.101 ns                  ; 3.738 ns                 ;
-; 3.855 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.755 ns                 ;
-; 3.866 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 3.763 ns                 ;
-; 3.899 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 2.205 ns                 ;
-; 3.902 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.203 ns                 ;
-; 3.906 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.722 ns                  ; 2.184 ns                 ;
-; 3.916 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 3.812 ns                 ;
-; 3.920 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.234 ns                 ;
-; 3.932 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.686 ns                  ; 2.246 ns                 ;
-; 3.933 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.613 ns                  ; 2.320 ns                 ;
-; 3.935 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.239 ns                 ;
-; 3.936 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 3.837 ns                 ;
-; 3.944 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.694 ns                  ; 2.250 ns                 ;
-; 3.951 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.851 ns                 ;
-; 3.973 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.101 ns                  ; 3.872 ns                 ;
-; 3.979 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.283 ns                 ;
-; 3.989 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.693 ns                  ; 2.296 ns                 ;
-; 4.004 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.904 ns                 ;
-; 4.029 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 3.931 ns                 ;
-; 4.042 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.683 ns                  ; 2.359 ns                 ;
-; 4.043 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.685 ns                  ; 2.358 ns                 ;
-; 4.043 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.344 ns                 ;
-; 4.048 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.696 ns                  ; 2.352 ns                 ;
-; 4.078 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 3.978 ns                 ;
-; 4.084 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 3.980 ns                 ;
-; 4.096 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 3.998 ns                 ;
-; 4.110 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.104 ns                  ; 4.006 ns                 ;
-; 4.112 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.371 ns                 ;
-; 4.112 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.689 ns                  ; 2.423 ns                 ;
-; 4.115 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.012 ns                 ;
-; 4.117 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.014 ns                 ;
-; 4.132 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.097 ns                  ; 4.035 ns                 ;
-; 4.168 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.429 ns                 ;
-; 4.169 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.699 ns                  ; 2.470 ns                 ;
-; 4.185 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.454 ns                 ;
-; 4.187 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.723 ns                  ; 2.464 ns                 ;
-; 4.195 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.431 ns                 ;
-; 4.196 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.713 ns                  ; 2.483 ns                 ;
-; 4.201 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 2.447 ns                 ;
-; 4.221 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.714 ns                  ; 2.507 ns                 ;
-; 4.231 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.614 ns                  ; 2.617 ns                 ;
-; 4.232 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.133 ns                 ;
-; 4.232 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.674 ns                  ; 2.558 ns                 ;
-; 4.235 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.103 ns                  ; 4.132 ns                 ;
-; 4.236 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.102 ns                  ; 4.134 ns                 ;
-; 4.239 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.673 ns                  ; 2.566 ns                 ;
-; 4.243 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.479 ns                 ;
-; 4.249 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.669 ns                  ; 2.580 ns                 ;
-; 4.251 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.152 ns                 ;
-; 4.269 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.099 ns                  ; 4.170 ns                 ;
-; 4.283 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.185 ns                 ;
-; 4.286 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.188 ns                 ;
-; 4.296 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.670 ns                  ; 2.626 ns                 ;
-; 4.313 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.666 ns                  ; 2.647 ns                 ;
-; 4.314 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.691 ns                  ; 2.623 ns                 ;
-; 4.331 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 2.596 ns                 ;
-; 4.333 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.145 ns                  ; 4.188 ns                 ;
-; 4.343 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.145 ns                  ; 4.198 ns                 ;
-; 4.347 ns                                ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns                  ; -1.665 ns                  ; 2.682 ns                 ;
-; 4.352 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.098 ns                  ; 4.254 ns                 ;
-; 4.352 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 4.252 ns                 ;
-; 4.362 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.717 ns                  ; 2.645 ns                 ;
-; 4.367 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.608 ns                 ;
-; 4.376 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.635 ns                 ;
-; 4.384 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.102 ns                  ; 4.282 ns                 ;
-; 4.406 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.615 ns                  ; 2.791 ns                 ;
-; 4.409 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.645 ns                 ;
-; 4.410 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.646 ns                 ;
-; 4.411 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.159 ns                  ; 4.252 ns                 ;
-; 4.417 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.746 ns                  ; 2.671 ns                 ;
-; 4.425 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.100 ns                  ; 4.325 ns                 ;
-; 4.431 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.670 ns                  ; 2.761 ns                 ;
-; 4.434 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.695 ns                 ;
-; 4.440 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.685 ns                 ;
-; 4.450 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.719 ns                 ;
-; 4.475 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.741 ns                  ; 2.734 ns                 ;
-; 4.477 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 2.805 ns                 ;
-; 4.478 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.730 ns                  ; 2.748 ns                 ;
-; 4.480 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.757 ns                  ; 2.723 ns                 ;
-; 4.485 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.736 ns                 ;
-; 4.486 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.672 ns                  ; 2.814 ns                 ;
-; 4.497 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.351 ns                 ;
-; 4.498 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.329 ns                 ;
-; 4.527 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 2.773 ns                 ;
-; 4.530 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 2.791 ns                 ;
-; 4.555 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 2.804 ns                 ;
-; 4.556 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.163 ns                  ; 4.393 ns                 ;
-; 4.573 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.818 ns                 ;
-; 4.587 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.615 ns                  ; 2.972 ns                 ;
-; 4.597 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.429 ns                 ;
-; 4.600 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 2.865 ns                 ;
-; 4.601 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.852 ns                 ;
-; 4.601 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.433 ns                 ;
-; 4.613 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.674 ns                  ; 2.939 ns                 ;
-; 4.614 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.855 ns                 ;
-; 4.618 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 2.867 ns                 ;
-; 4.623 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.159 ns                  ; 4.464 ns                 ;
-; 4.626 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.742 ns                  ; 2.884 ns                 ;
-; 4.630 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.740 ns                  ; 2.890 ns                 ;
-; 4.633 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 2.874 ns                 ;
-; 4.636 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.150 ns                  ; 4.486 ns                 ;
-; 4.637 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.906 ns                 ;
-; 4.660 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 2.911 ns                 ;
-; 4.670 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.517 ns                 ;
-; 4.671 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.164 ns                  ; 4.507 ns                 ;
-; 4.676 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.912 ns                 ;
-; 4.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.745 ns                  ; 2.932 ns                 ;
-; 4.677 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.764 ns                  ; 2.913 ns                 ;
-; 4.686 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.746 ns                  ; 2.940 ns                 ;
-; 4.690 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.726 ns                  ; 2.964 ns                 ;
-; 4.697 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.168 ns                  ; 4.529 ns                 ;
-; 4.699 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.874 ns                  ; 1.825 ns                 ;
-; 4.704 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 2.949 ns                 ;
-; 4.709 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.664 ns                  ; 3.045 ns                 ;
-; 4.722 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 2.991 ns                 ;
-; 4.749 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.603 ns                 ;
-; 4.753 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.004 ns                 ;
-; 4.780 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.155 ns                  ; 4.625 ns                 ;
-; 4.787 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.156 ns                  ; 4.631 ns                 ;
-; 4.791 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.638 ns                 ;
-; 4.805 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.730 ns                  ; 3.075 ns                 ;
-; 4.809 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.640 ns                 ;
-; 4.823 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 3.072 ns                 ;
-; 4.825 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.163 ns                  ; 4.662 ns                 ;
-; 4.840 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.712 ns                  ; 3.128 ns                 ;
-; 4.844 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.735 ns                  ; 3.109 ns                 ;
-; 4.844 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.155 ns                  ; 4.689 ns                 ;
-; 4.845 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.154 ns                  ; 4.691 ns                 ;
-; 4.846 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.146 ns                  ; 4.700 ns                 ;
-; 4.863 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.755 ns                  ; 3.108 ns                 ;
-; 4.869 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.131 ns                 ;
-; 4.871 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.122 ns                 ;
-; 4.878 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.153 ns                  ; 4.725 ns                 ;
-; 4.881 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.169 ns                  ; 4.712 ns                 ;
-; 4.885 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.751 ns                  ; 3.134 ns                 ;
-; 4.888 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.156 ns                  ; 4.732 ns                 ;
-; 4.892 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.147 ns                  ; 4.745 ns                 ;
-; 4.892 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.742 ns                  ; 3.150 ns                 ;
-; 4.896 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.740 ns                  ; 3.156 ns                 ;
-; 4.906 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.731 ns                  ; 3.175 ns                 ;
-; 4.916 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90                                                                                                       ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.866 ns                  ; 2.050 ns                 ;
-; 4.916 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.151 ns                  ; 4.765 ns                 ;
-; 4.924 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.749 ns                  ; 3.175 ns                 ;
-; 4.942 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.745 ns                  ; 3.197 ns                 ;
-; 4.979 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.160 ns                  ; 4.819 ns                 ;
-; 5.007 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.754 ns                  ; 3.253 ns                 ;
-; 5.009 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.759 ns                  ; 3.250 ns                 ;
-; 5.013 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.726 ns                  ; 3.287 ns                 ;
-; 5.029 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.164 ns                  ; 4.865 ns                 ;
-; 5.047 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.739 ns                  ; 3.308 ns                 ;
-; 5.088 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_3                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.869 ns                  ; 2.219 ns                 ;
-; 5.096 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR                       ; Video:Fredi_Aschwanden|inst90~_Duplicate_1                                                                                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns                  ; -2.933 ns                  ; 2.163 ns                 ;
-; 5.124 ns                                ; Video:Fredi_Aschwanden|inst90~_Duplicate_4                             ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns                   ; -0.154 ns                  ; 4.970 ns                 ;
-; 5.133 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.395 ns                 ;
-; 5.143 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.722 ns                  ; 3.421 ns                 ;
-; 5.166 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.738 ns                  ; 3.428 ns                 ;
-; 5.205 ns                                ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI  ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns                  ; -1.720 ns                  ; 3.485 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                    ;                                                                                                                                     ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'                                                                                                                                                                                                                                                                                                                                                        ;
-+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                            ; To                                                                     ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
-; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
-; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
-; 2.664 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.216 ns                 ;
-; 2.679 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.447 ns                  ; 2.232 ns                 ;
-; 2.684 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.447 ns                  ; 2.237 ns                 ;
-; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
-; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
-; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
-; 2.686 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9]                          ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.448 ns                  ; 2.238 ns                 ;
-; 2.714 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.264 ns                 ;
-; 2.714 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.264 ns                 ;
-; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
-; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
-; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
-; 2.716 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.266 ns                 ;
-; 2.769 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.319 ns                 ;
-; 2.769 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.450 ns                  ; 2.319 ns                 ;
-; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
-; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
-; 2.790 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.449 ns                  ; 2.341 ns                 ;
-; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
-; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
-; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
-; 2.794 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.451 ns                  ; 2.343 ns                 ;
-; 2.948 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -1.264 ns                  ; -1.316 ns                  ; 1.632 ns                 ;
-; 3.033 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.589 ns                 ;
-; 3.033 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.589 ns                 ;
-; 3.088 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.042 ns                  ; 3.046 ns                 ;
-; 3.100 ns                                ; FB_ALE                                                                          ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27]                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.444 ns                  ; 2.656 ns                 ;
-; 3.146 ns                                ; FB_ALE                                                                          ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns                   ; -0.316 ns                  ; 2.830 ns                 ;
-; 6.237 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.309 ns                  ; 1.928 ns                 ;
-; 6.282 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.386 ns                  ; 1.896 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.650 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.288 ns                 ;
-; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
-; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
-; 6.738 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.361 ns                  ; 2.377 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.739 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.358 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.775 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.413 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.981 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.619 ns                 ;
-; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
-; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
-; 6.987 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.624 ns                 ;
-; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
-; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
-; 7.023 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.363 ns                  ; 2.660 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.036 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.373 ns                  ; 2.663 ns                 ;
-; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
-; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
-; 7.043 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.362 ns                  ; 2.681 ns                 ;
-; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
-; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
-; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
-; 7.045 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.354 ns                  ; 2.691 ns                 ;
-; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
-; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
-; 7.106 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.381 ns                  ; 2.725 ns                 ;
-; 7.218 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT                                  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.355 ns                  ; 2.863 ns                 ;
-; 7.413 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.650 ns                  ; 2.763 ns                 ;
-; 7.427 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                         ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.650 ns                  ; 2.777 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.430 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.804 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.478 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.018 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.508 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.048 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.512 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.052 ns                 ;
-; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
-; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
-; 7.518 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.625 ns                  ; 2.893 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.524 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.064 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.531 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.071 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.555 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.626 ns                  ; 2.929 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.561 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.460 ns                  ; 3.101 ns                 ;
-; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
-; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
-; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
-; 7.571 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.622 ns                  ; 2.949 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.598 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.471 ns                  ; 3.127 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]  ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.629 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.278 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.675 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.351 ns                  ; 3.324 ns                 ;
-; 7.686 ns                                ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                   ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK                                                                 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns                  ; -4.470 ns                  ; 3.216 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                             ;                                                                        ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock                                                               ; To Clock                                                                 ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 0.502 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 0.460 ns                 ;
-; 1.487 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.443 ns                 ;
-; 1.492 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.447 ns                   ; 2.939 ns                 ;
-; 1.494 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.450 ns                 ;
-; 1.494 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.450 ns                 ;
-; 1.497 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.453 ns                 ;
-; 1.507 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.048 ns                  ; 1.459 ns                 ;
-; 1.512 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.503 ns                 ;
-; 1.513 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.004 ns                   ; 1.517 ns                 ;
-; 1.515 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.471 ns                 ;
-; 1.515 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.021 ns                  ; 1.494 ns                 ;
-; 1.516 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.373 ns                  ; 1.143 ns                 ;
-; 1.516 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.476 ns                 ;
-; 1.517 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.478 ns                 ;
-; 1.520 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.386 ns                  ; 1.134 ns                 ;
-; 1.523 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.514 ns                 ;
-; 1.526 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.486 ns                 ;
-; 1.529 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.051 ns                  ; 1.478 ns                 ;
-; 1.532 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.027 ns                  ; 1.505 ns                 ;
-; 1.534 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.490 ns                 ;
-; 1.535 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.493 ns                 ;
-; 1.536 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.864 ns                 ;
-; 1.539 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.037 ns                  ; 1.502 ns                 ;
-; 1.539 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.372 ns                  ; 1.167 ns                 ;
-; 1.539 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.494 ns                 ;
-; 1.540 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.551 ns                 ;
-; 1.541 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.496 ns                 ;
-; 1.542 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.500 ns                 ;
-; 1.544 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.504 ns                 ;
-; 1.545 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.495 ns                 ;
-; 1.545 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.047 ns                  ; 1.498 ns                 ;
-; 1.546 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.504 ns                 ;
-; 1.547 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.875 ns                 ;
-; 1.548 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.507 ns                 ;
-; 1.548 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.027 ns                  ; 1.521 ns                 ;
-; 1.553 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.511 ns                 ;
-; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.517 ns                 ;
-; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.524 ns                 ;
-; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.521 ns                 ;
-; 1.556 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.326 ns                   ; 1.882 ns                 ;
-; 1.557 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.513 ns                 ;
-; 1.557 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.030 ns                  ; 1.527 ns                 ;
-; 1.560 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.551 ns                 ;
-; 1.564 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.524 ns                 ;
-; 1.564 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.522 ns                 ;
-; 1.565 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.445 ns                   ; 3.010 ns                 ;
-; 1.566 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.894 ns                 ;
-; 1.567 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.528 ns                 ;
-; 1.569 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.527 ns                 ;
-; 1.569 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.530 ns                 ;
-; 1.569 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.580 ns                 ;
-; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.526 ns                 ;
-; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.526 ns                 ;
-; 1.570 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.531 ns                 ;
-; 1.570 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.561 ns                 ;
-; 1.570 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.531 ns                 ;
-; 1.573 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.534 ns                 ;
-; 1.574 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.006 ns                   ; 1.580 ns                 ;
-; 1.575 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.540 ns                 ;
-; 1.576 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.541 ns                 ;
-; 1.576 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.534 ns                 ;
-; 1.576 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.541 ns                 ;
-; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.542 ns                 ;
-; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.539 ns                 ;
-; 1.578 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.546 ns                 ;
-; 1.578 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.359 ns                  ; 1.219 ns                 ;
-; 1.578 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.528 ns                 ;
-; 1.579 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.537 ns                 ;
-; 1.579 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.544 ns                 ;
-; 1.579 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.327 ns                   ; 1.906 ns                 ;
-; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.547 ns                 ;
-; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.550 ns                 ;
-; 1.582 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.550 ns                 ;
-; 1.583 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.548 ns                 ;
-; 1.583 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.551 ns                 ;
-; 1.583 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.544 ns                 ;
-; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.543 ns                 ;
-; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.543 ns                 ;
-; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.912 ns                 ;
-; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.545 ns                 ;
-; 1.584 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.541 ns                 ;
-; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.550 ns                 ;
-; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.035 ns                  ; 1.550 ns                 ;
-; 1.585 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.553 ns                 ;
-; 1.586 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.544 ns                 ;
-; 1.586 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.554 ns                 ;
-; 1.587 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.545 ns                 ;
-; 1.588 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.368 ns                  ; 1.220 ns                 ;
-; 1.589 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.546 ns                 ;
-; 1.589 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.549 ns                 ;
-; 1.592 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.047 ns                  ; 1.545 ns                 ;
-; 1.593 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.551 ns                 ;
-; 1.593 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.551 ns                 ;
-; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.555 ns                 ;
-; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.549 ns                 ;
-; 1.594 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.552 ns                 ;
-; 1.595 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.556 ns                 ;
-; 1.595 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.555 ns                 ;
-; 1.597 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.558 ns                 ;
-; 1.597 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.555 ns                 ;
-; 1.598 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.558 ns                 ;
-; 1.599 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.557 ns                 ;
-; 1.600 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.558 ns                 ;
-; 1.600 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.611 ns                 ;
-; 1.601 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.557 ns                 ;
-; 1.602 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.560 ns                 ;
-; 1.602 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.370 ns                  ; 1.232 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.561 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.603 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.046 ns                  ; 1.557 ns                 ;
-; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.049 ns                  ; 1.555 ns                 ;
-; 1.604 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.379 ns                  ; 1.225 ns                 ;
-; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.560 ns                 ;
-; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.049 ns                  ; 1.555 ns                 ;
-; 1.604 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.562 ns                 ;
-; 1.605 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.566 ns                 ;
-; 1.605 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.567 ns                 ;
-; 1.605 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.563 ns                 ;
-; 1.606 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.568 ns                 ;
-; 1.606 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.386 ns                  ; 1.220 ns                 ;
-; 1.607 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.379 ns                  ; 1.228 ns                 ;
-; 1.607 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 1.448 ns                   ; 3.055 ns                 ;
-; 1.608 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.576 ns                 ;
-; 1.609 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.567 ns                 ;
-; 1.609 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.567 ns                 ;
-; 1.611 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.602 ns                 ;
-; 1.612 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.371 ns                  ; 1.241 ns                 ;
-; 1.612 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.326 ns                   ; 1.938 ns                 ;
-; 1.613 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.032 ns                  ; 1.581 ns                 ;
-; 1.613 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.571 ns                 ;
-; 1.614 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.051 ns                  ; 1.563 ns                 ;
-; 1.614 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.572 ns                 ;
-; 1.615 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.565 ns                 ;
-; 1.616 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.627 ns                 ;
-; 1.617 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.608 ns                 ;
-; 1.617 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.575 ns                 ;
-; 1.618 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.577 ns                 ;
-; 1.618 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.044 ns                  ; 1.574 ns                 ;
-; 1.618 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.576 ns                 ;
-; 1.618 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.038 ns                  ; 1.580 ns                 ;
-; 1.619 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.040 ns                  ; 1.579 ns                 ;
-; 1.619 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.009 ns                  ; 1.610 ns                 ;
-; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.045 ns                  ; 1.575 ns                 ;
-; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.026 ns                  ; 1.594 ns                 ;
-; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.050 ns                  ; 1.570 ns                 ;
-; 1.620 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.584 ns                 ;
-; 1.621 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.582 ns                 ;
-; 1.621 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.579 ns                 ;
-; 1.621 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.578 ns                 ;
-; 1.622 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.580 ns                 ;
-; 1.622 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.580 ns                 ;
-; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.581 ns                 ;
-; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.581 ns                 ;
-; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.036 ns                  ; 1.587 ns                 ;
-; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.580 ns                 ;
-; 1.623 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.634 ns                 ;
-; 1.625 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.371 ns                  ; 1.254 ns                 ;
-; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.043 ns                  ; 1.582 ns                 ;
-; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.328 ns                   ; 1.953 ns                 ;
-; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; 0.011 ns                   ; 1.636 ns                 ;
-; 1.625 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.583 ns                 ;
-; 1.626 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.584 ns                 ;
-; 1.626 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.039 ns                  ; 1.587 ns                 ;
-; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.041 ns                  ; 1.586 ns                 ;
-; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.048 ns                  ; 1.579 ns                 ;
-; 1.627 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns                   ; -0.042 ns                  ; 1.585 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;                                                                          ;                                                                          ;                            ;                            ;                          ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'CLK33M'                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; -0.687 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 0.460 ns                 ;
-; 0.298 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.443 ns                 ;
-; 0.303 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.636 ns                   ; 2.939 ns                 ;
-; 0.305 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.450 ns                 ;
-; 0.305 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.450 ns                 ;
-; 0.308 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.453 ns                 ;
-; 0.318 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.141 ns                   ; 1.459 ns                 ;
-; 0.323 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.503 ns                 ;
-; 0.324 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.193 ns                   ; 1.517 ns                 ;
-; 0.326 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.471 ns                 ;
-; 0.326 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.168 ns                   ; 1.494 ns                 ;
-; 0.327 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.816 ns                   ; 1.143 ns                 ;
-; 0.327 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.476 ns                 ;
-; 0.328 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.478 ns                 ;
-; 0.331 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.803 ns                   ; 1.134 ns                 ;
-; 0.334 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.514 ns                 ;
-; 0.337 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.486 ns                 ;
-; 0.340 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.138 ns                   ; 1.478 ns                 ;
-; 0.343 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.162 ns                   ; 1.505 ns                 ;
-; 0.345 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.490 ns                 ;
-; 0.346 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.493 ns                 ;
-; 0.347 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.864 ns                 ;
-; 0.350 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.152 ns                   ; 1.502 ns                 ;
-; 0.350 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.817 ns                   ; 1.167 ns                 ;
-; 0.350 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.494 ns                 ;
-; 0.351 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.551 ns                 ;
-; 0.352 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.496 ns                 ;
-; 0.353 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.500 ns                 ;
-; 0.355 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.504 ns                 ;
-; 0.356 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.495 ns                 ;
-; 0.356 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.142 ns                   ; 1.498 ns                 ;
-; 0.357 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.504 ns                 ;
-; 0.358 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.875 ns                 ;
-; 0.359 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.507 ns                 ;
-; 0.359 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.162 ns                   ; 1.521 ns                 ;
-; 0.364 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.511 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.517 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.524 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.521 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.515 ns                   ; 1.882 ns                 ;
-; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.513 ns                 ;
-; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.159 ns                   ; 1.527 ns                 ;
-; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.551 ns                 ;
-; 0.375 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.524 ns                 ;
-; 0.375 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.522 ns                 ;
-; 0.376 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                            ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.634 ns                   ; 3.010 ns                 ;
-; 0.377 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.894 ns                 ;
-; 0.378 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                       ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.528 ns                 ;
-; 0.380 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.527 ns                 ;
-; 0.380 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.530 ns                 ;
-; 0.380 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.580 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.526 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.526 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.531 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.561 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.531 ns                 ;
-; 0.384 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.534 ns                 ;
-; 0.385 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.195 ns                   ; 1.580 ns                 ;
-; 0.386 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.540 ns                 ;
-; 0.387 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.541 ns                 ;
-; 0.387 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.534 ns                 ;
-; 0.387 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.541 ns                 ;
-; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.542 ns                 ;
-; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.539 ns                 ;
-; 0.389 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.546 ns                 ;
-; 0.389 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.830 ns                   ; 1.219 ns                 ;
-; 0.389 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0]                                                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0]                                                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.528 ns                 ;
-; 0.390 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.537 ns                 ;
-; 0.390 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.544 ns                 ;
-; 0.390 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.516 ns                   ; 1.906 ns                 ;
-; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.547 ns                 ;
-; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.550 ns                 ;
-; 0.393 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.550 ns                 ;
-; 0.394 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.548 ns                 ;
-; 0.394 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.551 ns                 ;
-; 0.394 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3]                                                                  ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3]                                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.544 ns                 ;
-; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.543 ns                 ;
-; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6]                                                          ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.543 ns                 ;
-; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.912 ns                 ;
-; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.545 ns                 ;
-; 0.395 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.541 ns                 ;
-; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.550 ns                 ;
-; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.154 ns                   ; 1.550 ns                 ;
-; 0.396 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.553 ns                 ;
-; 0.397 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.544 ns                 ;
-; 0.397 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.554 ns                 ;
-; 0.398 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.545 ns                 ;
-; 0.399 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.821 ns                   ; 1.220 ns                 ;
-; 0.400 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.546 ns                 ;
-; 0.400 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5]                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6]                                                                                               ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.549 ns                 ;
-; 0.403 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.142 ns                   ; 1.545 ns                 ;
-; 0.404 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.551 ns                 ;
-; 0.404 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.551 ns                 ;
-; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.555 ns                 ;
-; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.549 ns                 ;
-; 0.405 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.552 ns                 ;
-; 0.406 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.556 ns                 ;
-; 0.406 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.555 ns                 ;
-; 0.408 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.558 ns                 ;
-; 0.408 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.555 ns                 ;
-; 0.409 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.558 ns                 ;
-; 0.410 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.557 ns                 ;
-; 0.411 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30                                                      ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.558 ns                 ;
-; 0.411 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.611 ns                 ;
-; 0.412 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.557 ns                 ;
-; 0.413 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107]                                                       ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.560 ns                 ;
-; 0.413 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8]                         ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.819 ns                   ; 1.232 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.561 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10]                                                                                             ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11]                                                                                             ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.414 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                             ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1]                                                                                              ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.143 ns                   ; 1.557 ns                 ;
-; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.140 ns                   ; 1.555 ns                 ;
-; 0.415 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.810 ns                   ; 1.225 ns                 ;
-; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114]                                 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.560 ns                 ;
-; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.140 ns                   ; 1.555 ns                 ;
-; 0.415 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.562 ns                 ;
-; 0.416 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.566 ns                 ;
-; 0.416 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.567 ns                 ;
-; 0.416 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.563 ns                 ;
-; 0.417 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.568 ns                 ;
-; 0.417 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107]                       ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107]                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.803 ns                   ; 1.220 ns                 ;
-; 0.418 ns                                ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0]                                 ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.810 ns                   ; 1.228 ns                 ;
-; 0.418 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO                                                                      ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 2.637 ns                   ; 3.055 ns                 ;
-; 0.419 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.576 ns                 ;
-; 0.420 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.567 ns                 ;
-; 0.420 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.567 ns                 ;
-; 0.422 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.602 ns                 ;
-; 0.423 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.818 ns                   ; 1.241 ns                 ;
-; 0.423 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.515 ns                   ; 1.938 ns                 ;
-; 0.424 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.157 ns                   ; 1.581 ns                 ;
-; 0.424 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.571 ns                 ;
-; 0.425 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46]                                   ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.138 ns                   ; 1.563 ns                 ;
-; 0.425 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.572 ns                 ;
-; 0.426 ns                                ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.565 ns                 ;
-; 0.427 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.627 ns                 ;
-; 0.428 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.608 ns                 ;
-; 0.428 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.575 ns                 ;
-; 0.429 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.577 ns                 ;
-; 0.429 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4]                                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.145 ns                   ; 1.574 ns                 ;
-; 0.429 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.576 ns                 ;
-; 0.429 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4]                                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.151 ns                   ; 1.580 ns                 ;
-; 0.430 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.149 ns                   ; 1.579 ns                 ;
-; 0.430 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.180 ns                   ; 1.610 ns                 ;
-; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.144 ns                   ; 1.575 ns                 ;
-; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21]                                                                              ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.163 ns                   ; 1.594 ns                 ;
-; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.139 ns                   ; 1.570 ns                 ;
-; 0.431 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.584 ns                 ;
-; 0.432 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.582 ns                 ;
-; 0.432 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1]                                                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.579 ns                 ;
-; 0.432 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.578 ns                 ;
-; 0.433 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4                                                       ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.580 ns                 ;
-; 0.433 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1]                                                                                     ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.580 ns                 ;
-; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.581 ns                 ;
-; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.581 ns                 ;
-; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                                         ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.153 ns                   ; 1.587 ns                 ;
-; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0]                                    ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.580 ns                 ;
-; 0.434 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.634 ns                 ;
-; 0.436 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21]                                                                                                   ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 0.818 ns                   ; 1.254 ns                 ;
-; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106]                                  ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.146 ns                   ; 1.582 ns                 ;
-; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.517 ns                   ; 1.953 ns                 ;
-; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117]                       ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.200 ns                   ; 1.636 ns                 ;
-; 0.436 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5]                                   ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25                                                                           ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.583 ns                 ;
-; 0.437 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.584 ns                 ;
-; 0.437 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.150 ns                   ; 1.587 ns                 ;
-; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49]                                                        ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.148 ns                   ; 1.586 ns                 ;
-; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.141 ns                   ; 1.579 ns                 ;
-; 0.438 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; CLK33M     ; CLK33M   ; 0.000 ns                   ; 1.147 ns                   ; 1.585 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;            ;          ;                            ;                            ;                          ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Hold: 'MAIN_CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-; Minimum Slack                           ; From                                                                                                                                                ; To                                                                                                                                                                       ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-; -3.786 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.716 ns                   ; 1.930 ns                 ;
-; -3.611 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.756 ns                   ; 2.145 ns                 ;
-; -3.448 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.709 ns                   ; 2.261 ns                 ;
-; -3.293 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[0]                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.327 ns                   ; 1.034 ns                 ;
-; -3.012 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 2.694 ns                 ;
-; -2.912 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 2.794 ns                 ;
-; -2.048 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.740 ns                   ; 1.692 ns                 ;
-; -1.996 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.143 ns                   ; 1.147 ns                 ;
-; -1.985 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.371 ns                 ;
-; -1.961 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.104 ns                   ; 1.143 ns                 ;
-; -1.958 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.142 ns                   ; 1.184 ns                 ;
-; -1.934 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.422 ns                 ;
-; -1.923 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.433 ns                 ;
-; -1.867 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.143 ns                   ; 1.276 ns                 ;
-; -1.842 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.356 ns                   ; 1.514 ns                 ;
-; -1.835 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.390 ns                   ; 1.555 ns                 ;
-; -1.795 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.392 ns                   ; 1.597 ns                 ;
-; -1.749 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.390 ns                   ; 1.641 ns                 ;
-; -1.745 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.392 ns                   ; 1.647 ns                 ;
-; -1.641 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.348 ns                   ; 1.707 ns                 ;
-; -1.595 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.204 ns                   ; 1.609 ns                 ;
-; -1.569 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.142 ns                   ; 1.573 ns                 ;
-; -1.508 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.111 ns                   ; 1.603 ns                 ;
-; -1.350 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe31                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.398 ns                   ; 2.048 ns                 ;
-; -1.326 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.623 ns                   ; 2.297 ns                 ;
-; -1.242 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.145 ns                   ; 1.903 ns                 ;
-; -1.234 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.973 ns                   ; 0.739 ns                 ;
-; -1.159 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 1.922 ns                 ;
-; -1.152 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe35                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 1.989 ns                 ;
-; -1.113 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.740 ns                   ; 2.627 ns                 ;
-; -1.095 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 2.046 ns                 ;
-; -1.072 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe19                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.362 ns                   ; 2.290 ns                 ;
-; -1.055 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.141 ns                   ; 2.086 ns                 ;
-; -1.001 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.966 ns                   ; 0.965 ns                 ;
-; -0.993 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 1.310 ns                 ;
-; -0.961 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 2.120 ns                 ;
-; -0.918 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]                                                                          ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.364 ns                   ; 2.446 ns                 ;
-; -0.893 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.350 ns                   ; 1.457 ns                 ;
-; -0.849 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.714 ns                 ;
-; -0.825 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.091 ns                   ; 2.266 ns                 ;
-; -0.819 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe5                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.080 ns                   ; 2.261 ns                 ;
-; -0.770 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe3                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.080 ns                   ; 2.310 ns                 ;
-; -0.743 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.179 ns                   ; 1.436 ns                 ;
-; -0.742 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.179 ns                   ; 1.437 ns                 ;
-; -0.692 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.089 ns                   ; 2.397 ns                 ;
-; -0.675 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.521 ns                   ; 2.846 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                    ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0]                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                         ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0]                                                                                      ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                  ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.672 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                         ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 0.460 ns                 ;
-; -0.668 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 2.975 ns                 ;
-; -0.658 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.905 ns                 ;
-; -0.655 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 1.908 ns                 ;
-; -0.591 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.081 ns                   ; 2.490 ns                 ;
-; -0.569 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.731 ns                 ;
-; -0.553 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.296 ns                   ; 1.743 ns                 ;
-; -0.530 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 2.033 ns                 ;
-; -0.447 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.350 ns                   ; 1.903 ns                 ;
-; -0.441 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.090 ns                   ; 1.649 ns                 ;
-; -0.422 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.878 ns                 ;
-; -0.420 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.880 ns                 ;
-; -0.407 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe7                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.091 ns                   ; 2.684 ns                 ;
-; -0.353 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.563 ns                   ; 2.210 ns                 ;
-; -0.320 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.980 ns                 ;
-; -0.319 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.300 ns                   ; 1.981 ns                 ;
-; -0.198 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.328 ns                 ;
-; -0.184 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.709 ns                   ; 5.525 ns                 ;
-; -0.155 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.216 ns                   ; 3.061 ns                 ;
-; -0.143 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 3.990 ns                 ;
-; -0.133 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.718 ns                   ; 5.585 ns                 ;
-; -0.126 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.007 ns                 ;
-; -0.126 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.685 ns                   ; 5.559 ns                 ;
-; -0.125 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.004 ns                 ;
-; -0.116 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.017 ns                 ;
-; -0.097 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 5.593 ns                 ;
-; -0.097 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.314 ns                 ;
-; -0.092 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.037 ns                 ;
-; -0.070 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.885 ns                   ; 3.815 ns                 ;
-; -0.067 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.214 ns                   ; 3.147 ns                 ;
-; -0.065 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 3.784 ns                 ;
-; -0.060 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.917 ns                   ; 3.857 ns                 ;
-; -0.059 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                           ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe21                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.363 ns                   ; 3.304 ns                 ;
-; -0.046 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.311 ns                   ; 4.265 ns                 ;
-; -0.025 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 5.665 ns                 ;
-; -0.022 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.389 ns                 ;
-; -0.006 ns                               ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.036 ns                   ; 2.030 ns                 ;
-; 0.007 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI                                                                          ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI                                                                                             ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.760 ns                   ; 3.767 ns                 ;
-; 0.026 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.689 ns                   ; 5.715 ns                 ;
-; 0.067 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.593 ns                 ;
-; 0.072 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.526 ns                   ; 3.598 ns                 ;
-; 0.091 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.637 ns                   ; 3.728 ns                 ;
-; 0.093 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.885 ns                   ; 3.978 ns                 ;
-; 0.093 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.961 ns                   ; 1.054 ns                 ;
-; 0.097 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.036 ns                   ; 2.133 ns                 ;
-; 0.104 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.718 ns                   ; 5.822 ns                 ;
-; 0.118 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 3.761 ns                 ;
-; 0.119 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.422 ns                 ;
-; 0.119 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.422 ns                 ;
-; 0.121 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.598 ns                   ; 4.719 ns                 ;
-; 0.123 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 3.972 ns                 ;
-; 0.132 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.083 ns                   ; 2.215 ns                 ;
-; 0.150 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.815 ns                   ; 3.965 ns                 ;
-; 0.151 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.129 ns                   ; 4.280 ns                 ;
-; 0.158 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.228 ns                   ; 1.386 ns                 ;
-; 0.167 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.470 ns                 ;
-; 0.168 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.817 ns                   ; 3.985 ns                 ;
-; 0.177 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.357 ns                   ; 2.534 ns                 ;
-; 0.181 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.689 ns                   ; 5.870 ns                 ;
-; 0.184 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.017 ns                   ; 6.201 ns                 ;
-; 0.186 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.615 ns                   ; 3.801 ns                 ;
-; 0.188 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.849 ns                   ; 4.037 ns                 ;
-; 0.191 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.323 ns                 ;
-; 0.192 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.324 ns                 ;
-; 0.195 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.693 ns                 ;
-; 0.216 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]                                                                     ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.685 ns                   ; 3.901 ns                 ;
-; 0.226 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.598 ns                   ; 4.824 ns                 ;
-; 0.231 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2]                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.707 ns                   ; 5.938 ns                 ;
-; 0.235 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.013 ns                   ; 6.248 ns                 ;
-; 0.243 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.459 ns                   ; 3.702 ns                 ;
-; 0.261 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.916 ns                   ; 2.177 ns                 ;
-; 0.262 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.916 ns                   ; 2.178 ns                 ;
-; 0.265 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.132 ns                   ; 4.397 ns                 ;
-; 0.266 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ZL                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.707 ns                   ; 5.973 ns                 ;
-; 0.291 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.917 ns                   ; 4.208 ns                 ;
-; 0.311 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.722 ns                 ;
-; 0.313 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.443 ns                 ;
-; 0.314 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]                                                             ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.133 ns                   ; 4.447 ns                 ;
-; 0.315 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.813 ns                 ;
-; 0.315 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.033 ns                   ; 2.348 ns                 ;
-; 0.318 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                            ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI                                                                      ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.621 ns                   ; 2.939 ns                 ;
-; 0.320 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.450 ns                 ;
-; 0.320 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.450 ns                 ;
-; 0.323 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0]                                                                         ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.453 ns                 ;
-; 0.324 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.768 ns                   ; 6.092 ns                 ;
-; 0.333 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1]                                    ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.126 ns                   ; 1.459 ns                 ;
-; 0.338 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.165 ns                   ; 1.503 ns                 ;
-; 0.339 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.178 ns                   ; 1.517 ns                 ;
-; 0.341 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19]                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.471 ns                 ;
-; 0.341 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE                                                                                              ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.153 ns                   ; 1.494 ns                 ;
-; 0.342 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5]                              ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23]                                                                                                   ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.801 ns                   ; 1.143 ns                 ;
-; 0.342 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.476 ns                 ;
-; 0.343 ns                                ; Video:Fredi_Aschwanden|inst95                                                                                                                       ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9]                                                                                     ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.135 ns                   ; 1.478 ns                 ;
-; 0.344 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.637 ns                   ; 3.981 ns                 ;
-; 0.346 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11]                        ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11]                                                       ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.788 ns                   ; 1.134 ns                 ;
-; 0.347 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.643 ns                   ; 3.990 ns                 ;
-; 0.349 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.165 ns                   ; 1.514 ns                 ;
-; 0.350 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 2.303 ns                   ; 2.653 ns                 ;
-; 0.352 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12]                                                               ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13]                                                                                    ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.486 ns                 ;
-; 0.354 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]                                                                      ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 6.067 ns                   ; 6.421 ns                 ;
-; 0.355 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.123 ns                   ; 1.478 ns                 ;
-; 0.355 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.498 ns                   ; 3.853 ns                 ;
-; 0.358 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]             ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                                          ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.147 ns                   ; 1.505 ns                 ;
-; 0.360 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.130 ns                   ; 1.490 ns                 ;
-; 0.360 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.411 ns                   ; 3.771 ns                 ;
-; 0.361 ns                                ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29                                                      ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.493 ns                 ;
-; 0.362 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.502 ns                   ; 1.864 ns                 ;
-; 0.365 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.137 ns                   ; 1.502 ns                 ;
-; 0.365 ns                                ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3]                            ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13]                                                                                                   ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.802 ns                   ; 1.167 ns                 ;
-; 0.365 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.129 ns                   ; 1.494 ns                 ;
-; 0.366 ns                                ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93]                        ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.185 ns                   ; 1.551 ns                 ;
-; 0.366 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.747 ns                   ; 6.113 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67]                                  ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.129 ns                   ; 1.496 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]                                                                        ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5]                                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 0.868 ns                   ; 1.235 ns                 ;
-; 0.367 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST                                                                                                  ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.746 ns                   ; 6.113 ns                 ;
-; 0.368 ns                                ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27]                                  ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11]                                                                                    ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.500 ns                 ;
-; 0.368 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 4.264 ns                   ; 4.632 ns                 ;
-; 0.370 ns                                ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49                                                       ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23]                                                         ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.134 ns                   ; 1.504 ns                 ;
-; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.124 ns                   ; 1.495 ns                 ;
-; 0.371 ns                                ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10]                                                                               ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.127 ns                   ; 1.498 ns                 ;
-; 0.372 ns                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3]                                                                ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4]                                                                                     ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.504 ns                 ;
-; 0.373 ns                                ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.502 ns                   ; 1.875 ns                 ;
-; 0.374 ns                                ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2]                                                   ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.133 ns                   ; 1.507 ns                 ;
-; 0.374 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_START                                                                                           ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.706 ns                   ; 6.080 ns                 ;
-; 0.374 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                           ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.147 ns                   ; 1.521 ns                 ;
-; 0.376 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]                                                                      ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF                                                                                               ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 5.690 ns                   ; 6.066 ns                 ;
-; 0.379 ns                                ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15]                                                                              ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32                                                                            ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.132 ns                   ; 1.511 ns                 ;
-; 0.381 ns                                ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                       ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON                                                                                                ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 3.460 ns                   ; 3.841 ns                 ;
-; 0.382 ns                                ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18]                                   ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50]                                                        ; MAIN_CLK   ; MAIN_CLK ; 0.000 ns                   ; 1.135 ns                   ; 1.517 ns                 ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu)                                                                                                 ;                                                                                                                                                                          ;            ;          ;                            ;                            ;                          ;
-+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; tsu                                                                                                                                                                                                                                                                                           ;
-+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
-; Slack                                   ; Required tsu                                        ; Actual tsu ; From      ; To                                                                                                                                                        ; To Clock ;
-+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
-; -4.528 ns                               ; 1.000 ns                                            ; 5.528 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state                                                     ; MAIN_CLK ;
-; -4.169 ns                               ; 1.000 ns                                            ; 5.169 ns   ; VD[19]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]                                                                        ; MAIN_CLK ;
-; -4.134 ns                               ; 1.000 ns                                            ; 5.134 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -4.083 ns                               ; 1.000 ns                                            ; 5.083 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
-; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
-; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
-; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
-; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
-; -4.051 ns                               ; 1.000 ns                                            ; 5.051 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
-; -4.047 ns                               ; 1.000 ns                                            ; 5.047 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
-; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
-; -4.022 ns                               ; 1.000 ns                                            ; 5.022 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
-; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
-; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
-; -3.961 ns                               ; 1.000 ns                                            ; 4.961 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
-; -3.956 ns                               ; 1.000 ns                                            ; 4.956 ns   ; VD[27]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]                                                                        ; MAIN_CLK ;
-; -3.930 ns                               ; 1.000 ns                                            ; 4.930 ns   ; nINDEX    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                        ; CLK33M   ;
-; -3.930 ns                               ; 1.000 ns                                            ; 4.930 ns   ; VD[31]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]                                                                        ; MAIN_CLK ;
-; -3.927 ns                               ; 1.000 ns                                            ; 4.927 ns   ; VD[1]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]                                                                         ; MAIN_CLK ;
-; -3.927 ns                               ; 1.000 ns                                            ; 4.927 ns   ; VD[9]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]                                                                         ; MAIN_CLK ;
-; -3.913 ns                               ; 1.000 ns                                            ; 4.913 ns   ; VD[2]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]                                                                         ; MAIN_CLK ;
-; -3.912 ns                               ; 1.000 ns                                            ; 4.912 ns   ; VD[12]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]                                                                        ; MAIN_CLK ;
-; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
-; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
-; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
-; -3.907 ns                               ; 1.000 ns                                            ; 4.907 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
-; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
-; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
-; -3.903 ns                               ; 1.000 ns                                            ; 4.903 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
-; -3.897 ns                               ; 1.000 ns                                            ; 4.897 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
-; -3.885 ns                               ; 1.000 ns                                            ; 4.885 ns   ; VD[20]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]                                                                        ; MAIN_CLK ;
-; -3.883 ns                               ; 1.000 ns                                            ; 4.883 ns   ; VD[25]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]                                                                        ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
-; -3.869 ns                               ; 1.000 ns                                            ; 4.869 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.860 ns                               ; 1.000 ns                                            ; 4.860 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.859 ns                               ; 1.000 ns                                            ; 4.859 ns   ; VD[28]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]                                                                        ; MAIN_CLK ;
-; -3.855 ns                               ; 1.000 ns                                            ; 4.855 ns   ; VD[22]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]                                                                        ; MAIN_CLK ;
-; -3.851 ns                               ; 1.000 ns                                            ; 4.851 ns   ; VD[17]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]                                                                        ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.850 ns                               ; 1.000 ns                                            ; 4.850 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
-; -3.846 ns                               ; 1.000 ns                                            ; 4.846 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
-; -3.827 ns                               ; 1.000 ns                                            ; 4.827 ns   ; VD[11]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]                                                                        ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
-; -3.814 ns                               ; 1.000 ns                                            ; 4.814 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
-; -3.804 ns                               ; 1.000 ns                                            ; 4.804 ns   ; VD[0]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]                                                                         ; MAIN_CLK ;
-; -3.801 ns                               ; 1.000 ns                                            ; 4.801 ns   ; VD[10]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]                                                                        ; MAIN_CLK ;
-; -3.796 ns                               ; 1.000 ns                                            ; 4.796 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state                                            ; MAIN_CLK ;
-; -3.794 ns                               ; 1.000 ns                                            ; 4.794 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1                                            ; MAIN_CLK ;
-; -3.794 ns                               ; 1.000 ns                                            ; 4.794 ns   ; MAIN_CLK  ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state                                            ; MAIN_CLK ;
-; -3.783 ns                               ; 1.000 ns                                            ; 4.783 ns   ; VD[14]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]                                                                        ; MAIN_CLK ;
-; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
-; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.768 ns                               ; 1.000 ns                                            ; 4.768 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.765 ns                               ; 1.000 ns                                            ; 4.765 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO                                        ; CLK33M   ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]                                                                                    ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]                                                                                    ; MAIN_CLK ;
-; -3.761 ns                               ; 1.000 ns                                            ; 4.761 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]                                                                                    ; MAIN_CLK ;
-; -3.752 ns                               ; 1.000 ns                                            ; 4.752 ns   ; VD[6]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]                                                                         ; MAIN_CLK ;
-; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
-; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]                                                                                    ; MAIN_CLK ;
-; -3.748 ns                               ; 1.000 ns                                            ; 4.748 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]                                                                                    ; MAIN_CLK ;
-; -3.744 ns                               ; 1.000 ns                                            ; 4.744 ns   ; VD[21]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]                                                                        ; MAIN_CLK ;
-; -3.742 ns                               ; 1.000 ns                                            ; 4.742 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.740 ns                               ; 1.000 ns                                            ; 4.740 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
-; -3.740 ns                               ; 1.000 ns                                            ; 4.740 ns   ; VD[16]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]                                                                        ; MAIN_CLK ;
-; -3.739 ns                               ; 1.000 ns                                            ; 4.739 ns   ; VD[29]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]                                                                        ; MAIN_CLK ;
-; -3.735 ns                               ; 1.000 ns                                            ; 4.735 ns   ; VD[15]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]                                                                        ; MAIN_CLK ;
-; -3.708 ns                               ; 1.000 ns                                            ; 4.708 ns   ; VD[26]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]                                                                        ; MAIN_CLK ;
-; -3.707 ns                               ; 1.000 ns                                            ; 4.707 ns   ; VD[13]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]                                                                        ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
-; -3.706 ns                               ; 1.000 ns                                            ; 4.706 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
-; -3.703 ns                               ; 1.000 ns                                            ; 4.703 ns   ; VD[3]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]                                                                         ; MAIN_CLK ;
-; -3.699 ns                               ; 1.000 ns                                            ; 4.699 ns   ; VD[30]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]                                                                        ; MAIN_CLK ;
-; -3.694 ns                               ; 1.000 ns                                            ; 4.694 ns   ; VD[24]    ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]                                                                        ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
-; -3.691 ns                               ; 1.000 ns                                            ; 4.691 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
-; -3.684 ns                               ; 1.000 ns                                            ; 4.684 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
-; -3.684 ns                               ; 1.000 ns                                            ; 4.684 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.680 ns                               ; 1.000 ns                                            ; 4.680 ns   ; FB_AD[30] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25]                                                                                    ; MAIN_CLK ;
-; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26]                                                                                    ; MAIN_CLK ;
-; -3.654 ns                               ; 1.000 ns                                            ; 4.654 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28]                                                                                    ; MAIN_CLK ;
-; -3.634 ns                               ; 1.000 ns                                            ; 4.634 ns   ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0]                                                                                     ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]                                                                                     ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]                                                                                     ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]                                                                                    ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23]                                                                                    ; MAIN_CLK ;
-; -3.566 ns                               ; 1.000 ns                                            ; 4.566 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27]                                                                                    ; MAIN_CLK ;
-; -3.471 ns                               ; 1.000 ns                                            ; 4.471 ns   ; VD[4]     ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]                                                                         ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9]                                                                                     ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]                                                                                    ; MAIN_CLK ;
-; -3.464 ns                               ; 1.000 ns                                            ; 4.464 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]                                                                                    ; MAIN_CLK ;
-; -3.386 ns                               ; 1.000 ns                                            ; 4.386 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]                                                                                                            ; MAIN_CLK ;
-; -3.339 ns                               ; 1.000 ns                                            ; 4.339 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
-; -3.334 ns                               ; 1.000 ns                                            ; 4.334 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE                            ; CLK33M   ;
-; -3.324 ns                               ; 1.000 ns                                            ; 4.324 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.290 ns                               ; 1.000 ns                                            ; 4.290 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
-; -3.272 ns                               ; 1.000 ns                                            ; 4.272 ns   ; FB_AD[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC                                                                                                            ; MAIN_CLK ;
-; -3.248 ns                               ; 1.000 ns                                            ; 4.248 ns   ; nFB_WR    ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                                     ; CLK33M   ;
-; -3.245 ns                               ; 1.000 ns                                            ; 4.245 ns   ; FB_AD[7]  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.236 ns                               ; 1.000 ns                                            ; 4.236 ns   ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.226 ns                               ; 1.000 ns                                            ; 4.226 ns   ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.226 ns                               ; 1.000 ns                                            ; 4.226 ns   ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]                                                                                    ; MAIN_CLK ;
-; -3.218 ns                               ; 1.000 ns                                            ; 4.218 ns   ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]                                                                                    ; MAIN_CLK ;
-; -3.214 ns                               ; 1.000 ns                                            ; 4.214 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.214 ns                               ; 1.000 ns                                            ; 4.214 ns   ; FB_AD[7]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7]                                                                                     ; MAIN_CLK ;
-; -3.211 ns                               ; 1.000 ns                                            ; 4.211 ns   ; FB_SIZE0  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC                                                                                                             ; MAIN_CLK ;
-; -3.208 ns                               ; 1.000 ns                                            ; 4.208 ns   ; FB_AD[3]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -3.206 ns                               ; 1.000 ns                                            ; 4.206 ns   ; FB_AD[4]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.203 ns                               ; 1.000 ns                                            ; 4.203 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.199 ns                               ; 1.000 ns                                            ; 4.199 ns   ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
-; -3.197 ns                               ; 1.000 ns                                            ; 4.197 ns   ; FB_AD[3]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]                                                                                     ; MAIN_CLK ;
-; -3.194 ns                               ; 1.000 ns                                            ; 4.194 ns   ; FB_AD[4]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]                                                                                     ; MAIN_CLK ;
-; -3.193 ns                               ; 1.000 ns                                            ; 4.193 ns   ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -3.190 ns                               ; 1.000 ns                                            ; 4.190 ns   ; FB_AD[10] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10]                                                                                    ; MAIN_CLK ;
-; -3.187 ns                               ; 1.000 ns                                            ; 4.187 ns   ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]                                                                                    ; MAIN_CLK ;
-; -3.182 ns                               ; 1.000 ns                                            ; 4.182 ns   ; HD_DD     ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[1] ; CLK33M   ;
-; -3.181 ns                               ; 1.000 ns                                            ; 4.181 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.174 ns                               ; 1.000 ns                                            ; 4.174 ns   ; FB_AD[12] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12]                                                                                    ; MAIN_CLK ;
-; -3.173 ns                               ; 1.000 ns                                            ; 4.173 ns   ; FB_SIZE1  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]                                                                                                           ; MAIN_CLK ;
-; -3.172 ns                               ; 1.000 ns                                            ; 4.172 ns   ; FB_ALE    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ                                                                                                            ; MAIN_CLK ;
-; -3.171 ns                               ; 1.000 ns                                            ; 4.171 ns   ; FB_AD[5]  ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]                                                                                     ; MAIN_CLK ;
-; -3.167 ns                               ; 1.000 ns                                            ; 4.167 ns   ; FB_AD[6]  ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]                                                                                     ; MAIN_CLK ;
-; -3.162 ns                               ; 1.000 ns                                            ; 4.162 ns   ; FB_AD[1]  ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1]                                                                                     ; MAIN_CLK ;
-; -3.160 ns                               ; 1.000 ns                                            ; 4.160 ns   ; nFB_WR    ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]                                                                                                            ; MAIN_CLK ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;           ;                                                                                                                                                           ;          ;
-+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; tco                                                                                                                                                                                                                                                                                ;
-+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
-; Slack                                   ; Required tco                                        ; Actual tco ; From                                                                                                                                         ; To        ; From Clock ;
-+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
-; -14.840 ns                              ; 1.000 ns                                            ; 15.840 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; nIRQ[5]   ; MAIN_CLK   ;
-; -14.829 ns                              ; 1.000 ns                                            ; 15.829 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; nIRQ[5]   ; MAIN_CLK   ;
-; -13.764 ns                              ; 1.000 ns                                            ; 14.764 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; FB_AD[8]  ; MAIN_CLK   ;
-; -13.654 ns                              ; 1.000 ns                                            ; 14.654 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; FB_AD[9]  ; MAIN_CLK   ;
-; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.587 ns                              ; 1.000 ns                                            ; 14.587 ns  ; interrupt_handler:nobody|INT_LATCH[8]                                                                                                        ; FB_AD[29] ; MAIN_CLK   ;
-; -13.575 ns                              ; 1.000 ns                                            ; 14.575 ns  ; interrupt_handler:nobody|INT_LATCH[9]                                                                                                        ; FB_AD[29] ; MAIN_CLK   ;
-; -13.493 ns                              ; 1.000 ns                                            ; 14.493 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.477 ns                              ; 1.000 ns                                            ; 14.477 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.457 ns                              ; 1.000 ns                                            ; 14.457 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                   ; FB_AD[18] ; MAIN_CLK   ;
-; -13.418 ns                              ; 1.000 ns                                            ; 14.418 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.386 ns                              ; 1.000 ns                                            ; 14.386 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                    ; FB_AD[7]  ; MAIN_CLK   ;
-; -13.358 ns                              ; 1.000 ns                                            ; 14.358 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.358 ns                              ; 1.000 ns                                            ; 14.358 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.309 ns                              ; 1.000 ns                                            ; 14.309 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
-; -13.294 ns                              ; 1.000 ns                                            ; 14.294 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -13.259 ns                              ; 1.000 ns                                            ; 14.259 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.250 ns                              ; 1.000 ns                                            ; 14.250 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                      ; FB_AD[18] ; MAIN_CLK   ;
-; -13.227 ns                              ; 1.000 ns                                            ; 14.227 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.207 ns                              ; 1.000 ns                                            ; 14.207 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[18] ; MAIN_CLK   ;
-; -13.171 ns                              ; 1.000 ns                                            ; 14.171 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.170 ns                              ; 1.000 ns                                            ; 14.170 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -13.157 ns                              ; 1.000 ns                                            ; 14.157 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -13.028 ns                              ; 1.000 ns                                            ; 14.028 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -13.015 ns                              ; 1.000 ns                                            ; 14.015 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2]                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -12.999 ns                              ; 1.000 ns                                            ; 13.999 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[2]                 ; FB_AD[18] ; MAIN_CLK   ;
-; -12.921 ns                              ; 1.000 ns                                            ; 13.921 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -12.886 ns                              ; 1.000 ns                                            ; 13.886 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -12.876 ns                              ; 1.000 ns                                            ; 13.876 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -12.861 ns                              ; 1.000 ns                                            ; 13.861 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -12.846 ns                              ; 1.000 ns                                            ; 13.846 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
-; -12.836 ns                              ; 1.000 ns                                            ; 13.836 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
-; -12.823 ns                              ; 1.000 ns                                            ; 13.823 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[2]                 ; FB_AD[18] ; MAIN_CLK   ;
-; -12.817 ns                              ; 1.000 ns                                            ; 13.817 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0]                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -12.784 ns                              ; 1.000 ns                                            ; 13.784 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
-; -12.732 ns                              ; 1.000 ns                                            ; 13.732 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.620 ns                              ; 1.000 ns                                            ; 13.620 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -12.567 ns                              ; 1.000 ns                                            ; 13.567 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3]                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -12.434 ns                              ; 1.000 ns                                            ; 13.434 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.425 ns                              ; 1.000 ns                                            ; 13.425 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.404 ns                              ; 1.000 ns                                            ; 13.404 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                     ; FB_AD[8]  ; MAIN_CLK   ;
-; -12.403 ns                              ; 1.000 ns                                            ; 13.403 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.361 ns                              ; 1.000 ns                                            ; 13.361 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -12.361 ns                              ; 1.000 ns                                            ; 13.361 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -12.302 ns                              ; 1.000 ns                                            ; 13.302 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]                     ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.301 ns                              ; 1.000 ns                                            ; 13.301 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -12.300 ns                              ; 1.000 ns                                            ; 13.300 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[2]                 ; FB_AD[18] ; MAIN_CLK   ;
-; -12.286 ns                              ; 1.000 ns                                            ; 13.286 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
-; -12.285 ns                              ; 1.000 ns                                            ; 13.285 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]                     ; FB_AD[18] ; MAIN_CLK   ;
-; -12.283 ns                              ; 1.000 ns                                            ; 13.283 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ                        ; FB_AD[7]  ; CLK33M     ;
-; -12.260 ns                              ; 1.000 ns                                            ; 13.260 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.241 ns                              ; 1.000 ns                                            ; 13.241 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.219 ns                              ; 1.000 ns                                            ; 13.219 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2]                      ; FB_AD[18] ; MAIN_CLK   ;
-; -12.211 ns                              ; 1.000 ns                                            ; 13.211 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -12.205 ns                              ; 1.000 ns                                            ; 13.205 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
-; -12.200 ns                              ; 1.000 ns                                            ; 13.200 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                               ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.186 ns                              ; 1.000 ns                                            ; 13.186 ns  ; interrupt_handler:nobody|WERTE[2][0]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -12.182 ns                              ; 1.000 ns                                            ; 13.182 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                   ; FB_AD[22] ; MAIN_CLK   ;
-; -12.177 ns                              ; 1.000 ns                                            ; 13.177 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -12.175 ns                              ; 1.000 ns                                            ; 13.175 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[2]                 ; FB_AD[18] ; MAIN_CLK   ;
-; -12.173 ns                              ; 1.000 ns                                            ; 13.173 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -12.166 ns                              ; 1.000 ns                                            ; 13.166 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
-; -12.158 ns                              ; 1.000 ns                                            ; 13.158 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -12.157 ns                              ; 1.000 ns                                            ; 13.157 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -12.082 ns                              ; 1.000 ns                                            ; 13.082 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2]                      ; FB_AD[18] ; MAIN_CLK   ;
-; -12.055 ns                              ; 1.000 ns                                            ; 13.055 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                   ; FB_AD[21] ; MAIN_CLK   ;
-; -12.052 ns                              ; 1.000 ns                                            ; 13.052 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
-; -12.039 ns                              ; 1.000 ns                                            ; 13.039 ns  ; interrupt_handler:nobody|ACP_CONF[28]                                                                                                        ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.038 ns                              ; 1.000 ns                                            ; 13.038 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -12.022 ns                              ; 1.000 ns                                            ; 13.022 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -12.008 ns                              ; 1.000 ns                                            ; 13.008 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QB     ; MAIN_CLK   ;
-; -12.005 ns                              ; 1.000 ns                                            ; 13.005 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_DOUT[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -12.004 ns                              ; 1.000 ns                                            ; 13.004 ns  ; interrupt_handler:nobody|WERTE[2][62]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.984 ns                              ; 1.000 ns                                            ; 12.984 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[27] ; MAIN_CLK   ;
-; -11.978 ns                              ; 1.000 ns                                            ; 12.978 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1]                                           ; YM_QB     ; MAIN_CLK   ;
-; -11.968 ns                              ; 1.000 ns                                            ; 12.968 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -11.957 ns                              ; 1.000 ns                                            ; 12.957 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.946 ns                              ; 1.000 ns                                            ; 12.946 ns  ; interrupt_handler:nobody|WERTE[2][42]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.939 ns                              ; 1.000 ns                                            ; 12.939 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -11.938 ns                              ; 1.000 ns                                            ; 12.938 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4]                                           ; YM_QB     ; MAIN_CLK   ;
-; -11.937 ns                              ; 1.000 ns                                            ; 12.937 ns  ; interrupt_handler:nobody|WERTE[2][10]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.935 ns                              ; 1.000 ns                                            ; 12.935 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                     ; FB_AD[9]  ; MAIN_CLK   ;
-; -11.933 ns                              ; 1.000 ns                                            ; 12.933 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.924 ns                              ; 1.000 ns                                            ; 12.924 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC                                                                     ; FB_AD[26] ; MAIN_CLK   ;
-; -11.922 ns                              ; 1.000 ns                                            ; 12.922 ns  ; interrupt_handler:nobody|WERTE[2][58]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.900 ns                              ; 1.000 ns                                            ; 12.900 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -11.874 ns                              ; 1.000 ns                                            ; 12.874 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
-; -11.871 ns                              ; 1.000 ns                                            ; 12.871 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[20] ; MAIN_CLK   ;
-; -11.867 ns                              ; 1.000 ns                                            ; 12.867 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.859 ns                              ; 1.000 ns                                            ; 12.859 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.857 ns                              ; 1.000 ns                                            ; 12.857 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                      ; FB_AD[20] ; MAIN_CLK   ;
-; -11.845 ns                              ; 1.000 ns                                            ; 12.845 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[17] ; MAIN_CLK   ;
-; -11.842 ns                              ; 1.000 ns                                            ; 12.842 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                   ; FB_AD[20] ; MAIN_CLK   ;
-; -11.834 ns                              ; 1.000 ns                                            ; 12.834 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
-; -11.831 ns                              ; 1.000 ns                                            ; 12.831 ns  ; interrupt_handler:nobody|WERTE[2][4]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -11.813 ns                              ; 1.000 ns                                            ; 12.813 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                              ; FB_AD[18] ; MAIN_CLK   ;
-; -11.794 ns                              ; 1.000 ns                                            ; 12.794 ns  ; interrupt_handler:nobody|WERTE[2][43]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.787 ns                              ; 1.000 ns                                            ; 12.787 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.775 ns                              ; 1.000 ns                                            ; 12.775 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.774 ns                              ; 1.000 ns                                            ; 12.774 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -11.769 ns                              ; 1.000 ns                                            ; 12.769 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[18] ; MAIN_CLK   ;
-; -11.762 ns                              ; 1.000 ns                                            ; 12.762 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4]                                                                ; FB_AD[20] ; MAIN_CLK   ;
-; -11.751 ns                              ; 1.000 ns                                            ; 12.751 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5]                                           ; YM_QC     ; MAIN_CLK   ;
-; -11.747 ns                              ; 1.000 ns                                            ; 12.747 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.746 ns                              ; 1.000 ns                                            ; 12.746 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -11.736 ns                              ; 1.000 ns                                            ; 12.736 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.727 ns                              ; 1.000 ns                                            ; 12.727 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.725 ns                              ; 1.000 ns                                            ; 12.725 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.VECTOR_OUT ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.724 ns                              ; 1.000 ns                                            ; 12.724 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2]                                           ; YM_QC     ; MAIN_CLK   ;
-; -11.721 ns                              ; 1.000 ns                                            ; 12.721 ns  ; interrupt_handler:nobody|WERTE[5][8]                                                                                                         ; FB_AD[21] ; MAIN_CLK   ;
-; -11.717 ns                              ; 1.000 ns                                            ; 12.717 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.710 ns                              ; 1.000 ns                                            ; 12.710 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7]                 ; FB_AD[9]  ; MAIN_CLK   ;
-; -11.709 ns                              ; 1.000 ns                                            ; 12.709 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.708 ns                              ; 1.000 ns                                            ; 12.708 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB[5]              ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.700 ns                              ; 1.000 ns                                            ; 12.700 ns  ; interrupt_handler:nobody|WERTE[2][2]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -11.694 ns                              ; 1.000 ns                                            ; 12.694 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC                                                                     ; FB_AD[28] ; MAIN_CLK   ;
-; -11.693 ns                              ; 1.000 ns                                            ; 12.693 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                   ; FB_AD[9]  ; MAIN_CLK   ;
-; -11.692 ns                              ; 1.000 ns                                            ; 12.692 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
-; -11.680 ns                              ; 1.000 ns                                            ; 12.680 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
-; -11.675 ns                              ; 1.000 ns                                            ; 12.675 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.673 ns                              ; 1.000 ns                                            ; 12.673 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[5]                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.659 ns                              ; 1.000 ns                                            ; 12.659 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.649 ns                              ; 1.000 ns                                            ; 12.649 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.648 ns                              ; 1.000 ns                                            ; 12.648 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[25] ; MAIN_CLK   ;
-; -11.646 ns                              ; 1.000 ns                                            ; 12.646 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
-; -11.640 ns                              ; 1.000 ns                                            ; 12.640 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.633 ns                              ; 1.000 ns                                            ; 12.633 ns  ; interrupt_handler:nobody|WERTE[2][38]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.631 ns                              ; 1.000 ns                                            ; 12.631 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[19] ; MAIN_CLK   ;
-; -11.628 ns                              ; 1.000 ns                                            ; 12.628 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                ; FB_AD[17] ; MAIN_CLK   ;
-; -11.628 ns                              ; 1.000 ns                                            ; 12.628 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -11.627 ns                              ; 1.000 ns                                            ; 12.627 ns  ; interrupt_handler:nobody|WERTE[2][63]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.620 ns                              ; 1.000 ns                                            ; 12.620 ns  ; interrupt_handler:nobody|WERTE[2][61]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.620 ns                              ; 1.000 ns                                            ; 12.620 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.619 ns                              ; 1.000 ns                                            ; 12.619 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]                   ; YM_QB     ; MAIN_CLK   ;
-; -11.618 ns                              ; 1.000 ns                                            ; 12.618 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.616 ns                              ; 1.000 ns                                            ; 12.616 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
-; -11.616 ns                              ; 1.000 ns                                            ; 12.616 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                ; FB_AD[25] ; MAIN_CLK   ;
-; -11.608 ns                              ; 1.000 ns                                            ; 12.608 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[19] ; MAIN_CLK   ;
-; -11.607 ns                              ; 1.000 ns                                            ; 12.607 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[21] ; MAIN_CLK   ;
-; -11.595 ns                              ; 1.000 ns                                            ; 12.595 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
-; -11.592 ns                              ; 1.000 ns                                            ; 12.592 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19]                                                              ; FB_AD[20] ; MAIN_CLK   ;
-; -11.592 ns                              ; 1.000 ns                                            ; 12.592 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
-; -11.589 ns                              ; 1.000 ns                                            ; 12.589 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3]                                           ; YM_QA     ; MAIN_CLK   ;
-; -11.588 ns                              ; 1.000 ns                                            ; 12.588 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.588 ns                              ; 1.000 ns                                            ; 12.588 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.583 ns                              ; 1.000 ns                                            ; 12.583 ns  ; interrupt_handler:nobody|WERTE[2][57]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.582 ns                              ; 1.000 ns                                            ; 12.582 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
-; -11.579 ns                              ; 1.000 ns                                            ; 12.579 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QA     ; MAIN_CLK   ;
-; -11.578 ns                              ; 1.000 ns                                            ; 12.578 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
-; -11.576 ns                              ; 1.000 ns                                            ; 12.576 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7]                 ; FB_AD[23] ; MAIN_CLK   ;
-; -11.576 ns                              ; 1.000 ns                                            ; 12.576 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
-; -11.567 ns                              ; 1.000 ns                                            ; 12.567 ns  ; interrupt_handler:nobody|RTC_ADR[1]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
-; -11.559 ns                              ; 1.000 ns                                            ; 12.559 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6]                                                                   ; FB_AD[23] ; MAIN_CLK   ;
-; -11.552 ns                              ; 1.000 ns                                            ; 12.552 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]   ; YM_QC     ; MAIN_CLK   ;
-; -11.550 ns                              ; 1.000 ns                                            ; 12.550 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -11.545 ns                              ; 1.000 ns                                            ; 12.545 ns  ; interrupt_handler:nobody|WERTE[2][31]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.544 ns                              ; 1.000 ns                                            ; 12.544 ns  ; interrupt_handler:nobody|WERTE[2][6]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -11.543 ns                              ; 1.000 ns                                            ; 12.543 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.542 ns                              ; 1.000 ns                                            ; 12.542 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2]                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.541 ns                              ; 1.000 ns                                            ; 12.541 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS                                                                                                ; FB_AD[23] ; MAIN_CLK   ;
-; -11.540 ns                              ; 1.000 ns                                            ; 12.540 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[4]                 ; FB_AD[20] ; MAIN_CLK   ;
-; -11.540 ns                              ; 1.000 ns                                            ; 12.540 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
-; -11.537 ns                              ; 1.000 ns                                            ; 12.537 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                    ; FB_AD[3]  ; MAIN_CLK   ;
-; -11.531 ns                              ; 1.000 ns                                            ; 12.531 ns  ; interrupt_handler:nobody|WERTE[2][45]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.527 ns                              ; 1.000 ns                                            ; 12.527 ns  ; interrupt_handler:nobody|WERTE[2][7]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -11.527 ns                              ; 1.000 ns                                            ; 12.527 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                ; FB_AD[25] ; MAIN_CLK   ;
-; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                ; FB_AD[20] ; MAIN_CLK   ;
-; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; interrupt_handler:nobody|RTC_ADR[3]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.526 ns                              ; 1.000 ns                                            ; 12.526 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.508 ns                              ; 1.000 ns                                            ; 12.508 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3]                   ; FB_AD[27] ; MAIN_CLK   ;
-; -11.507 ns                              ; 1.000 ns                                            ; 12.507 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7]                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.505 ns                              ; 1.000 ns                                            ; 12.505 ns  ; interrupt_handler:nobody|RTC_ADR[2]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.504 ns                              ; 1.000 ns                                            ; 12.504 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                              ; FB_AD[27] ; MAIN_CLK   ;
-; -11.502 ns                              ; 1.000 ns                                            ; 12.502 ns  ; interrupt_handler:nobody|WERTE[2][60]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.502 ns                              ; 1.000 ns                                            ; 12.502 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                               ; FB_AD[26] ; MAIN_CLK   ;
-; -11.495 ns                              ; 1.000 ns                                            ; 12.495 ns  ; interrupt_handler:nobody|WERTE[2][53]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.492 ns                              ; 1.000 ns                                            ; 12.492 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8]                                                                                                ; FB_AD[18] ; MAIN_CLK   ;
-; -11.488 ns                              ; 1.000 ns                                            ; 12.488 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                               ; FB_AD[3]  ; MAIN_CLK   ;
-; -11.487 ns                              ; 1.000 ns                                            ; 12.487 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.480 ns                              ; 1.000 ns                                            ; 12.480 ns  ; interrupt_handler:nobody|RTC_ADR[5]                                                                                                          ; FB_AD[23] ; MAIN_CLK   ;
-; -11.480 ns                              ; 1.000 ns                                            ; 12.480 ns  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                ; FB_AD[21] ; MAIN_CLK   ;
-; -11.479 ns                              ; 1.000 ns                                            ; 12.479 ns  ; interrupt_handler:nobody|WERTE[2][36]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.478 ns                              ; 1.000 ns                                            ; 12.478 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[2]                   ; YM_QB     ; MAIN_CLK   ;
-; -11.470 ns                              ; 1.000 ns                                            ; 12.470 ns  ; interrupt_handler:nobody|WERTE[2][15]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.461 ns                              ; 1.000 ns                                            ; 12.461 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -11.460 ns                              ; 1.000 ns                                            ; 12.460 ns  ; interrupt_handler:nobody|WERTE[2][8]                                                                                                         ; FB_AD[18] ; MAIN_CLK   ;
-; -11.459 ns                              ; 1.000 ns                                            ; 12.459 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12]                                                                                               ; FB_AD[27] ; MAIN_CLK   ;
-; -11.455 ns                              ; 1.000 ns                                            ; 12.455 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0]                                           ; YM_QA     ; MAIN_CLK   ;
-; -11.455 ns                              ; 1.000 ns                                            ; 12.455 ns  ; interrupt_handler:nobody|RTC_ADR[4]                                                                                                          ; FB_AD[22] ; MAIN_CLK   ;
-; -11.451 ns                              ; 1.000 ns                                            ; 12.451 ns  ; interrupt_handler:nobody|WERTE[2][50]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.447 ns                              ; 1.000 ns                                            ; 12.447 ns  ; interrupt_handler:nobody|WERTE[2][52]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; -11.444 ns                              ; 1.000 ns                                            ; 12.444 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5]                                                                                                ; FB_AD[27] ; MAIN_CLK   ;
-; -11.443 ns                              ; 1.000 ns                                            ; 12.443 ns  ; interrupt_handler:nobody|RTC_ADR[0]                                                                                                          ; FB_AD[20] ; MAIN_CLK   ;
-; -11.441 ns                              ; 1.000 ns                                            ; 12.441 ns  ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13]                                                                                               ; FB_AD[18] ; MAIN_CLK   ;
-; -11.435 ns                              ; 1.000 ns                                            ; 12.435 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3                                                                                                 ; FB_AD[18] ; MAIN_CLK   ;
-; -11.433 ns                              ; 1.000 ns                                            ; 12.433 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[4]                   ; YM_QB     ; MAIN_CLK   ;
-; -11.432 ns                              ; 1.000 ns                                            ; 12.432 ns  ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5]              ; FB_AD[7]  ; MAIN_CLK   ;
-; -11.431 ns                              ; 1.000 ns                                            ; 12.431 ns  ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1                                                                                                 ; FB_AD[20] ; MAIN_CLK   ;
-; -11.429 ns                              ; 1.000 ns                                            ; 12.429 ns  ; interrupt_handler:nobody|WERTE[2][55]                                                                                                        ; FB_AD[18] ; MAIN_CLK   ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;                                                                                                                                              ;           ;            ;
-+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------+
-; tpd                                                                                                                                    ;
-+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
-; Slack                                   ; Required P2P Time                                   ; Actual P2P Time ; From     ; To        ;
-+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
-; -11.944 ns                              ; 1.000 ns                                            ; 12.944 ns       ; nFB_CS1  ; FB_AD[18] ;
-; -11.849 ns                              ; 1.000 ns                                            ; 12.849 ns       ; FB_SIZE0 ; FB_AD[27] ;
-; -11.785 ns                              ; 1.000 ns                                            ; 12.785 ns       ; nFB_CS1  ; FB_AD[27] ;
-; -11.694 ns                              ; 1.000 ns                                            ; 12.694 ns       ; nFB_CS1  ; FB_AD[7]  ;
-; -11.672 ns                              ; 1.000 ns                                            ; 12.672 ns       ; FB_SIZE1 ; FB_AD[27] ;
-; -11.625 ns                              ; 1.000 ns                                            ; 12.625 ns       ; nFB_WR   ; FB_AD[7]  ;
-; -11.514 ns                              ; 1.000 ns                                            ; 12.514 ns       ; FB_SIZE0 ; FB_AD[18] ;
-; -11.464 ns                              ; 1.000 ns                                            ; 12.464 ns       ; IDE_INT  ; FB_AD[7]  ;
-; -11.450 ns                              ; 1.000 ns                                            ; 12.450 ns       ; SRD[11]  ; FB_AD[27] ;
-; -11.438 ns                              ; 1.000 ns                                            ; 12.438 ns       ; nFB_OE   ; FB_AD[27] ;
-; -11.420 ns                              ; 1.000 ns                                            ; 12.420 ns       ; nFB_CS2  ; FB_AD[27] ;
-; -11.399 ns                              ; 1.000 ns                                            ; 12.399 ns       ; nFB_WR   ; FB_AD[27] ;
-; -11.376 ns                              ; 1.000 ns                                            ; 12.376 ns       ; nFB_WR   ; FB_AD[18] ;
-; -11.337 ns                              ; 1.000 ns                                            ; 12.337 ns       ; FB_SIZE1 ; FB_AD[18] ;
-; -11.243 ns                              ; 1.000 ns                                            ; 12.243 ns       ; nFB_CS2  ; FB_AD[18] ;
-; -10.918 ns                              ; 1.000 ns                                            ; 11.918 ns       ; nFB_CS1  ; FB_AD[20] ;
-; -10.824 ns                              ; 1.000 ns                                            ; 11.824 ns       ; nFB_CS2  ; FB_AD[7]  ;
-; -10.814 ns                              ; 1.000 ns                                            ; 11.814 ns       ; FB_SIZE0 ; FB_AD[7]  ;
-; -10.798 ns                              ; 1.000 ns                                            ; 11.798 ns       ; nFB_OE   ; FB_AD[7]  ;
-; -10.779 ns                              ; 1.000 ns                                            ; 11.779 ns       ; CTS      ; FB_AD[18] ;
-; -10.758 ns                              ; 1.000 ns                                            ; 11.758 ns       ; FB_SIZE1 ; FB_AD[7]  ;
-; -10.658 ns                              ; 1.000 ns                                            ; 11.658 ns       ; MAIN_CLK ; FB_AD[27] ;
-; -10.631 ns                              ; 1.000 ns                                            ; 11.631 ns       ; nFB_OE   ; FB_AD[18] ;
-; -10.578 ns                              ; 1.000 ns                                            ; 11.578 ns       ; MAIN_CLK ; FB_AD[7]  ;
-; -10.573 ns                              ; 1.000 ns                                            ; 11.573 ns       ; nFB_CS2  ; FB_AD[20] ;
-; -10.561 ns                              ; 1.000 ns                                            ; 11.561 ns       ; nFB_CS1  ; FB_AD[6]  ;
-; -10.549 ns                              ; 1.000 ns                                            ; 11.549 ns       ; FB_SIZE0 ; FB_AD[20] ;
-; -10.543 ns                              ; 1.000 ns                                            ; 11.543 ns       ; nFB_CS1  ; FB_AD[9]  ;
-; -10.529 ns                              ; 1.000 ns                                            ; 11.529 ns       ; FB_SIZE0 ; FB_AD[23] ;
-; -10.521 ns                              ; 1.000 ns                                            ; 11.521 ns       ; nFB_CS1  ; FB_AD[23] ;
-; -10.471 ns                              ; 1.000 ns                                            ; 11.471 ns       ; FB_SIZE1 ; FB_AD[20] ;
-; -10.451 ns                              ; 1.000 ns                                            ; 11.451 ns       ; FB_SIZE1 ; FB_AD[23] ;
-; -10.425 ns                              ; 1.000 ns                                            ; 11.425 ns       ; nFB_WR   ; FB_AD[9]  ;
-; -10.420 ns                              ; 1.000 ns                                            ; 11.420 ns       ; nFB_CS1  ; FB_AD[17] ;
-; -10.415 ns                              ; 1.000 ns                                            ; 11.415 ns       ; nFB_CS1  ; FB_AD[25] ;
-; -10.412 ns                              ; 1.000 ns                                            ; 11.412 ns       ; nFB_CS1  ; FB_AD[21] ;
-; -10.370 ns                              ; 1.000 ns                                            ; 11.370 ns       ; nFB_OE   ; FB_AD[20] ;
-; -10.364 ns                              ; 1.000 ns                                            ; 11.364 ns       ; nFB_WR   ; FB_AD[25] ;
-; -10.362 ns                              ; 1.000 ns                                            ; 11.362 ns       ; nFB_CS1  ; FB_AD[26] ;
-; -10.361 ns                              ; 1.000 ns                                            ; 11.361 ns       ; nFB_WR   ; FB_AD[20] ;
-; -10.335 ns                              ; 1.000 ns                                            ; 11.335 ns       ; nFB_CS2  ; FB_AD[23] ;
-; -10.318 ns                              ; 1.000 ns                                            ; 11.318 ns       ; nFB_CS2  ; FB_AD[21] ;
-; -10.317 ns                              ; 1.000 ns                                            ; 11.317 ns       ; nFB_WR   ; FB_AD[22] ;
-; -10.312 ns                              ; 1.000 ns                                            ; 11.312 ns       ; nFB_CS1  ; FB_AD[22] ;
-; -10.311 ns                              ; 1.000 ns                                            ; 11.311 ns       ; nFB_WR   ; FB_AD[26] ;
-; -10.291 ns                              ; 1.000 ns                                            ; 11.291 ns       ; nFB_WR   ; FB_AD[23] ;
-; -10.278 ns                              ; 1.000 ns                                            ; 11.278 ns       ; FB_SIZE0 ; FB_AD[17] ;
-; -10.277 ns                              ; 1.000 ns                                            ; 11.277 ns       ; MAIN_CLK ; FB_AD[18] ;
-; -10.221 ns                              ; 1.000 ns                                            ; 11.221 ns       ; FB_SIZE0 ; FB_AD[29] ;
-; -10.220 ns                              ; 1.000 ns                                            ; 11.220 ns       ; nFB_CS2  ; FB_AD[22] ;
-; -10.178 ns                              ; 1.000 ns                                            ; 11.178 ns       ; FB_SIZE0 ; FB_AD[19] ;
-; -10.146 ns                              ; 1.000 ns                                            ; 11.146 ns       ; FB_SIZE0 ; FB_AD[31] ;
-; -10.136 ns                              ; 1.000 ns                                            ; 11.136 ns       ; nFB_CS1  ; FB_AD[24] ;
-; -10.123 ns                              ; 1.000 ns                                            ; 11.123 ns       ; nFB_CS1  ; FB_AD[19] ;
-; -10.101 ns                              ; 1.000 ns                                            ; 11.101 ns       ; FB_SIZE1 ; FB_AD[17] ;
-; -10.085 ns                              ; 1.000 ns                                            ; 11.085 ns       ; nFB_WR   ; FB_AD[24] ;
-; -10.081 ns                              ; 1.000 ns                                            ; 11.081 ns       ; nFB_CS1  ; FB_AD[16] ;
-; -10.077 ns                              ; 1.000 ns                                            ; 11.077 ns       ; nFB_CS2  ; FB_AD[19] ;
-; -10.077 ns                              ; 1.000 ns                                            ; 11.077 ns       ; FB_SIZE0 ; FB_AD[21] ;
-; -10.076 ns                              ; 1.000 ns                                            ; 11.076 ns       ; FB_SIZE1 ; FB_AD[19] ;
-; -10.074 ns                              ; 1.000 ns                                            ; 11.074 ns       ; SRD[9]   ; FB_AD[25] ;
-; -10.070 ns                              ; 1.000 ns                                            ; 11.070 ns       ; nFB_CS1  ; FB_AD[29] ;
-; -10.061 ns                              ; 1.000 ns                                            ; 11.061 ns       ; nFB_OE   ; FB_AD[21] ;
-; -10.060 ns                              ; 1.000 ns                                            ; 11.060 ns       ; nFB_WR   ; FB_AD[21] ;
-; -10.051 ns                              ; 1.000 ns                                            ; 11.051 ns       ; nFB_WR   ; FB_AD[19] ;
-; -10.044 ns                              ; 1.000 ns                                            ; 11.044 ns       ; FB_SIZE1 ; FB_AD[29] ;
-; -10.041 ns                              ; 1.000 ns                                            ; 11.041 ns       ; FB_SIZE0 ; FB_AD[30] ;
-; -10.021 ns                              ; 1.000 ns                                            ; 11.021 ns       ; FB_SIZE1 ; FB_AD[21] ;
-; -10.019 ns                              ; 1.000 ns                                            ; 11.019 ns       ; nFB_WR   ; FB_AD[29] ;
-; -10.004 ns                              ; 1.000 ns                                            ; 11.004 ns       ; nFB_WR   ; FB_AD[6]  ;
-; -9.969 ns                               ; 1.000 ns                                            ; 10.969 ns       ; FB_SIZE1 ; FB_AD[31] ;
-; -9.951 ns                               ; 1.000 ns                                            ; 10.951 ns       ; FB_SIZE0 ; FB_AD[22] ;
-; -9.938 ns                               ; 1.000 ns                                            ; 10.938 ns       ; nFB_CS2  ; FB_AD[26] ;
-; -9.918 ns                               ; 1.000 ns                                            ; 10.918 ns       ; nFB_CS1  ; FB_AD[31] ;
-; -9.914 ns                               ; 1.000 ns                                            ; 10.914 ns       ; nFB_CS2  ; FB_AD[17] ;
-; -9.903 ns                               ; 1.000 ns                                            ; 10.903 ns       ; FB_SIZE0 ; FB_AD[25] ;
-; -9.899 ns                               ; 1.000 ns                                            ; 10.899 ns       ; IDE_INT  ; FB_AD[21] ;
-; -9.876 ns                               ; 1.000 ns                                            ; 10.876 ns       ; nFB_CS2  ; FB_AD[31] ;
-; -9.864 ns                               ; 1.000 ns                                            ; 10.864 ns       ; FB_SIZE1 ; FB_AD[30] ;
-; -9.835 ns                               ; 1.000 ns                                            ; 10.835 ns       ; LP_D[3]  ; FB_AD[27] ;
-; -9.823 ns                               ; 1.000 ns                                            ; 10.823 ns       ; nFB_WR   ; FB_AD[17] ;
-; -9.820 ns                               ; 1.000 ns                                            ; 10.820 ns       ; nFB_CS2  ; FB_AD[30] ;
-; -9.813 ns                               ; 1.000 ns                                            ; 10.813 ns       ; MAIN_CLK ; FB_AD[20] ;
-; -9.802 ns                               ; 1.000 ns                                            ; 10.802 ns       ; nFB_CS2  ; FB_AD[25] ;
-; -9.801 ns                               ; 1.000 ns                                            ; 10.801 ns       ; FB_SIZE1 ; FB_AD[25] ;
-; -9.792 ns                               ; 1.000 ns                                            ; 10.792 ns       ; nFB_CS2  ; FB_AD[29] ;
-; -9.791 ns                               ; 1.000 ns                                            ; 10.791 ns       ; nFB_OE   ; FB_AD[25] ;
-; -9.778 ns                               ; 1.000 ns                                            ; 10.778 ns       ; FB_SIZE1 ; FB_AD[22] ;
-; -9.770 ns                               ; 1.000 ns                                            ; 10.770 ns       ; nFB_OE   ; FB_AD[23] ;
-; -9.763 ns                               ; 1.000 ns                                            ; 10.763 ns       ; nFB_CS1  ; FB_AD[2]  ;
-; -9.750 ns                               ; 1.000 ns                                            ; 10.750 ns       ; nFB_WR   ; FB_AD[31] ;
-; -9.729 ns                               ; 1.000 ns                                            ; 10.729 ns       ; FB_SIZE0 ; FB_AD[9]  ;
-; -9.729 ns                               ; 1.000 ns                                            ; 10.729 ns       ; nFB_CS1  ; FB_AD[30] ;
-; -9.701 ns                               ; 1.000 ns                                            ; 10.701 ns       ; MAIN_CLK ; FB_AD[21] ;
-; -9.699 ns                               ; 1.000 ns                                            ; 10.699 ns       ; FB_SIZE0 ; FB_AD[24] ;
-; -9.692 ns                               ; 1.000 ns                                            ; 10.692 ns       ; nFB_OE   ; FB_AD[22] ;
-; -9.685 ns                               ; 1.000 ns                                            ; 10.685 ns       ; nFB_OE   ; FB_AD[31] ;
-; -9.684 ns                               ; 1.000 ns                                            ; 10.684 ns       ; nFB_OE   ; FB_AD[19] ;
-; -9.671 ns                               ; 1.000 ns                                            ; 10.671 ns       ; nFB_OE   ; FB_AD[17] ;
-; -9.634 ns                               ; 1.000 ns                                            ; 10.634 ns       ; nFB_CS2  ; FB_AD[24] ;
-; -9.630 ns                               ; 1.000 ns                                            ; 10.630 ns       ; SRD[2]   ; FB_AD[18] ;
-; -9.629 ns                               ; 1.000 ns                                            ; 10.629 ns       ; nFB_WR   ; FB_AD[30] ;
-; -9.628 ns                               ; 1.000 ns                                            ; 10.628 ns       ; nFB_CS2  ; FB_AD[9]  ;
-; -9.627 ns                               ; 1.000 ns                                            ; 10.627 ns       ; FB_SIZE1 ; FB_AD[9]  ;
-; -9.600 ns                               ; 1.000 ns                                            ; 10.600 ns       ; nFB_CS1  ; FB_AD[28] ;
-; -9.597 ns                               ; 1.000 ns                                            ; 10.597 ns       ; FB_SIZE1 ; FB_AD[24] ;
-; -9.593 ns                               ; 1.000 ns                                            ; 10.593 ns       ; nFB_WR   ; FB_AD[16] ;
-; -9.574 ns                               ; 1.000 ns                                            ; 10.574 ns       ; FB_SIZE0 ; FB_AD[28] ;
-; -9.572 ns                               ; 1.000 ns                                            ; 10.572 ns       ; DCD      ; FB_AD[17] ;
-; -9.565 ns                               ; 1.000 ns                                            ; 10.565 ns       ; nFB_OE   ; FB_AD[24] ;
-; -9.559 ns                               ; 1.000 ns                                            ; 10.559 ns       ; nFB_WR   ; FB_AD[8]  ;
-; -9.554 ns                               ; 1.000 ns                                            ; 10.554 ns       ; nFB_CS1  ; FB_AD[8]  ;
-; -9.521 ns                               ; 1.000 ns                                            ; 10.521 ns       ; nFB_CS1  ; FB_AD[3]  ;
-; -9.491 ns                               ; 1.000 ns                                            ; 10.491 ns       ; nFB_WR   ; FB_AD[28] ;
-; -9.477 ns                               ; 1.000 ns                                            ; 10.477 ns       ; nFB_CS2  ; FB_AD[3]  ;
-; -9.455 ns                               ; 1.000 ns                                            ; 10.455 ns       ; FB_SIZE0 ; FB_AD[26] ;
-; -9.418 ns                               ; 1.000 ns                                            ; 10.418 ns       ; RI       ; FB_AD[22] ;
-; -9.410 ns                               ; 1.000 ns                                            ; 10.410 ns       ; nFB_CS1  ; FB_AD[5]  ;
-; -9.398 ns                               ; 1.000 ns                                            ; 10.398 ns       ; MAIN_CLK ; FB_AD[26] ;
-; -9.397 ns                               ; 1.000 ns                                            ; 10.397 ns       ; FB_SIZE1 ; FB_AD[28] ;
-; -9.394 ns                               ; 1.000 ns                                            ; 10.394 ns       ; SRD[8]   ; FB_AD[24] ;
-; -9.381 ns                               ; 1.000 ns                                            ; 10.381 ns       ; nFB_OE   ; FB_AD[26] ;
-; -9.380 ns                               ; 1.000 ns                                            ; 10.380 ns       ; nFB_CS2  ; FB_AD[11] ;
-; -9.371 ns                               ; 1.000 ns                                            ; 10.371 ns       ; FB_SIZE0 ; FB_AD[4]  ;
-; -9.370 ns                               ; 1.000 ns                                            ; 10.370 ns       ; nFB_WR   ; FB_AD[5]  ;
-; -9.355 ns                               ; 1.000 ns                                            ; 10.355 ns       ; nFB_OE   ; FB_AD[4]  ;
-; -9.344 ns                               ; 1.000 ns                                            ; 10.344 ns       ; nFB_CS2  ; FB_AD[5]  ;
-; -9.333 ns                               ; 1.000 ns                                            ; 10.333 ns       ; FB_SIZE0 ; FB_AD[16] ;
-; -9.328 ns                               ; 1.000 ns                                            ; 10.328 ns       ; FB_SIZE0 ; FB_AD[2]  ;
-; -9.315 ns                               ; 1.000 ns                                            ; 10.315 ns       ; FB_SIZE1 ; FB_AD[4]  ;
-; -9.312 ns                               ; 1.000 ns                                            ; 10.312 ns       ; FB_SIZE0 ; FB_AD[3]  ;
-; -9.312 ns                               ; 1.000 ns                                            ; 10.312 ns       ; nFB_OE   ; FB_AD[2]  ;
-; -9.309 ns                               ; 1.000 ns                                            ; 10.309 ns       ; MAIN_CLK ; FB_AD[22] ;
-; -9.305 ns                               ; 1.000 ns                                            ; 10.305 ns       ; MAIN_CLK ; FB_AD[25] ;
-; -9.296 ns                               ; 1.000 ns                                            ; 10.296 ns       ; nFB_OE   ; FB_AD[3]  ;
-; -9.278 ns                               ; 1.000 ns                                            ; 10.278 ns       ; FB_SIZE1 ; FB_AD[26] ;
-; -9.275 ns                               ; 1.000 ns                                            ; 10.275 ns       ; nFB_WR   ; FB_AD[2]  ;
-; -9.273 ns                               ; 1.000 ns                                            ; 10.273 ns       ; nFB_CS1  ; nFB_TA    ;
-; -9.272 ns                               ; 1.000 ns                                            ; 10.272 ns       ; FB_SIZE1 ; FB_AD[2]  ;
-; -9.271 ns                               ; 1.000 ns                                            ; 10.271 ns       ; nFB_CS2  ; FB_AD[16] ;
-; -9.262 ns                               ; 1.000 ns                                            ; 10.262 ns       ; nFB_OE   ; FB_AD[28] ;
-; -9.256 ns                               ; 1.000 ns                                            ; 10.256 ns       ; FB_SIZE1 ; FB_AD[3]  ;
-; -9.245 ns                               ; 1.000 ns                                            ; 10.245 ns       ; nFB_CS2  ; FB_AD[2]  ;
-; -9.231 ns                               ; 1.000 ns                                            ; 10.231 ns       ; CLK33M   ; VB[7]     ;
-; -9.210 ns                               ; 1.000 ns                                            ; 10.210 ns       ; nFB_CS2  ; FB_AD[4]  ;
-; -9.203 ns                               ; 1.000 ns                                            ; 10.203 ns       ; nFB_OE   ; FB_AD[9]  ;
-; -9.201 ns                               ; 1.000 ns                                            ; 10.201 ns       ; nFB_CS2  ; FB_AD[8]  ;
-; -9.199 ns                               ; 1.000 ns                                            ; 10.199 ns       ; MAIN_CLK ; FB_AD[31] ;
-; -9.198 ns                               ; 1.000 ns                                            ; 10.198 ns       ; CLK33M   ; VSYNC_PAD ;
-; -9.193 ns                               ; 1.000 ns                                            ; 10.193 ns       ; CLK33M   ; VR[6]     ;
-; -9.191 ns                               ; 1.000 ns                                            ; 10.191 ns       ; CLK33M   ; VG[3]     ;
-; -9.176 ns                               ; 1.000 ns                                            ; 10.176 ns       ; nFB_CS1  ; FB_AD[4]  ;
-; -9.168 ns                               ; 1.000 ns                                            ; 10.168 ns       ; LP_D[7]  ; FB_AD[31] ;
-; -9.156 ns                               ; 1.000 ns                                            ; 10.156 ns       ; FB_SIZE1 ; FB_AD[16] ;
-; -9.145 ns                               ; 1.000 ns                                            ; 10.145 ns       ; MAIN_CLK ; FB_AD[23] ;
-; -9.145 ns                               ; 1.000 ns                                            ; 10.145 ns       ; nFB_CS2  ; FB_AD[28] ;
-; -9.112 ns                               ; 1.000 ns                                            ; 10.112 ns       ; nFB_WR   ; FB_AD[3]  ;
-; -9.099 ns                               ; 1.000 ns                                            ; 10.099 ns       ; MAIN_CLK ; FB_AD[19] ;
-; -9.089 ns                               ; 1.000 ns                                            ; 10.089 ns       ; nFB_OE   ; FB_AD[5]  ;
-; -9.088 ns                               ; 1.000 ns                                            ; 10.088 ns       ; SRD[5]   ; FB_AD[21] ;
-; -9.081 ns                               ; 1.000 ns                                            ; 10.081 ns       ; nFB_OE   ; FB_AD[16] ;
-; -9.079 ns                               ; 1.000 ns                                            ; 10.079 ns       ; MAIN_CLK ; FB_AD[24] ;
-; -9.047 ns                               ; 1.000 ns                                            ; 10.047 ns       ; nFB_CS2  ; FB_AD[10] ;
-; -9.019 ns                               ; 1.000 ns                                            ; 10.019 ns       ; nFB_CS2  ; FB_AD[13] ;
-; -9.004 ns                               ; 1.000 ns                                            ; 10.004 ns       ; FB_SIZE0 ; FB_AD[8]  ;
-; -8.984 ns                               ; 1.000 ns                                            ; 9.984 ns        ; LP_D[5]  ; FB_AD[29] ;
-; -8.935 ns                               ; 1.000 ns                                            ; 9.935 ns        ; SRD[4]   ; FB_AD[20] ;
-; -8.933 ns                               ; 1.000 ns                                            ; 9.933 ns        ; nFB_OE   ; FB_AD[30] ;
-; -8.927 ns                               ; 1.000 ns                                            ; 9.927 ns        ; SRD[10]  ; FB_AD[26] ;
-; -8.926 ns                               ; 1.000 ns                                            ; 9.926 ns        ; nFB_OE   ; FB_AD[8]  ;
-; -8.924 ns                               ; 1.000 ns                                            ; 9.924 ns        ; nFB_CS2  ; FB_AD[6]  ;
-; -8.921 ns                               ; 1.000 ns                                            ; 9.921 ns        ; nFB_WR   ; FB_AD[4]  ;
-; -8.916 ns                               ; 1.000 ns                                            ; 9.916 ns        ; LP_D[6]  ; FB_AD[30] ;
-; -8.909 ns                               ; 1.000 ns                                            ; 9.909 ns        ; nFB_CS2  ; FB_AD[15] ;
-; -8.902 ns                               ; 1.000 ns                                            ; 9.902 ns        ; FB_SIZE1 ; FB_AD[8]  ;
-; -8.896 ns                               ; 1.000 ns                                            ; 9.896 ns        ; FB_SIZE0 ; FB_AD[5]  ;
-; -8.876 ns                               ; 1.000 ns                                            ; 9.876 ns        ; nFB_CS2  ; FB_AD[14] ;
-; -8.873 ns                               ; 1.000 ns                                            ; 9.873 ns        ; LP_BUSY  ; FB_AD[16] ;
-; -8.869 ns                               ; 1.000 ns                                            ; 9.869 ns        ; MAIN_CLK ; FB_AD[4]  ;
-; -8.864 ns                               ; 1.000 ns                                            ; 9.864 ns        ; nFB_OE   ; FB_AD[29] ;
-; -8.852 ns                               ; 1.000 ns                                            ; 9.852 ns        ; nFB_CS2  ; FB_AD[12] ;
-; -8.840 ns                               ; 1.000 ns                                            ; 9.840 ns        ; FB_SIZE1 ; FB_AD[5]  ;
-; -8.826 ns                               ; 1.000 ns                                            ; 9.826 ns        ; MAIN_CLK ; FB_AD[2]  ;
-; -8.819 ns                               ; 1.000 ns                                            ; 9.819 ns        ; DCD      ; FB_AD[3]  ;
-; -8.810 ns                               ; 1.000 ns                                            ; 9.810 ns        ; MAIN_CLK ; FB_AD[3]  ;
-; -8.804 ns                               ; 1.000 ns                                            ; 9.804 ns        ; nFB_OE   ; FB_AD[13] ;
-; -8.803 ns                               ; 1.000 ns                                            ; 9.803 ns        ; SRD[7]   ; FB_AD[23] ;
-; -8.780 ns                               ; 1.000 ns                                            ; 9.780 ns        ; nFB_CS2  ; FB_AD[1]  ;
-; -8.776 ns                               ; 1.000 ns                                            ; 9.776 ns        ; MAIN_CLK ; FB_AD[28] ;
-; -8.715 ns                               ; 1.000 ns                                            ; 9.715 ns        ; FB_SIZE0 ; FB_AD[12] ;
-; -8.715 ns                               ; 1.000 ns                                            ; 9.715 ns        ; FB_SIZE0 ; FB_AD[11] ;
-; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; FB_SIZE0 ; BA[0]     ;
-; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; nFB_OE   ; FB_AD[12] ;
-; -8.699 ns                               ; 1.000 ns                                            ; 9.699 ns        ; nFB_OE   ; FB_AD[11] ;
-; -8.672 ns                               ; 1.000 ns                                            ; 9.672 ns        ; FB_SIZE0 ; FB_AD[6]  ;
-; -8.660 ns                               ; 1.000 ns                                            ; 9.660 ns        ; RI       ; FB_AD[8]  ;
-; -8.659 ns                               ; 1.000 ns                                            ; 9.659 ns        ; FB_SIZE1 ; FB_AD[12] ;
-; -8.659 ns                               ; 1.000 ns                                            ; 9.659 ns        ; FB_SIZE1 ; FB_AD[11] ;
-; -8.656 ns                               ; 1.000 ns                                            ; 9.656 ns        ; nFB_OE   ; FB_AD[6]  ;
-; -8.651 ns                               ; 1.000 ns                                            ; 9.651 ns        ; FB_SIZE0 ; FB_AD[0]  ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                 ;          ;           ;
-+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; th                                                                                                                                                                                                                                                                               ;
-+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
-; Minimum Slack                           ; Required th                                         ; Actual th ; From      ; To                                                                                                                                            ; To Clock ;
-+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
-; -0.401 ns                               ; 1.000 ns                                            ; 1.401 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]                                                                 ; MAIN_CLK ;
-; -0.386 ns                               ; 1.000 ns                                            ; 1.386 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9]                                                                 ; MAIN_CLK ;
-; -0.383 ns                               ; 1.000 ns                                            ; 1.383 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5]                                                                 ; MAIN_CLK ;
-; -0.383 ns                               ; 1.000 ns                                            ; 1.383 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21]                                                               ; MAIN_CLK ;
-; -0.370 ns                               ; 1.000 ns                                            ; 1.370 ns  ; CTS       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[2]       ; MAIN_CLK ;
-; -0.339 ns                               ; 1.000 ns                                            ; 1.339 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2]                                                                 ; MAIN_CLK ;
-; -0.333 ns                               ; 1.000 ns                                            ; 1.333 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]                                                                    ; MAIN_CLK ;
-; -0.328 ns                               ; 1.000 ns                                            ; 1.328 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9]                                                                 ; MAIN_CLK ;
-; -0.325 ns                               ; 1.000 ns                                            ; 1.325 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]                                                                ; MAIN_CLK ;
-; -0.325 ns                               ; 1.000 ns                                            ; 1.325 ns  ; RI        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[14]      ; MAIN_CLK ;
-; -0.321 ns                               ; 1.000 ns                                            ; 1.321 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]                                                                 ; MAIN_CLK ;
-; -0.320 ns                               ; 1.000 ns                                            ; 1.320 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]                                                               ; MAIN_CLK ;
-; -0.310 ns                               ; 1.000 ns                                            ; 1.310 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5]                                                                     ; MAIN_CLK ;
-; -0.302 ns                               ; 1.000 ns                                            ; 1.302 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]                                                                ; MAIN_CLK ;
-; -0.302 ns                               ; 1.000 ns                                            ; 1.302 ns  ; CTS       ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[2]     ; MAIN_CLK ;
-; -0.293 ns                               ; 1.000 ns                                            ; 1.293 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2]                                                                 ; MAIN_CLK ;
-; -0.285 ns                               ; 1.000 ns                                            ; 1.285 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6]                                                                ; MAIN_CLK ;
-; -0.283 ns                               ; 1.000 ns                                            ; 1.283 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]                                                                 ; MAIN_CLK ;
-; -0.275 ns                               ; 1.000 ns                                            ; 1.275 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]                                                               ; MAIN_CLK ;
-; -0.272 ns                               ; 1.000 ns                                            ; 1.272 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8]                                                                 ; MAIN_CLK ;
-; -0.269 ns                               ; 1.000 ns                                            ; 1.269 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4]                                                                ; MAIN_CLK ;
-; -0.265 ns                               ; 1.000 ns                                            ; 1.265 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4]                                                                     ; MAIN_CLK ;
-; -0.252 ns                               ; 1.000 ns                                            ; 1.252 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3]                                                                 ; MAIN_CLK ;
-; -0.247 ns                               ; 1.000 ns                                            ; 1.247 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]                                                                 ; MAIN_CLK ;
-; -0.246 ns                               ; 1.000 ns                                            ; 1.246 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]                                                               ; MAIN_CLK ;
-; -0.245 ns                               ; 1.000 ns                                            ; 1.245 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]                                                                    ; MAIN_CLK ;
-; -0.238 ns                               ; 1.000 ns                                            ; 1.238 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16]                                                               ; MAIN_CLK ;
-; -0.235 ns                               ; 1.000 ns                                            ; 1.235 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3]                                                                  ; MAIN_CLK ;
-; -0.235 ns                               ; 1.000 ns                                            ; 1.235 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8]                                                                 ; MAIN_CLK ;
-; -0.227 ns                               ; 1.000 ns                                            ; 1.227 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18]                                                                    ; MAIN_CLK ;
-; -0.226 ns                               ; 1.000 ns                                            ; 1.226 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]                                                               ; MAIN_CLK ;
-; -0.224 ns                               ; 1.000 ns                                            ; 1.224 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18]                                                               ; MAIN_CLK ;
-; -0.223 ns                               ; 1.000 ns                                            ; 1.223 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0]                                                                 ; MAIN_CLK ;
-; -0.222 ns                               ; 1.000 ns                                            ; 1.222 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0]                                                                 ; MAIN_CLK ;
-; -0.216 ns                               ; 1.000 ns                                            ; 1.216 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]                                                                ; MAIN_CLK ;
-; -0.208 ns                               ; 1.000 ns                                            ; 1.208 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8]                                                                 ; MAIN_CLK ;
-; -0.202 ns                               ; 1.000 ns                                            ; 1.202 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22]                                                               ; MAIN_CLK ;
-; -0.197 ns                               ; 1.000 ns                                            ; 1.197 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]                                                                ; MAIN_CLK ;
-; -0.194 ns                               ; 1.000 ns                                            ; 1.194 ns  ; FB_AD[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]                                                               ; MAIN_CLK ;
-; -0.191 ns                               ; 1.000 ns                                            ; 1.191 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]                                                                ; MAIN_CLK ;
-; -0.189 ns                               ; 1.000 ns                                            ; 1.189 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6]                                                                     ; MAIN_CLK ;
-; -0.187 ns                               ; 1.000 ns                                            ; 1.187 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1]                                                                     ; MAIN_CLK ;
-; -0.181 ns                               ; 1.000 ns                                            ; 1.181 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4]                                                       ; MAIN_CLK ;
-; -0.179 ns                               ; 1.000 ns                                            ; 1.179 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3]                                                                ; MAIN_CLK ;
-; -0.173 ns                               ; 1.000 ns                                            ; 1.173 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18]                                                               ; MAIN_CLK ;
-; -0.172 ns                               ; 1.000 ns                                            ; 1.172 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0]                                                                 ; MAIN_CLK ;
-; -0.166 ns                               ; 1.000 ns                                            ; 1.166 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]                                                                ; MAIN_CLK ;
-; -0.165 ns                               ; 1.000 ns                                            ; 1.165 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10]                                                                ; MAIN_CLK ;
-; -0.162 ns                               ; 1.000 ns                                            ; 1.162 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6]                                                                 ; MAIN_CLK ;
-; -0.159 ns                               ; 1.000 ns                                            ; 1.159 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19]                                                                    ; MAIN_CLK ;
-; -0.159 ns                               ; 1.000 ns                                            ; 1.159 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27]                                                               ; MAIN_CLK ;
-; -0.154 ns                               ; 1.000 ns                                            ; 1.154 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19]                                                               ; MAIN_CLK ;
-; -0.151 ns                               ; 1.000 ns                                            ; 1.151 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9]                                                                 ; MAIN_CLK ;
-; -0.149 ns                               ; 1.000 ns                                            ; 1.149 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]                                                               ; MAIN_CLK ;
-; -0.146 ns                               ; 1.000 ns                                            ; 1.146 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1]                                                                 ; MAIN_CLK ;
-; -0.145 ns                               ; 1.000 ns                                            ; 1.145 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5]                                                                 ; MAIN_CLK ;
-; -0.142 ns                               ; 1.000 ns                                            ; 1.142 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9]                                                                 ; MAIN_CLK ;
-; -0.141 ns                               ; 1.000 ns                                            ; 1.141 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10]                                                                ; MAIN_CLK ;
-; -0.140 ns                               ; 1.000 ns                                            ; 1.140 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4]                                                                ; MAIN_CLK ;
-; -0.137 ns                               ; 1.000 ns                                            ; 1.137 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3]                                                                     ; MAIN_CLK ;
-; -0.134 ns                               ; 1.000 ns                                            ; 1.134 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]                                                                  ; MAIN_CLK ;
-; -0.130 ns                               ; 1.000 ns                                            ; 1.130 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]                                                               ; MAIN_CLK ;
-; -0.130 ns                               ; 1.000 ns                                            ; 1.130 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10]                                                                ; MAIN_CLK ;
-; -0.125 ns                               ; 1.000 ns                                            ; 1.125 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]                                                                     ; MAIN_CLK ;
-; -0.121 ns                               ; 1.000 ns                                            ; 1.121 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0]                                                                 ; MAIN_CLK ;
-; -0.121 ns                               ; 1.000 ns                                            ; 1.121 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2]                                                       ; MAIN_CLK ;
-; -0.113 ns                               ; 1.000 ns                                            ; 1.113 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5]                                                                 ; MAIN_CLK ;
-; -0.109 ns                               ; 1.000 ns                                            ; 1.109 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]                                                                 ; MAIN_CLK ;
-; -0.108 ns                               ; 1.000 ns                                            ; 1.108 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2]                                                                 ; MAIN_CLK ;
-; -0.099 ns                               ; 1.000 ns                                            ; 1.099 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10]                                                               ; MAIN_CLK ;
-; -0.094 ns                               ; 1.000 ns                                            ; 1.094 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]                                                               ; MAIN_CLK ;
-; -0.092 ns                               ; 1.000 ns                                            ; 1.092 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9]                                                                 ; MAIN_CLK ;
-; -0.090 ns                               ; 1.000 ns                                            ; 1.090 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]                                                                ; MAIN_CLK ;
-; -0.089 ns                               ; 1.000 ns                                            ; 1.089 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]                                                               ; MAIN_CLK ;
-; -0.087 ns                               ; 1.000 ns                                            ; 1.087 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3]                                                                 ; MAIN_CLK ;
-; -0.086 ns                               ; 1.000 ns                                            ; 1.086 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5]                                                       ; MAIN_CLK ;
-; -0.085 ns                               ; 1.000 ns                                            ; 1.085 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9]                                                                     ; MAIN_CLK ;
-; -0.081 ns                               ; 1.000 ns                                            ; 1.081 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0   ; MAIN_CLK ;
-; -0.079 ns                               ; 1.000 ns                                            ; 1.079 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]                                                               ; MAIN_CLK ;
-; -0.078 ns                               ; 1.000 ns                                            ; 1.078 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9]                                                                 ; MAIN_CLK ;
-; -0.077 ns                               ; 1.000 ns                                            ; 1.077 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9]                                                                 ; MAIN_CLK ;
-; -0.075 ns                               ; 1.000 ns                                            ; 1.075 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2]                                                                 ; MAIN_CLK ;
-; -0.074 ns                               ; 1.000 ns                                            ; 1.074 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21]                                                                    ; MAIN_CLK ;
-; -0.070 ns                               ; 1.000 ns                                            ; 1.070 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]                                                                ; MAIN_CLK ;
-; -0.070 ns                               ; 1.000 ns                                            ; 1.070 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14]                                                               ; MAIN_CLK ;
-; -0.068 ns                               ; 1.000 ns                                            ; 1.068 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5]                                                                 ; MAIN_CLK ;
-; -0.068 ns                               ; 1.000 ns                                            ; 1.068 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
-; -0.065 ns                               ; 1.000 ns                                            ; 1.065 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]                                                               ; MAIN_CLK ;
-; -0.064 ns                               ; 1.000 ns                                            ; 1.064 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]                                                                ; MAIN_CLK ;
-; -0.064 ns                               ; 1.000 ns                                            ; 1.064 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]                                                                ; MAIN_CLK ;
-; -0.062 ns                               ; 1.000 ns                                            ; 1.062 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27]                                                               ; MAIN_CLK ;
-; -0.059 ns                               ; 1.000 ns                                            ; 1.059 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3]                                                                 ; MAIN_CLK ;
-; -0.057 ns                               ; 1.000 ns                                            ; 1.057 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4]                                                                 ; MAIN_CLK ;
-; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18]                                                               ; MAIN_CLK ;
-; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[6]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6]                                                                ; MAIN_CLK ;
-; -0.055 ns                               ; 1.000 ns                                            ; 1.055 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25]                                                               ; MAIN_CLK ;
-; -0.053 ns                               ; 1.000 ns                                            ; 1.053 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]                                                                 ; MAIN_CLK ;
-; -0.047 ns                               ; 1.000 ns                                            ; 1.047 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3]                                                                 ; MAIN_CLK ;
-; -0.047 ns                               ; 1.000 ns                                            ; 1.047 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9]                                                       ; MAIN_CLK ;
-; -0.046 ns                               ; 1.000 ns                                            ; 1.046 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]                                                                 ; MAIN_CLK ;
-; -0.042 ns                               ; 1.000 ns                                            ; 1.042 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]                                                               ; MAIN_CLK ;
-; -0.042 ns                               ; 1.000 ns                                            ; 1.042 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8]                                                                 ; MAIN_CLK ;
-; -0.039 ns                               ; 1.000 ns                                            ; 1.039 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]                                                               ; MAIN_CLK ;
-; -0.037 ns                               ; 1.000 ns                                            ; 1.037 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]                                                       ; MAIN_CLK ;
-; -0.037 ns                               ; 1.000 ns                                            ; 1.037 ns  ; FB_AD[4]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4]                                                                ; MAIN_CLK ;
-; -0.035 ns                               ; 1.000 ns                                            ; 1.035 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14]                                                               ; MAIN_CLK ;
-; -0.033 ns                               ; 1.000 ns                                            ; 1.033 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]                                                               ; MAIN_CLK ;
-; -0.028 ns                               ; 1.000 ns                                            ; 1.028 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4]                                                                 ; MAIN_CLK ;
-; -0.026 ns                               ; 1.000 ns                                            ; 1.026 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]                                                                 ; MAIN_CLK ;
-; -0.022 ns                               ; 1.000 ns                                            ; 1.022 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0]                                                                ; MAIN_CLK ;
-; -0.018 ns                               ; 1.000 ns                                            ; 1.018 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]                                                                 ; MAIN_CLK ;
-; -0.018 ns                               ; 1.000 ns                                            ; 1.018 ns  ; FB_AD[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12]                                                               ; MAIN_CLK ;
-; -0.017 ns                               ; 1.000 ns                                            ; 1.017 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17]                                                                    ; MAIN_CLK ;
-; -0.017 ns                               ; 1.000 ns                                            ; 1.017 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]                                                                 ; MAIN_CLK ;
-; -0.011 ns                               ; 1.000 ns                                            ; 1.011 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3]                                                                ; MAIN_CLK ;
-; -0.010 ns                               ; 1.000 ns                                            ; 1.010 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3]                                                                 ; MAIN_CLK ;
-; -0.004 ns                               ; 1.000 ns                                            ; 1.004 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3]                                                                 ; MAIN_CLK ;
-; 0.007 ns                                ; 1.000 ns                                            ; 0.993 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2]                                                                 ; MAIN_CLK ;
-; 0.008 ns                                ; 1.000 ns                                            ; 0.992 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]                                                               ; MAIN_CLK ;
-; 0.009 ns                                ; 1.000 ns                                            ; 0.991 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10]                                                               ; MAIN_CLK ;
-; 0.009 ns                                ; 1.000 ns                                            ; 0.991 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]                                                                ; MAIN_CLK ;
-; 0.010 ns                                ; 1.000 ns                                            ; 0.990 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]                                                               ; MAIN_CLK ;
-; 0.015 ns                                ; 1.000 ns                                            ; 0.985 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2]                                                                 ; MAIN_CLK ;
-; 0.018 ns                                ; 1.000 ns                                            ; 0.982 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]                                                                 ; MAIN_CLK ;
-; 0.021 ns                                ; 1.000 ns                                            ; 0.979 ns  ; FB_AD[1]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1]                                                                ; MAIN_CLK ;
-; 0.022 ns                                ; 1.000 ns                                            ; 0.978 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2]                                                                ; MAIN_CLK ;
-; 0.027 ns                                ; 1.000 ns                                            ; 0.973 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]                                                                ; MAIN_CLK ;
-; 0.033 ns                                ; 1.000 ns                                            ; 0.967 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2]                                                                     ; MAIN_CLK ;
-; 0.036 ns                                ; 1.000 ns                                            ; 0.964 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6]                                                                 ; MAIN_CLK ;
-; 0.042 ns                                ; 1.000 ns                                            ; 0.958 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8]                                                                 ; MAIN_CLK ;
-; 0.044 ns                                ; 1.000 ns                                            ; 0.956 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0]                                                                ; MAIN_CLK ;
-; 0.045 ns                                ; 1.000 ns                                            ; 0.955 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22]                                                               ; MAIN_CLK ;
-; 0.045 ns                                ; 1.000 ns                                            ; 0.955 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]                                                                ; MAIN_CLK ;
-; 0.046 ns                                ; 1.000 ns                                            ; 0.954 ns  ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14]                                                               ; MAIN_CLK ;
-; 0.047 ns                                ; 1.000 ns                                            ; 0.953 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3]                                                                 ; MAIN_CLK ;
-; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]                                                       ; MAIN_CLK ;
-; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[14]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]              ; MAIN_CLK ;
-; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[5]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]               ; MAIN_CLK ;
-; 0.049 ns                                ; 1.000 ns                                            ; 0.951 ns  ; VD[5]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]               ; MAIN_CLK ;
-; 0.050 ns                                ; 1.000 ns                                            ; 0.950 ns  ; VD[14]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]              ; MAIN_CLK ;
-; 0.050 ns                                ; 1.000 ns                                            ; 0.950 ns  ; RI        ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[14]    ; MAIN_CLK ;
-; 0.054 ns                                ; 1.000 ns                                            ; 0.946 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3]                                                                ; MAIN_CLK ;
-; 0.054 ns                                ; 1.000 ns                                            ; 0.946 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]                                                                 ; MAIN_CLK ;
-; 0.055 ns                                ; 1.000 ns                                            ; 0.945 ns  ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29]                                                               ; MAIN_CLK ;
-; 0.055 ns                                ; 1.000 ns                                            ; 0.945 ns  ; VD[4]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]               ; MAIN_CLK ;
-; 0.057 ns                                ; 1.000 ns                                            ; 0.943 ns  ; VD[4]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]               ; MAIN_CLK ;
-; 0.064 ns                                ; 1.000 ns                                            ; 0.936 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20]                                                               ; MAIN_CLK ;
-; 0.078 ns                                ; 1.000 ns                                            ; 0.922 ns  ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]                                                                  ; MAIN_CLK ;
-; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3]                                                       ; MAIN_CLK ;
-; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; VD[8]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]               ; MAIN_CLK ;
-; 0.079 ns                                ; 1.000 ns                                            ; 0.921 ns  ; VD[8]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]               ; MAIN_CLK ;
-; 0.081 ns                                ; 1.000 ns                                            ; 0.919 ns  ; VD[7]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]               ; MAIN_CLK ;
-; 0.082 ns                                ; 1.000 ns                                            ; 0.918 ns  ; VD[7]     ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]               ; MAIN_CLK ;
-; 0.091 ns                                ; 1.000 ns                                            ; 0.909 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1]                                                                 ; MAIN_CLK ;
-; 0.098 ns                                ; 1.000 ns                                            ; 0.902 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3]                                                                ; MAIN_CLK ;
-; 0.106 ns                                ; 1.000 ns                                            ; 0.894 ns  ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9]                                                                 ; MAIN_CLK ;
-; 0.107 ns                                ; 1.000 ns                                            ; 0.893 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16]                                                                    ; MAIN_CLK ;
-; 0.109 ns                                ; 1.000 ns                                            ; 0.891 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0]                                                                ; MAIN_CLK ;
-; 0.110 ns                                ; 1.000 ns                                            ; 0.890 ns  ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27]                                                               ; MAIN_CLK ;
-; 0.114 ns                                ; 1.000 ns                                            ; 0.886 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
-; 0.119 ns                                ; 1.000 ns                                            ; 0.881 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]                                                               ; MAIN_CLK ;
-; 0.125 ns                                ; 1.000 ns                                            ; 0.875 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4]                                                                 ; MAIN_CLK ;
-; 0.125 ns                                ; 1.000 ns                                            ; 0.875 ns  ; FB_AD[5]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5]                                                                ; MAIN_CLK ;
-; 0.128 ns                                ; 1.000 ns                                            ; 0.872 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2]                                                                ; MAIN_CLK ;
-; 0.131 ns                                ; 1.000 ns                                            ; 0.869 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21]                                                               ; MAIN_CLK ;
-; 0.131 ns                                ; 1.000 ns                                            ; 0.869 ns  ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29]                                                               ; MAIN_CLK ;
-; 0.132 ns                                ; 1.000 ns                                            ; 0.868 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0    ; MAIN_CLK ;
-; 0.133 ns                                ; 1.000 ns                                            ; 0.867 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8]                                                                ; MAIN_CLK ;
-; 0.136 ns                                ; 1.000 ns                                            ; 0.864 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]                                                                 ; MAIN_CLK ;
-; 0.148 ns                                ; 1.000 ns                                            ; 0.852 ns  ; FB_AD[9]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9]                                                                ; MAIN_CLK ;
-; 0.149 ns                                ; 1.000 ns                                            ; 0.851 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6]                                                                 ; MAIN_CLK ;
-; 0.151 ns                                ; 1.000 ns                                            ; 0.849 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]                                                                 ; MAIN_CLK ;
-; 0.151 ns                                ; 1.000 ns                                            ; 0.849 ns  ; FB_AD[2]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]                                                                ; MAIN_CLK ;
-; 0.158 ns                                ; 1.000 ns                                            ; 0.842 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]                                                                ; MAIN_CLK ;
-; 0.159 ns                                ; 1.000 ns                                            ; 0.841 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]                                                                 ; MAIN_CLK ;
-; 0.159 ns                                ; 1.000 ns                                            ; 0.841 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22]                                                               ; MAIN_CLK ;
-; 0.161 ns                                ; 1.000 ns                                            ; 0.839 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4]                                                                 ; MAIN_CLK ;
-; 0.163 ns                                ; 1.000 ns                                            ; 0.837 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0]                                                                 ; MAIN_CLK ;
-; 0.168 ns                                ; 1.000 ns                                            ; 0.832 ns  ; FB_AD[7]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]                                                                ; MAIN_CLK ;
-; 0.170 ns                                ; 1.000 ns                                            ; 0.830 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0   ; MAIN_CLK ;
-; 0.170 ns                                ; 1.000 ns                                            ; 0.830 ns  ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]                                                                 ; MAIN_CLK ;
-; 0.172 ns                                ; 1.000 ns                                            ; 0.828 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8]                                                                     ; MAIN_CLK ;
-; 0.178 ns                                ; 1.000 ns                                            ; 0.822 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]                                                                    ; MAIN_CLK ;
-; 0.180 ns                                ; 1.000 ns                                            ; 0.820 ns  ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10]                                                               ; MAIN_CLK ;
-; 0.181 ns                                ; 1.000 ns                                            ; 0.819 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1]                                                                 ; MAIN_CLK ;
-; 0.186 ns                                ; 1.000 ns                                            ; 0.814 ns  ; FB_AD[0]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0]                                                                     ; MAIN_CLK ;
-; 0.188 ns                                ; 1.000 ns                                            ; 0.812 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]                                                       ; MAIN_CLK ;
-; 0.191 ns                                ; 1.000 ns                                            ; 0.809 ns  ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]                                                               ; MAIN_CLK ;
-; 0.195 ns                                ; 1.000 ns                                            ; 0.805 ns  ; FB_AD[23] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ;
-; 0.198 ns                                ; 1.000 ns                                            ; 0.802 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5]                                                                 ; MAIN_CLK ;
-; 0.201 ns                                ; 1.000 ns                                            ; 0.799 ns  ; FB_AD[8]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8]                                                                ; MAIN_CLK ;
-; 0.202 ns                                ; 1.000 ns                                            ; 0.798 ns  ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]                                                                 ; MAIN_CLK ;
-; 0.209 ns                                ; 1.000 ns                                            ; 0.791 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4]                                                                 ; MAIN_CLK ;
-; 0.213 ns                                ; 1.000 ns                                            ; 0.787 ns  ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0]                                                           ; MAIN_CLK ;
-; 0.216 ns                                ; 1.000 ns                                            ; 0.784 ns  ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]                                                                    ; MAIN_CLK ;
-; 0.220 ns                                ; 1.000 ns                                            ; 0.780 ns  ; VD[26]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]              ; MAIN_CLK ;
-; 0.221 ns                                ; 1.000 ns                                            ; 0.779 ns  ; VD[26]    ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]              ; MAIN_CLK ;
-; 0.228 ns                                ; 1.000 ns                                            ; 0.772 ns  ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0]                                                                 ; MAIN_CLK ;
-; 0.228 ns                                ; 1.000 ns                                            ; 0.772 ns  ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5]                                                                 ; MAIN_CLK ;
-; 0.233 ns                                ; 1.000 ns                                            ; 0.767 ns  ; FB_AD[3]  ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3]                                                                ; MAIN_CLK ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;                                                                                                                                               ;          ;
-+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                    ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
-; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
-; CLK24M576     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_STR        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; CLK25M        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nACSI_ACK     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nACSI_RESET   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nACSI_CS      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_DIR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_A1       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_DIR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; MIDI_OLR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; MIDI_TLR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; TxD           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; RTS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; DTR           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; AMKB_TX       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IDE_RES       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIDE_CS0      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIDE_CS1      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIDE_WR       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIDE_RD       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nCF_CS0       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nCF_CS1       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nROM3         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nROM4         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nRP_UDS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nRP_LDS       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSDSEL        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nWR_GATE      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nWR           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; YM_QA         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; YM_QB         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; YM_QC         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SD_CLK        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; DSA_D         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nVWE          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nVCAS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nVRAS         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nVCS          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nPD_VGA       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; TIN0          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSRCS         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSRBLE        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSRBHE        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSRWE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nDREQ1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LED_FPGA_OK   ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSROE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VCKE          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nFB_TA        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nDDR_CLK      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; DDR_CLK       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSYNC         ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nMOT_ON       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSTEP         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; CLKUSB        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LPDIR         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; BA[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; BA[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[4]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[3]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nIRQ[2]       ; 3.0-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[12]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[11]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[10]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[9]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[8]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[7]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[6]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[5]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[4]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[3]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VA[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VB[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDM[3]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDM[2]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDM[1]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDM[0]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VG[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[7]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[6]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[5]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[4]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[3]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[2]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[1]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VR[0]         ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[31]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[30]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[29]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[28]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[27]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[26]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[25]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[24]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[23]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[22]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[21]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[20]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[19]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[18]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[17]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[16]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[15]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[14]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[13]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[12]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[11]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[10]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[9]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[8]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[7]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[6]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[5]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[4]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; FB_AD[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[31]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[30]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[29]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[28]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[27]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[26]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[25]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[24]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[23]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[22]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[21]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[20]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[19]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[18]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[17]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[16]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[15]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[14]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[13]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[12]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[11]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[10]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[9]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[8]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[7]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[6]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[5]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[4]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[3]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VD[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDQS[3]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDQS[2]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDQS[1]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; VDQS[0]       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[17]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[16]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[15]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[14]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[13]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[12]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[11]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[10]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[9]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[8]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[7]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[6]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[5]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[4]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; IO[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SRD[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_PAR      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; nSCSI_RST     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; LP_D[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
-+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
-
-
-+----------------------------------------------------------------------------+
-; Input Transition Times                                                     ;
-+-------------------------+--------------+-----------------+-----------------+
-; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+-------------------------+--------------+-----------------+-----------------+
-; nFB_BURST               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nACSI_DRQ               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nACSI_INT               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_DRQ               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_MSG               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nDCHG                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_DATA0                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_DATA1                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_DATA2                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_CARD_DEDECT          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_WP                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nDACK0                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; WP_CF_CARD              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_C_D               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_I_O               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nFB_CS3                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; TOUT0                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nMASTER                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[31]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[30]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[29]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[28]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[27]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[26]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[25]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[24]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[23]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[22]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[21]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[20]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[19]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[18]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[17]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[16]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[15]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[14]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[13]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[12]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[11]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[10]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[9]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[8]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[7]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[6]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[5]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[4]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[3]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[2]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[1]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_AD[0]                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; VD[31]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[30]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[29]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[28]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[27]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[26]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[25]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[24]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[23]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[22]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[21]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[20]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[19]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[18]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[17]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[16]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[15]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[14]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[13]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[12]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[11]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[10]                  ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[9]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[8]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[7]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[6]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[5]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[4]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[3]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[2]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[1]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VD[0]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VDQS[3]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VDQS[2]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VDQS[1]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; VDQS[0]                 ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; IO[17]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[16]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[15]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[14]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[13]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[12]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[11]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[10]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IO[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[15]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[14]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[13]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[12]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[11]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[10]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[9]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[8]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[7]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[6]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[5]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[4]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[3]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SRD[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_PAR                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_SEL               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_BUSY              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nSCSI_RST               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_CD_DATA3             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SD_CMD_D1               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ACSI_D[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[7]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[6]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[5]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[4]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[3]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[2]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[1]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_D[0]                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; SCSI_D[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nRSTO_MCF               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nFB_WR                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nFB_CS1                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_SIZE1                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_SIZE0                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; FB_ALE                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nFB_CS2                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; MAIN_CLK                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nDACK1                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nFB_OE                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IDE_RDY                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CLK33M                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; HD_DD                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nINDEX                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; RxD                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nWP                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; LP_BUSY                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; DCD                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; CTS                     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; TRACK00                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; IDE_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; RI                      ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nPCI_INTD               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nPCI_INTC               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nPCI_INTB               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nPCI_INTA               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; DVI_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; E0_INT                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; PIC_INT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; PIC_AMKB_RX             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; MIDI_IN                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; nRD_DATA                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; AMKB_RX                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ~ALTERA_DCLK~           ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
-; ~ALTERA_DEV_OE~         ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-; ~ALTERA_DEV_CLRn~       ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
-+-------------------------+--------------+-----------------+-----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; CLK24M576     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_STR        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; CLK25M        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0394 V           ; 0.292 V                              ; 0.188 V                              ; 9.15e-010 s                 ; 8.35e-010 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0394 V          ; 0.292 V                             ; 0.188 V                             ; 9.15e-010 s                ; 8.35e-010 s                ; No                        ; Yes                       ;
-; nACSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nACSI_RESET   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nACSI_CS      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_A1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; MIDI_OLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; MIDI_TLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; RTS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; DTR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; AMKB_TX       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.36e-006 V                  ; 3.09 V              ; -0.013 V            ; 0.103 V                              ; 0.224 V                              ; 1.59e-009 s                 ; 1.71e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.36e-006 V                 ; 3.09 V             ; -0.013 V           ; 0.103 V                             ; 0.224 V                             ; 1.59e-009 s                ; 1.71e-009 s                ; Yes                       ; Yes                       ;
-; IDE_RES       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; nIDE_CS0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nIDE_CS1      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nIDE_WR       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nIDE_RD       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nCF_CS0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nCF_CS1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nROM3         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nROM4         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nRP_UDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nRP_LDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0394 V           ; 0.292 V                              ; 0.188 V                              ; 9.15e-010 s                 ; 8.35e-010 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0394 V          ; 0.292 V                             ; 0.188 V                             ; 9.15e-010 s                ; 8.35e-010 s                ; No                        ; Yes                       ;
-; nSDSEL        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nWR_GATE      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; nWR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; YM_QA         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; YM_QB         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; YM_QC         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SD_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; DSA_D         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nVWE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; nVCAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; nVRAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; nVCS          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
-; nPD_VGA       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; TIN0          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; nSRCS         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nSRBLE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nSRBHE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nSRWE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nDREQ1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LED_FPGA_OK   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.97e-006 V                  ; 2.34 V              ; -0.00258 V          ; 0.168 V                              ; 0.069 V                              ; 1.53e-009 s                 ; 1.92e-009 s                 ; No                         ; Yes                        ; 2.32 V                      ; 1.97e-006 V                 ; 2.34 V             ; -0.00258 V         ; 0.168 V                             ; 0.069 V                             ; 1.53e-009 s                ; 1.92e-009 s                ; No                        ; Yes                       ;
-; nSROE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; VCKE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; nFB_TA        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nDDR_CLK      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; DDR_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
-; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; nSYNC         ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.97e-007 V                  ; 2.86 V              ; -0.0234 V           ; 0.145 V                              ; 0.061 V                              ; 4.67e-010 s                 ; 4.98e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.97e-007 V                 ; 2.86 V             ; -0.0234 V          ; 0.145 V                             ; 0.061 V                             ; 4.67e-010 s                ; 4.98e-010 s                ; Yes                       ; Yes                       ;
-; nMOT_ON       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; nSTEP         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; CLKUSB        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; LPDIR         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; BA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; BA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
-; nIRQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nIRQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nIRQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; nIRQ[4]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
-; nIRQ[3]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
-; nIRQ[2]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.1e-006 V                   ; 2.84 V              ; -0.0267 V           ; 0.263 V                              ; 0.124 V                              ; 7.35e-010 s                 ; 8.02e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 1.1e-006 V                  ; 2.84 V             ; -0.0267 V          ; 0.263 V                             ; 0.124 V                             ; 7.35e-010 s                ; 8.02e-010 s                ; Yes                       ; Yes                       ;
-; VA[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
-; VA[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VA[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VA[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VA[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
-; VB[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
-; VB[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VB[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VDM[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
-; VDM[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VDM[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
-; VDM[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VG[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
-; VG[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VG[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.81 V              ; -0.00874 V          ; 0.219 V                              ; 0.11 V                               ; 1.91e-009 s                 ; 2.08e-009 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.81 V             ; -0.00874 V         ; 0.219 V                             ; 0.11 V                              ; 1.91e-009 s                ; 2.08e-009 s                ; Yes                       ; Yes                       ;
-; VR[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; VR[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 6.88e-007 V                  ; 2.86 V              ; -0.0441 V           ; 0.132 V                              ; 0.083 V                              ; 4.56e-010 s                 ; 4.87e-010 s                 ; Yes                        ; Yes                        ; 2.8 V                       ; 6.88e-007 V                 ; 2.86 V             ; -0.0441 V          ; 0.132 V                             ; 0.083 V                             ; 4.56e-010 s                ; 4.87e-010 s                ; Yes                       ; Yes                       ;
-; FB_AD[31]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[30]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[29]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[28]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[27]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; FB_AD[26]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[25]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[24]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[23]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[22]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[21]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[20]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[19]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[18]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; FB_AD[17]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[16]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[15]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[14]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[13]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; FB_AD[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; FB_AD[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; VD[31]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[30]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
-; VD[29]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[28]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[27]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[26]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[25]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[24]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[23]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[22]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.33 V              ; -0.00282 V          ; 0.119 V                              ; 0.046 V                              ; 2.08e-009 s                 ; 2.71e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.33 V             ; -0.00282 V         ; 0.119 V                             ; 0.046 V                             ; 2.08e-009 s                ; 2.71e-009 s                ; Yes                       ; Yes                       ;
-; VD[21]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[20]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[19]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[18]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[17]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[16]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VD[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
-; VD[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.37 V              ; -0.00683 V          ; 0.081 V                              ; 0.016 V                              ; 4.14e-010 s                 ; 5.19e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.37 V             ; -0.00683 V         ; 0.081 V                             ; 0.016 V                             ; 4.14e-010 s                ; 5.19e-010 s                ; Yes                       ; Yes                       ;
-; VD[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.33 V              ; -0.00279 V          ; 0.14 V                               ; 0.06 V                               ; 2.15e-009 s                 ; 2.83e-009 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.33 V             ; -0.00279 V         ; 0.14 V                              ; 0.06 V                              ; 2.15e-009 s                ; 2.83e-009 s                ; Yes                       ; Yes                       ;
-; VD[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VD[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VDQS[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VDQS[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 6.14e-007 V                  ; 2.36 V              ; -0.00551 V          ; 0.142 V                              ; 0.014 V                              ; 4.9e-010 s                  ; 6.6e-010 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 6.14e-007 V                 ; 2.36 V             ; -0.00551 V         ; 0.142 V                             ; 0.014 V                             ; 4.9e-010 s                 ; 6.6e-010 s                 ; Yes                       ; Yes                       ;
-; VDQS[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; VDQS[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 9.13e-007 V                  ; 2.36 V              ; -0.00797 V          ; 0.096 V                              ; 0.016 V                              ; 2.7e-010 s                  ; 3.71e-010 s                 ; Yes                        ; Yes                        ; 2.32 V                      ; 9.13e-007 V                 ; 2.36 V             ; -0.00797 V         ; 0.096 V                             ; 0.016 V                             ; 2.7e-010 s                 ; 3.71e-010 s                ; Yes                       ; Yes                       ;
-; IO[17]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[16]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[15]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[14]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[13]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; IO[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; IO[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; IO[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; SRD[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SRD[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; SCSI_PAR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; nSCSI_RST     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.08 V              ; -0.0041 V           ; 0.274 V                              ; 0.267 V                              ; 5.67e-009 s                 ; 4.62e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.08 V             ; -0.0041 V          ; 0.274 V                             ; 0.267 V                             ; 5.67e-009 s                ; 4.62e-009 s                ; No                        ; Yes                       ;
-; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; LP_D[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.08 V              ; -0.00548 V          ; 0.305 V                              ; 0.267 V                              ; 5.3e-009 s                  ; 4.39e-009 s                 ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-006 V                 ; 3.08 V             ; -0.00548 V         ; 0.305 V                             ; 0.267 V                             ; 5.3e-009 s                 ; 4.39e-009 s                ; Yes                       ; Yes                       ;
-; LP_D[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; LP_D[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-006 V                  ; 3.13 V              ; -0.0541 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-010 s                 ; 6.12e-010 s                 ; No                         ; No                         ; 3.08 V                      ; 3.08e-006 V                 ; 3.13 V             ; -0.0541 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-010 s                ; 6.12e-010 s                ; No                        ; No                        ;
-; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-006 V                  ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-009 s                 ; 1.07e-009 s                 ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-006 V                 ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-009 s                ; 1.07e-009 s                ; No                        ; Yes                       ;
-; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 2.8 V                        ; 1.43e-006 V                  ; 2.84 V              ; -0.0141 V           ; 0.183 V                              ; 0.066 V                              ; 8.84e-010 s                 ; 1.02e-009 s                 ; No                         ; Yes                        ; 2.8 V                       ; 1.43e-006 V                 ; 2.84 V             ; -0.0141 V          ; 0.183 V                             ; 0.066 V                             ; 8.84e-010 s                ; 1.02e-009 s                ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; CLK24M576     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_STR        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; CLK25M        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.57 V              ; -0.0649 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-010 s                 ; 6.19e-010 s                 ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-007 V                 ; 3.57 V             ; -0.0649 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-010 s                ; 6.19e-010 s                ; No                        ; Yes                       ;
-; nACSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nACSI_RESET   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nACSI_CS      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_A1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nSCSI_ACK     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nSCSI_ATN     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_DIR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; MIDI_OLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; MIDI_TLR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; TxD           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; RTS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; DTR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; AMKB_TX       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-007 V                   ; 3.5 V               ; -0.042 V            ; 0.297 V                              ; 0.24 V                               ; 1.12e-009 s                 ; 1.29e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 2.1e-007 V                  ; 3.5 V              ; -0.042 V           ; 0.297 V                             ; 0.24 V                              ; 1.12e-009 s                ; 1.29e-009 s                ; No                        ; No                        ;
-; IDE_RES       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; nIDE_CS0      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nIDE_CS1      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nIDE_WR       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nIDE_RD       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nCF_CS0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nCF_CS1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nROM3         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nROM4         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nRP_UDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nRP_LDS       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.57 V              ; -0.0649 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-010 s                 ; 6.19e-010 s                 ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-007 V                 ; 3.57 V             ; -0.0649 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-010 s                ; 6.19e-010 s                ; No                        ; Yes                       ;
-; nSDSEL        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nWR_GATE      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; nWR           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; YM_QA         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; YM_QB         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; YM_QC         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SD_CLK        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; DSA_D         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nVWE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; nVCAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; nVRAS         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; nVCS          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
-; nPD_VGA       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; TIN0          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; nSRCS         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nSRBLE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nSRBHE        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nSRWE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nDREQ1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LED_FPGA_OK   ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 7.2e-008 V                   ; 2.68 V              ; -0.0147 V           ; 0.295 V                              ; 0.167 V                              ; 9.36e-010 s                 ; 1.3e-009 s                  ; No                         ; Yes                        ; 2.62 V                      ; 7.2e-008 V                  ; 2.68 V             ; -0.0147 V          ; 0.295 V                             ; 0.167 V                             ; 9.36e-010 s                ; 1.3e-009 s                 ; No                        ; Yes                       ;
-; nSROE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; VCKE          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; nFB_TA        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nDDR_CLK      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; DDR_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
-; HSYNC_PAD     ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; nBLANK_PAD    ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; PIXEL_CLK_PAD ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; nSYNC         ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.66e-008 V                  ; 3.29 V              ; -0.0256 V           ; 0.236 V                              ; 0.049 V                              ; 2.86e-010 s                 ; 3.59e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.66e-008 V                 ; 3.29 V             ; -0.0256 V          ; 0.236 V                             ; 0.049 V                             ; 2.86e-010 s                ; 3.59e-010 s                ; Yes                       ; Yes                       ;
-; nMOT_ON       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nSTEP_DIR     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; nSTEP         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; CLKUSB        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; LPDIR         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; BA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; BA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
-; nIRQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nIRQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nIRQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; nIRQ[4]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
-; nIRQ[3]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
-; nIRQ[2]       ; 3.0-V LVCMOS ; 0 s                 ; 0 s                 ; 3.15 V                       ; 5.7e-008 V                   ; 3.25 V              ; -0.0382 V           ; 0.318 V                              ; 0.098 V                              ; 5.02e-010 s                 ; 5.55e-010 s                 ; No                         ; Yes                        ; 3.15 V                      ; 5.7e-008 V                  ; 3.25 V             ; -0.0382 V          ; 0.318 V                             ; 0.098 V                             ; 5.02e-010 s                ; 5.55e-010 s                ; No                        ; Yes                       ;
-; VA[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
-; VA[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VA[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VA[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VA[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VA[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
-; VB[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
-; VB[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VB[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VDM[3]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
-; VDM[2]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VDM[1]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
-; VDM[0]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VG[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
-; VG[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VG[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[7]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[6]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.19 V              ; -0.0203 V           ; 0.22 V                               ; 0.194 V                              ; 1.43e-009 s                 ; 1.59e-009 s                 ; No                         ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.19 V             ; -0.0203 V          ; 0.22 V                              ; 0.194 V                             ; 1.43e-009 s                ; 1.59e-009 s                ; No                        ; Yes                       ;
-; VR[5]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[4]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[3]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[2]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[1]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; VR[0]         ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 3.57e-008 V                  ; 3.27 V              ; -0.0618 V           ; 0.21 V                               ; 0.097 V                              ; 2.81e-010 s                 ; 3.83e-010 s                 ; Yes                        ; Yes                        ; 3.15 V                      ; 3.57e-008 V                 ; 3.27 V             ; -0.0618 V          ; 0.21 V                              ; 0.097 V                             ; 2.81e-010 s                ; 3.83e-010 s                ; Yes                       ; Yes                       ;
-; FB_AD[31]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[30]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[29]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[28]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[27]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; FB_AD[26]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[25]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[24]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[23]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[22]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[21]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[20]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[19]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[18]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; FB_AD[17]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[16]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[15]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[14]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[13]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[12]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[11]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[10]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[9]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[8]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[7]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; FB_AD[6]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[5]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[4]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; FB_AD[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; VD[31]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[30]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
-; VD[29]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[28]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[27]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[26]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[25]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[24]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[23]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[22]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.65 V              ; -0.00976 V          ; 0.206 V                              ; 0.133 V                              ; 1.45e-009 s                 ; 1.89e-009 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.65 V             ; -0.00976 V         ; 0.206 V                             ; 0.133 V                             ; 1.45e-009 s                ; 1.89e-009 s                ; No                        ; Yes                       ;
-; VD[21]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[20]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[19]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[18]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[17]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[16]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VD[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
-; VD[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.73 V              ; -0.0168 V           ; 0.137 V                              ; 0.024 V                              ; 2.65e-010 s                 ; 3.37e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.73 V             ; -0.0168 V          ; 0.137 V                             ; 0.024 V                             ; 2.65e-010 s                ; 3.37e-010 s                ; Yes                       ; Yes                       ;
-; VD[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.65 V              ; -0.00959 V          ; 0.236 V                              ; 0.105 V                              ; 1.48e-009 s                 ; 2e-009 s                    ; No                         ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.65 V             ; -0.00959 V         ; 0.236 V                             ; 0.105 V                             ; 1.48e-009 s                ; 2e-009 s                   ; No                        ; Yes                       ;
-; VD[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VD[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VDQS[3]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VDQS[2]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.33e-008 V                  ; 2.72 V              ; -0.00806 V          ; 0.218 V                              ; 0.013 V                              ; 2.92e-010 s                 ; 4.58e-010 s                 ; Yes                        ; Yes                        ; 2.62 V                      ; 2.33e-008 V                 ; 2.72 V             ; -0.00806 V         ; 0.218 V                             ; 0.013 V                             ; 2.92e-010 s                ; 4.58e-010 s                ; Yes                       ; Yes                       ;
-; VDQS[1]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; VDQS[0]       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.47e-008 V                  ; 2.83 V              ; -0.0265 V           ; 0.321 V                              ; 0.029 V                              ; 1.21e-010 s                 ; 2.36e-010 s                 ; No                         ; Yes                        ; 2.62 V                      ; 3.47e-008 V                 ; 2.83 V             ; -0.0265 V          ; 0.321 V                             ; 0.029 V                             ; 1.21e-010 s                ; 2.36e-010 s                ; No                        ; Yes                       ;
-; IO[17]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[16]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[15]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[14]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[13]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; IO[12]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[11]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[10]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[9]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[8]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[7]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[6]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[5]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; IO[4]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; IO[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; SRD[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SRD[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; SCSI_PAR      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nSCSI_SEL     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nSCSI_BUSY    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; nSCSI_RST     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SD_CD_DATA3   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SD_CMD_D1     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; ACSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; ACSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ACSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.347 V                              ; 4.12e-009 s                 ; 3.35e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.347 V                             ; 4.12e-009 s                ; 3.35e-009 s                ; No                        ; No                        ;
-; ACSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; LP_D[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.48 V              ; -0.0145 V           ; 0.362 V                              ; 0.287 V                              ; 3.89e-009 s                 ; 3.26e-009 s                 ; No                         ; No                         ; 3.46 V                      ; 1.9e-007 V                  ; 3.48 V             ; -0.0145 V          ; 0.362 V                             ; 0.287 V                             ; 3.89e-009 s                ; 3.26e-009 s                ; No                        ; No                        ;
-; LP_D[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; LP_D[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-007 V                   ; 3.59 V              ; -0.0877 V           ; 0.332 V                              ; 0.187 V                              ; 4.6e-010 s                  ; 4.2e-010 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-007 V                  ; 3.59 V             ; -0.0877 V          ; 0.332 V                             ; 0.187 V                             ; 4.6e-010 s                 ; 4.2e-010 s                 ; No                        ; Yes                       ;
-; SCSI_D[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; SCSI_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-007 V                  ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.351 V                              ; 9.04e-010 s                 ; 7.28e-010 s                 ; No                         ; No                         ; 3.46 V                      ; 1.29e-007 V                 ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.351 V                             ; 9.04e-010 s                ; 7.28e-010 s                ; No                        ; No                        ;
-; ~ALTERA_nCEO~ ; 3.0-V LVTTL  ; 0 s                 ; 0 s                 ; 3.15 V                       ; 7.44e-008 V                  ; 3.24 V              ; -0.0384 V           ; 0.38 V                               ; 0.235 V                              ; 5.22e-010 s                 ; 7e-010 s                    ; No                         ; Yes                        ; 3.15 V                      ; 7.44e-008 V                 ; 3.24 V             ; -0.0384 V          ; 0.38 V                              ; 0.235 V                             ; 5.22e-010 s                ; 7e-010 s                   ; No                        ; Yes                       ;
-+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Ignored Timing Assignments                                                                                                                                                                                                                 ;
-+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
-; Option          ; Setting  ; From            ; To                                                               ; Entity Name ; Help                                                                                                       ;
-+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
-; Cut Timing Path ; On       ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a                                        ; dcfifo_8fi1 ; Node named delayed_wrptr_g removed during synthesis                                                        ;
-; Clock Settings  ; fast     ;                 ; DDRCLK                                                           ;             ; Node named DDRCLK removed during synthesis                                                                 ;
-; Clock Settings  ; fast     ;                 ; DDRCLK[0]                                                        ;             ; Node named DDRCLK[0] removed during synthesis                                                              ;
-; Clock Settings  ; fast     ;                 ; DDRCLK[1]                                                        ;             ; Node named DDRCLK[1] removed during synthesis                                                              ;
-; Clock Settings  ; fast     ;                 ; DDRCLK[2]                                                        ;             ; Node named DDRCLK[2] removed during synthesis                                                              ;
-; Clock Settings  ; fast     ;                 ; DDRCLK[3]                                                        ;             ; Node named DDRCLK[3] removed during synthesis                                                              ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK                                    ;             ; Node named Video:Fredi_Aschwanden|DDRCLK removed during synthesis                                          ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[0]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[0] removed during synthesis                                       ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[1]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[1] removed during synthesis                                       ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[2]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[2] removed during synthesis                                       ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDRCLK[3]                                 ;             ; Node named Video:Fredi_Aschwanden|DDRCLK[3] removed during synthesis                                       ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK    ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK was found in the netlist    ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] was found in the netlist ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] was found in the netlist ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] was found in the netlist ;
-; Clock Settings  ; fast     ;                 ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] ;             ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] was found in the netlist ;
-; Maximum Delay   ; 5 ns     ; VD              ; FB_AD                                                            ;             ; No timing path applicable to specified source and destination                                              ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[16]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[22]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[17]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[18]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[18]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[24]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[15]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[25]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[19]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[23]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[5]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; BA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[3]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[10]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[14]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[26]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[12]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[21]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[11]                                                           ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[7]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[9]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; nVRAS                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[20]       ; VA[6]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; BA[1]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[13]       ; VA[4]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[12]       ; VA[8]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[30]       ; VA[0]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-; MAX_DELAY       ; 5.000 ns ; FB_AD[31]       ; VA[2]                                                            ;             ; Assignment is illegal for node and/or path                                                                 ;
-+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+
-
-
-+--------------------------+
-; Timing Analyzer Messages ;
-+--------------------------+
-Info: *******************************************************************
-Info: Running Quartus II Classic Timing Analyzer
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Wed Dec 15 02:25:14 2010
-Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only
-Warning: Timing Analysis is analyzing one or more combinational loops as latches
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]" is a latch
-    Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]" is a latch
-Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
-Warning: Clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" frequency requirement of 47.96 MHz overrides "Cyclone III" PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 48.0 MHz
-Warning: Clock Setting "fast" is unassigned
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" input frequency requirement of 0.5 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" input frequency requirement of 2.46 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" input frequency requirement of 24.57 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" input frequency requirement of 2.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" input frequency requirement of 15.99 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" input frequency requirement of 24.98 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" input frequency requirement of 47.96 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" input frequency requirement of 66.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 95.92 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported
-Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[3]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[1]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[4]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[2]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[5]" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[3]~23" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[1]~25" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[4]~22" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[2]~24" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[0]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[6]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[9]" as buffer
-    Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[8]" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[5]~21" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[0]~26" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[6]~20" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[9]~18" as buffer
-    Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[8]~19" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~31" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~30" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~2" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]" as buffer
-    Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~29" as buffer
-    Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1" as buffer
-Info: Found timing assignments -- calculating delays
-Info: Slack time is 1.997 us for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]"
-    Info: Fmax is 362.45 MHz (period= 2.759 ns)
-    Info: + Largest register to register requirement is 1999.813 ns
-        Info: + Setup relationship between source and destination is 1999.998 ns
-            Info: + Latch edge is 1990.420 ns
-                Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is -9.578 ns
-                Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -0.001 ns
-            Info: + Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
-            Info: - Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.532 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.084 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.998 ns ( 84.88 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest register to register delay is 2.574 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]'
-        Info: 2: + IC(0.325 ns) + CELL(0.446 ns) = 0.771 ns; Loc. = LCCOMB_X65_Y16_N14; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita0~COUT'
-        Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.829 ns; Loc. = LCCOMB_X65_Y16_N16; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita1~COUT'
-        Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.887 ns; Loc. = LCCOMB_X65_Y16_N18; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita2~COUT'
-        Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.945 ns; Loc. = LCCOMB_X65_Y16_N20; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita3~COUT'
-        Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 1.003 ns; Loc. = LCCOMB_X65_Y16_N22; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita4~COUT'
-        Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 1.061 ns; Loc. = LCCOMB_X65_Y16_N24; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita5~COUT'
-        Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 1.119 ns; Loc. = LCCOMB_X65_Y16_N26; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita6~COUT'
-        Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 1.177 ns; Loc. = LCCOMB_X65_Y16_N28; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita7~COUT'
-        Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 1.235 ns; Loc. = LCCOMB_X65_Y16_N30; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita8~COUT'
-        Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 1.293 ns; Loc. = LCCOMB_X65_Y15_N0; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita9~COUT'
-        Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 1.351 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10~COUT'
-        Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 1.409 ns; Loc. = LCCOMB_X65_Y15_N4; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita11~COUT'
-        Info: 14: + IC(0.000 ns) + CELL(0.058 ns) = 1.467 ns; Loc. = LCCOMB_X65_Y15_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita12~COUT'
-        Info: 15: + IC(0.000 ns) + CELL(0.058 ns) = 1.525 ns; Loc. = LCCOMB_X65_Y15_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita13~COUT'
-        Info: 16: + IC(0.000 ns) + CELL(0.058 ns) = 1.583 ns; Loc. = LCCOMB_X65_Y15_N10; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita14~COUT'
-        Info: 17: + IC(0.000 ns) + CELL(0.058 ns) = 1.641 ns; Loc. = LCCOMB_X65_Y15_N12; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita15~COUT'
-        Info: 18: + IC(0.000 ns) + CELL(0.058 ns) = 1.699 ns; Loc. = LCCOMB_X65_Y15_N14; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita16~COUT'
-        Info: 19: + IC(0.000 ns) + CELL(0.455 ns) = 2.154 ns; Loc. = LCCOMB_X65_Y15_N16; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita17'
-        Info: 20: + IC(0.199 ns) + CELL(0.130 ns) = 2.483 ns; Loc. = LCCOMB_X65_Y15_N26; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]~feeder'
-        Info: 21: + IC(0.000 ns) + CELL(0.091 ns) = 2.574 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]'
-        Info: Total cell delay = 2.050 ns ( 79.64 % )
-        Info: Total interconnect delay = 0.524 ns ( 20.36 % )
-Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]"
-Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]"
-Info: Slack time is 498.663 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]"
-    Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits
-    Info: + Largest register to register requirement is 500.232 ns
-        Info: + Setup relationship between source and destination is 500.416 ns
-            Info: + Latch edge is 498.552 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is -1.864 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 0.000 ns
-            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]'
-                Info: Total cell delay = 0.534 ns ( 15.16 % )
-                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
-            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-                Info: Total cell delay = 0.534 ns ( 15.16 % )
-                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest register to register delay is 1.569 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-        Info: 2: + IC(0.344 ns) + CELL(0.376 ns) = 0.720 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 5; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13'
-        Info: 3: + IC(0.240 ns) + CELL(0.609 ns) = 1.569 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]'
-        Info: Total cell delay = 0.985 ns ( 62.78 % )
-        Info: Total interconnect delay = 0.584 ns ( 37.22 % )
-Info: Slack time is 28.59 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK"
-    Info: Fmax is 186.15 MHz (period= 5.372 ns)
-    Info: + Largest register to register requirement is 31.135 ns
-        Info: + Setup relationship between source and destination is 31.276 ns
-            Info: + Latch edge is 60.688 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 29.412 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with inverted offset of 29.412 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 0.020 ns
-            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.508 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.065 ns) + CELL(0.534 ns) = 3.508 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK'
-                Info: Total cell delay = 0.534 ns ( 15.22 % )
-                Info: Total interconnect delay = 2.974 ns ( 84.78 % )
-            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.488 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.131 ns) + CELL(0.448 ns) = 3.488 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In'
-                Info: Total cell delay = 0.448 ns ( 12.84 % )
-                Info: Total interconnect delay = 3.040 ns ( 87.16 % )
-        Info: - Micro clock to output delay of source is 0.176 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest register to register delay is 2.545 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.418 ns) = 0.418 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In'
-        Info: 2: + IC(1.655 ns) + CELL(0.381 ns) = 2.454 ns; Loc. = LCCOMB_X30_Y32_N2; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK~0'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 2.545 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK'
-        Info: Total cell delay = 0.890 ns ( 34.97 % )
-        Info: Total interconnect delay = 1.655 ns ( 65.03 % )
-Info: Slack time is -4.615 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
-    Info: + Largest memory to register requirement is -0.928 ns
-        Info: + Setup relationship between source and destination is 0.145 ns
-            Info: + Latch edge is 0.221 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 0.076 ns
-                Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -0.862 ns
-            Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 7.507 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
-                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 7.507 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-                Info: Total cell delay = 1.084 ns ( 14.44 % )
-                Info: Total interconnect delay = 6.423 ns ( 85.56 % )
-            Info: - Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source memory is 8.369 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.112 ns) + CELL(0.816 ns) = 8.369 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-                Info: Total cell delay = 1.525 ns ( 18.22 % )
-                Info: Total interconnect delay = 6.844 ns ( 81.78 % )
-        Info: - Micro clock to output delay of source is 0.226 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest memory to register delay is 3.687 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
-        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
-        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-        Info: Total cell delay = 2.700 ns ( 73.23 % )
-        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
-Warning: Can't achieve timing requirement Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' along 3741 path(s). See Report window for details.
-Info: No valid register-to-register data paths exist for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]"
-Info: Slack time is -2.673 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC"
-    Info: + Largest pin to register requirement is 0.814 ns
-        Info: + Setup relationship between source and destination is 1.262 ns
-            Info: + Latch edge is 3.955 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 2.693 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 3.537 ns
-            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.537 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.102 ns) + CELL(0.534 ns) = 3.537 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC'
-                Info: Total cell delay = 0.534 ns ( 15.10 % )
-                Info: Total interconnect delay = 3.003 ns ( 84.90 % )
-        Info: - Micro setup delay of destination is -0.015 ns
-        Info: - Max Input delay of pin is 4.0 ns
-    Info: - Longest pin to register delay is 3.487 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
-        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
-        Info: 3: + IC(1.144 ns) + CELL(0.130 ns) = 2.215 ns; Loc. = LCCOMB_X22_Y6_N18; Fanout = 18; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5'
-        Info: 4: + IC(0.241 ns) + CELL(0.130 ns) = 2.586 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 19; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~0'
-        Info: 5: + IC(0.680 ns) + CELL(0.130 ns) = 3.396 ns; Loc. = LCCOMB_X25_Y6_N20; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC~1'
-        Info: 6: + IC(0.000 ns) + CELL(0.091 ns) = 3.487 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC'
-        Info: Total cell delay = 1.422 ns ( 40.78 % )
-        Info: Total interconnect delay = 2.065 ns ( 59.22 % )
-Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' along 86 path(s). See Report window for details.
-Info: Slack time is 2.965 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]"
-    Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits
-    Info: + Largest register to register requirement is 3.604 ns
-        Info: + Setup relationship between source and destination is 3.788 ns
-            Info: + Latch edge is 6.481 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 2.693 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 0.000 ns
-            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.531 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
-            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.531 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest register to register delay is 0.639 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]'
-        Info: 2: + IC(0.297 ns) + CELL(0.342 ns) = 0.639 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]'
-        Info: Total cell delay = 0.342 ns ( 53.52 % )
-        Info: Total interconnect delay = 0.297 ns ( 46.48 % )
-Info: Slack time is 5.299 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]"
-    Info: + Largest register to register requirement is 6.118 ns
-        Info: + Setup relationship between source and destination is 6.313 ns
-            Info: + Latch edge is 10.268 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 3.955 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -0.011 ns
-            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.532 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.097 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.998 ns ( 84.88 % )
-            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]'
-                Info: Total cell delay = 0.534 ns ( 15.07 % )
-                Info: Total interconnect delay = 3.009 ns ( 84.93 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest register to register delay is 0.819 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]'
-        Info: 2: + IC(0.598 ns) + CELL(0.130 ns) = 0.728 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]~feeder'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.819 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]'
-        Info: Total cell delay = 0.221 ns ( 26.98 % )
-        Info: Total interconnect delay = 0.598 ns ( 73.02 % )
-Info: Slack time is 1.672 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI"
-    Info: + Largest register to register requirement is 5.308 ns
-        Info: + Setup relationship between source and destination is 5.999 ns
-            Info: + Latch edge is 8.690 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 2.691 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -0.064 ns
-            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.487 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl'
-                Info: 3: + IC(1.098 ns) + CELL(0.488 ns) = 3.487 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI'
-                Info: Total cell delay = 0.488 ns ( 13.99 % )
-                Info: Total interconnect delay = 2.999 ns ( 86.01 % )
-            Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.551 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
-                Info: 3: + IC(1.116 ns) + CELL(0.534 ns) = 3.551 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]'
-                Info: Total cell delay = 0.534 ns ( 15.04 % )
-                Info: Total interconnect delay = 3.017 ns ( 84.96 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: - Micro setup delay of destination is 0.428 ns
-    Info: - Longest register to register delay is 3.636 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]'
-        Info: 2: + IC(0.330 ns) + CELL(0.367 ns) = 0.697 ns; Loc. = LCCOMB_X22_Y2_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[34]~59'
-        Info: 3: + IC(2.591 ns) + CELL(0.348 ns) = 3.636 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI'
-        Info: Total cell delay = 0.715 ns ( 19.66 % )
-        Info: Total interconnect delay = 2.921 ns ( 80.34 % )
-Info: Slack time is -1.712 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ"
-    Info: + Largest pin to register requirement is 1.118 ns
-        Info: + Setup relationship between source and destination is 1.576 ns
-            Info: + Latch edge is 2.691 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 1.115 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 3.527 ns
-            Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.527 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
-                Info: 3: + IC(1.092 ns) + CELL(0.534 ns) = 3.527 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ'
-                Info: Total cell delay = 0.534 ns ( 15.14 % )
-                Info: Total interconnect delay = 2.993 ns ( 84.86 % )
-        Info: - Micro setup delay of destination is -0.015 ns
-        Info: - Max Input delay of pin is 4.0 ns
-    Info: - Longest pin to register delay is 2.830 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
-        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
-        Info: 3: + IC(1.138 ns) + CELL(0.130 ns) = 2.209 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 7; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL'
-        Info: 4: + IC(0.400 ns) + CELL(0.130 ns) = 2.739 ns; Loc. = LCCOMB_X21_Y6_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~2'
-        Info: 5: + IC(0.000 ns) + CELL(0.091 ns) = 2.830 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ'
-        Info: Total cell delay = 1.292 ns ( 45.65 % )
-        Info: Total interconnect delay = 1.538 ns ( 54.35 % )
-Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' along 29 path(s). See Report window for details.
-Info: Slack time is -4.294 ns for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
-    Info: + Largest memory to register requirement is -0.607 ns
-        Info: + Setup relationship between source and destination is 0.272 ns
-            Info: + Latch edge is 0.493 ns
-                Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 0.221 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -0.668 ns
-            Info: + Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.082 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 8.082 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-                Info: Total cell delay = 1.243 ns ( 15.38 % )
-                Info: Total interconnect delay = 6.839 ns ( 84.62 % )
-            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
-                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-                Info: Total cell delay = 1.680 ns ( 19.20 % )
-                Info: Total interconnect delay = 7.070 ns ( 80.80 % )
-        Info: - Micro clock to output delay of source is 0.226 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest memory to register delay is 3.687 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
-        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
-        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-        Info: Total cell delay = 2.700 ns ( 73.23 % )
-        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
-Warning: Can't achieve timing requirement Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' along 3741 path(s). See Report window for details.
-Info: Slack time is -5.966 ns for clock "CLK33M" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]"
-    Info: + Largest memory to register requirement is -2.279 ns
-        Info: + Setup relationship between source and destination is 0.196 ns
-            Info: + Latch edge is 0.278 ns
-                Info: Clock period of Destination clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 0.082 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is -2.264 ns
-            Info: + Shortest clock path from clock "CLK33M" to destination register is 6.486 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
-                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
-                Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
-                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 6.486 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-                Info: Total cell delay = 2.006 ns ( 30.93 % )
-                Info: Total interconnect delay = 4.480 ns ( 69.07 % )
-            Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
-                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-                Info: Total cell delay = 1.680 ns ( 19.20 % )
-                Info: Total interconnect delay = 7.070 ns ( 80.80 % )
-        Info: - Micro clock to output delay of source is 0.226 ns
-        Info: - Micro setup delay of destination is -0.015 ns
-    Info: - Longest memory to register delay is 3.687 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0'
-        Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]'
-        Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67'
-        Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]'
-        Info: Total cell delay = 2.700 ns ( 73.23 % )
-        Info: Total interconnect delay = 0.987 ns ( 26.77 % )
-Warning: Can't achieve timing requirement Clock Setup: 'CLK33M' along 3741 path(s). See Report window for details.
-Info: Slack time is -4.261 ns for clock "MAIN_CLK" between source pin "FB_ALE" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7"
-    Info: + Largest pin to register requirement is 0.057 ns
-        Info: + Setup relationship between source and destination is 1.094 ns
-            Info: + Latch edge is 7.575 ns
-                Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-            Info: - Launch edge is 6.481 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-        Info: + Largest clock skew is 2.948 ns
-            Info: + Shortest clock path from clock "MAIN_CLK" to destination register is 2.948 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-                Info: 3: + IC(1.433 ns) + CELL(0.534 ns) = 2.948 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7'
-                Info: Total cell delay = 1.515 ns ( 51.39 % )
-                Info: Total interconnect delay = 1.433 ns ( 48.61 % )
-        Info: - Micro setup delay of destination is -0.015 ns
-        Info: - Max Input delay of pin is 4.0 ns
-    Info: - Longest pin to register delay is 4.318 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
-        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
-        Info: 3: + IC(1.524 ns) + CELL(0.130 ns) = 2.595 ns; Loc. = LCCOMB_X23_Y7_N20; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2'
-        Info: 4: + IC(0.212 ns) + CELL(0.130 ns) = 2.937 ns; Loc. = LCCOMB_X23_Y7_N18; Fanout = 52; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1'
-        Info: 5: + IC(0.445 ns) + CELL(0.130 ns) = 3.512 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 4; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~2'
-        Info: 6: + IC(0.235 ns) + CELL(0.130 ns) = 3.877 ns; Loc. = LCCOMB_X22_Y7_N28; Fanout = 3; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~4'
-        Info: 7: + IC(0.220 ns) + CELL(0.130 ns) = 4.227 ns; Loc. = LCCOMB_X22_Y7_N16; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7~0'
-        Info: 8: + IC(0.000 ns) + CELL(0.091 ns) = 4.318 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7'
-        Info: Total cell delay = 1.682 ns ( 38.95 % )
-        Info: Total interconnect delay = 2.636 ns ( 61.05 % )
-Warning: Can't achieve timing requirement Clock Setup: 'MAIN_CLK' along 27347 path(s). See Report window for details.
-Info: Minimum slack time is 825 ps for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]"
-    Info: + Shortest register to register delay is 0.783 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
-        Info: 2: + IC(0.323 ns) + CELL(0.369 ns) = 0.692 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.783 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
-        Info: Total cell delay = 0.460 ns ( 58.75 % )
-        Info: Total interconnect delay = 0.323 ns ( 41.25 % )
-    Info: - Smallest register to register requirement is -0.042 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -9.578 ns
-                Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -9.578 ns
-                Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with  offset of -9.578 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
-            Info: - Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.531 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-                Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]'
-                Info: Total cell delay = 0.534 ns ( 15.12 % )
-                Info: Total interconnect delay = 2.997 ns ( 84.88 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is 564 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]"
-    Info: + Shortest register to register delay is 0.522 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-        Info: 2: + IC(0.301 ns) + CELL(0.130 ns) = 0.431 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-        Info: Total cell delay = 0.221 ns ( 42.34 % )
-        Info: Total interconnect delay = 0.301 ns ( 57.66 % )
-    Info: - Smallest register to register requirement is -0.042 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -1.864 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -1.864 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-                Info: Total cell delay = 0.534 ns ( 15.16 % )
-                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
-            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]'
-                Info: Total cell delay = 0.534 ns ( 15.16 % )
-                Info: Total interconnect delay = 2.988 ns ( 84.84 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is 502 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1"
-    Info: + Shortest register to register delay is 0.460 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y28_N4; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector77~1'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
-        Info: Total cell delay = 0.460 ns ( 100.00 % )
-    Info: - Smallest register to register requirement is -0.042 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -1.864 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -1.864 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.526 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
-                Info: Total cell delay = 0.534 ns ( 15.14 % )
-                Info: Total interconnect delay = 2.992 ns ( 84.86 % )
-            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.526 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1'
-                Info: Total cell delay = 0.534 ns ( 15.14 % )
-                Info: Total interconnect delay = 2.992 ns ( 84.86 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is -454 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
-    Info: + Shortest register to register delay is 0.460 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: Total cell delay = 0.460 ns ( 100.00 % )
-    Info: - Smallest register to register requirement is 0.914 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -1.864 ns
-                Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -1.864 ns
-                Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with  offset of -1.864 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.956 ns
-            Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 8.469 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0'
-                Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 8.469 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 1.398 ns ( 16.51 % )
-                Info: Total interconnect delay = 7.071 ns ( 83.49 % )
-            Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source register is 7.513 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-                Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
-                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 7.513 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 1.084 ns ( 14.43 % )
-                Info: Total interconnect delay = 6.429 ns ( 85.57 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Warning: Can't achieve minimum setup and hold requirement altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] along 26 path(s). See Report window for details.
-Info: Minimum slack time is 502 ps for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]"
-    Info: + Shortest register to register delay is 0.460 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X45_Y15_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]~3'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
-        Info: Total cell delay = 0.460 ns ( 100.00 % )
-    Info: - Smallest register to register requirement is -0.042 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -3.620 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -3.620 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.559 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
-                Info: Total cell delay = 0.534 ns ( 15.00 % )
-                Info: Total interconnect delay = 3.025 ns ( 85.00 % )
-            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.559 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]'
-                Info: Total cell delay = 0.534 ns ( 15.00 % )
-                Info: Total interconnect delay = 3.025 ns ( 85.00 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is 4.336 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]"
-    Info: + Shortest register to register delay is 0.507 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]'
-        Info: 2: + IC(0.286 ns) + CELL(0.130 ns) = 0.416 ns; Loc. = LCCOMB_X66_Y14_N30; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]~feeder'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.507 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]'
-        Info: Total cell delay = 0.221 ns ( 43.59 % )
-        Info: Total interconnect delay = 0.286 ns ( 56.41 % )
-    Info: - Smallest register to register requirement is -3.829 ns
-        Info: + Hold relationship between source and destination is -3.787 ns
-            Info: + Latch edge is -1.094 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with  offset of -1.094 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is 2.693 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.538 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]'
-                Info: Total cell delay = 0.534 ns ( 15.09 % )
-                Info: Total interconnect delay = 3.004 ns ( 84.91 % )
-            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.538 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl'
-                Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]'
-                Info: Total cell delay = 0.534 ns ( 15.09 % )
-                Info: Total interconnect delay = 3.004 ns ( 84.91 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is 1.825 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]"
-    Info: + Shortest register to register delay is 0.508 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]'
-        Info: 2: + IC(0.287 ns) + CELL(0.130 ns) = 0.417 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]~feeder'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.508 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]'
-        Info: Total cell delay = 0.221 ns ( 43.50 % )
-        Info: Total interconnect delay = 0.287 ns ( 56.50 % )
-    Info: - Smallest register to register requirement is -1.317 ns
-        Info: + Hold relationship between source and destination is -1.262 ns
-            Info: + Latch edge is 2.693 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with  offset of 2.693 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is 3.955 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with  offset of -3.620 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is -0.013 ns
-            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.530 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl'
-                Info: 3: + IC(1.095 ns) + CELL(0.534 ns) = 3.530 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]'
-                Info: Total cell delay = 0.534 ns ( 15.13 % )
-                Info: Total interconnect delay = 2.996 ns ( 84.87 % )
-            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]'
-                Info: Total cell delay = 0.534 ns ( 15.07 % )
-                Info: Total interconnect delay = 3.009 ns ( 84.93 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is 3.263 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO"
-    Info: + Shortest register to register delay is 1.570 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y2_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[29]~4'
-        Info: 3: + IC(0.737 ns) + CELL(0.464 ns) = 1.570 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO'
-        Info: Total cell delay = 0.833 ns ( 53.06 % )
-        Info: Total interconnect delay = 0.737 ns ( 46.94 % )
-    Info: - Smallest register to register requirement is -1.693 ns
-        Info: + Hold relationship between source and destination is -1.576 ns
-            Info: + Latch edge is 1.115 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with  offset of 1.115 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is 2.691 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is -0.019 ns
-            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.543 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl'
-                Info: 3: + IC(1.154 ns) + CELL(0.488 ns) = 3.543 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO'
-                Info: Total cell delay = 0.488 ns ( 13.77 % )
-                Info: Total interconnect delay = 3.055 ns ( 86.23 % )
-            Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.562 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
-                Info: 3: + IC(1.127 ns) + CELL(0.534 ns) = 3.562 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]'
-                Info: Total cell delay = 0.534 ns ( 14.99 % )
-                Info: Total interconnect delay = 3.028 ns ( 85.01 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.101 ns
-Info: Minimum slack time is 2.664 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]"
-    Info: + Shortest pin to register delay is 2.216 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE'
-        Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input'
-        Info: 3: + IC(0.929 ns) + CELL(0.346 ns) = 2.216 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]'
-        Info: Total cell delay = 1.287 ns ( 58.08 % )
-        Info: Total interconnect delay = 0.929 ns ( 41.92 % )
-    Info: - Smallest pin to register requirement is -0.448 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -4.884 ns
-                Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -4.884 ns
-                Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with  offset of -4.884 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 3.500 ns
-            Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.500 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-                Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl'
-                Info: 3: + IC(1.151 ns) + CELL(0.448 ns) = 3.500 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]'
-                Info: Total cell delay = 0.448 ns ( 12.80 % )
-                Info: Total interconnect delay = 3.052 ns ( 87.20 % )
-        Info: + Micro hold delay of destination is 0.052 ns
-        Info: - Min Input delay of pin is 4.0 ns
-Info: Minimum slack time is 502 ps for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
-    Info: + Shortest register to register delay is 0.460 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: Total cell delay = 0.460 ns ( 100.00 % )
-    Info: - Smallest register to register requirement is -0.042 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is -2.843 ns
-                Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is -2.843 ns
-                Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with  offset of -2.843 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 0.000 ns
-            Info: + Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.088 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 1.243 ns ( 15.37 % )
-                Info: Total interconnect delay = 6.845 ns ( 84.63 % )
-            Info: - Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source register is 8.088 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-                Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl'
-                Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 1.243 ns ( 15.37 % )
-                Info: Total interconnect delay = 6.845 ns ( 84.63 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Info: Minimum slack time is -687 ps for clock "CLK33M" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]"
-    Info: + Shortest register to register delay is 0.460 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-        Info: Total cell delay = 0.460 ns ( 100.00 % )
-    Info: - Smallest register to register requirement is 1.147 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is 0.000 ns
-                Info: Clock period of Destination clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is 0.000 ns
-                Info: Clock period of Source clock "CLK33M" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 1.189 ns
-            Info: + Longest clock path from clock "CLK33M" to destination register is 7.681 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
-                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
-                Info: 3: + IC(1.161 ns) + CELL(0.733 ns) = 2.812 ns; Loc. = FF_X33_Y18_N25; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M'
-                Info: 4: + IC(0.852 ns) + CELL(0.311 ns) = 3.975 ns; Loc. = LCCOMB_X26_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4'
-                Info: 5: + IC(0.197 ns) + CELL(0.130 ns) = 4.302 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.034 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 7.681 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 2.626 ns ( 34.19 % )
-                Info: Total interconnect delay = 5.055 ns ( 65.81 % )
-            Info: - Shortest clock path from clock "CLK33M" to source register is 6.492 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M'
-                Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input'
-                Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3'
-                Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 6.492 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]'
-                Info: Total cell delay = 2.006 ns ( 30.90 % )
-                Info: Total interconnect delay = 4.486 ns ( 69.10 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Warning: Can't achieve minimum setup and hold requirement CLK33M along 26 path(s). See Report window for details.
-Info: Minimum slack time is -3.786 ns for clock "MAIN_CLK" between source register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]"
-    Info: + Shortest register to register delay is 1.930 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]'
-        Info: 2: + IC(1.597 ns) + CELL(0.242 ns) = 1.839 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]~1'
-        Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 1.930 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]'
-        Info: Total cell delay = 0.333 ns ( 17.25 % )
-        Info: Total interconnect delay = 1.597 ns ( 82.75 % )
-    Info: - Smallest register to register requirement is 5.716 ns
-        Info: + Hold relationship between source and destination is 0.000 ns
-            Info: + Latch edge is 0.000 ns
-                Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Destination register is 1
-                Info: Multicycle Hold factor for Destination register is 1
-            Info: - Launch edge is 0.000 ns
-                Info: Clock period of Source clock "MAIN_CLK" is 30.303 ns with  offset of 0.000 ns and duty cycle of 50
-                Info: Multicycle Setup factor for Source register is 1
-                Info: Multicycle Hold factor for Source register is 1
-        Info: + Smallest clock skew is 5.758 ns
-            Info: + Longest clock path from clock "MAIN_CLK" to destination register is 8.630 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-                Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]'
-                Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-                Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-                Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.988 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl'
-                Info: 7: + IC(1.108 ns) + CELL(0.534 ns) = 8.630 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]'
-                Info: Total cell delay = 2.858 ns ( 33.12 % )
-                Info: Total interconnect delay = 5.772 ns ( 66.88 % )
-            Info: - Shortest clock path from clock "MAIN_CLK" to source register is 2.872 ns
-                Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-                Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-                Info: 3: + IC(1.357 ns) + CELL(0.534 ns) = 2.872 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]'
-                Info: Total cell delay = 1.515 ns ( 52.75 % )
-                Info: Total interconnect delay = 1.357 ns ( 47.25 % )
-        Info: - Micro clock to output delay of source is 0.199 ns
-        Info: + Micro hold delay of destination is 0.157 ns
-Warning: Can't achieve minimum setup and hold requirement MAIN_CLK along 108 path(s). See Report window for details.
-Warning: Can't achieve timing requirement tsu along 6867 path(s). See Report window for details.
-Info: Slack time is -4.528 ns for clock "MAIN_CLK" between source clock "MAIN_CLK" and destination register "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state"
-    Info: + tsu requirement for source pin and destination register is 1.000 ns
-    Info: - tsu from clock to input pin is 5.528 ns
-        Info: + Longest clock to register delay is 8.706 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-            Info: 3: + IC(4.109 ns) + CELL(0.869 ns) = 5.959 ns; Loc. = PLL_2; Fanout = 4; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|scandone'
-            Info: 4: + IC(1.722 ns) + CELL(0.130 ns) = 7.811 ns; Loc. = LCCOMB_X21_Y26_N18; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~0'
-            Info: 5: + IC(0.198 ns) + CELL(0.130 ns) = 8.139 ns; Loc. = LCCOMB_X21_Y26_N28; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~1'
-            Info: 6: + IC(0.346 ns) + CELL(0.130 ns) = 8.615 ns; Loc. = LCCOMB_X22_Y26_N16; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~2'
-            Info: 7: + IC(0.000 ns) + CELL(0.091 ns) = 8.706 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state'
-            Info: Total cell delay = 2.331 ns ( 26.77 % )
-            Info: Total interconnect delay = 6.375 ns ( 73.23 % )
-        Info: + Micro setup delay of destination is -0.015 ns
-        Info: - Shortest clock path from clock "MAIN_CLK" to destination register is 3.163 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-            Info: 3: + IC(1.648 ns) + CELL(0.534 ns) = 3.163 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state'
-            Info: Total cell delay = 1.515 ns ( 47.90 % )
-            Info: Total interconnect delay = 1.648 ns ( 52.10 % )
-Warning: Can't achieve timing requirement tco along 4976 path(s). See Report window for details.
-Info: Slack time is -14.84 ns for clock "MAIN_CLK" between source register "interrupt_handler:nobody|INT_LATCH[8]" and destination pin "nIRQ[5]"
-    Info: + tco requirement for source register and destination pin is 1.000 ns
-    Info: - tco from clock to output pin is 15.840 ns
-        Info: + Longest clock path from clock "MAIN_CLK" to source register is 9.460 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-            Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]'
-            Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1'
-            Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK'
-            Info: 6: + IC(1.232 ns) + CELL(0.733 ns) = 7.221 ns; Loc. = FF_X18_Y15_N21; Fanout = 5; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-            Info: 7: + IC(0.716 ns) + CELL(0.308 ns) = 8.245 ns; Loc. = LCCOMB_X15_Y15_N6; Fanout = 1; COMB Node = 'interrupt_handler:nobody|INT_LATCH[8]~19'
-            Info: 8: + IC(0.681 ns) + CELL(0.534 ns) = 9.460 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]'
-            Info: Total cell delay = 3.899 ns ( 41.22 % )
-            Info: Total interconnect delay = 5.561 ns ( 58.78 % )
-        Info: + Micro clock to output delay of source is 0.199 ns
-        Info: + Longest register to pin delay is 6.181 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]'
-            Info: 2: + IC(0.325 ns) + CELL(0.241 ns) = 0.566 ns; Loc. = LCCOMB_X16_Y12_N20; Fanout = 1; COMB Node = 'interrupt_handler:nobody|_~17'
-            Info: 3: + IC(0.198 ns) + CELL(0.130 ns) = 0.894 ns; Loc. = LCCOMB_X16_Y12_N22; Fanout = 1; COMB Node = 'interrupt_handler:nobody|nIRQ[5]'
-            Info: 4: + IC(1.158 ns) + CELL(4.129 ns) = 6.181 ns; Loc. = IOOBUF_X0_Y12_N16; Fanout = 1; COMB Node = 'nIRQ[5]~output'
-            Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 6.181 ns; Loc. = PIN_P5; Fanout = 0; PIN Node = 'nIRQ[5]'
-            Info: Total cell delay = 4.500 ns ( 72.80 % )
-            Info: Total interconnect delay = 1.681 ns ( 27.20 % )
-Info: Slack time is -11.944 ns between source pin "nFB_CS1" and destination pin "FB_AD[18]"
-    Info: + Longest pin to pin requirement is 1.000 ns
-    Info: - Longest pin to pin delay is 12.944 ns
-        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T8; Fanout = 1; PIN Node = 'nFB_CS1'
-        Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X14_Y0_N29; Fanout = 59; COMB Node = 'nFB_CS1~input'
-        Info: 3: + IC(1.591 ns) + CELL(0.241 ns) = 2.750 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 68; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1'
-        Info: 4: + IC(0.915 ns) + CELL(0.130 ns) = 3.795 ns; Loc. = LCCOMB_X29_Y10_N14; Fanout = 12; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB_CS'
-        Info: 5: + IC(0.302 ns) + CELL(0.342 ns) = 4.439 ns; Loc. = LCCOMB_X29_Y10_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~44'
-        Info: 6: + IC(0.648 ns) + CELL(0.243 ns) = 5.330 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~48'
-        Info: 7: + IC(0.807 ns) + CELL(0.243 ns) = 6.380 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~55'
-        Info: 8: + IC(0.200 ns) + CELL(0.130 ns) = 6.710 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5'
-        Info: 9: + IC(1.088 ns) + CELL(0.242 ns) = 8.040 ns; Loc. = LCCOMB_X21_Y14_N4; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180'
-        Info: 10: + IC(0.876 ns) + CELL(4.028 ns) = 12.944 ns; Loc. = IOOBUF_X20_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[18]~output'
-        Info: 11: + IC(0.000 ns) + CELL(0.000 ns) = 12.944 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'FB_AD[18]'
-        Info: Total cell delay = 6.517 ns ( 50.35 % )
-        Info: Total interconnect delay = 6.427 ns ( 49.65 % )
-Warning: Can't achieve timing requirement tpd along 514 path(s). See Report window for details.
-Warning: Can't achieve timing requirement th along 117 path(s). See Report window for details.
-Info: Minimum slack time is -401 ps for clock "MAIN_CLK" between source pin "FB_AD[25]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]"
-    Info: + th requirement for source pin and destination register is 1.000 ns
-    Info: - th from clock to input pin is 1.401 ns
-        Info: + Longest clock path from clock "MAIN_CLK" to destination register is 4.679 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK'
-            Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input'
-            Info: 3: + IC(3.164 ns) + CELL(0.534 ns) = 4.679 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]'
-            Info: Total cell delay = 1.515 ns ( 32.38 % )
-            Info: Total interconnect delay = 3.164 ns ( 67.62 % )
-        Info: + Micro hold delay of destination is 0.157 ns
-        Info: - Shortest pin to register delay is 3.435 ns
-            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'FB_AD[25]'
-            Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X27_Y0_N8; Fanout = 59; COMB Node = 'FB_AD[25]~input'
-            Info: 3: + IC(2.175 ns) + CELL(0.342 ns) = 3.435 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]'
-            Info: Total cell delay = 1.260 ns ( 36.68 % )
-            Info: Total interconnect delay = 2.175 ns ( 63.32 % )
-Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.
-Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
-Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 65 warnings
-    Info: Peak virtual memory: 238 megabytes
-    Info: Processing ended: Wed Dec 15 02:25:23 2010
-    Info: Elapsed time: 00:00:09
-    Info: Total CPU time (on all processors): 00:00:11
-
-
diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
index 219f117..2b4b381 100644
--- a/FPGA_by_Fredi/firebee1.tan.summary
+++ b/FPGA_by_Fredi/firebee1.tan.summary
@@ -3,203 +3,183 @@ Timing Analyzer Summary
 --------------------------------------------------------------------------------------
 
 Type           : Worst-case tsu
-Slack          : -4.528 ns
+Slack          : -10.339 ns
 Required Time  : 1.000 ns
-Actual Time    : 5.528 ns
-From           : MAIN_CLK
-To             : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state
+Actual Time    : 11.339 ns
+From           : FB_SIZE1
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2]
 From Clock     : --
 To Clock       : MAIN_CLK
-Failed Paths   : 6867
+Failed Paths   : 10192
 
 Type           : Worst-case tco
-Slack          : -14.840 ns
+Slack          : -14.371 ns
 Required Time  : 1.000 ns
-Actual Time    : 15.840 ns
-From           : interrupt_handler:nobody|INT_LATCH[8]
-To             : nIRQ[5]
+Actual Time    : 15.371 ns
+From           : interrupt_handler:nobody|RTC_ADR[0]
+To             : FB_AD[18]
 From Clock     : MAIN_CLK
 To Clock       : --
-Failed Paths   : 4976
+Failed Paths   : 5354
 
 Type           : Worst-case tpd
-Slack          : -11.944 ns
+Slack          : -13.264 ns
 Required Time  : 1.000 ns
-Actual Time    : 12.944 ns
+Actual Time    : 14.264 ns
 From           : nFB_CS1
 To             : FB_AD[18]
 From Clock     : --
 To Clock       : --
-Failed Paths   : 514
+Failed Paths   : 538
 
 Type           : Worst-case th
-Slack          : -0.401 ns
+Slack          : -0.110 ns
 Required Time  : 1.000 ns
-Actual Time    : 1.401 ns
-From           : FB_AD[25]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]
+Actual Time    : 1.110 ns
+From           : VD[31]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
 From Clock     : --
 To Clock       : MAIN_CLK
-Failed Paths   : 117
+Failed Paths   : 2
 
-Type           : Clock Setup: 'CLK33M'
-Slack          : -5.966 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
+Slack          : -7.918 ns
+Required Time  : 25.00 MHz ( period = 39.999 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-To Clock       : CLK33M
-Failed Paths   : 3741
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-Slack          : -4.615 ns
-Required Time  : 24.98 MHz ( period = 40.033 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-Failed Paths   : 3741
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
+From Clock     : MAIN_CLK
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+Failed Paths   : 4748
 
 Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : -4.294 ns
-Required Time  : 95.92 MHz ( period = 10.425 ns )
+Slack          : -6.799 ns
+Required Time  : 96.01 MHz ( period = 10.416 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0
-To             : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
+From Clock     : MAIN_CLK
 To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 3741
+Failed Paths   : 4694
 
 Type           : Clock Setup: 'MAIN_CLK'
-Slack          : -4.261 ns
+Slack          : -5.955 ns
 Required Time  : 33.00 MHz ( period = 30.303 ns )
 Actual Time    : N/A
-From           : FB_ALE
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|nBLANK
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
 To Clock       : MAIN_CLK
-Failed Paths   : 27347
+Failed Paths   : 41276
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : -2.673 ns
+Slack          : -5.567 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : FB_ALE
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 86
+Failed Paths   : 129
+
+Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
+Slack          : -4.614 ns
+Required Time  : 16.00 MHz ( period = 62.499 ns )
+Actual Time    : N/A
+From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+Failed Paths   : 2882
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : -1.712 ns
+Slack          : -3.520 ns
 Required Time  : 66.00 MHz ( period = 15.151 ns )
 Actual Time    : N/A
 From           : FB_ALE
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
 Failed Paths   : 29
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 1.672 ns
+Slack          : 2.410 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR
+To             : Video:Fredi_Aschwanden|inst90~_Duplicate_2
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
 Failed Paths   : 0
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 2.965 ns
+Slack          : 2.966 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 Failed Paths   : 0
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 5.299 ns
+Slack          : 5.144 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
 Failed Paths   : 0
 
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
-Slack          : 28.590 ns
-Required Time  : 15.99 MHz ( period = 62.552 ns )
-Actual Time    : 186.15 MHz ( period = 5.372 ns )
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-Slack          : 498.663 ns
-Required Time  : 2.00 MHz ( period = 500.416 ns )
-Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-Slack          : 1997.239 ns
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
+Slack          : 26.171 ns
 Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : 362.45 MHz ( period = 2.759 ns )
-From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]
-To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[0]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
+From Clock     : MAIN_CLK
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
 Failed Paths   : 0
 
 Type           : Clock Hold: 'MAIN_CLK'
-Slack          : -3.786 ns
+Slack          : -3.299 ns
 Required Time  : 33.00 MHz ( period = 30.303 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2]
 From Clock     : MAIN_CLK
 To Clock       : MAIN_CLK
-Failed Paths   : 108
+Failed Paths   : 529
 
-Type           : Clock Hold: 'CLK33M'
-Slack          : -0.687 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
+Slack          : -0.640 ns
+Required Time  : 25.00 MHz ( period = 39.999 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
 To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-From Clock     : CLK33M
-To Clock       : CLK33M
-Failed Paths   : 26
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+Failed Paths   : 33
 
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]'
-Slack          : -0.454 ns
-Required Time  : 24.98 MHz ( period = 40.033 ns )
+Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
+Slack          : 0.453 ns
+Required Time  : 16.00 MHz ( period = 62.499 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]
-Failed Paths   : 26
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[6]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
+From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+Failed Paths   : 0
 
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]'
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
 Slack          : 0.502 ns
-Required Time  : 15.99 MHz ( period = 62.552 ns )
+Required Time  : 0.50 MHz ( period = 1999.998 ns )
 Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
 Failed Paths   : 0
 
 Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
@@ -214,7 +194,7 @@ Failed Paths   : 0
 
 Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
 Slack          : 0.502 ns
-Required Time  : 95.92 MHz ( period = 10.425 ns )
+Required Time  : 96.01 MHz ( period = 10.416 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
 To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
@@ -222,62 +202,42 @@ From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generat
 To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
 Failed Paths   : 0
 
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]'
-Slack          : 0.564 ns
-Required Time  : 2.00 MHz ( period = 500.416 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]'
-Slack          : 0.825 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
-To             : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 1.825 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
 Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : 2.664 ns
+Slack          : 1.775 ns
 Required Time  : 66.00 MHz ( period = 15.151 ns )
 Actual Time    : N/A
-From           : FB_ALE
-To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
 Failed Paths   : 0
 
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 3.263 ns
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 1.829 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : 2.585 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|inst90~_Duplicate_4
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
 Failed Paths   : 0
 
 Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 4.336 ns
+Slack          : 4.335 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 Failed Paths   : 0
@@ -290,7 +250,7 @@ From           :
 To             : 
 From Clock     : 
 To Clock       : 
-Failed Paths   : 51319
+Failed Paths   : 70406
 
 --------------------------------------------------------------------------------------
 
diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws
deleted file mode 100644
index 89bdcec..0000000
--- a/FPGA_by_Fredi/firebeei1.qws
+++ /dev/null
@@ -1,27 +0,0 @@
-[ProjectWorkspace]
-ptn_Child1=Frames
-[ProjectWorkspace.Frames]
-ptn_Child1=ChildFrames
-[ProjectWorkspace.Frames.ChildFrames]
-ptn_Child1=Document-0
-ptn_Child2=Document-1
-ptn_Child3=Document-2
-ptn_Child4=Document-3
-[ProjectWorkspace.Frames.ChildFrames.Document-0]
-ptn_Child1=ViewFrame-0
-[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
-DocPathName=firebee1.bdf
-DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
-IsChildFrameDetached=False
-IsActiveChildFrame=False
-ptn_Child1=StateMap
-[ProjectWorkspace.Frames.ChildFrames.Document-1]
-ptn_Child1=ViewFrame-0
-[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
-DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
-DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
-IsChildFrameDetached=False
-IsActiveChildFrame=False
-ptn_Child1=StateMap
-[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
-AFC_IN_REPORT=False
diff --git a/FPGA_by_Fredi/incremental_db/README b/FPGA_by_Fredi/incremental_db/README
new file mode 100644
index 0000000..6191fbe
--- /dev/null
+++ b/FPGA_by_Fredi/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb
new file mode 100644
index 0000000000000000000000000000000000000000..02d4502eef5a779b397c54db97384993da1e0770
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp
new file mode 100644
index 0000000000000000000000000000000000000000..b1c67d625638bb473b681fa4acb00be38889ece3
GIT binary patch
literal 33
mcmZ3(&&U7*6?3%pJax1>&--+q_tkmeb=JGlkg@C*Cl3Idx(b*8

literal 0
HcmV?d00001

diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb
new file mode 100644
index 0000000000000000000000000000000000000000..541ae5c20da7f62151053d981e4ee68d40bbd123
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt
new file mode 100644
index 0000000000000000000000000000000000000000..8376a16a777965d247e2be94522a44af87095a22
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
new file mode 100644
index 0000000..4107b3a
--- /dev/null
+++ b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
@@ -0,0 +1,5 @@
+v1
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb
new file mode 100644
index 0000000000000000000000000000000000000000..15c6a52d2b93c211e2cacdf577b04adbd78ac5e2
GIT binary patch
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.re.rcfdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.re.rcfdb
new file mode 100644
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.dpi b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.dpi
new file mode 100644
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.hdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.hdb
new file mode 100644
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.kpt b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.kpt
new file mode 100644
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm
new file mode 100644
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diff --git a/FPGA_by_Fredi/lpm_counter1.bsf b/FPGA_by_Fredi/lpm_counter1.bsf
new file mode 100644
index 0000000..1d5fb86
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_counter1" (rect 23 2 138 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 61 31 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 24 57 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[11..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
+		(text "q[11..0]" (rect 81 32 125 48)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "cout" (rect 0 0 29 16)(font "Arial" (font_size 8)))
+		(text "cout" (rect 100 48 125 64)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 1))
+	)
+	(drawing
+		(text "up counter" (rect 70 18 122 32)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_counter1.cmp b/FPGA_by_Fredi/lpm_counter1.cmp
new file mode 100644
index 0000000..2e72417
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_counter1
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		cout		: OUT STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_counter1.inc b/FPGA_by_Fredi/lpm_counter1.inc
new file mode 100644
index 0000000..59d19df
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_counter1 
+(
+	clock
+)
+
+RETURNS (
+	cout,
+	q[11..0]
+);
diff --git a/FPGA_by_Fredi/lpm_counter1.qip b/FPGA_by_Fredi/lpm_counter1.qip
new file mode 100644
index 0000000..2bcc1a0
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"]
diff --git a/FPGA_by_Fredi/lpm_counter1.tdf b/FPGA_by_Fredi/lpm_counter1.tdf
new file mode 100644
index 0000000..46924c3
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_counter1.tdf
@@ -0,0 +1,103 @@
+-- megafunction wizard: %LPM_COUNTER%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_counter 
+
+-- ============================================================
+-- File Name: lpm_counter1.tdf
+-- Megafunction Name(s):
+-- 			lpm_counter
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_counter.inc";
+
+
+
+SUBDESIGN lpm_counter1
+(
+	clock	 : INPUT;
+	cout	 : OUTPUT;
+	q[11..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_counter_component : lpm_counter WITH (
+			LPM_DIRECTION = "UP",
+			LPM_PORT_UPDOWN = "PORT_UNUSED",
+			LPM_TYPE = "LPM_COUNTER",
+			LPM_WIDTH = 12
+			);
+
+BEGIN
+
+	cout = lpm_counter_component.cout;
+	q[11..0] = lpm_counter_component.q[11..0];
+	lpm_counter_component.clock = clock;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
+-- Retrieval info: PRIVATE: Direction NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "12"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
+-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL q[11..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
+-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.tdf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_counter1_wave0.jpg b/FPGA_by_Fredi/lpm_counter1_wave0.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..8298f97b574e500d7a35fc7591d7504c9290cd03
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diff --git a/FPGA_by_Fredi/lpm_counter1_waveforms.html b/FPGA_by_Fredi/lpm_counter1_waveforms.html
index cea3320..a353967 100644
--- a/FPGA_by_Fredi/lpm_counter1_waveforms.html
+++ b/FPGA_by_Fredi/lpm_counter1_waveforms.html
@@ -1,16 +1,13 @@
 <html>
 <head>
-<title>Sample Waveforms for lpm_counter1.vhd </title>
+<title>Sample Waveforms for "lpm_counter1.tdf" </title>
 </head>
 <body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_counter1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter. </P>
+<h2><CENTER>Sample behavioral waveforms for design file "lpm_counter1.tdf" </CENTER></h2>
+<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design "lpm_counter1.tdf". The design "lpm_counter1.tdf" is a 12 bit up counter. </P>
 <CENTER><img src=lpm_counter1_wave0.jpg> </CENTER>
 <P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
-<P><FONT size=3></P>
-<CENTER><img src=lpm_counter1_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Wave showing counter cout and/or modulus operation. </CENTER></P>
-<P><FONT size=3>The counter counts till the modulus value 7. </P>
+<P><FONT size=3>The output port cout will be asserted at the completion of count sequence. The ports cin and cout are used to chain multiple counters together. </P>
 <P></P>
 </body>
 </html>
diff --git a/FPGA_by_Fredi/lpm_mux0.bsf b/FPGA_by_Fredi/lpm_mux0.bsf
new file mode 100644
index 0000000..ae881bd
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.bsf
@@ -0,0 +1,1838 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
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+	(text "lpm_mux0" (rect 76 3 160 22)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 4125 31 4140)(font "Arial" ))
+	(port
+		(pt 0 40)
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+		(text "data31x[127..0]" (rect 4 3608 94 3624)(font "Arial" (font_size 8)))
+		(line (pt 0 3624)(pt 104 3624)(line_width 3))
+	)
+	(port
+		(pt 0 3640)
+		(input)
+		(text "data30x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data30x[127..0]" (rect 4 3624 94 3640)(font "Arial" (font_size 8)))
+		(line (pt 0 3640)(pt 104 3640)(line_width 3))
+	)
+	(port
+		(pt 0 3656)
+		(input)
+		(text "data29x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data29x[127..0]" (rect 4 3640 94 3656)(font "Arial" (font_size 8)))
+		(line (pt 0 3656)(pt 104 3656)(line_width 3))
+	)
+	(port
+		(pt 0 3672)
+		(input)
+		(text "data28x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data28x[127..0]" (rect 4 3656 94 3672)(font "Arial" (font_size 8)))
+		(line (pt 0 3672)(pt 104 3672)(line_width 3))
+	)
+	(port
+		(pt 0 3688)
+		(input)
+		(text "data27x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data27x[127..0]" (rect 4 3672 94 3688)(font "Arial" (font_size 8)))
+		(line (pt 0 3688)(pt 104 3688)(line_width 3))
+	)
+	(port
+		(pt 0 3704)
+		(input)
+		(text "data26x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data26x[127..0]" (rect 4 3688 94 3704)(font "Arial" (font_size 8)))
+		(line (pt 0 3704)(pt 104 3704)(line_width 3))
+	)
+	(port
+		(pt 0 3720)
+		(input)
+		(text "data25x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data25x[127..0]" (rect 4 3704 94 3720)(font "Arial" (font_size 8)))
+		(line (pt 0 3720)(pt 104 3720)(line_width 3))
+	)
+	(port
+		(pt 0 3736)
+		(input)
+		(text "data24x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data24x[127..0]" (rect 4 3720 94 3736)(font "Arial" (font_size 8)))
+		(line (pt 0 3736)(pt 104 3736)(line_width 3))
+	)
+	(port
+		(pt 0 3752)
+		(input)
+		(text "data23x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data23x[127..0]" (rect 4 3736 94 3752)(font "Arial" (font_size 8)))
+		(line (pt 0 3752)(pt 104 3752)(line_width 3))
+	)
+	(port
+		(pt 0 3768)
+		(input)
+		(text "data22x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data22x[127..0]" (rect 4 3752 94 3768)(font "Arial" (font_size 8)))
+		(line (pt 0 3768)(pt 104 3768)(line_width 3))
+	)
+	(port
+		(pt 0 3784)
+		(input)
+		(text "data21x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data21x[127..0]" (rect 4 3768 94 3784)(font "Arial" (font_size 8)))
+		(line (pt 0 3784)(pt 104 3784)(line_width 3))
+	)
+	(port
+		(pt 0 3800)
+		(input)
+		(text "data20x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data20x[127..0]" (rect 4 3784 94 3800)(font "Arial" (font_size 8)))
+		(line (pt 0 3800)(pt 104 3800)(line_width 3))
+	)
+	(port
+		(pt 0 3816)
+		(input)
+		(text "data19x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data19x[127..0]" (rect 4 3800 94 3816)(font "Arial" (font_size 8)))
+		(line (pt 0 3816)(pt 104 3816)(line_width 3))
+	)
+	(port
+		(pt 0 3832)
+		(input)
+		(text "data18x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data18x[127..0]" (rect 4 3816 94 3832)(font "Arial" (font_size 8)))
+		(line (pt 0 3832)(pt 104 3832)(line_width 3))
+	)
+	(port
+		(pt 0 3848)
+		(input)
+		(text "data17x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data17x[127..0]" (rect 4 3832 94 3848)(font "Arial" (font_size 8)))
+		(line (pt 0 3848)(pt 104 3848)(line_width 3))
+	)
+	(port
+		(pt 0 3864)
+		(input)
+		(text "data16x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data16x[127..0]" (rect 4 3848 94 3864)(font "Arial" (font_size 8)))
+		(line (pt 0 3864)(pt 104 3864)(line_width 3))
+	)
+	(port
+		(pt 0 3880)
+		(input)
+		(text "data15x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 3864 94 3880)(font "Arial" (font_size 8)))
+		(line (pt 0 3880)(pt 104 3880)(line_width 3))
+	)
+	(port
+		(pt 0 3896)
+		(input)
+		(text "data14x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 3880 94 3896)(font "Arial" (font_size 8)))
+		(line (pt 0 3896)(pt 104 3896)(line_width 3))
+	)
+	(port
+		(pt 0 3912)
+		(input)
+		(text "data13x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 3896 94 3912)(font "Arial" (font_size 8)))
+		(line (pt 0 3912)(pt 104 3912)(line_width 3))
+	)
+	(port
+		(pt 0 3928)
+		(input)
+		(text "data12x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 3912 94 3928)(font "Arial" (font_size 8)))
+		(line (pt 0 3928)(pt 104 3928)(line_width 3))
+	)
+	(port
+		(pt 0 3944)
+		(input)
+		(text "data11x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 3928 94 3944)(font "Arial" (font_size 8)))
+		(line (pt 0 3944)(pt 104 3944)(line_width 3))
+	)
+	(port
+		(pt 0 3960)
+		(input)
+		(text "data10x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 3944 94 3960)(font "Arial" (font_size 8)))
+		(line (pt 0 3960)(pt 104 3960)(line_width 3))
+	)
+	(port
+		(pt 0 3976)
+		(input)
+		(text "data9x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 3960 87 3976)(font "Arial" (font_size 8)))
+		(line (pt 0 3976)(pt 104 3976)(line_width 3))
+	)
+	(port
+		(pt 0 3992)
+		(input)
+		(text "data8x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 3976 87 3992)(font "Arial" (font_size 8)))
+		(line (pt 0 3992)(pt 104 3992)(line_width 3))
+	)
+	(port
+		(pt 0 4008)
+		(input)
+		(text "data7x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 3992 87 4008)(font "Arial" (font_size 8)))
+		(line (pt 0 4008)(pt 104 4008)(line_width 3))
+	)
+	(port
+		(pt 0 4024)
+		(input)
+		(text "data6x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 4008 87 4024)(font "Arial" (font_size 8)))
+		(line (pt 0 4024)(pt 104 4024)(line_width 3))
+	)
+	(port
+		(pt 0 4040)
+		(input)
+		(text "data5x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 4024 87 4040)(font "Arial" (font_size 8)))
+		(line (pt 0 4040)(pt 104 4040)(line_width 3))
+	)
+	(port
+		(pt 0 4056)
+		(input)
+		(text "data4x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 4040 87 4056)(font "Arial" (font_size 8)))
+		(line (pt 0 4056)(pt 104 4056)(line_width 3))
+	)
+	(port
+		(pt 0 4072)
+		(input)
+		(text "data3x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 4056 87 4072)(font "Arial" (font_size 8)))
+		(line (pt 0 4072)(pt 104 4072)(line_width 3))
+	)
+	(port
+		(pt 0 4088)
+		(input)
+		(text "data2x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 4072 87 4088)(font "Arial" (font_size 8)))
+		(line (pt 0 4088)(pt 104 4088)(line_width 3))
+	)
+	(port
+		(pt 0 4104)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 4088 87 4104)(font "Arial" (font_size 8)))
+		(line (pt 0 4104)(pt 104 4104)(line_width 3))
+	)
+	(port
+		(pt 0 4120)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 4104 87 4120)(font "Arial" (font_size 8)))
+		(line (pt 0 4120)(pt 104 4120)(line_width 3))
+	)
+	(port
+		(pt 112 4144)
+		(input)
+		(text "sel[7..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
+		(text "sel[7..0]" (rect 116 4128 163 4144)(font "Arial" (font_size 8)))
+		(line (pt 112 4144)(pt 112 4132)(line_width 3))
+	)
+	(port
+		(pt 200 2080)
+		(output)
+		(text "result[127..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 121 2064 197 2080)(font "Arial" (font_size 8)))
+		(line (pt 200 2080)(pt 120 2080)(line_width 3))
+	)
+	(drawing
+		(line (pt 104 24)(pt 104 4136)(line_width 1))
+		(line (pt 120 32)(pt 120 4128)(line_width 1))
+		(line (pt 104 24)(pt 120 32)(line_width 1))
+		(line (pt 104 4136)(pt 120 4128)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_mux0.cmp b/FPGA_by_Fredi/lpm_mux0.cmp
new file mode 100644
index 0000000..a2d329f
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.cmp
@@ -0,0 +1,278 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux0
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data100x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data101x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data102x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data103x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data104x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data105x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data106x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data107x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data108x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data109x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data110x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data111x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data112x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data113x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data114x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data115x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data116x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data117x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data118x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data119x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data120x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data121x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data122x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data123x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data124x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data125x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data126x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data127x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data128x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data129x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data130x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data131x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data132x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data133x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data134x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data135x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data136x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data137x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data138x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data139x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data140x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data141x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data142x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data143x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data144x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data145x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data146x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data147x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data148x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data149x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data150x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data151x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data152x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data153x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data154x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data155x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data156x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data157x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data158x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data159x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data160x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data161x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data162x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data163x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data164x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data165x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data166x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data167x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data168x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data169x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data16x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data170x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data171x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data172x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data173x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data174x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data175x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data176x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data177x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data178x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data179x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data17x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data180x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data181x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data182x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data183x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data184x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data185x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data186x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data187x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data188x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data189x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data18x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data190x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data191x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data192x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data193x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data194x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data195x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data196x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data197x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data198x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data199x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data19x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data200x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data201x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data202x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data203x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data204x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data205x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data206x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data207x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data208x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data209x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data20x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data210x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data211x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data212x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data213x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data214x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data215x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data216x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data217x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data218x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data219x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data21x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data220x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data221x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data222x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data223x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data224x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data225x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data226x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data227x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data228x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data229x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data22x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data230x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data231x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data232x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data233x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data234x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data235x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data236x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data237x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data238x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data239x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data23x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data240x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data241x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data242x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data243x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data244x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data245x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data246x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data247x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data248x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data249x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data24x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data250x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data251x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data252x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data253x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data254x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data255x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data25x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data26x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data27x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data28x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data29x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data30x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data31x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data32x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data33x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data34x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data35x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data36x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data37x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data38x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data39x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data40x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data41x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data42x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data43x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data44x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data45x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data46x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data47x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data48x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data49x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data50x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data51x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data52x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data53x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data54x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data55x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data56x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data57x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data58x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data59x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data60x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data61x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data62x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data63x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data64x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data65x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data66x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data67x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data68x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data69x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data70x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data71x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data72x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data73x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data74x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data75x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data76x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data77x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data78x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data79x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data80x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data81x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data82x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data83x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data84x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data85x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data86x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data87x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data88x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data89x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data90x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data91x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data92x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data93x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data94x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data95x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data96x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data97x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data98x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data99x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_mux0.inc b/FPGA_by_Fredi/lpm_mux0.inc
new file mode 100644
index 0000000..f79ebc5
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.inc
@@ -0,0 +1,279 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux0 
+(
+	data0x[127..0],
+	data100x[127..0],
+	data101x[127..0],
+	data102x[127..0],
+	data103x[127..0],
+	data104x[127..0],
+	data105x[127..0],
+	data106x[127..0],
+	data107x[127..0],
+	data108x[127..0],
+	data109x[127..0],
+	data10x[127..0],
+	data110x[127..0],
+	data111x[127..0],
+	data112x[127..0],
+	data113x[127..0],
+	data114x[127..0],
+	data115x[127..0],
+	data116x[127..0],
+	data117x[127..0],
+	data118x[127..0],
+	data119x[127..0],
+	data11x[127..0],
+	data120x[127..0],
+	data121x[127..0],
+	data122x[127..0],
+	data123x[127..0],
+	data124x[127..0],
+	data125x[127..0],
+	data126x[127..0],
+	data127x[127..0],
+	data128x[127..0],
+	data129x[127..0],
+	data12x[127..0],
+	data130x[127..0],
+	data131x[127..0],
+	data132x[127..0],
+	data133x[127..0],
+	data134x[127..0],
+	data135x[127..0],
+	data136x[127..0],
+	data137x[127..0],
+	data138x[127..0],
+	data139x[127..0],
+	data13x[127..0],
+	data140x[127..0],
+	data141x[127..0],
+	data142x[127..0],
+	data143x[127..0],
+	data144x[127..0],
+	data145x[127..0],
+	data146x[127..0],
+	data147x[127..0],
+	data148x[127..0],
+	data149x[127..0],
+	data14x[127..0],
+	data150x[127..0],
+	data151x[127..0],
+	data152x[127..0],
+	data153x[127..0],
+	data154x[127..0],
+	data155x[127..0],
+	data156x[127..0],
+	data157x[127..0],
+	data158x[127..0],
+	data159x[127..0],
+	data15x[127..0],
+	data160x[127..0],
+	data161x[127..0],
+	data162x[127..0],
+	data163x[127..0],
+	data164x[127..0],
+	data165x[127..0],
+	data166x[127..0],
+	data167x[127..0],
+	data168x[127..0],
+	data169x[127..0],
+	data16x[127..0],
+	data170x[127..0],
+	data171x[127..0],
+	data172x[127..0],
+	data173x[127..0],
+	data174x[127..0],
+	data175x[127..0],
+	data176x[127..0],
+	data177x[127..0],
+	data178x[127..0],
+	data179x[127..0],
+	data17x[127..0],
+	data180x[127..0],
+	data181x[127..0],
+	data182x[127..0],
+	data183x[127..0],
+	data184x[127..0],
+	data185x[127..0],
+	data186x[127..0],
+	data187x[127..0],
+	data188x[127..0],
+	data189x[127..0],
+	data18x[127..0],
+	data190x[127..0],
+	data191x[127..0],
+	data192x[127..0],
+	data193x[127..0],
+	data194x[127..0],
+	data195x[127..0],
+	data196x[127..0],
+	data197x[127..0],
+	data198x[127..0],
+	data199x[127..0],
+	data19x[127..0],
+	data1x[127..0],
+	data200x[127..0],
+	data201x[127..0],
+	data202x[127..0],
+	data203x[127..0],
+	data204x[127..0],
+	data205x[127..0],
+	data206x[127..0],
+	data207x[127..0],
+	data208x[127..0],
+	data209x[127..0],
+	data20x[127..0],
+	data210x[127..0],
+	data211x[127..0],
+	data212x[127..0],
+	data213x[127..0],
+	data214x[127..0],
+	data215x[127..0],
+	data216x[127..0],
+	data217x[127..0],
+	data218x[127..0],
+	data219x[127..0],
+	data21x[127..0],
+	data220x[127..0],
+	data221x[127..0],
+	data222x[127..0],
+	data223x[127..0],
+	data224x[127..0],
+	data225x[127..0],
+	data226x[127..0],
+	data227x[127..0],
+	data228x[127..0],
+	data229x[127..0],
+	data22x[127..0],
+	data230x[127..0],
+	data231x[127..0],
+	data232x[127..0],
+	data233x[127..0],
+	data234x[127..0],
+	data235x[127..0],
+	data236x[127..0],
+	data237x[127..0],
+	data238x[127..0],
+	data239x[127..0],
+	data23x[127..0],
+	data240x[127..0],
+	data241x[127..0],
+	data242x[127..0],
+	data243x[127..0],
+	data244x[127..0],
+	data245x[127..0],
+	data246x[127..0],
+	data247x[127..0],
+	data248x[127..0],
+	data249x[127..0],
+	data24x[127..0],
+	data250x[127..0],
+	data251x[127..0],
+	data252x[127..0],
+	data253x[127..0],
+	data254x[127..0],
+	data255x[127..0],
+	data25x[127..0],
+	data26x[127..0],
+	data27x[127..0],
+	data28x[127..0],
+	data29x[127..0],
+	data2x[127..0],
+	data30x[127..0],
+	data31x[127..0],
+	data32x[127..0],
+	data33x[127..0],
+	data34x[127..0],
+	data35x[127..0],
+	data36x[127..0],
+	data37x[127..0],
+	data38x[127..0],
+	data39x[127..0],
+	data3x[127..0],
+	data40x[127..0],
+	data41x[127..0],
+	data42x[127..0],
+	data43x[127..0],
+	data44x[127..0],
+	data45x[127..0],
+	data46x[127..0],
+	data47x[127..0],
+	data48x[127..0],
+	data49x[127..0],
+	data4x[127..0],
+	data50x[127..0],
+	data51x[127..0],
+	data52x[127..0],
+	data53x[127..0],
+	data54x[127..0],
+	data55x[127..0],
+	data56x[127..0],
+	data57x[127..0],
+	data58x[127..0],
+	data59x[127..0],
+	data5x[127..0],
+	data60x[127..0],
+	data61x[127..0],
+	data62x[127..0],
+	data63x[127..0],
+	data64x[127..0],
+	data65x[127..0],
+	data66x[127..0],
+	data67x[127..0],
+	data68x[127..0],
+	data69x[127..0],
+	data6x[127..0],
+	data70x[127..0],
+	data71x[127..0],
+	data72x[127..0],
+	data73x[127..0],
+	data74x[127..0],
+	data75x[127..0],
+	data76x[127..0],
+	data77x[127..0],
+	data78x[127..0],
+	data79x[127..0],
+	data7x[127..0],
+	data80x[127..0],
+	data81x[127..0],
+	data82x[127..0],
+	data83x[127..0],
+	data84x[127..0],
+	data85x[127..0],
+	data86x[127..0],
+	data87x[127..0],
+	data88x[127..0],
+	data89x[127..0],
+	data8x[127..0],
+	data90x[127..0],
+	data91x[127..0],
+	data92x[127..0],
+	data93x[127..0],
+	data94x[127..0],
+	data95x[127..0],
+	data96x[127..0],
+	data97x[127..0],
+	data98x[127..0],
+	data99x[127..0],
+	data9x[127..0],
+	sel[7..0]
+)
+
+RETURNS (
+	result[127..0]
+);
diff --git a/FPGA_by_Fredi/lpm_mux0.qip b/FPGA_by_Fredi/lpm_mux0.qip
new file mode 100644
index 0000000..b46f6a0
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]
diff --git a/FPGA_by_Fredi/lpm_mux0.tdf b/FPGA_by_Fredi/lpm_mux0.tdf
new file mode 100644
index 0000000..9bd3bed
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.tdf
@@ -0,0 +1,1105 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux0.tdf
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_mux.inc";
+
+
+
+SUBDESIGN lpm_mux0
+(
+	data0x[127..0]	 : INPUT;
+	data100x[127..0]	 : INPUT;
+	data101x[127..0]	 : INPUT;
+	data102x[127..0]	 : INPUT;
+	data103x[127..0]	 : INPUT;
+	data104x[127..0]	 : INPUT;
+	data105x[127..0]	 : INPUT;
+	data106x[127..0]	 : INPUT;
+	data107x[127..0]	 : INPUT;
+	data108x[127..0]	 : INPUT;
+	data109x[127..0]	 : INPUT;
+	data10x[127..0]	 : INPUT;
+	data110x[127..0]	 : INPUT;
+	data111x[127..0]	 : INPUT;
+	data112x[127..0]	 : INPUT;
+	data113x[127..0]	 : INPUT;
+	data114x[127..0]	 : INPUT;
+	data115x[127..0]	 : INPUT;
+	data116x[127..0]	 : INPUT;
+	data117x[127..0]	 : INPUT;
+	data118x[127..0]	 : INPUT;
+	data119x[127..0]	 : INPUT;
+	data11x[127..0]	 : INPUT;
+	data120x[127..0]	 : INPUT;
+	data121x[127..0]	 : INPUT;
+	data122x[127..0]	 : INPUT;
+	data123x[127..0]	 : INPUT;
+	data124x[127..0]	 : INPUT;
+	data125x[127..0]	 : INPUT;
+	data126x[127..0]	 : INPUT;
+	data127x[127..0]	 : INPUT;
+	data128x[127..0]	 : INPUT;
+	data129x[127..0]	 : INPUT;
+	data12x[127..0]	 : INPUT;
+	data130x[127..0]	 : INPUT;
+	data131x[127..0]	 : INPUT;
+	data132x[127..0]	 : INPUT;
+	data133x[127..0]	 : INPUT;
+	data134x[127..0]	 : INPUT;
+	data135x[127..0]	 : INPUT;
+	data136x[127..0]	 : INPUT;
+	data137x[127..0]	 : INPUT;
+	data138x[127..0]	 : INPUT;
+	data139x[127..0]	 : INPUT;
+	data13x[127..0]	 : INPUT;
+	data140x[127..0]	 : INPUT;
+	data141x[127..0]	 : INPUT;
+	data142x[127..0]	 : INPUT;
+	data143x[127..0]	 : INPUT;
+	data144x[127..0]	 : INPUT;
+	data145x[127..0]	 : INPUT;
+	data146x[127..0]	 : INPUT;
+	data147x[127..0]	 : INPUT;
+	data148x[127..0]	 : INPUT;
+	data149x[127..0]	 : INPUT;
+	data14x[127..0]	 : INPUT;
+	data150x[127..0]	 : INPUT;
+	data151x[127..0]	 : INPUT;
+	data152x[127..0]	 : INPUT;
+	data153x[127..0]	 : INPUT;
+	data154x[127..0]	 : INPUT;
+	data155x[127..0]	 : INPUT;
+	data156x[127..0]	 : INPUT;
+	data157x[127..0]	 : INPUT;
+	data158x[127..0]	 : INPUT;
+	data159x[127..0]	 : INPUT;
+	data15x[127..0]	 : INPUT;
+	data160x[127..0]	 : INPUT;
+	data161x[127..0]	 : INPUT;
+	data162x[127..0]	 : INPUT;
+	data163x[127..0]	 : INPUT;
+	data164x[127..0]	 : INPUT;
+	data165x[127..0]	 : INPUT;
+	data166x[127..0]	 : INPUT;
+	data167x[127..0]	 : INPUT;
+	data168x[127..0]	 : INPUT;
+	data169x[127..0]	 : INPUT;
+	data16x[127..0]	 : INPUT;
+	data170x[127..0]	 : INPUT;
+	data171x[127..0]	 : INPUT;
+	data172x[127..0]	 : INPUT;
+	data173x[127..0]	 : INPUT;
+	data174x[127..0]	 : INPUT;
+	data175x[127..0]	 : INPUT;
+	data176x[127..0]	 : INPUT;
+	data177x[127..0]	 : INPUT;
+	data178x[127..0]	 : INPUT;
+	data179x[127..0]	 : INPUT;
+	data17x[127..0]	 : INPUT;
+	data180x[127..0]	 : INPUT;
+	data181x[127..0]	 : INPUT;
+	data182x[127..0]	 : INPUT;
+	data183x[127..0]	 : INPUT;
+	data184x[127..0]	 : INPUT;
+	data185x[127..0]	 : INPUT;
+	data186x[127..0]	 : INPUT;
+	data187x[127..0]	 : INPUT;
+	data188x[127..0]	 : INPUT;
+	data189x[127..0]	 : INPUT;
+	data18x[127..0]	 : INPUT;
+	data190x[127..0]	 : INPUT;
+	data191x[127..0]	 : INPUT;
+	data192x[127..0]	 : INPUT;
+	data193x[127..0]	 : INPUT;
+	data194x[127..0]	 : INPUT;
+	data195x[127..0]	 : INPUT;
+	data196x[127..0]	 : INPUT;
+	data197x[127..0]	 : INPUT;
+	data198x[127..0]	 : INPUT;
+	data199x[127..0]	 : INPUT;
+	data19x[127..0]	 : INPUT;
+	data1x[127..0]	 : INPUT;
+	data200x[127..0]	 : INPUT;
+	data201x[127..0]	 : INPUT;
+	data202x[127..0]	 : INPUT;
+	data203x[127..0]	 : INPUT;
+	data204x[127..0]	 : INPUT;
+	data205x[127..0]	 : INPUT;
+	data206x[127..0]	 : INPUT;
+	data207x[127..0]	 : INPUT;
+	data208x[127..0]	 : INPUT;
+	data209x[127..0]	 : INPUT;
+	data20x[127..0]	 : INPUT;
+	data210x[127..0]	 : INPUT;
+	data211x[127..0]	 : INPUT;
+	data212x[127..0]	 : INPUT;
+	data213x[127..0]	 : INPUT;
+	data214x[127..0]	 : INPUT;
+	data215x[127..0]	 : INPUT;
+	data216x[127..0]	 : INPUT;
+	data217x[127..0]	 : INPUT;
+	data218x[127..0]	 : INPUT;
+	data219x[127..0]	 : INPUT;
+	data21x[127..0]	 : INPUT;
+	data220x[127..0]	 : INPUT;
+	data221x[127..0]	 : INPUT;
+	data222x[127..0]	 : INPUT;
+	data223x[127..0]	 : INPUT;
+	data224x[127..0]	 : INPUT;
+	data225x[127..0]	 : INPUT;
+	data226x[127..0]	 : INPUT;
+	data227x[127..0]	 : INPUT;
+	data228x[127..0]	 : INPUT;
+	data229x[127..0]	 : INPUT;
+	data22x[127..0]	 : INPUT;
+	data230x[127..0]	 : INPUT;
+	data231x[127..0]	 : INPUT;
+	data232x[127..0]	 : INPUT;
+	data233x[127..0]	 : INPUT;
+	data234x[127..0]	 : INPUT;
+	data235x[127..0]	 : INPUT;
+	data236x[127..0]	 : INPUT;
+	data237x[127..0]	 : INPUT;
+	data238x[127..0]	 : INPUT;
+	data239x[127..0]	 : INPUT;
+	data23x[127..0]	 : INPUT;
+	data240x[127..0]	 : INPUT;
+	data241x[127..0]	 : INPUT;
+	data242x[127..0]	 : INPUT;
+	data243x[127..0]	 : INPUT;
+	data244x[127..0]	 : INPUT;
+	data245x[127..0]	 : INPUT;
+	data246x[127..0]	 : INPUT;
+	data247x[127..0]	 : INPUT;
+	data248x[127..0]	 : INPUT;
+	data249x[127..0]	 : INPUT;
+	data24x[127..0]	 : INPUT;
+	data250x[127..0]	 : INPUT;
+	data251x[127..0]	 : INPUT;
+	data252x[127..0]	 : INPUT;
+	data253x[127..0]	 : INPUT;
+	data254x[127..0]	 : INPUT;
+	data255x[127..0]	 : INPUT;
+	data25x[127..0]	 : INPUT;
+	data26x[127..0]	 : INPUT;
+	data27x[127..0]	 : INPUT;
+	data28x[127..0]	 : INPUT;
+	data29x[127..0]	 : INPUT;
+	data2x[127..0]	 : INPUT;
+	data30x[127..0]	 : INPUT;
+	data31x[127..0]	 : INPUT;
+	data32x[127..0]	 : INPUT;
+	data33x[127..0]	 : INPUT;
+	data34x[127..0]	 : INPUT;
+	data35x[127..0]	 : INPUT;
+	data36x[127..0]	 : INPUT;
+	data37x[127..0]	 : INPUT;
+	data38x[127..0]	 : INPUT;
+	data39x[127..0]	 : INPUT;
+	data3x[127..0]	 : INPUT;
+	data40x[127..0]	 : INPUT;
+	data41x[127..0]	 : INPUT;
+	data42x[127..0]	 : INPUT;
+	data43x[127..0]	 : INPUT;
+	data44x[127..0]	 : INPUT;
+	data45x[127..0]	 : INPUT;
+	data46x[127..0]	 : INPUT;
+	data47x[127..0]	 : INPUT;
+	data48x[127..0]	 : INPUT;
+	data49x[127..0]	 : INPUT;
+	data4x[127..0]	 : INPUT;
+	data50x[127..0]	 : INPUT;
+	data51x[127..0]	 : INPUT;
+	data52x[127..0]	 : INPUT;
+	data53x[127..0]	 : INPUT;
+	data54x[127..0]	 : INPUT;
+	data55x[127..0]	 : INPUT;
+	data56x[127..0]	 : INPUT;
+	data57x[127..0]	 : INPUT;
+	data58x[127..0]	 : INPUT;
+	data59x[127..0]	 : INPUT;
+	data5x[127..0]	 : INPUT;
+	data60x[127..0]	 : INPUT;
+	data61x[127..0]	 : INPUT;
+	data62x[127..0]	 : INPUT;
+	data63x[127..0]	 : INPUT;
+	data64x[127..0]	 : INPUT;
+	data65x[127..0]	 : INPUT;
+	data66x[127..0]	 : INPUT;
+	data67x[127..0]	 : INPUT;
+	data68x[127..0]	 : INPUT;
+	data69x[127..0]	 : INPUT;
+	data6x[127..0]	 : INPUT;
+	data70x[127..0]	 : INPUT;
+	data71x[127..0]	 : INPUT;
+	data72x[127..0]	 : INPUT;
+	data73x[127..0]	 : INPUT;
+	data74x[127..0]	 : INPUT;
+	data75x[127..0]	 : INPUT;
+	data76x[127..0]	 : INPUT;
+	data77x[127..0]	 : INPUT;
+	data78x[127..0]	 : INPUT;
+	data79x[127..0]	 : INPUT;
+	data7x[127..0]	 : INPUT;
+	data80x[127..0]	 : INPUT;
+	data81x[127..0]	 : INPUT;
+	data82x[127..0]	 : INPUT;
+	data83x[127..0]	 : INPUT;
+	data84x[127..0]	 : INPUT;
+	data85x[127..0]	 : INPUT;
+	data86x[127..0]	 : INPUT;
+	data87x[127..0]	 : INPUT;
+	data88x[127..0]	 : INPUT;
+	data89x[127..0]	 : INPUT;
+	data8x[127..0]	 : INPUT;
+	data90x[127..0]	 : INPUT;
+	data91x[127..0]	 : INPUT;
+	data92x[127..0]	 : INPUT;
+	data93x[127..0]	 : INPUT;
+	data94x[127..0]	 : INPUT;
+	data95x[127..0]	 : INPUT;
+	data96x[127..0]	 : INPUT;
+	data97x[127..0]	 : INPUT;
+	data98x[127..0]	 : INPUT;
+	data99x[127..0]	 : INPUT;
+	data9x[127..0]	 : INPUT;
+	sel[7..0]	 : INPUT;
+	result[127..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_mux_component : lpm_mux WITH (
+			LPM_SIZE = 256,
+			LPM_TYPE = "LPM_MUX",
+			LPM_WIDTH = 128,
+			LPM_WIDTHS = 8
+			);
+
+BEGIN
+
+	result[127..0] = lpm_mux_component.result[127..0];
+	lpm_mux_component.sel[7..0] = sel[7..0];
+	lpm_mux_component.data[255..255][127..0] = data255x[127..0];
+	lpm_mux_component.data[254..254][127..0] = data254x[127..0];
+	lpm_mux_component.data[253..253][127..0] = data253x[127..0];
+	lpm_mux_component.data[252..252][127..0] = data252x[127..0];
+	lpm_mux_component.data[251..251][127..0] = data251x[127..0];
+	lpm_mux_component.data[250..250][127..0] = data250x[127..0];
+	lpm_mux_component.data[249..249][127..0] = data249x[127..0];
+	lpm_mux_component.data[248..248][127..0] = data248x[127..0];
+	lpm_mux_component.data[247..247][127..0] = data247x[127..0];
+	lpm_mux_component.data[246..246][127..0] = data246x[127..0];
+	lpm_mux_component.data[245..245][127..0] = data245x[127..0];
+	lpm_mux_component.data[244..244][127..0] = data244x[127..0];
+	lpm_mux_component.data[243..243][127..0] = data243x[127..0];
+	lpm_mux_component.data[242..242][127..0] = data242x[127..0];
+	lpm_mux_component.data[241..241][127..0] = data241x[127..0];
+	lpm_mux_component.data[240..240][127..0] = data240x[127..0];
+	lpm_mux_component.data[239..239][127..0] = data239x[127..0];
+	lpm_mux_component.data[238..238][127..0] = data238x[127..0];
+	lpm_mux_component.data[237..237][127..0] = data237x[127..0];
+	lpm_mux_component.data[236..236][127..0] = data236x[127..0];
+	lpm_mux_component.data[235..235][127..0] = data235x[127..0];
+	lpm_mux_component.data[234..234][127..0] = data234x[127..0];
+	lpm_mux_component.data[233..233][127..0] = data233x[127..0];
+	lpm_mux_component.data[232..232][127..0] = data232x[127..0];
+	lpm_mux_component.data[231..231][127..0] = data231x[127..0];
+	lpm_mux_component.data[230..230][127..0] = data230x[127..0];
+	lpm_mux_component.data[229..229][127..0] = data229x[127..0];
+	lpm_mux_component.data[228..228][127..0] = data228x[127..0];
+	lpm_mux_component.data[227..227][127..0] = data227x[127..0];
+	lpm_mux_component.data[226..226][127..0] = data226x[127..0];
+	lpm_mux_component.data[225..225][127..0] = data225x[127..0];
+	lpm_mux_component.data[224..224][127..0] = data224x[127..0];
+	lpm_mux_component.data[223..223][127..0] = data223x[127..0];
+	lpm_mux_component.data[222..222][127..0] = data222x[127..0];
+	lpm_mux_component.data[221..221][127..0] = data221x[127..0];
+	lpm_mux_component.data[220..220][127..0] = data220x[127..0];
+	lpm_mux_component.data[219..219][127..0] = data219x[127..0];
+	lpm_mux_component.data[218..218][127..0] = data218x[127..0];
+	lpm_mux_component.data[217..217][127..0] = data217x[127..0];
+	lpm_mux_component.data[216..216][127..0] = data216x[127..0];
+	lpm_mux_component.data[215..215][127..0] = data215x[127..0];
+	lpm_mux_component.data[214..214][127..0] = data214x[127..0];
+	lpm_mux_component.data[213..213][127..0] = data213x[127..0];
+	lpm_mux_component.data[212..212][127..0] = data212x[127..0];
+	lpm_mux_component.data[211..211][127..0] = data211x[127..0];
+	lpm_mux_component.data[210..210][127..0] = data210x[127..0];
+	lpm_mux_component.data[209..209][127..0] = data209x[127..0];
+	lpm_mux_component.data[208..208][127..0] = data208x[127..0];
+	lpm_mux_component.data[207..207][127..0] = data207x[127..0];
+	lpm_mux_component.data[206..206][127..0] = data206x[127..0];
+	lpm_mux_component.data[205..205][127..0] = data205x[127..0];
+	lpm_mux_component.data[204..204][127..0] = data204x[127..0];
+	lpm_mux_component.data[203..203][127..0] = data203x[127..0];
+	lpm_mux_component.data[202..202][127..0] = data202x[127..0];
+	lpm_mux_component.data[201..201][127..0] = data201x[127..0];
+	lpm_mux_component.data[200..200][127..0] = data200x[127..0];
+	lpm_mux_component.data[199..199][127..0] = data199x[127..0];
+	lpm_mux_component.data[198..198][127..0] = data198x[127..0];
+	lpm_mux_component.data[197..197][127..0] = data197x[127..0];
+	lpm_mux_component.data[196..196][127..0] = data196x[127..0];
+	lpm_mux_component.data[195..195][127..0] = data195x[127..0];
+	lpm_mux_component.data[194..194][127..0] = data194x[127..0];
+	lpm_mux_component.data[193..193][127..0] = data193x[127..0];
+	lpm_mux_component.data[192..192][127..0] = data192x[127..0];
+	lpm_mux_component.data[191..191][127..0] = data191x[127..0];
+	lpm_mux_component.data[190..190][127..0] = data190x[127..0];
+	lpm_mux_component.data[189..189][127..0] = data189x[127..0];
+	lpm_mux_component.data[188..188][127..0] = data188x[127..0];
+	lpm_mux_component.data[187..187][127..0] = data187x[127..0];
+	lpm_mux_component.data[186..186][127..0] = data186x[127..0];
+	lpm_mux_component.data[185..185][127..0] = data185x[127..0];
+	lpm_mux_component.data[184..184][127..0] = data184x[127..0];
+	lpm_mux_component.data[183..183][127..0] = data183x[127..0];
+	lpm_mux_component.data[182..182][127..0] = data182x[127..0];
+	lpm_mux_component.data[181..181][127..0] = data181x[127..0];
+	lpm_mux_component.data[180..180][127..0] = data180x[127..0];
+	lpm_mux_component.data[179..179][127..0] = data179x[127..0];
+	lpm_mux_component.data[178..178][127..0] = data178x[127..0];
+	lpm_mux_component.data[177..177][127..0] = data177x[127..0];
+	lpm_mux_component.data[176..176][127..0] = data176x[127..0];
+	lpm_mux_component.data[175..175][127..0] = data175x[127..0];
+	lpm_mux_component.data[174..174][127..0] = data174x[127..0];
+	lpm_mux_component.data[173..173][127..0] = data173x[127..0];
+	lpm_mux_component.data[172..172][127..0] = data172x[127..0];
+	lpm_mux_component.data[171..171][127..0] = data171x[127..0];
+	lpm_mux_component.data[170..170][127..0] = data170x[127..0];
+	lpm_mux_component.data[169..169][127..0] = data169x[127..0];
+	lpm_mux_component.data[168..168][127..0] = data168x[127..0];
+	lpm_mux_component.data[167..167][127..0] = data167x[127..0];
+	lpm_mux_component.data[166..166][127..0] = data166x[127..0];
+	lpm_mux_component.data[165..165][127..0] = data165x[127..0];
+	lpm_mux_component.data[164..164][127..0] = data164x[127..0];
+	lpm_mux_component.data[163..163][127..0] = data163x[127..0];
+	lpm_mux_component.data[162..162][127..0] = data162x[127..0];
+	lpm_mux_component.data[161..161][127..0] = data161x[127..0];
+	lpm_mux_component.data[160..160][127..0] = data160x[127..0];
+	lpm_mux_component.data[159..159][127..0] = data159x[127..0];
+	lpm_mux_component.data[158..158][127..0] = data158x[127..0];
+	lpm_mux_component.data[157..157][127..0] = data157x[127..0];
+	lpm_mux_component.data[156..156][127..0] = data156x[127..0];
+	lpm_mux_component.data[155..155][127..0] = data155x[127..0];
+	lpm_mux_component.data[154..154][127..0] = data154x[127..0];
+	lpm_mux_component.data[153..153][127..0] = data153x[127..0];
+	lpm_mux_component.data[152..152][127..0] = data152x[127..0];
+	lpm_mux_component.data[151..151][127..0] = data151x[127..0];
+	lpm_mux_component.data[150..150][127..0] = data150x[127..0];
+	lpm_mux_component.data[149..149][127..0] = data149x[127..0];
+	lpm_mux_component.data[148..148][127..0] = data148x[127..0];
+	lpm_mux_component.data[147..147][127..0] = data147x[127..0];
+	lpm_mux_component.data[146..146][127..0] = data146x[127..0];
+	lpm_mux_component.data[145..145][127..0] = data145x[127..0];
+	lpm_mux_component.data[144..144][127..0] = data144x[127..0];
+	lpm_mux_component.data[143..143][127..0] = data143x[127..0];
+	lpm_mux_component.data[142..142][127..0] = data142x[127..0];
+	lpm_mux_component.data[141..141][127..0] = data141x[127..0];
+	lpm_mux_component.data[140..140][127..0] = data140x[127..0];
+	lpm_mux_component.data[139..139][127..0] = data139x[127..0];
+	lpm_mux_component.data[138..138][127..0] = data138x[127..0];
+	lpm_mux_component.data[137..137][127..0] = data137x[127..0];
+	lpm_mux_component.data[136..136][127..0] = data136x[127..0];
+	lpm_mux_component.data[135..135][127..0] = data135x[127..0];
+	lpm_mux_component.data[134..134][127..0] = data134x[127..0];
+	lpm_mux_component.data[133..133][127..0] = data133x[127..0];
+	lpm_mux_component.data[132..132][127..0] = data132x[127..0];
+	lpm_mux_component.data[131..131][127..0] = data131x[127..0];
+	lpm_mux_component.data[130..130][127..0] = data130x[127..0];
+	lpm_mux_component.data[129..129][127..0] = data129x[127..0];
+	lpm_mux_component.data[128..128][127..0] = data128x[127..0];
+	lpm_mux_component.data[127..127][127..0] = data127x[127..0];
+	lpm_mux_component.data[126..126][127..0] = data126x[127..0];
+	lpm_mux_component.data[125..125][127..0] = data125x[127..0];
+	lpm_mux_component.data[124..124][127..0] = data124x[127..0];
+	lpm_mux_component.data[123..123][127..0] = data123x[127..0];
+	lpm_mux_component.data[122..122][127..0] = data122x[127..0];
+	lpm_mux_component.data[121..121][127..0] = data121x[127..0];
+	lpm_mux_component.data[120..120][127..0] = data120x[127..0];
+	lpm_mux_component.data[119..119][127..0] = data119x[127..0];
+	lpm_mux_component.data[118..118][127..0] = data118x[127..0];
+	lpm_mux_component.data[117..117][127..0] = data117x[127..0];
+	lpm_mux_component.data[116..116][127..0] = data116x[127..0];
+	lpm_mux_component.data[115..115][127..0] = data115x[127..0];
+	lpm_mux_component.data[114..114][127..0] = data114x[127..0];
+	lpm_mux_component.data[113..113][127..0] = data113x[127..0];
+	lpm_mux_component.data[112..112][127..0] = data112x[127..0];
+	lpm_mux_component.data[111..111][127..0] = data111x[127..0];
+	lpm_mux_component.data[110..110][127..0] = data110x[127..0];
+	lpm_mux_component.data[109..109][127..0] = data109x[127..0];
+	lpm_mux_component.data[108..108][127..0] = data108x[127..0];
+	lpm_mux_component.data[107..107][127..0] = data107x[127..0];
+	lpm_mux_component.data[106..106][127..0] = data106x[127..0];
+	lpm_mux_component.data[105..105][127..0] = data105x[127..0];
+	lpm_mux_component.data[104..104][127..0] = data104x[127..0];
+	lpm_mux_component.data[103..103][127..0] = data103x[127..0];
+	lpm_mux_component.data[102..102][127..0] = data102x[127..0];
+	lpm_mux_component.data[101..101][127..0] = data101x[127..0];
+	lpm_mux_component.data[100..100][127..0] = data100x[127..0];
+	lpm_mux_component.data[99..99][127..0] = data99x[127..0];
+	lpm_mux_component.data[98..98][127..0] = data98x[127..0];
+	lpm_mux_component.data[97..97][127..0] = data97x[127..0];
+	lpm_mux_component.data[96..96][127..0] = data96x[127..0];
+	lpm_mux_component.data[95..95][127..0] = data95x[127..0];
+	lpm_mux_component.data[94..94][127..0] = data94x[127..0];
+	lpm_mux_component.data[93..93][127..0] = data93x[127..0];
+	lpm_mux_component.data[92..92][127..0] = data92x[127..0];
+	lpm_mux_component.data[91..91][127..0] = data91x[127..0];
+	lpm_mux_component.data[90..90][127..0] = data90x[127..0];
+	lpm_mux_component.data[89..89][127..0] = data89x[127..0];
+	lpm_mux_component.data[88..88][127..0] = data88x[127..0];
+	lpm_mux_component.data[87..87][127..0] = data87x[127..0];
+	lpm_mux_component.data[86..86][127..0] = data86x[127..0];
+	lpm_mux_component.data[85..85][127..0] = data85x[127..0];
+	lpm_mux_component.data[84..84][127..0] = data84x[127..0];
+	lpm_mux_component.data[83..83][127..0] = data83x[127..0];
+	lpm_mux_component.data[82..82][127..0] = data82x[127..0];
+	lpm_mux_component.data[81..81][127..0] = data81x[127..0];
+	lpm_mux_component.data[80..80][127..0] = data80x[127..0];
+	lpm_mux_component.data[79..79][127..0] = data79x[127..0];
+	lpm_mux_component.data[78..78][127..0] = data78x[127..0];
+	lpm_mux_component.data[77..77][127..0] = data77x[127..0];
+	lpm_mux_component.data[76..76][127..0] = data76x[127..0];
+	lpm_mux_component.data[75..75][127..0] = data75x[127..0];
+	lpm_mux_component.data[74..74][127..0] = data74x[127..0];
+	lpm_mux_component.data[73..73][127..0] = data73x[127..0];
+	lpm_mux_component.data[72..72][127..0] = data72x[127..0];
+	lpm_mux_component.data[71..71][127..0] = data71x[127..0];
+	lpm_mux_component.data[70..70][127..0] = data70x[127..0];
+	lpm_mux_component.data[69..69][127..0] = data69x[127..0];
+	lpm_mux_component.data[68..68][127..0] = data68x[127..0];
+	lpm_mux_component.data[67..67][127..0] = data67x[127..0];
+	lpm_mux_component.data[66..66][127..0] = data66x[127..0];
+	lpm_mux_component.data[65..65][127..0] = data65x[127..0];
+	lpm_mux_component.data[64..64][127..0] = data64x[127..0];
+	lpm_mux_component.data[63..63][127..0] = data63x[127..0];
+	lpm_mux_component.data[62..62][127..0] = data62x[127..0];
+	lpm_mux_component.data[61..61][127..0] = data61x[127..0];
+	lpm_mux_component.data[60..60][127..0] = data60x[127..0];
+	lpm_mux_component.data[59..59][127..0] = data59x[127..0];
+	lpm_mux_component.data[58..58][127..0] = data58x[127..0];
+	lpm_mux_component.data[57..57][127..0] = data57x[127..0];
+	lpm_mux_component.data[56..56][127..0] = data56x[127..0];
+	lpm_mux_component.data[55..55][127..0] = data55x[127..0];
+	lpm_mux_component.data[54..54][127..0] = data54x[127..0];
+	lpm_mux_component.data[53..53][127..0] = data53x[127..0];
+	lpm_mux_component.data[52..52][127..0] = data52x[127..0];
+	lpm_mux_component.data[51..51][127..0] = data51x[127..0];
+	lpm_mux_component.data[50..50][127..0] = data50x[127..0];
+	lpm_mux_component.data[49..49][127..0] = data49x[127..0];
+	lpm_mux_component.data[48..48][127..0] = data48x[127..0];
+	lpm_mux_component.data[47..47][127..0] = data47x[127..0];
+	lpm_mux_component.data[46..46][127..0] = data46x[127..0];
+	lpm_mux_component.data[45..45][127..0] = data45x[127..0];
+	lpm_mux_component.data[44..44][127..0] = data44x[127..0];
+	lpm_mux_component.data[43..43][127..0] = data43x[127..0];
+	lpm_mux_component.data[42..42][127..0] = data42x[127..0];
+	lpm_mux_component.data[41..41][127..0] = data41x[127..0];
+	lpm_mux_component.data[40..40][127..0] = data40x[127..0];
+	lpm_mux_component.data[39..39][127..0] = data39x[127..0];
+	lpm_mux_component.data[38..38][127..0] = data38x[127..0];
+	lpm_mux_component.data[37..37][127..0] = data37x[127..0];
+	lpm_mux_component.data[36..36][127..0] = data36x[127..0];
+	lpm_mux_component.data[35..35][127..0] = data35x[127..0];
+	lpm_mux_component.data[34..34][127..0] = data34x[127..0];
+	lpm_mux_component.data[33..33][127..0] = data33x[127..0];
+	lpm_mux_component.data[32..32][127..0] = data32x[127..0];
+	lpm_mux_component.data[31..31][127..0] = data31x[127..0];
+	lpm_mux_component.data[30..30][127..0] = data30x[127..0];
+	lpm_mux_component.data[29..29][127..0] = data29x[127..0];
+	lpm_mux_component.data[28..28][127..0] = data28x[127..0];
+	lpm_mux_component.data[27..27][127..0] = data27x[127..0];
+	lpm_mux_component.data[26..26][127..0] = data26x[127..0];
+	lpm_mux_component.data[25..25][127..0] = data25x[127..0];
+	lpm_mux_component.data[24..24][127..0] = data24x[127..0];
+	lpm_mux_component.data[23..23][127..0] = data23x[127..0];
+	lpm_mux_component.data[22..22][127..0] = data22x[127..0];
+	lpm_mux_component.data[21..21][127..0] = data21x[127..0];
+	lpm_mux_component.data[20..20][127..0] = data20x[127..0];
+	lpm_mux_component.data[19..19][127..0] = data19x[127..0];
+	lpm_mux_component.data[18..18][127..0] = data18x[127..0];
+	lpm_mux_component.data[17..17][127..0] = data17x[127..0];
+	lpm_mux_component.data[16..16][127..0] = data16x[127..0];
+	lpm_mux_component.data[15..15][127..0] = data15x[127..0];
+	lpm_mux_component.data[14..14][127..0] = data14x[127..0];
+	lpm_mux_component.data[13..13][127..0] = data13x[127..0];
+	lpm_mux_component.data[12..12][127..0] = data12x[127..0];
+	lpm_mux_component.data[11..11][127..0] = data11x[127..0];
+	lpm_mux_component.data[10..10][127..0] = data10x[127..0];
+	lpm_mux_component.data[9..9][127..0] = data9x[127..0];
+	lpm_mux_component.data[8..8][127..0] = data8x[127..0];
+	lpm_mux_component.data[7..7][127..0] = data7x[127..0];
+	lpm_mux_component.data[6..6][127..0] = data6x[127..0];
+	lpm_mux_component.data[5..5][127..0] = data5x[127..0];
+	lpm_mux_component.data[4..4][127..0] = data4x[127..0];
+	lpm_mux_component.data[3..3][127..0] = data3x[127..0];
+	lpm_mux_component.data[2..2][127..0] = data2x[127..0];
+	lpm_mux_component.data[1..1][127..0] = data1x[127..0];
+	lpm_mux_component.data[0..0][127..0] = data0x[127..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "8"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data100x 0 0 128 0 INPUT NODEFVAL data100x[127..0]
+-- Retrieval info: USED_PORT: data101x 0 0 128 0 INPUT NODEFVAL data101x[127..0]
+-- Retrieval info: USED_PORT: data102x 0 0 128 0 INPUT NODEFVAL data102x[127..0]
+-- Retrieval info: USED_PORT: data103x 0 0 128 0 INPUT NODEFVAL data103x[127..0]
+-- Retrieval info: USED_PORT: data104x 0 0 128 0 INPUT NODEFVAL data104x[127..0]
+-- Retrieval info: USED_PORT: data105x 0 0 128 0 INPUT NODEFVAL data105x[127..0]
+-- Retrieval info: USED_PORT: data106x 0 0 128 0 INPUT NODEFVAL data106x[127..0]
+-- Retrieval info: USED_PORT: data107x 0 0 128 0 INPUT NODEFVAL data107x[127..0]
+-- Retrieval info: USED_PORT: data108x 0 0 128 0 INPUT NODEFVAL data108x[127..0]
+-- Retrieval info: USED_PORT: data109x 0 0 128 0 INPUT NODEFVAL data109x[127..0]
+-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
+-- Retrieval info: USED_PORT: data110x 0 0 128 0 INPUT NODEFVAL data110x[127..0]
+-- Retrieval info: USED_PORT: data111x 0 0 128 0 INPUT NODEFVAL data111x[127..0]
+-- Retrieval info: USED_PORT: data112x 0 0 128 0 INPUT NODEFVAL data112x[127..0]
+-- Retrieval info: USED_PORT: data113x 0 0 128 0 INPUT NODEFVAL data113x[127..0]
+-- Retrieval info: USED_PORT: data114x 0 0 128 0 INPUT NODEFVAL data114x[127..0]
+-- Retrieval info: USED_PORT: data115x 0 0 128 0 INPUT NODEFVAL data115x[127..0]
+-- Retrieval info: USED_PORT: data116x 0 0 128 0 INPUT NODEFVAL data116x[127..0]
+-- Retrieval info: USED_PORT: data117x 0 0 128 0 INPUT NODEFVAL data117x[127..0]
+-- Retrieval info: USED_PORT: data118x 0 0 128 0 INPUT NODEFVAL data118x[127..0]
+-- Retrieval info: USED_PORT: data119x 0 0 128 0 INPUT NODEFVAL data119x[127..0]
+-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
+-- Retrieval info: USED_PORT: data120x 0 0 128 0 INPUT NODEFVAL data120x[127..0]
+-- Retrieval info: USED_PORT: data121x 0 0 128 0 INPUT NODEFVAL data121x[127..0]
+-- Retrieval info: USED_PORT: data122x 0 0 128 0 INPUT NODEFVAL data122x[127..0]
+-- Retrieval info: USED_PORT: data123x 0 0 128 0 INPUT NODEFVAL data123x[127..0]
+-- Retrieval info: USED_PORT: data124x 0 0 128 0 INPUT NODEFVAL data124x[127..0]
+-- Retrieval info: USED_PORT: data125x 0 0 128 0 INPUT NODEFVAL data125x[127..0]
+-- Retrieval info: USED_PORT: data126x 0 0 128 0 INPUT NODEFVAL data126x[127..0]
+-- Retrieval info: USED_PORT: data127x 0 0 128 0 INPUT NODEFVAL data127x[127..0]
+-- Retrieval info: USED_PORT: data128x 0 0 128 0 INPUT NODEFVAL data128x[127..0]
+-- Retrieval info: USED_PORT: data129x 0 0 128 0 INPUT NODEFVAL data129x[127..0]
+-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
+-- Retrieval info: USED_PORT: data130x 0 0 128 0 INPUT NODEFVAL data130x[127..0]
+-- Retrieval info: USED_PORT: data131x 0 0 128 0 INPUT NODEFVAL data131x[127..0]
+-- Retrieval info: USED_PORT: data132x 0 0 128 0 INPUT NODEFVAL data132x[127..0]
+-- Retrieval info: USED_PORT: data133x 0 0 128 0 INPUT NODEFVAL data133x[127..0]
+-- Retrieval info: USED_PORT: data134x 0 0 128 0 INPUT NODEFVAL data134x[127..0]
+-- Retrieval info: USED_PORT: data135x 0 0 128 0 INPUT NODEFVAL data135x[127..0]
+-- Retrieval info: USED_PORT: data136x 0 0 128 0 INPUT NODEFVAL data136x[127..0]
+-- Retrieval info: USED_PORT: data137x 0 0 128 0 INPUT NODEFVAL data137x[127..0]
+-- Retrieval info: USED_PORT: data138x 0 0 128 0 INPUT NODEFVAL data138x[127..0]
+-- Retrieval info: USED_PORT: data139x 0 0 128 0 INPUT NODEFVAL data139x[127..0]
+-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
+-- Retrieval info: USED_PORT: data140x 0 0 128 0 INPUT NODEFVAL data140x[127..0]
+-- Retrieval info: USED_PORT: data141x 0 0 128 0 INPUT NODEFVAL data141x[127..0]
+-- Retrieval info: USED_PORT: data142x 0 0 128 0 INPUT NODEFVAL data142x[127..0]
+-- Retrieval info: USED_PORT: data143x 0 0 128 0 INPUT NODEFVAL data143x[127..0]
+-- Retrieval info: USED_PORT: data144x 0 0 128 0 INPUT NODEFVAL data144x[127..0]
+-- Retrieval info: USED_PORT: data145x 0 0 128 0 INPUT NODEFVAL data145x[127..0]
+-- Retrieval info: USED_PORT: data146x 0 0 128 0 INPUT NODEFVAL data146x[127..0]
+-- Retrieval info: USED_PORT: data147x 0 0 128 0 INPUT NODEFVAL data147x[127..0]
+-- Retrieval info: USED_PORT: data148x 0 0 128 0 INPUT NODEFVAL data148x[127..0]
+-- Retrieval info: USED_PORT: data149x 0 0 128 0 INPUT NODEFVAL data149x[127..0]
+-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
+-- Retrieval info: USED_PORT: data150x 0 0 128 0 INPUT NODEFVAL data150x[127..0]
+-- Retrieval info: USED_PORT: data151x 0 0 128 0 INPUT NODEFVAL data151x[127..0]
+-- Retrieval info: USED_PORT: data152x 0 0 128 0 INPUT NODEFVAL data152x[127..0]
+-- Retrieval info: USED_PORT: data153x 0 0 128 0 INPUT NODEFVAL data153x[127..0]
+-- Retrieval info: USED_PORT: data154x 0 0 128 0 INPUT NODEFVAL data154x[127..0]
+-- Retrieval info: USED_PORT: data155x 0 0 128 0 INPUT NODEFVAL data155x[127..0]
+-- Retrieval info: USED_PORT: data156x 0 0 128 0 INPUT NODEFVAL data156x[127..0]
+-- Retrieval info: USED_PORT: data157x 0 0 128 0 INPUT NODEFVAL data157x[127..0]
+-- Retrieval info: USED_PORT: data158x 0 0 128 0 INPUT NODEFVAL data158x[127..0]
+-- Retrieval info: USED_PORT: data159x 0 0 128 0 INPUT NODEFVAL data159x[127..0]
+-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
+-- Retrieval info: USED_PORT: data160x 0 0 128 0 INPUT NODEFVAL data160x[127..0]
+-- Retrieval info: USED_PORT: data161x 0 0 128 0 INPUT NODEFVAL data161x[127..0]
+-- Retrieval info: USED_PORT: data162x 0 0 128 0 INPUT NODEFVAL data162x[127..0]
+-- Retrieval info: USED_PORT: data163x 0 0 128 0 INPUT NODEFVAL data163x[127..0]
+-- Retrieval info: USED_PORT: data164x 0 0 128 0 INPUT NODEFVAL data164x[127..0]
+-- Retrieval info: USED_PORT: data165x 0 0 128 0 INPUT NODEFVAL data165x[127..0]
+-- Retrieval info: USED_PORT: data166x 0 0 128 0 INPUT NODEFVAL data166x[127..0]
+-- Retrieval info: USED_PORT: data167x 0 0 128 0 INPUT NODEFVAL data167x[127..0]
+-- Retrieval info: USED_PORT: data168x 0 0 128 0 INPUT NODEFVAL data168x[127..0]
+-- Retrieval info: USED_PORT: data169x 0 0 128 0 INPUT NODEFVAL data169x[127..0]
+-- Retrieval info: USED_PORT: data16x 0 0 128 0 INPUT NODEFVAL data16x[127..0]
+-- Retrieval info: USED_PORT: data170x 0 0 128 0 INPUT NODEFVAL data170x[127..0]
+-- Retrieval info: USED_PORT: data171x 0 0 128 0 INPUT NODEFVAL data171x[127..0]
+-- Retrieval info: USED_PORT: data172x 0 0 128 0 INPUT NODEFVAL data172x[127..0]
+-- Retrieval info: USED_PORT: data173x 0 0 128 0 INPUT NODEFVAL data173x[127..0]
+-- Retrieval info: USED_PORT: data174x 0 0 128 0 INPUT NODEFVAL data174x[127..0]
+-- Retrieval info: USED_PORT: data175x 0 0 128 0 INPUT NODEFVAL data175x[127..0]
+-- Retrieval info: USED_PORT: data176x 0 0 128 0 INPUT NODEFVAL data176x[127..0]
+-- Retrieval info: USED_PORT: data177x 0 0 128 0 INPUT NODEFVAL data177x[127..0]
+-- Retrieval info: USED_PORT: data178x 0 0 128 0 INPUT NODEFVAL data178x[127..0]
+-- Retrieval info: USED_PORT: data179x 0 0 128 0 INPUT NODEFVAL data179x[127..0]
+-- Retrieval info: USED_PORT: data17x 0 0 128 0 INPUT NODEFVAL data17x[127..0]
+-- Retrieval info: USED_PORT: data180x 0 0 128 0 INPUT NODEFVAL data180x[127..0]
+-- Retrieval info: USED_PORT: data181x 0 0 128 0 INPUT NODEFVAL data181x[127..0]
+-- Retrieval info: USED_PORT: data182x 0 0 128 0 INPUT NODEFVAL data182x[127..0]
+-- Retrieval info: USED_PORT: data183x 0 0 128 0 INPUT NODEFVAL data183x[127..0]
+-- Retrieval info: USED_PORT: data184x 0 0 128 0 INPUT NODEFVAL data184x[127..0]
+-- Retrieval info: USED_PORT: data185x 0 0 128 0 INPUT NODEFVAL data185x[127..0]
+-- Retrieval info: USED_PORT: data186x 0 0 128 0 INPUT NODEFVAL data186x[127..0]
+-- Retrieval info: USED_PORT: data187x 0 0 128 0 INPUT NODEFVAL data187x[127..0]
+-- Retrieval info: USED_PORT: data188x 0 0 128 0 INPUT NODEFVAL data188x[127..0]
+-- Retrieval info: USED_PORT: data189x 0 0 128 0 INPUT NODEFVAL data189x[127..0]
+-- Retrieval info: USED_PORT: data18x 0 0 128 0 INPUT NODEFVAL data18x[127..0]
+-- Retrieval info: USED_PORT: data190x 0 0 128 0 INPUT NODEFVAL data190x[127..0]
+-- Retrieval info: USED_PORT: data191x 0 0 128 0 INPUT NODEFVAL data191x[127..0]
+-- Retrieval info: USED_PORT: data192x 0 0 128 0 INPUT NODEFVAL data192x[127..0]
+-- Retrieval info: USED_PORT: data193x 0 0 128 0 INPUT NODEFVAL data193x[127..0]
+-- Retrieval info: USED_PORT: data194x 0 0 128 0 INPUT NODEFVAL data194x[127..0]
+-- Retrieval info: USED_PORT: data195x 0 0 128 0 INPUT NODEFVAL data195x[127..0]
+-- Retrieval info: USED_PORT: data196x 0 0 128 0 INPUT NODEFVAL data196x[127..0]
+-- Retrieval info: USED_PORT: data197x 0 0 128 0 INPUT NODEFVAL data197x[127..0]
+-- Retrieval info: USED_PORT: data198x 0 0 128 0 INPUT NODEFVAL data198x[127..0]
+-- Retrieval info: USED_PORT: data199x 0 0 128 0 INPUT NODEFVAL data199x[127..0]
+-- Retrieval info: USED_PORT: data19x 0 0 128 0 INPUT NODEFVAL data19x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: data200x 0 0 128 0 INPUT NODEFVAL data200x[127..0]
+-- Retrieval info: USED_PORT: data201x 0 0 128 0 INPUT NODEFVAL data201x[127..0]
+-- Retrieval info: USED_PORT: data202x 0 0 128 0 INPUT NODEFVAL data202x[127..0]
+-- Retrieval info: USED_PORT: data203x 0 0 128 0 INPUT NODEFVAL data203x[127..0]
+-- Retrieval info: USED_PORT: data204x 0 0 128 0 INPUT NODEFVAL data204x[127..0]
+-- Retrieval info: USED_PORT: data205x 0 0 128 0 INPUT NODEFVAL data205x[127..0]
+-- Retrieval info: USED_PORT: data206x 0 0 128 0 INPUT NODEFVAL data206x[127..0]
+-- Retrieval info: USED_PORT: data207x 0 0 128 0 INPUT NODEFVAL data207x[127..0]
+-- Retrieval info: USED_PORT: data208x 0 0 128 0 INPUT NODEFVAL data208x[127..0]
+-- Retrieval info: USED_PORT: data209x 0 0 128 0 INPUT NODEFVAL data209x[127..0]
+-- Retrieval info: USED_PORT: data20x 0 0 128 0 INPUT NODEFVAL data20x[127..0]
+-- Retrieval info: USED_PORT: data210x 0 0 128 0 INPUT NODEFVAL data210x[127..0]
+-- Retrieval info: USED_PORT: data211x 0 0 128 0 INPUT NODEFVAL data211x[127..0]
+-- Retrieval info: USED_PORT: data212x 0 0 128 0 INPUT NODEFVAL data212x[127..0]
+-- Retrieval info: USED_PORT: data213x 0 0 128 0 INPUT NODEFVAL data213x[127..0]
+-- Retrieval info: USED_PORT: data214x 0 0 128 0 INPUT NODEFVAL data214x[127..0]
+-- Retrieval info: USED_PORT: data215x 0 0 128 0 INPUT NODEFVAL data215x[127..0]
+-- Retrieval info: USED_PORT: data216x 0 0 128 0 INPUT NODEFVAL data216x[127..0]
+-- Retrieval info: USED_PORT: data217x 0 0 128 0 INPUT NODEFVAL data217x[127..0]
+-- Retrieval info: USED_PORT: data218x 0 0 128 0 INPUT NODEFVAL data218x[127..0]
+-- Retrieval info: USED_PORT: data219x 0 0 128 0 INPUT NODEFVAL data219x[127..0]
+-- Retrieval info: USED_PORT: data21x 0 0 128 0 INPUT NODEFVAL data21x[127..0]
+-- Retrieval info: USED_PORT: data220x 0 0 128 0 INPUT NODEFVAL data220x[127..0]
+-- Retrieval info: USED_PORT: data221x 0 0 128 0 INPUT NODEFVAL data221x[127..0]
+-- Retrieval info: USED_PORT: data222x 0 0 128 0 INPUT NODEFVAL data222x[127..0]
+-- Retrieval info: USED_PORT: data223x 0 0 128 0 INPUT NODEFVAL data223x[127..0]
+-- Retrieval info: USED_PORT: data224x 0 0 128 0 INPUT NODEFVAL data224x[127..0]
+-- Retrieval info: USED_PORT: data225x 0 0 128 0 INPUT NODEFVAL data225x[127..0]
+-- Retrieval info: USED_PORT: data226x 0 0 128 0 INPUT NODEFVAL data226x[127..0]
+-- Retrieval info: USED_PORT: data227x 0 0 128 0 INPUT NODEFVAL data227x[127..0]
+-- Retrieval info: USED_PORT: data228x 0 0 128 0 INPUT NODEFVAL data228x[127..0]
+-- Retrieval info: USED_PORT: data229x 0 0 128 0 INPUT NODEFVAL data229x[127..0]
+-- Retrieval info: USED_PORT: data22x 0 0 128 0 INPUT NODEFVAL data22x[127..0]
+-- Retrieval info: USED_PORT: data230x 0 0 128 0 INPUT NODEFVAL data230x[127..0]
+-- Retrieval info: USED_PORT: data231x 0 0 128 0 INPUT NODEFVAL data231x[127..0]
+-- Retrieval info: USED_PORT: data232x 0 0 128 0 INPUT NODEFVAL data232x[127..0]
+-- Retrieval info: USED_PORT: data233x 0 0 128 0 INPUT NODEFVAL data233x[127..0]
+-- Retrieval info: USED_PORT: data234x 0 0 128 0 INPUT NODEFVAL data234x[127..0]
+-- Retrieval info: USED_PORT: data235x 0 0 128 0 INPUT NODEFVAL data235x[127..0]
+-- Retrieval info: USED_PORT: data236x 0 0 128 0 INPUT NODEFVAL data236x[127..0]
+-- Retrieval info: USED_PORT: data237x 0 0 128 0 INPUT NODEFVAL data237x[127..0]
+-- Retrieval info: USED_PORT: data238x 0 0 128 0 INPUT NODEFVAL data238x[127..0]
+-- Retrieval info: USED_PORT: data239x 0 0 128 0 INPUT NODEFVAL data239x[127..0]
+-- Retrieval info: USED_PORT: data23x 0 0 128 0 INPUT NODEFVAL data23x[127..0]
+-- Retrieval info: USED_PORT: data240x 0 0 128 0 INPUT NODEFVAL data240x[127..0]
+-- Retrieval info: USED_PORT: data241x 0 0 128 0 INPUT NODEFVAL data241x[127..0]
+-- Retrieval info: USED_PORT: data242x 0 0 128 0 INPUT NODEFVAL data242x[127..0]
+-- Retrieval info: USED_PORT: data243x 0 0 128 0 INPUT NODEFVAL data243x[127..0]
+-- Retrieval info: USED_PORT: data244x 0 0 128 0 INPUT NODEFVAL data244x[127..0]
+-- Retrieval info: USED_PORT: data245x 0 0 128 0 INPUT NODEFVAL data245x[127..0]
+-- Retrieval info: USED_PORT: data246x 0 0 128 0 INPUT NODEFVAL data246x[127..0]
+-- Retrieval info: USED_PORT: data247x 0 0 128 0 INPUT NODEFVAL data247x[127..0]
+-- Retrieval info: USED_PORT: data248x 0 0 128 0 INPUT NODEFVAL data248x[127..0]
+-- Retrieval info: USED_PORT: data249x 0 0 128 0 INPUT NODEFVAL data249x[127..0]
+-- Retrieval info: USED_PORT: data24x 0 0 128 0 INPUT NODEFVAL data24x[127..0]
+-- Retrieval info: USED_PORT: data250x 0 0 128 0 INPUT NODEFVAL data250x[127..0]
+-- Retrieval info: USED_PORT: data251x 0 0 128 0 INPUT NODEFVAL data251x[127..0]
+-- Retrieval info: USED_PORT: data252x 0 0 128 0 INPUT NODEFVAL data252x[127..0]
+-- Retrieval info: USED_PORT: data253x 0 0 128 0 INPUT NODEFVAL data253x[127..0]
+-- Retrieval info: USED_PORT: data254x 0 0 128 0 INPUT NODEFVAL data254x[127..0]
+-- Retrieval info: USED_PORT: data255x 0 0 128 0 INPUT NODEFVAL data255x[127..0]
+-- Retrieval info: USED_PORT: data25x 0 0 128 0 INPUT NODEFVAL data25x[127..0]
+-- Retrieval info: USED_PORT: data26x 0 0 128 0 INPUT NODEFVAL data26x[127..0]
+-- Retrieval info: USED_PORT: data27x 0 0 128 0 INPUT NODEFVAL data27x[127..0]
+-- Retrieval info: USED_PORT: data28x 0 0 128 0 INPUT NODEFVAL data28x[127..0]
+-- Retrieval info: USED_PORT: data29x 0 0 128 0 INPUT NODEFVAL data29x[127..0]
+-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
+-- Retrieval info: USED_PORT: data30x 0 0 128 0 INPUT NODEFVAL data30x[127..0]
+-- Retrieval info: USED_PORT: data31x 0 0 128 0 INPUT NODEFVAL data31x[127..0]
+-- Retrieval info: USED_PORT: data32x 0 0 128 0 INPUT NODEFVAL data32x[127..0]
+-- Retrieval info: USED_PORT: data33x 0 0 128 0 INPUT NODEFVAL data33x[127..0]
+-- Retrieval info: USED_PORT: data34x 0 0 128 0 INPUT NODEFVAL data34x[127..0]
+-- Retrieval info: USED_PORT: data35x 0 0 128 0 INPUT NODEFVAL data35x[127..0]
+-- Retrieval info: USED_PORT: data36x 0 0 128 0 INPUT NODEFVAL data36x[127..0]
+-- Retrieval info: USED_PORT: data37x 0 0 128 0 INPUT NODEFVAL data37x[127..0]
+-- Retrieval info: USED_PORT: data38x 0 0 128 0 INPUT NODEFVAL data38x[127..0]
+-- Retrieval info: USED_PORT: data39x 0 0 128 0 INPUT NODEFVAL data39x[127..0]
+-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
+-- Retrieval info: USED_PORT: data40x 0 0 128 0 INPUT NODEFVAL data40x[127..0]
+-- Retrieval info: USED_PORT: data41x 0 0 128 0 INPUT NODEFVAL data41x[127..0]
+-- Retrieval info: USED_PORT: data42x 0 0 128 0 INPUT NODEFVAL data42x[127..0]
+-- Retrieval info: USED_PORT: data43x 0 0 128 0 INPUT NODEFVAL data43x[127..0]
+-- Retrieval info: USED_PORT: data44x 0 0 128 0 INPUT NODEFVAL data44x[127..0]
+-- Retrieval info: USED_PORT: data45x 0 0 128 0 INPUT NODEFVAL data45x[127..0]
+-- Retrieval info: USED_PORT: data46x 0 0 128 0 INPUT NODEFVAL data46x[127..0]
+-- Retrieval info: USED_PORT: data47x 0 0 128 0 INPUT NODEFVAL data47x[127..0]
+-- Retrieval info: USED_PORT: data48x 0 0 128 0 INPUT NODEFVAL data48x[127..0]
+-- Retrieval info: USED_PORT: data49x 0 0 128 0 INPUT NODEFVAL data49x[127..0]
+-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
+-- Retrieval info: USED_PORT: data50x 0 0 128 0 INPUT NODEFVAL data50x[127..0]
+-- Retrieval info: USED_PORT: data51x 0 0 128 0 INPUT NODEFVAL data51x[127..0]
+-- Retrieval info: USED_PORT: data52x 0 0 128 0 INPUT NODEFVAL data52x[127..0]
+-- Retrieval info: USED_PORT: data53x 0 0 128 0 INPUT NODEFVAL data53x[127..0]
+-- Retrieval info: USED_PORT: data54x 0 0 128 0 INPUT NODEFVAL data54x[127..0]
+-- Retrieval info: USED_PORT: data55x 0 0 128 0 INPUT NODEFVAL data55x[127..0]
+-- Retrieval info: USED_PORT: data56x 0 0 128 0 INPUT NODEFVAL data56x[127..0]
+-- Retrieval info: USED_PORT: data57x 0 0 128 0 INPUT NODEFVAL data57x[127..0]
+-- Retrieval info: USED_PORT: data58x 0 0 128 0 INPUT NODEFVAL data58x[127..0]
+-- Retrieval info: USED_PORT: data59x 0 0 128 0 INPUT NODEFVAL data59x[127..0]
+-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
+-- Retrieval info: USED_PORT: data60x 0 0 128 0 INPUT NODEFVAL data60x[127..0]
+-- Retrieval info: USED_PORT: data61x 0 0 128 0 INPUT NODEFVAL data61x[127..0]
+-- Retrieval info: USED_PORT: data62x 0 0 128 0 INPUT NODEFVAL data62x[127..0]
+-- Retrieval info: USED_PORT: data63x 0 0 128 0 INPUT NODEFVAL data63x[127..0]
+-- Retrieval info: USED_PORT: data64x 0 0 128 0 INPUT NODEFVAL data64x[127..0]
+-- Retrieval info: USED_PORT: data65x 0 0 128 0 INPUT NODEFVAL data65x[127..0]
+-- Retrieval info: USED_PORT: data66x 0 0 128 0 INPUT NODEFVAL data66x[127..0]
+-- Retrieval info: USED_PORT: data67x 0 0 128 0 INPUT NODEFVAL data67x[127..0]
+-- Retrieval info: USED_PORT: data68x 0 0 128 0 INPUT NODEFVAL data68x[127..0]
+-- Retrieval info: USED_PORT: data69x 0 0 128 0 INPUT NODEFVAL data69x[127..0]
+-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
+-- Retrieval info: USED_PORT: data70x 0 0 128 0 INPUT NODEFVAL data70x[127..0]
+-- Retrieval info: USED_PORT: data71x 0 0 128 0 INPUT NODEFVAL data71x[127..0]
+-- Retrieval info: USED_PORT: data72x 0 0 128 0 INPUT NODEFVAL data72x[127..0]
+-- Retrieval info: USED_PORT: data73x 0 0 128 0 INPUT NODEFVAL data73x[127..0]
+-- Retrieval info: USED_PORT: data74x 0 0 128 0 INPUT NODEFVAL data74x[127..0]
+-- Retrieval info: USED_PORT: data75x 0 0 128 0 INPUT NODEFVAL data75x[127..0]
+-- Retrieval info: USED_PORT: data76x 0 0 128 0 INPUT NODEFVAL data76x[127..0]
+-- Retrieval info: USED_PORT: data77x 0 0 128 0 INPUT NODEFVAL data77x[127..0]
+-- Retrieval info: USED_PORT: data78x 0 0 128 0 INPUT NODEFVAL data78x[127..0]
+-- Retrieval info: USED_PORT: data79x 0 0 128 0 INPUT NODEFVAL data79x[127..0]
+-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
+-- Retrieval info: USED_PORT: data80x 0 0 128 0 INPUT NODEFVAL data80x[127..0]
+-- Retrieval info: USED_PORT: data81x 0 0 128 0 INPUT NODEFVAL data81x[127..0]
+-- Retrieval info: USED_PORT: data82x 0 0 128 0 INPUT NODEFVAL data82x[127..0]
+-- Retrieval info: USED_PORT: data83x 0 0 128 0 INPUT NODEFVAL data83x[127..0]
+-- Retrieval info: USED_PORT: data84x 0 0 128 0 INPUT NODEFVAL data84x[127..0]
+-- Retrieval info: USED_PORT: data85x 0 0 128 0 INPUT NODEFVAL data85x[127..0]
+-- Retrieval info: USED_PORT: data86x 0 0 128 0 INPUT NODEFVAL data86x[127..0]
+-- Retrieval info: USED_PORT: data87x 0 0 128 0 INPUT NODEFVAL data87x[127..0]
+-- Retrieval info: USED_PORT: data88x 0 0 128 0 INPUT NODEFVAL data88x[127..0]
+-- Retrieval info: USED_PORT: data89x 0 0 128 0 INPUT NODEFVAL data89x[127..0]
+-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
+-- Retrieval info: USED_PORT: data90x 0 0 128 0 INPUT NODEFVAL data90x[127..0]
+-- Retrieval info: USED_PORT: data91x 0 0 128 0 INPUT NODEFVAL data91x[127..0]
+-- Retrieval info: USED_PORT: data92x 0 0 128 0 INPUT NODEFVAL data92x[127..0]
+-- Retrieval info: USED_PORT: data93x 0 0 128 0 INPUT NODEFVAL data93x[127..0]
+-- Retrieval info: USED_PORT: data94x 0 0 128 0 INPUT NODEFVAL data94x[127..0]
+-- Retrieval info: USED_PORT: data95x 0 0 128 0 INPUT NODEFVAL data95x[127..0]
+-- Retrieval info: USED_PORT: data96x 0 0 128 0 INPUT NODEFVAL data96x[127..0]
+-- Retrieval info: USED_PORT: data97x 0 0 128 0 INPUT NODEFVAL data97x[127..0]
+-- Retrieval info: USED_PORT: data98x 0 0 128 0 INPUT NODEFVAL data98x[127..0]
+-- Retrieval info: USED_PORT: data99x 0 0 128 0 INPUT NODEFVAL data99x[127..0]
+-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 8 0 INPUT NODEFVAL sel[7..0]
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 255 128 0 data255x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 254 128 0 data254x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 253 128 0 data253x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 252 128 0 data252x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 251 128 0 data251x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 250 128 0 data250x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 249 128 0 data249x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 248 128 0 data248x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 247 128 0 data247x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 246 128 0 data246x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 245 128 0 data245x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 244 128 0 data244x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 243 128 0 data243x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 242 128 0 data242x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 241 128 0 data241x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 240 128 0 data240x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 239 128 0 data239x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 238 128 0 data238x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 237 128 0 data237x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 236 128 0 data236x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 235 128 0 data235x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 234 128 0 data234x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 233 128 0 data233x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 232 128 0 data232x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 231 128 0 data231x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 230 128 0 data230x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 229 128 0 data229x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 228 128 0 data228x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 227 128 0 data227x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 226 128 0 data226x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 225 128 0 data225x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 224 128 0 data224x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 223 128 0 data223x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 222 128 0 data222x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 221 128 0 data221x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 220 128 0 data220x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 219 128 0 data219x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 218 128 0 data218x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 217 128 0 data217x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 216 128 0 data216x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 215 128 0 data215x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 214 128 0 data214x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 213 128 0 data213x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 212 128 0 data212x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 211 128 0 data211x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 210 128 0 data210x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 209 128 0 data209x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 208 128 0 data208x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 207 128 0 data207x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 206 128 0 data206x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 205 128 0 data205x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 204 128 0 data204x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 203 128 0 data203x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 202 128 0 data202x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 201 128 0 data201x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 200 128 0 data200x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 199 128 0 data199x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 198 128 0 data198x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 197 128 0 data197x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 196 128 0 data196x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 195 128 0 data195x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 194 128 0 data194x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 193 128 0 data193x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 192 128 0 data192x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 191 128 0 data191x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 190 128 0 data190x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 189 128 0 data189x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 188 128 0 data188x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 187 128 0 data187x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 186 128 0 data186x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 185 128 0 data185x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 184 128 0 data184x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 183 128 0 data183x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 182 128 0 data182x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 181 128 0 data181x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 180 128 0 data180x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 179 128 0 data179x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 178 128 0 data178x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 177 128 0 data177x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 176 128 0 data176x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 175 128 0 data175x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 174 128 0 data174x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 173 128 0 data173x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 172 128 0 data172x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 171 128 0 data171x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 170 128 0 data170x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 169 128 0 data169x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 168 128 0 data168x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 167 128 0 data167x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 166 128 0 data166x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 165 128 0 data165x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 164 128 0 data164x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 163 128 0 data163x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 162 128 0 data162x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 161 128 0 data161x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 160 128 0 data160x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 159 128 0 data159x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 158 128 0 data158x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 157 128 0 data157x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 156 128 0 data156x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 155 128 0 data155x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 154 128 0 data154x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 153 128 0 data153x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 152 128 0 data152x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 151 128 0 data151x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 150 128 0 data150x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 149 128 0 data149x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 148 128 0 data148x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 147 128 0 data147x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 146 128 0 data146x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 145 128 0 data145x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 144 128 0 data144x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 143 128 0 data143x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 142 128 0 data142x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 141 128 0 data141x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 140 128 0 data140x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 139 128 0 data139x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 138 128 0 data138x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 137 128 0 data137x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 136 128 0 data136x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 135 128 0 data135x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 134 128 0 data134x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 133 128 0 data133x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 132 128 0 data132x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 131 128 0 data131x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 130 128 0 data130x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 129 128 0 data129x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 128 128 0 data128x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 127 128 0 data127x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 126 128 0 data126x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 125 128 0 data125x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 124 128 0 data124x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 123 128 0 data123x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 122 128 0 data122x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 121 128 0 data121x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 120 128 0 data120x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 119 128 0 data119x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 118 128 0 data118x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 117 128 0 data117x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 116 128 0 data116x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 115 128 0 data115x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 114 128 0 data114x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 113 128 0 data113x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 112 128 0 data112x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 111 128 0 data111x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 110 128 0 data110x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 109 128 0 data109x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 108 128 0 data108x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 107 128 0 data107x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 106 128 0 data106x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 105 128 0 data105x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 104 128 0 data104x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 103 128 0 data103x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 102 128 0 data102x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 101 128 0 data101x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 100 128 0 data100x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 99 128 0 data99x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 98 128 0 data98x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 97 128 0 data97x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 96 128 0 data96x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 95 128 0 data95x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 94 128 0 data94x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 93 128 0 data93x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 92 128 0 data92x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 91 128 0 data91x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 90 128 0 data90x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 89 128 0 data89x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 88 128 0 data88x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 87 128 0 data87x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 86 128 0 data86x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 85 128 0 data85x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 84 128 0 data84x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 83 128 0 data83x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 82 128 0 data82x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 81 128 0 data81x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 80 128 0 data80x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 79 128 0 data79x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 78 128 0 data78x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 77 128 0 data77x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 76 128 0 data76x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 75 128 0 data75x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 74 128 0 data74x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 73 128 0 data73x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 72 128 0 data72x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 71 128 0 data71x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 70 128 0 data70x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 69 128 0 data69x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 68 128 0 data68x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 67 128 0 data67x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 66 128 0 data66x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 65 128 0 data65x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 64 128 0 data64x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 63 128 0 data63x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 62 128 0 data62x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 61 128 0 data61x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 60 128 0 data60x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 59 128 0 data59x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 58 128 0 data58x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 57 128 0 data57x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 56 128 0 data56x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 55 128 0 data55x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 54 128 0 data54x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 53 128 0 data53x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 52 128 0 data52x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 51 128 0 data51x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 50 128 0 data50x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 49 128 0 data49x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 48 128 0 data48x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 47 128 0 data47x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 46 128 0 data46x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 45 128 0 data45x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 44 128 0 data44x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 43 128 0 data43x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 42 128 0 data42x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 41 128 0 data41x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 40 128 0 data40x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 39 128 0 data39x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 38 128 0 data38x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 37 128 0 data37x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 36 128 0 data36x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 35 128 0 data35x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 34 128 0 data34x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 33 128 0 data33x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 32 128 0 data32x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 31 128 0 data31x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 30 128 0 data30x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 29 128 0 data29x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 28 128 0 data28x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 27 128 0 data27x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 26 128 0 data26x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 25 128 0 data25x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 24 128 0 data24x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 23 128 0 data23x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 22 128 0 data22x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 21 128 0 data21x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 20 128 0 data20x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 19 128 0 data19x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 18 128 0 data18x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 17 128 0 data17x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 16 128 0 data16x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 8 0 sel 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/lpm_shiftreg0.bsf b/FPGA_by_Fredi/lpm_shiftreg0.bsf
new file mode 100644
index 0000000..7bc8450
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_shiftreg0.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg0" (rect 24 2 138 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 61 31 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 24 57 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 40 54 56)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 83 40 125 56)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "left shift" (rect 86 18 125 32)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_shiftreg0.cmp b/FPGA_by_Fredi/lpm_shiftreg0.cmp
new file mode 100644
index 0000000..011be2b
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_shiftreg0.cmp
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_shiftreg0
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_shiftreg0.inc b/FPGA_by_Fredi/lpm_shiftreg0.inc
new file mode 100644
index 0000000..765230e
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_shiftreg0.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg0 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_by_Fredi/lpm_shiftreg0.qip b/FPGA_by_Fredi/lpm_shiftreg0.qip
new file mode 100644
index 0000000..7fd6c84
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_shiftreg0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]
diff --git a/FPGA_by_Fredi/lpm_shiftreg0.tdf b/FPGA_by_Fredi/lpm_shiftreg0.tdf
new file mode 100644
index 0000000..0c8820c
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_shiftreg0.tdf
@@ -0,0 +1,98 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg0.tdf
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_shiftreg.inc";
+
+
+
+SUBDESIGN lpm_shiftreg0
+(
+	clock	 : INPUT;
+	shiftin	 : INPUT;
+	shiftout	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_shiftreg_component : lpm_shiftreg WITH (
+			LPM_DIRECTION = "LEFT",
+			LPM_TYPE = "LPM_SHIFTREG",
+			LPM_WIDTH = 16
+			);
+
+BEGIN
+
+	shiftout = lpm_shiftreg_component.shiftout;
+	lpm_shiftreg_component.clock = clock;
+	lpm_shiftreg_component.shiftin = shiftin;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt
index e69de29..0a0000b 100644
--- a/FPGA_by_Fredi/undo_redo.txt
+++ b/FPGA_by_Fredi/undo_redo.txt
@@ -0,0 +1,27 @@
+GED
+
+	Undo Commands
+	     1.	Properties
+	     2.	Move
+	     3.	Delete
+	     4.	Delete
+	     5.	Insert Node
+	     6.	Insert Symbol
+	     7.	Delete
+	     8.	Move
+	     9.	Move
+	    10.	Paste
+	    11.	Delete
+	    12.	Insert Symbol
+	    13.	Move
+	    14.	Paste
+	    15.	Delete
+	    16.	Delete
+
+
+RPW
+
+	Undo Commands
+	     1.	||Compilation Report||Flow Summary
+
+

From b2d17efff1c1f9241e31bb86ca47165fb6cc122f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20G=C3=A1lvez?= <dgalvez75@gmail.com>
Date: Mon, 9 Apr 2018 17:21:35 +0200
Subject: [PATCH 03/16] Sync with Fredi's source tree 15/04/2017

IDE and Blitter work.
---
 FPGA_by_Fredi/.sopc_builder/filters.xml       |    2 +
 FPGA_by_Fredi/.sopc_builder/preferences.xml   |   18 +
 FPGA_by_Fredi/BLITTER.tdf                     |  314 --
 FPGA_by_Fredi/BLITTER.tdf.bak                 |  313 --
 FPGA_by_Fredi/FPGA_DATE.bsf                   |   42 +
 .../lpm_clshift0.inc => FPGA_DATE.inc}        |    7 +-
 FPGA_by_Fredi/FPGA_DATE.qip                   |    5 +
 FPGA_by_Fredi/FPGA_DATE.tdf                   |   79 +
 FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf  |   30 +
 .../FalconIO_SDCard_IDE_CF.vhd                |  221 +-
 .../FalconIO_SDCard_IDE_CF.vhd.bak            | 1153 -----
 .../FalconIO_SDCard_IDE_CF_pgk.vhd.bak        |  406 --
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd        |    4 +-
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd.bak    |  229 -
 .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak    |  202 -
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak    |  202 -
 .../Interrupt_Handler/interrupt_handler.tdf   |   17 +-
 .../interrupt_handler.tdf.bak                 |  382 --
 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt            |   20 -
 FPGA_by_Fredi/UNUSED                          |   27 -
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf   |  110 -
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc   |   15 +-
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip   |    2 -
 FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf   |  110 +-
 .../Video/BLITTER/altsyncram0_wave0.jpg       |  Bin 90072 -> 0 bytes
 .../Video/BLITTER/altsyncram0_waveforms.html  |   13 -
 FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT   |  427 --
 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf  |   54 -
 .../{altsyncram0.cmp => lpm_clshift144.inc}   |   21 +-
 .../Video/BLITTER/lpm_clshift144.qip          |    4 +
 .../Video/BLITTER/lpm_clshift144.tdf          |   94 +
 .../Video/BLITTER/lpm_clshift384.inc          |   25 +
 .../Video/BLITTER/lpm_clshift384.qip          |    5 +
 .../{lpm_clshift0.tdf => lpm_clshift384.tdf}  |   50 +-
 FPGA_by_Fredi/Video/DDR_CTR.tdf               |   58 +-
 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak           |  659 ---
 FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak   |  352 --
 FPGA_by_Fredi/Video/UNUSED                    |  267 -
 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf |    4 +-
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       |  675 ---
 FPGA_by_Fredi/Video/Video.bdf                 | 4450 ++++++++---------
 FPGA_by_Fredi/Video/altdpram0_waveforms.html  |   16 -
 FPGA_by_Fredi/Video/altdpram1_waveforms.html  |   16 -
 FPGA_by_Fredi/Video/altdpram2_waveforms.html  |   16 -
 FPGA_by_Fredi/Video/lpm_blitter.bsf           |   63 +
 .../lpm_clshift0.cmp => lpm_blitter.cmp}      |    9 +-
 FPGA_by_Fredi/Video/lpm_blitter.inc           |   25 +
 FPGA_by_Fredi/Video/lpm_blitter.qip           |    6 +
 FPGA_by_Fredi/Video/lpm_blitter.vhd           |  127 +
 .../Video/lpm_compare1_waveforms.html         |   13 -
 FPGA_by_Fredi/Video/lpm_fifoDZ.bsf            |   32 +-
 FPGA_by_Fredi/Video/lpm_fifoDZ.vhd            |   10 +-
 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html |   13 -
 FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf          |   15 +-
 FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp          |    5 +-
 FPGA_by_Fredi/Video/lpm_fifo_dc0.inc          |    5 +-
 FPGA_by_Fredi/Video/lpm_fifo_dc0.qip          |    2 +-
 FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd          |   43 +-
 .../Video/lpm_fifo_dc0_waveforms.html         |   13 -
 FPGA_by_Fredi/altddio_out0.bsf                |   64 -
 FPGA_by_Fredi/blitter.tdf                     |  604 +++
 FPGA_by_Fredi/blitter.tdf.bak                 |  604 +++
 FPGA_by_Fredi/blitter.tdf.pdf                 |  Bin 0 -> 78291 bytes
 FPGA_by_Fredi/firebee1.asm.rpt                |  128 +
 FPGA_by_Fredi/firebee1.bdf                    |  622 ++-
 FPGA_by_Fredi/firebee1.done                   |    2 +-
 FPGA_by_Fredi/firebee1.fit.summary            |   16 +-
 FPGA_by_Fredi/firebee1.flow.rpt               |  428 ++
 FPGA_by_Fredi/firebee1.map.summary            |   16 +-
 FPGA_by_Fredi/firebee1.pin                    |    2 +-
 FPGA_by_Fredi/firebee1.qsf                    |  183 +-
 FPGA_by_Fredi/firebee1.sim.rpt                |  247 +
 FPGA_by_Fredi/firebee1.tan.summary            |  214 +-
 FPGA_by_Fredi/firebeei1.qws                   |   16 +
 FPGA_by_Fredi/incremental_db/README           |   11 -
 .../firebee1.root_partition.cmp.cdb           |  Bin 957707 -> 0 bytes
 .../firebee1.root_partition.cmp.dfp           |  Bin 33 -> 0 bytes
 .../firebee1.root_partition.cmp.hdb           |  Bin 311894 -> 0 bytes
 .../firebee1.root_partition.cmp.kpt           |  Bin 209 -> 0 bytes
 .../firebee1.root_partition.cmp.logdb         |    5 -
 .../firebee1.root_partition.cmp.rcfdb         |  Bin 1235709 -> 0 bytes
 .../firebee1.root_partition.cmp.re.rcfdb      |  Bin 1334605 -> 0 bytes
 .../firebee1.root_partition.map.cdb           |  Bin 627274 -> 0 bytes
 .../firebee1.root_partition.map.dpi           |  Bin 34612 -> 0 bytes
 .../firebee1.root_partition.map.hdb           |  Bin 322501 -> 0 bytes
 .../firebee1.root_partition.map.kpt           |  Bin 152376 -> 0 bytes
 .../firebee1.root_partition.merge_hb.atm      |  Bin 349010 -> 0 bytes
 FPGA_by_Fredi/lpm_counter0_wave0.jpg          |  Bin 56372 -> 0 bytes
 FPGA_by_Fredi/lpm_counter0_waveforms.html     |   13 -
 FPGA_by_Fredi/lpm_mux0.s19                    |  185 +
 FPGA_by_Fredi/lpm_mux1.bsf                    | 1838 +++++++
 FPGA_by_Fredi/lpm_mux1.cmp                    |  278 +
 FPGA_by_Fredi/lpm_mux1.inc                    |  279 ++
 .../BLITTER/lpm_clshift0.qip => lpm_mux1.qip} |   10 +-
 FPGA_by_Fredi/lpm_mux1.tdf                    | 1105 ++++
 FPGA_by_Fredi/serv_req_info.txt               |  115 -
 FPGA_by_Fredi/undo_redo.txt                   |   27 -
 97 files changed, 9395 insertions(+), 9114 deletions(-)
 create mode 100644 FPGA_by_Fredi/.sopc_builder/filters.xml
 create mode 100644 FPGA_by_Fredi/.sopc_builder/preferences.xml
 delete mode 100644 FPGA_by_Fredi/BLITTER.tdf
 delete mode 100644 FPGA_by_Fredi/BLITTER.tdf.bak
 create mode 100644 FPGA_by_Fredi/FPGA_DATE.bsf
 rename FPGA_by_Fredi/{Video/BLITTER/lpm_clshift0.inc => FPGA_DATE.inc} (89%)
 create mode 100644 FPGA_by_Fredi/FPGA_DATE.qip
 create mode 100644 FPGA_by_Fredi/FPGA_DATE.tdf
 create mode 100644 FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
 delete mode 100644 FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
 delete mode 100644 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
 delete mode 100644 FPGA_by_Fredi/UNUSED
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
 delete mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
 rename FPGA_by_Fredi/Video/BLITTER/{altsyncram0.cmp => lpm_clshift144.inc} (69%)
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.inc
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.qip
 rename FPGA_by_Fredi/Video/BLITTER/{lpm_clshift0.tdf => lpm_clshift384.tdf} (62%)
 delete mode 100644 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
 delete mode 100644 FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
 delete mode 100644 FPGA_by_Fredi/Video/UNUSED
 delete mode 100644 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/lpm_blitter.bsf
 rename FPGA_by_Fredi/Video/{BLITTER/lpm_clshift0.cmp => lpm_blitter.cmp} (81%)
 create mode 100644 FPGA_by_Fredi/Video/lpm_blitter.inc
 create mode 100644 FPGA_by_Fredi/Video/lpm_blitter.qip
 create mode 100644 FPGA_by_Fredi/Video/lpm_blitter.vhd
 delete mode 100644 FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/altddio_out0.bsf
 create mode 100644 FPGA_by_Fredi/blitter.tdf
 create mode 100644 FPGA_by_Fredi/blitter.tdf.bak
 create mode 100644 FPGA_by_Fredi/blitter.tdf.pdf
 create mode 100644 FPGA_by_Fredi/firebee1.asm.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.flow.rpt
 create mode 100644 FPGA_by_Fredi/firebee1.sim.rpt
 create mode 100644 FPGA_by_Fredi/firebeei1.qws
 delete mode 100644 FPGA_by_Fredi/incremental_db/README
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.re.rcfdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.cdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.dpi
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.hdb
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.map.kpt
 delete mode 100644 FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm
 delete mode 100644 FPGA_by_Fredi/lpm_counter0_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/lpm_counter0_waveforms.html
 create mode 100644 FPGA_by_Fredi/lpm_mux0.s19
 create mode 100644 FPGA_by_Fredi/lpm_mux1.bsf
 create mode 100644 FPGA_by_Fredi/lpm_mux1.cmp
 create mode 100644 FPGA_by_Fredi/lpm_mux1.inc
 rename FPGA_by_Fredi/{Video/BLITTER/lpm_clshift0.qip => lpm_mux1.qip} (64%)
 create mode 100644 FPGA_by_Fredi/lpm_mux1.tdf
 delete mode 100644 FPGA_by_Fredi/serv_req_info.txt
 delete mode 100644 FPGA_by_Fredi/undo_redo.txt

diff --git a/FPGA_by_Fredi/.sopc_builder/filters.xml b/FPGA_by_Fredi/.sopc_builder/filters.xml
new file mode 100644
index 0000000..47a9392
--- /dev/null
+++ b/FPGA_by_Fredi/.sopc_builder/filters.xml
@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="9.1sp2" />
diff --git a/FPGA_by_Fredi/.sopc_builder/preferences.xml b/FPGA_by_Fredi/.sopc_builder/preferences.xml
new file mode 100644
index 0000000..80f9764
--- /dev/null
+++ b/FPGA_by_Fredi/.sopc_builder/preferences.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <systemtable>
+  <columns>
+   <connections preferredWidth="30" />
+   <export visible="0" />
+   <irq preferredWidth="34" />
+  </columns>
+ </systemtable>
+ <clocktable>
+  <columns>
+   <clockname preferredWidth="138" />
+   <clocksource preferredWidth="138" />
+   <frequency preferredWidth="119" />
+  </columns>
+ </clocktable>
+ <window width="900" height="600" x="0" y="0" />
+</preferences>
diff --git a/FPGA_by_Fredi/BLITTER.tdf b/FPGA_by_Fredi/BLITTER.tdf
deleted file mode 100644
index 536bd9a..0000000
--- a/FPGA_by_Fredi/BLITTER.tdf
+++ /dev/null
@@ -1,314 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2010 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
--- Created on Sat Jan 15 11:06:17 2011
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
-INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
-
-CONSTANT	BL_SKEW_LF = 255;
-
---  Title Statement (optional)
-TITLE "Blitter";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN BLITTER
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ON : INPUT;
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	DDRCLK0 : INPUT;
-	BLITTER_DIN[127..0] : INPUT;
-	BLITTER_DACK[4..0] : INPUT;
-	SR_BLITTER_DACK : INPUT;
-	BLITTER_RUN : OUTPUT;
-	BLITTER_DOUT[127..0] : OUTPUT;
-	BLITTER_ADR[31..0] : OUTPUT;
-	BLITTER_SIG : OUTPUT;
-	BLITTER_WR : OUTPUT;
-	BLITTER_TA : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_B[3..0]					:NODE;
-	FB_16B[1..0]				:NODE;
-	BLITTER_CS					:NODE;
-	BL_BUSY						:NODE;
-	BL_HRAM_CS 					:NODE;
-	BL_HRAM_ADR[3..0]			:NODE;
-	BL_HRAM_OUT[15..0]			:NODE;
-	BL_HRAM_BE[1..0]			:NODE;
-	BL_SRC_X_INC_CS				:NODE;
-	BL_SRC_X_INC[15..0]			:DFFE;
-	BL_SRC_Y_INC_CS				:NODE;
-	BL_SRC_Y_INC[15..0]			:DFFE;
-	BL_ENDMASK1_CS				:NODE;
-	BL_ENDMASK1[15..0]			:DFFE;
-	BL_ENDMASK2_CS				:NODE;
-	BL_ENDMASK2[15..0]			:DFFE;
-	BL_ENDMASK3_CS				:NODE;
-	BL_ENDMASK3[15..0]			:DFFE;
-	BL_SRC_ADRH_CS				:NODE;
-	BL_SRC_ADRL_CS				:NODE;
-	BL_SRC_ADR[31..0]			:DFFE;
-	BL_DST_X_INC_CS				:NODE;
-	BL_DST_X_INC[15..0]			:DFFE;
-	BL_DST_Y_INC_CS				:NODE;
-	BL_DST_Y_INC[15..0]			:DFFE;
-	BL_DST_ADRH_CS				:NODE;
-	BL_DST_ADRL_CS				:NODE;
-	BL_DST_ADR[31..0]			:DFFE;
-	BL_X_CNT_CS					:NODE;
-	BL_X_CNT[15..0]				:DFFE;
-	BL_Y_CNT_CS					:NODE;
-	BL_Y_CNT[15..0]				:DFFE;
-	BL_HT_OP_CS					:NODE;
-	BL_HT_OP[7..0]				:DFFE;
-	BL_LC_OP[7..0]				:DFFE;
-	BL_LN_CS					:NODE;
-	BL_LN[7..0]					:DFFE;
-	BL_SKEW[7..0]				:DFFE;
-	
-	BL_SKEW_EXT[6..0]			:NODE;
-	BL_SKEW_IN[255..0]			:DFFE;
-	BL_SKEW_OUT[255..0]			:NODE;
-	
-	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
-	BL_READ_SRC					:DFFE;
-	BL_DST_BUFFER[127..0]		:DFFE;
-	BL_READ_DST					:DFFE;
-	
-	HOP_OUT[127..0]				:NODE;
-	
-	COUNT[18..0]				:DFF;
-	
-BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- BLITTER CS
-	BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40  
-	BLITTER_TA = BLITTER_CS;
--- REGISTER
-	-- HALFTON RAM 
-	BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50";			-- $F8A00/20
-	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
-	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
-	BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1] 
-				 # !BL_HRAM_CS & BL_LN[3..0];
-	BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-	-- SRC X INC
-	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510";		-- $F8A20/2
-	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC Y INC
-	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511";		-- $F8A22/2
-	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR HIGH
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
-	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR LOW
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
-	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 1
-	BL_ENDMASK1[].CLK = MAIN_CLK;
-	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514";		-- $F8A28/2
-	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 2
-	BL_ENDMASK2[].CLK = MAIN_CLK;
-	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515";		-- $F8A2A/2
-	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 3
-	BL_ENDMASK3[].CLK = MAIN_CLK;
-	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516";		-- $F8A2C/2
-	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-	-- DST X INC
-	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517";		-- $F8A2E/2
-	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	-- DST Y INC
-	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518";		-- $F8A30/2
-	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- DST ADR HIGH
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
-	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-	-- DST ADR LOW
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
-	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-	-- X COUNT
-	BL_X_CNT[].CLK = MAIN_CLK;
-	BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
-	BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B";			-- $F8A36/2
-	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
-	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-	-- Y COUNT
-	BL_Y_CNT[].CLK = MAIN_CLK;
-	BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
-	BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C";			-- $F8A38/2
-	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
-	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-	-- HALFTONE OP BYT
-	BL_HT_OP[].CLK = MAIN_CLK;
-	BL_HT_OP[] = FB_AD[31..24];
-	BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D";			-- $F8A3A/2
-	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-	-- LOGIC OP BYT
-	BL_LC_OP[].CLK = MAIN_CLK;
-	BL_LC_OP[] = FB_AD[23..16];
-	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;				-- $F8A3B
-	-- LINE NUMBER BYT
-	BL_LN[].CLK = MAIN_CLK;
-	BL_LN[] = !BL_BUSY & FB_AD[31..24];
-	BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E";			-- $F8A3C/2
-	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
-	-- SKEW BYT
-	BL_SKEW[].CLK = MAIN_CLK;
-	BL_SKEW[] = FB_AD[31..24];
-	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;					-- $F8A3D
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						BL_HRAM_CS	    & BL_HRAM_OUT[]
-					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
-					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
-					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
-					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
-					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
-					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
-					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
-					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
-					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
-					  # BL_X_CNT_CS 	& BL_X_CNT[]
-					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
-					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
-					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
-					  ,BLITTER_CS & !nFB_OE); 								-- FFFF8A00-3F/40
------------------------------------------
---  
-	BL_READ_SRC.CLK = DDRCLK0;
-	BL_READ_DST.CLK = DDRCLK0;
-	
--- READY SIGNAL 1 CLOCK SPÄTER
-	BL_DATA_DDR_READY.CLK	= DDRCLK0;
-	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
--- SRC BUFFER LADEN
-	BL_SKEW_IN[].CLK = DDRCLK0;
-	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
-	BL_SKEW_IN[255..128] = BLITTER_DIN[];
-	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
--- DST BUFFER LADEN	
-	BL_DST_BUFFER[].CLK = DDRCLK0;
-	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
-	BL_DST_BUFFER[] = BLITTER_DIN[];
--- SKEW EXTENDET
-	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
-	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
--- SKEW EXT MUX
-	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
--- HOP
-	IF BL_HT_OP[1..0]==B"00" THEN
-		HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-	ELSE 
-		IF BL_HT_OP[1..0]==B"01" THEN
-			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
-		ELSE
-			IF BL_HT_OP[1..0]==B"10" THEN
-				HOP_OUT[] = BL_SKEW_OUT[127..0];
-			ELSE 
-				HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
-			END IF;
-		END IF;
-	END IF;
-
-			
-		
-	BLITTER_RUN = GND; --VCC;
-	BLITTER_SIG = GND; --VCC;
-	BLITTER_WR = GND; --VCC;
-	BL_BUSY = GND;
-	
-	COUNT[] = COUNT[] + 16;
-	COUNT[].CLK = BLITTER_DACK0;
-	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
-	BLITTER_ADR[] = (0, COUNT[]) + 400000;
-	
-END;
-
diff --git a/FPGA_by_Fredi/BLITTER.tdf.bak b/FPGA_by_Fredi/BLITTER.tdf.bak
deleted file mode 100644
index b80e5c2..0000000
--- a/FPGA_by_Fredi/BLITTER.tdf.bak
+++ /dev/null
@@ -1,313 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2010 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
--- Created on Sat Jan 15 11:06:17 2011
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
-INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
-
-CONSTANT	BL_SKEW_LF = 255;
-
---  Title Statement (optional)
-TITLE "Blitter";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN BLITTER
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ON : INPUT;
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	DDRCLK0 : INPUT;
-	BLITTER_DIN[127..0] : INPUT;
-	BLITTER_DACK[4..0] : INPUT;
-	SR_BLITTER_DACK : INPUT;
-	BLITTER_RUN : OUTPUT;
-	BLITTER_DOUT[127..0] : OUTPUT;
-	BLITTER_ADR[31..0] : OUTPUT;
-	BLITTER_SIG : OUTPUT;
-	BLITTER_WR : OUTPUT;
-	BLITTER_TA : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_B[3..0]					:NODE;
-	FB_16B[1..0]				:NODE;
-	BLITTER_CS					:NODE;
-	BL_BUSY						:NODE;
-	BL_HRAM_CS 					:NODE;
-	BL_HRAM_ADR[3..0]			:NODE;
-	BL_HRAM_OUT[15..0]			:NODE;
-	BL_HRAM_BE[1..0]			:NODE;
-	BL_SRC_X_INC_CS				:NODE;
-	BL_SRC_X_INC[15..0]			:DFFE;
-	BL_SRC_Y_INC_CS				:NODE;
-	BL_SRC_Y_INC[15..0]			:DFFE;
-	BL_ENDMASK1_CS				:NODE;
-	BL_ENDMASK1[15..0]			:DFFE;
-	BL_ENDMASK2_CS				:NODE;
-	BL_ENDMASK2[15..0]			:DFFE;
-	BL_ENDMASK3_CS				:NODE;
-	BL_ENDMASK3[15..0]			:DFFE;
-	BL_SRC_ADRH_CS				:NODE;
-	BL_SRC_ADRL_CS				:NODE;
-	BL_SRC_ADR[31..0]			:DFFE;
-	BL_DST_X_INC_CS				:NODE;
-	BL_DST_X_INC[15..0]			:DFFE;
-	BL_DST_Y_INC_CS				:NODE;
-	BL_DST_Y_INC[15..0]			:DFFE;
-	BL_DST_ADRH_CS				:NODE;
-	BL_DST_ADRL_CS				:NODE;
-	BL_DST_ADR[31..0]			:DFFE;
-	BL_X_CNT_CS					:NODE;
-	BL_X_CNT[15..0]				:DFFE;
-	BL_Y_CNT_CS					:NODE;
-	BL_Y_CNT[15..0]				:DFFE;
-	BL_HT_OP_CS					:NODE;
-	BL_HT_OP[7..0]				:DFFE;
-	BL_LC_OP[7..0]				:DFFE;
-	BL_LN_CS					:NODE;
-	BL_LN[7..0]					:DFFE;
-	BL_SKEW[7..0]				:DFFE;
-	
-	BL_SKEW_EXT[6..0]			:NODE;
-	BL_SKEW_IN[255..0]			:DFFE;
-	BL_SKEW_OUT[255..0]			:NODE;
-	
-	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
-	BL_READ_SRC					:DFFE;
-	BL_DST_BUFFER[127..0]		:DFFE;
-	BL_READ_DST					:DFFE;
-	
-	HOP_OUT[127..0]				:NODE;
-	
-	COUNT[18..0]				:DFF;
-	
-BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- BLITTER CS
-	BLITTER_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40  
-	BLITTER_TA = BLITTER_CS;
--- REGISTER
-	-- HALFTON RAM 
-	BL_HRAM_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..5]==H"7C50";			-- $F8A00/20
-	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0 # !BL_HRAM_CS;
-	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1 # !BL_HRAM_CS;
-	BL_HRAM_ADR[] = BL_HRAM_CS & FB_ADR[4..1] 
-				 # !BL_HRAM_CS & BL_LN[3..0];
-	BL_HRAM_OUT[] = altsyncram0(BL_HRAM_ADR[],BL_HRAM_BE[],DDRCLK0,FB_AD[31..16],BL_HRAM_CS & !nFB_WR);
-	-- SRC X INC
-	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C510";		-- $F8A20/2
-	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC Y INC
-	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C511";		-- $F8A22/2
-	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR HIGH
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
-	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR LOW
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
-	BL_SRC_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
-	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 1
-	BL_ENDMASK1[].CLK = MAIN_CLK;
-	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C514";		-- $F8A28/2
-	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 2
-	BL_ENDMASK2[].CLK = MAIN_CLK;
-	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C515";		-- $F8A2A/2
-	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 3
-	BL_ENDMASK3[].CLK = MAIN_CLK;
-	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C516";		-- $F8A2C/2
-	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-	-- DST X INC
-	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_X_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C517";		-- $F8A2E/2
-	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	-- DST Y INC
-	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_Y_INC_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C518";		-- $F8A30/2
-	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- DST ADR HIGH
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[31..16] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_ADRH_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C512";		-- $F8A24/2
-	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-	-- DST ADR LOW
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..0] = !BL_BUSY & FB_AD[31..16];
-	BL_DST_ADRL_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C513";		-- $F8A26/2
-	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-	-- X COUNT
-	BL_X_CNT[].CLK = MAIN_CLK;
-	BL_X_CNT[] = !BL_BUSY & FB_AD[31..16];
-	BL_X_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51B";			-- $F8A36/2
-	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
-	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-	-- Y COUNT
-	BL_Y_CNT[].CLK = MAIN_CLK;
-	BL_Y_CNT[] = !BL_BUSY & FB_AD[31..16];
-	BL_Y_CNT_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51C";			-- $F8A38/2
-	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
-	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-	-- HALFTONE OP BYT
-	BL_HT_OP[].CLK = MAIN_CLK;
-	BL_HT_OP[] = FB_AD[31..24];
-	BL_HT_OP_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51D";			-- $F8A3A/2
-	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-	-- LOGIC OP BYT
-	BL_LC_OP[].CLK = MAIN_CLK;
-	BL_LC_OP[] = FB_AD[23..16];
-	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;				-- $F8A3B
-	-- LINE NUMBER BYT
-	BL_LN[].CLK = MAIN_CLK;
-	BL_LN[] = !BL_BUSY & FB_AD[31..24];
-	BL_LN_CS = !BL_BUSY & !nFB_CS1 & FB_ADR[19..1]==H"7C51E";			-- $F8A3C/2
-	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
-	-- SKEW BYT
-	BL_SKEW[].CLK = MAIN_CLK;
-	BL_SKEW[] = FB_AD[31..24];
-	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;					-- $F8A3D
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						BL_HRAM_CS	    & BL_HRAM_OUT[]
-					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
-					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
-					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
-					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
-					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
-					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
-					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
-					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
-					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
-					  # BL_X_CNT_CS 	& BL_X_CNT[]
-					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
-					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
-					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
-					  ,BLITTER_CS & !nFB_OE); 								-- FFFF8A00-3F/40
------------------------------------------
---  
-	BL_READ_SRC.CLK = DDRCLK0;
-	BL_READ_DST.CLK = DDRCLK0;
-	
--- READY SIGNAL 1 CLOCK SPÄTER
-	BL_DATA_DDR_READY.CLK	= DDRCLK0;
-	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
--- SRC BUFFER LADEN
-	BL_SKEW_IN[].CLK = DDRCLK0;
-	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
-	BL_SKEW_IN[255..128] = BLITTER_DIN[];
-	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
--- DST BUFFER LADEN	
-	BL_DST_BUFFER[].CLK = DDRCLK0;
-	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
-	BL_DST_BUFFER[] = BLITTER_DIN[];
--- SKEW EXTENDET
-	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
-	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
--- SKEW EXT MUX
-	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
--- HOP
-	IF BL_HT_OP[1..0]==B"00" THEN
-		HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-	ELSE 
-		IF BL_HT_OP[1..0]==B"01" THEN
-			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
-		ELSE
-			IF BL_HT_OP[1..0]==B"10" THEN
-				HOP_OUT[] = BL_SKEW_OUT[127..0];
-			ELSE 
-				HOP_OUT[] = BL_SKEW_OUT[127..0] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
-			END IF;
-		END IF;
-	END IF;
-
-			
-		
-	BLITTER_RUN = gnd; --VCC;
-	BLITTER_SIG = gnd; --VCC;
-	BLITTER_WR = gnd; --VCC;
-	
-	COUNT[] = COUNT[] + 16;
-	COUNT[].CLK = BLITTER_DACK0;
-	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
-	BLITTER_ADR[] = (0, COUNT[]) + 400000;
-	
-END;
-
diff --git a/FPGA_by_Fredi/FPGA_DATE.bsf b/FPGA_by_Fredi/FPGA_DATE.bsf
new file mode 100644
index 0000000..fd5ac89
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 88 48)
+	(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 88 24)
+		(output)
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 85 -31 98 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 88 24)(pt 72 24)(line_width 3))
+	)
+	(drawing
+		(text "319037463" (rect 27 18 72 30)(font "Arial" ))
+		(text "32" (rect 77 25 87 37)(font "Arial" ))
+		(line (pt 16 16)(pt 72 16)(line_width 1))
+		(line (pt 72 16)(pt 72 32)(line_width 1))
+		(line (pt 72 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc b/FPGA_by_Fredi/FPGA_DATE.inc
similarity index 89%
rename from FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc
rename to FPGA_by_Fredi/FPGA_DATE.inc
index ccf215e..2aab8ca 100644
--- a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.inc
+++ b/FPGA_by_Fredi/FPGA_DATE.inc
@@ -13,12 +13,11 @@
 --applicable agreement for further details.
 
 
-FUNCTION lpm_clshift0 
+FUNCTION FPGA_DATE 
 (
-	data[255..0],
-	distance[6..0]
+
 )
 
 RETURNS (
-	result[255..0]
+	result[31..0]
 );
diff --git a/FPGA_by_Fredi/FPGA_DATE.qip b/FPGA_by_Fredi/FPGA_DATE.qip
new file mode 100644
index 0000000..8a1183f
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.inc"]
diff --git a/FPGA_by_Fredi/FPGA_DATE.tdf b/FPGA_by_Fredi/FPGA_DATE.tdf
new file mode 100644
index 0000000..6769853
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE.tdf
@@ -0,0 +1,79 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: FPGA_DATE.tdf
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+-- Clearbox generated function header
+FUNCTION FPGA_DATE_lpm_constant_d19 ()
+RETURNS ( result[31..0]);
+
+
+
+
+SUBDESIGN FPGA_DATE
+(
+	result[31..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	FPGA_DATE_lpm_constant_d19_component : FPGA_DATE_lpm_constant_d19;
+
+BEGIN
+
+	result[31..0] = FPGA_DATE_lpm_constant_d19_component.result[31..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "16"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "319037463"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "319037463"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf
new file mode 100644
index 0000000..a611f11
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf
@@ -0,0 +1,30 @@
+--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=13042017 LPM_WIDTH=32 result
+--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN FPGA_DATE_lpm_constant_d19
+( 
+	result[31..0]	:	output;
+) 
+
+BEGIN 
+	result[] = B"00010011000001000010000000010111";
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
index f3aeb16..31728ca 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
@@ -42,6 +42,7 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		CLK2M : IN STD_LOGIC;
 		CLK500k : IN STD_LOGIC;
 		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
 		FB_SIZE0 : IN STD_LOGIC;
 		FB_SIZE1 : IN STD_LOGIC;
 		nFB_BURST : IN STD_LOGIC;
@@ -83,11 +84,12 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		nFB_OE : IN STD_LOGIC;
 		VSYNC : IN STD_LOGIC;
 		HSYNC : IN STD_LOGIC;
+		BLITTER_INT : IN STD_LOGIC;
 		DSP_INT : IN STD_LOGIC;
 		nBLANK : IN STD_LOGIC;
 		FDC_CLK : IN STD_LOGIC;
 		FB_ALE : IN STD_LOGIC;
-		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
+		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 0);
 		nIDE_CS1 : OUT STD_LOGIC;
 		nIDE_CS0 : OUT STD_LOGIC;
 		LP_STR : OUT STD_LOGIC;
@@ -132,7 +134,6 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		DMA_DRQ : OUT STD_LOGIC;
 		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
 		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
 		SCSI_PAR : INOUT STD_LOGIC;
@@ -140,7 +141,8 @@ ENTITY FalconIO_SDCard_IDE_CF IS
 		nSCSI_BUSY : INOUT STD_LOGIC;
 		nSCSI_RST : INOUT STD_LOGIC;
 		SD_CD_DATA3 : INOUT STD_LOGIC;
-		SD_CDM_D1 : INOUT STD_LOGIC
+		SD_CDM_D1 : INOUT STD_LOGIC;
+		VIDEO_TA : IN STD_LOGIC
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 	
@@ -156,7 +158,7 @@ signal RESETn					: STD_LOGIC;
 signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
 signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
 signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
-signal LONG						: STD_LOGIC;	-- WENN  -> 1
+signal LONG						: STD_LOGIC;	-- WENN Long -> 1
 signal FB_ADI					: STD_LOGIC_VECTOR(15 downto 0);	-- gespeicherte writedaten
 signal nResetatio				: STD_LOGIC;	-- reset atari bausteine
 -- KEYBOARD MIDI
@@ -184,7 +186,6 @@ signal SNDCS_I					: STD_LOGIC;
 signal SNDIR_I					: STD_LOGIC;
 signal LP_DIR_X					: STD_LOGIC;
 signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal SND_A_X					: STD_LOGIC_VECTOR(7 downto 0);
 signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
 signal nLP_STR					: STD_LOGIC;
 -- DMA SOUND
@@ -278,10 +279,11 @@ signal SEL_EN					: STD_LOGIC;
 -- IDE
 signal nnIDE_RES				: STD_LOGIC;
 signal IDE_CF_CS				: STD_LOGIC;
-signal IDE_CF_TA				: STD_LOGIC;
-signal NEXT_nIDE_RD				: STD_LOGIC;
-signal NEXT_nIDE_WR				: STD_LOGIC;
-type CMD_STATES is(	IDLE, T1, T6, T7);
+signal IDE_DRIVE0				: STD_LOGIC;
+signal IDE_DRIVE1				: STD_LOGIC;
+signal IDE_DCS					: STD_LOGIC;
+signal IDE_TA					: STD_LOGIC;
+type CMD_STATES is(IDLE,T1,T2,T3,T4,T5,T6,T7,T8,T9);
 signal CMD_STATE				: CMD_STATES;
 signal NEXT_CMD_STATE			: CMD_STATES;
 -- Paddle
@@ -294,13 +296,13 @@ FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
 FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
 
 FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
-				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or 
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_TA = '1' else '0';	--SNDCS = '1' or 
 SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
-           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
-           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
-nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; 
-nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; 
-nDREQ0 <= '0';
+           '1' when IDE_CF_CS = '1' ELSE
+           '1' when   nFB_CS3 = '0' ELSE '0';
+nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+
 -- input daten halten
 process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
 	begin
@@ -329,64 +331,145 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
 			CMD_STATE <= IDLE;
 		elsif rising_edge(MAIN_CLK) then
 				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
-				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
-				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
 			else
 				CMD_STATE <= CMD_STATE; 		-- halten
-				nIDE_RD   <= nIDE_RD;			-- halten
-				nIDE_WR   <= nIDE_WR;			-- halten
 			end if;
 	end process CMD_REG;
 
-	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY)
 	begin
 		case CMD_STATE is
 			when IDLE =>
-				IDE_CF_TA <= '0';
-				if  IDE_CF_CS = '1' then
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T1;
+				IDE_TA <= '0';
+				nIDE_RD <= '1';
+				nIDE_WR <= '1';
+				if IDE_DCS = '1' then
+					if FB_ADR(6) = '0' then
+						if ACP_CONF(18 downto 16) = x"1" then
+							NEXT_CMD_STATE <= T3;
+						else
+							if ACP_CONF(18 downto 16) = x"2"  then
+								NEXT_CMD_STATE <= T2;
+							else
+								NEXT_CMD_STATE <= T1;
+							end if;
+						end if;
+					else
+						if ACP_CONF(22 downto 20) = x"1" then
+							NEXT_CMD_STATE <= T3;
+						else
+							if ACP_CONF(22 downto 20) = x"2" then
+								NEXT_CMD_STATE <= T2;
+							else
+								NEXT_CMD_STATE <= T1;
+							end if;
+						end if;
+					end if;
 				else
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= IDLE; 		 
+					if  IDE_CF_CS = '1' then
+						NEXT_CMD_STATE <= T1;
+					else
+						NEXT_CMD_STATE <= IDLE; 
+					end if;		 
 				end if;
 			when T1 =>
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= not nFB_WR;
-				NEXT_nIDE_WR <=     nFB_WR;
-				NEXT_CMD_STATE <= T6;
-			when T6 =>
-				IF IDE_RDY = '1' then
-					IDE_CF_TA <= '1';
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= T7;
+				IDE_TA <= '0';
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T2;
+			when T2 =>
+				IDE_TA <= '0';
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T3;
+			when T3 =>
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				IF IDE_RDY = '0'  then
+					IDE_TA <= '0';
+					NEXT_CMD_STATE <= T3;
 				else
-					IDE_CF_TA <= '0';
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T6;
+					IDE_TA <= '1';
+					NEXT_CMD_STATE <= T5;
 				end if;
-			when T7 => 
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= '1';
-				NEXT_nIDE_WR <= '1';
+			when T4 => 
+				IDE_TA <= '0';
+				nIDE_RD <= '1';
+				nIDE_WR <= '1';
 				NEXT_CMD_STATE <= IDLE;
+			when T5 => 
+				IDE_TA <= '0';
+				nIDE_RD <= '1';
+				nIDE_WR <= '1';
+				if IDE_DCS = '0' or FB_SIZE0 = '1' or FB_SIZE1 = '1' then 	-- wenn kein cs oder nicht long ->> fertig
+					NEXT_CMD_STATE <= T4;
+				else
+					if FB_ADR(6) = '0' then
+						if ACP_CONF(18 downto 16) = x"1" then
+							NEXT_CMD_STATE <= T9;
+						else
+							if ACP_CONF(18 downto 16) = x"2" then
+								NEXT_CMD_STATE <= T8;
+							else
+								NEXT_CMD_STATE <= T6;
+							end if;
+						end if;
+					else
+						if ACP_CONF(22 downto 20) = x"1" then
+							NEXT_CMD_STATE <= T9;
+						else
+							if ACP_CONF(22 downto 20) = x"2" then
+								NEXT_CMD_STATE <= T8;
+							else
+								NEXT_CMD_STATE <= T6;
+							end if;
+						end if;
+					end if;
+				end if;
+			when T6 => 
+				IDE_TA <= '0';
+				nIDE_RD <= '1';
+				nIDE_WR <= '1';
+				NEXT_CMD_STATE <= T7;
+			when T7 =>
+				IDE_TA <= '0';
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T8;
+			when T8 =>
+				IDE_TA <= '0';
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T9;
+			when T9 =>
+				nIDE_RD <= not nFB_WR;
+				nIDE_WR <=     nFB_WR;
+				IF IDE_RDY = '0'  then
+					IDE_TA <= '0';
+					NEXT_CMD_STATE <= T9;
+				else
+					IDE_TA <= '1';
+					NEXT_CMD_STATE <= T4;
+				end if;
 		end case;
 	end process CMD_DECODER;
 	
-IDE_RES <= not nnIDE_RES and nRSTO;
-IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
-nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
-nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
-nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
-nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
+IDE_RES <= not ACP_CONF(25) and nRSTO; 	-- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO 
+IDE_CF_CS  	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';		-- FFF0'0000-FFF0'007F
+IDE_DRIVE0 	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"99" else '0';		-- FFF0'0099 (19+80!)
+IDE_DRIVE1 	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"D9" else '0';		-- FFF0'00D9 (19+40+80!)
+IDE_DCS    	<= '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else 	-- FFF0'000x 0-3
+               '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"0" else			-- FFF0'000x 0-3
+			   '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else 	-- FFF0'004x 0-3
+               '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"10" else '0';		-- FFF0'004x 0-3
+nCF_CS0    <=     FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 			-- xxxx'xx00-1F
+nCF_CS1    <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 			-- xxxx'xx20-3F
+nIDE_CS0   <=     FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 			-- xxxx'xx40-5F
+nIDE_CS1   <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 			-- xxxx'xx60-7F
+nDREQ0 <= '1';
+FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
+FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
+
 -----------------------------------------------------------------------------------------------------------------------------------------
 -- ACSI, SCSI UND FLOPPY WD1772 
 -------------------------------------------------------------------------------------------------------------------------------------------
@@ -909,7 +992,7 @@ MIDI_OLR <= MIDI_OUT;
 			GPIP_IN(6)			=> not RI,
 			GPIP_IN(5)			=> DINTn,
 			GPIP_IN(4)			=> acia_irq,
-			GPIP_IN(3)			=> DSP_INT,
+			GPIP_IN(3)			=> BLITTER_INT OR DSP_INT,
 			GPIP_IN(2)			=> not CTS,
 			GPIP_IN(1)			=> not DCD,
 			GPIP_IN(0)			=> LP_BUSY,
@@ -948,7 +1031,7 @@ FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "Z
 FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
 DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
          '0' when FDINT = '1' else
-         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
+         '0' when SCSI_INT = '1' AND ACP_CONF(27) = '1' else '1';
  ----------------------------------------------------------------------------
 -- Sound
 ----------------------------------------------------------------------------
@@ -969,8 +1052,15 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
 			DA_IN				=> FB_ADI(15 downto 8),
 			DA_OUT 				=> DA_OUT_X,
 
-			IO_A_IN				=> SND_A,	
-			IO_A_OUT			=> SND_A_X,
+			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
+			IO_A_OUT(7)			=> nnIDE_RES,
+            IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> nLP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+--			IO_A_OUT(2)			=> FDD_D1SEL,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> nSDSEL,
 			-- IO_A_EN			=>, -- Not required.
 			IO_B_IN				=> LP_D,
 			IO_B_OUT			=> LP_D_X,
@@ -985,18 +1075,9 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		--
 SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
 SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
 FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-nnIDE_RES <= SND_A_X(7);
-LP_DIR_X  <= SND_A_X(6);
-LP_STR    <= SND_A_X(5);
-DTR       <= SND_A_X(4); 
-RTS		  <= SND_A_X(3);
--- FDD_D1SEL   <= SND_A_X(2)
-DSA_D	  <= SND_A_X(1);
-nSDSEL    <= SND_A_X(0);
-SND_A <= SND_A_X;
 LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
 LP_DIR <= LP_DIR_X;
-
+LP_STR <= not nLP_STR;
 
 ----------------------------------------------------------------------------
 -- DMA Sound register
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
deleted file mode 100644
index a789c9f..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
+++ /dev/null
@@ -1,1153 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2008 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
--- Created on Tue Sep 08 16:24:20 2009
-
-library work;
-use work.FalconIO_SDCard_IDE_CF_pkg.all;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-
---  Entity Declaration
-
-
---  Entity Declaration
-
-ENTITY FalconIO_SDCard_IDE_CF IS
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	PORT
-	(
-		CLK33M : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		CLK2M : IN STD_LOGIC;
-		CLK500k : IN STD_LOGIC;
-		nFB_CS1 : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		nFB_BURST : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		LP_BUSY : IN STD_LOGIC;
-		nACSI_DRQ : IN STD_LOGIC;
-		nACSI_INT : IN STD_LOGIC;
-		nSCSI_DRQ : IN STD_LOGIC;
-		nSCSI_MSG : IN STD_LOGIC;
-		MIDI_IN : IN STD_LOGIC;
-		RxD : IN STD_LOGIC;
-		CTS : IN STD_LOGIC;
-		RI : IN STD_LOGIC;
-		DCD : IN STD_LOGIC;
-		AMKB_RX : IN STD_LOGIC;
-		PIC_AMKB_RX : IN STD_LOGIC;
-		IDE_RDY : IN STD_LOGIC;
-		IDE_INT : IN STD_LOGIC;
-		WP_CS_CARD : IN STD_LOGIC;
-		nINDEX : IN STD_LOGIC;
-		TRACK00 : IN STD_LOGIC;
-		nRD_DATA : IN STD_LOGIC;
-		nDCHG : IN STD_LOGIC;
-		SD_DATA0 : IN STD_LOGIC;
-		SD_DATA1 : IN STD_LOGIC;
-		SD_DATA2 : IN STD_LOGIC;
-		SD_CARD_DEDECT : IN STD_LOGIC;
-		SD_WP : IN STD_LOGIC;
-		nDACK0 : IN STD_LOGIC;
-		nFB_WR : INOUT STD_LOGIC;
-		WP_CF_CARD : IN STD_LOGIC;
-		nWP : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		nRSTO : IN STD_LOGIC;
-		HD_DD : IN STD_LOGIC;
-		nSCSI_C_D : IN STD_LOGIC;
-		nSCSI_I_O : IN STD_LOGIC;
-		CLK2M4576 : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		VSYNC : IN STD_LOGIC;
-		HSYNC : IN STD_LOGIC;
-		DSP_INT : IN STD_LOGIC;
-		nBLANK : IN STD_LOGIC;
-		FDC_CLK : IN STD_LOGIC;
-		FB_ALE : IN STD_LOGIC;
-		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
-		nIDE_CS1 : OUT STD_LOGIC;
-		nIDE_CS0 : OUT STD_LOGIC;
-		LP_STR : OUT STD_LOGIC;
-		LP_DIR : OUT STD_LOGIC;
-		nACSI_ACK : OUT STD_LOGIC;
-		nACSI_RESET : OUT STD_LOGIC;
-		nACSI_CS : OUT STD_LOGIC;
-		ACSI_DIR : OUT STD_LOGIC;
-		ACSI_A1 : OUT STD_LOGIC;
-		nSCSI_ACK : OUT STD_LOGIC;
-		nSCSI_ATN : OUT STD_LOGIC;
-		SCSI_DIR : OUT STD_LOGIC;
-		SD_CLK : OUT STD_LOGIC;
-		YM_QA : OUT STD_LOGIC;
-		YM_QC : OUT STD_LOGIC;
-		YM_QB : OUT STD_LOGIC;
-		nSDSEL : OUT STD_LOGIC;
-		STEP : OUT STD_LOGIC;
-		MOT_ON : OUT STD_LOGIC;
-		nRP_LDS : OUT STD_LOGIC;
-		nRP_UDS : OUT STD_LOGIC;
-		nROM4 : OUT STD_LOGIC;
-		nROM3 : OUT STD_LOGIC;
-		nCF_CS1 : OUT STD_LOGIC;
-		nCF_CS0 : OUT STD_LOGIC;
-		nIDE_RD : INOUT STD_LOGIC;
-		nIDE_WR : INOUT STD_LOGIC;
-		AMKB_TX : buffer STD_LOGIC;
-		IDE_RES : OUT STD_LOGIC;
-		DTR : OUT STD_LOGIC;
-		RTS : OUT STD_LOGIC;
-		TxD : OUT STD_LOGIC;
-		MIDI_OLR : OUT STD_LOGIC;
-		MIDI_TLR : OUT STD_LOGIC;
-		nDREQ0 : OUT STD_LOGIC;
-		DSA_D : OUT STD_LOGIC;
-		nMFP_INT : OUT STD_LOGIC;
-		FALCON_IO_TA : OUT STD_LOGIC;
-		STEP_DIR : OUT STD_LOGIC;
-		WR_DATA : OUT STD_LOGIC;
-		WR_GATE : OUT STD_LOGIC;
-		DMA_DRQ : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
-		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SND_A : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
-		SCSI_PAR : INOUT STD_LOGIC;
-		nSCSI_SEL : INOUT STD_LOGIC;
-		nSCSI_BUSY : INOUT STD_LOGIC;
-		nSCSI_RST : INOUT STD_LOGIC;
-		SD_CD_DATA3 : INOUT STD_LOGIC;
-		SD_CDM_D1 : INOUT STD_LOGIC
-	);
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-	
-END FalconIO_SDCard_IDE_CF;
-
-
---  Architecture Body
-
-ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
--- system
-signal SYS_CLK					: STD_LOGIC;
-signal RESETn					: STD_LOGIC;
-signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
-signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
-signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
-signal LONG						: STD_LOGIC;	-- WENN  -> 1
-signal FB_ADI					: STD_LOGIC_VECTOR(15 downto 0);	-- gespeicherte writedaten
-signal nResetatio				: STD_LOGIC;	-- reset atari bausteine
--- KEYBOARD MIDI
-signal ACIA_CS_I				: STD_LOGIC;
-signal IRQ_KEYBDn				: STD_LOGIC;
-signal IRQ_MIDIn				: STD_LOGIC;
-signal KEYB_RxD					: STD_LOGIC;
-signal AMKB_REG					: STD_LOGIC_VECTOR(3 downto 0);
-signal AMKB_TX_sync				: std_logic;
-signal MIDI_OUT					: STD_LOGIC;
-signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
-signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
--- MFP
-signal MFP_CS					: STD_LOGIC;
-signal MFP_INTACK				: STD_LOGIC;
-signal LDS						: STD_LOGIC;
-signal acia_irq					: STD_LOGIC;
-signal DTACK_OUT_MFPn			: STD_LOGIC;
-signal DINTn					: STD_LOGIC;
-signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
-signal TDO						: STD_LOGIC;
--- SOUND
-signal SNDCS					: STD_LOGIC;
-signal SNDCS_I					: STD_LOGIC;
-signal SNDIR_I					: STD_LOGIC;
-signal LP_DIR_X					: STD_LOGIC;
-signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal SND_A_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal nLP_STR					: STD_LOGIC;
--- DMA SOUND
-signal dma_snd_cs				: STD_LOGIC;
-signal sndmactl					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndbashi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndbasmi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndbaslo					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndadrhi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndadrmi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndadrlo					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndendhi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndendmi					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndendlo					: STD_LOGIC_VECTOR(7 downto 0);
-signal sndmode					: STD_LOGIC_VECTOR(7 downto 0);
--- DIV
-signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
-signal ROM_CS					: STD_LOGIC;
--- DMA UND FLOPPY
-signal DMA_DATEN_CS				: STD_LOGIC;
-signal DMA_MODUS_CS				: STD_LOGIC;
-signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
-signal WDC_BSL_CS				: STD_LOGIC;
-signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
-signal HD_DD_OUT				: STD_LOGIC;
-signal FDCS_In					: STD_LOGIC;
-signal CA0						: STD_LOGIC;
-signal CA1						: STD_LOGIC;
-signal CA2						: STD_LOGIC;
-signal FDINT					: STD_LOGIC;
-signal FDRQ						: STD_LOGIC;
-signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
-signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_TOP_CS				: STD_LOGIC;
-signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_HIGH_CS				: STD_LOGIC;
-signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_MID_CS				: STD_LOGIC;
-signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_LOW_CS				: STD_LOGIC;
-signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
-signal DMA_DIRM_CS				: STD_LOGIC;
-signal DMA_ADR_CS				: STD_LOGIC;
-signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
-signal DMA_DIR_OLD				: STD_LOGIC;
-signal DMA_BYT_CNT_CS			: STD_LOGIC;
-signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
-signal CLR_FIFO					: STD_LOGIC;
-signal DMA_DRQ_I				: STD_LOGIC;
-signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
-signal DMA_DRQQ					: STD_LOGIC;
-signal DMA_DRQ_Q				: STD_LOGIC;
-signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
-signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
-signal RDF_RDE					: STD_LOGIC;
-signal RDF_WRE					: STD_LOGIC;
-signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
-signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
-signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
-signal WRF_RDE					: STD_LOGIC;
-signal WRF_WRE					: STD_LOGIC;
-signal nFDC_WR					: STD_LOGIC;
-type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
-signal FCF_STATE				: FCF_STATES;
-signal NEXT_FCF_STATE			: FCF_STATES;
-signal DMA_REQ					: STD_LOGIC;
-signal FDC_CS					: STD_LOGIC;
-signal FCF_CS					: STD_LOGIC;
-signal FCF_APH					: STD_LOGIC;
-signal DMA_AZ_CS				: STD_LOGIC;
-signal DMA_ACTIV				: STD_LOGIC;
-signal DMA_ACTIV_NEW			: STD_LOGIC;
-signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
--- SCSI
-signal SCSI_CS					: STD_LOGIC;
-signal SCSI_CSn					: STD_LOGIC;
-signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
-signal nSCSI_DACK				: STD_LOGIC;
-signal SCSI_DRQ					: STD_LOGIC;
-signal SCSI_INT					: STD_LOGIC;
-signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
-signal DB_EN					: STD_LOGIC;
-signal DBP_OUTn					: STD_LOGIC;
-signal DBP_EN					: STD_LOGIC;
-signal RST_OUTn					: STD_LOGIC;
-signal RST_EN					: STD_LOGIC;
-signal BSY_OUTn					: STD_LOGIC;
-signal BSY_EN					: STD_LOGIC;
-signal SEL_OUTn					: STD_LOGIC;
-signal SEL_EN					: STD_LOGIC;
--- IDE
-signal nnIDE_RES				: STD_LOGIC;
-signal IDE_CF_CS				: STD_LOGIC;
-signal IDE_CF_TA				: STD_LOGIC;
-signal NEXT_nIDE_RD				: STD_LOGIC;
-signal NEXT_nIDE_WR				: STD_LOGIC;
-type CMD_STATES is(	IDLE, T1, T6, T7);
-signal CMD_STATE				: CMD_STATES;
-signal NEXT_CMD_STATE			: CMD_STATES;
--- Paddle
-signal paddle_cs				: STD_LOGIC;
-
-BEGIN
-LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
-BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
-FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
-FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
-
-FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
-				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or 
-SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
-           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
-           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
-nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; 
-nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; 
-nDREQ0 <= '0';
--- input daten halten
-process(MAIN_CLK, nFB_WR, FB_AD(31 downto 16), FB_ADI(15 downto 0))
-	begin
-		if rising_edge(MAIN_CLK) then
-			IF nFB_WR = '0' THEN
-				FB_ADI <= FB_AD(31 downto 16); 
-			ELSE
-				FB_ADI <= FB_ADI; 
-			end if;
-		ELSE
-			FB_ADI <= FB_ADI; 
-		end if;
-	END PROCESS;
-----------------------------------------------------------------------------
--- SD
-----------------------------------------------------------------------------
-SD_CLK <= 'Z';
-SD_CD_DATA3 <= 'Z';
-SD_CDM_D1 <= 'Z';
-----------------------------------------------------------------------------
--- IDE
-----------------------------------------------------------------------------
-CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
-	begin
-		if nRSTO = '0' then
-			CMD_STATE <= IDLE;
-		elsif rising_edge(MAIN_CLK) then
-				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
-				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
-				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
-			else
-				CMD_STATE <= CMD_STATE; 		-- halten
-				nIDE_RD   <= nIDE_RD;			-- halten
-				nIDE_WR   <= nIDE_WR;			-- halten
-			end if;
-	end process CMD_REG;
-
-	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
-	begin
-		case CMD_STATE is
-			when IDLE =>
-				IDE_CF_TA <= '0';
-				if  IDE_CF_CS = '1' then
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T1;
-				else
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= IDLE; 		 
-				end if;
-			when T1 =>
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= not nFB_WR;
-				NEXT_nIDE_WR <=     nFB_WR;
-				NEXT_CMD_STATE <= T6;
-			when T6 =>
-				IF IDE_RDY = '1' then
-					IDE_CF_TA <= '1';
-					NEXT_nIDE_RD <= '1';
-					NEXT_nIDE_WR <= '1';
-					NEXT_CMD_STATE <= T7;
-				else
-					IDE_CF_TA <= '0';
-					NEXT_nIDE_RD <= not nFB_WR;
-					NEXT_nIDE_WR <=     nFB_WR;
-					NEXT_CMD_STATE <= T6;
-				end if;
-			when T7 => 
-				IDE_CF_TA <= '0';
-				NEXT_nIDE_RD <= '1';
-				NEXT_nIDE_WR <= '1';
-				NEXT_CMD_STATE <= IDLE;
-		end case;
-	end process CMD_DECODER;
-	
-IDE_RES <= not nnIDE_RES and nRSTO;
-IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
-nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
-nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
-			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
-nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
-nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
-			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
------------------------------------------------------------------------------------------------------------------------------------------
--- ACSI, SCSI UND FLOPPY WD1772 
--------------------------------------------------------------------------------------------------------------------------------------------
--- daten read fifo
-	RDF: dcfifo0
-		port map(
-			aclr				=> CLR_FIFO,
-			data				=> RDF_DIN,
-			rdclk				=> MAIN_CLK,
-			rdreq				=> RDF_RDE,
-			wrclk				=> FDC_CLK,
-			wrreq				=> RDF_WRE,
-			q					=> RDF_DOUT,
-			wrusedw				=> RDF_AZ
-	);
-FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
-FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
-RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
-FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
-RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
--- daten write fifo
-	WRF: dcfifo1
-		port map(
-			aclr				=> CLR_FIFO,
-			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
-			rdclk				=> FDC_CLK,
-			rdreq				=> WRF_RDE,
-			wrclk				=> MAIN_CLK,
-			wrreq				=> WRF_WRE,
-			q					=> WRF_DOUT,
-			rdusedw				=> WRF_AZ
-	);
-CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_ADI(7 downto 0); 							-- BEI DMA WRITE <-FIFO SONST <-FB
-DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
-FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
--- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
-	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
-	begin
-		if nRSTO = '0' THEN
-			WRF_WRE <= '0';
-		elsif rising_edge(MAIN_CLK) then
-				IF FCF_APH = '1' and nFB_WR = '0' then
-					WRF_WRE <= '1';
-				else
-					WRF_WRE <= '0';
-				end if;
-			else
-				WRF_WRE <= WRF_WRE;
-			end if;
-	END PROCESS;
- 
-FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
-	begin
-		if nRSTO = '0' then
-			FCF_STATE <= FCF_IDLE;
-			DMA_ACTIV <= '0';
-		elsif rising_edge(FDC_CLK) then
-				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
-				DMA_ACTIV <= DMA_ACTIV_NEW;
-			else
-				FCF_STATE <= FCF_STATE; 					-- halten
-				DMA_ACTIV <= DMA_ACTIV;
-			end if;
-	end process FCF_REG;
-
-FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
-	begin
-		if nRSTO = '0' then
-			FDC_OUT <= x"00";
-		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
-				FDC_OUT <= CD_OUT_FDC; 						-- set
-			else
-				FDC_OUT <= FDC_OUT; 						-- halten
-			end if;
-	end process FDC_REG;
-
-DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
-FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
-SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
-
-	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
-	begin
-		case FCF_STATE is
-			when FCF_IDLE =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				nSCSI_DACK <= '1';
-				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
-					DMA_ACTIV_NEW <= DMA_REQ;
-					NEXT_FCF_STATE <= FCF_T0;
-				else
-					DMA_ACTIV_NEW <= '0';
-					NEXT_FCF_STATE <= FCF_IDLE; 		 
-				end if;
-			when FCF_T0 =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				nSCSI_DACK <= '1';
-				DMA_ACTIV_NEW <= DMA_REQ;
-				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
-				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
-					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
-				else
-					NEXT_FCF_STATE <= FCF_T1;
-				end if;
-			when FCF_T1 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T2;
-			when FCF_T2 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T3;
-			when FCF_T3 =>
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
-				NEXT_FCF_STATE <= FCF_T6;
-			when FCF_T6 =>
-				WRF_RDE <= '0';
-				DMA_ACTIV_NEW <= DMA_ACTIV;
-				SCSI_CSn <= not SCSI_CS;
-				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
-				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
-				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
-				NEXT_FCF_STATE <= FCF_T7;
-			when FCF_T7 =>
-				SCSI_CSn <= '1';
-				FDCS_In <= '1';
-				RDF_WRE <= '0';
-				WRF_RDE <= '0';
-				nSCSI_DACK <= '1';
-				DMA_ACTIV_NEW <= '0';
-				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
-					NEXT_FCF_STATE <= FCF_T7;
-				else
-					NEXT_FCF_STATE <= FCF_IDLE; 		 
-				end if;
-		end case;
-	end process FCF_DECODER;
-
-	I_FDC: WF1772IP_TOP_SOC
-		port map(
-            CLK					=> FDC_CLK,
-			RESETn				=> nResetatio,
-			CSn					=> FDCS_In,
-			RWn					=> nFDC_WR,
-			A1					=> CA2,
-			A0					=> CA1,
-			DATA_IN				=> CD_IN_FDC,
-			DATA_OUT			=> CD_OUT_FDC,
---			DATA_EN				=> CD_EN_FDC,
-			RDn					=> nRD_DATA,
-			TR00n				=> TRACK00,
-			IPn					=> nINDEX,
-			WPRTn				=> nWP,
-			DDEn				=> '0', -- Fixed to MFM.
-			HDTYPE				=> HD_DD_OUT,  
-			MO					=> MOT_ON,
-			WG					=> WR_GATE,
-			WD					=> WR_DATA,
-			STEP				=> STEP,
-			DIRC				=> STEP_DIR,
-			DRQ					=> DMA_DRQ_I,
-			INTRQ				=> FDINT 
-		);
-DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
-DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
-WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
-HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
-nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
-CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
-CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
-CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
-FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
-                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
-      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
---- WDC BSL REGISTER -------------------------------------------------------
-	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
-	begin
-		if nRSTO = '0' THEN
-			WDC_BSL <= "00";
-		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
-			IF FB_B0 = '1' THEN
-				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
-			else
-				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
-			end if;
-		end if;
-	END PROCESS;
---- DMA MODUS REGISTER -------------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
-	begin
-		if nRSTO = '0' THEN
-			DMA_MODUS <= x"0000";
-		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
-			IF FB_B0 = '1' THEN
-				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
-			else
-				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
-			end if;
-			IF FB_B1 = '1' THEN
-				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
-			else
-				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
-			end if;
-		else
-			DMA_MODUS <= DMA_MODUS;
-		end if;
-	END PROCESS;
--- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
-	begin
-		if nRSTO = '0' or CLR_FIFO = '1' THEN
-			DMA_BYT_CNT <= x"00000000";													 
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
-				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
-				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
-				DMA_BYT_CNT(8 downto 0) <= "000000000";
-			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
-					DMA_BYT_CNT <= FB_AD;
-				else
-					DMA_BYT_CNT <= DMA_BYT_CNT;
-				end if;
-	END PROCESS;
---------------------------------------------------------------------
-FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-DMA_STATUS(0) <= '1';													-- DMA OK
-DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
-DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
-DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
-            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
-DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
--- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
-	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
-	begin
-		if nRSTO = '0' THEN
-			DMA_DRQ_REG <= "00";
-		elsif rising_edge(FDC_CLK) then
-				DMA_DRQ_REG(0) <= DMA_DRQQ;
-				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
-			else
-				DMA_DRQ_REG <= DMA_DRQ_REG;
-			end if;
-	END PROCESS;
--- DMA ADRESSE ------------------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
-	begin
-		if nRSTO = '0' THEN
-			DMA_TOP <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
-				DMA_TOP <= FB_AD(31 downto 24);
-			else 
-				DMA_TOP <= DMA_TOP;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
-	begin
-		if nRSTO = '0' THEN
-			DMA_HIGH <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
-				DMA_HIGH <= FB_AD(23 downto 16);
-			else
-				DMA_HIGH <= DMA_HIGH;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
-	begin
-		DMA_MID <= DMA_MID;
-		if nRSTO = '0' THEN
-			DMA_MID <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
-				if DMA_MID_CS = '1' then
-					DMA_MID <= FB_AD(23 downto 16);
-				elsif DMA_ADR_CS = '1' then
-						DMA_MID <= FB_AD(15 downto 8);
-					end if;
-			end if;
-	END PROCESS;
-	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
-	begin
-		DMA_LOW <= DMA_LOW;
-		if nRSTO = '0' THEN
-			DMA_LOW <= x"00";
-		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
-				if DMA_LOW_CS = '1'then
-					DMA_LOW <= FB_AD(23 downto 16);
-				elsif DMA_ADR_CS = '1' then
-						DMA_LOW <= FB_AD(7 downto 0);
-					end if;
-			end if;
-	END PROCESS;
---------------------------------------------------------------------------------------------
-DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
-DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
-DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
-DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
-FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
--- DIRECTZUGRIFF
-DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
-DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
-DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
-FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
--- DMA RW TOGGLE ------------------------------------------
-	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
-	begin
-		if nRSTO = '0' THEN
-			DMA_DIR_OLD <= '0';
-		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
-				DMA_DIR_OLD <= DMA_MODUS(8);
-			else
-				DMA_DIR_OLD <= DMA_DIR_OLD;
-			end if;
-	END PROCESS;
-CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
--- SCSI ----------------------------------------------------------------------------------
-    I_SCSI: WF5380_TOP_SOC
-        port map(
-            CLK					=> FDC_CLK,
-            RESETn				=> nResetatio,
-			ADR			        => CA2 & CA1 & CA0,
-			DATA_IN		        => CD_IN_FDC,	
-			DATA_OUT			=> SCSI_DOUT,
-			--DATA_EN			: out bit;
-            -- Bus and DMA controls:
-			CSn			        => SCSI_CSn,
-			RDn		            => (not nFDC_WR) or (not SCSI_CS),
-			WRn	                =>      nFDC_WR  or (not SCSI_CS),
-            EOPn                => '1',
-			DACKn	            => nSCSI_DACK,
-			DRQ		            => SCSI_DRQ,
-			INT		            => SCSI_INT,
---            READY                	=> 
-            -- SCSI bus:
-            DB_INn		        => SCSI_D,
-            DB_OUTn		        => DB_OUTn,
-            DB_EN               => DB_EN,
-            DBP_INn		        => SCSI_PAR,
-            DBP_OUTn	        => DBP_OUTn,
-            DBP_EN              => DBP_EN,				-- wenn 1 dann output
-            RST_INn             => nSCSI_RST,
-            RST_OUTn            => RST_OUTn,
-            RST_EN              => RST_EN,
-            BSY_INn             => nSCSI_BUSY,
-            BSY_OUTn            => BSY_OUTn,
-            BSY_EN              => BSY_EN,
-            SEL_INn             => nSCSI_SEL,
-            SEL_OUTn            => SEL_OUTn,
-            SEL_EN              => SEL_EN,
-            ACK_INn             => '1',
-            ACK_OUTn            => nSCSI_ACK,
---            ACK_EN              => ACK_EN,
-            ATN_INn             => '1',
-            ATN_OUTn            => nSCSI_ATN,
---            ATN_EN              => ATN_EN,
-            REQ_INn             => nSCSI_DRQ,
---            REQ_OUTn            => REQ_OUTn,
---            REQ_EN              => REQ_EN,
-            IOn_IN              => nSCSI_I_O,
---            IOn_OUT             => IOn_OUT,
---            IO_EN               => IO_EN,
-            CDn_IN              => nSCSI_C_D,
---            CDn_OUT             => CDn_OUT,
---            CD_EN               => CD_EN,
-            MSG_INn             => nSCSI_MSG
---            MSG_OUTn            => MSG_OUTn,
---            MSG_EN              => MSG_EN
-        );              
--- SCSI ACSI ---------------------------------------------------------------
-SCSI_D <= "ZZZZZZZZ";--DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
-SCSI_DIR <= '1';-- when DB_EN = '1' else '1';	 
-SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
-nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
-nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
-nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
-ACSI_DIR <= '0';
-ACSI_D <= "ZZZZZZZZ";
-nACSI_CS <= '1';
-ACSI_A1 <= CA1;
-nACSI_RESET <= nRSTO;
-nACSI_ACK <= '1';
-nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
-----------------------------------------------------------------------------
--- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
-----------------------------------------------------------------------------
-ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
-nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
-nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
-----------------------------------------------------------------------------
--- ACIA KEYBOARD
-----------------------------------------------------------------------------
-	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
-	  port map(
-			CLK					=> MAIN_CLK,
-			RESETn				=> nResetatio,
-
-			CS2n				=> FB_ADR(2),
-			CS1					=> '1',
-			CS0					=> ACIA_CS_I,
-			E					=> ACIA_CS_I,
-			RWn					=> nFB_WR,
-			RS					=> FB_ADR(1),
-
-			DATA_IN				=> FB_ADI(15 downto 8),
-			DATA_OUT			=> DATA_OUT_ACIA_I,
---			DATA_EN				=> DATA_EN_ACIA_I,
-
-			TXCLK				=> CLK500k,
-			RXCLK				=> CLK500k,
-			RXDATA				=> KEYB_RxD,
-
-			CTSn				=> '0',
-			DCDn				=> '0',
-        
-			IRQn				=> IRQ_KEYBDn,
-			TXDATA				=> AMKB_TX_sync
-			--RTSn				=> -- Not used.
-		);                                              
-ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
-KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL  // 
-FB_AD(31 downto 24) <= DATA_OUT_ACIA_I  when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else  
-					   DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- AMKB_TX: SPIKES AUSFILTERN  und sychronisieren ------------------------------------------
-	process(CLK2M, AMKB_RX, AMKB_REG)
-	begin
-		if rising_edge(CLK500k) then
-			AMKB_TX <= AMKB_TX_sync;
-			IF AMKB_RX = '0' THEN
-				IF AMKB_REG < 8 THEN
-					AMKB_REG <= "0000";
-				ELSE
-					AMKB_REG <= AMKB_REG - 1;
-				END IF;
-			ELSE
-				IF AMKB_REG > 7 THEN
-					AMKB_REG <= "1111";
-				ELSE
-					AMKB_REG <= AMKB_REG + 1;
-				END IF;
-			END IF;
-		ELSE
-			AMKB_TX <= AMKB_TX;
-			AMKB_REG <= AMKB_REG;
-		end if;
-	END PROCESS;
--- acia interrupt  ------------------------------------------
-acia_irq <= '0' when IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' else '1';
-----------------------------------------------------------------------------
--- ACIA MIDI
-----------------------------------------------------------------------------
-	I_ACIA_MIDI: WF6850IP_TOP_SOC
-		port map(
-			CLK					=> MAIN_CLK,
-			RESETn				=> nResetatio,
-
-			CS2n				=> '0',
-			CS1					=> FB_ADR(2),
-			CS0					=> ACIA_CS_I,
-            E					=> ACIA_CS_I,
-			RWn					=> nFB_WR,
-			RS					=> FB_ADR(1),
-
-			DATA_IN				=> FB_ADI(15 downto 8),
-			DATA_OUT			=> DATA_OUT_ACIA_II,
---			DATA_EN				=> DATA_EN_ACIA_II,
-
-			TXCLK				=> CLK500k,
-			RXCLK				=> CLK500k,
-			RXDATA				=> MIDI_IN,
-			CTSn				=> '0',
-			DCDn				=> '0',
-        
-			IRQn				=> IRQ_MIDIn,
-			TXDATA				=> MIDI_OUT
-			--RTSn				=> -- Not used.
-	    );
-MIDI_TLR <= MIDI_IN;
-MIDI_OLR <= MIDI_OUT;
-----------------------------------------------------------------------------
--- MFP
-----------------------------------------------------------------------------
-	I_MFP: WF68901IP_TOP_SOC
-		port map(  
-			-- System control:
-			CLK					=> not MAIN_CLK,
-			RESETn				=> nResetatio,
-			-- Asynchronous bus control:
-			DSn					=> not LDS,
-			CSn					=> not MFP_CS,
-			RWn					=> nFB_WR,
- 			DTACKn				=> DTACK_OUT_MFPn,
-			-- Data and Adresses:
-			RS					=> FB_ADR(5 downto 1),
-			DATA_IN				=> FB_AD(23 downto 16),
-			DATA_OUT			=> DATA_OUT_MFP,
---			DATA_EN				=> DATA_EN_MFP,
-			GPIP_IN(7)			=> not DMA_DRQ_Q,
-			GPIP_IN(6)			=> not RI,
-			GPIP_IN(5)			=> DINTn,
-			GPIP_IN(4)			=> acia_irq,
-			GPIP_IN(3)			=> DSP_INT,
-			GPIP_IN(2)			=> not CTS,
-			GPIP_IN(1)			=> not DCD,
-			GPIP_IN(0)			=> LP_BUSY,
-			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
-			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
-			-- Interrupt control:
-			IACKn				=> not MFP_INTACK,
-			IEIn				=> '0',
-			-- IEOn				=>, -- Not used.
-			IRQn				=> nMFP_INT,
-			-- Timers and timer control:
-			XTAL1				=> CLK2M4576,
-            TAI					=> '0',
-			TBI				   	=> nBLANK,
-            -- TAO				=>,
-			-- TBO				=>,
-            -- TCO				=>,
-			TDO					=> TDO,
-			-- Serial I/O control:
-			RC					=> TDO,
-			TC					=> TDO,
-			SI					=> RxD, 
-			SO					=> TxD
-			-- SO_EN			=> MFP_SO_EN
-			-- DMA control:
-			-- RRn				=>,
-			-- TRn				=>
-		);
-
-MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
-MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
-LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
-FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
-FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
-DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
-         '0' when FDINT = '1' else
-         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
- ----------------------------------------------------------------------------
--- Sound
-----------------------------------------------------------------------------
- 	I_SOUND: WF2149IP_TOP_SOC
-		port map(
-			SYS_CLK				=> not MAIN_CLK,
-			RESETn				=> nResetatio,
-
-			WAV_CLK				=> CLK2M,
-			SELn				=> '1',
-
-			BDIR				=> SNDIR_I,
-			BC2					=> '1',
-			BC1					=> SNDCS_I,
-
-			A9n					=> '0',
-			A8					=> '1',
-			DA_IN				=> FB_ADI(15 downto 8),
-			DA_OUT 				=> DA_OUT_X,
-
-			IO_A_IN				=> SND_A,	
-			IO_A_OUT			=> SND_A_X,
-			-- IO_A_EN			=>, -- Not required.
-			IO_B_IN				=> LP_D,
-			IO_B_OUT			=> LP_D_X,
- --			IO_B_EN				=> IO_B_EN,
-
-			OUT_A				=> YM_QA,
-			OUT_B				=> YM_QB,
-			OUT_C				=> YM_QC
-		);
-
-SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
-SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
-SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
-FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-nnIDE_RES <= SND_A_X(7);
-LP_DIR_X  <= SND_A_X(6);
-LP_STR    <= SND_A_X(5);
-DTR       <= SND_A_X(4); 
-RTS		  <= SND_A_X(3);
--- FDD_D1SEL   <= SND_A_X(2)
-DSA_D	  <= SND_A_X(1);
-nSDSEL    <= SND_A_X(0);
-LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
-LP_DIR <= LP_DIR_X;
-
-
-----------------------------------------------------------------------------
--- DMA Sound register
-----------------------------------------------------------------------------
-
-dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';	-- F8900-F893F
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndmactl <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' then
-				sndmactl <= FB_AD(23 downto 16);
-			else
-				sndmactl <= sndmactl;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndbashi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' then
-				sndbashi <= FB_AD(23 downto 16);
-			else
-				sndbashi <= sndbashi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndbashi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndbasmi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' then
-				sndbasmi <= FB_AD(23downto 16);
-			else
-				sndbasmi <= sndbasmi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndbasmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"2" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndbaslo <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' then
-				sndbaslo <= FB_AD(23 downto 16);
-			else
-				sndbaslo <= sndbaslo;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndbaslo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"3" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndadrhi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' then
-				sndadrhi <= FB_AD(23 downto 16);
-			else
-				sndadrhi <= sndadrhi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndadrhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"4" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndadrmi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' then
-				sndadrmi <= FB_AD(23 downto 16);
-			else
-				sndadrmi <= sndadrmi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndadrmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndadrlo <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' then
-				sndadrlo <= FB_AD(23 downto 16);
-			else
-				sndadrlo <= sndadrlo;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndadrlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"6" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndendhi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' then
-				sndendhi <= FB_AD(23 downto 16);
-			else
-				sndendhi <= sndendhi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndendhi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"7" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndendmi <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' then
-				sndendmi <= FB_AD(23 downto 16);
-			else
-				sndendmi <= sndendmi;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndendmi when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndendlo <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' then
-				sndendlo <= FB_AD(23 downto 16);
-			else
-				sndendlo <= sndendlo;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndendlo when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZ";
-
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
-	begin
-		if nRSTO = '0' THEN
-			sndmode <= x"00";
-		elsif rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' then
-				sndmode <= FB_AD(23 downto 16);
-			else
-				sndmode <= sndmode;
-			end if;
-	END PROCESS;
-FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZ";
-
-----------------------------------------------------------------------------
--- Paddle
-----------------------------------------------------------------------------
-
-paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0';	-- F9200-F923F
-
-FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"1" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"8" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"9" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"A" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
-
-END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
deleted file mode 100644
index 4f42cf2..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
+++ /dev/null
@@ -1,406 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- Atari Coldfire IP Core				                          ----
-----                                                              ----
----- This file is part of the Atari Coldfire project.             ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
-----                                                              ----
-----                                                              ----
-----                                                              ----
-----                                                              ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2009 Wolfgang Foerster                         ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 1.0 Initial Release, 20090925.
--- 
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-package FalconIO_SDCard_IDE_CF_PKG is
-	component WF25915IP_TOP_V1_SOC -- GLUE.
-		port (
-		    -- Clock system:
-			GL_CLK		: in std_logic; -- Originally 8MHz.
-			GL_CLK_016	: in std_logic; -- One sixteenth of GL_CLK.
-			
-            -- Core address select:
-            GL_ROMSEL_FC_E0n    : in std_logic;
-            EN_RAM_14MB         : in std_logic;
-			-- Adress decoder outputs:
-			GL_ROM_6n	: out std_logic;	-- STE.
-			GL_ROM_5n	: out std_logic;	-- STE.
-			GL_ROM_4n	: out std_logic;	-- ST.
-			GL_ROM_3n	: out std_logic;	-- ST.
-			GL_ROM_2n	: out std_logic;
-			GL_ROM_1n	: out std_logic;
-			GL_ROM_0n	: out std_logic;
-			
-			GL_ACIACS	: out std_logic;
-			GL_MFPCSn	: out std_logic;
-			GL_SNDCSn	: out std_logic;
-			GL_FCSn		: out std_logic;
-
-			GL_STE_SNDCS	: out std_logic; 	-- STE: Sound chip select.
-			GL_STE_SNDIR	: out std_logic; 	-- STE: Data flow direction control.
-
-			GL_STE_RTCCSn	: out std_logic; 	--STE only.
-			GL_STE_RTC_WRn	: out std_logic; 	--STE only.
-			GL_STE_RTC_RDn	: out std_logic;	--STE only.
-
-			-- 6800 peripheral control, 
-			GL_VPAn			: out std_logic;
-			GL_VMAn 		: in std_logic;
-			
-			GL_DMA_SYNC		: in std_logic;
-			GL_DEVn			: out std_logic;
-			GL_RAMn			: out std_logic;
-			GL_DMAn			: out std_logic;
-			
-			-- Interrupt system:
-			-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
-			GL_AVECn		: out std_logic;
-			GL_STE_FDINT	: in std_logic; 	-- Floppy disk interrupt; STE only.
-			GL_STE_HDINTn	: in std_logic; 	-- Hard disk interrupt; STE only.
-			GL_MFPINTn		: in std_logic; 	-- ST.
-			GL_STE_EINT3n	: in std_logic; 	--STE only.
-			GL_STE_EINT5n	: in std_logic; 	--STE only.
-			GL_STE_EINT7n	: in std_logic; 	--STE only.
-			GL_STE_DINTn	: out std_logic; 	-- Disk interrupt (floppy or hard disk); STE only.
-			GL_IACKn		: out std_logic; 	-- ST.
-			GL_STE_IPL2n	: out std_logic; 	--STE only.
-			GL_STE_IPL1n	: out std_logic; 	--STE only.
-			GL_STE_IPL0n	: out std_logic; 	--STE only.
-			
-			-- Video timing:
-			GL_BLANKn		: out std_logic;
-			GL_DE			: out std_logic;
-			GL_MULTISYNC	: in std_logic_vector(3 downto 2);
-            GL_VIDEO_HIMODE : out std_logic;
-			GL_HSYNC_INn	: in std_logic;
-			GL_HSYNC_OUTn	: out std_logic;
-			GL_VSYNC_INn	: in std_logic;
-			GL_VSYNC_OUTn	: out std_logic;
-			GL_SYNC_OUT_EN	: out std_logic;
-			
-			-- Bus arstd_logicration control:
-			GL_RDY_INn		: in std_logic;
-			GL_RDY_OUTn		: out std_logic;
-			GL_BRn			: out std_logic;
-			GL_BGIn			: in std_logic;
-			GL_BGOn			: out std_logic;
-			GL_BGACK_INn	: in std_logic;
-			GL_BGACK_OUTn	: out std_logic;
-
-			-- Adress and data bus:
-			GL_ADDRESS		: in std_logic_vector(23 downto 1);
-			-- ST: put the data bus to 1 downto 0. 
-			-- STE: put the data out bus to 15 downto 0. 
-			GL_DATA_IN		: in std_logic_vector(7 downto 0);
-			GL_DATA_OUT		: out std_logic_vector(15 downto 0);
-			GL_DATA_EN		: out std_logic;
-			
-			-- Asynchronous bus control:
-			GL_RWn_IN		: in std_logic;
-			GL_RWn_OUT		: out std_logic;
-			GL_AS_INn		: in std_logic;
-			GL_AS_OUTn		: out std_logic;
-			GL_UDS_INn		: in std_logic;
-			GL_UDS_OUTn		: out std_logic;
-			GL_LDS_INn		: in std_logic;
-			GL_LDS_OUTn		: out std_logic;
-			GL_DTACK_INn	: in std_logic;
-			GL_DTACK_OUTn	: out std_logic;
-			GL_CTRL_EN		: out std_logic;
-			
-			-- System control:
-			GL_RESETn		: in std_logic;
-			GL_BERRn		: out std_logic;
-			
-			-- Processor function codes:
-			GL_FC	: in std_logic_vector(2 downto 0);
-
-			-- STE enhancements:
-			GL_STE_FDDS		: out std_logic; 		-- Floppy type select (HD or DD).
-			GL_STE_FCCLK	: out std_logic; 		-- Floppy controller clock select.
-			GL_STE_JOY_RHn	: out std_logic; 		-- Read only FF9202 high byte.
-			GL_STE_JOY_RLn	: out std_logic; 		-- Read only FF9202 low byte.
-			GL_STE_JOY_WL	: out std_logic; 		-- Write only FF9202 low byte.
-			GL_STE_JOY_WEn	: out std_logic; 		-- Write only FF9202 output enable.
-			GL_STE_BUTTONn	: out std_logic; 		-- Read only FF9000 low byte.		
-			GL_STE_PAD0Xn	: in std_logic; 		-- Counter input for the Paddle 0X.
-			GL_STE_PAD0Yn	: in std_logic; 		-- Counter input for the Paddle 0Y.
-			GL_STE_PAD1Xn	: in std_logic; 		-- Counter input for the Paddle 1X.
-			GL_STE_PAD1Yn	: in std_logic; 		-- Counter input for the Paddle 1Y.
-			GL_STE_PADRSTn	: out std_logic; 		-- Paddle monoflops reset.
-			GL_STE_PENn		: in std_logic; 		-- Input of the light pen.
-			GL_STE_SCCn		: out std_logic;	-- Select signal for the STE or TT SCC chip.
-			GL_STE_CPROGn	: out std_logic	-- Select signal for the STE's cache processor.
-			);
-	end component WF25915IP_TOP_V1_SOC;
-
-    component WF5380_TOP_SOC
-        port (
-            CLK			: in std_logic;
-            RESETn	    : in std_logic;
-            ADR			: in std_logic_vector(2 downto 0);
-            DATA_IN		: in std_logic_vector(7 downto 0);
-            DATA_OUT	: out std_logic_vector(7 downto 0);
-            DATA_EN		: out std_logic;
-            CSn			: in std_logic;
-            RDn		    : in std_logic;
-            WRn	        : in std_logic;
-            EOPn        : in std_logic;
-            DACKn	    : in std_logic;
-            DRQ		    : out std_logic;
-            INT		    : out std_logic;
-            READY       : out std_logic;
-            DB_INn		: in std_logic_vector(7 downto 0);
-            DB_OUTn		: out std_logic_vector(7 downto 0);
-            DB_EN       : out std_logic;
-            DBP_INn		: in std_logic;
-            DBP_OUTn	: out std_logic;
-            DBP_EN      : out std_logic;
-            RST_INn     : in std_logic;
-            RST_OUTn    : out std_logic;
-            RST_EN      : out std_logic;
-            BSY_INn     : in std_logic;
-            BSY_OUTn    : out std_logic;
-            BSY_EN      : out std_logic;
-            SEL_INn     : in std_logic;
-            SEL_OUTn    : out std_logic;
-            SEL_EN      : out std_logic;
-            ACK_INn     : in std_logic;
-            ACK_OUTn    : out std_logic;
-            ACK_EN      : out std_logic;
-            ATN_INn     : in std_logic;
-            ATN_OUTn    : out std_logic;
-            ATN_EN      : out std_logic;
-            REQ_INn     : in std_logic;
-            REQ_OUTn    : out std_logic;
-            REQ_EN      : out std_logic;
-            IOn_IN      : in std_logic;
-            IOn_OUT     : out std_logic;
-            IO_EN       : out std_logic;
-            CDn_IN      : in std_logic;
-            CDn_OUT     : out std_logic;
-            CD_EN       : out std_logic;
-            MSG_INn     : in std_logic;
-            MSG_OUTn    : out std_logic;
-            MSG_EN      : out std_logic
-        );
-    end component WF5380_TOP_SOC;
-
-	component WF1772IP_TOP_SOC -- FDC.
-		port (
-			CLK			: in std_logic; -- 16MHz clock!
-			RESETn		: in std_logic;
-			CSn			: in std_logic;
-			RWn			: in std_logic;
-			A1, A0		: in std_logic;
-			DATA_IN		: in std_logic_vector(7 downto 0);
-			DATA_OUT	: out std_logic_vector(7 downto 0);
-			DATA_EN		: out std_logic;
-			RDn			: in std_logic;
-			TR00n		: in std_logic;
-			IPn			: in std_logic;
-			WPRTn		: in std_logic;
-			DDEn		: in std_logic;
-			HDTYPE		: in std_logic; -- '0' = DD disks, '1' = HD disks.
-			MO			: out std_logic;
-			WG			: out std_logic;
-			WD			: out std_logic;
-			STEP		: out std_logic;
-			DIRC		: out std_logic;
-			DRQ			: out std_logic;
-			INTRQ		: out std_logic
-		);
-	end component WF1772IP_TOP_SOC;
-
-	component WF68901IP_TOP_SOC -- MFP.
-		port (  -- System control:
-				CLK			: in std_logic;
-				RESETn		: in std_logic;
-				
-				-- Asynchronous bus control:
-				DSn			: in std_logic;
-				CSn			: in std_logic;
-				RWn			: in std_logic;
-				DTACKn		: out std_logic;
-				
-				-- Data and Adresses:
-				RS			: in std_logic_vector(5 downto 1);
-				DATA_IN		: in std_logic_vector(7 downto 0);
-				DATA_OUT	: out std_logic_vector(7 downto 0);
-				DATA_EN		: out std_logic;
-				GPIP_IN		: in std_logic_vector(7 downto 0);
-				GPIP_OUT	: out std_logic_vector(7 downto 0);
-				GPIP_EN		: out std_logic_vector(7 downto 0);
-				
-				-- Interrupt control:
-				IACKn		: in std_logic;
-				IEIn		: in std_logic;
-				IEOn		: out std_logic;
-				IRQn		: out std_logic;
-				
-				-- Timers and timer control:
-				XTAL1		: in std_logic; -- Use an oszillator instead of a quartz.
-				TAI			: in std_logic;
-				TBI			: in std_logic;
-				TAO			: out std_logic;			
-				TBO			: out std_logic;			
-				TCO			: out std_logic;			
-				TDO			: out std_logic;			
-				
-				-- Serial I/O control:
-				RC			: in std_logic;
-				TC			: in std_logic;
-				SI			: in std_logic;
-				SO			: out std_logic;
-				SO_EN		: out std_logic;
-				
-				-- DMA control:
-				RRn			: out std_logic;
-				TRn			: out std_logic			
-		);
-	end component WF68901IP_TOP_SOC;
-
-	component WF2149IP_TOP_SOC -- Sound.
-		port(
-			
-			SYS_CLK		: in std_logic; -- Read the inforation in the header!
-			RESETn   	: in std_logic;
-
-			WAV_CLK		: in std_logic; -- Read the inforation in the header!
-			SELn		: in std_logic;
-			
-			BDIR		: in std_logic;
-			BC2, BC1	: in std_logic;
-
-			A9n, A8		: in std_logic;
-			DA_IN		: in std_logic_vector(7 downto 0);
-			DA_OUT		: out std_logic_vector(7 downto 0);
-			DA_EN		: out std_logic;
-			
-			IO_A_IN		: in std_logic_vector(7 downto 0);
-			IO_A_OUT	: out std_logic_vector(7 downto 0);
-			IO_A_EN		: out std_logic;
-			IO_B_IN		: in std_logic_vector(7 downto 0);
-			IO_B_OUT	: out std_logic_vector(7 downto 0);
-			IO_B_EN		: out std_logic;
-
-			OUT_A		: out std_logic; -- Analog (PWM) outputs.
-			OUT_B		: out std_logic;
-			OUT_C		: out std_logic
-		);
-	end component WF2149IP_TOP_SOC;
-
-	component WF6850IP_TOP_SOC -- ACIA.
-	  port (
-			CLK					: in std_logic;
-	        RESETn				: in std_logic;
-
-	        CS2n, CS1, CS0		: in std_logic;
-	        E		       		: in std_logic;   
-	        RWn              	: in std_logic;
-	        RS					: in std_logic;
-
-	        DATA_IN		        : in std_logic_vector(7 downto 0);   
-	        DATA_OUT	        : out std_logic_vector(7 downto 0);   
-			DATA_EN				: out std_logic;
-
-	        TXCLK				: in std_logic;
-	        RXCLK				: in std_logic;
-	        RXDATA				: in std_logic;
-	        CTSn				: in std_logic;
-	        DCDn				: in std_logic;
-	        
-	        IRQn				: out std_logic;
-	        TXDATA				: out std_logic;   
-	        RTSn				: out std_logic
-	       );                                              
-	end component WF6850IP_TOP_SOC;
-
-	component WF_SD_CARD
-		port (
-			RESETn			: in std_logic;
-			CLK				: in std_logic;
-			ACSI_A1			: in std_logic;
-			ACSI_CSn		: in std_logic;
-			ACSI_ACKn		: in std_logic;
-			ACSI_INTn		: out std_logic;
-			ACSI_DRQn		: out std_logic;
-			ACSI_D_IN		: in std_logic_vector(7 downto 0);
-			ACSI_D_OUT		: out std_logic_vector(7 downto 0);
-			ACSI_D_EN		: out std_logic;
-			MC_DO			: in std_logic;
-			MC_PIO_DMAn		: in std_logic;
-			MC_RWn			: in std_logic;
-			MC_CLR_CMD		: in std_logic;
-			MC_DONE			: out std_logic;
-			MC_GOT_CMD		: out std_logic;
-			MC_D_IN			: in std_logic_vector(7 downto 0);
-			MC_D_OUT		: out std_logic_vector(7 downto 0);
-			MC_D_EN			: out std_logic
-	      );
-	end component WF_SD_CARD;
-
-	component dcfifo0 
-		PORT (
-			aclr			: IN STD_LOGIC ;
-			data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-			rdclk			: IN STD_LOGIC ;
-			rdreq			: IN STD_LOGIC ;
-			wrclk			: IN STD_LOGIC ;
-			wrreq			: IN STD_LOGIC ;
-			q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-			wrusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
-	);
-	end component dcfifo0;
-	
-	component dcfifo1
-		PORT (
-			aclr			: IN STD_LOGIC ;
-			data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
-			rdclk			: IN STD_LOGIC ;
-			rdreq			: IN STD_LOGIC ;
-			wrclk			: IN STD_LOGIC ;
-			wrreq			: IN STD_LOGIC ;
-			q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-			rdusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
-		);
-	end component;
-
-
-end FalconIO_SDCard_IDE_CF_PKG;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
index dac4e9d..77ea5ef 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
@@ -190,8 +190,8 @@ begin
 		end if;	
 	end process DIG_PORTS;
 	-- Set port direction to input or to output:
-	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';  
-	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';  
+	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
+	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
 	IO_A_OUT <= PORT_A;
 	IO_B_OUT <= PORT_B;
 
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
deleted file mode 100644
index d81f23c..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd.bak
+++ /dev/null
@@ -1,229 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
-----  YM2149 compatible sound generator.			              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- Model of the ST or STE's YM2149 sound generator.             ----
----- This IP core of the sound generator differs slightly from    ----
----- the original. Firstly it is a synchronous design without any ----
----- latches (like assumed in the original chip). This required   ----
----- the introduction of a system adequate clock. In detail this  ----
----- SYS_CLK should on the one hand be fast enough to meet the    ----
----- timing requirements of the system's bus cycle and should one ----
----- the other hand drive the PWM modules correctly. To meet both ----
----- a SYS_CLK of 16MHz or above is recommended.                  ----
----- Secondly, the original chip has an implemented DA converter. ----
----- This feature is not possible in today's FPGAs. Therefore the ----
----- converter is replaced by pulse width modulators. This solu-  ----
----- tion is very simple in comparison to other approaches like   ----
----- external DA converters with wave tables etc. The soltution   ----
----- with the pulse width modulators is probably not as accurate  ----
----- DAs with wavetables. For a detailed descrition of the hard-  ----
----- ware PWM filter look at the end of the wave file, where the  ----
----- pulse width modulators can be found.                         ----
----- For a proper operation it is required, that the wave clock   ----
----- is lower than the system clock. A good choice is for example ----
----- 2MHz for the wave clock and 16MHz for the system clock.      ----
-----                                                              ----
----- Main module file.                                            ----
----- Top level file for use in systems on programmable chips.     ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
---   Top level file provided for SOC (systems on programmable chips).
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use work.wf2149ip_pkg.all;
-
-entity WF2149IP_TOP_SOC is
-	port(
-		
-		SYS_CLK		: in bit; -- Read the inforation in the header!
-		RESETn   	: in bit;
-
-		WAV_CLK		: in bit; -- Read the inforation in the header!
-		SELn		: in bit;
-		
-		BDIR		: in bit;
-		BC2, BC1	: in bit;
-
-		A9n, A8		: in bit;
-		DA_IN		: in std_logic_vector(7 downto 0);
-		DA_OUT		: out std_logic_vector(7 downto 0);
-		DA_EN		: out bit;
-		
-		IO_A_IN		: in bit_vector(7 downto 0);
-		IO_A_OUT	: out bit_vector(7 downto 0);
-		IO_A_EN		: out bit;
-		IO_B_IN		: in bit_vector(7 downto 0);
-		IO_B_OUT	: out bit_vector(7 downto 0);
-		IO_B_EN		: out bit;
-
-		OUT_A		: out bit; -- Analog (PWM) outputs.
-		OUT_B		: out bit;
-		OUT_C		: out bit
-	);
-end WF2149IP_TOP_SOC;
-
-architecture STRUCTURE of WF2149IP_TOP_SOC is
-signal BUSCYCLE		: BUSCYCLES;
-signal DATA_OUT_I	: std_logic_vector(7 downto 0);
-signal DATA_EN_I	: bit;
-signal WAV_STRB		: bit;
-signal ADR_I		: bit_vector(3 downto 0);
-signal CTRL_REG		: bit_vector(7 downto 0);
-signal PORT_A		: bit_vector(7 downto 0);
-signal PORT_B		: bit_vector(7 downto 0);
-begin
-	P_WAVSTRB: process(RESETn, SYS_CLK)
-	variable LOCK	: boolean;
-	variable TMP	: bit;
-	begin
-		if RESETn = '0' then
-			LOCK := false;
-			TMP := '0';
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if WAV_CLK = '1' and LOCK = false then
-				LOCK := true;
-				TMP := not TMP; -- Divider by 2.
-				case SELn is
-					when '1' 	=> WAV_STRB <= '1';
-					when others => WAV_STRB <= TMP;
-				end case;
-			elsif WAV_CLK = '0' then
-				LOCK := false;
-				WAV_STRB <= '0';
-			else
-				WAV_STRB <= '0';
-			end if;
-		end if;
-	end process P_WAVSTRB;		
-
-	with BDIR & BC2 & BC1 select
-		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
-					ADDRESS 	when "001" | "100" | "111",
-					R_READ 		when "011",
-					R_WRITE 	when "110";
-
-	ADDRESSLATCH: process(RESETn, SYS_CLK)
-	-- This process is responsible to store the desired register
-	-- address. The default (after reset) is channel A fine tone 
-	-- adjustment.
-	begin
-		if RESETn = '0' then
-			ADR_I <= (others => '0');
-        elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
-				ADR_I <= To_BitVector(DA_IN(3 downto 0));
-			end if;
-		end if;
-	end process ADDRESSLATCH;	
-
-	P_CTRL_REG: process(RESETn, SYS_CLK)
-	-- THIS is the Control register for the mixer and for the I/O ports.
-	begin
-		if RESETn = '0' then
-			CTRL_REG <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
-				CTRL_REG <= To_BitVector(DA_IN);
-			end if;
-		end if;
-	end process P_CTRL_REG;
-	
-	DIG_PORTS: process(RESETn, SYS_CLK)
-	begin
-		if RESETn = '0' then
-			PORT_A <= x"00";
-			PORT_B <= x"00";
-		elsif SYS_CLK = '1' and SYS_CLK' event then
-			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
-				PORT_A <= To_BitVector(DA_IN);
-			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
-				PORT_B <= To_BitVector(DA_IN);
-			end if;
-		end if;	
-	end process DIG_PORTS;
-	-- Set port direction to input or to output:
-	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '1'; --0
-	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '1'; --0
-	IO_A_OUT <= PORT_A;
-	IO_B_OUT <= PORT_B;
-
-	I_PSG_WAVE: WF2149IP_WAVE
-		port map(
-			RESETn		=> RESETn,
-			SYS_CLK	=> SYS_CLK,
-
-			WAV_STRB	=> WAV_STRB,
-
-			ADR			=> ADR_I,
-			DATA_IN		=> DA_IN,
-			DATA_OUT	=> DATA_OUT_I,
-			DATA_EN		=> DATA_EN_I,
-			
-			BUSCYCLE	=> BUSCYCLE,
-			CTRL_REG	=> CTRL_REG(5 downto 0),
-						
-			OUT_A		=> OUT_A,
-			OUT_B		=> OUT_B,
-			OUT_C		=> OUT_C
-		);
-
-	-- Read the ports and registers:
-	DA_EN <= 	'1' when DATA_EN_I = '1' else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
-				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
-				
-	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
-				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
-				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
-				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
-
-end STRUCTURE;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
deleted file mode 100644
index c3ca670..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
+++ /dev/null
@@ -1,202 +0,0 @@
--- megafunction wizard: %LPM_FIFO+%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: dcfifo_mixed_widths 
-
--- ============================================================
--- File Name: dcfifo0.vhd
--- Megafunction Name(s):
--- 			dcfifo_mixed_widths
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 222 10/21/2009 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2009 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY dcfifo0 IS
-	PORT
-	(
-		aclr		: IN STD_LOGIC  := '0';
-		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		rdclk		: IN STD_LOGIC ;
-		rdreq		: IN STD_LOGIC ;
-		wrclk		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-		wrusedw		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
-	);
-END dcfifo0;
-
-
-ARCHITECTURE SYN OF dcfifo0 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
-
-
-
-	COMPONENT dcfifo_mixed_widths
-	GENERIC (
-		intended_device_family		: STRING;
-		lpm_numwords		: NATURAL;
-		lpm_showahead		: STRING;
-		lpm_type		: STRING;
-		lpm_width		: NATURAL;
-		lpm_widthu		: NATURAL;
-		lpm_widthu_r		: NATURAL;
-		lpm_width_r		: NATURAL;
-		overflow_checking		: STRING;
-		rdsync_delaypipe		: NATURAL;
-		underflow_checking		: STRING;
-		use_eab		: STRING;
-		write_aclr_synch		: STRING;
-		wrsync_delaypipe		: NATURAL
-	);
-	PORT (
-			wrclk	: IN STD_LOGIC ;
-			rdreq	: IN STD_LOGIC ;
-			wrusedw	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			aclr	: IN STD_LOGIC ;
-			rdclk	: IN STD_LOGIC ;
-			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
-			wrreq	: IN STD_LOGIC ;
-			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	wrusedw    <= sub_wire0(4 DOWNTO 0);
-	q    <= sub_wire1(15 DOWNTO 0);
-
-	dcfifo_mixed_widths_component : dcfifo_mixed_widths
-	GENERIC MAP (
-		intended_device_family => "Cyclone III",
-		lpm_numwords => 32,
-		lpm_showahead => "OFF",
-		lpm_type => "dcfifo",
-		lpm_width => 8,
-		lpm_widthu => 5,
-		lpm_widthu_r => 4,
-		lpm_width_r => 16,
-		overflow_checking => "ON",
-		rdsync_delaypipe => 5,
-		underflow_checking => "ON",
-		use_eab => "ON",
-		write_aclr_synch => "OFF",
-		wrsync_delaypipe => 5
-	)
-	PORT MAP (
-		wrclk => wrclk,
-		rdreq => rdreq,
-		aclr => aclr,
-		rdclk => rdclk,
-		wrreq => wrreq,
-		data => data,
-		wrusedw => sub_wire0,
-		q => sub_wire1
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "32"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "8"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "16"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "0"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
--- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
--- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
--- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
--- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
--- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0]
--- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
--- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
--- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
deleted file mode 100644
index e7c6ae6..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
+++ /dev/null
@@ -1,202 +0,0 @@
--- megafunction wizard: %LPM_FIFO+%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: dcfifo_mixed_widths 
-
--- ============================================================
--- File Name: dcfifo1.vhd
--- Megafunction Name(s):
--- 			dcfifo_mixed_widths
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 222 10/21/2009 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2009 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY dcfifo1 IS
-	PORT
-	(
-		aclr		: IN STD_LOGIC  := '0';
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		rdclk		: IN STD_LOGIC ;
-		rdreq		: IN STD_LOGIC ;
-		wrclk		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-		wrusedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END dcfifo1;
-
-
-ARCHITECTURE SYN OF dcfifo1 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-
-
-	COMPONENT dcfifo_mixed_widths
-	GENERIC (
-		intended_device_family		: STRING;
-		lpm_numwords		: NATURAL;
-		lpm_showahead		: STRING;
-		lpm_type		: STRING;
-		lpm_width		: NATURAL;
-		lpm_widthu		: NATURAL;
-		lpm_widthu_r		: NATURAL;
-		lpm_width_r		: NATURAL;
-		overflow_checking		: STRING;
-		rdsync_delaypipe		: NATURAL;
-		underflow_checking		: STRING;
-		use_eab		: STRING;
-		write_aclr_synch		: STRING;
-		wrsync_delaypipe		: NATURAL
-	);
-	PORT (
-			wrclk	: IN STD_LOGIC ;
-			rdreq	: IN STD_LOGIC ;
-			wrusedw	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
-			aclr	: IN STD_LOGIC ;
-			rdclk	: IN STD_LOGIC ;
-			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-			wrreq	: IN STD_LOGIC ;
-			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	wrusedw    <= sub_wire0(3 DOWNTO 0);
-	q    <= sub_wire1(7 DOWNTO 0);
-
-	dcfifo_mixed_widths_component : dcfifo_mixed_widths
-	GENERIC MAP (
-		intended_device_family => "Cyclone III",
-		lpm_numwords => 16,
-		lpm_showahead => "OFF",
-		lpm_type => "dcfifo",
-		lpm_width => 16,
-		lpm_widthu => 4,
-		lpm_widthu_r => 5,
-		lpm_width_r => 8,
-		overflow_checking => "ON",
-		rdsync_delaypipe => 5,
-		underflow_checking => "ON",
-		use_eab => "ON",
-		write_aclr_synch => "OFF",
-		wrsync_delaypipe => 5
-	)
-	PORT MAP (
-		wrclk => wrclk,
-		rdreq => rdreq,
-		aclr => aclr,
-		rdclk => rdclk,
-		wrreq => wrreq,
-		data => data,
-		wrusedw => sub_wire0,
-		q => sub_wire1
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "16"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "16"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "8"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "0"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
--- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
--- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
--- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
--- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
--- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
--- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
index 16de480..64354fe 100644
--- a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf
@@ -24,6 +24,7 @@ SUBDESIGN interrupt_handler
 	FB_SIZE0 : INPUT;
 	FB_SIZE1 : INPUT;
 	FB_ADR[31..0] : INPUT;
+	FPGA_DATE[31..0] : INPUT;
 	PIC_INT : INPUT;
 	E0_INT : INPUT;
 	DVI_INT : INPUT;
@@ -61,6 +62,7 @@ VARIABLE
 	INT_LA[9..0][3..0]		:DFF;
 	ACP_CONF[31..0]			:DFFE;
 	ACP_CONF_CS				:NODE;
+	FPGA_DATE_CS			:NODE;
 	PSEUDO_BUS_ERROR		:NODE;
 	UHR_AS					:NODE;
 	UHR_DS					:NODE;
@@ -201,6 +203,9 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
 	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
 --***************************************************************************************
+-- FPGA DATE HEX (ddmmyyyy)
+	FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040";		-- $4'0000/4
+--***************************************************************************************
 	
 --------------------------------------------------------------	
 -- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
@@ -288,7 +293,8 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				  #	INT_LATCH_CS & INT_LATCH[31..24]
 				  # INT_CLEAR_CS & INT_IN[31..24]
 				  # ACP_CONF_CS  & ACP_CONF[31..24]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+				  # FPGA_DATE_CS  & FPGA_DATE[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
 	FB_AD[23..16] = lpm_bustri_BYT(
 				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
 				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
@@ -360,21 +366,24 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR H
 				 # INT_LATCH_CS & INT_LATCH[23..16]
 				 # INT_CLEAR_CS & INT_IN[23..16]
 				 # ACP_CONF_CS  & ACP_CONF[23..16]
-				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+				 # FPGA_DATE_CS  & FPGA_DATE[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
 	FB_AD[15..8] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[15..8] 
 				  #	INT_ENA_CS   & INT_ENA[15..8]
 				  #	INT_LATCH_CS & INT_LATCH[15..8]
 				  # INT_CLEAR_CS & INT_IN[15..8]
 				  # ACP_CONF_CS  & ACP_CONF[15..8]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+				  # FPGA_DATE_CS  & FPGA_DATE[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
 	FB_AD[7..0] = lpm_bustri_BYT(
 					INT_CTR_CS   & INT_CTR[7..0] 
 				  #	INT_ENA_CS   & INT_ENA[7..0]
 				  #	INT_LATCH_CS & INT_LATCH[7..0]
 				  # INT_CLEAR_CS & INT_IN[7..0]
 				  # ACP_CONF_CS  & ACP_CONF[7..0]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+				  # FPGA_DATE_CS  & FPGA_DATE[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS # FPGA_DATE_CS) & !nFB_OE);
 
 	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
 END;
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
deleted file mode 100644
index 459192d..0000000
--- a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
+++ /dev/null
@@ -1,382 +0,0 @@
-TITLE "INTERRUPT HANDLER UND C1287";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_LONG.inc";
-INCLUDE "lpm_bustri_BYT.inc";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN interrupt_handler
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	MAIN_CLK : INPUT;
-	nFB_WR : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	FB_ADR[31..0] : INPUT;
-	PIC_INT : INPUT;
-	E0_INT : INPUT;
-	DVI_INT : INPUT;
-	nPCI_INTA : INPUT;
-	nPCI_INTB : INPUT;
-	nPCI_INTC : INPUT;
-	nPCI_INTD : INPUT;
-	nMFP_INT : INPUT;
-	nFB_OE : INPUT;
-	DSP_INT : INPUT;
-	VSYNC : INPUT;
-	HSYNC : INPUT;
-	DMA_DRQ : INPUT;
-	nRSTO : INPUT;
-	nIRQ[7..2] : OUTPUT;
-	INT_HANDLER_TA : OUTPUT;
-	ACP_CONF[31..0] : OUTPUT;
-	TIN0 : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_B[3..0]				:NODE;
-	INT_CTR[31..0]			:DFFE;
-	INT_CTR_CS				:NODE;
-	INT_LATCH[31..0]		:DFF;
-	INT_LATCH_CS			:NODE;
-	INT_CLEAR[31..0]		:DFF;
-	INT_CLEAR_CS			:NODE;
-	INT_IN[31..0]			:NODE;
-	INT_ENA[31..0]			:DFFE;
-	INT_ENA_CS				:NODE;
-	INT_L[9..0]				:DFF;
-	INT_LA[9..0][3..0]		:DFF;
-	ACP_CONF[31..0]			:DFFE;
-	ACP_CONF_CS				:NODE;
-	PSEUDO_BUS_ERROR		:NODE;
-	UHR_AS					:NODE;
-	UHR_DS					:NODE;
-	RTC_ADR[5..0]			:DFFE;
-	ACHTELSEKUNDEN[2..0]	:DFFE;
-	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
-	PIC_INT_SYNC[2..0]		:DFF;
-	INC_SEC					:NODE;
-	INC_MIN					:NODE;
-	INC_STD					:NODE;
-	INC_TAG					:NODE;
-	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
-	WINTERZEIT				:NODE;
-	SOMMERZEIT				:NODE;
-	INC_MONAT				:NODE;
-	INC_JAHR				:NODE;
-	UPDATE_ON				:NODE;
-	
-BEGIN
--- BYT SELECT
-	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
-		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
-		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
-		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
-		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-
--- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
-	INT_CTR[].CLK = MAIN_CLK;
-	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
-	INT_CTR[] = FB_AD[];
-	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
-	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
-	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
-	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
--- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
-	INT_ENA[].CLK = MAIN_CLK;
-	INT_ENA[].CLRN = nRSTO;
-	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
-	INT_ENA[] = FB_AD[];
-	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
-	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
-	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
-	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
--- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
-	INT_CLEAR[].CLK = MAIN_CLK;
-	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
-	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
-	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
-	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
-	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
--- INTERRUPT LATCH REGISTER READ ONLY
-	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
--- INTERRUPT
-	!nIRQ2 = HSYNC 						& INT_ENA[26];
-	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
-	!nIRQ4 = VSYNC 						& INT_ENA[28];
-	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
-	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
-	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
-
-PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
-							#  FB_ADR[19..4]==H"F8E0"			-- VME
---							#  FB_ADR[19..4]==H"F920"			-- PADDLE
---							#  FB_ADR[19..4]==H"F921"			-- PADDLE
---							#  FB_ADR[19..4]==H"F922"			-- PADDLE
-							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
-							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
-							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
-							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
-							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
-							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
-							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
---							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
---							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
---							#  FB_ADR[19..4]==H"F892"			-- DMA SOUND
-							 );
--- IF VIDEO ADR CHANGE
-TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-
--- INTERRUPT LATCH
-	INT_L[].CLK = MAIN_CLK;
-	INT_L[].CLRN = nRSTO;
-	INT_L0 = PIC_INT & INT_ENA[0];
-	INT_L1 = E0_INT & INT_ENA[1];
-	INT_L2 = DVI_INT & INT_ENA[2];
-	INT_L3 = !nPCI_INTA & INT_ENA[3];
-	INT_L4 = !nPCI_INTB & INT_ENA[4];
-	INT_L5 = !nPCI_INTC & INT_ENA[5];
-	INT_L6 = !nPCI_INTD & INT_ENA[6];
-	INT_L7 = DSP_INT & INT_ENA[7];
-	INT_L8 = VSYNC & INT_ENA[8];
-	INT_L9 = HSYNC & INT_ENA[9];
-	
-	INT_LA[][].CLK = MAIN_CLK;
-	INT_LATCH[] = H"FFFFFFFF";
-	INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
-	FOR I IN 0 TO 9 GENERATE
-		INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
-		INT_LA[I][] = INT_LA[I][]+1 &  INT_L[I] & INT_LA[I][]<7 
-		            # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
-		            # 15            &  INT_L[I] & INT_LA[I][]>6
-		            # 0             & !INT_L[I] & INT_LA[I][]<9;
-		INT_LATCH[I].CLK = INT_LA[I][3];
-	END GENERATE;
-	
--- INT_IN
-	INT_IN0 = PIC_INT;
-	INT_IN1 = E0_INT;
-	INT_IN2 = DVI_INT;
-	INT_IN3 = !nPCI_INTA;
-	INT_IN4 = !nPCI_INTB;
-	INT_IN5 = !nPCI_INTC;
-	INT_IN6 = !nPCI_INTD;
-	INT_IN7 = DSP_INT;
-	INT_IN8 = VSYNC;
-	INT_IN9 = HSYNC;
-	INT_IN[25..10] = H"0";
-	INT_IN26 = HSYNC; 
-	INT_IN27 = INT_CTR0; 
-	INT_IN28 = VSYNC; 
-	INT_IN29 = INT_LATCH[]!=H"00000000";
-	INT_IN30 = !nMFP_INT; 
-	INT_IN31 = DMA_DRQ; 
---***************************************************************************************
--- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
-	ACP_CONF[].CLK = MAIN_CLK;
-	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
-	ACP_CONF[] = FB_AD[];
-	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
-	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
-	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
-	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
---***************************************************************************************
-	
---------------------------------------------------------------	
--- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
-----------------------------------------------------------
-	RTC_ADR[].CLK = MAIN_CLK;
-	RTC_ADR[] = FB_AD[21..16];
-	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
-	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
-	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
-	WERTE[][].CLK = MAIN_CLK;
-	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
-	WERTE[7..0][1] = FB_AD[23..16];
-	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
-	WERTE[7..0][3] = FB_AD[23..16];
-	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
-	WERTE[7..0][5] = FB_AD[23..16];
-	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
-	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
-	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
-	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	FOR I IN 10 TO 63 GENERATE
-		WERTE[7..0][I] = FB_AD[23..16];
-	END GENERATE;
-	FOR I IN 0 TO 63 GENERATE
-		WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
-	END GENERATE;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	
-	PIC_INT_SYNC[0] = PIC_INT;
-	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
-	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
-	UPDATE_ON = !WERTE[7][11];		
-	WERTE[6][10].CLRN = GND;	-- KEIN UIP
-	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
-	WERTE[2][11] = VCC;	-- IMMER BINARY
-	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
-	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
-	WERTE[7][13] = VCC;	-- IMMER RICHTIG
--- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
-	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
-	WERTE[0][13] = SOMMERZEIT;
-	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
-	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
--- ACHTELSEKUNDEN
-	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
-	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
-	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
--- SEKUNDEN
-	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
-	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
-	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
--- MINUTEN
-	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
-	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
-	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
--- STUNDEN
-	INC_STD = INC_MIN & WERTE[][2]==59;							  
-	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
-	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
--- WOCHENTAG UND TAG 
-	INC_TAG = INC_STD & WERTE[][2]==23;						
-	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
-			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
-	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
-	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
-							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
-							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
-							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
-	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
-			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
-	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
--- MONATE
-	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
-	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
-			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
-	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
--- JAHR		   
-	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
-	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
-	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
--- TRISTATE OUTPUT
-
-	FB_AD[31..24] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[31..24] 
-				  #	INT_ENA_CS   & INT_ENA[31..24]
-				  #	INT_LATCH_CS & INT_LATCH[31..24]
-				  # INT_CLEAR_CS & INT_IN[31..24]
-				  # ACP_CONF_CS  & ACP_CONF[31..24]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[23..16] = lpm_bustri_BYT(
-				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
-				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
-				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
-				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
-				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
-				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
-				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
-				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
-				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
-				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
-				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
-				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
-				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
-				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
-				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
-				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
-				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
-				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
-				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
-				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
-				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
-				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
-				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
-				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
-				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
-				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
-				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
-				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
-				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
-				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
-				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
-				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
-				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
-				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
-				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
-				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
-				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
-				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
-				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
-				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
-				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
-				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
-				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
-				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
-				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
-				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
-				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
-				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
-				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
-				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
-				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
-				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
-				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
-				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
-				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
-				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
-				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
-				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
-				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
-				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
-				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
-				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
-				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
-				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
-				 # (0,RTC_ADR[])			   & UHR_AS
-				 # INT_CTR_CS   & INT_CTR[23..16] 
-				 # INT_ENA_CS   & INT_ENA[23..16]
-				 # INT_LATCH_CS & INT_LATCH[23..16]
-				 # INT_CLEAR_CS & INT_IN[23..16]
-				 # ACP_CONF_CS  & ACP_CONF[23..16]
-				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[15..8] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[15..8] 
-				  #	INT_ENA_CS   & INT_ENA[15..8]
-				  #	INT_LATCH_CS & INT_LATCH[15..8]
-				  # INT_CLEAR_CS & INT_IN[15..8]
-				  # ACP_CONF_CS  & ACP_CONF[15..8]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[7..0] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[7..0] 
-				  #	INT_ENA_CS   & INT_ENA[7..0]
-				  #	INT_LATCH_CS & INT_LATCH[7..0]
-				  # INT_CLEAR_CS & INT_IN[7..0]
-				  # ACP_CONF_CS  & ACP_CONF[7..0]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-
-	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
-END;
-
-
diff --git a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
deleted file mode 100644
index 797d4f8..0000000
--- a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-PLL_Name	altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
-PLLJITTER	36
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
-PLLJITTER	43
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
-PLLJITTER	NA
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
-PLLJITTER	31
-PLLSPEmax	84
-PLLSPEmin	-53
-
diff --git a/FPGA_by_Fredi/UNUSED b/FPGA_by_Fredi/UNUSED
deleted file mode 100644
index 3a7d9e6..0000000
--- a/FPGA_by_Fredi/UNUSED
+++ /dev/null
@@ -1,27 +0,0 @@
-
--- Clearbox generated Memory Initialization File (.mif)
-
-WIDTH=3;
-DEPTH=16;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	00  :   7;
-	01  :   6;
-	02  :   5;
-	03  :   4;
-	04  :   3;
-	05  :   2;
-	06  :   1;
-	07  :   0;
-	08  :   7;
-	09  :   6;
-	0a  :   5;
-	0b  :   4;
-	0c  :   3;
-	0d  :   2;
-	0e  :   1;
-	0f  :   0;
-END;
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
deleted file mode 100644
index b0acfb7..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.bsf
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 256 128)
-	(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 109 31 124)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 112 32)(line_width 3))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 112 48)(line_width 3))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
-		(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 112 64)(line_width 1))
-	)
-	(port
-		(pt 0 88)
-		(input)
-		(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
-		(line (pt 0 88)(pt 112 88)(line_width 3))
-	)
-	(port
-		(pt 0 104)
-		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 104 104)(line_width 1))
-	)
-	(port
-		(pt 256 32)
-		(output)
-		(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
-		(line (pt 256 32)(pt 168 32)(line_width 3))
-	)
-	(drawing
-		(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
-		(line (pt 128 24)(pt 168 24)(line_width 1))
-		(line (pt 168 24)(pt 168 96)(line_width 1))
-		(line (pt 168 96)(pt 128 96)(line_width 1))
-		(line (pt 128 96)(pt 128 24)(line_width 1))
-		(line (pt 112 27)(pt 120 27)(line_width 1))
-		(line (pt 120 27)(pt 120 39)(line_width 1))
-		(line (pt 120 39)(pt 112 39)(line_width 1))
-		(line (pt 112 39)(pt 112 27)(line_width 1))
-		(line (pt 112 34)(pt 114 36)(line_width 1))
-		(line (pt 114 36)(pt 112 38)(line_width 1))
-		(line (pt 104 36)(pt 112 36)(line_width 1))
-		(line (pt 120 32)(pt 128 32)(line_width 3))
-		(line (pt 112 43)(pt 120 43)(line_width 1))
-		(line (pt 120 43)(pt 120 55)(line_width 1))
-		(line (pt 120 55)(pt 112 55)(line_width 1))
-		(line (pt 112 55)(pt 112 43)(line_width 1))
-		(line (pt 112 50)(pt 114 52)(line_width 1))
-		(line (pt 114 52)(pt 112 54)(line_width 1))
-		(line (pt 104 52)(pt 112 52)(line_width 1))
-		(line (pt 120 48)(pt 128 48)(line_width 3))
-		(line (pt 112 59)(pt 120 59)(line_width 1))
-		(line (pt 120 59)(pt 120 71)(line_width 1))
-		(line (pt 120 71)(pt 112 71)(line_width 1))
-		(line (pt 112 71)(pt 112 59)(line_width 1))
-		(line (pt 112 66)(pt 114 68)(line_width 1))
-		(line (pt 114 68)(pt 112 70)(line_width 1))
-		(line (pt 104 68)(pt 112 68)(line_width 1))
-		(line (pt 120 64)(pt 128 64)(line_width 1))
-		(line (pt 112 83)(pt 120 83)(line_width 1))
-		(line (pt 120 83)(pt 120 95)(line_width 1))
-		(line (pt 120 95)(pt 112 95)(line_width 1))
-		(line (pt 112 95)(pt 112 83)(line_width 1))
-		(line (pt 112 90)(pt 114 92)(line_width 1))
-		(line (pt 114 92)(pt 112 94)(line_width 1))
-		(line (pt 104 92)(pt 112 92)(line_width 1))
-		(line (pt 120 88)(pt 128 88)(line_width 3))
-		(line (pt 104 36)(pt 104 105)(line_width 1))
-	)
-)
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
index f3eee7b..4137fa8 100644
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.inc
@@ -15,13 +15,18 @@
 
 FUNCTION altsyncram0 
 (
-	address[3..0],
+	address_a[3..0],
+	address_b[3..0],
 	byteena_a[1..0],
-	clock,
-	data[15..0],
-	wren
+	clock_a,
+	clock_b,
+	data_a[15..0],
+	data_b[15..0],
+	wren_a,
+	wren_b
 )
 
 RETURNS (
-	q[15..0]
+	q_a[15..0],
+	q_b[15..0]
 );
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
index c42bd21..767f8c4 100644
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.qip
@@ -1,6 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
 set_global_assignment -name IP_TOOL_VERSION "9.1"
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
index f260092..ef814b9 100644
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
+++ b/FPGA_by_Fredi/Video/BLITTER/altsyncram0.tdf
@@ -38,43 +38,63 @@ INCLUDE "altsyncram.inc";
 
 SUBDESIGN altsyncram0
 (
-	address[3..0]	 : INPUT;
+	address_a[3..0]	 : INPUT;
+	address_b[3..0]	 : INPUT;
 	byteena_a[1..0]	 : INPUT = VCC;
-	clock	 : INPUT = VCC;
-	data[15..0]	 : INPUT;
-	wren	 : INPUT = GND;
-	q[15..0]	 : OUTPUT;
+	clock_a	 : INPUT = VCC;
+	clock_b	 : INPUT;
+	data_a[15..0]	 : INPUT;
+	data_b[15..0]	 : INPUT;
+	wren_a	 : INPUT = GND;
+	wren_b	 : INPUT = GND;
+	q_a[15..0]	 : OUTPUT;
+	q_b[15..0]	 : OUTPUT;
 )
 
 VARIABLE
 
 	altsyncram_component : altsyncram WITH (
+			ADDRESS_REG_B = "CLOCK1",
 			BYTE_SIZE = 8,
 			CLOCK_ENABLE_INPUT_A = "BYPASS",
+			CLOCK_ENABLE_INPUT_B = "BYPASS",
 			CLOCK_ENABLE_OUTPUT_A = "BYPASS",
+			CLOCK_ENABLE_OUTPUT_B = "BYPASS",
+			INDATA_REG_B = "CLOCK1",
 			INTENDED_DEVICE_FAMILY = "Cyclone III",
-			LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
 			LPM_TYPE = "altsyncram",
 			NUMWORDS_A = 16,
-			OPERATION_MODE = "SINGLE_PORT",
+			NUMWORDS_B = 16,
+			OPERATION_MODE = "BIDIR_DUAL_PORT",
 			OUTDATA_ACLR_A = "NONE",
+			OUTDATA_ACLR_B = "NONE",
 			OUTDATA_REG_A = "UNREGISTERED",
+			OUTDATA_REG_B = "UNREGISTERED",
 			POWER_UP_UNINITIALIZED = "FALSE",
 			READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
 			READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
 			WIDTHAD_A = 4,
+			WIDTHAD_B = 4,
 			WIDTH_A = 16,
-			WIDTH_BYTEENA_A = 2
+			WIDTH_B = 16,
+			WIDTH_BYTEENA_A = 2,
+			WIDTH_BYTEENA_B = 1,
+			WRCONTROL_WRADDRESS_REG_B = "CLOCK1"
 			);
 
 BEGIN
 
-	q[15..0] = altsyncram_component.q_a[15..0];
-	altsyncram_component.wren_a = wren;
-	altsyncram_component.clock0 = clock;
+	q_a[15..0] = altsyncram_component.q_a[15..0];
+	q_b[15..0] = altsyncram_component.q_b[15..0];
+	altsyncram_component.wren_a = wren_a;
+	altsyncram_component.clock0 = clock_a;
+	altsyncram_component.wren_b = wren_b;
+	altsyncram_component.clock1 = clock_b;
 	altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
-	altsyncram_component.address_a[3..0] = address[3..0];
-	altsyncram_component.data_a[15..0] = data[15..0];
+	altsyncram_component.address_a[3..0] = address_a[3..0];
+	altsyncram_component.address_b[3..0] = address_b[3..0];
+	altsyncram_component.data_a[15..0] = data_a[15..0];
+	altsyncram_component.data_b[15..0] = data_b[15..0];
 END;
 
 
@@ -100,13 +120,13 @@ END;
 -- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
 -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
 -- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
 -- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
 -- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 -- Retrieval info: PRIVATE: ECC NUMERIC "0"
 -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
 -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -116,17 +136,17 @@ END;
 -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
 -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 -- Retrieval info: PRIVATE: MIFfilename STRING ""
--- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
 -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
 -- Retrieval info: PRIVATE: REGdata NUMERIC "1"
 -- Retrieval info: PRIVATE: REGq NUMERIC "0"
--- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
--- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
 -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 -- Retrieval info: PRIVATE: REGwren NUMERIC "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
@@ -138,44 +158,64 @@ END;
 -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
 -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
 -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
 -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
 -- Retrieval info: PRIVATE: enable NUMERIC "0"
 -- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
 -- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
 -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
 -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
 -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
 -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
 -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
 -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
--- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
+-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
 -- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
--- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
--- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
--- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
--- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
--- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
--- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
--- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
+-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
+-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
+-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
+-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
 -- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
 -- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg b/FPGA_by_Fredi/Video/BLITTER/altsyncram0_wave0.jpg
deleted file mode 100644
index 84314f4e1a03352ec152e2aff9a922132f3d7fea..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html b/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
deleted file mode 100644
index 7b89eb9..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "altsyncram0.tdf" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
-<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT b/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
deleted file mode 100644
index 1ad8825..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/blitter.tdf.ALT
+++ /dev/null
@@ -1,427 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2010 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
--- Created on Sat Jan 15 11:06:17 2011
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
-
-CONSTANT	BL_SKEW_LF = 255;
-
---  Title Statement (optional)
-TITLE "Blitter";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN BLITTER
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ON : INPUT;
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	DDRCLK0 : INPUT;
-	BLITTER_DIN[127..0] : INPUT;
-	BLITTER_DACK[4..0] : INPUT;
-	SR_BLITTER_DACK : INPUT;
-	BLITTER_RUN : OUTPUT;
-	BLITTER_DOUT[127..0] : OUTPUT;
-	BLITTER_ADR[31..0] : OUTPUT;
-	BLITTER_SIG : OUTPUT;
-	BLITTER_WR : OUTPUT;
-	BLITTER_TA : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_B[3..0]					:NODE;
-	FB_16B[1..0]				:NODE;
-	BLITTER_CS					:NODE;
-	BL_HRAM0_CS					:NODE;
-	BL_HRAM0[15..0]				:DFFE;
-	BL_HRAM1_CS					:NODE;
-	BL_HRAM1[15..0]				:DFFE;
-	BL_HRAM2_CS					:NODE;
-	BL_HRAM2[15..0]				:DFFE;
-	BL_HRAM3_CS					:NODE;
-	BL_HRAM3[15..0]				:DFFE;
-	BL_HRAM4_CS					:NODE;
-	BL_HRAM4[15..0]				:DFFE;
-	BL_HRAM5_CS					:NODE;
-	BL_HRAM5[15..0]				:DFFE;
-	BL_HRAM6_CS					:NODE;
-	BL_HRAM6[15..0]				:DFFE;
-	BL_HRAM7_CS					:NODE;
-	BL_HRAM7[15..0]				:DFFE;
-	BL_HRAM8_CS					:NODE;
-	BL_HRAM8[15..0]				:DFFE;
-	BL_HRAM9_CS					:NODE;
-	BL_HRAM9[15..0]				:DFFE;
-	BL_HRAMA_CS					:NODE;
-	BL_HRAMA[15..0]				:DFFE;
-	BL_HRAMB_CS					:NODE;
-	BL_HRAMB[15..0]				:DFFE;
-	BL_HRAMC_CS					:NODE;
-	BL_HRAMC[15..0]				:DFFE;
-	BL_HRAMD_CS					:NODE;
-	BL_HRAMD[15..0]				:DFFE;
-	BL_HRAME_CS					:NODE;
-	BL_HRAME[15..0]				:DFFE;
-	BL_HRAMF_CS					:NODE;
-	BL_HRAMF[15..0]				:DFFE;
-	BL_SRC_X_INC_CS				:NODE;
-	BL_SRC_X_INC[15..0]			:DFFE;
-	BL_SRC_Y_INC_CS				:NODE;
-	BL_SRC_Y_INC[15..0]			:DFFE;
-	BL_ENDMASK1_CS				:NODE;
-	BL_ENDMASK1[15..0]			:DFFE;
-	BL_ENDMASK2_CS				:NODE;
-	BL_ENDMASK2[15..0]			:DFFE;
-	BL_ENDMASK3_CS				:NODE;
-	BL_ENDMASK3[15..0]			:DFFE;
-	BL_SRC_ADRH_CS				:NODE;
-	BL_SRC_ADRL_CS				:NODE;
-	BL_SRC_ADR[31..0]			:DFFE;
-	BL_DST_X_INC_CS				:NODE;
-	BL_DST_X_INC[15..0]			:DFFE;
-	BL_DST_Y_INC_CS				:NODE;
-	BL_DST_Y_INC[15..0]			:DFFE;
-	BL_DST_ADRH_CS				:NODE;
-	BL_DST_ADRL_CS				:NODE;
-	BL_DST_ADR[31..0]			:DFFE;
-	BL_X_CNT_CS					:NODE;
-	BL_X_CNT[15..0]				:DFFE;
-	BL_Y_CNT_CS					:NODE;
-	BL_Y_CNT[15..0]				:DFFE;
-	BL_HT_OP_CS					:NODE;
-	BL_HT_OP[7..0]				:DFFE;
-	BL_LC_OP[7..0]				:DFFE;
-	BL_LN_CS					:NODE;
-	BL_LN[7..0]					:DFFE;
-	BL_SKEW[7..0]				:DFFE;
-	
-	BL_SKEW_EXT[6..0]			:NODE;
-	BL_SKEW_IN[255..0]			:DFFE;
-	BL_SKEW_OUT[255..0]			:DFFE;
-	
-	BL_DATA_DDR_READY			:DFF;						-- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
-	BL_READ_SRC					:DFFE;
-	BL_DST_BUFFER[127..0]		:DFFE;
-	BL_READ_DST					:DFFE;
-	
-	COUNT[18..0]				:DFF;
-	
-BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- BLITTER CS
-	BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28";			-- FFFF8A00-3F/40
-	BLITTER_TA = BLITTER_CS;
--- REGISTER
-	-- HALFTON RAM 0
-	BL_HRAM0[].CLK = MAIN_CLK;
-	BL_HRAM0[15..0] = FB_AD[31..16];
-	BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500";						-- $F8A00/2
-	BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
-	BL_HRAM0[7..0].ENA  = BL_HRAM0_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 1
-	BL_HRAM1[].CLK = MAIN_CLK;
-	BL_HRAM1[15..0] = FB_AD[31..16];
-	BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501";						-- $F8A02/2
-	BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
-	BL_HRAM1[7..0].ENA  = BL_HRAM1_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 2
-	BL_HRAM2[].CLK = MAIN_CLK;
-	BL_HRAM2[15..0] = FB_AD[31..16];
-	BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502";						-- $F8A04/2
-	BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
-	BL_HRAM2[7..0].ENA  = BL_HRAM2_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 3
-	BL_HRAM3[].CLK = MAIN_CLK;
-	BL_HRAM3[15..0] = FB_AD[31..16];
-	BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503";						-- $F8A06/2
-	BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
-	BL_HRAM3[7..0].ENA  = BL_HRAM3_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 4
-	BL_HRAM4[].CLK = MAIN_CLK;
-	BL_HRAM4[15..0] = FB_AD[31..16];
-	BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504";						-- $F8A08/2
-	BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
-	BL_HRAM4[7..0].ENA  = BL_HRAM4_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 5
-	BL_HRAM5[].CLK = MAIN_CLK;
-	BL_HRAM5[15..0] = FB_AD[31..16];
-	BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505";						-- $F8A08/2
-	BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
-	BL_HRAM5[7..0].ENA  = BL_HRAM5_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 6
-	BL_HRAM6[].CLK = MAIN_CLK;
-	BL_HRAM6[15..0] = FB_AD[31..16];
-	BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506";						-- $F8A08/2
-	BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
-	BL_HRAM6[7..0].ENA  = BL_HRAM6_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 7
-	BL_HRAM7[].CLK = MAIN_CLK;
-	BL_HRAM7[15..0] = FB_AD[31..16];
-	BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507";						-- $F8A08/2
-	BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
-	BL_HRAM7[7..0].ENA  = BL_HRAM7_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 8
-	BL_HRAM8[].CLK = MAIN_CLK;
-	BL_HRAM8[15..0] = FB_AD[31..16];
-	BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508";						-- $F8A10/2
-	BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
-	BL_HRAM8[7..0].ENA  = BL_HRAM8_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 9
-	BL_HRAM9[].CLK = MAIN_CLK;
-	BL_HRAM9[15..0] = FB_AD[31..16];
-	BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509";						-- $F8A12/2
-	BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
-	BL_HRAM9[7..0].ENA  = BL_HRAM9_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 10
-	BL_HRAMA[].CLK = MAIN_CLK;
-	BL_HRAMA[15..0] = FB_AD[31..16];
-	BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A";						-- $F8A4/2
-	BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
-	BL_HRAMA[7..0].ENA  = BL_HRAMA_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 11
-	BL_HRAMB[].CLK = MAIN_CLK;
-	BL_HRAMB[15..0] = FB_AD[31..16];
-	BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B";						-- $F8A16/2
-	BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
-	BL_HRAMB[7..0].ENA  = BL_HRAMB_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 12
-	BL_HRAMC[].CLK = MAIN_CLK;
-	BL_HRAMC[15..0] = FB_AD[31..16];
-	BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C";						-- $F8A18/2
-	BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
-	BL_HRAMC[7..0].ENA  = BL_HRAMC_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 13
-	BL_HRAMD[].CLK = MAIN_CLK;
-	BL_HRAMD[15..0] = FB_AD[31..16];
-	BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D";						-- $F8A1A/2
-	BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
-	BL_HRAMD[7..0].ENA  = BL_HRAMD_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 14
-	BL_HRAME[].CLK = MAIN_CLK;
-	BL_HRAME[15..0] = FB_AD[31..16];
-	BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E";						-- $F8A1C/2
-	BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
-	BL_HRAME[7..0].ENA  = BL_HRAME_CS & !nFB_WR & FB_16B1;
-	-- HALFTON RAM 15
-	BL_HRAMF[].CLK = MAIN_CLK;
-	BL_HRAMF[15..0] = FB_AD[31..16];
-	BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F";						-- $F8A1E/2
-	BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
-	BL_HRAMF[7..0].ENA  = BL_HRAMF_CS & !nFB_WR & FB_16B1;
-	-- SRC X INC
-	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[] = FB_AD[31..16];
-	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20/2
-	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC Y INC
-	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[] = FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22/2
-	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR HIGH
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
-	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[23..16].ENA  = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR LOW
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..0] = FB_AD[31..16];
-	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
-	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 1
-	BL_ENDMASK1[].CLK = MAIN_CLK;
-	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";					-- $F8A28/2
-	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 2
-	BL_ENDMASK2[].CLK = MAIN_CLK;
-	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";					-- $F8A2A/2
-	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 3
-	BL_ENDMASK3[].CLK = MAIN_CLK;
-	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";					-- $F8A2C/2
-	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-	-- DST X INC
-	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[] = FB_AD[31..16];
-	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";					-- $F8A2E/2
-	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	-- DST Y INC
-	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[] = FB_AD[31..16];
-	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";					-- $F8A30/2
-	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	-- DST ADR HIGH
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24/2
-	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[23..16].ENA  = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-	-- DST ADR LOW
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..0] = FB_AD[31..16];
-	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";					-- $F8A26/2
-	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-	-- X COUNT
-	BL_X_CNT[].CLK = MAIN_CLK;
-	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";						-- $F8A36/2
-	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
-	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-	-- Y COUNT
-	BL_Y_CNT[].CLK = MAIN_CLK;
-	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";						-- $F8A38/2
-	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
-	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-	-- HALFTONE OP BYT
-	BL_HT_OP[].CLK = MAIN_CLK;
-	BL_HT_OP[] = FB_AD[31..24];
-	BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A/2
-	BL_HT_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B0;
-	-- LOGIC OP BYT
-	BL_LC_OP[].CLK = MAIN_CLK;
-	BL_LC_OP[] = FB_AD[23..16];
-	BL_LC_OP[7..0].ENA  = BL_HT_OP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
-	-- LINE NUMBER BYT
-	BL_LN[].CLK = MAIN_CLK;
-	BL_LN[] = FB_AD[31..24];
-	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";							-- $F8A3C/2
-	BL_LN[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;
-	-- SKEW BYT
-	BL_SKEW[].CLK = MAIN_CLK;
-	BL_SKEW[] = FB_AD[31..24];
-	BL_SKEW[7..0].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						BL_HRAM0_CS	& BL_HRAM0[15..0]
-					  #	BL_HRAM1_CS	& BL_HRAM1[15..0]
-					  #	BL_HRAM2_CS	& BL_HRAM2[15..0]
-					  #	BL_HRAM3_CS	& BL_HRAM3[15..0]
-					  #	BL_HRAM4_CS	& BL_HRAM4[15..0]
-					  #	BL_HRAM5_CS	& BL_HRAM5[15..0]
-					  #	BL_HRAM6_CS	& BL_HRAM6[15..0]
-					  #	BL_HRAM7_CS	& BL_HRAM7[15..0]
-					  #	BL_HRAM8_CS	& BL_HRAM8[15..0]
-					  #	BL_HRAM9_CS	& BL_HRAM9[15..0]
-					  #	BL_HRAMA_CS	& BL_HRAMA[15..0]
-					  #	BL_HRAMB_CS	& BL_HRAMB[15..0]
-					  #	BL_HRAMC_CS	& BL_HRAMC[15..0]
-					  #	BL_HRAMD_CS	& BL_HRAMD[15..0]
-					  #	BL_HRAME_CS	& BL_HRAME[15..0]
-					  #	BL_HRAMF_CS	& BL_HRAMF[15..0]
-					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
-					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & BL_SRC_ADR[31..16]
-					  # BL_SRC_ADRL_CS  & BL_SRC_ADR[15..0]
-					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
-					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
-					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
-					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
-					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & BL_DST_ADR[31..16]
-					  # BL_DST_ADRL_CS  & BL_DST_ADR[15..0]
-					  # BL_X_CNT_CS 	& BL_X_CNT[]
-					  # BL_Y_CNT_CS 	& BL_Y_CNT[]
-					  # BL_HT_OP_CS 	& (BL_HT_OP[],BL_LC_OP[])
-					  # BL_LN_CS 		& (BL_LN[],BL_SKEW[])
-					  ,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); 				-- FFFF8A00-3F/40
------------------------------------------
---  
-	BL_READ_SRC.CLK = DDRCLK0;
-	BL_READ_DST.CLK = DDRCLK0;
-
-	
-	BLITTER_RUN = VCC;
-	BLITTER_SIG = VCC;
-	BLITTER_WR = VCC;
--- READY SIGNAL 1 CLOCK SPÄTER
-	BL_DATA_DDR_READY.CLK	= DDRCLK0;
-	BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
--- SRC BUFFER LADEN
-	BL_SKEW_IN[].CLK = DDRCLK0;
-	BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
-	BL_SKEW_IN[255..128] = BLITTER_DIN[];
-	BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
--- DST BUFFER LADEN	
-	BL_DST_BUFFER[].CLK = DDRCLK0;
-	BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
-	BL_DST_BUFFER[] = BLITTER_DIN[];
--- SKEW EXTENDET
-	BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
-	BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
--- SKEW EXT MUX
-	BL_SKEW_OUT[].CLK = DDRCLK0;
-	BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
-	BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]);	-- BIT 127..0 SIND RELEVANT
-	
-	COUNT[] = COUNT[] + 16;
-	COUNT[].CLK = BLITTER_DACK0;
-	BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
-	BLITTER_ADR[] = (0, COUNT[]) + 400000;
-	
-END;
-
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
deleted file mode 100644
index 9b12256..0000000
--- a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.bsf
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 208 80)
-	(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 61 31 76)(font "Arial" ))
-	(port
-		(pt 0 24)
-		(input)
-		(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
-		(line (pt 0 24)(pt 16 24)(line_width 3))
-	)
-	(port
-		(pt 0 40)
-		(input)
-		(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
-		(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 16 40)(line_width 3))
-	)
-	(port
-		(pt 208 24)
-		(output)
-		(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
-		(line (pt 208 24)(pt 192 24)(line_width 3))
-	)
-	(drawing
-		(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
-		(line (pt 16 16)(pt 16 64)(line_width 1))
-		(line (pt 192 16)(pt 192 64)(line_width 1))
-		(line (pt 16 16)(pt 192 16)(line_width 1))
-		(line (pt 16 64)(pt 192 64)(line_width 1))
-	)
-)
diff --git a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.inc
similarity index 69%
rename from FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp
rename to FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.inc
index d0a0d93..b8538c0 100644
--- a/FPGA_by_Fredi/Video/BLITTER/altsyncram0.cmp
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.inc
@@ -13,14 +13,13 @@
 --applicable agreement for further details.
 
 
-component altsyncram0
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
-		byteena_a		: IN STD_LOGIC_VECTOR (1 DOWNTO 0) :=  (OTHERS => '1');
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		wren		: IN STD_LOGIC  := '0';
-		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-end component;
+FUNCTION lpm_clshift144 
+(
+	data[143..0],
+	direction,
+	distance[7..0]
+)
+
+RETURNS (
+	result[143..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip
new file mode 100644
index 0000000..8686c8a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.inc"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf
new file mode 100644
index 0000000..1ea9db4
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf
@@ -0,0 +1,94 @@
+-- megafunction wizard: %LPM_CLSHIFT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_clshift 
+
+-- ============================================================
+-- File Name: lpm_clshift144.tdf
+-- Megafunction Name(s):
+-- 			lpm_clshift
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_clshift.inc";
+
+
+
+SUBDESIGN lpm_clshift144
+(
+	data[143..0]	 : INPUT;
+	direction	 : INPUT;
+	distance[7..0]	 : INPUT;
+	result[143..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_clshift_component : lpm_clshift WITH (
+			LPM_SHIFTTYPE = "LOGICAL",
+			LPM_TYPE = "LPM_CLSHIFT",
+			LPM_WIDTH = 144,
+			LPM_WIDTHDIST = 8
+			);
+
+BEGIN
+
+	result[143..0] = lpm_clshift_component.result[143..0];
+	lpm_clshift_component.distance[7..0] = distance[7..0];
+	lpm_clshift_component.direction = direction;
+	lpm_clshift_component.data[143..0] = data[143..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "144"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
+-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
+-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
+-- Retrieval info: PRIVATE: port_direction NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
+-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
+-- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
+-- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
+-- Retrieval info: USED_PORT: result 0 0 144 0 OUTPUT NODEFVAL result[143..0]
+-- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
+-- Retrieval info: CONNECT: result 0 0 144 0 @result 0 0 144 0
+-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.inc b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.inc
new file mode 100644
index 0000000..dc44264
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_clshift384 
+(
+	data[383..0],
+	direction,
+	distance[7..0]
+)
+
+RETURNS (
+	result[383..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.qip b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.qip
new file mode 100644
index 0000000..ade4236
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.cmp"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.tdf
similarity index 62%
rename from FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf
rename to FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.tdf
index d7d910f..deac5a7 100644
--- a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.tdf
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_clshift384.tdf
@@ -36,11 +36,12 @@ INCLUDE "lpm_clshift.inc";
 
 
 
-SUBDESIGN lpm_clshift0
+SUBDESIGN lpm_clshift384
 (
-	data[255..0]	 : INPUT;
-	distance[6..0]	 : INPUT;
-	result[255..0]	 : OUTPUT;
+	data[383..0]	: INPUT;
+	direction	 	: INPUT;
+	distance[7..0]	: INPUT;
+	result[383..0]	: OUTPUT;
 )
 
 VARIABLE
@@ -48,16 +49,16 @@ VARIABLE
 	lpm_clshift_component : lpm_clshift WITH (
 			LPM_SHIFTTYPE = "LOGICAL",
 			LPM_TYPE = "LPM_CLSHIFT",
-			LPM_WIDTH = 256,
-			LPM_WIDTHDIST = 7
+			LPM_WIDTH = 384,
+			LPM_WIDTHDIST = 8
 			);
 
 BEGIN
 
-	result[255..0] = lpm_clshift_component.result[255..0];
-	lpm_clshift_component.distance[6..0] = distance[6..0];
-	lpm_clshift_component.direction = VCC;
-	lpm_clshift_component.data[255..0] = data[255..0];
+	result[383..0] = lpm_clshift_component.result[383..0];
+	lpm_clshift_component.distance[7..0] = distance[7..0];
+	lpm_clshift_component.direction = direction;
+	lpm_clshift_component.data[383..0] = data[383..0];
 END;
 
 
@@ -67,26 +68,27 @@ END;
 -- ============================================================
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
--- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256"
+-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "384"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
--- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
--- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
--- Retrieval info: PRIVATE: port_direction NUMERIC "1"
+-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
+-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
+-- Retrieval info: PRIVATE: port_direction NUMERIC "2"
 -- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256"
--- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
--- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0]
--- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
--- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0]
--- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
--- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0
--- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0
--- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "384"
+-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 384 0 INPUT NODEFVAL data[383..0]
+-- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
+-- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
+-- Retrieval info: USED_PORT: result 0 0 384 0 OUTPUT NODEFVAL result[383..0]
+-- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 384 0 data 0 0 384 0
+-- Retrieval info: CONNECT: result 0 0 384 0 @result 0 0 384 0
+-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf b/FPGA_by_Fredi/Video/DDR_CTR.tdf
index 6c74c7a..72bee92 100644
--- a/FPGA_by_Fredi/Video/DDR_CTR.tdf
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf
@@ -6,8 +6,8 @@ INCLUDE "lpm_bustri_BYT.inc";
 
 -- FIFO WATER MARK
 CONSTANT FIFO_LWM = 0;
-CONSTANT FIFO_MWM = 200;
-CONSTANT FIFO_HWM = 500;
+CONSTANT FIFO_MWM = 1000;
+CONSTANT FIFO_HWM = 2000;
 
 -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
 -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
@@ -34,7 +34,7 @@ SUBDESIGN DDR_CTR
 	BLITTER_WR : INPUT;
 	DDRCLK0 : INPUT;
 	CLK33M : INPUT;
-	FIFO_MW[8..0] : INPUT;
+	FIFO_MW[10..0] : INPUT;
 	VA[12..0] : OUTPUT;
 	nVWE : OUTPUT;
 	nVRAS : OUTPUT;
@@ -205,26 +205,13 @@ BEGIN
 	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
 	DDR_CONFIG = VIDEO_RAM_CTR3;	
 	FIFO_ACTIVE = VIDEO_RAM_CTR8;
---------------------------------
+----------------------------------------------------------------
+-- CPU ---------------------------
+--------------------------------------------------------
 	CPU_ROW_ADR[] = FB_ADR[26..14];
 	CPU_BA[] = FB_ADR[13..12];
 	CPU_COL_ADR[] = FB_ADR[11..2];
-	nVRAS = !VRAS;
-	nVCAS = !VCAS;
-	nVWE = !VWE;
-	SR_DDR_WR.CLK = DDRCLK0;
-	SR_DDRWR_D_SEL.CLK = DDRCLK0;
-	SR_VDMP[7..0].CLK = DDRCLK0;
-	SR_FIFO_WRE.CLK = DDRCLK0; 
 	CPU_AC.CLK = DDRCLK0;
-	FIFO_AC.CLK = DDRCLK0;
-	BLITTER_AC.CLK = DDRCLK0;
-	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
-	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
-	DDR_CS.CLK = MAIN_CLK;
-	DDR_CS.ENA = FB_ALE;
-	DDR_CS	 = DDR_SEL;
 -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
 	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
 			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
@@ -234,6 +221,30 @@ BEGIN
 			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
 	BUS_CYC.CLK = DDRCLK0;
 	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA[] = BLITTER_ADR[13..12];
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+---------------------------------------------------
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	FIFO_AC.CLK = DDRCLK0;
 	-- STATE MACHINE SYNCHRONISIEREN -----------------
 	MCS[].CLK = DDRCLK0;
 	MCS0 = MAIN_CLK;
@@ -563,15 +574,6 @@ BEGIN
 			DDR_SM = DS_T1;
 	END CASE;
 
----------------------------------------------------------------
--- BLITTER ----------------------
------------------------------------------
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
-	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
-	BLITTER_BA1 = BLITTER_ADR13;
-	BLITTER_BA0 = BLITTER_ADR12;
-	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
 ------------------------------------------------------------------------------	
 -- FIFO ---------------------------------
 --------------------------------------------------------
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
deleted file mode 100644
index d5b5ec2..0000000
--- a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
+++ /dev/null
@@ -1,659 +0,0 @@
-TITLE "DDR_CTR";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_BYT.inc";
-
--- FIFO WATER MARK
-CONSTANT FIFO_LWM = 0;
-CONSTANT FIFO_MWM = 200;
-CONSTANT FIFO_HWM = 500;
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN DDR_CTR
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	DDR_SYNC_66M : INPUT;
-	CLR_FIFO : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ADR[31..0] : INPUT;
-	BLITTER_SIG : INPUT;
-	BLITTER_WR : INPUT;
-	DDRCLK0 : INPUT;
-	CLK33M : INPUT;
-	FIFO_MW[8..0] : INPUT;
-	VA[12..0] : OUTPUT;
-	nVWE : OUTPUT;
-	nVRAS : OUTPUT;
-	nVCS : OUTPUT;
-	VCKE : OUTPUT;
-	nVCAS : OUTPUT;
-	FB_LE[3..0] : OUTPUT;
-	FB_VDOE[3..0] : OUTPUT;
-	SR_FIFO_WRE : OUTPUT;
-	SR_DDR_FB : OUTPUT;
-	SR_DDR_WR : OUTPUT;
-	SR_DDRWR_D_SEL : OUTPUT;
-	SR_VDMP[7..0] : OUTPUT;
-	VIDEO_DDR_TA : OUTPUT;
-	SR_BLITTER_DACK : OUTPUT;
-	BA[1..0] : OUTPUT;
-	DDRWR_D_SEL1 : OUTPUT;
-	VDM_SEL[3..0] : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
-													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
-												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
-												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
-												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
-																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
-												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
-	LINE					:NODE;
-	FB_B[3..0]				:NODE;
-	VCAS					:NODE;
-	VRAS					:NODE;
-	VWE						:NODE;
-	VA_P[12..0]				:DFF;
-	BA_P[1..0]				:DFF;
-	VA_S[12..0]				:DFF;
-	BA_S[1..0]				:DFF;
-	MCS[1..0]				:DFF;
-	CPU_DDR_SYNC			:DFF;
-	DDR_SEL					:NODE;
-	DDR_CS					:DFFE;
-	DDR_CONFIG				:NODE;
-	SR_DDR_WR				:DFF;
-	SR_DDRWR_D_SEL			:DFF;
-	SR_VDMP[7..0] 			:DFF;
-	CPU_ROW_ADR[12..0]		:NODE;
-	CPU_BA[1..0]			:NODE;
-	CPU_COL_ADR[9..0]		:NODE;
-	CPU_SIG					:NODE;
-	CPU_REQ					:DFF;
-	CPU_AC					:DFF;
-	BUS_CYC					:DFF;
-	BUS_CYC_END				:NODE;
-	BLITTER_REQ				:DFF;
-	BLITTER_AC				:DFF;
-	BLITTER_ROW_ADR[12..0]	:NODE;
-	BLITTER_BA[1..0]		:NODE;
-	BLITTER_COL_ADR[9..0]	:NODE;
-	FIFO_REQ				:DFF;
-	FIFO_AC					:DFF;
-	FIFO_ROW_ADR[12..0]		:NODE;
-	FIFO_BA[1..0]			:NODE;
-	FIFO_COL_ADR[9..0]		:NODE;
-	FIFO_ACTIVE				:NODE;
-	CLR_FIFO_SYNC			:DFF;
-	CLEAR_FIFO_CNT			:DFF;
-	STOP					:DFF;
-	SR_FIFO_WRE				:DFF;
-	FIFO_BANK_OK			:DFF;
-	FIFO_BANK_NOT_OK		:NODE;
-	DDR_REFRESH_ON			:NODE;
-	DDR_REFRESH_CNT[10..0]	:DFF;
-	DDR_REFRESH_REQ			:DFF;
-	DDR_REFRESH_SIG[3..0]	:DFFE;
-	REFRESH_TIME			:DFF;
-	VIDEO_BASE_L_D[7..0]	:DFFE;
-	VIDEO_BASE_L			:NODE;
-	VIDEO_BASE_M_D[7..0]	:DFFE;
-	VIDEO_BASE_M			:NODE;
-	VIDEO_BASE_H_D[7..0]	:DFFE;
-	VIDEO_BASE_H			:NODE;
-	VIDEO_BASE_X_D[2..0]	:DFFE;
-	VIDEO_ADR_CNT[22..0]	:DFFE;
-	VIDEO_CNT_L				:NODE;
-	VIDEO_CNT_M				:NODE;
-	VIDEO_CNT_H				:NODE;
-	VIDEO_BASE_ADR[22..0]	:NODE;
-	VIDEO_ACT_ADR[26..0]	:NODE;
-	
-BEGIN
-	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
-	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
-	FB_REGDDR.CLK = MAIN_CLK;
-	CASE FB_REGDDR IS
-		WHEN FR_WAIT => 
-			FB_LE0   = !nFB_WR;
-			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
-				FB_REGDDR = FR_S0;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S0 =>
-			IF DDR_CS THEN
-				FB_LE0   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				IF LINE THEN							
-					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
-					FB_REGDDR = FR_S1;
-				ELSE
-					BUS_CYC_END = VCC;
-					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-					FB_REGDDR = FR_WAIT;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;	
-			END IF;
-		WHEN FR_S1 => 
-			IF DDR_CS THEN
-				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
-				FB_LE1   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				FB_REGDDR = FR_S2;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S2 => 
-			IF DDR_CS THEN
-				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
-				FB_LE2   = !nFB_WR;
-				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
-					FB_REGDDR = FR_S2;
-				ELSE
-					VIDEO_DDR_TA = VCC;
-					FB_REGDDR = FR_S3;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S3 => 
-			IF DDR_CS THEN
-				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-				FB_LE3   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				BUS_CYC_END = VCC;
-				FB_REGDDR = FR_WAIT;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
--- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
-	VCKE = VIDEO_RAM_CTR0;
-	nVCS = !VIDEO_RAM_CTR1;
-	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
-	DDR_CONFIG = VIDEO_RAM_CTR3;	
-	FIFO_ACTIVE = VIDEO_RAM_CTR8;
---------------------------------
-	CPU_ROW_ADR[] = FB_ADR[26..14];
-	CPU_BA[] = FB_ADR[13..12];
-	CPU_COL_ADR[] = FB_ADR[11..2];
-	nVRAS = !VRAS;
-	nVCAS = !VCAS;
-	nVWE = !VWE;
-	SR_DDR_WR.CLK = DDRCLK0;
-	SR_DDRWR_D_SEL.CLK = DDRCLK0;
-	SR_VDMP[7..0].CLK = DDRCLK0;
-	SR_FIFO_WRE.CLK = DDRCLK0; 
-	CPU_AC.CLK = DDRCLK0;
-	FIFO_AC.CLK = DDRCLK0;
-	BLITTER_AC.CLK = DDRCLK0;
-	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
-	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
-	DDR_CS.CLK = MAIN_CLK;
-	DDR_CS.ENA = FB_ALE;
-	DDR_CS	 = DDR_SEL;
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
-	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
-			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
-			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
-	CPU_REQ.CLK = DDR_SYNC_66M;
-	CPU_REQ = CPU_SIG 
-			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
-	BUS_CYC.CLK = DDRCLK0;
-	BUS_CYC = BUS_CYC & !BUS_CYC_END;
-	-- STATE MACHINE SYNCHRONISIEREN -----------------
-	MCS[].CLK = DDRCLK0;
-	MCS0 = MAIN_CLK;
-	MCS1 = MCS0;		
-	CPU_DDR_SYNC.CLK = DDRCLK0;
-	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
-	---------------------------------------------------
-	VA_S[].CLK = DDRCLK0;
-	BA_S[].CLK = DDRCLK0;
-	VA[] =  VA_S[];
-	BA[] =  BA_S[];
-	VA_P[].CLK = DDRCLK0;
-	BA_P[].CLK = DDRCLK0;
--- DDR STATE MACHINE  -----------------------------------------------
-	DDR_SM.CLK = DDRCLK0;
-	CASE DDR_SM IS
-		WHEN DS_T1 =>
-			IF DDR_REFRESH_REQ THEN
-				DDR_SM = DS_R2;
-			ELSE
-				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
-					IF DDR_CONFIG THEN							-- JA
-						DDR_SM = DS_C2;
-					ELSE
-						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
-							VA_S[] = CPU_ROW_ADR[];
-							BA_S[] = CPU_BA[];
-							CPU_AC = VCC;
-							BUS_CYC = VCC;
-							DDR_SM = DS_T2B;
-						ELSE
-							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
-								VA_P[] = FIFO_ROW_ADR[];
-								BA_P[] = FIFO_BA[];
-								FIFO_AC = VCC;						-- VORBESETZEN
-							ELSE
-								VA_P[] = BLITTER_ROW_ADR[];
-								BA_P[] = BLITTER_BA[];
-								BLITTER_AC = VCC;					-- VORBESETZEN
-							END IF;
-							DDR_SM = DS_T2A;
-						END IF;
-					END IF;
-				ELSE
-					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
-				END IF;
-			END IF;
-			
-		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
-			IF DDR_SEL & (nFB_WR # !LINE) THEN
-				VRAS = VCC;
-				VA[] = FB_AD[26..14];
-				BA[] = FB_AD[13..12]; 
-				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
-				CPU_AC = VCC;
-				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
-			ELSE
-				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
-				VA[] = VA_P[];
-				BA[] = BA_P[]; 
-				VA_S[10] = !(FIFO_AC & FIFO_REQ);
-				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
-				FIFO_AC = FIFO_AC & FIFO_REQ;
-				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
-			END IF;	
-			DDR_SM = DS_T3;
-
-		WHEN DS_T2B =>
-			VRAS = VCC;
-			FIFO_BANK_NOT_OK = VCC;
-			CPU_AC = VCC;
-			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
-			DDR_SM = DS_T3;
-
-		WHEN DS_T3 =>
-			CPU_AC = CPU_AC;
-			FIFO_AC = FIFO_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
-				DDR_SM = DS_T4W;
-			ELSE
-				IF CPU_AC THEN										-- CPU?
-					VA_S[9..0] = CPU_COL_ADR[];
-					BA_S[] = CPU_BA[];
-					DDR_SM = DS_T4R;												 
-				ELSE
-					IF FIFO_AC THEN									-- FIFO?
-						VA_S[9..0] = FIFO_COL_ADR[];
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T4F;
-					ELSE
-						IF BLITTER_AC THEN
-							VA_S[9..0] = BLITTER_COL_ADR[];
-							BA_S[] = BLITTER_BA[];
-							DDR_SM = DS_T4R;												 
-						ELSE
-							DDR_SM = DS_N8;
-						END IF;
-					END IF;
-				END IF;
-			END IF;
--- READ			
-		WHEN DS_T4R =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
-			DDR_SM = DS_T5R;	
-			
-		WHEN DS_T5R =>
- 			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
- 				VA_S[9..0] = FIFO_COL_ADR[];
- 				VA_S[10] = GND;										-- MANUEL PRECHARGE
- 				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
- 			ELSE	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- WRITE			
-		WHEN DS_T4W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
- 			DDR_SM = DS_T5W;
-			
-		WHEN DS_T5W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
-					   # BLITTER_AC & BLITTER_COL_ADR[];
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			BA_S[]  = CPU_AC     & CPU_BA[]
-				    # BLITTER_AC & BLITTER_BA[];
-			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
-			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
-			DDR_SM = DS_T6W;
-			
-		WHEN DS_T6W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			VWE  = VCC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
-			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
-			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
-			DDR_SM = DS_T7W;
-
-		WHEN DS_T7W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
-			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
-			DDR_SM = DS_T8W;
-
-		WHEN DS_T8W =>								 
-			DDR_SM = DS_T9W;
-
-		WHEN DS_T9W =>								 
-			IF FIFO_REQ & FIFO_BANK_OK  THEN
-				VA_S[9..0] = FIFO_COL_ADR[];
-				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
-				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- FIFO READ 
-		WHEN DS_T4F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T5F;
-			
-		WHEN DS_T5F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
-					VA_S[9..0] = FIFO_COL_ADR[]+4;
-					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_S[] = FIFO_BA[];
-					DDR_SM = DS_T6F;
-				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
-			END IF;
-			
-		WHEN DS_T6F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T7F;
-																							 
-		WHEN DS_T7F =>
-			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
-				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
-			ELSE
-				IF FIFO_REQ THEN
-					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
-						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
-						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
-					ELSE
-						VA_S[9..0] = FIFO_COL_ADR[]+4;
-						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T8F;
-					END IF;											 
-				ELSE
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
-					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
-				END IF;
-			END IF;
-			
-		WHEN DS_T8F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
-				DDR_SM = DS_T5F;									-- JA->
-			ELSE
-				DDR_SM = DS_T9F;
-			END IF;																	 
-			
-		WHEN DS_T9F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
- 					VA_P[9..0] = FIFO_COL_ADR[]+4;
-					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_P[] = FIFO_BA[];
-					DDR_SM = DS_T10F;
- 				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
-				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
-			END IF;
-
-		WHEN DS_T10F =>
- 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
- 				VRAS = VCC;
- 				VA[] = FB_AD[26..14];
- 				BA[] = FB_AD[13..12]; 
- 				CPU_AC = VCC;
- 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
- 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
- 				DDR_SM = DS_T3;
- 			ELSE
-				VCAS = VCC;
-				VA[] = VA_P[];
-				BA[] = BA_P[];
-				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
-				DDR_SM = DS_T7F;
-			END IF;	
-
--- CONFIG CYCLUS
-		WHEN DS_C2 =>
-			DDR_SM = DS_C3;
-		WHEN DS_C3 =>
-			BUS_CYC = CPU_REQ;
-			DDR_SM = DS_C4;
-		WHEN DS_C4 =>
-			IF CPU_REQ THEN
-				DDR_SM = DS_C5;
-			ELSE
-				DDR_SM = DS_T1;
-			END IF;	
-		WHEN DS_C5 =>
-			DDR_SM = DS_C6;
-		WHEN DS_C6 =>
-			VA_S[] = FB_AD[12..0];
-			BA_S[] = FB_AD[14..13];
-			DDR_SM = DS_C7;
-		WHEN DS_C7 =>
-			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			DDR_SM = DS_N8;
--- CLOSE FIFO BANK
-		WHEN DS_CB6 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- BÄNKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_N7;
-		WHEN DS_CB8 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- BÄNKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_T1;
--- REFRESH 70NS = 10 ZYCLEN
-		WHEN DS_R2 =>
-			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
-				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
-				VWE = VCC;		
-				VA[10] = VCC;
-				FIFO_BANK_NOT_OK = VCC;
-				DDR_SM = DS_R4;
-			ELSE
-				VCAS = VCC;
-				VRAS = VCC;
-				DDR_SM = DS_R3;
-			END IF;
-		WHEN DS_R3 =>
-			DDR_SM = DS_R4;
-		WHEN DS_R4 =>
-			DDR_SM = DS_R5;
-		WHEN DS_R5 =>
-			DDR_SM = DS_R6;
-		WHEN DS_R6 =>
-			DDR_SM = DS_N5;
--- LEERSCHLAUFE			
-		WHEN DS_N5 =>
-			DDR_SM = DS_N6;
-		WHEN DS_N6 =>
-			DDR_SM = DS_N7;
-		WHEN DS_N7 =>
-			DDR_SM = DS_N8;
-		WHEN DS_N8 =>
-			DDR_SM = DS_T1;
-	END CASE;
-
----------------------------------------------------------------
--- BLITTER ----------------------
------------------------------------------
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
-	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
-	BLITTER_BA1 = BLITTER_ADR13;
-	BLITTER_BA0 = BLITTER_ADR12;
-	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
-------------------------------------------------------------------------------	
--- FIFO ---------------------------------
---------------------------------------------------------
-	FIFO_REQ.CLK = DDRCLK0;
-	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
-			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
-	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
-	FIFO_BA1 	   = VIDEO_ADR_CNT9;
-	FIFO_BA0 	   = VIDEO_ADR_CNT8;
-	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
-	FIFO_BANK_OK.CLK = DDRCLK0;
-	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
-	CLR_FIFO_SYNC.CLK =DDRCLK0;
-	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
-	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
-	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
-	STOP.CLK = DDRCLK0;
-	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-	-- ZÄHLEN -----------------------------------------------
-	VIDEO_ADR_CNT[].CLK = DDRCLK0;
-	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
-	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
-					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
-	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
-	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
-	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
-	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
-	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-	-- AKTUELLE VIDEO ADRESSE
-	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
-	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
------------------------------------------------------------------------------------------
--- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
------------------------------------------------------------------------------------------
-	DDR_REFRESH_CNT[].CLK = CLK33M;
-	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
-	REFRESH_TIME.CLK = DDRCLK0;
-	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
-	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
-	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
-	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
-					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
-	DDR_REFRESH_REQ.CLK = DDRCLK0;
-	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
------------------------------------------------------------	
--- VIDEO REGISTER -----------------------
----------------------------------------------------------------------------------------------------------------------
-	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
-	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
-	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
-
-	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
-	VIDEO_BASE_M_D[] = FB_AD[23..16];
-	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
-
-	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
-	VIDEO_BASE_H_D[] = FB_AD[23..16];
-	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
-	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_X_D[] = FB_AD[26..24];
-	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
-
-	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
-	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
-	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
-					  
-	FB_AD[31..24] = lpm_bustri_BYT(
-						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
-					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
-					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
-
-	FB_AD[23..16] = lpm_bustri_BYT(
-						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
-					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
-					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
-					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
-					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
-					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
-					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
-END;
-
diff --git a/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
deleted file mode 100644
index 03052b4..0000000
--- a/FPGA_by_Fredi/Video/DDR_CTR_BLITTER.tdf.bak
+++ /dev/null
@@ -1,352 +0,0 @@
-TITLE "DDR_CTR_BLITTER";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_BYT.inc";
-
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN DDR_CTR_BLITTER
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FIFO_FULL : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	DDR_SYNC_66M : INPUT;
-	VSYNC : INPUT;
-	BLITTER_ON : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	VDVZ[127..0] : INPUT;
-	DDRCLK[3..0] : INPUT;
-	BA0 : OUTPUT;
-	BA1 : OUTPUT;
-	VA[12..0] : OUTPUT;
-	nVWE : OUTPUT;
-	nVRAS : OUTPUT;
-	nVCS : OUTPUT;
-	VCKE : OUTPUT;
-	nVCAS : OUTPUT;
-	FIFO_WRE : OUTPUT;
-	FB_LE[3..0] : OUTPUT;
-	FB_VDOE[3..0] : OUTPUT;
-	START_CYC_RDWR : OUTPUT;
-	DDR_WR : OUTPUT;
-	CLEAR_FIFO_CNT : OUTPUT;
-	BLITTER_RUN : OUTPUT;
-	BLITTER_DOUT[127..0] : OUTPUT;
-	BLITTER_LE[3..0] : OUTPUT;
-	BLITTER_RDE : OUTPUT;
-	DDRWR_D_SEL[1..0] : OUTPUT;
-	VDMP[7..0] : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
-	LINE					:NODE;
-	FB_B[3..0]				:NODE;
-	VCAS					:NODE;
-	VRAS					:NODE;
-	VWE						:NODE;
-	VA[12..0]				:NODE;
-	BA0						:NODE;
-	BA1						:NODE;
-	DDR_WR					:DFF;
-	DDR_SEL					:NODE;
-	DDR_CONFIG				:NODE;
-	DDRWR_D_SEL[1..0]		:DFF;
-	CPU_ROW_ADR[12..0]		:NODE;
-	CPU_BA0					:NODE;
-	CPU_BA1					:NODE;
-	CPU_COL_ADR[9..0]		:NODE;
-	CPU_SIG					:NODE;
-	CPU_REQ					:DFF;
-	BLITTER_SIG				:NODE;
-	BLITTER_REQ				:DFF;
-	BLITTER_RUN				:DFF;
-	BLITTER_WR				:DFF;
-	BLITTER_ROW_ADR[12..0]	:NODE;
-	BLITTER_BA0				:NODE;
-	BLITTER_BA1				:NODE;
-	BLITTER_COL_ADR[9..0]	:NODE;
-	FIFO_SIG				:NODE;
-	FIFO_REQ				:DFF;
-	FIFO_ROW_ADR[12..0]		:NODE;
-	FIFO_BA0				:NODE;
-	FIFO_BA1				:NODE;
-	FIFO_COL_ADR[9..0]		:NODE;
-	FIFO_WRE				:DFF;
-	FIFO_ACTIVE				:NODE;
-	CLEAR_FIFO_CNT			:DFF;
-	STOP					:DFF;
-	DDR_REFRESH_ON			:NODE;
-	VIDEO_BASE_L_D[3..0]	:DFFE;
-	VIDEO_BASE_L			:NODE;
-	VIDEO_BASE_M_D[7..0]	:DFFE;
-	VIDEO_BASE_M			:NODE;
-	VIDEO_BASE_H_D[7..0]	:DFFE;
-	VIDEO_BASE_H			:NODE;
-	VIDEO_BASE_X_D[7..0]	:DFFE;
-	VIDEO_ADR_CNT[27..0]	:DFFE;
-	VIDEO_CNT_L				:NODE;
-	VIDEO_CNT_M				:NODE;
-	VIDEO_CNT_H				:NODE;
-	VIDEO_BASE_ADR[27..0]	:NODE;
-	
-BEGIN
-	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
-	FB_REGDDR.CLK = MAIN_CLK;
-	CASE FB_REGDDR IS
-		WHEN FR_WAIT => 
-			IF DDR_SEL THEN
-				FB_REGDDR = FR_S0;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S0 =>
-			FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
-			FB_LE0   = !nFB_WR;
-			IF LINE THEN							
-				FB_REGDDR = FR_S1;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S1 => 
-			FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
-			FB_LE1   = !nFB_WR;
-			FB_REGDDR = FR_S2;
-		WHEN FR_S2 => 
-			FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
-			FB_LE2   = !nFB_WR;
-			FB_REGDDR = FR_S3;
-		WHEN FR_S3 => 
-			FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
-			FB_LE3   = !nFB_WR;
-			FB_REGDDR = FR_WAIT;
-	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
--- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
-	VCKE = VIDEO_RAM_CTR0;
-	nVCS = !VIDEO_RAM_CTR1;
-	FIFO_ACTIVE = VIDEO_RAM_CTR2;
-	DDR_CONFIG = VIDEO_RAM_CTR3;	
-	DDR_REFRESH_ON = VIDEO_RAM_CTR4;
---------------------------------
-	CPU_ROW_ADR[] = FB_ADR[26..14];
-	CPU_BA1 = FB_ADR13;
-	CPU_BA0 = FB_ADR12;
-	CPU_COL_ADR[] = FB_ADR[11..2];
-	nVRAS = !VRAS;
-	nVCAS = !VCAS;
-	nVWE = !VWE;
-	DDR_WR.CLK = DDRCLK0;
--- SELECT LOGIC
-	DDR_SEL  =  FB_ALE & FB_AD[31..29]==B"011";
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
-	CPU_SIG = DDR_SEL &  nFB_WR & !DDR_CONFIG						-- READ SOFORT LOS
-			# FR_S0   & !nFB_WR 		   							-- WRITE SPÄTER AUCH CONFIG
-			# FR_S3   & !nFB_WR &  LINE  & !DDR_CONFIG;				-- LINE WRITE
-	CPU_REQ = CPU_SIG;
-	CPU_REQ.CLK = DDR_SYNC_66M;
-	DDR_D_SEL[].CLK = DDRCLK3;
--- DDR STATE MACHINE  -----------------------------------------------
-	DDR_SM.CLK = DDRCLK0;
-	CASE DDR_SM IS
-		WHEN DS_T1 =>
-			IF MAIN_CLK THEN
-				DDR_WR = DDR_WR;									-- WRITE HALTEN (VON T4)
-				DDR_SM = DS_T2;
-			ELSE
-				DDR_SM = DS_LS;										-- SYNCHRONISIEREN
-			END IF;
-		WHEN DS_T2 =>
-			IF !DDR_CONFIG THEN
-				VRAS  = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
-				VA[]  = CPU_SIG 	& CPU_ROW_ADR[]
-					#  BLITTER_SIG & BLITTER_ROW_ADR[]
-					#  FIFO_SIG 	& FIFO_ROW_ADR[];
-				BA0   = CPU_SIG 	& CPU_BA0
-					#  BLITTER_SIG & BLITTER_BA0
-					#  FIFO_SIG 	& FIFO_BA0;
-				BA1   = CPU_SIG 	& CPU_BA1
-					#  BLITTER_SIG & BLITTER_BA1
-					#  FIFO_SIG 	& FIFO_BA1;
-				VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON;		-- AUTO REFRESH WENN SONST NICHTS
-				BLITTER_REQ = BLITTER_SIG;
-				FIFO_REQ = FIFO_SIG;	
-			END IF;
-			IF MAIN_CLK THEN
-				DDR_SM = DS_T3;
-			ELSE
-				DDR_SM = DS_LS;
-			END IF;
-		WHEN DS_T3 =>
-			IF DDR_CONFIG & CPU_REQ THEN
-				VRAS = FB_AD18;
-				VCAS = FB_AD17;
-				VWE	 = FB_AD16;
-				BA1  = FB_AD14;
-				BA0  = FB_AD13;
-				VA[] = FB_AD[12..0];
-			END IF;
-			IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
-				DDR_SM = DS_LS;
-			ELSE
-				BLITTER_REQ = BLITTER_SIG;
-				FIFO_REQ = FIFO_SIG;						
-				DDR_SM = DS_T4;
-			END IF;
-		WHEN DS_T4 =>
-			FIFO_REQ = FIFO_SIG;	
-			VCAS = VCC;															
-			VWE  = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
-			VA[9..0] = CPU_REQ     & CPU_COL_ADR[]
-					# BLITTER_REQ & BLITTER_COL_ADR[]
-					# FIFO_REQ    & FIFO_COL_ADR[];
-			VA10 = VCC;															-- AUTO PRECHARGE
-			BA0 = CPU_REQ     & CPU_BA0
-				# BLITTER_REQ & BLITTER_BA0
-				# FIFO_REQ    & FIFO_BA0;
-			BA1 = CPU_REQ     & CPU_BA1
-				# BLITTER_REQ & BLITTER_BA1
-				# FIFO_REQ    & FIFO_BA1;
-			DDR_WR         = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
-			FIFO_REQ = FIFO_SIG;						
-			IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
-				DDR_SM = DS_T5;													-- JA->
-			ELSE
-				DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
-			END IF;
-		WHEN DS_T5 =>
-			FIFO_REQ = FIFO_SIG;	
-			DDR_SM = DS_T6;
-		WHEN DS_T6 =>								 
-			IF CPU_SIG THEN															-- SOFORT UMSCHALTEN WENN CPU REQ
-				VRAS = VCC;
-				VA[] = CPU_ROW_ADR[];
-				BA1  = CPU_BA1;
-				BA0  = CPU_BA0;
-				DDR_SM = DS_T3;
-			ELSE
-				FIFO_REQ = FIFO_SIG;	
-				VCAS = VCC;															
-				VA[9..0] = FIFO_COL_ADR[];
-				VA10 = VCC;															-- AUTO PRECHARGE
-				BA0 = FIFO_BA0;
-				BA1 = FIFO_BA1;
-				FIFO_WRE 	   =  FIFO_REQ;											-- ODER FIFO LATCH IN 5 CYC 133
-				IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
-					DDR_SM = DS_T5;													-- JA->
-				ELSE
-					DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
-				END IF;
-			END IF;
-		WHEN DS_LS =>
-			IF !MAIN_CLK THEN														-- LEERSTATE UND SYNC
-				DDR_SM = DS_T1;	
-			ELSE
-				DDR_SM = DS_LS;	
-			END IF;
-	END CASE;
-------------------------------------------------------------------------------	
--- FIFO ---------------------------------
-	FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
-	FIFO_REQ.CLK = DDR_SYNC_66M;
-	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
-	FIFO_BA1 	   = VIDEO_ADR_CNT11;
-	FIFO_BA0 	   = VIDEO_ADR_CNT10;
-	FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
-	-- ZÄHLER RÜCKSETZEN WENN VSYNC ----------------
-	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
-	CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
-	STOP.CLK = DDRCLK0;
-	STOP = VSYNC # CLEAR_FIFO_CNT;
-	VIDEO_ADR_CNT[].CLK = DDRCLK0;
-	VIDEO_ADR_CNT[] =   CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]			-- SET 
-					 # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1);		-- NEXT 16 BYTS
-	VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
-	FIFO_WRE.CLK = DDRCLK0;
----------------------------------------------------------------
--- BLITTER BUS IST 128 BIT BREIT ------
-	BLITTER_SIG = GND & !CPU_SIG;
-	BLITTER_REQ.CLK = DDR_SYNC_66M;
-	BLITTER_RUN.CLK = DDRCLK0;
-	BLITTER_RUN = GND;
-	BLITTER_WR.CLK = DDRCLK0;
-	BLITTER_WR = GND;
-	DDRWR_D_SEL1 = BLITTER_WR;
-	BLITTER_ROW_ADR[] = H"0";
-	BLITTER_BA1 = GND;
-	BLITTER_BA0 = GND;
-	BLITTER_COL_ADR[] = H"0";
-	BLITTER_DOUT[] = H"0";
-	BLITTER_LE[] = H"0";
------------------------------------------------------------	
--- VIDEO REGISTER -----------------------
----------------------------------------------------------------------------------------------------------------------
-	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; 								-- 820D/2
-	VIDEO_BASE_L_D[] = FB_AD[23..20];												-- SORRY, NUR 16 BYT GRENZEN
-	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
-
-	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; 								-- 8203/2
-	VIDEO_BASE_M_D[] = FB_AD[23..16];
-	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
-
-	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100";			 					-- 8200-1/2
-	VIDEO_BASE_H_D[] = FB_AD[23..16];
-	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
-	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_X_D[] = FB_AD[31..24];
-	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
-
-	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; 								-- 8209/2
-	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; 								-- 8207/2
-	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; 								-- 8205/2
-					  
-	FB_AD[31..24] = lpm_bustri_BYT(
-						VIDEO_BASE_H     & VIDEO_BASE_X_D[] 
-					  # VIDEO_CNT_H		 & VIDEO_ADR_CNT[27..20]
-					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
-
-	FB_AD[23..16] = lpm_bustri_BYT(
-						VIDEO_BASE_L  & (VIDEO_BASE_L_D[],B"0000")
-					  # VIDEO_BASE_M  &  VIDEO_BASE_M_D[]
-					  # VIDEO_BASE_H  &  VIDEO_BASE_H_D[]
-					  # VIDEO_CNT_L	  & (VIDEO_ADR_CNT[3..0],B"0000")
-					  # VIDEO_CNT_M	  &  VIDEO_ADR_CNT[11..4]
-					  # VIDEO_CNT_H	  &  VIDEO_ADR_CNT[19..12]
-					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
-						
-	VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
-	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
-	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
-	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[];
-END;
-
diff --git a/FPGA_by_Fredi/Video/UNUSED b/FPGA_by_Fredi/Video/UNUSED
deleted file mode 100644
index 12f424b..0000000
--- a/FPGA_by_Fredi/Video/UNUSED
+++ /dev/null
@@ -1,267 +0,0 @@
-
--- Clearbox generated Memory Initialization File (.mif)
-
-WIDTH=6;
-DEPTH=256;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	000  :   0F;
-	001  :   0E;
-	002  :   0D;
-	003  :   0C;
-	004  :   0B;
-	005  :   0A;
-	006  :   09;
-	007  :   08;
-	008  :   07;
-	009  :   06;
-	00a  :   05;
-	00b  :   04;
-	00c  :   03;
-	00d  :   02;
-	00e  :   01;
-	00f  :   00;
-	010  :   0F;
-	011  :   0E;
-	012  :   0D;
-	013  :   0C;
-	014  :   0B;
-	015  :   0A;
-	016  :   09;
-	017  :   08;
-	018  :   07;
-	019  :   06;
-	01a  :   05;
-	01b  :   04;
-	01c  :   03;
-	01d  :   02;
-	01e  :   01;
-	01f  :   00;
-	020  :   0F;
-	021  :   0E;
-	022  :   0D;
-	023  :   0C;
-	024  :   0B;
-	025  :   0A;
-	026  :   09;
-	027  :   08;
-	028  :   07;
-	029  :   06;
-	02a  :   05;
-	02b  :   04;
-	02c  :   03;
-	02d  :   02;
-	02e  :   01;
-	02f  :   00;
-	030  :   0F;
-	031  :   0E;
-	032  :   0D;
-	033  :   0C;
-	034  :   0B;
-	035  :   0A;
-	036  :   09;
-	037  :   08;
-	038  :   07;
-	039  :   06;
-	03a  :   05;
-	03b  :   04;
-	03c  :   03;
-	03d  :   02;
-	03e  :   01;
-	03f  :   00;
-	040  :   0F;
-	041  :   0E;
-	042  :   0D;
-	043  :   0C;
-	044  :   0B;
-	045  :   0A;
-	046  :   09;
-	047  :   08;
-	048  :   07;
-	049  :   06;
-	04a  :   05;
-	04b  :   04;
-	04c  :   03;
-	04d  :   02;
-	04e  :   01;
-	04f  :   00;
-	050  :   0F;
-	051  :   0E;
-	052  :   0D;
-	053  :   0C;
-	054  :   0B;
-	055  :   0A;
-	056  :   09;
-	057  :   08;
-	058  :   07;
-	059  :   06;
-	05a  :   05;
-	05b  :   04;
-	05c  :   03;
-	05d  :   02;
-	05e  :   01;
-	05f  :   00;
-	060  :   0F;
-	061  :   0E;
-	062  :   0D;
-	063  :   0C;
-	064  :   0B;
-	065  :   0A;
-	066  :   09;
-	067  :   08;
-	068  :   07;
-	069  :   06;
-	06a  :   05;
-	06b  :   04;
-	06c  :   03;
-	06d  :   02;
-	06e  :   01;
-	06f  :   00;
-	070  :   0F;
-	071  :   0E;
-	072  :   0D;
-	073  :   0C;
-	074  :   0B;
-	075  :   0A;
-	076  :   09;
-	077  :   08;
-	078  :   07;
-	079  :   06;
-	07a  :   05;
-	07b  :   04;
-	07c  :   03;
-	07d  :   02;
-	07e  :   01;
-	07f  :   00;
-	080  :   0F;
-	081  :   0E;
-	082  :   0D;
-	083  :   0C;
-	084  :   0B;
-	085  :   0A;
-	086  :   09;
-	087  :   08;
-	088  :   07;
-	089  :   06;
-	08a  :   05;
-	08b  :   04;
-	08c  :   03;
-	08d  :   02;
-	08e  :   01;
-	08f  :   00;
-	090  :   0F;
-	091  :   0E;
-	092  :   0D;
-	093  :   0C;
-	094  :   0B;
-	095  :   0A;
-	096  :   09;
-	097  :   08;
-	098  :   07;
-	099  :   06;
-	09a  :   05;
-	09b  :   04;
-	09c  :   03;
-	09d  :   02;
-	09e  :   01;
-	09f  :   00;
-	0a0  :   0F;
-	0a1  :   0E;
-	0a2  :   0D;
-	0a3  :   0C;
-	0a4  :   0B;
-	0a5  :   0A;
-	0a6  :   09;
-	0a7  :   08;
-	0a8  :   07;
-	0a9  :   06;
-	0aa  :   05;
-	0ab  :   04;
-	0ac  :   03;
-	0ad  :   02;
-	0ae  :   01;
-	0af  :   00;
-	0b0  :   0F;
-	0b1  :   0E;
-	0b2  :   0D;
-	0b3  :   0C;
-	0b4  :   0B;
-	0b5  :   0A;
-	0b6  :   09;
-	0b7  :   08;
-	0b8  :   07;
-	0b9  :   06;
-	0ba  :   05;
-	0bb  :   04;
-	0bc  :   03;
-	0bd  :   02;
-	0be  :   01;
-	0bf  :   00;
-	0c0  :   0F;
-	0c1  :   0E;
-	0c2  :   0D;
-	0c3  :   0C;
-	0c4  :   0B;
-	0c5  :   0A;
-	0c6  :   09;
-	0c7  :   08;
-	0c8  :   07;
-	0c9  :   06;
-	0ca  :   05;
-	0cb  :   04;
-	0cc  :   03;
-	0cd  :   02;
-	0ce  :   01;
-	0cf  :   00;
-	0d0  :   0F;
-	0d1  :   0E;
-	0d2  :   0D;
-	0d3  :   0C;
-	0d4  :   0B;
-	0d5  :   0A;
-	0d6  :   09;
-	0d7  :   08;
-	0d8  :   07;
-	0d9  :   06;
-	0da  :   05;
-	0db  :   04;
-	0dc  :   03;
-	0dd  :   02;
-	0de  :   01;
-	0df  :   00;
-	0e0  :   0F;
-	0e1  :   0E;
-	0e2  :   0D;
-	0e3  :   0C;
-	0e4  :   0B;
-	0e5  :   0A;
-	0e6  :   09;
-	0e7  :   08;
-	0e8  :   07;
-	0e9  :   06;
-	0ea  :   05;
-	0eb  :   04;
-	0ec  :   03;
-	0ed  :   02;
-	0ee  :   01;
-	0ef  :   00;
-	0f0  :   0F;
-	0f1  :   0E;
-	0f2  :   0D;
-	0f3  :   0C;
-	0f4  :   0B;
-	0f5  :   0A;
-	0f6  :   09;
-	0f7  :   08;
-	0f8  :   07;
-	0f9  :   06;
-	0fa  :   05;
-	0fb  :   04;
-	0fc  :   03;
-	0fd  :   02;
-	0fe  :   01;
-	0ff  :   00;
-END;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
index 6a77969..fc80715 100644
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -338,7 +338,7 @@ BEGIN
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
-	BLITTER_ON = !SYS_CTR3;
+	BLITTER_ON = SYS_CTR3;
 --VDL_LOF
 	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
@@ -440,7 +440,7 @@ BEGIN
 	FB_AD[31..16] = lpm_bustri_WORD(
 						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
 					  # VDL_LOF_CS & VDL_LOF[]
 					  # VDL_LWD_CS & VDL_LWD[]
 					  #	VDL_HBE_CS & (0,VDL_HBE[])
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
deleted file mode 100644
index 2c9adcc..0000000
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
+++ /dev/null
@@ -1,675 +0,0 @@
-TITLE "VIDEO MODUSE UND CLUT CONTROL";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "lpm_bustri_BYT.inc";
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nFB_BURST : INPUT;
-	FB_ADR[31..0] : INPUT;
-	CLK33M : INPUT;
-	CLK25M : INPUT;
-	BLITTER_RUN : INPUT;
-	CLK_VIDEO : INPUT;
-	VR_D[8..0] : INPUT;
-	VR_BUSY : INPUT;
-	COLOR8 : OUTPUT;
-	ACP_CLUT_RD : OUTPUT;
-	COLOR1 : OUTPUT;
-	FALCON_CLUT_RDH : OUTPUT;
-	FALCON_CLUT_RDL : OUTPUT;
-	FALCON_CLUT_WR[3..0] : OUTPUT;
-	ST_CLUT_RD : OUTPUT;
-	ST_CLUT_WR[1..0] : OUTPUT;
-	CLUT_MUX_ADR[3..0] : OUTPUT;
-	HSYNC : OUTPUT;
-	VSYNC : OUTPUT;
-	nBLANK : OUTPUT;
-	nSYNC : OUTPUT;
-	nPD_VGA : OUTPUT;
-	FIFO_RDE : OUTPUT;
-	COLOR2 : OUTPUT;
-	COLOR4 : OUTPUT;
-	PIXEL_CLK : OUTPUT;
-	CLUT_OFF[3..0] : OUTPUT;
-	BLITTER_ON : OUTPUT;
-	VIDEO_RAM_CTR[15..0] : OUTPUT;
-	VIDEO_MOD_TA : OUTPUT;
-	CCR[23..0] : OUTPUT;
-	CCSEL[2..0] : OUTPUT;
-	ACP_CLUT_WR[3..0] : OUTPUT;
-	INTER_ZEI : OUTPUT;
-	DOP_FIFO_CLR : OUTPUT;
-	VIDEO_RECONFIG : OUTPUT;
-	VR_WR : OUTPUT;
-	VR_RD : OUTPUT;
-	CLR_FIFO : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	CLK17M						:DFF;
-	CLK13M						:DFF;
-	ACP_CLUT_CS					:NODE;
-	ACP_CLUT					:NODE;
-	VIDEO_PLL_CONFIG_CS			:NODE;
-	VR_WR						:DFF;
-	VR_DOUT[8..0]				:DFFE;
-	VR_FRQ[7..0]				:DFFE;
-	VIDEO_PLL_RECONFIG_CS		:NODE;
-	VIDEO_RECONFIG				:DFF;
-	FALCON_CLUT_CS				:NODE;
-	FALCON_CLUT					:NODE;
-	ST_CLUT_CS					:NODE;
-	ST_CLUT						:NODE;
-	FB_B[3..0]					:NODE;
-	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[1..0]			:DFFE;
-	ST_SHIFT_MODE_CS			:NODE;
-	FALCON_SHIFT_MODE[10..0]	:DFFE;
-	FALCON_SHIFT_MODE_CS		:NODE;
-	CLUT_MUX_ADR[3..0]			:DFF;
-	CLUT_MUX_AV[1..0][3..0]		:DFF;
-	ACP_VCTR_CS					:NODE;
-	ACP_VCTR[31..0]				:DFFE;
-	CCR_CS						:NODE;
-	CCR[23..0]					:DFFE;
-	ACP_VIDEO_ON				:NODE;
-	SYS_CTR[6..0]				:DFFE;
-	SYS_CTR_CS					:NODE;
-	VDL_LOF[15..0]				:DFFE;
-	VDL_LOF_CS					:NODE;
-	VDL_LWD[15..0]				:DFFE;
-	VDL_LWD_CS					:NODE;
--- DIV. CONTROL REGISTER
-	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
-	HSYNC						:DFF;
-	HSYNC_I[7..0]				:DFF;
-	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
-	HSYNC_START					:DFF;
-	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
-	VSYNC						:DFF;
-	VSYNC_START					:DFFE;
-	VSYNC_I[2..0]				:DFFE;
-	nBLANK						:DFF;
-	DISP_ON						:DFF;
-	DPO_ZL						:DFFE;
-	DPO_ON						:DFF;
-	DPO_OFF						:DFF;
-	VDTRON						:DFF;
-	VDO_ZL						:DFFE;
-	VDO_ON						:DFF;
-	VDO_OFF						:DFF;
-	VHCNT[11..0]				:DFF;
-	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[10..0]				:DFFE;
-	VERZ[2..0][9..0]			:DFF;
-	RAND[6..0]					:DFF;
-	RAND_ON						:NODE;
-	FIFO_RDE					:DFF;
-	CLR_FIFO					:DFFE;
-	START_ZEILE					:DFFE;
-	SYNC_PIX					:DFF;
-	SYNC_PIX1					:DFF;
-	SYNC_PIX2					:DFF;
-	CCSEL[2..0]					:DFF;
-	COLOR16						:NODE;
-	COLOR24						:NODE;
--- ATARI RESOLUTION
-	ATARI_SYNC					:NODE;	 
-	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
-	ATARI_HH_CS					:NODE;
-	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
-	ATARI_VH_CS					:NODE;
-	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
-	ATARI_HL_CS					:NODE;
-	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
-	ATARI_VL_CS					:NODE;
--- HORIZONTAL
-	RAND_LINKS[11..0]			:NODE;
-	HDIS_START[11..0]			:NODE;
-	HDIS_END[11..0]				:NODE;  
-	RAND_RECHTS[11..0]			:NODE;
-	HS_START[11..0]				:NODE;
-	H_TOTAL[11..0]				:NODE;
-	HDIS_LEN[11..0]				:NODE;
-	MULF[5..0]					:NODE;
-	VDL_HHT[11..0]				:DFFE;
-	VDL_HHT_CS					:NODE;
-	VDL_HBE[11..0]				:DFFE;
-	VDL_HBE_CS					:NODE;
-	VDL_HDB[11..0]				:DFFE;
-	VDL_HDB_CS					:NODE;
-	VDL_HDE[11..0]				:DFFE;
-	VDL_HDE_CS					:NODE;
-	VDL_HBB[11..0]				:DFFE;
-	VDL_HBB_CS					:NODE;
-	VDL_HSS[11..0]				:DFFE;
-	VDL_HSS_CS					:NODE;
--- VERTIKAL
-	RAND_OBEN[10..0]			:NODE; 
-	VDIS_START[10..0]			:NODE; 
-	VDIS_END[10..0]				:NODE; 
-	RAND_UNTEN[10..0]			:NODE; 
-	VS_START[10..0]				:NODE; 
-	V_TOTAL[10..0]				:NODE;  
-	FALCON_VIDEO				:NODE;
-	ST_VIDEO					:NODE;
-	INTER_ZEI					:DFF;
-	DOP_ZEI						:DFF;
-	DOP_FIFO_CLR				:DFF;
-	
-	VDL_VBE[10..0]				:DFFE;
-	VDL_VBE_CS					:NODE;
-	VDL_VDB[10..0]				:DFFE;
-	VDL_VDB_CS					:NODE;
-	VDL_VDE[10..0]				:DFFE;
-	VDL_VDE_CS					:NODE;
-	VDL_VBB[10..0]				:DFFE;
-	VDL_VBB_CS					:NODE;
-	VDL_VSS[10..0]				:DFFE;
-	VDL_VSS_CS					:NODE;
-	VDL_VFT[10..0]				:DFFE;
-	VDL_VFT_CS					:NODE;
-	VDL_VCT[8..0]				:DFFE;
-	VDL_VCT_CS					:NODE;
-	VDL_VMD[3..0]				:DFFE;
-	VDL_VMD_CS					:NODE;
-
-BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- ACP CLUT --
-	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
-	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
-	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
-	CLUT_TA.CLK = MAIN_CLK;
-	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
---FALCON CLUT --
-	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
-	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
-	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
-	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
--- ST CLUT --
-	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
-	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
-	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
--- ST SHIFT MODE
-	ST_SHIFT_MODE[].CLK = MAIN_CLK;
-	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[25..24];
-	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
--- FALCON SHIFT MODE
-	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
-	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
-	FALCON_SHIFT_MODE[] = FB_AD[26..16];
-	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
-	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
-	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
-	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
-	ACP_VCTR[31..8] = FB_AD[31..8];
-	ACP_VCTR[5..0] = FB_AD[5..0];
-	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
-	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
-	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
-	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
-	ACP_VIDEO_ON = ACP_VCTR0;
-	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
-	-- HORIZONTAL TIMING 640x480
-	ATARI_HH[].CLK = MAIN_CLK;
-	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
-	ATARI_HH[] = FB_AD[];
-	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
-	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
-	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
-	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
-	ATARI_VH[].CLK = MAIN_CLK;
-	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
-	ATARI_VH[] = FB_AD[];
-	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
-	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
-	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
-	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
-	ATARI_HL[].CLK = MAIN_CLK;
-	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
-	ATARI_HL[] = FB_AD[];
-	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
-	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
-	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
-	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
-	ATARI_VL[].CLK = MAIN_CLK;
-	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
-	ATARI_VL[] = FB_AD[];
-	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
-	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
-	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
-	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
--- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
-	VR_WR.CLK = MAIN_CLK;
-	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
-	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
-	VR_DOUT[].CLK = MAIN_CLK;
-	VR_DOUT[].ENA = !VR_BUSY;
-	VR_DOUT[] = VR_D[];
-	VR_FRQ[].CLK = MAIN_CLK;
-	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
-	VR_FRQ[] = FB_AD[23..16];
--- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
-	VIDEO_RECONFIG.CLK = MAIN_CLK;
-	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
-------------------------------------------------------------------------------------------------------------------------
-	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
--------------- COLOR MODE IM ACP SETZEN	
-	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
-	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
--- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
-	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
-	FALCON_VIDEO	   = ACP_VCTR7;
-	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_VIDEO		   = ACP_VCTR6;
-	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
-	CCSEL[].CLK = PIXEL_CLK;
-	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
-			# B"001" & FALCON_CLUT
-			# B"100" & ACP_CLUT
-			# B"101" & COLOR16
-			# B"110" & COLOR24
-			# B"111" & RAND_ON;
--- DIVERSE (VIDEO)-REGISTER ----------------------------
--- RANDFARBE
-	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
-	CCR[] = FB_AD[23..0];
-	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
-	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
-	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
---SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
-	SYS_CTR[].CLK = MAIN_CLK;
-	SYS_CTR[6..0] = FB_AD[22..16];
-	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
-	BLITTER_ON = !SYS_CTR3;
---VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
-	VDL_LOF[].CLK = MAIN_CLK;
-	VDL_LOF[] = FB_AD[31..16];
-	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
-	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
---VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
-	VDL_LWD[].CLK = MAIN_CLK;
-	VDL_LWD[] = FB_AD[31..16];
-	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
-	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
--- HORIZONTAL
--- VDL_HHT
-	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
-	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[27..16];
-	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
-	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
--- VDL_HBE
-	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
-	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[27..16];
-	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
-	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
--- VDL_HDB
-	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
-	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[27..16];
-	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
-	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
--- VDL_HDE
-	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
-	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[27..16];
-	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
-	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
--- VDL_HBB
-	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
-	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[27..16];
-	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
-	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
--- VDL_HSS
-	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
-	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[27..16];
-	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
-	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
--- VERTIKAL
--- VDL_VBE
-	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
-	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[26..16];
-	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
-	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
--- VDL_VDB
-	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
-	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[26..16];
-	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
-	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
--- VDL_VDE
-	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
-	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[26..16];
-	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
-	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
--- VDL_VBB
-	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
-	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[26..16];
-	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
-	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
--- VDL_VSS
-	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
-	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[26..16];
-	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
-	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
--- VDL_VFT
-	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
-	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[26..16];
-	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
-	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
--- VDL_VCT
-	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
-	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[24..16];
-	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
-	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
--- VDL_VMD
-	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
-	VDL_VMD[].CLK = MAIN_CLK;
-	VDL_VMD[] = FB_AD[19..16];
-	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
-					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS & VDL_LOF[]
-					  # VDL_LWD_CS & VDL_LWD[]
-					  #	VDL_HBE_CS & (0,VDL_HBE[])
-					  #	VDL_HDB_CS & (0,VDL_HDB[])
-					  #	VDL_HDE_CS & (0,VDL_HDE[])
-					  #	VDL_HBB_CS & (0,VDL_HBB[])
-					  #	VDL_HSS_CS & (0,VDL_HSS[])
-					  #	VDL_HHT_CS & (0,VDL_HHT[])
-					  #	VDL_VBE_CS & (0,VDL_VBE[])
-					  #	VDL_VDB_CS & (0,VDL_VDB[])
-					  #	VDL_VDE_CS & (0,VDL_VDE[])
-					  #	VDL_VBB_CS & (0,VDL_VBB[])
-					  #	VDL_VSS_CS & (0,VDL_VSS[])
-					  #	VDL_VFT_CS & (0,VDL_VFT[])
-					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS & (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
- 					  #	ATARI_HH_CS & ATARI_HH[31..16]
-					  #	ATARI_VH_CS & ATARI_VH[31..16]
-					  #	ATARI_HL_CS & ATARI_HL[31..16]
-					  #	ATARI_VL_CS & ATARI_VL[31..16]
-					  #	CCR_CS & (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
-					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
-					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
-					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
-
- 	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
-					  #	ATARI_HH_CS & ATARI_HH[15..0]
-					  #	ATARI_VH_CS & ATARI_VH[15..0]
-					  #	ATARI_HL_CS & ATARI_HL[15..0]
-					  #	ATARI_VL_CS & ATARI_VL[15..0]
- 					  #	CCR_CS & CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
-
-	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
-			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
-				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
-				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-	
--- VIDEO AUSGABE SETZEN
-	CLK17M.CLK = CLK33M;
-	CLK17M = !CLK17M;
-	CLK13M.CLK = CLK25M;
-	CLK13M = !CLK13M;
-	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
-			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
-----------------------------------------------------------------
-	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
-			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
-
- 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
-			# 4  & !ST_VIDEO & !VDL_VMD2
-			# 16 &  ST_VIDEO &  VDL_VMD2
-			# 32 &  ST_VIDEO & !VDL_VMD2;
-	 	
-	 	
-	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
-			   #  640 & !VDL_VMD2;
-					
--- DOPPELZEILENMODUS
-	DOP_ZEI.CLK = MAIN_CLK;
-	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
-	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
-					
-	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
-					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
-	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
-					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
-	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-					
-	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
-					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
-					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
-					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
-					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
-					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
-					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
-	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
-	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- ZÄHLER
-	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[]-2);
-	VHCNT[].CLK = PIXEL_CLK;
-	VHCNT[] = (VHCNT[] + 1) & !LAST;
-	VVCNT[].CLK = PIXEL_CLK;
-	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
--- DISPLAY ON OFF
-	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
-	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
-	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
-	DISP_ON.CLK = PIXEL_CLK;
-	DISP_ON = DISP_ON & !DPO_OFF 
-			# DPO_ON & DPO_ZL;
--- DATENTRANSFER ON OFF
-	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
-	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==HDIS_END[];
-	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
-	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
-	VDTRON.CLK = PIXEL_CLK;
-	VDTRON = VDTRON & !VDO_OFF
-		   # VDO_ON & VDO_ZL;
--- VERZÖGERUNG UND SYNC	
-	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[]-3;
-	HSYNC_I[].CLK = PIXEL_CLK;
-	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
-			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
-	VSYNC_START.ENA = LAST;
-	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
-	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
-	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
-	VERZ[][].CLK = PIXEL_CLK;
-	VERZ[][1] = VERZ[][0];
-	VERZ[][2] = VERZ[][1];
-	VERZ[][3] = VERZ[][2];
-	VERZ[][4] = VERZ[][3];
-	VERZ[][5] = VERZ[][4];
-	VERZ[][6] = VERZ[][5];
-	VERZ[][7] = VERZ[][6];
-	VERZ[][8] = VERZ[][7];
-	VERZ[][9] = VERZ[][8];
-	VERZ[0][0] = DISP_ON;
-	VERZ[1][0] = HSYNC_I[]!=0;
-	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
-	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
-	nBLANK.CLK = PIXEL_CLK;
-	nBLANK =  VERZ[0][8];
-	HSYNC.CLK = PIXEL_CLK;
-	HSYNC  =  VERZ[1][9];
-	VSYNC.CLK = PIXEL_CLK;
-	VSYNC  =  VERZ[2][9];
-	nSYNC  = GND;
--- RANDFARBE MACHEN ------------------------------------
-	RAND[].CLK = PIXEL_CLK;
-	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
-	RAND[1] = RAND[0];
-	RAND[2] = RAND[1];
-	RAND[3] = RAND[2];
-	RAND[4] = RAND[3];
-	RAND[5] = RAND[4];
-	RAND[6] = RAND[5];
-	RAND_ON = RAND[6];
-----------------------------------------------------------
-	CLR_FIFO.CLK = PIXEL_CLK;
-	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
-	START_ZEILE.CLK = PIXEL_CLK;
-	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
-	SYNC_PIX.CLK = PIXEL_CLK;
-	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SYNC_PIX1.CLK = PIXEL_CLK;
-	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SYNC_PIX2.CLK = PIXEL_CLK;
-	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
-	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
-	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
-	FIFO_RDE.CLK = PIXEL_CLK;	
-	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
-			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
-			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
-			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
-			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
-			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
-			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
-	
-	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
-	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
-	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
-	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
-	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
-END;
diff --git a/FPGA_by_Fredi/Video/Video.bdf b/FPGA_by_Fredi/Video/Video.bdf
index 669eb72..0df55be 100644
--- a/FPGA_by_Fredi/Video/Video.bdf
+++ b/FPGA_by_Fredi/Video/Video.bdf
@@ -25,8 +25,8 @@ applicable agreement for further details.
 (pin
 	(input)
 	(rect 184 1192 352 1208)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_ADR[31..0]" (rect 9 0 103 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_ADR[31..0]" (rect 9 0 84 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -37,13 +37,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1248 352 1264)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "MAIN_CLK" (rect 9 0 78 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "MAIN_CLK" (rect 9 0 63 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -54,13 +54,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1352 352 1368)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS1" (rect 9 0 71 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -71,13 +71,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1384 352 1400)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS2" (rect 9 0 71 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS2" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -88,13 +88,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1416 352 1432)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_CS3" (rect 9 0 71 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_CS3" (rect 9 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -105,13 +105,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1448 352 1464)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_WR" (rect 9 0 66 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_WR" (rect 9 0 53 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -122,13 +122,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1480 352 1496)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_SIZE0" (rect 9 0 73 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE0" (rect 9 0 59 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -139,13 +139,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1512 352 1528)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_SIZE1" (rect 9 0 73 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_SIZE1" (rect 9 0 59 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -156,13 +156,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1544 352 1560)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nRSTO" (rect 9 0 56 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nRSTO" (rect 9 0 44 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -173,13 +173,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1608 352 1624)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "nFB_OE" (rect 9 0 63 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "nFB_OE" (rect 9 0 50 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -190,13 +190,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1736 352 1752)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "FB_ALE" (rect 9 0 60 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "FB_ALE" (rect 9 0 49 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -207,13 +207,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 184 1312 352 1328)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "DDRCLK[3..0]" (rect 9 0 99 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "DDRCLK[3..0]" (rect 9 0 80 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -224,13 +224,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 176 1280 344 1296)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "DDR_SYNC_66M" (rect 9 0 123 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "DDR_SYNC_66M" (rect 9 0 97 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -241,13 +241,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 1344 2176 1512 2192)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "CLK33M" (rect 9 0 64 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CLK33M" (rect 9 0 50 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -258,13 +258,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 1344 2200 1512 2216)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "CLK25M" (rect 9 0 64 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CLK25M" (rect 9 0 50 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -275,13 +275,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 1344 2152 1512 2168)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "CLK_VIDEO" (rect 5 0 84 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CLK_VIDEO" (rect 5 0 66 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -292,13 +292,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 1344 2128 1512 2144)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "VR_D[8..0]" (rect 5 0 73 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "VR_D[8..0]" (rect 5 0 60 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -309,13 +309,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(input)
 	(rect 1344 2112 1512 2128)
-	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
-	(text "VR_BUSY" (rect 5 0 69 15)(font "Arial" ))
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "VR_BUSY" (rect 5 0 56 12)(font "Arial" ))
 	(pt 168 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -326,13 +326,13 @@ applicable agreement for further details.
 		(line (pt 117 4)(pt 121 8)(line_width 1))
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
-	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(output)
 	(rect 472 1200 648 1216)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VG[7..0]" (rect 90 0 139 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VG[7..0]" (rect 90 0 131 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -348,8 +348,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1232 648 1248)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VB[7..0]" (rect 90 0 138 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VB[7..0]" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -365,8 +365,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1264 648 1280)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VR[7..0]" (rect 90 0 139 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VR[7..0]" (rect 90 0 131 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -382,8 +382,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1408 648 1424)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nBLANK" (rect 90 0 144 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nBLANK" (rect 90 0 131 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -399,8 +399,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1480 648 1496)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VA[12..0]" (rect 90 0 145 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VA[12..0]" (rect 90 0 136 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -416,8 +416,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1512 648 1528)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nVWE" (rect 90 0 128 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nVWE" (rect 90 0 120 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -433,8 +433,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1544 648 1560)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nVCAS" (rect 90 0 134 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nVCAS" (rect 90 0 125 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -450,8 +450,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1576 648 1592)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nVRAS" (rect 90 0 134 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nVRAS" (rect 90 0 125 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -467,8 +467,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1608 648 1624)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nVCS" (rect 90 0 126 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nVCS" (rect 90 0 118 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -484,8 +484,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1704 648 1720)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VDM[3..0]" (rect 90 0 150 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VDM[3..0]" (rect 90 0 139 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -501,8 +501,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1736 648 1752)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nPD_VGA" (rect 90 0 153 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nPD_VGA" (rect 90 0 139 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -518,8 +518,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1768 648 1784)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VCKE" (rect 90 0 127 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VCKE" (rect 90 0 119 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -535,8 +535,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1288 648 1304)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VSYNC" (rect 90 0 137 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VSYNC" (rect 90 0 128 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -552,8 +552,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1336 648 1352)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "HSYNC" (rect 90 0 139 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HSYNC" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -569,8 +569,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1384 648 1400)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "nSYNC" (rect 90 0 137 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nSYNC" (rect 90 0 127 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -586,8 +586,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1800 648 1816)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VIDEO_TA" (rect 90 0 157 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VIDEO_TA" (rect 90 0 143 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -603,8 +603,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1448 648 1464)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "PIXEL_CLK" (rect 90 0 165 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "PIXEL_CLK" (rect 90 0 146 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -620,8 +620,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 472 1656 648 1672)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "BA[1..0]" (rect 90 0 138 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "BA[1..0]" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -637,8 +637,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 2144 1696 2364 1712)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VIDEO_RECONFIG" (rect 90 0 215 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VIDEO_RECONFIG" (rect 90 0 189 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -654,8 +654,8 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 2112 1792 2288 1808)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VR_WR" (rect 90 0 140 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VR_WR" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -671,8 +671,25 @@ applicable agreement for further details.
 (pin
 	(output)
 	(rect 2112 1808 2288 1824)
-	(text "OUTPUT" (rect 1 0 51 13)(font "Arial" (font_size 6)))
-	(text "VR_RD" (rect 90 0 138 15)(font "Arial" ))
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "VR_RD" (rect 90 0 127 12)(font "Arial" ))
+	(pt 0 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+)
+(pin
+	(output)
+	(rect 672 3000 848 3016)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "BLITTER_INT" (rect 90 0 157 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -688,8 +705,8 @@ applicable agreement for further details.
 (pin
 	(bidir)
 	(rect 184 1640 360 1656)
-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "VDQS[3..0]" (rect 90 0 159 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "VDQS[3..0]" (rect 90 0 146 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -701,13 +718,13 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(bidir)
 	(rect 184 1672 360 1688)
-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "FB_AD[31..0]" (rect 90 0 173 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "FB_AD[31..0]" (rect 90 0 157 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -719,13 +736,13 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
 )
 (pin
 	(bidir)
 	(rect 184 1704 360 1720)
-	(text "BIDIR" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "VD[31..0]" (rect 90 0 147 15)(font "Arial" ))
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "VD[31..0]" (rect 90 0 137 12)(font "Arial" ))
 	(pt 0 8)
 	(connected_pin (pt 0 0))
 	(drawing
@@ -737,42 +754,42 @@ applicable agreement for further details.
 		(line (pt 56 4)(pt 52 8)(line_width 1))
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
-	(text "VCC" (rect 4 7 28 20)(font "Arial" (font_size 6)))
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
 )
 (symbol
 	(rect 920 1616 1064 1712)
-	(text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst13" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst13" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 50 140 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 131 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -783,38 +800,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 920 1760 1064 1856)
-	(text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst14" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst14" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 50 140 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 131 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -825,38 +842,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 920 1896 1064 1992)
-	(text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst15" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst15" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 50 140 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 131 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -867,38 +884,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 920 2032 1064 2128)
-	(text "lpm_ff0" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst16" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst16" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 50 140 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 131 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -909,62 +926,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 2040 2496 2184)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst40" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst40" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -976,62 +993,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 1880 2496 2024)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst41" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst41" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -1043,62 +1060,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 1720 2496 1864)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst42" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst42" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -1110,62 +1127,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 1560 2496 1704)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst43" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst43" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -1177,62 +1194,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 1400 2496 1544)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst44" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst44" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -1244,62 +1261,62 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2392 1240 2496 1384)
-	(text "MUX41" (rect 29 -1 88 19)(font "Courier New" (font_size 10)(bold)))
-	(text "inst45" (rect 3 133 36 146)(font "Arial" (font_size 6)))
+	(text "MUX41" (rect 29 -1 76 15)(font "Courier New" (font_size 10)(bold)))
+	(text "inst45" (rect 3 133 26 143)(font "Arial" (font_size 6)))
 	(port
 		(pt 0 120)
 		(input)
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
-		(text "S0" (rect 20 116 36 132)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
+		(text "S0" (rect 20 116 31 128)(font "Courier New" (bold)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
-		(text "D2" (rect 20 68 36 84)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
+		(text "D2" (rect 20 68 31 80)(font "Courier New" (bold)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
-		(text "S1" (rect 20 100 36 116)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
+		(text "S1" (rect 20 100 31 112)(font "Courier New" (bold)))
 		(line (pt 0 104)(pt 16 104)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
-		(text "D3" (rect 20 84 36 100)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
+		(text "D3" (rect 20 84 31 96)(font "Courier New" (bold)))
 		(line (pt 0 88)(pt 16 88)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
-		(text "D0" (rect 20 36 36 52)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
+		(text "D0" (rect 20 36 31 48)(font "Courier New" (bold)))
 		(line (pt 0 40)(pt 16 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
-		(text "INH" (rect 20 20 44 36)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
+		(text "INH" (rect 20 20 37 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 16 24)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
-		(text "D1" (rect 20 52 36 68)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
+		(text "D1" (rect 20 52 31 64)(font "Courier New" (bold)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 104 72)
 		(output)
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
-		(text "Q" (rect 81 68 89 84)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
+		(text "Q" (rect 81 68 86 80)(font "Courier New" (bold)))
 		(line (pt 88 72)(pt 104 72)(line_width 1))
 	)
 	(drawing
@@ -1311,45 +1328,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 1216 2776 1344)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr0" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr0" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1360,45 +1377,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 1376 2776 1504)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr1" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr1" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1409,45 +1426,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 1536 2776 1664)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr2" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr2" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1458,45 +1475,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 1696 2776 1824)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr3" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr3" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1507,45 +1524,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 1856 2776 1984)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr4" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr4" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1556,45 +1573,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 2016 2776 2144)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr5" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr5" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1605,45 +1622,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 2176 2776 2304)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr6" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr6" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1654,45 +1671,45 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2632 2336 2776 2464)
-	(text "lpm_shiftreg0" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "sr7" (rect 8 112 29 127)(font "Arial" ))
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "sr7" (rect 8 112 23 124)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "load" (rect 0 0 28 16)(font "Arial" (font_size 8)))
-		(text "load" (rect 20 26 48 42)(font "Arial" (font_size 8)))
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 43 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 42 93 58)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 80 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
 		(pt 0 80)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 74 62 90)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 55 88)(font "Arial" (font_size 8)))
 		(line (pt 0 80)(pt 16 80)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 90 60 106)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 54 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 144 72)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 66 138 82)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 131 80)(font "Arial" (font_size 8)))
 		(line (pt 144 72)(pt 128 72)(line_width 1))
 	)
 	(drawing
-		(text "left shift" (rect 92 17 141 32)(font "Arial" ))
+		(text "left shift" (rect 92 17 134 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 112)(line_width 1))
 		(line (pt 128 112)(pt 16 112)(line_width 1))
@@ -1703,13 +1720,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 888 3328 920)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst50" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst50" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -1721,32 +1738,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 784 3920 824)
-	(text "lpm_bustri1" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst51" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst51" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[2..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[2..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[2..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[2..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[2..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[2..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "3" (rect 63 25 71 40)(font "Arial" ))
-		(text "3" (rect 15 25 23 40)(font "Arial" ))
+		(text "3" (rect 63 25 68 37)(font "Arial" ))
+		(text "3" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -1756,18 +1773,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3712 880 3808 928)
-	(text "lpm_constant0" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst54" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst54" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[4..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[4..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "5" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -1777,13 +1794,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 1096 3328 1128)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst55" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst55" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -1795,32 +1812,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 992 3920 1032)
-	(text "lpm_bustri1" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst56" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst56" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[2..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[2..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[2..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[2..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[2..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[2..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "3" (rect 63 25 71 40)(font "Arial" ))
-		(text "3" (rect 15 25 23 40)(font "Arial" ))
+		(text "3" (rect 63 25 68 37)(font "Arial" ))
+		(text "3" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -1830,18 +1847,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3720 1088 3816 1136)
-	(text "lpm_constant0" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst59" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst59" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[4..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[4..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "5" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -1851,13 +1868,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 1528 3328 1560)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst60" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst60" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -1869,32 +1886,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 1200 3920 1240)
-	(text "lpm_bustri1" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst61" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst61" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[2..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[2..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[2..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[2..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[2..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[2..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "3" (rect 63 25 71 40)(font "Arial" ))
-		(text "3" (rect 15 25 23 40)(font "Arial" ))
+		(text "3" (rect 63 25 68 37)(font "Arial" ))
+		(text "3" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -1904,18 +1921,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3712 1296 3808 1344)
-	(text "lpm_constant0" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst64" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst64" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[4..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[4..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "5" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -1925,32 +1942,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 1424 3920 1464)
-	(text "lpm_bustri3" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst66" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst66" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[5..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[5..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[5..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[5..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[5..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[5..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "6" (rect 63 25 71 40)(font "Arial" ))
-		(text "6" (rect 15 25 23 40)(font "Arial" ))
+		(text "6" (rect 63 25 68 37)(font "Arial" ))
+		(text "6" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -1960,13 +1977,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 1736 3328 1768)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst68" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst68" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -1978,32 +1995,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 1632 3920 1672)
-	(text "lpm_bustri3" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst70" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst70" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[5..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[5..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[5..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[5..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[5..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[5..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "6" (rect 63 25 71 40)(font "Arial" ))
-		(text "6" (rect 15 25 23 40)(font "Arial" ))
+		(text "6" (rect 63 25 68 37)(font "Arial" ))
+		(text "6" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -2013,13 +2030,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 1944 3328 1976)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst72" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst72" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2031,32 +2048,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3840 1840 3920 1880)
-	(text "lpm_bustri3" (rect 7 1 104 20)(font "Arial" (font_size 10)))
-	(text "inst74" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst74" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[5..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[5..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[5..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 80 24)
 		(bidir)
-		(text "tridata[5..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[5..0]" (rect 84 -30 161 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[5..0]" (rect 84 -30 147 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 80 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "6" (rect 63 25 71 40)(font "Arial" ))
-		(text "6" (rect 15 25 23 40)(font "Arial" ))
+		(text "6" (rect 63 25 68 37)(font "Arial" ))
+		(text "6" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -2066,13 +2083,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 1304 3328 1336)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst78" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst78" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2084,27 +2101,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3008 1432 3072 1480)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst29" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst29" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2116,27 +2133,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3008 1736 3072 1784)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst30" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst30" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2148,27 +2165,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3024 2080 3088 2128)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst31" (rect 3 37 43 52)(font "Arial" ))
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst31" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2181,27 +2198,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2904 1912 2968 1960)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst32" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst32" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2213,27 +2230,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2904 2072 2968 2120)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst33" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst33" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2245,27 +2262,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2904 2232 2968 2280)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst34" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst34" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
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-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2277,27 +2294,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2904 2392 2968 2440)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst35" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst35" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2309,13 +2326,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 2592 3328 2624)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst73" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst73" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2327,34 +2344,34 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3160 3064 3296 3144)
-	(text "lpm_mux4" (rect 42 62 126 81)(font "Arial" (font_size 10)))
-	(text "inst81" (rect 8 4 48 19)(font "Arial" ))
+	(text "lpm_mux4" (rect 42 62 112 78)(font "Arial" (font_size 10)))
+	(text "inst81" (rect 8 4 37 16)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1x[6..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data1x[6..0]" (rect 4 39 85 55)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 4 39 71 53)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 64 40)(line_width 3))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data0x[6..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data0x[6..0]" (rect 4 23 85 39)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 4 23 71 37)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 64 24)(line_width 3))
 	)
 	(port
 		(pt 72 0)
 		(input)
-		(text "sel" (rect 0 0 20 16)(font "Arial" (font_size 8)))
-		(text "sel" (rect 76 -1 96 15)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 76 -1 92 13)(font "Arial" (font_size 8)))
 		(line (pt 72 0)(pt 72 12)(line_width 1))
 	)
 	(port
 		(pt 136 32)
 		(output)
-		(text "result[6..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[6..0]" (rect 82 31 155 47)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 82 31 142 45)(font "Arial" (font_size 8)))
 		(line (pt 136 32)(pt 80 32)(line_width 3))
 	)
 	(drawing
@@ -2367,18 +2384,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2976 3080 3072 3128)
-	(text "lpm_constant3" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst82" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst82" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[6..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[6..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "7" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "7" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -2388,82 +2405,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 776 3704 984)
-	(text "altdpram0" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ST_CLUT_RED" (rect 8 192 110 207)(font "Arial" ))
+	(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ST_CLUT_RED" (rect 8 192 84 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[2..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[3..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[2..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[3..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[2..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[2..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "16 Word(s)" (rect 136 61 151 132)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "16 Word(s)" (rect 136 61 148 115)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -2540,82 +2557,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 984 3704 1192)
-	(text "altdpram0" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ST_CLUT_GREEN" (rect 8 192 130 207)(font "Arial" ))
+	(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ST_CLUT_GREEN" (rect 8 192 100 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[2..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[3..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[2..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[3..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[2..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[2..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "16 Word(s)" (rect 136 61 151 132)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "16 Word(s)" (rect 136 61 148 115)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -2692,27 +2709,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1360 2992 1408 3024)
-	(text "TRI" (rect 1 0 21 13)(font "Arial" (font_size 6)))
-	(text "inst84" (rect 3 21 43 36)(font "Arial" ))
+	(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
+	(text "inst84" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 24 0)
 		(input)
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
 		(line (pt 24 12)(pt 24 0)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 32 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2723,27 +2740,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1360 2936 1408 2968)
-	(text "TRI" (rect 1 0 21 13)(font "Arial" (font_size 6)))
-	(text "inst85" (rect 3 21 43 36)(font "Arial" ))
+	(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
+	(text "inst85" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 24 0)
 		(input)
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
 		(line (pt 24 12)(pt 24 0)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 32 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2754,27 +2771,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1360 2888 1408 2920)
-	(text "TRI" (rect 1 0 21 13)(font "Arial" (font_size 6)))
-	(text "inst86" (rect 3 21 43 36)(font "Arial" ))
+	(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
+	(text "inst86" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 24 0)
 		(input)
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
 		(line (pt 24 12)(pt 24 0)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 32 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2785,27 +2802,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1360 2840 1408 2872)
-	(text "TRI" (rect 1 0 21 13)(font "Arial" (font_size 6)))
-	(text "inst87" (rect 3 21 43 36)(font "Arial" ))
+	(text "TRI" (rect 1 0 16 10)(font "Arial" (font_size 6)))
+	(text "inst87" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 24 0)
 		(input)
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
-		(text "OE" (rect 26 0 42 16)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
+		(text "OE" (rect 26 0 37 12)(font "Courier New" (bold))(invisible))
 		(line (pt 24 12)(pt 24 0)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 32 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -2816,13 +2833,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 1248 2304 1280)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst6" (rect -1 3 14 34)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst6" (rect -1 3 11 26)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2834,13 +2851,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 1408 2304 1440)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst8" (rect -1 3 14 34)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst8" (rect -1 3 11 26)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2852,13 +2869,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 1568 2304 1600)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst28" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst28" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2870,13 +2887,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 1728 2304 1760)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst38" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst38" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2888,13 +2905,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 1888 2304 1920)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst48" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst48" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2906,13 +2923,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2272 2048 2304 2080)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst96" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst96" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -2924,34 +2941,34 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3192 2920 3272 3000)
-	(text "lpm_mux3" (rect 10 2 94 21)(font "Arial" (font_size 10)))
-	(text "inst102" (rect 8 64 56 79)(font "Arial" ))
+	(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
+	(text "inst102" (rect 8 64 43 76)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1" (rect 0 0 37 16)(font "Arial" (font_size 8)))
-		(text "data1" (rect 4 27 41 43)(font "Arial" (font_size 8)))
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 35 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 32 40)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data0" (rect 0 0 37 16)(font "Arial" (font_size 8)))
-		(text "data0" (rect 4 43 41 59)(font "Arial" (font_size 8)))
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 35 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 32 56)(line_width 1))
 	)
 	(port
 		(pt 40 80)
 		(input)
-		(text "sel" (rect 0 0 20 16)(font "Arial" (font_size 8)))
-		(text "sel" (rect 44 67 64 83)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 44 67 60 81)(font "Arial" (font_size 8)))
 		(line (pt 40 80)(pt 40 68)(line_width 1))
 	)
 	(port
 		(pt 80 48)
 		(output)
-		(text "result" (rect 0 0 37 16)(font "Arial" (font_size 8)))
-		(text "result" (rect 50 35 87 51)(font "Arial" (font_size 8)))
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 50 35 81 49)(font "Arial" (font_size 8)))
 		(line (pt 80 48)(pt 48 48)(line_width 1))
 	)
 	(drawing
@@ -2963,27 +2980,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3032 2400 3096 2448)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst79" (rect 3 37 43 52)(font "Arial" ))
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst79" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -2996,27 +3013,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3016 1920 3080 1968)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst103" (rect 3 37 51 52)(font "Arial" ))
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst103" (rect 3 37 38 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3029,27 +3046,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3024 2240 3088 2288)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst104" (rect 3 37 51 52)(font "Arial" ))
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst104" (rect 3 37 38 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3062,27 +3079,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2912 1664 2976 1712)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst105" (rect 3 37 51 52)(font "Arial" ))
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst105" (rect 3 37 38 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3095,27 +3112,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3008 1592 3072 1640)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst106" (rect 3 37 51 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst106" (rect 3 37 38 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3127,34 +3144,34 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2920 1472 2984 1520)
-	(text "OR3" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst107" (rect 3 37 52 53)(font "Arial" (font_size 8)))
+	(text "OR3" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst107" (rect 3 37 44 51)(font "Arial" (font_size 8)))
 	(port
 		(pt 0 24)
 		(input)
-		(text "IN2" (rect 2 15 26 31)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 15 26 31)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
 		(line (pt 0 24)(pt 18 24)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN3" (rect 2 24 26 40)(font "Courier New" (bold))(invisible))
-		(text "IN3" (rect 2 24 26 40)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
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-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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-		(text "OUT" (rect 47 15 71 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 47 15 71 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
 		(line (pt 49 24)(pt 64 24)(line_width 1))
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@@ -3167,32 +3184,32 @@ applicable agreement for further details.
 )
 (symbol
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-	(text "lpm_bustri_LONG" (rect -14 1 135 20)(font "Arial" (font_size 10)))
-	(text "inst108" (rect 69 24 117 39)(font "Arial" ))
+	(text "lpm_bustri_LONG" (rect -14 1 107 17)(font "Arial" (font_size 10)))
+	(text "inst108" (rect 69 24 104 36)(font "Arial" ))
 	(port
 		(pt 72 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 24 -6 81 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 24 -6 72 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 72 40)(pt 72 28)(line_width 1))
 	)
 	(port
 		(pt 112 24)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 55 -27 128 -11)(font "Arial" (font_size 8))(invisible))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 55 -27 115 -13)(font "Arial" (font_size 8))(invisible))
 		(line (pt 112 24)(pt 80 24)(line_width 3))
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 	(port
 		(pt 0 24)
 		(bidir)
-		(text "tridata[31..0]" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "tridata[31..0]" (rect -74 -36 12 -20)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect -74 -36 -4 -22)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 64 24)(line_width 3))
 	)
 	(drawing
-		(text "32" (rect 24 25 40 40)(font "Arial" ))
-		(text "32" (rect 88 25 104 40)(font "Arial" ))
+		(text "32" (rect 24 25 35 37)(font "Arial" ))
+		(text "32" (rect 88 25 99 37)(font "Arial" ))
 		(line (pt 80 16)(pt 64 24)(line_width 1))
 		(line (pt 64 24)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 80 16)(line_width 1))
@@ -3203,32 +3220,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 808 1288 920 1328)
-	(text "lpm_bustri_LONG" (rect -14 1 135 20)(font "Arial" (font_size 10)))
-	(text "inst109" (rect 69 24 117 39)(font "Arial" ))
+	(text "lpm_bustri_LONG" (rect -14 1 107 17)(font "Arial" (font_size 10)))
+	(text "inst109" (rect 69 24 104 36)(font "Arial" ))
 	(port
 		(pt 72 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 24 -6 81 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 24 -6 72 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 72 40)(pt 72 28)(line_width 1))
 	)
 	(port
 		(pt 112 24)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 55 -27 128 -11)(font "Arial" (font_size 8))(invisible))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 55 -27 115 -13)(font "Arial" (font_size 8))(invisible))
 		(line (pt 112 24)(pt 80 24)(line_width 3))
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 	(port
 		(pt 0 24)
 		(bidir)
-		(text "tridata[31..0]" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "tridata[31..0]" (rect -74 -36 12 -20)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect -74 -36 -4 -22)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 64 24)(line_width 3))
 	)
 	(drawing
-		(text "32" (rect 24 25 40 40)(font "Arial" ))
-		(text "32" (rect 88 25 104 40)(font "Arial" ))
+		(text "32" (rect 24 25 35 37)(font "Arial" ))
+		(text "32" (rect 88 25 99 37)(font "Arial" ))
 		(line (pt 80 16)(pt 64 24)(line_width 1))
 		(line (pt 64 24)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 80 16)(line_width 1))
@@ -3239,32 +3256,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 808 1408 920 1448)
-	(text "lpm_bustri_LONG" (rect -14 1 135 20)(font "Arial" (font_size 10)))
-	(text "inst110" (rect 69 24 117 39)(font "Arial" ))
+	(text "lpm_bustri_LONG" (rect -14 1 107 17)(font "Arial" (font_size 10)))
+	(text "inst110" (rect 69 24 104 36)(font "Arial" ))
 	(port
 		(pt 72 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 24 -6 81 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 24 -6 72 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 72 40)(pt 72 28)(line_width 1))
 	)
 	(port
 		(pt 112 24)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 55 -27 128 -11)(font "Arial" (font_size 8))(invisible))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 55 -27 115 -13)(font "Arial" (font_size 8))(invisible))
 		(line (pt 112 24)(pt 80 24)(line_width 3))
 	)
 	(port
 		(pt 0 24)
 		(bidir)
-		(text "tridata[31..0]" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "tridata[31..0]" (rect -74 -36 12 -20)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect -74 -36 -4 -22)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 64 24)(line_width 3))
 	)
 	(drawing
-		(text "32" (rect 24 25 40 40)(font "Arial" ))
-		(text "32" (rect 88 25 104 40)(font "Arial" ))
+		(text "32" (rect 24 25 35 37)(font "Arial" ))
+		(text "32" (rect 88 25 99 37)(font "Arial" ))
 		(line (pt 80 16)(pt 64 24)(line_width 1))
 		(line (pt 64 24)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 80 16)(line_width 1))
@@ -3275,32 +3292,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 808 1528 920 1568)
-	(text "lpm_bustri_LONG" (rect -14 1 135 20)(font "Arial" (font_size 10)))
-	(text "inst119" (rect 69 24 117 39)(font "Arial" ))
+	(text "lpm_bustri_LONG" (rect -14 1 107 17)(font "Arial" (font_size 10)))
+	(text "inst119" (rect 69 24 104 36)(font "Arial" ))
 	(port
 		(pt 72 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 24 -6 81 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 24 -6 72 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 72 40)(pt 72 28)(line_width 1))
 	)
 	(port
 		(pt 112 24)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 55 -27 128 -11)(font "Arial" (font_size 8))(invisible))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 55 -27 115 -13)(font "Arial" (font_size 8))(invisible))
 		(line (pt 112 24)(pt 80 24)(line_width 3))
 	)
 	(port
 		(pt 0 24)
 		(bidir)
-		(text "tridata[31..0]" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "tridata[31..0]" (rect -74 -36 12 -20)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect -74 -36 -4 -22)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 64 24)(line_width 3))
 	)
 	(drawing
-		(text "32" (rect 24 25 40 40)(font "Arial" ))
-		(text "32" (rect 88 25 104 40)(font "Arial" ))
+		(text "32" (rect 24 25 35 37)(font "Arial" ))
+		(text "32" (rect 88 25 99 37)(font "Arial" ))
 		(line (pt 80 16)(pt 64 24)(line_width 1))
 		(line (pt 64 24)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 80 16)(line_width 1))
@@ -3311,31 +3328,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1832 2728 1976 2808)
-	(text "lpm_ff1" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst9" (rect 8 64 39 79)(font "Arial" ))
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst9" (rect 8 64 31 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3346,31 +3363,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2416 2616 2560 2696)
-	(text "lpm_ff4" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst10" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst10" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[15..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[15..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3381,31 +3398,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3088 2680 3232 2760)
-	(text "lpm_ff5" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst11" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst11" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[7..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[7..0]" (rect 20 26 84 42)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 73 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[7..0]" (rect 0 0 43 16)(font "Arial" (font_size 8)))
-		(text "q[7..0]" (rect 95 42 138 58)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 95 42 130 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3415,42 +3432,42 @@ applicable agreement for further details.
 	)
 )
 (symbol
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-	(text "altddio_out0" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst2" (rect 8 104 39 119)(font "Arial" ))
+	(rect 1240 2568 1472 2688)
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst2" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h[3..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
-		(text "datain_h[3..0]" (rect 4 11 97 27)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 4 11 80 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l[3..0]" (rect 0 0 88 16)(font "Arial" (font_size 8)))
-		(text "datain_l[3..0]" (rect 4 27 92 43)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 4 27 75 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout[3..0]" (rect 0 0 86 16)(font "Arial" (font_size 8)))
-		(text "dataout[3..0]" (rect 169 11 255 27)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 169 11 239 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 3))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "high" (rect 92 84 120 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "high" (rect 92 84 112 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -3459,38 +3476,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 960 1256 1104 1352)
-	(text "lpm_ff0" (rect 44 1 106 20)(font "Arial" (font_size 10)))
-	(text "inst17" (rect 107 80 147 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 44 1 92 17)(font "Arial" (font_size 10)))
+	(text "inst17" (rect 107 80 136 92)(font "Arial" ))
 	(port
 		(pt 144 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 64 26 137 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 64 26 124 40)(font "Arial" (font_size 8)))
 		(line (pt 144 32)(pt 128 32)(line_width 3))
 	)
 	(port
 		(pt 144 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 89 42 125 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 89 42 118 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 1))
 	)
 	(port
 		(pt 144 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 87 58 131 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 87 58 124 72)(font "Arial" (font_size 8)))
 		(line (pt 144 64)(pt 128 64)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 13 50 64 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 13 50 55 64)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 13 17 40 32)(font "Arial" ))
+		(text "DFF" (rect 13 17 35 29)(font "Arial" ))
 		(line (pt 128 16)(pt 16 16)(line_width 1))
 		(line (pt 16 16)(pt 16 80)(line_width 1))
 		(line (pt 16 80)(pt 128 80)(line_width 1))
@@ -3502,38 +3519,38 @@ applicable agreement for further details.
 )
 (symbol
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-	(text "lpm_ff0" (rect 44 1 106 20)(font "Arial" (font_size 10)))
-	(text "inst18" (rect 107 80 147 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 44 1 92 17)(font "Arial" (font_size 10)))
+	(text "inst18" (rect 107 80 136 92)(font "Arial" ))
 	(port
 		(pt 144 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 64 26 137 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 64 26 124 40)(font "Arial" (font_size 8)))
 		(line (pt 144 32)(pt 128 32)(line_width 3))
 	)
 	(port
 		(pt 144 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 89 42 125 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 89 42 118 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 1))
 	)
 	(port
 		(pt 144 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 87 58 131 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 87 58 124 72)(font "Arial" (font_size 8)))
 		(line (pt 144 64)(pt 128 64)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 13 50 64 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 13 50 55 64)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 13 17 40 32)(font "Arial" ))
+		(text "DFF" (rect 13 17 35 29)(font "Arial" ))
 		(line (pt 128 16)(pt 16 16)(line_width 1))
 		(line (pt 16 16)(pt 16 80)(line_width 1))
 		(line (pt 16 80)(pt 128 80)(line_width 1))
@@ -3545,38 +3562,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 960 1496 1104 1592)
-	(text "lpm_ff0" (rect 44 1 106 20)(font "Arial" (font_size 10)))
-	(text "inst19" (rect 107 80 147 95)(font "Arial" ))
+	(text "lpm_ff0" (rect 44 1 92 17)(font "Arial" (font_size 10)))
+	(text "inst19" (rect 107 80 136 92)(font "Arial" ))
 	(port
 		(pt 144 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 64 26 137 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 64 26 124 40)(font "Arial" (font_size 8)))
 		(line (pt 144 32)(pt 128 32)(line_width 3))
 	)
 	(port
 		(pt 144 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 89 42 125 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 89 42 118 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 1))
 	)
 	(port
 		(pt 144 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 87 58 131 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 87 58 124 72)(font "Arial" (font_size 8)))
 		(line (pt 144 64)(pt 128 64)(line_width 1))
 	)
 	(port
 		(pt 0 56)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 13 50 64 66)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 13 50 55 64)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 13 17 40 32)(font "Arial" ))
+		(text "DFF" (rect 13 17 35 29)(font "Arial" ))
 		(line (pt 128 16)(pt 16 16)(line_width 1))
 		(line (pt 16 16)(pt 16 80)(line_width 1))
 		(line (pt 16 80)(pt 128 80)(line_width 1))
@@ -3588,31 +3605,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1040 888 1184 968)
-	(text "lpm_ff1" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst3" (rect 8 64 39 79)(font "Arial" ))
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst3" (rect 8 64 31 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3623,31 +3640,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1296 904 1440 984)
-	(text "lpm_ff1" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst4" (rect 8 64 39 79)(font "Arial" ))
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst4" (rect 8 64 31 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3658,31 +3675,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1040 976 1184 1056)
-	(text "lpm_ff1" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst12" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst12" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3693,31 +3710,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1296 992 1440 1072)
-	(text "lpm_ff1" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst20" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst20" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -3728,48 +3745,48 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1344 1280 1496 1392)
-	(text "lpm_mux5" (rect 50 2 134 21)(font "Arial" (font_size 10)))
-	(text "inst22" (rect 8 96 48 111)(font "Arial" ))
+	(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst22" (rect 8 96 37 108)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data3x[63..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data3x[63..0]" (rect 4 27 93 43)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 4 27 78 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data2x[63..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data2x[63..0]" (rect 4 43 93 59)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 4 43 78 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data1x[63..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data1x[63..0]" (rect 4 59 93 75)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 4 59 78 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data0x[63..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data0x[63..0]" (rect 4 75 93 91)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 4 75 78 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 80 112)
 		(input)
-		(text "sel[1..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[1..0]" (rect 84 99 139 115)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 99 128 113)(font "Arial" (font_size 8)))
 		(line (pt 80 112)(pt 80 100)(line_width 3))
 	)
 	(port
 		(pt 152 64)
 		(output)
-		(text "result[63..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[63..0]" (rect 92 51 173 67)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 92 51 159 65)(font "Arial" (font_size 8)))
 		(line (pt 152 64)(pt 88 64)(line_width 3))
 	)
 	(drawing
@@ -3780,42 +3797,42 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 992 2760 1056 2840)
-	(text "DFF" (rect 1 0 23 13)(font "Arial" (font_size 6)))
-	(text "inst88" (rect 3 68 43 83)(font "Arial" ))
+	(rect 1352 1792 1416 1872)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst88" (rect 3 68 32 80)(font "Arial" ))
 	(port
 		(pt 32 80)
 		(input)
-		(text "CLRN" (rect 21 59 54 75)(font "Courier New" (bold)))
-		(text "CLRN" (rect 21 58 54 74)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
 		(line (pt 32 80)(pt 32 76)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
 		(line (pt 0 40)(pt 12 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 12 24)(line_width 1))
 	)
 	(port
 		(pt 32 0)
 		(input)
-		(text "PRN" (rect 24 13 48 29)(font "Courier New" (bold)))
-		(text "PRN" (rect 24 11 48 27)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
 		(line (pt 32 4)(pt 32 0)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
 		(line (pt 52 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3830,42 +3847,42 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 968 2376 1032 2456)
-	(text "DFF" (rect 1 0 23 13)(font "Arial" (font_size 6)))
-	(text "inst90" (rect 3 68 43 83)(font "Arial" ))
+	(rect 1352 1688 1416 1768)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst90" (rect 3 68 32 80)(font "Arial" ))
 	(port
 		(pt 32 80)
 		(input)
-		(text "CLRN" (rect 21 59 54 75)(font "Courier New" (bold)))
-		(text "CLRN" (rect 21 58 54 74)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
 		(line (pt 32 80)(pt 32 76)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
 		(line (pt 0 40)(pt 12 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 12 24)(line_width 1))
 	)
 	(port
 		(pt 32 0)
 		(input)
-		(text "PRN" (rect 24 13 48 29)(font "Courier New" (bold)))
-		(text "PRN" (rect 24 11 48 27)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
 		(line (pt 32 4)(pt 32 0)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
 		(line (pt 52 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3881,76 +3898,76 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1312 1512 1552 1648)
-	(text "altddio_bidir0" (rect 82 1 196 20)(font "Arial" (font_size 10)))
-	(text "inst1" (rect 8 120 39 135)(font "Arial" ))
+	(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
+	(text "inst1" (rect 8 120 31 132)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h[31..0]" (rect 0 0 101 16)(font "Arial" (font_size 8)))
-		(text "datain_h[31..0]" (rect 4 11 105 27)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 4 11 87 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l[31..0]" (rect 0 0 96 16)(font "Arial" (font_size 8)))
-		(text "datain_l[31..0]" (rect 4 27 100 43)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 4 27 83 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "oe" (rect 0 0 16 16)(font "Arial" (font_size 8)))
-		(text "oe" (rect 4 43 20 59)(font "Arial" (font_size 8)))
+		(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "oe" (rect 4 43 18 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "inclock" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "inclock" (rect 4 59 52 75)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 4 59 42 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 88 72)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 75 61 91)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 75 51 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 88 88)(line_width 1))
 	)
 	(port
 		(pt 240 24)
 		(output)
-		(text "dataout_h[31..0]" (rect 0 0 110 16)(font "Arial" (font_size 8)))
-		(text "dataout_h[31..0]" (rect 159 11 269 27)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 159 11 251 25)(font "Arial" (font_size 8)))
 		(line (pt 240 24)(pt 144 24)(line_width 3))
 	)
 	(port
 		(pt 240 40)
 		(output)
-		(text "dataout_l[31..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "dataout_l[31..0]" (rect 163 27 269 43)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 163 27 250 41)(font "Arial" (font_size 8)))
 		(line (pt 240 40)(pt 144 40)(line_width 3))
 	)
 	(port
 		(pt 240 72)
 		(output)
-		(text "combout[31..0]" (rect 0 0 102 16)(font "Arial" (font_size 8)))
-		(text "combout[31..0]" (rect 166 59 268 75)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 166 59 249 73)(font "Arial" (font_size 8)))
 		(line (pt 240 72)(pt 144 72)(line_width 3))
 	)
 	(port
 		(pt 240 56)
 		(bidir)
-		(text "padio[31..0]" (rect 0 0 80 16)(font "Arial" (font_size 8)))
-		(text "padio[31..0]" (rect 181 43 261 59)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 181 43 247 57)(font "Arial" (font_size 8)))
 		(line (pt 240 56)(pt 144 56)(line_width 3))
 	)
 	(drawing
-		(text "ddio" (rect 108 27 136 43)(font "Arial" (font_size 8)))
-		(text "bidir" (rect 108 42 136 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 90 152 105)(font "Arial" ))
-		(text "low" (rect 92 100 114 115)(font "Arial" ))
+		(text "ddio" (rect 108 27 131 41)(font "Arial" (font_size 8)))
+		(text "bidir" (rect 108 42 131 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 90 135 102)(font "Arial" ))
+		(text "low" (rect 92 100 107 112)(font "Arial" ))
 		(line (pt 88 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 112)(line_width 1))
 		(line (pt 144 112)(pt 88 112)(line_width 1))
@@ -3959,34 +3976,34 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 368 1784 432 1832)
-	(text "OR3" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst39" (rect 3 37 44 53)(font "Arial" (font_size 8)))
+	(text "OR3" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst39" (rect 3 37 37 51)(font "Arial" (font_size 8)))
 	(port
 		(pt 0 24)
 		(input)
-		(text "IN2" (rect 2 15 26 31)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 15 26 31)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 15 19 27)(font "Courier New" (bold))(invisible))
 		(line (pt 0 24)(pt 18 24)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN3" (rect 2 24 26 40)(font "Courier New" (bold))(invisible))
-		(text "IN3" (rect 2 24 26 40)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
+		(text "IN3" (rect 2 24 19 36)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 16 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 47 15 71 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 47 15 71 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 47 15 64 27)(font "Courier New" (bold))(invisible))
 		(line (pt 49 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -3999,27 +4016,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1688 1552 1848 1632)
-	(text "lpm_latch0" (rect 49 1 139 20)(font "Arial" (font_size 10)))
-	(text "inst27" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10)))
+	(text "inst27" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[31..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[31..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "gate" (rect 0 0 29 16)(font "Arial" (font_size 8)))
-		(text "gate" (rect 20 42 49 58)(font "Arial" (font_size 8)))
+		(text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "gate" (rect 20 42 44 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 160 32)
 		(output)
-		(text "q[31..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[31..0]" (rect 105 26 156 42)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 26 147 40)(font "Arial" (font_size 8)))
 		(line (pt 160 32)(pt 144 32)(line_width 3))
 	)
 	(drawing
@@ -4029,75 +4046,33 @@ applicable agreement for further details.
 		(line (pt 16 64)(pt 16 16)(line_width 1))
 	)
 )
-(symbol
-	(rect 888 2904 1032 3000)
-	(text "lpm_ff6" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst36" (rect 8 80 48 95)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 101 42)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 48)
-		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
-		(line (pt 0 48)(pt 16 48)(line_width 1))
-	)
-	(port
-		(pt 0 64)
-		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 16 64)(line_width 1))
-	)
-	(port
-		(pt 144 56)
-		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 83 50 143 66)(font "Arial" (font_size 8)))
-		(line (pt 144 56)(pt 128 56)(line_width 3))
-	)
-	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
-		(line (pt 16 16)(pt 128 16)(line_width 1))
-		(line (pt 128 16)(pt 128 80)(line_width 1))
-		(line (pt 128 80)(pt 16 80)(line_width 1))
-		(line (pt 16 80)(pt 16 16)(line_width 1))
-		(line (pt 16 42)(pt 22 48)(line_width 1))
-		(line (pt 22 48)(pt 16 54)(line_width 1))
-	)
-)
 (symbol
 	(rect 920 2144 1064 2224)
-	(text "lpm_shiftreg6" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "inst92" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst92" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 62 42)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 55 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 60 58)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 54 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[4..0]" (rect 0 0 43 16)(font "Arial" (font_size 8)))
-		(text "q[4..0]" (rect 95 42 138 58)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 130 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "right shift" (rect 88 17 147 32)(font "Arial" ))
+		(text "right shift" (rect 88 17 135 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4107,32 +4082,32 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 904 2528 1048 2608)
-	(text "lpm_shiftreg6" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "inst89" (rect 8 64 48 79)(font "Arial" ))
+	(rect 920 2240 1064 2320)
+	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst89" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 62 42)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 55 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 60 58)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 54 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[4..0]" (rect 0 0 43 16)(font "Arial" (font_size 8)))
-		(text "q[4..0]" (rect 95 42 138 58)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 130 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "right shift" (rect 88 17 147 32)(font "Arial" ))
+		(text "right shift" (rect 88 17 135 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4142,32 +4117,32 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 920 2248 1064 2328)
-	(text "lpm_shiftreg4" (rect 34 1 148 20)(font "Arial" (font_size 10)))
-	(text "inst26" (rect 8 64 48 79)(font "Arial" ))
+	(rect 1336 2000 1480 2080)
+	(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst26" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 26 62 42)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 55 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 1))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "shiftin" (rect 0 0 40 16)(font "Arial" (font_size 8)))
-		(text "shiftin" (rect 20 42 60 58)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 54 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "shiftout" (rect 0 0 49 16)(font "Arial" (font_size 8)))
-		(text "shiftout" (rect 89 42 138 58)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 1))
 	)
 	(drawing
-		(text "right shift" (rect 88 17 147 32)(font "Arial" ))
+		(text "right shift" (rect 88 17 135 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4178,41 +4153,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2080 1528 2144 1608)
-	(text "DFF" (rect 1 0 23 13)(font "Arial" (font_size 6)))
-	(text "inst95" (rect 3 68 43 83)(font "Arial" ))
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst95" (rect 3 68 32 80)(font "Arial" ))
 	(port
 		(pt 32 80)
 		(input)
-		(text "CLRN" (rect 21 59 54 75)(font "Courier New" (bold)))
-		(text "CLRN" (rect 21 58 54 74)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
 		(line (pt 32 80)(pt 32 76)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
 		(line (pt 0 40)(pt 12 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 12 24)(line_width 1))
 	)
 	(port
 		(pt 32 0)
 		(input)
-		(text "PRN" (rect 24 13 48 29)(font "Courier New" (bold)))
-		(text "PRN" (rect 24 11 48 27)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
 		(line (pt 32 4)(pt 32 0)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
 		(line (pt 52 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -4227,28 +4202,28 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 1312 2320 1376 2368)
-	(text "OR2" (rect 1 0 25 13)(font "Arial" (font_size 6)))
-	(text "inst37" (rect 3 37 43 52)(font "Arial" ))
+	(rect 1352 1912 1416 1960)
+	(text "OR2" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst37" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 15 32)(line_width 1))
 	)
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 15 16)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 48 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -4260,32 +4235,32 @@ applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 1088 2640 1232 2720)
-	(text "lpm_ff5" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst97" (rect 8 64 48 79)(font "Arial" ))
+	(rect 928 2696 1072 2776)
+	(text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst97" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[7..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[7..0]" (rect 20 26 84 42)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 73 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[7..0]" (rect 0 0 43 16)(font "Arial" (font_size 8)))
-		(text "q[7..0]" (rect 95 42 138 58)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 95 42 130 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4296,41 +4271,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 4280 2768 4512 2888)
-	(text "altddio_out2" (rect 81 1 183 20)(font "Arial" (font_size 10)))
-	(text "inst5" (rect 8 104 39 119)(font "Arial" ))
+	(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst5" (rect 8 104 31 116)(font "Arial" ))
 	(port
 		(pt 0 24)
 		(input)
-		(text "datain_h[23..0]" (rect 0 0 101 16)(font "Arial" (font_size 8)))
-		(text "datain_h[23..0]" (rect 4 11 105 27)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 4 11 87 25)(font "Arial" (font_size 8)))
 		(line (pt 0 24)(pt 88 24)(line_width 3))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "datain_l[23..0]" (rect 0 0 96 16)(font "Arial" (font_size 8)))
-		(text "datain_l[23..0]" (rect 4 27 100 43)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 4 27 83 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 88 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "outclock" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 61 59)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 51 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 88 56)(line_width 1))
 	)
 	(port
 		(pt 232 24)
 		(output)
-		(text "dataout[23..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
-		(text "dataout[23..0]" (rect 163 11 257 27)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 163 11 240 25)(font "Arial" (font_size 8)))
 		(line (pt 232 24)(pt 152 24)(line_width 3))
 	)
 	(drawing
-		(text "ddio" (rect 110 27 138 43)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 147 58)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 152 89)(font "Arial" ))
-		(text "low" (rect 92 84 114 99)(font "Arial" ))
+		(text "ddio" (rect 110 27 133 41)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 140 56)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 135 86)(font "Arial" ))
+		(text "low" (rect 92 84 107 96)(font "Arial" ))
 		(line (pt 88 16)(pt 152 16)(line_width 1))
 		(line (pt 152 16)(pt 152 96)(line_width 1))
 		(line (pt 152 96)(pt 88 96)(line_width 1))
@@ -4339,18 +4314,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3720 1936 3816 1984)
-	(text "lpm_constant1" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst77" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst77" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[1..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[1..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "2" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -4360,18 +4335,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3720 1736 3816 1784)
-	(text "lpm_constant1" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst80" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst80" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[1..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[1..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "2" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -4381,18 +4356,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3720 1528 3816 1576)
-	(text "lpm_constant1" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst83" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst83" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[1..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[1..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "2" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -4402,18 +4377,18 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2424 2720 2520 2768)
-	(text "lpm_constant2" (rect 6 1 128 20)(font "Arial" (font_size 10)))
-	(text "inst23" (rect 8 32 48 47)(font "Arial" ))
+	(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst23" (rect 8 32 37 44)(font "Arial" ))
 	(port
 		(pt 96 24)
 		(output)
-		(text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 93 -25 166 -9)(font "Arial" (font_size 8))(invisible))
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 93 -25 153 -11)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 80 24)(line_width 3))
 	)
 	(drawing
-		(text "0" (rect 75 18 83 33)(font "Arial" ))
-		(text "8" (rect 87 25 95 40)(font "Arial" ))
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "8" (rect 87 25 92 37)(font "Arial" ))
 		(line (pt 16 16)(pt 80 16)(line_width 1))
 		(line (pt 80 16)(pt 80 32)(line_width 1))
 		(line (pt 80 32)(pt 16 32)(line_width 1))
@@ -4423,83 +4398,83 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 4024 2696 4176 2888)
-	(text "lpm_mux6" (rect 50 2 134 21)(font "Arial" (font_size 10)))
-	(text "inst7" (rect 8 176 39 191)(font "Arial" ))
+	(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst7" (rect 8 176 31 188)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data7x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data7x[23..0]" (rect 4 27 93 43)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 4 27 78 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data6x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data6x[23..0]" (rect 4 43 93 59)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 4 43 78 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data5x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data5x[23..0]" (rect 4 59 93 75)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 4 59 78 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data4x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data4x[23..0]" (rect 4 75 93 91)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 4 75 78 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data3x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data3x[23..0]" (rect 4 91 93 107)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 4 91 78 105)(font "Arial" (font_size 8)))
 		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data2x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data2x[23..0]" (rect 4 107 93 123)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 4 107 78 121)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data1x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data1x[23..0]" (rect 4 123 93 139)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 4 123 78 137)(font "Arial" (font_size 8)))
 		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data0x[23..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data0x[23..0]" (rect 4 139 93 155)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 4 139 78 153)(font "Arial" (font_size 8)))
 		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 40 171)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 33 169)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 72 168)(line_width 1))
 	)
 	(port
 		(pt 80 192)
 		(input)
-		(text "sel[2..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[2..0]" (rect 84 179 139 195)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 128 193)(font "Arial" (font_size 8)))
 		(line (pt 80 192)(pt 80 180)(line_width 3))
 	)
 	(port
 		(pt 152 104)
 		(output)
-		(text "result[23..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[23..0]" (rect 92 91 173 107)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 92 91 159 105)(font "Arial" (font_size 8)))
 		(line (pt 152 104)(pt 88 104)(line_width 3))
 	)
 	(drawing
@@ -4513,139 +4488,139 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2824 2544 2968 2864)
-	(text "lpm_mux2" (rect 50 2 134 21)(font "Arial" (font_size 10)))
-	(text "inst25" (rect 8 304 48 319)(font "Arial" ))
+	(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst25" (rect 8 304 37 316)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data15x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data15x[7..0]" (rect 4 27 93 43)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 4 27 78 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data14x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data14x[7..0]" (rect 4 43 93 59)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 4 43 78 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data13x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data13x[7..0]" (rect 4 59 93 75)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 4 59 78 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data12x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data12x[7..0]" (rect 4 75 93 91)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 4 75 78 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data11x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data11x[7..0]" (rect 4 91 93 107)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 4 91 78 105)(font "Arial" (font_size 8)))
 		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data10x[7..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data10x[7..0]" (rect 4 107 93 123)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 4 107 78 121)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data9x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data9x[7..0]" (rect 4 123 85 139)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 4 123 71 137)(font "Arial" (font_size 8)))
 		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data8x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data8x[7..0]" (rect 4 139 85 155)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 4 139 71 153)(font "Arial" (font_size 8)))
 		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "data7x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data7x[7..0]" (rect 4 155 85 171)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 4 155 71 169)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 72 168)(line_width 3))
 	)
 	(port
 		(pt 0 184)
 		(input)
-		(text "data6x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data6x[7..0]" (rect 4 171 85 187)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 4 171 71 185)(font "Arial" (font_size 8)))
 		(line (pt 0 184)(pt 72 184)(line_width 3))
 	)
 	(port
 		(pt 0 200)
 		(input)
-		(text "data5x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data5x[7..0]" (rect 4 187 85 203)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 4 187 71 201)(font "Arial" (font_size 8)))
 		(line (pt 0 200)(pt 72 200)(line_width 3))
 	)
 	(port
 		(pt 0 216)
 		(input)
-		(text "data4x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data4x[7..0]" (rect 4 203 85 219)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 4 203 71 217)(font "Arial" (font_size 8)))
 		(line (pt 0 216)(pt 72 216)(line_width 3))
 	)
 	(port
 		(pt 0 232)
 		(input)
-		(text "data3x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data3x[7..0]" (rect 4 219 85 235)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 4 219 71 233)(font "Arial" (font_size 8)))
 		(line (pt 0 232)(pt 72 232)(line_width 3))
 	)
 	(port
 		(pt 0 248)
 		(input)
-		(text "data2x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data2x[7..0]" (rect 4 235 85 251)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 4 235 71 249)(font "Arial" (font_size 8)))
 		(line (pt 0 248)(pt 72 248)(line_width 3))
 	)
 	(port
 		(pt 0 264)
 		(input)
-		(text "data1x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data1x[7..0]" (rect 4 251 85 267)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 4 251 71 265)(font "Arial" (font_size 8)))
 		(line (pt 0 264)(pt 72 264)(line_width 3))
 	)
 	(port
 		(pt 0 280)
 		(input)
-		(text "data0x[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data0x[7..0]" (rect 4 267 85 283)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 4 267 71 281)(font "Arial" (font_size 8)))
 		(line (pt 0 280)(pt 72 280)(line_width 3))
 	)
 	(port
 		(pt 0 296)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 283 40 299)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 283 33 297)(font "Arial" (font_size 8)))
 		(line (pt 0 296)(pt 72 296)(line_width 1))
 	)
 	(port
 		(pt 80 320)
 		(input)
-		(text "sel[3..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[3..0]" (rect 84 307 139 323)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 84 307 128 321)(font "Arial" (font_size 8)))
 		(line (pt 80 320)(pt 80 308)(line_width 3))
 	)
 	(port
 		(pt 144 168)
 		(output)
-		(text "result[7..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "result[7..0]" (rect 90 155 163 171)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 90 155 150 169)(font "Arial" (font_size 8)))
 		(line (pt 144 168)(pt 88 168)(line_width 3))
 	)
 	(drawing
@@ -4659,83 +4634,83 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2224 2544 2376 2736)
-	(text "lpm_mux1" (rect 50 2 134 21)(font "Arial" (font_size 10)))
-	(text "inst24" (rect 8 176 48 191)(font "Arial" ))
+	(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst24" (rect 8 176 37 188)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data7x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data7x[15..0]" (rect 4 27 93 43)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 4 27 78 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data6x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data6x[15..0]" (rect 4 43 93 59)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 4 43 78 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data5x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data5x[15..0]" (rect 4 59 93 75)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 4 59 78 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data4x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data4x[15..0]" (rect 4 75 93 91)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 4 75 78 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data3x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data3x[15..0]" (rect 4 91 93 107)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 4 91 78 105)(font "Arial" (font_size 8)))
 		(line (pt 0 104)(pt 72 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data2x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data2x[15..0]" (rect 4 107 93 123)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 4 107 78 121)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 72 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data1x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data1x[15..0]" (rect 4 123 93 139)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 4 123 78 137)(font "Arial" (font_size 8)))
 		(line (pt 0 136)(pt 72 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data0x[15..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data0x[15..0]" (rect 4 139 93 155)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 4 139 78 153)(font "Arial" (font_size 8)))
 		(line (pt 0 152)(pt 72 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 155 40 171)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 33 169)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 72 168)(line_width 1))
 	)
 	(port
 		(pt 80 192)
 		(input)
-		(text "sel[2..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[2..0]" (rect 84 179 139 195)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 128 193)(font "Arial" (font_size 8)))
 		(line (pt 80 192)(pt 80 180)(line_width 3))
 	)
 	(port
 		(pt 152 104)
 		(output)
-		(text "result[15..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[15..0]" (rect 92 91 173 107)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 92 91 159 105)(font "Arial" (font_size 8)))
 		(line (pt 152 104)(pt 88 104)(line_width 3))
 	)
 	(drawing
@@ -4749,55 +4724,55 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1616 2688 1768 2816)
-	(text "lpm_mux0" (rect 50 2 134 21)(font "Arial" (font_size 10)))
-	(text "inst21" (rect 8 112 48 127)(font "Arial" ))
+	(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst21" (rect 8 112 37 124)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data3x[31..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data3x[31..0]" (rect 4 27 93 43)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 4 27 78 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 72 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data2x[31..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data2x[31..0]" (rect 4 43 93 59)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 4 43 78 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 72 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data1x[31..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data1x[31..0]" (rect 4 59 93 75)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 4 59 78 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 72 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data0x[31..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "data0x[31..0]" (rect 4 75 93 91)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 4 75 78 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 72 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 91 40 107)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 91 33 105)(font "Arial" (font_size 8)))
 		(line (pt 0 104)(pt 72 104)(line_width 1))
 	)
 	(port
 		(pt 80 128)
 		(input)
-		(text "sel[1..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[1..0]" (rect 84 115 139 131)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 115 128 129)(font "Arial" (font_size 8)))
 		(line (pt 80 128)(pt 80 116)(line_width 3))
 	)
 	(port
 		(pt 152 72)
 		(output)
-		(text "result[31..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 92 59 173 75)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 92 59 159 73)(font "Arial" (font_size 8)))
 		(line (pt 152 72)(pt 88 72)(line_width 3))
 	)
 	(drawing
@@ -4811,31 +4786,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3672 2752 3816 2832)
-	(text "lpm_ff3" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst46" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst46" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[23..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[23..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[23..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[23..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4846,31 +4821,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3432 2736 3576 2816)
-	(text "lpm_ff3" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst47" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst47" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[23..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[23..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[23..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[23..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4881,31 +4856,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3672 2840 3816 2920)
-	(text "lpm_ff3" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst49" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst49" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[23..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[23..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[23..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[23..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4916,31 +4891,31 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3432 2824 3576 2904)
-	(text "lpm_ff3" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst52" (rect 8 64 48 79)(font "Arial" ))
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst52" (rect 8 64 37 76)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[23..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
-		(text "data[23..0]" (rect 20 26 93 42)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 80 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 144 48)
 		(output)
-		(text "q[23..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
-		(text "q[23..0]" (rect 89 42 140 58)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 131 56)(font "Arial" (font_size 8)))
 		(line (pt 144 48)(pt 128 48)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 64)(line_width 1))
 		(line (pt 128 64)(pt 16 64)(line_width 1))
@@ -4951,41 +4926,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2912 2936 2976 3016)
-	(text "DFF" (rect 1 0 23 13)(font "Arial" (font_size 6)))
-	(text "inst91" (rect 3 68 43 83)(font "Arial" ))
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst91" (rect 3 68 32 80)(font "Arial" ))
 	(port
 		(pt 32 80)
 		(input)
-		(text "CLRN" (rect 21 59 54 75)(font "Courier New" (bold)))
-		(text "CLRN" (rect 21 58 54 74)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
 		(line (pt 32 80)(pt 32 76)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
 		(line (pt 0 40)(pt 12 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 12 24)(line_width 1))
 	)
 	(port
 		(pt 32 0)
 		(input)
-		(text "PRN" (rect 24 13 48 29)(font "Courier New" (bold)))
-		(text "PRN" (rect 24 11 48 27)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
 		(line (pt 32 4)(pt 32 0)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
 		(line (pt 52 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -5001,41 +4976,41 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3048 2936 3112 3016)
-	(text "DFF" (rect 1 0 23 13)(font "Arial" (font_size 6)))
-	(text "inst93" (rect 3 68 43 83)(font "Arial" ))
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst93" (rect 3 68 32 80)(font "Arial" ))
 	(port
 		(pt 32 80)
 		(input)
-		(text "CLRN" (rect 21 59 54 75)(font "Courier New" (bold)))
-		(text "CLRN" (rect 21 58 54 74)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
 		(line (pt 32 80)(pt 32 76)(line_width 1))
 	)
 	(port
 		(pt 0 40)
 		(input)
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
-		(text "CLK" (rect 3 29 27 45)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
 		(line (pt 0 40)(pt 12 40)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
-		(text "D" (rect 14 20 22 36)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
 		(line (pt 0 24)(pt 12 24)(line_width 1))
 	)
 	(port
 		(pt 32 0)
 		(input)
-		(text "PRN" (rect 24 13 48 29)(font "Courier New" (bold)))
-		(text "PRN" (rect 24 11 48 27)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
 		(line (pt 32 4)(pt 32 0)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
-		(text "Q" (rect 45 20 53 36)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
 		(line (pt 52 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -5049,115 +5024,34 @@ applicable agreement for further details.
 		(circle (rect 28 68 36 76)(line_width 1))
 	)
 )
-(symbol
-	(rect 1712 1328 1872 1496)
-	(text "lpm_fifo_dc0" (rect 44 1 153 20)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 152 31 167)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 101 42)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "wrreq" (rect 20 50 56 66)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 16 56)(line_width 1))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "wrclk" (rect 0 0 35 16)(font "Arial" (font_size 8)))
-		(text "wrclk" (rect 26 66 61 82)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 16 72)(line_width 1))
-	)
-	(port
-		(pt 0 104)
-		(input)
-		(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
-		(text "rdreq" (rect 20 98 54 114)(font "Arial" (font_size 8)))
-		(line (pt 0 104)(pt 16 104)(line_width 1))
-	)
-	(port
-		(pt 0 120)
-		(input)
-		(text "rdclk" (rect 0 0 33 16)(font "Arial" (font_size 8)))
-		(text "rdclk" (rect 26 114 59 130)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 16 120)(line_width 1))
-	)
-	(port
-		(pt 0 144)
-		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 138 44 154)(font "Arial" (font_size 8)))
-		(line (pt 0 144)(pt 16 144)(line_width 1))
-	)
-	(port
-		(pt 160 72)
-		(output)
-		(text "wrusedw[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
-		(text "wrusedw[8..0]" (rect 69 66 163 82)(font "Arial" (font_size 8)))
-		(line (pt 160 72)(pt 144 72)(line_width 3))
-	)
-	(port
-		(pt 160 96)
-		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 99 90 159 106)(font "Arial" (font_size 8)))
-		(line (pt 160 96)(pt 144 96)(line_width 3))
-	)
-	(port
-		(pt 160 120)
-		(output)
-		(text "rdempty" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "rdempty" (rect 102 114 157 130)(font "Arial" (font_size 8)))
-		(line (pt 160 120)(pt 144 120)(line_width 1))
-	)
-	(drawing
-		(text "128 bits x 512 words" (rect 58 140 191 155)(font "Arial" ))
-		(line (pt 16 16)(pt 144 16)(line_width 1))
-		(line (pt 144 16)(pt 144 152)(line_width 1))
-		(line (pt 144 152)(pt 16 152)(line_width 1))
-		(line (pt 16 152)(pt 16 16)(line_width 1))
-		(line (pt 16 84)(pt 144 84)(line_width 1))
-		(line (pt 16 132)(pt 144 132)(line_width 1))
-		(line (pt 16 66)(pt 22 72)(line_width 1))
-		(line (pt 22 72)(pt 16 78)(line_width 1))
-		(line (pt 16 114)(pt 22 120)(line_width 1))
-		(line (pt 22 120)(pt 16 126)(line_width 1))
-	)
-)
 (symbol
 	(rect 3768 2488 3864 2528)
-	(text "lpm_bustri_BYT" (rect 2 1 136 20)(font "Arial" (font_size 10)))
-	(text "inst53" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
+	(text "inst53" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[7..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[7..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 96 24)
 		(bidir)
-		(text "tridata[7..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[7..0]" (rect 100 -30 177 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 100 -30 163 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "8" (rect 71 25 79 40)(font "Arial" ))
-		(text "8" (rect 15 25 23 40)(font "Arial" ))
+		(text "8" (rect 71 25 76 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -5167,13 +5061,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 2384 3328 2416)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst75" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst75" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -5185,32 +5079,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3768 2280 3864 2320)
-	(text "lpm_bustri_BYT" (rect 2 1 136 20)(font "Arial" (font_size 10)))
-	(text "inst57" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
+	(text "inst57" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[7..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[7..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 96 24)
 		(bidir)
-		(text "tridata[7..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[7..0]" (rect 100 -30 177 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 100 -30 163 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "8" (rect 71 25 79 40)(font "Arial" ))
-		(text "8" (rect 15 25 23 40)(font "Arial" ))
+		(text "8" (rect 71 25 76 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -5220,13 +5114,13 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3296 2176 3328 2208)
-	(text "GND" (rect 6 8 19 33)(font "Arial" (font_size 6))(vertical))
-	(text "inst76" (rect -1 3 14 43)(font "Arial" )(vertical)(invisible))
+	(text "GND" (rect 6 8 16 29)(font "Arial" (font_size 6))(vertical))
+	(text "inst76" (rect -1 3 11 32)(font "Arial" )(vertical)(invisible))
 	(port
 		(pt 32 16)
 		(output)
-		(text "1" (rect 18 0 26 16)(font "Courier New" (bold))(invisible))
-		(text "1" (rect 20 18 36 26)(font "Courier New" (bold))(vertical)(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 20 18 32 23)(font "Courier New" (bold))(vertical)(invisible))
 		(line (pt 24 16)(pt 32 16)(line_width 1))
 	)
 	(drawing
@@ -5238,32 +5132,32 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3768 2072 3864 2112)
-	(text "lpm_bustri_BYT" (rect 2 1 136 20)(font "Arial" (font_size 10)))
-	(text "inst58" (rect 8 24 48 39)(font "Arial" ))
+	(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
+	(text "inst58" (rect 8 24 37 36)(font "Arial" ))
 	(port
 		(pt 40 40)
 		(input)
-		(text "enabledt" (rect 0 0 57 16)(font "Arial" (font_size 8)))
-		(text "enabledt" (rect 40 -6 97 10)(font "Arial" (font_size 8))(invisible))
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 88 8)(font "Arial" (font_size 8))(invisible))
 		(line (pt 40 40)(pt 40 28)(line_width 1))
 	)
 	(port
 		(pt 0 24)
 		(input)
-		(text "data[7..0]" (rect 0 0 64 16)(font "Arial" (font_size 8)))
-		(text "data[7..0]" (rect -3 -21 61 -5)(font "Arial" (font_size 8))(invisible))
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 50 -7)(font "Arial" (font_size 8))(invisible))
 		(line (pt 0 24)(pt 32 24)(line_width 3))
 	)
 	(port
 		(pt 96 24)
 		(bidir)
-		(text "tridata[7..0]" (rect 0 0 77 16)(font "Arial" (font_size 8)))
-		(text "tridata[7..0]" (rect 100 -30 177 -14)(font "Arial" (font_size 8))(invisible))
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 100 -30 163 -16)(font "Arial" (font_size 8))(invisible))
 		(line (pt 96 24)(pt 48 24)(line_width 3))
 	)
 	(drawing
-		(text "8" (rect 71 25 79 40)(font "Arial" ))
-		(text "8" (rect 15 25 23 40)(font "Arial" ))
+		(text "8" (rect 71 25 76 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
 		(line (pt 32 16)(pt 48 24)(line_width 1))
 		(line (pt 48 24)(pt 32 32)(line_width 1))
 		(line (pt 32 32)(pt 32 16)(line_width 1))
@@ -5273,82 +5167,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 2272 3704 2480)
-	(text "altdpram2" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ACP_CLUT_RAM54" (rect 8 192 136 207)(font "Arial" ))
+	(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ACP_CLUT_RAM54" (rect 8 192 105 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[7..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[7..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[7..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[7..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -5425,82 +5319,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 2480 3704 2688)
-	(text "altdpram2" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ACP_CLUT_RAM" (rect 8 192 120 207)(font "Arial" ))
+	(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ACP_CLUT_RAM" (rect 8 192 94 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[7..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[7..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[7..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[7..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -5577,82 +5471,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 1832 3704 2040)
-	(text "altdpram1" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "FALCON_CLUT_BLUE" (rect 8 192 156 207)(font "Arial" ))
+	(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "FALCON_CLUT_BLUE" (rect 8 192 121 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[5..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[5..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[5..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[5..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -5729,82 +5623,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 1416 3704 1624)
-	(text "altdpram1" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "FALCON_CLUT_RED" (rect 8 192 149 207)(font "Arial" ))
+	(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "FALCON_CLUT_RED" (rect 8 192 116 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[5..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[5..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[5..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[5..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -5881,82 +5775,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 1624 3704 1832)
-	(text "altdpram1" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "FALCON_CLUT_GREEN" (rect 8 192 169 207)(font "Arial" ))
+	(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "FALCON_CLUT_GREEN" (rect 8 192 131 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[5..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[5..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[5..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[5..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[5..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[5..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -6033,82 +5927,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 2064 3704 2272)
-	(text "altdpram2" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ACP_CLUT_RAM55" (rect 8 192 136 207)(font "Arial" ))
+	(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ACP_CLUT_RAM55" (rect 8 192 105 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[7..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[7..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[7..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[7..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[7..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[7..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[7..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[7..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[7..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "256 Word(s)" (rect 136 58 151 138)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "256 Word(s)" (rect 136 58 148 118)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -6185,82 +6079,82 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 3448 1192 3704 1400)
-	(text "altdpram0" (rect 100 1 183 20)(font "Arial" (font_size 10)))
-	(text "ST_CLUT_BLUE" (rect 8 192 117 207)(font "Arial" ))
+	(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "ST_CLUT_BLUE" (rect 8 192 89 204)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data_a[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_a[2..0]" (rect 4 19 85 35)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 4 19 71 33)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 112 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "address_a[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_a[3..0]" (rect 4 35 110 51)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 4 35 93 49)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 112 48)(line_width 3))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "wren_a" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_a" (rect 4 51 52 67)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 48 65)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 112 64)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "data_b[2..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data_b[2..0]" (rect 4 83 85 99)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 4 83 71 97)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 112 96)(line_width 3))
 	)
 	(port
 		(pt 0 112)
 		(input)
-		(text "address_b[3..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "address_b[3..0]" (rect 4 99 110 115)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 4 99 93 113)(font "Arial" (font_size 8)))
 		(line (pt 0 112)(pt 112 112)(line_width 3))
 	)
 	(port
 		(pt 0 128)
 		(input)
-		(text "wren_b" (rect 0 0 48 16)(font "Arial" (font_size 8)))
-		(text "wren_b" (rect 4 115 52 131)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 48 129)(font "Arial" (font_size 8)))
 		(line (pt 0 128)(pt 112 128)(line_width 1))
 	)
 	(port
 		(pt 0 160)
 		(input)
-		(text "clock_a" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_a" (rect 4 147 57 163)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 47 161)(font "Arial" (font_size 8)))
 		(line (pt 0 160)(pt 176 160)(line_width 1))
 	)
 	(port
 		(pt 0 176)
 		(input)
-		(text "clock_b" (rect 0 0 53 16)(font "Arial" (font_size 8)))
-		(text "clock_b" (rect 4 163 57 179)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 47 177)(font "Arial" (font_size 8)))
 		(line (pt 0 176)(pt 181 176)(line_width 1))
 	)
 	(port
 		(pt 256 32)
 		(output)
-		(text "q_a[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_a[2..0]" (rect 211 19 271 35)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 211 19 260 33)(font "Arial" (font_size 8)))
 		(line (pt 256 32)(pt 192 32)(line_width 3))
 	)
 	(port
 		(pt 256 96)
 		(output)
-		(text "q_b[2..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q_b[2..0]" (rect 211 83 271 99)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 211 83 260 97)(font "Arial" (font_size 8)))
 		(line (pt 256 96)(pt 192 96)(line_width 3))
 	)
 	(drawing
-		(text "16 Word(s)" (rect 136 61 151 132)(font "Arial" )(vertical))
-		(text "RAM" (rect 149 74 164 103)(font "Arial" )(vertical))
-		(text "Block Type: AUTO" (rect 41 188 155 203)(font "Arial" ))
+		(text "16 Word(s)" (rect 136 61 148 115)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 97)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 133 200)(font "Arial" ))
 		(line (pt 128 24)(pt 168 24)(line_width 1))
 		(line (pt 168 24)(pt 168 144)(line_width 1))
 		(line (pt 168 144)(pt 128 144)(line_width 1))
@@ -6337,48 +6231,48 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2000 1368 2168 1480)
-	(text "lpm_muxDZ" (rect 54 2 153 21)(font "Arial" (font_size 10)))
-	(text "inst62" (rect 8 96 48 111)(font "Arial" ))
+	(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
+	(text "inst62" (rect 8 96 37 108)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data1x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 27 101 43)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 27 85 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 80 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data0x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 43 101 59)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 43 85 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 80 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 4 59 40 75)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 59 33 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 80 72)(line_width 1))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "clken" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clken" (rect 4 75 40 91)(font "Arial" (font_size 8)))
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 75 33 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 80 88)(line_width 1))
 	)
 	(port
 		(pt 88 112)
 		(input)
-		(text "sel" (rect 0 0 20 16)(font "Arial" (font_size 8)))
-		(text "sel" (rect 92 99 112 115)(font "Arial" (font_size 8)))
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 92 99 108 113)(font "Arial" (font_size 8)))
 		(line (pt 88 112)(pt 88 100)(line_width 1))
 	)
 	(port
 		(pt 168 64)
 		(output)
-		(text "result[127..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 102 51 191 67)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 51 176 65)(font "Arial" (font_size 8)))
 		(line (pt 168 64)(pt 96 64)(line_width 3))
 	)
 	(drawing
@@ -6392,27 +6286,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1536 1408 1600 1456)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst65" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst65" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -6424,27 +6318,27 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1856 1272 1920 1320)
-	(text "AND2" (rect 1 0 32 13)(font "Arial" (font_size 6)))
-	(text "inst67" (rect 3 37 43 52)(font "Arial" ))
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst67" (rect 3 37 32 49)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
-		(text "IN1" (rect 2 7 26 23)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 14 16)(line_width 1))
 	)
 	(port
 		(pt 0 32)
 		(input)
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
-		(text "IN2" (rect 2 23 26 39)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
 		(line (pt 0 32)(pt 14 32)(line_width 1))
 	)
 	(port
 		(pt 64 24)
 		(output)
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 48 15 72 31)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
 		(line (pt 42 24)(pt 64 24)(line_width 1))
 	)
 	(drawing
@@ -6456,20 +6350,20 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1456 1424 1504 1456)
-	(text "NOT" (rect 1 0 26 13)(font "Arial" (font_size 6)))
-	(text "inst69" (rect 3 21 43 36)(font "Arial" ))
+	(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
+	(text "inst69" (rect 3 21 32 33)(font "Arial" ))
 	(port
 		(pt 0 16)
 		(input)
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
-		(text "IN" (rect 2 7 18 23)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
+		(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
 		(line (pt 0 16)(pt 13 16)(line_width 1))
 	)
 	(port
 		(pt 48 16)
 		(output)
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
-		(text "OUT" (rect 32 7 56 23)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
 		(line (pt 39 16)(pt 48 16)(line_width 1))
 	)
 	(drawing
@@ -6481,38 +6375,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1160 1104 1304 1200)
-	(text "lpm_ff6" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst71" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst71" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 101 42)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 83 50 143 66)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 50 132 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -6523,38 +6417,38 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1400 1128 1544 1224)
-	(text "lpm_ff6" (rect 52 1 114 20)(font "Arial" (font_size 10)))
-	(text "inst94" (rect 8 80 48 95)(font "Arial" ))
+	(text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst94" (rect 8 80 37 92)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 101 42)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 42 62 58)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 55 56)(font "Arial" (font_size 8)))
 		(line (pt 0 48)(pt 16 48)(line_width 1))
 	)
 	(port
 		(pt 0 64)
 		(input)
-		(text "enable" (rect 0 0 44 16)(font "Arial" (font_size 8)))
-		(text "enable" (rect 20 58 64 74)(font "Arial" (font_size 8)))
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 57 72)(font "Arial" (font_size 8)))
 		(line (pt 0 64)(pt 16 64)(line_width 1))
 	)
 	(port
 		(pt 144 56)
 		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 83 50 143 66)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 50 132 64)(font "Arial" (font_size 8)))
 		(line (pt 144 56)(pt 128 56)(line_width 3))
 	)
 	(drawing
-		(text "DFF" (rect 109 17 136 32)(font "Arial" ))
+		(text "DFF" (rect 109 17 131 29)(font "Arial" ))
 		(line (pt 16 16)(pt 128 16)(line_width 1))
 		(line (pt 128 16)(pt 128 80)(line_width 1))
 		(line (pt 128 80)(pt 16 80)(line_width 1))
@@ -6565,132 +6459,132 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 1800 816 1968 1120)
-	(text "lpm_muxVDM" (rect 47 2 163 21)(font "Arial" (font_size 10)))
-	(text "inst100" (rect 8 288 56 303)(font "Arial" ))
+	(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
+	(text "inst100" (rect 8 288 43 300)(font "Arial" ))
 	(port
 		(pt 0 40)
 		(input)
-		(text "data15x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data15x[127..0]" (rect 4 27 110 43)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 27 92 41)(font "Arial" (font_size 8)))
 		(line (pt 0 40)(pt 80 40)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "data14x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data14x[127..0]" (rect 4 43 110 59)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 43 92 57)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 80 56)(line_width 3))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "data13x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data13x[127..0]" (rect 4 59 110 75)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 59 92 73)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 80 72)(line_width 3))
 	)
 	(port
 		(pt 0 88)
 		(input)
-		(text "data12x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data12x[127..0]" (rect 4 75 110 91)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 75 92 89)(font "Arial" (font_size 8)))
 		(line (pt 0 88)(pt 80 88)(line_width 3))
 	)
 	(port
 		(pt 0 104)
 		(input)
-		(text "data11x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data11x[127..0]" (rect 4 91 110 107)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 91 92 105)(font "Arial" (font_size 8)))
 		(line (pt 0 104)(pt 80 104)(line_width 3))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "data10x[127..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
-		(text "data10x[127..0]" (rect 4 107 110 123)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 107 92 121)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 80 120)(line_width 3))
 	)
 	(port
 		(pt 0 136)
 		(input)
-		(text "data9x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data9x[127..0]" (rect 4 123 101 139)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 123 85 137)(font "Arial" (font_size 8)))
 		(line (pt 0 136)(pt 80 136)(line_width 3))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "data8x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data8x[127..0]" (rect 4 139 101 155)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 139 85 153)(font "Arial" (font_size 8)))
 		(line (pt 0 152)(pt 80 152)(line_width 3))
 	)
 	(port
 		(pt 0 168)
 		(input)
-		(text "data7x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data7x[127..0]" (rect 4 155 101 171)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 155 85 169)(font "Arial" (font_size 8)))
 		(line (pt 0 168)(pt 80 168)(line_width 3))
 	)
 	(port
 		(pt 0 184)
 		(input)
-		(text "data6x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data6x[127..0]" (rect 4 171 101 187)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 171 85 185)(font "Arial" (font_size 8)))
 		(line (pt 0 184)(pt 80 184)(line_width 3))
 	)
 	(port
 		(pt 0 200)
 		(input)
-		(text "data5x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data5x[127..0]" (rect 4 187 101 203)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 187 85 201)(font "Arial" (font_size 8)))
 		(line (pt 0 200)(pt 80 200)(line_width 3))
 	)
 	(port
 		(pt 0 216)
 		(input)
-		(text "data4x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data4x[127..0]" (rect 4 203 101 219)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 203 85 217)(font "Arial" (font_size 8)))
 		(line (pt 0 216)(pt 80 216)(line_width 3))
 	)
 	(port
 		(pt 0 232)
 		(input)
-		(text "data3x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data3x[127..0]" (rect 4 219 101 235)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 219 85 233)(font "Arial" (font_size 8)))
 		(line (pt 0 232)(pt 80 232)(line_width 3))
 	)
 	(port
 		(pt 0 248)
 		(input)
-		(text "data2x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data2x[127..0]" (rect 4 235 101 251)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 235 85 249)(font "Arial" (font_size 8)))
 		(line (pt 0 248)(pt 80 248)(line_width 3))
 	)
 	(port
 		(pt 0 264)
 		(input)
-		(text "data1x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data1x[127..0]" (rect 4 251 101 267)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 251 85 265)(font "Arial" (font_size 8)))
 		(line (pt 0 264)(pt 80 264)(line_width 3))
 	)
 	(port
 		(pt 0 280)
 		(input)
-		(text "data0x[127..0]" (rect 0 0 97 16)(font "Arial" (font_size 8)))
-		(text "data0x[127..0]" (rect 4 267 101 283)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 267 85 281)(font "Arial" (font_size 8)))
 		(line (pt 0 280)(pt 80 280)(line_width 3))
 	)
 	(port
 		(pt 88 304)
 		(input)
-		(text "sel[3..0]" (rect 0 0 55 16)(font "Arial" (font_size 8)))
-		(text "sel[3..0]" (rect 92 291 147 307)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 92 291 136 305)(font "Arial" (font_size 8)))
 		(line (pt 88 304)(pt 88 292)(line_width 3))
 	)
 	(port
 		(pt 168 160)
 		(output)
-		(text "result[127..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
-		(text "result[127..0]" (rect 102 147 191 163)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 147 176 161)(font "Arial" (font_size 8)))
 		(line (pt 168 160)(pt 96 160)(line_width 3))
 	)
 	(drawing
@@ -6702,53 +6596,53 @@ applicable agreement for further details.
 )
 (symbol
 	(rect 2072 1176 2232 1320)
-	(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10)))
-	(text "inst63" (rect 8 125 48 140)(font "Arial" ))
+	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
+	(text "inst63" (rect 8 128 37 140)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 24 101 40)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "wrreq" (rect 20 48 56 64)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
-		(text "rdreq" (rect 20 64 54 80)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 66 50 80)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 88 62 104)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 90 55 104)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 112 44 128)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 160 32)
 		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 90 24 150 40)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
 		(line (pt 160 32)(pt 144 32)(line_width 3))
 	)
 	(drawing
-		(text "(ack)" (rect 51 67 82 82)(font "Arial" ))
-		(text "128 bits x 128 words" (rect 31 114 164 129)(font "Arial" ))
+		(text "(ack)" (rect 51 67 75 79)(font "Arial" ))
+		(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
 		(line (pt 16 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 128)(line_width 1))
 		(line (pt 144 128)(pt 16 128)(line_width 1))
@@ -6758,9 +6652,83 @@ applicable agreement for further details.
 		(line (pt 22 96)(pt 16 102)(line_width 1))
 	)
 )
+(symbol
+	(rect 1712 1328 1872 1496)
+	(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 57 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 50 112)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 53 128)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 41 152)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "wrusedw[10..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[10..0]" (rect 63 66 155 80)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 90 148 104)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(drawing
+		(text "128 bits x 2048 words" (rect 53 140 160 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
 (block
 	(rect 1664 1664 2016 2600)
-	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 211 21)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 200 937)(font "Arial" ))	(block_io "nRSTO" (input))
+	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" ))	(block_io "nRSTO" (input))
 	(block_io "MAIN_CLK" (input))
 	(block_io "nFB_CS1" (input))
 	(block_io "nFB_CS2" (input))
@@ -7008,7 +6976,7 @@ applicable agreement for further details.
 )
 (block
 	(rect 296 1872 560 2536)
-	(text "DDR_CTR" (rect 5 5 74 21)(font "Arial" (font_size 8)))	(text "DDR_CTR" (rect 5 650 74 665)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
+	(text "DDR_CTR" (rect 5 5 60 19)(font "Arial" (font_size 8)))	(text "DDR_CTR" (rect 5 650 58 662)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
 	(block_io "nFB_CS1" (input))
 	(block_io "nFB_CS2" (input))
 	(block_io "nFB_CS3" (input))
@@ -7026,8 +6994,8 @@ applicable agreement for further details.
 	(block_io "BLITTER_WR" (input))
 	(block_io "DDRCLK0" (input))
 	(block_io "CLK33M" (input))
-	(block_io "FIFO_MW[8..0]" (input))
 	(block_io "CLR_FIFO" (input))
+	(block_io "FIFO_MW[10..0]" (input))
 	(block_io "VA[12..0]" (output))
 	(block_io "nVWE" (output))
 	(block_io "nVRAS" (output))
@@ -7206,7 +7174,7 @@ applicable agreement for further details.
 )
 (block
 	(rect 296 2552 568 3040)
-	(text "BLITTER" (rect 5 5 65 21)(font "Arial" (font_size 8)))	(text "BLITTER" (rect 5 474 62 489)(font "Arial" ))	(block_io "nRSTO" (input))
+	(text "BLITTER" (rect 5 5 52 19)(font "Arial" (font_size 8)))	(text "BLITTER" (rect 5 474 48 486)(font "Arial" ))	(block_io "nRSTO" (input))
 	(block_io "MAIN_CLK" (input))
 	(block_io "FB_ALE" (input))
 	(block_io "nFB_WR" (input))
@@ -7220,15 +7188,16 @@ applicable agreement for further details.
 	(block_io "nFB_CS2" (input))
 	(block_io "nFB_CS3" (input))
 	(block_io "DDRCLK0" (input))
-	(block_io "BLITTER_DIN[127..0]" (input))
 	(block_io "BLITTER_DACK[4..0]" (input))
 	(block_io "SR_BLITTER_DACK" (input))
+	(block_io "VDP_IN[63..0]" (input))
 	(block_io "BLITTER_RUN" (output))
 	(block_io "BLITTER_DOUT[127..0]" (output))
 	(block_io "BLITTER_ADR[31..0]" (output))
 	(block_io "BLITTER_SIG" (output))
 	(block_io "BLITTER_WR" (output))
 	(block_io "BLITTER_TA" (output))
+	(block_io "BLITTER_INT" (output))
 	(block_io "FB_AD[31..0]" (bidir))
 	(mapper
 		(pt 272 176)
@@ -7326,19 +7295,23 @@ applicable agreement for further details.
 		(pt 0 440)
 		(bidir)
 		)
+	(mapper
+		(pt 272 456)
+		(bidir)
+		)
 )
 (connector
-	(text "CLUT_ADR0" (rect 2786 1272 2869 1287)(font "Arial" ))
+	(text "CLUT_ADR0" (rect 2786 1272 2849 1284)(font "Arial" ))
 	(pt 2776 1288)
 	(pt 2848 1288)
 )
 (connector
-	(text "CLUT_ADR3" (rect 3082 1744 3165 1759)(font "Arial" ))
+	(text "CLUT_ADR3" (rect 3082 1744 3145 1756)(font "Arial" ))
 	(pt 3072 1760)
 	(pt 3144 1760)
 )
 (connector
-	(text "CLUT_ADR2" (rect 3082 1600 3165 1615)(font "Arial" ))
+	(text "CLUT_ADR2" (rect 3082 1600 3145 1612)(font "Arial" ))
 	(pt 3072 1616)
 	(pt 3144 1616)
 )
@@ -7351,91 +7324,91 @@ applicable agreement for further details.
 	(pt 2984 1688)
 )
 (connector
-	(text "FB_AD[31..0]" (rect 802 1120 885 1135)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 802 1120 869 1132)(font "Arial" ))
 	(pt 792 1136)
 	(pt 912 1136)
 	(bus)
 )
 (connector
-	(text "FIFO_D[127..112]" (rect 2546 1248 2659 1263)(font "Arial" ))
+	(text "FIFO_D[127..112]" (rect 2546 1248 2635 1260)(font "Arial" ))
 	(pt 2536 1264)
 	(pt 2632 1264)
 	(bus)
 )
 (connector
-	(text "FIFO_D[111..96]" (rect 2546 1408 2651 1423)(font "Arial" ))
+	(text "FIFO_D[111..96]" (rect 2546 1408 2629 1420)(font "Arial" ))
 	(pt 2536 1424)
 	(pt 2632 1424)
 	(bus)
 )
 (connector
-	(text "FIFO_D[95..80]" (rect 2546 1568 2642 1583)(font "Arial" ))
+	(text "FIFO_D[95..80]" (rect 2546 1568 2623 1580)(font "Arial" ))
 	(pt 2536 1584)
 	(pt 2632 1584)
 	(bus)
 )
 (connector
-	(text "FIFO_D[79..64]" (rect 2546 1728 2642 1743)(font "Arial" ))
+	(text "FIFO_D[79..64]" (rect 2546 1728 2623 1740)(font "Arial" ))
 	(pt 2536 1744)
 	(pt 2632 1744)
 	(bus)
 )
 (connector
-	(text "FIFO_D[63..48]" (rect 2546 1888 2642 1903)(font "Arial" ))
+	(text "FIFO_D[63..48]" (rect 2546 1888 2623 1900)(font "Arial" ))
 	(pt 2536 1904)
 	(pt 2632 1904)
 	(bus)
 )
 (connector
-	(text "FIFO_D[47..32]" (rect 2546 2048 2642 2063)(font "Arial" ))
+	(text "FIFO_D[47..32]" (rect 2546 2048 2623 2060)(font "Arial" ))
 	(pt 2536 2064)
 	(pt 2632 2064)
 	(bus)
 )
 (connector
-	(text "FIFO_D[31..16]" (rect 2546 2208 2642 2223)(font "Arial" ))
+	(text "FIFO_D[31..16]" (rect 2546 2208 2623 2220)(font "Arial" ))
 	(pt 2536 2224)
 	(pt 2632 2224)
 	(bus)
 )
 (connector
-	(text "FIFO_D[15..0]" (rect 2546 2368 2634 2383)(font "Arial" ))
+	(text "FIFO_D[15..0]" (rect 2546 2368 2617 2380)(font "Arial" ))
 	(pt 2536 2384)
 	(pt 2632 2384)
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 1280 2621 1295)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 1280 2602 1292)(font "Arial" ))
 	(pt 2632 1296)
 	(pt 2536 1296)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 1440 2621 1455)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 1440 2602 1452)(font "Arial" ))
 	(pt 2632 1456)
 	(pt 2536 1456)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 1600 2621 1615)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 1600 2602 1612)(font "Arial" ))
 	(pt 2632 1616)
 	(pt 2536 1616)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 1760 2621 1775)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 1760 2602 1772)(font "Arial" ))
 	(pt 2632 1776)
 	(pt 2536 1776)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 2080 2621 2095)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 2080 2602 2092)(font "Arial" ))
 	(pt 2632 2096)
 	(pt 2536 2096)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 2240 2621 2255)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 2240 2602 2252)(font "Arial" ))
 	(pt 2632 2256)
 	(pt 2536 2256)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 2400 2621 2415)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 2400 2602 2412)(font "Arial" ))
 	(pt 2632 2416)
 	(pt 2536 2416)
 )
@@ -7464,62 +7437,62 @@ applicable agreement for further details.
 	(pt 2632 2112)
 )
 (connector
-	(text "COLOR2" (rect 2330 1344 2389 1359)(font "Arial" ))
+	(text "COLOR2" (rect 2330 1344 2374 1356)(font "Arial" ))
 	(pt 2392 1360)
 	(pt 2320 1360)
 )
 (connector
-	(text "COLOR4" (rect 2330 1328 2389 1343)(font "Arial" ))
+	(text "COLOR4" (rect 2330 1328 2374 1340)(font "Arial" ))
 	(pt 2392 1344)
 	(pt 2320 1344)
 )
 (connector
-	(text "COLOR2" (rect 2330 1504 2389 1519)(font "Arial" ))
+	(text "COLOR2" (rect 2330 1504 2374 1516)(font "Arial" ))
 	(pt 2392 1520)
 	(pt 2320 1520)
 )
 (connector
-	(text "COLOR4" (rect 2330 1488 2389 1503)(font "Arial" ))
+	(text "COLOR4" (rect 2330 1488 2374 1500)(font "Arial" ))
 	(pt 2392 1504)
 	(pt 2320 1504)
 )
 (connector
-	(text "COLOR2" (rect 2330 1664 2389 1679)(font "Arial" ))
+	(text "COLOR2" (rect 2330 1664 2374 1676)(font "Arial" ))
 	(pt 2392 1680)
 	(pt 2320 1680)
 )
 (connector
-	(text "COLOR4" (rect 2330 1648 2389 1663)(font "Arial" ))
+	(text "COLOR4" (rect 2330 1648 2374 1660)(font "Arial" ))
 	(pt 2392 1664)
 	(pt 2320 1664)
 )
 (connector
-	(text "COLOR2" (rect 2330 1824 2389 1839)(font "Arial" ))
+	(text "COLOR2" (rect 2330 1824 2374 1836)(font "Arial" ))
 	(pt 2392 1840)
 	(pt 2320 1840)
 )
 (connector
-	(text "COLOR4" (rect 2330 1808 2389 1823)(font "Arial" ))
+	(text "COLOR4" (rect 2330 1808 2374 1820)(font "Arial" ))
 	(pt 2392 1824)
 	(pt 2320 1824)
 )
 (connector
-	(text "COLOR2" (rect 2330 1984 2389 1999)(font "Arial" ))
+	(text "COLOR2" (rect 2330 1984 2374 1996)(font "Arial" ))
 	(pt 2392 2000)
 	(pt 2320 2000)
 )
 (connector
-	(text "COLOR4" (rect 2330 1968 2389 1983)(font "Arial" ))
+	(text "COLOR4" (rect 2330 1968 2374 1980)(font "Arial" ))
 	(pt 2392 1984)
 	(pt 2320 1984)
 )
 (connector
-	(text "COLOR2" (rect 2330 2144 2389 2159)(font "Arial" ))
+	(text "COLOR2" (rect 2330 2144 2374 2156)(font "Arial" ))
 	(pt 2392 2160)
 	(pt 2320 2160)
 )
 (connector
-	(text "COLOR4" (rect 2330 2128 2389 2143)(font "Arial" ))
+	(text "COLOR4" (rect 2330 2128 2374 2140)(font "Arial" ))
 	(pt 2392 2144)
 	(pt 2320 2144)
 )
@@ -7560,147 +7533,147 @@ applicable agreement for further details.
 	(pt 2304 2064)
 )
 (connector
-	(text "CLUT_ADR2A" (rect 2786 1592 2878 1607)(font "Arial" ))
+	(text "CLUT_ADR2A" (rect 2786 1592 2856 1604)(font "Arial" ))
 	(pt 2776 1608)
 	(pt 3008 1608)
 )
 (connector
-	(text "CLUT_ADR3A" (rect 2786 1752 2878 1767)(font "Arial" ))
+	(text "CLUT_ADR3A" (rect 2786 1752 2856 1764)(font "Arial" ))
 	(pt 3008 1768)
 	(pt 2776 1768)
 )
 (connector
-	(text "CLUT_ADR7A" (rect 2330 2080 2422 2095)(font "Arial" ))
+	(text "CLUT_ADR7A" (rect 2330 2080 2400 2092)(font "Arial" ))
 	(pt 2320 2096)
 	(pt 2392 2096)
 )
 (connector
-	(text "CLUT_ADR6A" (rect 2330 2064 2422 2079)(font "Arial" ))
+	(text "CLUT_ADR6A" (rect 2330 2064 2400 2076)(font "Arial" ))
 	(pt 2320 2080)
 	(pt 2392 2080)
 )
 (connector
-	(text "CLUT_ADR6A" (rect 2330 1920 2422 1935)(font "Arial" ))
+	(text "CLUT_ADR6A" (rect 2330 1920 2400 1932)(font "Arial" ))
 	(pt 2320 1936)
 	(pt 2392 1936)
 )
 (connector
-	(text "CLUT_ADR5A" (rect 2330 1904 2422 1919)(font "Arial" ))
+	(text "CLUT_ADR5A" (rect 2330 1904 2400 1916)(font "Arial" ))
 	(pt 2320 1920)
 	(pt 2392 1920)
 )
 (connector
-	(text "CLUT_ADR7A" (rect 2330 1776 2422 1791)(font "Arial" ))
+	(text "CLUT_ADR7A" (rect 2330 1776 2400 1788)(font "Arial" ))
 	(pt 2320 1792)
 	(pt 2392 1792)
 )
 (connector
-	(text "CLUT_ADR5A" (rect 2330 1760 2422 1775)(font "Arial" ))
+	(text "CLUT_ADR5A" (rect 2330 1760 2400 1772)(font "Arial" ))
 	(pt 2320 1776)
 	(pt 2392 1776)
 )
 (connector
-	(text "CLUT_ADR4A" (rect 2330 1744 2422 1759)(font "Arial" ))
+	(text "CLUT_ADR4A" (rect 2330 1744 2400 1756)(font "Arial" ))
 	(pt 2320 1760)
 	(pt 2392 1760)
 )
 (connector
-	(text "CLUT_ADR6A" (rect 2330 1616 2422 1631)(font "Arial" ))
+	(text "CLUT_ADR6A" (rect 2330 1616 2400 1628)(font "Arial" ))
 	(pt 2320 1632)
 	(pt 2392 1632)
 )
 (connector
-	(text "CLUT_ADR4A" (rect 2330 1600 2422 1615)(font "Arial" ))
+	(text "CLUT_ADR4A" (rect 2330 1600 2400 1612)(font "Arial" ))
 	(pt 2320 1616)
 	(pt 2392 1616)
 )
 (connector
-	(text "CLUT_ADR3A" (rect 2330 1584 2422 1599)(font "Arial" ))
+	(text "CLUT_ADR3A" (rect 2330 1584 2400 1596)(font "Arial" ))
 	(pt 2320 1600)
 	(pt 2392 1600)
 )
 (connector
-	(text "CLUT_ADR5A" (rect 2330 1456 2422 1471)(font "Arial" ))
+	(text "CLUT_ADR5A" (rect 2330 1456 2400 1468)(font "Arial" ))
 	(pt 2320 1472)
 	(pt 2392 1472)
 )
 (connector
-	(text "CLUT_ADR3A" (rect 2330 1440 2422 1455)(font "Arial" ))
+	(text "CLUT_ADR3A" (rect 2330 1440 2400 1452)(font "Arial" ))
 	(pt 2320 1456)
 	(pt 2392 1456)
 )
 (connector
-	(text "CLUT_ADR4A" (rect 2330 1296 2422 1311)(font "Arial" ))
+	(text "CLUT_ADR4A" (rect 2330 1296 2400 1308)(font "Arial" ))
 	(pt 2320 1312)
 	(pt 2392 1312)
 )
 (connector
-	(text "CLUT_ADR2A" (rect 2330 1280 2422 1295)(font "Arial" ))
+	(text "CLUT_ADR2A" (rect 2330 1280 2400 1292)(font "Arial" ))
 	(pt 2320 1296)
 	(pt 2392 1296)
 )
 (connector
-	(text "CLUT_ADR2A" (rect 2330 1424 2422 1439)(font "Arial" ))
+	(text "CLUT_ADR2A" (rect 2330 1424 2400 1436)(font "Arial" ))
 	(pt 2392 1440)
 	(pt 2320 1440)
 )
 (connector
-	(text "CLUT_ADR7A" (rect 2570 2256 2662 2271)(font "Arial" ))
+	(text "CLUT_ADR7A" (rect 2570 2256 2640 2268)(font "Arial" ))
 	(pt 2560 2272)
 	(pt 2632 2272)
 )
 (connector
-	(text "CLUT_ADR0" (rect 2554 2416 2637 2431)(font "Arial" ))
+	(text "CLUT_ADR0" (rect 2554 2416 2617 2428)(font "Arial" ))
 	(pt 2632 2432)
 	(pt 2544 2432)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2546 1920 2621 1935)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2546 1920 2602 1932)(font "Arial" ))
 	(pt 2632 1936)
 	(pt 2536 1936)
 )
 (connector
-	(text "CLUT_ADR4A" (rect 2794 1912 2886 1927)(font "Arial" ))
+	(text "CLUT_ADR4A" (rect 2794 1912 2864 1924)(font "Arial" ))
 	(pt 2776 1928)
 	(pt 2904 1928)
 )
 (connector
-	(text "CLUT_ADR5A" (rect 2786 2072 2878 2087)(font "Arial" ))
+	(text "CLUT_ADR5A" (rect 2786 2072 2856 2084)(font "Arial" ))
 	(pt 2776 2088)
 	(pt 2904 2088)
 )
 (connector
-	(text "CLUT_ADR6A" (rect 2794 2232 2886 2247)(font "Arial" ))
+	(text "CLUT_ADR6A" (rect 2794 2232 2864 2244)(font "Arial" ))
 	(pt 2776 2248)
 	(pt 2904 2248)
 )
 (connector
-	(text "CLUT_ADR7A" (rect 2794 2392 2886 2407)(font "Arial" ))
+	(text "CLUT_ADR7A" (rect 2794 2392 2864 2404)(font "Arial" ))
 	(pt 2776 2408)
 	(pt 2904 2408)
 )
 (connector
-	(text "COLOR8" (rect 2834 1928 2893 1943)(font "Arial" ))
+	(text "COLOR8" (rect 2834 1928 2878 1940)(font "Arial" ))
 	(pt 2904 1944)
 	(pt 2824 1944)
 )
 (connector
-	(text "COLOR8" (rect 2834 2088 2893 2103)(font "Arial" ))
+	(text "COLOR8" (rect 2834 2088 2878 2100)(font "Arial" ))
 	(pt 2904 2104)
 	(pt 2824 2104)
 )
 (connector
-	(text "COLOR8" (rect 2834 2248 2893 2263)(font "Arial" ))
+	(text "COLOR8" (rect 2834 2248 2878 2260)(font "Arial" ))
 	(pt 2904 2264)
 	(pt 2824 2264)
 )
 (connector
-	(text "COLOR8" (rect 2834 2408 2893 2423)(font "Arial" ))
+	(text "COLOR8" (rect 2834 2408 2878 2420)(font "Arial" ))
 	(pt 2904 2424)
 	(pt 2824 2424)
 )
 (connector
-	(text "CLUT_ADR4" (rect 3090 1928 3173 1943)(font "Arial" ))
+	(text "CLUT_ADR4" (rect 3090 1928 3153 1940)(font "Arial" ))
 	(pt 3080 1944)
 	(pt 3152 1944)
 )
@@ -7713,17 +7686,17 @@ applicable agreement for further details.
 	(pt 3016 2144)
 )
 (connector
-	(text "CLUT_ADR5" (rect 3098 2088 3181 2103)(font "Arial" ))
+	(text "CLUT_ADR5" (rect 3098 2088 3161 2100)(font "Arial" ))
 	(pt 3088 2104)
 	(pt 3160 2104)
 )
 (connector
-	(text "CLUT_ADR7" (rect 3106 2408 3189 2423)(font "Arial" ))
+	(text "CLUT_ADR7" (rect 3106 2408 3169 2420)(font "Arial" ))
 	(pt 3096 2424)
 	(pt 3168 2424)
 )
 (connector
-	(text "CLUT_ADR6" (rect 3098 2248 3181 2263)(font "Arial" ))
+	(text "CLUT_ADR6" (rect 3098 2248 3161 2260)(font "Arial" ))
 	(pt 3088 2264)
 	(pt 3160 2264)
 )
@@ -7768,37 +7741,37 @@ applicable agreement for further details.
 	(pt 2968 2416)
 )
 (connector
-	(text "CLUT_OFF0" (rect 2938 1968 3019 1983)(font "Arial" ))
+	(text "CLUT_OFF0" (rect 2938 1968 3000 1980)(font "Arial" ))
 	(pt 2928 1984)
 	(pt 3008 1984)
 )
 (connector
-	(text "CLUT_OFF1" (rect 2946 2128 3027 2143)(font "Arial" ))
+	(text "CLUT_OFF1" (rect 2946 2128 3008 2140)(font "Arial" ))
 	(pt 2936 2144)
 	(pt 3016 2144)
 )
 (connector
-	(text "CLUT_OFF2" (rect 2946 2288 3027 2303)(font "Arial" ))
+	(text "CLUT_OFF2" (rect 2946 2288 3008 2300)(font "Arial" ))
 	(pt 2936 2304)
 	(pt 3016 2304)
 )
 (connector
-	(text "CLUT_OFF3" (rect 2954 2448 3035 2463)(font "Arial" ))
+	(text "CLUT_OFF3" (rect 2954 2448 3016 2460)(font "Arial" ))
 	(pt 2944 2464)
 	(pt 3024 2464)
 )
 (connector
-	(text "COLOR4" (rect 2834 1664 2893 1679)(font "Arial" ))
+	(text "COLOR4" (rect 2834 1664 2878 1676)(font "Arial" ))
 	(pt 2824 1680)
 	(pt 2912 1680)
 )
 (connector
-	(text "COLOR8" (rect 2834 1680 2893 1695)(font "Arial" ))
+	(text "COLOR8" (rect 2834 1680 2878 1692)(font "Arial" ))
 	(pt 2912 1696)
 	(pt 2824 1696)
 )
 (connector
-	(text "CLUT_ADR1" (rect 3082 1440 3165 1455)(font "Arial" ))
+	(text "CLUT_ADR1" (rect 3082 1440 3145 1452)(font "Arial" ))
 	(pt 3072 1456)
 	(pt 3144 1456)
 )
@@ -7815,7 +7788,7 @@ applicable agreement for further details.
 	(pt 2984 1496)
 )
 (connector
-	(text "COLOR4" (rect 2842 1480 2901 1495)(font "Arial" ))
+	(text "COLOR4" (rect 2842 1480 2886 1492)(font "Arial" ))
 	(pt 2832 1496)
 	(pt 2920 1496)
 )
@@ -7828,7 +7801,7 @@ applicable agreement for further details.
 	(pt 2912 1520)
 )
 (connector
-	(text "COLOR8" (rect 2842 1504 2901 1519)(font "Arial" ))
+	(text "COLOR8" (rect 2842 1504 2886 1516)(font "Arial" ))
 	(pt 2912 1520)
 	(pt 2832 1520)
 )
@@ -7841,94 +7814,94 @@ applicable agreement for further details.
 	(pt 2912 1488)
 )
 (connector
-	(text "COLOR2" (rect 2842 1456 2901 1471)(font "Arial" ))
+	(text "COLOR2" (rect 2842 1456 2886 1468)(font "Arial" ))
 	(pt 2912 1472)
 	(pt 2832 1472)
 )
 (connector
-	(text "CLUT_ADR1A" (rect 2786 1432 2878 1447)(font "Arial" ))
+	(text "CLUT_ADR1A" (rect 2786 1432 2856 1444)(font "Arial" ))
 	(pt 3008 1448)
 	(pt 2776 1448)
 )
 (connector
-	(text "CLUT_ADR1A" (rect 2330 1264 2422 1279)(font "Arial" ))
+	(text "CLUT_ADR1A" (rect 2330 1264 2400 1276)(font "Arial" ))
 	(pt 2320 1280)
 	(pt 2392 1280)
 )
 (connector
-	(text "FIFO_D[127..112]" (rect 2098 2680 2211 2695)(font "Arial" ))
+	(text "FIFO_D[127..112]" (rect 2098 2680 2187 2692)(font "Arial" ))
 	(pt 2088 2696)
 	(pt 2224 2696)
 	(bus)
 )
 (connector
-	(text "FIFO_D[111..96]" (rect 2098 2664 2203 2679)(font "Arial" ))
+	(text "FIFO_D[111..96]" (rect 2098 2664 2181 2676)(font "Arial" ))
 	(pt 2088 2680)
 	(pt 2224 2680)
 	(bus)
 )
 (connector
-	(text "FIFO_D[95..80]" (rect 2098 2648 2194 2663)(font "Arial" ))
+	(text "FIFO_D[95..80]" (rect 2098 2648 2175 2660)(font "Arial" ))
 	(pt 2088 2664)
 	(pt 2224 2664)
 	(bus)
 )
 (connector
-	(text "FIFO_D[79..64]" (rect 2098 2632 2194 2647)(font "Arial" ))
+	(text "FIFO_D[79..64]" (rect 2098 2632 2175 2644)(font "Arial" ))
 	(pt 2088 2648)
 	(pt 2224 2648)
 	(bus)
 )
 (connector
-	(text "FIFO_D[63..48]" (rect 2098 2616 2194 2631)(font "Arial" ))
+	(text "FIFO_D[63..48]" (rect 2098 2616 2175 2628)(font "Arial" ))
 	(pt 2088 2632)
 	(pt 2224 2632)
 	(bus)
 )
 (connector
-	(text "FIFO_D[47..32]" (rect 2098 2600 2194 2615)(font "Arial" ))
+	(text "FIFO_D[47..32]" (rect 2098 2600 2175 2612)(font "Arial" ))
 	(pt 2088 2616)
 	(pt 2224 2616)
 	(bus)
 )
 (connector
-	(text "FIFO_D[31..16]" (rect 2098 2584 2194 2599)(font "Arial" ))
+	(text "FIFO_D[31..16]" (rect 2098 2584 2175 2596)(font "Arial" ))
 	(pt 2088 2600)
 	(pt 2224 2600)
 	(bus)
 )
 (connector
-	(text "FIFO_D[15..0]" (rect 2098 2568 2186 2583)(font "Arial" ))
+	(text "FIFO_D[15..0]" (rect 2098 2568 2169 2580)(font "Arial" ))
 	(pt 2088 2584)
 	(pt 2224 2584)
 	(bus)
 )
 (connector
-	(text "FIFO_D[95..64]" (rect 1490 2744 1586 2759)(font "Arial" ))
+	(text "FIFO_D[95..64]" (rect 1490 2744 1567 2756)(font "Arial" ))
 	(pt 1616 2760)
 	(pt 1480 2760)
 	(bus)
 )
 (connector
-	(text "FIFO_D[127..96]" (rect 1490 2760 1595 2775)(font "Arial" ))
+	(text "FIFO_D[127..96]" (rect 1490 2760 1573 2772)(font "Arial" ))
 	(pt 1616 2776)
 	(pt 1480 2776)
 	(bus)
 )
 (connector
-	(text "CLUT_MUX_ADR[1..0]" (rect 1594 2824 1737 2839)(font "Arial" ))
+	(text "CLUT_MUX_ADR[1..0]" (rect 1594 2824 1706 2836)(font "Arial" ))
 	(pt 1696 2840)
 	(pt 1592 2840)
 	(bus)
 )
 (connector
-	(text "FIFO_D[63..32]" (rect 1490 2728 1586 2743)(font "Arial" ))
+	(text "FIFO_D[63..32]" (rect 1490 2728 1567 2740)(font "Arial" ))
 	(pt 1480 2744)
 	(pt 1616 2744)
 	(bus)
 )
 (connector
-	(text "FIFO_D[31..0]" (rect 1490 2712 1578 2727)(font "Arial" ))
+	(text "FIFO_D[31..0]" (rect 1490 2712 1561 2724)(font "Arial" ))
 	(pt 1480 2728)
 	(pt 1616 2728)
 	(bus)
@@ -7938,7 +7911,7 @@ applicable agreement for further details.
 	(pt 880 1592)
 )
 (connector
-	(text "FB_VDOE3" (rect 890 1576 963 1591)(font "Arial" ))
+	(text "FB_VDOE3" (rect 890 1576 946 1588)(font "Arial" ))
 	(pt 880 1592)
 	(pt 944 1592)
 )
@@ -7947,7 +7920,7 @@ applicable agreement for further details.
 	(pt 880 1472)
 )
 (connector
-	(text "FB_VDOE2" (rect 890 1456 963 1471)(font "Arial" ))
+	(text "FB_VDOE2" (rect 890 1456 946 1468)(font "Arial" ))
 	(pt 880 1472)
 	(pt 944 1472)
 )
@@ -7956,7 +7929,7 @@ applicable agreement for further details.
 	(pt 880 1352)
 )
 (connector
-	(text "FB_VDOE1" (rect 890 1336 963 1351)(font "Arial" ))
+	(text "FB_VDOE1" (rect 890 1336 946 1348)(font "Arial" ))
 	(pt 880 1352)
 	(pt 944 1352)
 )
@@ -7965,7 +7938,7 @@ applicable agreement for further details.
 	(pt 880 1232)
 )
 (connector
-	(text "FB_VDOE0" (rect 890 1216 963 1231)(font "Arial" ))
+	(text "FB_VDOE0" (rect 890 1216 946 1228)(font "Arial" ))
 	(pt 880 1232)
 	(pt 944 1232)
 )
@@ -8015,128 +7988,128 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1738 2824 1813 2839)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1738 2824 1794 2836)(font "Arial" ))
 	(pt 1728 2840)
 	(pt 1808 2840)
 )
 (connector
-	(text "CLUT_MUX_ADR[3..0]" (rect 2722 2880 2865 2895)(font "Arial" ))
+	(text "CLUT_MUX_ADR[3..0]" (rect 2722 2880 2834 2892)(font "Arial" ))
 	(pt 2712 2896)
 	(pt 2904 2896)
 	(bus)
 )
 (connector
-	(text "FB_AD[31..0]" (rect 570 1904 653 1919)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 570 1904 637 1916)(font "Arial" ))
 	(pt 680 1920)
 	(pt 560 1920)
 	(bus)
 )
 (connector
-	(text "nFB_CS1" (rect 202 2040 264 2055)(font "Arial" ))
+	(text "nFB_CS1" (rect 202 2040 249 2052)(font "Arial" ))
 	(pt 192 2056)
 	(pt 296 2056)
 )
 (connector
-	(text "nFB_CS2" (rect 202 2064 264 2079)(font "Arial" ))
+	(text "nFB_CS2" (rect 202 2064 249 2076)(font "Arial" ))
 	(pt 192 2080)
 	(pt 296 2080)
 )
 (connector
-	(text "nFB_CS3" (rect 202 2088 264 2103)(font "Arial" ))
+	(text "nFB_CS3" (rect 202 2088 249 2100)(font "Arial" ))
 	(pt 192 2104)
 	(pt 296 2104)
 )
 (connector
-	(text "nFB_WR" (rect 202 2112 259 2127)(font "Arial" ))
+	(text "nFB_WR" (rect 202 2112 246 2124)(font "Arial" ))
 	(pt 192 2128)
 	(pt 296 2128)
 )
 (connector
-	(text "FB_SIZE0" (rect 202 2136 266 2151)(font "Arial" ))
+	(text "FB_SIZE0" (rect 202 2136 252 2148)(font "Arial" ))
 	(pt 192 2152)
 	(pt 296 2152)
 )
 (connector
-	(text "FB_SIZE1" (rect 202 2160 266 2175)(font "Arial" ))
+	(text "FB_SIZE1" (rect 202 2160 252 2172)(font "Arial" ))
 	(pt 192 2176)
 	(pt 296 2176)
 )
 (connector
-	(text "nFB_OE" (rect 202 2184 256 2199)(font "Arial" ))
+	(text "nFB_OE" (rect 202 2184 243 2196)(font "Arial" ))
 	(pt 192 2200)
 	(pt 296 2200)
 )
 (connector
-	(text "VA[12..0]" (rect 570 2168 625 2183)(font "Arial" ))
+	(text "VA[12..0]" (rect 570 2168 616 2180)(font "Arial" ))
 	(pt 632 2184)
 	(pt 560 2184)
 	(bus)
 )
 (connector
-	(text "nVWE" (rect 570 2192 608 2207)(font "Arial" ))
+	(text "nVWE" (rect 570 2192 600 2204)(font "Arial" ))
 	(pt 632 2208)
 	(pt 560 2208)
 )
 (connector
-	(text "nVCAS" (rect 570 2216 614 2231)(font "Arial" ))
+	(text "nVCAS" (rect 570 2216 605 2228)(font "Arial" ))
 	(pt 632 2232)
 	(pt 560 2232)
 )
 (connector
-	(text "nVRAS" (rect 570 2240 614 2255)(font "Arial" ))
+	(text "nVRAS" (rect 570 2240 605 2252)(font "Arial" ))
 	(pt 632 2256)
 	(pt 560 2256)
 )
 (connector
-	(text "nVCS" (rect 570 2264 606 2279)(font "Arial" ))
+	(text "nVCS" (rect 570 2264 598 2276)(font "Arial" ))
 	(pt 632 2280)
 	(pt 560 2280)
 )
 (connector
-	(text "VCKE" (rect 570 2288 607 2303)(font "Arial" ))
+	(text "VCKE" (rect 570 2288 599 2300)(font "Arial" ))
 	(pt 632 2304)
 	(pt 560 2304)
 )
 (connector
-	(text "MAIN_CLK" (rect 202 1944 271 1959)(font "Arial" ))
+	(text "MAIN_CLK" (rect 202 1944 256 1956)(font "Arial" ))
 	(pt 296 1960)
 	(pt 192 1960)
 )
 (connector
-	(text "FB_ALE" (rect 202 2016 253 2031)(font "Arial" ))
+	(text "FB_ALE" (rect 202 2016 242 2028)(font "Arial" ))
 	(pt 296 2032)
 	(pt 192 2032)
 )
 (connector
-	(text "FB_LE[3..0]" (rect 570 1976 644 1991)(font "Arial" ))
+	(text "FB_LE[3..0]" (rect 570 1976 629 1988)(font "Arial" ))
 	(pt 560 1992)
 	(pt 680 1992)
 	(bus)
 )
 (connector
-	(text "FB_VDOE[3..0]" (rect 570 2000 665 2015)(font "Arial" ))
+	(text "FB_VDOE[3..0]" (rect 570 2000 646 2012)(font "Arial" ))
 	(pt 560 2016)
 	(pt 680 2016)
 	(bus)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 210 1968 324 1983)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 210 1968 298 1980)(font "Arial" ))
 	(pt 200 1984)
 	(pt 296 1984)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 202 1992 296 2007)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 202 1992 277 2004)(font "Arial" ))
 	(pt 192 2008)
 	(pt 296 2008)
 	(bus)
 )
 (connector
-	(text "nRSTO" (rect 202 1896 249 1911)(font "Arial" ))
+	(text "nRSTO" (rect 202 1896 237 1908)(font "Arial" ))
 	(pt 192 1912)
 	(pt 296 1912)
 )
 (connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 334 2255)(font "Arial" ))
+	(text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 301 2252)(font "Arial" ))
 	(pt 296 2256)
 	(pt 168 2256)
 	(bus)
@@ -8162,42 +8135,42 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "FB_LE0" (rect 826 1664 877 1679)(font "Arial" ))
+	(text "FB_LE0" (rect 826 1664 864 1676)(font "Arial" ))
 	(pt 920 1680)
 	(pt 816 1680)
 )
 (connector
-	(text "FB_LE1" (rect 834 1808 885 1823)(font "Arial" ))
+	(text "FB_LE1" (rect 834 1808 872 1820)(font "Arial" ))
 	(pt 920 1824)
 	(pt 824 1824)
 )
 (connector
-	(text "FB_LE2" (rect 834 1944 885 1959)(font "Arial" ))
+	(text "FB_LE2" (rect 834 1944 872 1956)(font "Arial" ))
 	(pt 920 1960)
 	(pt 824 1960)
 )
 (connector
-	(text "FB_LE3" (rect 834 2080 885 2095)(font "Arial" ))
+	(text "FB_LE3" (rect 834 2080 872 2092)(font "Arial" ))
 	(pt 920 2096)
 	(pt 824 2096)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 834 1648 948 1663)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 834 1648 922 1660)(font "Arial" ))
 	(pt 824 1664)
 	(pt 920 1664)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 834 1792 948 1807)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 834 1792 922 1804)(font "Arial" ))
 	(pt 824 1808)
 	(pt 920 1808)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 834 1928 948 1943)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 834 1928 922 1940)(font "Arial" ))
 	(pt 824 1944)
 	(pt 920 1944)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 834 2064 948 2079)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 834 2064 922 2076)(font "Arial" ))
 	(pt 824 2080)
 	(pt 920 2080)
 )
@@ -8227,12 +8200,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "FIFO_RDE" (rect 1450 1408 1519 1423)(font "Arial" ))
+	(text "FIFO_RDE" (rect 1450 1408 1505 1420)(font "Arial" ))
 	(pt 1440 1424)
 	(pt 1536 1424)
 )
 (connector
-	(text "VDP_IN[63..32]" (rect 1114 1392 1211 1407)(font "Arial" ))
+	(text "VDP_IN[63..32]" (rect 1114 1392 1191 1404)(font "Arial" ))
 	(pt 1104 1408)
 	(pt 1192 1408)
 	(bus)
@@ -8274,22 +8247,22 @@ applicable agreement for further details.
 	(pt 1384 2992)
 )
 (connector
-	(text "VDQS0" (rect 1418 2840 1465 2855)(font "Arial" ))
+	(text "VDQS0" (rect 1418 2840 1454 2852)(font "Arial" ))
 	(pt 1408 2856)
 	(pt 1520 2856)
 )
 (connector
-	(text "VDQS1" (rect 1418 2888 1465 2903)(font "Arial" ))
+	(text "VDQS1" (rect 1418 2888 1454 2900)(font "Arial" ))
 	(pt 1408 2904)
 	(pt 1520 2904)
 )
 (connector
-	(text "VDQS2" (rect 1418 2936 1465 2951)(font "Arial" ))
+	(text "VDQS2" (rect 1418 2936 1454 2948)(font "Arial" ))
 	(pt 1408 2952)
 	(pt 1520 2952)
 )
 (connector
-	(text "VDQS3" (rect 1418 2992 1465 3007)(font "Arial" ))
+	(text "VDQS3" (rect 1418 2992 1454 3004)(font "Arial" ))
 	(pt 1408 3008)
 	(pt 1520 3008)
 )
@@ -8298,161 +8271,150 @@ applicable agreement for further details.
 	(pt 1384 2984)
 )
 (connector
-	(text "FB_DDR[63..32]" (rect 1074 1936 1179 1951)(font "Arial" ))
+	(text "FB_DDR[63..32]" (rect 1074 1936 1156 1948)(font "Arial" ))
 	(pt 1064 1952)
 	(pt 1160 1952)
 	(bus)
 )
 (connector
-	(text "FB_DDR[31..0]" (rect 1074 2072 1170 2087)(font "Arial" ))
+	(text "FB_DDR[31..0]" (rect 1074 2072 1150 2084)(font "Arial" ))
 	(pt 1064 2088)
 	(pt 1160 2088)
 	(bus)
 )
 (connector
-	(text "FB_DDR[95..64]" (rect 1074 1800 1179 1815)(font "Arial" ))
+	(text "FB_DDR[95..64]" (rect 1074 1800 1156 1812)(font "Arial" ))
 	(pt 1064 1816)
 	(pt 1160 1816)
 	(bus)
 )
 (connector
-	(text "FB_DDR[127..96]" (rect 1074 1656 1187 1671)(font "Arial" ))
+	(text "FB_DDR[127..96]" (rect 1074 1656 1162 1668)(font "Arial" ))
 	(pt 1064 1672)
 	(pt 1160 1672)
 	(bus)
 )
 (connector
-	(text "BLITTER_ADR[31..0]" (rect 194 2288 328 2303)(font "Arial" ))
+	(text "BLITTER_ADR[31..0]" (rect 194 2288 299 2300)(font "Arial" ))
 	(pt 184 2304)
 	(pt 296 2304)
 	(bus)
 )
 (connector
-	(text "BLITTER_SIG" (rect 194 2312 283 2327)(font "Arial" ))
+	(text "BLITTER_SIG" (rect 194 2312 262 2324)(font "Arial" ))
 	(pt 184 2328)
 	(pt 296 2328)
 )
 (connector
-	(text "BLITTER_WR" (rect 194 2336 283 2351)(font "Arial" ))
+	(text "BLITTER_WR" (rect 194 2336 262 2348)(font "Arial" ))
 	(pt 184 2352)
 	(pt 296 2352)
 )
 (connector
-	(text "SR_FIFO_WRE" (rect 570 2072 670 2087)(font "Arial" ))
+	(text "SR_FIFO_WRE" (rect 570 2072 649 2084)(font "Arial" ))
 	(pt 648 2088)
 	(pt 560 2088)
 )
 (connector
-	(text "SR_DDR_FB" (rect 570 2312 656 2327)(font "Arial" ))
+	(text "SR_DDR_FB" (rect 570 2312 636 2324)(font "Arial" ))
 	(pt 640 2328)
 	(pt 560 2328)
 )
 (connector
-	(text "SR_FIFO_WRE" (rect 842 2280 942 2295)(font "Arial" ))
-	(pt 920 2296)
-	(pt 832 2296)
-)
-(connector
-	(text "SR_DDR_WR" (rect 570 2024 662 2039)(font "Arial" ))
+	(text "SR_DDR_WR" (rect 570 2024 640 2036)(font "Arial" ))
 	(pt 664 2040)
 	(pt 560 2040)
 )
 (connector
-	(text "SR_VDMP[7..0]" (rect 570 2336 667 2351)(font "Arial" ))
+	(text "SR_VDMP[7..0]" (rect 570 2336 647 2348)(font "Arial" ))
 	(pt 560 2352)
 	(pt 664 2352)
 	(bus)
 )
 (connector
-	(text "SR_DDRWR_D_SEL" (rect 570 2360 708 2375)(font "Arial" ))
+	(text "SR_DDRWR_D_SEL" (rect 570 2360 675 2372)(font "Arial" ))
 	(pt 560 2376)
 	(pt 664 2376)
 )
 (connector
-	(text "VDVZ[127..0]" (rect 810 2920 892 2935)(font "Arial" ))
-	(pt 800 2936)
-	(pt 888 2936)
-	(bus)
-)
-(connector
-	(text "BLITTER_SIG" (rect 578 2800 667 2815)(font "Arial" ))
+	(text "BLITTER_SIG" (rect 578 2800 646 2812)(font "Arial" ))
 	(pt 568 2816)
 	(pt 680 2816)
 )
 (connector
-	(text "BLITTER_WR" (rect 578 2824 667 2839)(font "Arial" ))
+	(text "BLITTER_WR" (rect 578 2824 646 2836)(font "Arial" ))
 	(pt 568 2840)
 	(pt 680 2840)
 )
 (connector
-	(text "nFB_CS1" (rect 202 2688 264 2703)(font "Arial" ))
+	(text "nFB_CS1" (rect 202 2688 249 2700)(font "Arial" ))
 	(pt 192 2704)
 	(pt 296 2704)
 )
 (connector
-	(text "nFB_CS2" (rect 202 2712 264 2727)(font "Arial" ))
+	(text "nFB_CS2" (rect 202 2712 249 2724)(font "Arial" ))
 	(pt 192 2728)
 	(pt 296 2728)
 )
 (connector
-	(text "nFB_CS3" (rect 202 2736 264 2751)(font "Arial" ))
+	(text "nFB_CS3" (rect 202 2736 249 2748)(font "Arial" ))
 	(pt 192 2752)
 	(pt 296 2752)
 )
 (connector
-	(text "nFB_WR" (rect 202 2760 259 2775)(font "Arial" ))
+	(text "nFB_WR" (rect 202 2760 246 2772)(font "Arial" ))
 	(pt 192 2776)
 	(pt 296 2776)
 )
 (connector
-	(text "FB_SIZE0" (rect 202 2784 266 2799)(font "Arial" ))
+	(text "FB_SIZE0" (rect 202 2784 252 2796)(font "Arial" ))
 	(pt 192 2800)
 	(pt 296 2800)
 )
 (connector
-	(text "FB_SIZE1" (rect 202 2808 266 2823)(font "Arial" ))
+	(text "FB_SIZE1" (rect 202 2808 252 2820)(font "Arial" ))
 	(pt 192 2824)
 	(pt 296 2824)
 )
 (connector
-	(text "nFB_OE" (rect 202 2832 256 2847)(font "Arial" ))
+	(text "nFB_OE" (rect 202 2832 243 2844)(font "Arial" ))
 	(pt 192 2848)
 	(pt 296 2848)
 )
 (connector
-	(text "MAIN_CLK" (rect 202 2616 271 2631)(font "Arial" ))
+	(text "MAIN_CLK" (rect 202 2616 256 2628)(font "Arial" ))
 	(pt 296 2632)
 	(pt 192 2632)
 )
 (connector
-	(text "FB_ALE" (rect 202 2664 253 2679)(font "Arial" ))
+	(text "FB_ALE" (rect 202 2664 242 2676)(font "Arial" ))
 	(pt 296 2680)
 	(pt 192 2680)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 202 2640 296 2655)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 202 2640 277 2652)(font "Arial" ))
 	(pt 192 2656)
 	(pt 296 2656)
 	(bus)
 )
 (connector
-	(text "nRSTO" (rect 202 2568 249 2583)(font "Arial" ))
+	(text "nRSTO" (rect 202 2568 237 2580)(font "Arial" ))
 	(pt 192 2584)
 	(pt 296 2584)
 )
 (connector
-	(text "FB_AD[31..0]" (rect 578 2608 661 2623)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 578 2608 645 2620)(font "Arial" ))
 	(pt 688 2624)
 	(pt 568 2624)
 	(bus)
 )
 (connector
-	(text "DDRCLK0" (rect 842 2160 910 2175)(font "Arial" ))
+	(text "DDRCLK0" (rect 842 2160 893 2172)(font "Arial" ))
 	(pt 832 2176)
 	(pt 920 2176)
 )
 (connector
-	(text "SR_DDR_FB" (rect 850 2176 936 2191)(font "Arial" ))
+	(text "SR_DDR_FB" (rect 850 2176 916 2188)(font "Arial" ))
 	(pt 920 2192)
 	(pt 840 2192)
 )
@@ -8462,43 +8424,38 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "VDP_IN[31..0]" (rect 1114 1512 1203 1527)(font "Arial" ))
+	(text "VDP_IN[31..0]" (rect 1114 1512 1185 1524)(font "Arial" ))
 	(pt 1104 1528)
 	(pt 1192 1528)
 	(bus)
 )
 (connector
-	(text "DDR_FB1" (rect 1106 1304 1172 1319)(font "Arial" ))
+	(text "DDR_FB1" (rect 1106 1304 1156 1316)(font "Arial" ))
 	(pt 1104 1320)
 	(pt 1176 1320)
 )
 (connector
-	(text "DDR_FB0" (rect 1106 1544 1172 1559)(font "Arial" ))
+	(text "DDR_FB0" (rect 1106 1544 1156 1556)(font "Arial" ))
 	(pt 1104 1560)
 	(pt 1176 1560)
 )
 (connector
-	(text "FIFO_WRE" (rect 1074 2280 1145 2295)(font "Arial" ))
-	(pt 1064 2296)
-	(pt 1144 2296)
-)
-(connector
-	(text "DDRCLK0" (rect 194 2592 262 2607)(font "Arial" ))
+	(text "DDRCLK0" (rect 194 2592 245 2604)(font "Arial" ))
 	(pt 296 2608)
 	(pt 184 2608)
 )
 (connector
-	(text "DDRCLK0" (rect 194 1920 262 1935)(font "Arial" ))
+	(text "DDRCLK0" (rect 194 1920 245 1932)(font "Arial" ))
 	(pt 296 1936)
 	(pt 184 1936)
 )
 (connector
-	(text "VIDEO_DDR_TA" (rect 570 2488 677 2503)(font "Arial" ))
+	(text "VIDEO_DDR_TA" (rect 570 2488 653 2500)(font "Arial" ))
 	(pt 560 2504)
 	(pt 664 2504)
 )
 (connector
-	(text "BLITTER_TA" (rect 578 2960 660 2975)(font "Arial" ))
+	(text "BLITTER_TA" (rect 578 2960 640 2972)(font "Arial" ))
 	(pt 568 2976)
 	(pt 672 2976)
 )
@@ -8507,7 +8464,7 @@ applicable agreement for further details.
 	(pt 472 1808)
 )
 (connector
-	(text "BLITTER_TA" (rect 274 1792 356 1807)(font "Arial" ))
+	(text "BLITTER_TA" (rect 274 1792 336 1804)(font "Arial" ))
 	(pt 264 1808)
 	(pt 368 1808)
 )
@@ -8528,48 +8485,48 @@ applicable agreement for further details.
 	(pt 360 1800)
 )
 (connector
-	(text "VIDEO_DDR_TA" (rect 258 1768 365 1783)(font "Arial" ))
+	(text "VIDEO_DDR_TA" (rect 258 1768 341 1780)(font "Arial" ))
 	(pt 360 1784)
 	(pt 264 1784)
 )
 (connector
-	(text "VDP_OUT[63..0]" (rect 1506 1328 1611 1343)(font "Arial" ))
+	(text "VDP_OUT[63..0]" (rect 1506 1328 1588 1340)(font "Arial" ))
 	(pt 1584 1344)
 	(pt 1496 1344)
 	(bus)
 )
 (connector
-	(text "FB_DDR[127..64]" (rect 1258 1352 1371 1367)(font "Arial" ))
+	(text "FB_DDR[127..64]" (rect 1258 1352 1346 1364)(font "Arial" ))
 	(pt 1224 1368)
 	(pt 1344 1368)
 	(bus)
 )
 (connector
-	(text "BLITTER_DOUT[63..0]" (rect 1234 1304 1379 1319)(font "Arial" ))
+	(text "BLITTER_DOUT[63..0]" (rect 1234 1304 1346 1316)(font "Arial" ))
 	(pt 1224 1320)
 	(pt 1344 1320)
 	(bus)
 )
 (connector
-	(text "BLITTER_DOUT[127..64]" (rect 1234 1320 1395 1335)(font "Arial" ))
+	(text "BLITTER_DOUT[127..64]" (rect 1234 1320 1357 1332)(font "Arial" ))
 	(pt 1224 1336)
 	(pt 1344 1336)
 	(bus)
 )
 (connector
-	(text "FB_DDR[63..0]" (rect 1258 1336 1354 1351)(font "Arial" ))
+	(text "FB_DDR[63..0]" (rect 1258 1336 1334 1348)(font "Arial" ))
 	(pt 1224 1352)
 	(pt 1344 1352)
 	(bus)
 )
 (connector
-	(text "VDR[31..0]" (rect 930 1176 998 1191)(font "Arial" ))
+	(text "VDR[31..0]" (rect 930 1176 985 1188)(font "Arial" ))
 	(pt 920 1192)
 	(pt 1008 1192)
 	(bus)
 )
 (connector
-	(text "DDRWR_D_SEL[1..0]" (rect 1298 1400 1438 1415)(font "Arial" ))
+	(text "DDRWR_D_SEL[1..0]" (rect 1298 1400 1407 1412)(font "Arial" ))
 	(pt 1424 1416)
 	(pt 1288 1416)
 	(bus)
@@ -8580,64 +8537,54 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "DDR_FB0" (rect 1106 1424 1172 1439)(font "Arial" ))
+	(text "DDR_FB0" (rect 1106 1424 1156 1436)(font "Arial" ))
 	(pt 1104 1440)
 	(pt 1176 1440)
 )
 (connector
-	(text "VDP_IN[31..0]" (rect 1114 1272 1203 1287)(font "Arial" ))
+	(text "VDP_IN[31..0]" (rect 1114 1272 1185 1284)(font "Arial" ))
 	(pt 1104 1288)
 	(pt 1192 1288)
 	(bus)
 )
 (connector
-	(text "SR_BLITTER_DACK" (rect 570 2464 703 2479)(font "Arial" ))
+	(text "SR_BLITTER_DACK" (rect 570 2464 671 2476)(font "Arial" ))
 	(pt 664 2480)
 	(pt 560 2480)
 )
 (connector
-	(text "DDRCLK0" (rect 1114 1528 1182 1543)(font "Arial" ))
+	(text "DDRCLK0" (rect 1114 1528 1165 1540)(font "Arial" ))
 	(pt 1104 1544)
 	(pt 1176 1544)
 )
 (connector
-	(text "DDRCLK0" (rect 1114 1408 1182 1423)(font "Arial" ))
+	(text "DDRCLK0" (rect 1114 1408 1165 1420)(font "Arial" ))
 	(pt 1104 1424)
 	(pt 1176 1424)
 )
 (connector
-	(text "DDRCLK0" (rect 1114 1288 1182 1303)(font "Arial" ))
+	(text "DDRCLK0" (rect 1114 1288 1165 1300)(font "Arial" ))
 	(pt 1104 1304)
 	(pt 1176 1304)
 )
 (connector
-	(text "DDRCLK0" (rect 1650 1384 1718 1399)(font "Arial" ))
+	(text "DDRCLK0" (rect 1650 1384 1701 1396)(font "Arial" ))
 	(pt 1712 1400)
 	(pt 1640 1400)
 )
 (connector
-	(text "DDRCLK0" (rect 810 2936 878 2951)(font "Arial" ))
-	(pt 800 2952)
-	(pt 888 2952)
-)
-(connector
-	(text "DDRCLK0" (rect 842 2264 910 2279)(font "Arial" ))
-	(pt 832 2280)
-	(pt 920 2280)
-)
-(connector
-	(text "DDR_FB[4..0]" (rect 1074 2176 1162 2191)(font "Arial" ))
+	(text "DDR_FB[4..0]" (rect 1074 2176 1144 2188)(font "Arial" ))
 	(pt 1064 2192)
 	(pt 1168 2192)
 	(bus)
 )
 (connector
-	(text "CLK33M" (rect 218 2432 273 2447)(font "Arial" ))
+	(text "CLK33M" (rect 218 2432 259 2444)(font "Arial" ))
 	(pt 208 2448)
 	(pt 296 2448)
 )
 (connector
-	(text "FIFO_D[127..0]" (rect 2170 1416 2266 1431)(font "Arial" ))
+	(text "FIFO_D[127..0]" (rect 2170 1416 2247 1428)(font "Arial" ))
 	(pt 2168 1432)
 	(pt 2232 1432)
 	(bus)
@@ -8683,27 +8630,27 @@ applicable agreement for further details.
 	(pt 2512 1728)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1634 1432 1709 1447)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
 	(pt 1640 1448)
 	(pt 1712 1448)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1938 1424 2013 1439)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1938 1424 1994 1436)(font "Arial" ))
 	(pt 1928 1440)
 	(pt 2000 1440)
 )
 (connector
-	(text "FIFO_RDE" (rect 1914 1440 1983 1455)(font "Arial" ))
+	(text "FIFO_RDE" (rect 1914 1440 1969 1452)(font "Arial" ))
 	(pt 1904 1456)
 	(pt 2000 1456)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2018 1552 2093 1567)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2018 1552 2074 1564)(font "Arial" ))
 	(pt 2008 1568)
 	(pt 2080 1568)
 )
 (connector
-	(text "FIFO_RDE" (rect 1994 1536 2063 1551)(font "Arial" ))
+	(text "FIFO_RDE" (rect 1994 1536 2049 1548)(font "Arial" ))
 	(pt 1984 1552)
 	(pt 2080 1552)
 )
@@ -8732,7 +8679,7 @@ applicable agreement for further details.
 	(pt 2512 2368)
 )
 (connector
-	(text "DDR_WR" (rect 1290 2808 1353 2823)(font "Arial" ))
+	(text "DDR_WR" (rect 1290 2808 1339 2820)(font "Arial" ))
 	(pt 1280 2824)
 	(pt 1344 2824)
 )
@@ -8765,7 +8712,7 @@ applicable agreement for further details.
 	(pt 1328 3008)
 )
 (connector
-	(text "DDRCLK0" (rect 1218 2936 1286 2951)(font "Arial" ))
+	(text "DDRCLK0" (rect 1218 2936 1269 2948)(font "Arial" ))
 	(pt 1208 2952)
 	(pt 1328 2952)
 )
@@ -8774,53 +8721,53 @@ applicable agreement for further details.
 	(pt 1360 2952)
 )
 (connector
-	(text "VDP_OUT[63..32]" (rect 1234 1520 1347 1535)(font "Arial" ))
+	(text "VDP_OUT[63..32]" (rect 1234 1520 1322 1532)(font "Arial" ))
 	(pt 1312 1536)
 	(pt 1224 1536)
 	(bus)
 )
 (connector
-	(text "VDP_OUT[31..0]" (rect 1234 1536 1339 1551)(font "Arial" ))
+	(text "VDP_OUT[31..0]" (rect 1234 1536 1316 1548)(font "Arial" ))
 	(pt 1312 1552)
 	(pt 1224 1552)
 	(bus)
 )
 (connector
-	(text "VDP_IN[63..32]" (rect 1562 1536 1659 1551)(font "Arial" ))
+	(text "VDP_IN[63..32]" (rect 1562 1536 1639 1548)(font "Arial" ))
 	(pt 1552 1552)
 	(pt 1640 1552)
 	(bus)
 )
 (connector
-	(text "VD[31..0]" (rect 1578 1552 1635 1567)(font "Arial" ))
+	(text "VD[31..0]" (rect 1578 1552 1625 1564)(font "Arial" ))
 	(pt 1640 1568)
 	(pt 1552 1568)
 	(bus)
 )
 (connector
-	(text "DDRCLK3" (rect 1250 1584 1318 1599)(font "Arial" ))
+	(text "DDRCLK3" (rect 1250 1584 1301 1596)(font "Arial" ))
 	(pt 1312 1600)
 	(pt 1240 1600)
 )
 (connector
-	(text "VDP_IN[31..0]" (rect 1554 1520 1643 1535)(font "Arial" ))
+	(text "VDP_IN[31..0]" (rect 1554 1520 1625 1532)(font "Arial" ))
 	(pt 1552 1536)
 	(pt 1632 1536)
 	(bus)
 )
 (connector
-	(text "DDRCLK1" (rect 1250 1568 1318 1583)(font "Arial" ))
+	(text "DDRCLK1" (rect 1250 1568 1301 1580)(font "Arial" ))
 	(pt 1312 1584)
 	(pt 1240 1584)
 )
 (connector
-	(text "VDR[31..0]" (rect 1858 1568 1926 1583)(font "Arial" ))
+	(text "VDR[31..0]" (rect 1858 1568 1913 1580)(font "Arial" ))
 	(pt 1848 1584)
 	(pt 1936 1584)
 	(bus)
 )
 (connector
-	(text "DDR_SYNC_66M" (rect 1602 1584 1716 1599)(font "Arial" ))
+	(text "DDR_SYNC_66M" (rect 1602 1584 1690 1596)(font "Arial" ))
 	(pt 1592 1600)
 	(pt 1688 1600)
 )
@@ -8830,106 +8777,21 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "VDOUT_OE" (rect 1242 1552 1318 1567)(font "Arial" ))
+	(text "VDOUT_OE" (rect 1242 1552 1301 1564)(font "Arial" ))
 	(pt 1232 1568)
 	(pt 1312 1568)
 )
 (connector
-	(text "DDRCLK3" (rect 1170 2472 1238 2487)(font "Arial" ))
-	(pt 1160 2488)
-	(pt 1240 2488)
-)
-(connector
-	(text "VDM[3..0]" (rect 1482 2440 1542 2455)(font "Arial" ))
-	(pt 1536 2456)
-	(pt 1472 2456)
-	(bus)
-)
-(connector
-	(text "VDMP[7..4]" (rect 1170 2440 1239 2455)(font "Arial" ))
-	(pt 1160 2456)
-	(pt 1240 2456)
-	(bus)
-)
-(connector
-	(text "VDMP[3..0]" (rect 1170 2456 1239 2471)(font "Arial" ))
-	(pt 1160 2472)
-	(pt 1240 2472)
-	(bus)
-)
-(connector
-	(text "VDMP[7..0]" (rect 1242 2672 1311 2687)(font "Arial" ))
-	(pt 1232 2688)
-	(pt 1304 2688)
-	(bus)
-)
-(connector
-	(text "BA[1..0]" (rect 570 2120 618 2135)(font "Arial" ))
+	(text "BA[1..0]" (rect 570 2120 610 2132)(font "Arial" ))
 	(pt 632 2136)
 	(pt 560 2136)
 	(bus)
 )
 (connector
-	(text "DDRWR_D_SEL0" (rect 1066 2768 1184 2783)(font "Arial" ))
-	(pt 1056 2784)
-	(pt 1152 2784)
-)
-(connector
-	(text "DDRCLK3" (rect 930 2784 998 2799)(font "Arial" ))
-	(pt 928 2800)
-	(pt 992 2800)
-)
-(connector
-	(text "SR_VDMP[7..0]" (rect 1002 2656 1099 2671)(font "Arial" ))
-	(pt 992 2672)
-	(pt 1088 2672)
-	(bus)
-)
-(connector
-	(text "SR_DDRWR_D_SEL" (rect 890 2768 1028 2783)(font "Arial" ))
-	(pt 888 2784)
-	(pt 992 2784)
-)
-(connector
-	(text "DDRWR_D_SEL1" (rect 570 2392 688 2407)(font "Arial" ))
+	(text "DDRWR_D_SEL1" (rect 570 2392 659 2404)(font "Arial" ))
 	(pt 656 2408)
 	(pt 560 2408)
 )
-(connector
-	(text "VDOUT_OE" (rect 1386 2328 1462 2343)(font "Arial" ))
-	(pt 1376 2344)
-	(pt 1456 2344)
-)
-(connector
-	(text "DDR_WR" (rect 1258 2336 1321 2351)(font "Arial" ))
-	(pt 1248 2352)
-	(pt 1312 2352)
-)
-(connector
-	(text "SR_DDR_WR" (rect 1242 2320 1334 2335)(font "Arial" ))
-	(pt 1248 2336)
-	(pt 1312 2336)
-)
-(connector
-	(text "DDRCLK3" (rect 906 2400 974 2415)(font "Arial" ))
-	(pt 904 2416)
-	(pt 968 2416)
-)
-(connector
-	(text "SR_DDR_WR" (rect 898 2384 990 2399)(font "Arial" ))
-	(pt 896 2400)
-	(pt 968 2400)
-)
-(connector
-	(text "DDR_WR" (rect 1042 2384 1105 2399)(font "Arial" ))
-	(pt 1032 2400)
-	(pt 1096 2400)
-)
-(connector
-	(text "DDRCLK2" (rect 1018 2672 1086 2687)(font "Arial" ))
-	(pt 1008 2688)
-	(pt 1088 2688)
-)
 (connector
 	(pt 1696 2840)
 	(pt 1696 2816)
@@ -8949,18 +8811,18 @@ applicable agreement for further details.
 	(pt 1808 2776)
 )
 (connector
-	(text "PIXEL_CLK" (rect 1546 2776 1621 2791)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 1546 2776 1602 2788)(font "Arial" ))
 	(pt 1536 2792)
 	(pt 1616 2792)
 )
 (connector
-	(text "CLUT_MUX_ADR[2..0]" (rect 2130 2744 2273 2759)(font "Arial" ))
+	(text "CLUT_MUX_ADR[2..0]" (rect 2130 2744 2242 2756)(font "Arial" ))
 	(pt 2304 2760)
 	(pt 2120 2760)
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2338 2744 2413 2759)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2338 2744 2394 2756)(font "Arial" ))
 	(pt 2400 2760)
 	(pt 2328 2760)
 )
@@ -8983,132 +8845,132 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2162 2696 2237 2711)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2162 2696 2218 2708)(font "Arial" ))
 	(pt 2224 2712)
 	(pt 2152 2712)
 )
 (connector
-	(text "FIFO_D[7..0]" (rect 2730 2568 2810 2583)(font "Arial" ))
+	(text "FIFO_D[7..0]" (rect 2730 2568 2796 2580)(font "Arial" ))
 	(pt 2824 2584)
 	(pt 2720 2584)
 	(bus)
 )
 (connector
-	(text "FIFO_D[15..8]" (rect 2730 2584 2818 2599)(font "Arial" ))
+	(text "FIFO_D[15..8]" (rect 2730 2584 2801 2596)(font "Arial" ))
 	(pt 2824 2600)
 	(pt 2720 2600)
 	(bus)
 )
 (connector
-	(text "FIFO_D[23..16]" (rect 2730 2600 2826 2615)(font "Arial" ))
+	(text "FIFO_D[23..16]" (rect 2730 2600 2807 2612)(font "Arial" ))
 	(pt 2824 2616)
 	(pt 2720 2616)
 	(bus)
 )
 (connector
-	(text "FIFO_D[31..24]" (rect 2730 2616 2826 2631)(font "Arial" ))
+	(text "FIFO_D[31..24]" (rect 2730 2616 2807 2628)(font "Arial" ))
 	(pt 2824 2632)
 	(pt 2720 2632)
 	(bus)
 )
 (connector
-	(text "FIFO_D[39..32]" (rect 2730 2632 2826 2647)(font "Arial" ))
+	(text "FIFO_D[39..32]" (rect 2730 2632 2807 2644)(font "Arial" ))
 	(pt 2824 2648)
 	(pt 2720 2648)
 	(bus)
 )
 (connector
-	(text "FIFO_D[47..40]" (rect 2730 2648 2826 2663)(font "Arial" ))
+	(text "FIFO_D[47..40]" (rect 2730 2648 2807 2660)(font "Arial" ))
 	(pt 2824 2664)
 	(pt 2720 2664)
 	(bus)
 )
 (connector
-	(text "FIFO_D[55..48]" (rect 2730 2664 2826 2679)(font "Arial" ))
+	(text "FIFO_D[55..48]" (rect 2730 2664 2807 2676)(font "Arial" ))
 	(pt 2824 2680)
 	(pt 2720 2680)
 	(bus)
 )
 (connector
-	(text "FIFO_D[63..56]" (rect 2730 2680 2826 2695)(font "Arial" ))
+	(text "FIFO_D[63..56]" (rect 2730 2680 2807 2692)(font "Arial" ))
 	(pt 2824 2696)
 	(pt 2720 2696)
 	(bus)
 )
 (connector
-	(text "FIFO_D[71..64]" (rect 2730 2696 2826 2711)(font "Arial" ))
+	(text "FIFO_D[71..64]" (rect 2730 2696 2807 2708)(font "Arial" ))
 	(pt 2824 2712)
 	(pt 2720 2712)
 	(bus)
 )
 (connector
-	(text "FIFO_D[79..72]" (rect 2730 2712 2826 2727)(font "Arial" ))
+	(text "FIFO_D[79..72]" (rect 2730 2712 2807 2724)(font "Arial" ))
 	(pt 2824 2728)
 	(pt 2720 2728)
 	(bus)
 )
 (connector
-	(text "FIFO_D[87..80]" (rect 2730 2728 2826 2743)(font "Arial" ))
+	(text "FIFO_D[87..80]" (rect 2730 2728 2807 2740)(font "Arial" ))
 	(pt 2824 2744)
 	(pt 2720 2744)
 	(bus)
 )
 (connector
-	(text "FIFO_D[95..88]" (rect 2730 2744 2826 2759)(font "Arial" ))
+	(text "FIFO_D[95..88]" (rect 2730 2744 2807 2756)(font "Arial" ))
 	(pt 2824 2760)
 	(pt 2720 2760)
 	(bus)
 )
 (connector
-	(text "FIFO_D[103..96]" (rect 2730 2760 2835 2775)(font "Arial" ))
+	(text "FIFO_D[103..96]" (rect 2730 2760 2813 2772)(font "Arial" ))
 	(pt 2824 2776)
 	(pt 2720 2776)
 	(bus)
 )
 (connector
-	(text "FIFO_D[111..104]" (rect 2730 2776 2843 2791)(font "Arial" ))
+	(text "FIFO_D[111..104]" (rect 2730 2776 2819 2788)(font "Arial" ))
 	(pt 2824 2792)
 	(pt 2720 2792)
 	(bus)
 )
 (connector
-	(text "FIFO_D[119..112]" (rect 2730 2792 2843 2807)(font "Arial" ))
+	(text "FIFO_D[119..112]" (rect 2730 2792 2819 2804)(font "Arial" ))
 	(pt 2824 2808)
 	(pt 2720 2808)
 	(bus)
 )
 (connector
-	(text "FIFO_D[127..120]" (rect 2730 2808 2843 2823)(font "Arial" ))
+	(text "FIFO_D[127..120]" (rect 2730 2808 2819 2820)(font "Arial" ))
 	(pt 2824 2824)
 	(pt 2720 2824)
 	(bus)
 )
 (connector
-	(text "CCF[23..0]" (rect 3362 2752 3430 2767)(font "Arial" ))
+	(text "CCF[23..0]" (rect 3362 2752 3417 2764)(font "Arial" ))
 	(pt 3432 2768)
 	(pt 3352 2768)
 	(bus)
 )
 (connector
-	(text "CCR[23..0]" (rect 3954 2720 4024 2735)(font "Arial" ))
+	(text "CCR[23..0]" (rect 3954 2720 4010 2732)(font "Arial" ))
 	(pt 4024 2736)
 	(pt 3944 2736)
 	(bus)
 )
 (connector
-	(text "CCS[23..0]" (rect 3362 2840 3431 2855)(font "Arial" ))
+	(text "CCS[23..0]" (rect 3362 2840 3417 2852)(font "Arial" ))
 	(pt 3432 2856)
 	(pt 3352 2856)
 	(bus)
 )
 (connector
-	(text "CC16[23..0]" (rect 3954 2752 4030 2767)(font "Arial" ))
+	(text "CC16[23..0]" (rect 3954 2752 4014 2764)(font "Arial" ))
 	(pt 4024 2768)
 	(pt 3944 2768)
 	(bus)
 )
 (connector
-	(text "VR[7..0],VG[7..0],VB[7..0]" (rect 4522 2776 4676 2791)(font "Arial" ))
+	(text "VR[7..0],VG[7..0],VB[7..0]" (rect 4522 2776 4651 2788)(font "Arial" ))
 	(pt 4512 2792)
 	(pt 4664 2792)
 	(bus)
@@ -9119,7 +8981,7 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 4202 2808 4277 2823)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 4202 2808 4258 2820)(font "Arial" ))
 	(pt 4192 2824)
 	(pt 4280 2824)
 )
@@ -9134,7 +8996,7 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3946 2848 4021 2863)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3946 2848 4002 2860)(font "Arial" ))
 	(pt 3936 2864)
 	(pt 4024 2864)
 )
@@ -9144,13 +9006,13 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "CCSEL[2..0]" (rect 4010 2904 4089 2919)(font "Arial" ))
+	(text "CCSEL[2..0]" (rect 4010 2904 4072 2916)(font "Arial" ))
 	(pt 4104 2920)
 	(pt 4000 2920)
 	(bus)
 )
 (connector
-	(text "CCA[23..0]" (rect 3954 2768 4022 2783)(font "Arial" ))
+	(text "CCA[23..0]" (rect 3954 2768 4009 2780)(font "Arial" ))
 	(pt 4024 2784)
 	(pt 3944 2784)
 	(bus)
@@ -9161,7 +9023,7 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "ZR_C8[7..0]" (rect 3232 2712 3308 2727)(font "Arial" ))
+	(text "ZR_C8[7..0]" (rect 3232 2712 3293 2724)(font "Arial" ))
 	(pt 3232 2728)
 	(pt 3304 2728)
 	(bus)
@@ -9172,12 +9034,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2746 2824 2821 2839)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2746 2824 2802 2836)(font "Arial" ))
 	(pt 2824 2840)
 	(pt 2736 2840)
 )
 (connector
-	(text "CC24[23..0]" (rect 3954 2736 4030 2751)(font "Arial" ))
+	(text "CC24[23..0]" (rect 3954 2736 4014 2748)(font "Arial" ))
 	(pt 3944 2752)
 	(pt 4024 2752)
 	(bus)
@@ -9233,60 +9095,60 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3034 2712 3109 2727)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3034 2712 3090 2724)(font "Arial" ))
 	(pt 3032 2728)
 	(pt 3088 2728)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3618 2784 3693 2799)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3618 2784 3674 2796)(font "Arial" ))
 	(pt 3616 2800)
 	(pt 3672 2800)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3618 2872 3693 2887)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3618 2872 3674 2884)(font "Arial" ))
 	(pt 3616 2888)
 	(pt 3672 2888)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3378 2856 3453 2871)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3378 2856 3434 2868)(font "Arial" ))
 	(pt 3376 2872)
 	(pt 3432 2872)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3378 2768 3453 2783)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3378 2768 3434 2780)(font "Arial" ))
 	(pt 3376 2784)
 	(pt 3432 2784)
 )
 (connector
-	(text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2506 2592 2751 2607)(font "Arial" ))
+	(text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2506 2592 2699 2604)(font "Arial" ))
 	(pt 2688 2664)
 	(pt 2560 2664)
 	(bus)
 )
 (connector
-	(text "CC16[18..16],CC16[9..8],CC16[2..0]" (rect 2530 2728 2758 2743)(font "Arial" ))
+	(text "CC16[18..16],CC16[9..8],CC16[2..0]" (rect 2530 2728 2711 2740)(font "Arial" ))
 	(pt 2696 2744)
 	(pt 2520 2744)
 	(bus)
 )
 (connector
-	(text "CC24[31..0]" (rect 1986 2760 2062 2775)(font "Arial" ))
+	(text "CC24[31..0]" (rect 1986 2760 2046 2772)(font "Arial" ))
 	(pt 1976 2776)
 	(pt 2072 2776)
 	(bus)
 )
 (connector
-	(text "ZR_C8B[0]" (rect 3282 2952 3352 2967)(font "Arial" ))
+	(text "ZR_C8B[0]" (rect 3282 2952 3337 2964)(font "Arial" ))
 	(pt 3272 2968)
 	(pt 3344 2968)
 )
 (connector
-	(text "COLOR1" (rect 3154 3008 3213 3023)(font "Arial" ))
+	(text "COLOR1" (rect 3154 3008 3198 3020)(font "Arial" ))
 	(pt 3232 3024)
 	(pt 3144 3024)
 )
 (connector
-	(text "ZR_C8[7..1]" (rect 3090 3072 3166 3087)(font "Arial" ))
+	(text "ZR_C8[7..1]" (rect 3090 3072 3151 3084)(font "Arial" ))
 	(pt 3080 3088)
 	(pt 3160 3088)
 	(bus)
@@ -9300,7 +9162,7 @@ applicable agreement for further details.
 	(pt 3232 3064)
 )
 (connector
-	(text "ZR_C8B[7..1]" (rect 3306 3080 3392 3095)(font "Arial" ))
+	(text "ZR_C8B[7..1]" (rect 3306 3080 3374 3092)(font "Arial" ))
 	(pt 3296 3096)
 	(pt 3392 3096)
 	(bus)
@@ -9311,22 +9173,22 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "ZR_C8[0]" (rect 3146 2960 3207 2975)(font "Arial" ))
+	(text "ZR_C8[0]" (rect 3146 2960 3194 2972)(font "Arial" ))
 	(pt 3136 2976)
 	(pt 3192 2976)
 )
 (connector
-	(text "CLUT_ADR0" (rect 2842 2944 2925 2959)(font "Arial" ))
+	(text "CLUT_ADR0" (rect 2842 2944 2905 2956)(font "Arial" ))
 	(pt 2832 2960)
 	(pt 2912 2960)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2858 2960 2933 2975)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2858 2960 2914 2972)(font "Arial" ))
 	(pt 2856 2976)
 	(pt 2912 2976)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2994 2960 3069 2975)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2994 2960 3050 2972)(font "Arial" ))
 	(pt 2992 2976)
 	(pt 3048 2976)
 )
@@ -9339,18 +9201,12 @@ applicable agreement for further details.
 	(pt 3192 2960)
 )
 (connector
-	(text "FIFO_MW[8..0]" (rect 194 2376 287 2391)(font "Arial" ))
-	(pt 296 2392)
-	(pt 184 2392)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 2208 3439 2223)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 2208 3424 2220)(font "Arial" ))
 	(pt 3448 2224)
 	(pt 3360 2224)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 2224 3445 2239)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 2224 3426 2236)(font "Arial" ))
 	(pt 3448 2240)
 	(pt 3360 2240)
 )
@@ -9359,7 +9215,7 @@ applicable agreement for further details.
 	(pt 3808 2128)
 )
 (connector
-	(text "ACP_CLUT_RD" (rect 3722 2112 3825 2127)(font "Arial" ))
+	(text "ACP_CLUT_RD" (rect 3722 2112 3801 2124)(font "Arial" ))
 	(pt 3808 2128)
 	(pt 3712 2128)
 )
@@ -9373,12 +9229,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 2416 3439 2431)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 2416 3424 2428)(font "Arial" ))
 	(pt 3448 2432)
 	(pt 3360 2432)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 2432 3445 2447)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 2432 3426 2444)(font "Arial" ))
 	(pt 3448 2448)
 	(pt 3360 2448)
 )
@@ -9387,7 +9243,7 @@ applicable agreement for further details.
 	(pt 3808 2336)
 )
 (connector
-	(text "ACP_CLUT_RD" (rect 3722 2320 3825 2335)(font "Arial" ))
+	(text "ACP_CLUT_RD" (rect 3722 2320 3801 2332)(font "Arial" ))
 	(pt 3808 2336)
 	(pt 3712 2336)
 )
@@ -9401,12 +9257,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 2624 3439 2639)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 2624 3424 2636)(font "Arial" ))
 	(pt 3448 2640)
 	(pt 3360 2640)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 2640 3445 2655)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 2640 3426 2652)(font "Arial" ))
 	(pt 3448 2656)
 	(pt 3360 2656)
 )
@@ -9415,7 +9271,7 @@ applicable agreement for further details.
 	(pt 3808 2544)
 )
 (connector
-	(text "ACP_CLUT_RD" (rect 3722 2528 3825 2543)(font "Arial" ))
+	(text "ACP_CLUT_RD" (rect 3722 2528 3801 2540)(font "Arial" ))
 	(pt 3808 2544)
 	(pt 3712 2544)
 )
@@ -9429,12 +9285,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 1560 3439 1575)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 1560 3424 1572)(font "Arial" ))
 	(pt 3448 1576)
 	(pt 3360 1576)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 1576 3445 1591)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 1576 3426 1588)(font "Arial" ))
 	(pt 3448 1592)
 	(pt 3360 1592)
 )
@@ -9444,18 +9300,18 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "FB_AD[31..26]" (rect 3930 1432 4022 1447)(font "Arial" ))
+	(text "FB_AD[31..26]" (rect 3930 1432 4003 1444)(font "Arial" ))
 	(pt 3920 1448)
 	(pt 4032 1448)
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 1768 3439 1783)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 1768 3424 1780)(font "Arial" ))
 	(pt 3448 1784)
 	(pt 3360 1784)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 1784 3445 1799)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 1784 3426 1796)(font "Arial" ))
 	(pt 3448 1800)
 	(pt 3360 1800)
 )
@@ -9465,12 +9321,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 1976 3439 1991)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 1976 3424 1988)(font "Arial" ))
 	(pt 3448 1992)
 	(pt 3360 1992)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 1992 3445 2007)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 1992 3426 2004)(font "Arial" ))
 	(pt 3448 2008)
 	(pt 3360 2008)
 )
@@ -9484,19 +9340,19 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1928 3444 1943)(font "Arial" ))
+	(text "CLUT_ADR[7..0]" (rect 3338 1928 3421 1940)(font "Arial" ))
 	(pt 3336 1944)
 	(pt 3448 1944)
 	(bus)
 )
 (connector
-	(text "FB_AD[23..18]" (rect 3930 1640 4022 1655)(font "Arial" ))
+	(text "FB_AD[23..18]" (rect 3930 1640 4003 1652)(font "Arial" ))
 	(pt 3920 1656)
 	(pt 4032 1656)
 	(bus)
 )
 (connector
-	(text "FB_AD[23..18]" (rect 3930 1848 4022 1863)(font "Arial" ))
+	(text "FB_AD[23..18]" (rect 3930 1848 4003 1860)(font "Arial" ))
 	(pt 3920 1864)
 	(pt 4032 1864)
 	(bus)
@@ -9506,7 +9362,7 @@ applicable agreement for further details.
 	(pt 3880 1480)
 )
 (connector
-	(text "FALCON_CLUT_RDH" (rect 3762 1464 3904 1479)(font "Arial" ))
+	(text "FALCON_CLUT_RDH" (rect 3762 1464 3871 1476)(font "Arial" ))
 	(pt 3880 1480)
 	(pt 3752 1480)
 )
@@ -9515,7 +9371,7 @@ applicable agreement for further details.
 	(pt 3880 1688)
 )
 (connector
-	(text "FALCON_CLUT_RDH" (rect 3762 1672 3904 1687)(font "Arial" ))
+	(text "FALCON_CLUT_RDH" (rect 3762 1672 3871 1684)(font "Arial" ))
 	(pt 3880 1688)
 	(pt 3752 1688)
 )
@@ -9524,63 +9380,63 @@ applicable agreement for further details.
 	(pt 3880 1896)
 )
 (connector
-	(text "FALCON_CLUT_RDL" (rect 3762 1880 3902 1895)(font "Arial" ))
+	(text "FALCON_CLUT_RDL" (rect 3762 1880 3869 1892)(font "Arial" ))
 	(pt 3880 1896)
 	(pt 3752 1896)
 )
 (connector
-	(text "FALCON_CLUT_WR3" (rect 3346 1880 3488 1895)(font "Arial" ))
+	(text "FALCON_CLUT_WR3" (rect 3346 1880 3455 1892)(font "Arial" ))
 	(pt 3448 1896)
 	(pt 3336 1896)
 )
 (connector
-	(text "FALCON_CLUT_WR0" (rect 3346 1464 3488 1479)(font "Arial" ))
+	(text "FALCON_CLUT_WR0" (rect 3346 1464 3455 1476)(font "Arial" ))
 	(pt 3448 1480)
 	(pt 3336 1480)
 )
 (connector
-	(text "FALCON_CLUT_WR1" (rect 3346 1672 3488 1687)(font "Arial" ))
+	(text "FALCON_CLUT_WR1" (rect 3346 1672 3455 1684)(font "Arial" ))
 	(pt 3448 1688)
 	(pt 3336 1688)
 )
 (connector
-	(text "CCF[7..2]" (rect 3834 1912 3894 1927)(font "Arial" ))
+	(text "CCF[7..2]" (rect 3834 1912 3883 1924)(font "Arial" ))
 	(pt 3904 1928)
 	(pt 3704 1928)
 	(bus)
 )
 (connector
-	(text "CCF[1..0]" (rect 3842 1944 3902 1959)(font "Arial" ))
+	(text "CCF[1..0]" (rect 3842 1944 3891 1956)(font "Arial" ))
 	(pt 3904 1960)
 	(pt 3816 1960)
 	(bus)
 )
 (connector
-	(text "CCF[23..18]" (rect 3826 1496 3902 1511)(font "Arial" ))
+	(text "CCF[23..18]" (rect 3826 1496 3887 1508)(font "Arial" ))
 	(pt 3904 1512)
 	(pt 3704 1512)
 	(bus)
 )
 (connector
-	(text "CCF[15..10]" (rect 3826 1704 3902 1719)(font "Arial" ))
+	(text "CCF[15..10]" (rect 3826 1704 3887 1716)(font "Arial" ))
 	(pt 3904 1720)
 	(pt 3704 1720)
 	(bus)
 )
 (connector
-	(text "CCF[9..8]" (rect 3842 1744 3902 1759)(font "Arial" ))
+	(text "CCF[9..8]" (rect 3842 1744 3891 1756)(font "Arial" ))
 	(pt 3904 1760)
 	(pt 3816 1760)
 	(bus)
 )
 (connector
-	(text "CCF[17..16]" (rect 3842 1536 3918 1551)(font "Arial" ))
+	(text "CCF[17..16]" (rect 3842 1536 3903 1548)(font "Arial" ))
 	(pt 3904 1552)
 	(pt 3816 1552)
 	(bus)
 )
 (connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1720 3444 1735)(font "Arial" ))
+	(text "CLUT_ADR[7..0]" (rect 3338 1720 3421 1732)(font "Arial" ))
 	(pt 3336 1736)
 	(pt 3448 1736)
 	(bus)
@@ -9590,19 +9446,19 @@ applicable agreement for further details.
 	(pt 3448 1752)
 )
 (connector
-	(text "FB_AD[23..18]" (rect 3346 1848 3438 1863)(font "Arial" ))
+	(text "FB_AD[23..18]" (rect 3346 1848 3419 1860)(font "Arial" ))
 	(pt 3336 1864)
 	(pt 3448 1864)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3346 1864 3432 1879)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3346 1864 3415 1876)(font "Arial" ))
 	(pt 3336 1880)
 	(pt 3448 1880)
 	(bus)
 )
 (connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1512 3444 1527)(font "Arial" ))
+	(text "CLUT_ADR[7..0]" (rect 3338 1512 3421 1524)(font "Arial" ))
 	(pt 3336 1528)
 	(pt 3448 1528)
 	(bus)
@@ -9612,36 +9468,36 @@ applicable agreement for further details.
 	(pt 3448 1544)
 )
 (connector
-	(text "FB_AD[23..18]" (rect 3346 1640 3438 1655)(font "Arial" ))
+	(text "FB_AD[23..18]" (rect 3346 1640 3419 1652)(font "Arial" ))
 	(pt 3336 1656)
 	(pt 3448 1656)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3346 1656 3432 1671)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3346 1656 3415 1668)(font "Arial" ))
 	(pt 3336 1672)
 	(pt 3448 1672)
 	(bus)
 )
 (connector
-	(text "FB_AD[31..26]" (rect 3346 1432 3438 1447)(font "Arial" ))
+	(text "FB_AD[31..26]" (rect 3346 1432 3419 1444)(font "Arial" ))
 	(pt 3336 1448)
 	(pt 3448 1448)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3346 1448 3432 1463)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3346 1448 3415 1460)(font "Arial" ))
 	(pt 3336 1464)
 	(pt 3448 1464)
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 920 3439 935)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 920 3424 932)(font "Arial" ))
 	(pt 3448 936)
 	(pt 3360 936)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 936 3445 951)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 936 3426 948)(font "Arial" ))
 	(pt 3448 952)
 	(pt 3360 952)
 )
@@ -9651,12 +9507,12 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 1128 3439 1143)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 1128 3424 1140)(font "Arial" ))
 	(pt 3448 1144)
 	(pt 3360 1144)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 1144 3445 1159)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 1144 3426 1156)(font "Arial" ))
 	(pt 3448 1160)
 	(pt 3360 1160)
 )
@@ -9671,17 +9527,17 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "MAIN_CLK" (rect 3370 1336 3439 1351)(font "Arial" ))
+	(text "MAIN_CLK" (rect 3370 1336 3424 1348)(font "Arial" ))
 	(pt 3448 1352)
 	(pt 3360 1352)
 )
 (connector
-	(text "PIXEL_CLK" (rect 3370 1352 3445 1367)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 3370 1352 3426 1364)(font "Arial" ))
 	(pt 3448 1368)
 	(pt 3360 1368)
 )
 (connector
-	(text "CLUT_ADR[3..0]" (rect 3338 1288 3444 1303)(font "Arial" ))
+	(text "CLUT_ADR[3..0]" (rect 3338 1288 3421 1300)(font "Arial" ))
 	(pt 3336 1304)
 	(pt 3448 1304)
 	(bus)
@@ -9691,19 +9547,19 @@ applicable agreement for further details.
 	(pt 3448 1320)
 )
 (connector
-	(text "FB_AD[26..24]" (rect 3930 792 4022 807)(font "Arial" ))
+	(text "FB_AD[26..24]" (rect 3930 792 4003 804)(font "Arial" ))
 	(pt 3920 808)
 	(pt 4032 808)
 	(bus)
 )
 (connector
-	(text "FB_AD[22..20]" (rect 3930 1000 4022 1015)(font "Arial" ))
+	(text "FB_AD[22..20]" (rect 3930 1000 4003 1012)(font "Arial" ))
 	(pt 3920 1016)
 	(pt 4032 1016)
 	(bus)
 )
 (connector
-	(text "FB_AD[18..16]" (rect 3930 1208 4022 1223)(font "Arial" ))
+	(text "FB_AD[18..16]" (rect 3930 1208 4003 1220)(font "Arial" ))
 	(pt 3920 1224)
 	(pt 4032 1224)
 	(bus)
@@ -9713,7 +9569,7 @@ applicable agreement for further details.
 	(pt 3880 840)
 )
 (connector
-	(text "ST_CLUT_RD" (rect 3802 824 3895 839)(font "Arial" ))
+	(text "ST_CLUT_RD" (rect 3802 824 3871 836)(font "Arial" ))
 	(pt 3880 840)
 	(pt 3792 840)
 )
@@ -9722,7 +9578,7 @@ applicable agreement for further details.
 	(pt 3880 1048)
 )
 (connector
-	(text "ST_CLUT_RD" (rect 3802 1032 3895 1047)(font "Arial" ))
+	(text "ST_CLUT_RD" (rect 3802 1032 3871 1044)(font "Arial" ))
 	(pt 3880 1048)
 	(pt 3792 1048)
 )
@@ -9731,75 +9587,75 @@ applicable agreement for further details.
 	(pt 3880 1256)
 )
 (connector
-	(text "ST_CLUT_RD" (rect 3802 1240 3895 1255)(font "Arial" ))
+	(text "ST_CLUT_RD" (rect 3802 1240 3871 1252)(font "Arial" ))
 	(pt 3880 1256)
 	(pt 3792 1256)
 )
 (connector
-	(text "ST_CLUT_WR1" (rect 3346 1240 3449 1255)(font "Arial" ))
+	(text "ST_CLUT_WR1" (rect 3346 1240 3423 1252)(font "Arial" ))
 	(pt 3448 1256)
 	(pt 3336 1256)
 )
 (connector
-	(text "ST_CLUT_WR0" (rect 3346 824 3449 839)(font "Arial" ))
+	(text "ST_CLUT_WR0" (rect 3346 824 3423 836)(font "Arial" ))
 	(pt 3448 840)
 	(pt 3336 840)
 )
 (connector
-	(text "ST_CLUT_WR1" (rect 3346 1032 3449 1047)(font "Arial" ))
+	(text "ST_CLUT_WR1" (rect 3346 1032 3423 1044)(font "Arial" ))
 	(pt 3448 1048)
 	(pt 3336 1048)
 )
 (connector
-	(text "CCS[15..13]" (rect 3826 1064 3903 1079)(font "Arial" ))
+	(text "CCS[15..13]" (rect 3826 1064 3887 1076)(font "Arial" ))
 	(pt 3920 1080)
 	(pt 3704 1080)
 	(bus)
 )
 (connector
-	(text "CCS[12..8]" (rect 3826 1096 3895 1111)(font "Arial" ))
+	(text "CCS[12..8]" (rect 3826 1096 3881 1108)(font "Arial" ))
 	(pt 3816 1112)
 	(pt 3920 1112)
 	(bus)
 )
 (connector
-	(text "CCS[23..21]" (rect 3810 856 3887 871)(font "Arial" ))
+	(text "CCS[23..21]" (rect 3810 856 3871 868)(font "Arial" ))
 	(pt 3904 872)
 	(pt 3704 872)
 	(bus)
 )
 (connector
-	(text "CCS[20..16]" (rect 3818 888 3895 903)(font "Arial" ))
+	(text "CCS[20..16]" (rect 3818 888 3879 900)(font "Arial" ))
 	(pt 3808 904)
 	(pt 3904 904)
 	(bus)
 )
 (connector
-	(text "CCS[7..5]" (rect 3714 1272 3775 1287)(font "Arial" ))
+	(text "CCS[7..5]" (rect 3714 1272 3763 1284)(font "Arial" ))
 	(pt 3920 1288)
 	(pt 3704 1288)
 	(bus)
 )
 (connector
-	(text "CCS[4..0]" (rect 3818 1304 3879 1319)(font "Arial" ))
+	(text "CCS[4..0]" (rect 3818 1304 3867 1316)(font "Arial" ))
 	(pt 3808 1320)
 	(pt 3920 1320)
 	(bus)
 )
 (connector
-	(text "FB_AD[26..24]" (rect 3346 792 3438 807)(font "Arial" ))
+	(text "FB_AD[26..24]" (rect 3346 792 3419 804)(font "Arial" ))
 	(pt 3336 808)
 	(pt 3448 808)
 	(bus)
 )
 (connector
-	(text "FB_ADR[4..1]" (rect 3346 808 3432 823)(font "Arial" ))
+	(text "FB_ADR[4..1]" (rect 3346 808 3415 820)(font "Arial" ))
 	(pt 3336 824)
 	(pt 3448 824)
 	(bus)
 )
 (connector
-	(text "CLUT_ADR[3..0]" (rect 3338 872 3444 887)(font "Arial" ))
+	(text "CLUT_ADR[3..0]" (rect 3338 872 3421 884)(font "Arial" ))
 	(pt 3336 888)
 	(pt 3448 888)
 	(bus)
@@ -9809,19 +9665,19 @@ applicable agreement for further details.
 	(pt 3448 904)
 )
 (connector
-	(text "FB_AD[22..20]" (rect 3346 1000 3438 1015)(font "Arial" ))
+	(text "FB_AD[22..20]" (rect 3346 1000 3419 1012)(font "Arial" ))
 	(pt 3336 1016)
 	(pt 3448 1016)
 	(bus)
 )
 (connector
-	(text "FB_ADR[4..1]" (rect 3346 1016 3432 1031)(font "Arial" ))
+	(text "FB_ADR[4..1]" (rect 3346 1016 3415 1028)(font "Arial" ))
 	(pt 3336 1032)
 	(pt 3448 1032)
 	(bus)
 )
 (connector
-	(text "CLUT_ADR[3..0]" (rect 3338 1080 3444 1095)(font "Arial" ))
+	(text "CLUT_ADR[3..0]" (rect 3338 1080 3421 1092)(font "Arial" ))
 	(pt 3336 1096)
 	(pt 3448 1096)
 	(bus)
@@ -9831,128 +9687,122 @@ applicable agreement for further details.
 	(pt 3448 1112)
 )
 (connector
-	(text "FB_AD[18..16]" (rect 3346 1208 3438 1223)(font "Arial" ))
+	(text "FB_AD[18..16]" (rect 3346 1208 3419 1220)(font "Arial" ))
 	(pt 3336 1224)
 	(pt 3448 1224)
 	(bus)
 )
 (connector
-	(text "FB_ADR[4..1]" (rect 3346 1224 3432 1239)(font "Arial" ))
+	(text "FB_ADR[4..1]" (rect 3346 1224 3415 1236)(font "Arial" ))
 	(pt 3336 1240)
 	(pt 3448 1240)
 	(bus)
 )
 (connector
-	(text "ACP_CLUT_WR1" (rect 3314 2112 3428 2127)(font "Arial" ))
+	(text "ACP_CLUT_WR1" (rect 3314 2112 3401 2124)(font "Arial" ))
 	(pt 3304 2128)
 	(pt 3448 2128)
 )
 (connector
-	(text "FB_AD[23..16]" (rect 3874 2080 3966 2095)(font "Arial" ))
+	(text "FB_AD[23..16]" (rect 3874 2080 3947 2092)(font "Arial" ))
 	(pt 3960 2096)
 	(pt 3864 2096)
 	(bus)
 )
 (connector
-	(text "FB_AD[15..8]" (rect 3874 2288 3957 2303)(font "Arial" ))
+	(text "FB_AD[15..8]" (rect 3874 2288 3941 2300)(font "Arial" ))
 	(pt 3864 2304)
 	(pt 3952 2304)
 	(bus)
 )
 (connector
-	(text "FB_AD[15..8]" (rect 3370 2288 3453 2303)(font "Arial" ))
+	(text "FB_AD[15..8]" (rect 3370 2288 3437 2300)(font "Arial" ))
 	(pt 3360 2304)
 	(pt 3448 2304)
 	(bus)
 )
 (connector
-	(text "FB_AD[7..0]" (rect 3874 2496 3949 2511)(font "Arial" ))
+	(text "FB_AD[7..0]" (rect 3874 2496 3935 2508)(font "Arial" ))
 	(pt 3864 2512)
 	(pt 3952 2512)
 	(bus)
 )
 (connector
-	(text "FB_AD[7..0]" (rect 3370 2496 3445 2511)(font "Arial" ))
+	(text "FB_AD[7..0]" (rect 3370 2496 3431 2508)(font "Arial" ))
 	(pt 3360 2512)
 	(pt 3448 2512)
 	(bus)
 )
 (connector
-	(text "CCA[23..16]" (rect 3730 2144 3806 2159)(font "Arial" ))
+	(text "CCA[23..16]" (rect 3730 2144 3791 2156)(font "Arial" ))
 	(pt 3808 2160)
 	(pt 3704 2160)
 	(bus)
 )
 (connector
-	(text "CCA[15..8]" (rect 3730 2352 3798 2367)(font "Arial" ))
+	(text "CCA[15..8]" (rect 3730 2352 3785 2364)(font "Arial" ))
 	(pt 3808 2368)
 	(pt 3704 2368)
 	(bus)
 )
 (connector
-	(text "CCA[7..0]" (rect 3730 2560 3790 2575)(font "Arial" ))
+	(text "CCA[7..0]" (rect 3730 2560 3779 2572)(font "Arial" ))
 	(pt 3808 2576)
 	(pt 3704 2576)
 	(bus)
 )
 (connector
-	(text "FB_AD[23..16]" (rect 3362 2080 3454 2095)(font "Arial" ))
+	(text "FB_AD[23..16]" (rect 3362 2080 3435 2092)(font "Arial" ))
 	(pt 3448 2096)
 	(pt 3352 2096)
 	(bus)
 )
 (connector
-	(text "ZR_C8B[7..0]" (rect 3354 2576 3440 2591)(font "Arial" ))
+	(text "ZR_C8B[7..0]" (rect 3354 2576 3422 2588)(font "Arial" ))
 	(pt 3448 2592)
 	(pt 3344 2592)
 	(bus)
 )
 (connector
-	(text "ZR_C8B[7..0]" (rect 3362 2368 3448 2383)(font "Arial" ))
+	(text "ZR_C8B[7..0]" (rect 3362 2368 3430 2380)(font "Arial" ))
 	(pt 3448 2384)
 	(pt 3352 2384)
 	(bus)
 )
 (connector
-	(text "ZR_C8B[7..0]" (rect 3362 2160 3448 2175)(font "Arial" ))
+	(text "ZR_C8B[7..0]" (rect 3362 2160 3430 2172)(font "Arial" ))
 	(pt 3448 2176)
 	(pt 3352 2176)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3266 2304 3352 2319)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3266 2304 3335 2316)(font "Arial" ))
 	(pt 3448 2320)
 	(pt 3256 2320)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3266 2096 3352 2111)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3266 2096 3335 2108)(font "Arial" ))
 	(pt 3448 2112)
 	(pt 3256 2112)
 	(bus)
 )
 (connector
-	(text "FB_ADR[9..2]" (rect 3266 2512 3352 2527)(font "Arial" ))
+	(text "FB_ADR[9..2]" (rect 3266 2512 3335 2524)(font "Arial" ))
 	(pt 3448 2528)
 	(pt 3256 2528)
 	(bus)
 )
 (connector
-	(text "ACP_CLUT_WR3" (rect 3346 2528 3460 2543)(font "Arial" ))
+	(text "ACP_CLUT_WR3" (rect 3346 2528 3433 2540)(font "Arial" ))
 	(pt 3448 2544)
 	(pt 3336 2544)
 )
 (connector
-	(text "ACP_CLUT_WR2" (rect 3346 2320 3460 2335)(font "Arial" ))
+	(text "ACP_CLUT_WR2" (rect 3346 2320 3433 2332)(font "Arial" ))
 	(pt 3448 2336)
 	(pt 3336 2336)
 )
-(connector
-	(text "FIFO_MW[8..0]" (rect 1882 1384 1975 1399)(font "Arial" ))
-	(pt 1952 1400)
-	(pt 1872 1400)
-	(bus)
-)
 (connector
 	(pt 2000 1408)
 	(pt 1984 1408)
@@ -10007,12 +9857,12 @@ applicable agreement for further details.
 	(pt 2088 1512)
 )
 (connector
-	(text "INTER_ZEI" (rect 1994 1496 2065 1511)(font "Arial" ))
+	(text "INTER_ZEI" (rect 1994 1496 2050 1508)(font "Arial" ))
 	(pt 1984 1512)
 	(pt 2088 1512)
 )
 (connector
-	(text "INTER_ZEI" (rect 1362 1424 1433 1439)(font "Arial" ))
+	(text "INTER_ZEI" (rect 1362 1424 1418 1436)(font "Arial" ))
 	(pt 1352 1440)
 	(pt 1456 1440)
 )
@@ -10021,410 +9871,410 @@ applicable agreement for further details.
 	(pt 1536 1440)
 )
 (connector
-	(text "VDVZ[127..0]" (rect 1090 1120 1172 1135)(font "Arial" ))
+	(text "VDVZ[127..0]" (rect 1090 1120 1157 1132)(font "Arial" ))
 	(pt 1088 1136)
 	(pt 1160 1136)
 	(bus)
 )
 (connector
-	(text "DOP_FIFO_CLR" (rect 1978 1280 2085 1295)(font "Arial" ))
+	(text "DOP_FIFO_CLR" (rect 1978 1280 2061 1292)(font "Arial" ))
 	(pt 2072 1296)
 	(pt 1992 1296)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2002 1256 2077 1271)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2002 1256 2058 1268)(font "Arial" ))
 	(pt 2072 1272)
 	(pt 1992 1272)
 )
 (connector
-	(text "VDVZ[127..96]" (rect 1450 936 1540 951)(font "Arial" ))
+	(text "VDVZ[127..96]" (rect 1450 936 1523 948)(font "Arial" ))
 	(pt 1440 952)
 	(pt 1520 952)
 	(bus)
 )
 (connector
-	(text "VDVZ[63..32]" (rect 1194 920 1276 935)(font "Arial" ))
+	(text "VDVZ[63..32]" (rect 1194 920 1261 932)(font "Arial" ))
 	(pt 1184 936)
 	(pt 1296 936)
 	(bus)
 )
 (connector
-	(text "VDP_IN[31..0]" (rect 962 992 1051 1007)(font "Arial" ))
+	(text "VDP_IN[31..0]" (rect 962 992 1033 1004)(font "Arial" ))
 	(pt 952 1008)
 	(pt 1040 1008)
 	(bus)
 )
 (connector
-	(text "VDVZ[95..64]" (rect 1450 1024 1532 1039)(font "Arial" ))
+	(text "VDVZ[95..64]" (rect 1450 1024 1517 1036)(font "Arial" ))
 	(pt 1440 1040)
 	(pt 1520 1040)
 	(bus)
 )
 (connector
-	(text "VDVZ[31..0]" (rect 1194 1008 1268 1023)(font "Arial" ))
+	(text "VDVZ[31..0]" (rect 1194 1008 1255 1020)(font "Arial" ))
 	(pt 1184 1024)
 	(pt 1296 1024)
 	(bus)
 )
 (connector
-	(text "VDP_IN[63..32]" (rect 962 904 1059 919)(font "Arial" ))
+	(text "VDP_IN[63..32]" (rect 962 904 1039 916)(font "Arial" ))
 	(pt 952 920)
 	(pt 1040 920)
 	(bus)
 )
 (connector
-	(text "DDRCLK0" (rect 978 920 1046 935)(font "Arial" ))
+	(text "DDRCLK0" (rect 978 920 1029 932)(font "Arial" ))
 	(pt 1040 936)
 	(pt 968 936)
 )
 (connector
-	(text "DDRCLK0" (rect 978 1008 1046 1023)(font "Arial" ))
+	(text "DDRCLK0" (rect 978 1008 1029 1020)(font "Arial" ))
 	(pt 1040 1024)
 	(pt 968 1024)
 )
 (connector
-	(text "DDRCLK0" (rect 1234 936 1302 951)(font "Arial" ))
+	(text "DDRCLK0" (rect 1234 936 1285 948)(font "Arial" ))
 	(pt 1296 952)
 	(pt 1224 952)
 )
 (connector
-	(text "DDRCLK0" (rect 1234 1024 1302 1039)(font "Arial" ))
+	(text "DDRCLK0" (rect 1234 1024 1285 1036)(font "Arial" ))
 	(pt 1224 1040)
 	(pt 1296 1040)
 )
 (connector
-	(text "DDRCLK0" (rect 1098 1136 1166 1151)(font "Arial" ))
+	(text "DDRCLK0" (rect 1098 1136 1149 1148)(font "Arial" ))
 	(pt 1160 1152)
 	(pt 1088 1152)
 )
 (connector
-	(text "DDRCLK0" (rect 1338 1160 1406 1175)(font "Arial" ))
+	(text "DDRCLK0" (rect 1338 1160 1389 1172)(font "Arial" ))
 	(pt 1400 1176)
 	(pt 1328 1176)
 )
 (connector
-	(text "VDMB[127..0]" (rect 1554 1168 1640 1183)(font "Arial" ))
+	(text "VDMB[127..0]" (rect 1554 1168 1622 1180)(font "Arial" ))
 	(pt 1544 1184)
 	(pt 1624 1184)
 	(bus)
 )
 (connector
-	(text "VDMA[127..0]" (rect 1314 1144 1398 1159)(font "Arial" ))
+	(text "VDMA[127..0]" (rect 1314 1144 1382 1156)(font "Arial" ))
 	(pt 1304 1160)
 	(pt 1400 1160)
 	(bus)
 )
 (connector
-	(text "VDMC[127..0]" (rect 1642 1344 1729 1359)(font "Arial" ))
+	(text "VDMC[127..0]" (rect 1642 1344 1711 1356)(font "Arial" ))
 	(pt 1640 1360)
 	(pt 1712 1360)
 	(bus)
 )
 (connector
-	(text "VDMC[127..0]" (rect 1970 960 2057 975)(font "Arial" ))
+	(text "VDMC[127..0]" (rect 1970 960 2039 972)(font "Arial" ))
 	(pt 1968 976)
 	(pt 2040 976)
 	(bus)
 )
 (connector
-	(text "VDM_SEL[3..0]" (rect 570 2416 665 2431)(font "Arial" ))
+	(text "VDM_SEL[3..0]" (rect 570 2416 645 2428)(font "Arial" ))
 	(pt 560 2432)
 	(pt 656 2432)
 	(bus)
 )
 (connector
-	(text "VDMB[127..0]" (rect 1586 1080 1672 1095)(font "Arial" ))
+	(text "VDMB[127..0]" (rect 1586 1080 1654 1092)(font "Arial" ))
 	(pt 1576 1096)
 	(pt 1800 1096)
 	(bus)
 )
 (connector
-	(text "VDMB[119..0],VDMA[127..120]" (rect 1586 1064 1777 1079)(font "Arial" ))
+	(text "VDMB[119..0],VDMA[127..120]" (rect 1586 1064 1738 1076)(font "Arial" ))
 	(pt 1576 1080)
 	(pt 1800 1080)
 	(bus)
 )
 (connector
-	(text "VDMB[111..0],VDMA[127..112]" (rect 1586 1048 1777 1063)(font "Arial" ))
+	(text "VDMB[111..0],VDMA[127..112]" (rect 1586 1048 1738 1060)(font "Arial" ))
 	(pt 1576 1064)
 	(pt 1800 1064)
 	(bus)
 )
 (connector
-	(text "VDMB[103..0],VDMA[127..104]" (rect 1586 1032 1777 1047)(font "Arial" ))
+	(text "VDMB[103..0],VDMA[127..104]" (rect 1586 1032 1738 1044)(font "Arial" ))
 	(pt 1576 1048)
 	(pt 1800 1048)
 	(bus)
 )
 (connector
-	(text "VDMB[95..0],VDMA[127..96]" (rect 1586 1016 1760 1031)(font "Arial" ))
+	(text "VDMB[95..0],VDMA[127..96]" (rect 1586 1016 1726 1028)(font "Arial" ))
 	(pt 1576 1032)
 	(pt 1800 1032)
 	(bus)
 )
 (connector
-	(text "VDMB[87..0],VDMA[127..88]" (rect 1586 1000 1760 1015)(font "Arial" ))
+	(text "VDMB[87..0],VDMA[127..88]" (rect 1586 1000 1726 1012)(font "Arial" ))
 	(pt 1576 1016)
 	(pt 1800 1016)
 	(bus)
 )
 (connector
-	(text "VDMB[79..0],VDMA[127..80]" (rect 1586 984 1760 999)(font "Arial" ))
+	(text "VDMB[79..0],VDMA[127..80]" (rect 1586 984 1726 996)(font "Arial" ))
 	(pt 1576 1000)
 	(pt 1800 1000)
 	(bus)
 )
 (connector
-	(text "VDMB[71..0],VDMA[127..72]" (rect 1586 968 1760 983)(font "Arial" ))
+	(text "VDMB[71..0],VDMA[127..72]" (rect 1586 968 1726 980)(font "Arial" ))
 	(pt 1576 984)
 	(pt 1800 984)
 	(bus)
 )
 (connector
-	(text "VDMB[63..0],VDMA[127..64]" (rect 1586 952 1760 967)(font "Arial" ))
+	(text "VDMB[63..0],VDMA[127..64]" (rect 1586 952 1726 964)(font "Arial" ))
 	(pt 1576 968)
 	(pt 1800 968)
 	(bus)
 )
 (connector
-	(text "VDMB[55..0],VDMA[127..56]" (rect 1586 936 1760 951)(font "Arial" ))
+	(text "VDMB[55..0],VDMA[127..56]" (rect 1586 936 1726 948)(font "Arial" ))
 	(pt 1576 952)
 	(pt 1800 952)
 	(bus)
 )
 (connector
-	(text "VDMB[47..0],VDMA[127..48]" (rect 1586 920 1760 935)(font "Arial" ))
+	(text "VDMB[47..0],VDMA[127..48]" (rect 1586 920 1726 932)(font "Arial" ))
 	(pt 1576 936)
 	(pt 1800 936)
 	(bus)
 )
 (connector
-	(text "VDMB[39..0],VDMA[127..40]" (rect 1586 904 1760 919)(font "Arial" ))
+	(text "VDMB[39..0],VDMA[127..40]" (rect 1586 904 1726 916)(font "Arial" ))
 	(pt 1576 920)
 	(pt 1800 920)
 	(bus)
 )
 (connector
-	(text "VDMB[31..0],VDMA[127..32]" (rect 1586 888 1760 903)(font "Arial" ))
+	(text "VDMB[31..0],VDMA[127..32]" (rect 1586 888 1726 900)(font "Arial" ))
 	(pt 1576 904)
 	(pt 1800 904)
 	(bus)
 )
 (connector
-	(text "VDMB[23..0],VDMA[127..24]" (rect 1586 872 1760 887)(font "Arial" ))
+	(text "VDMB[23..0],VDMA[127..24]" (rect 1586 872 1726 884)(font "Arial" ))
 	(pt 1576 888)
 	(pt 1800 888)
 	(bus)
 )
 (connector
-	(text "VDMB[15..0],VDMA[127..16]" (rect 1586 856 1760 871)(font "Arial" ))
+	(text "VDMB[15..0],VDMA[127..16]" (rect 1586 856 1726 868)(font "Arial" ))
 	(pt 1576 872)
 	(pt 1800 872)
 	(bus)
 )
 (connector
-	(text "VDMB[7..0],VDMA[127..8]" (rect 1586 840 1744 855)(font "Arial" ))
+	(text "VDMB[7..0],VDMA[127..8]" (rect 1586 840 1714 852)(font "Arial" ))
 	(pt 1576 856)
 	(pt 1800 856)
 	(bus)
 )
 (connector
-	(text "FIFO_WRE" (rect 1098 1152 1169 1167)(font "Arial" ))
+	(text "FIFO_WRE" (rect 1098 1152 1155 1164)(font "Arial" ))
 	(pt 1088 1168)
 	(pt 1160 1168)
 )
 (connector
-	(text "FIFO_WRE" (rect 1338 1176 1409 1191)(font "Arial" ))
+	(text "FIFO_WRE" (rect 1338 1176 1395 1188)(font "Arial" ))
 	(pt 1328 1192)
 	(pt 1400 1192)
 )
 (connector
-	(text "FIFO_WRE" (rect 1650 1368 1721 1383)(font "Arial" ))
+	(text "FIFO_WRE" (rect 1650 1368 1707 1380)(font "Arial" ))
 	(pt 1640 1384)
 	(pt 1712 1384)
 )
 (connector
-	(text "nFB_BURST" (rect 1570 1896 1652 1911)(font "Arial" ))
+	(text "nFB_BURST" (rect 1570 1896 1632 1908)(font "Arial" ))
 	(pt 1560 1912)
 	(pt 1664 1912)
 )
 (connector
-	(text "nFB_OE" (rect 1570 1920 1624 1935)(font "Arial" ))
+	(text "nFB_OE" (rect 1570 1920 1611 1932)(font "Arial" ))
 	(pt 1560 1936)
 	(pt 1664 1936)
 )
 (connector
-	(text "nRSTO" (rect 1570 1704 1617 1719)(font "Arial" ))
+	(text "nRSTO" (rect 1570 1704 1605 1716)(font "Arial" ))
 	(pt 1560 1720)
 	(pt 1664 1720)
 )
 (connector
-	(text "MAIN_CLK" (rect 1570 1728 1639 1743)(font "Arial" ))
+	(text "MAIN_CLK" (rect 1570 1728 1624 1740)(font "Arial" ))
 	(pt 1664 1744)
 	(pt 1560 1744)
 )
 (connector
-	(text "nFB_CS1" (rect 1570 1752 1632 1767)(font "Arial" ))
+	(text "nFB_CS1" (rect 1570 1752 1617 1764)(font "Arial" ))
 	(pt 1560 1768)
 	(pt 1664 1768)
 )
 (connector
-	(text "nFB_CS2" (rect 1570 1776 1632 1791)(font "Arial" ))
+	(text "nFB_CS2" (rect 1570 1776 1617 1788)(font "Arial" ))
 	(pt 1560 1792)
 	(pt 1664 1792)
 )
 (connector
-	(text "nFB_CS3" (rect 1570 1800 1632 1815)(font "Arial" ))
+	(text "nFB_CS3" (rect 1570 1800 1617 1812)(font "Arial" ))
 	(pt 1560 1816)
 	(pt 1664 1816)
 )
 (connector
-	(text "nFB_WR" (rect 1570 1824 1627 1839)(font "Arial" ))
+	(text "nFB_WR" (rect 1570 1824 1614 1836)(font "Arial" ))
 	(pt 1560 1840)
 	(pt 1664 1840)
 )
 (connector
-	(text "FB_SIZE0" (rect 1570 1848 1634 1863)(font "Arial" ))
+	(text "FB_SIZE0" (rect 1570 1848 1620 1860)(font "Arial" ))
 	(pt 1560 1864)
 	(pt 1664 1864)
 )
 (connector
-	(text "FB_SIZE1" (rect 1570 1872 1634 1887)(font "Arial" ))
+	(text "FB_SIZE1" (rect 1570 1872 1620 1884)(font "Arial" ))
 	(pt 1560 1888)
 	(pt 1664 1888)
 )
 (connector
-	(text "FB_AD[31..0]" (rect 2026 1720 2109 1735)(font "Arial" ))
+	(text "FB_AD[31..0]" (rect 2026 1720 2093 1732)(font "Arial" ))
 	(pt 2136 1736)
 	(pt 2016 1736)
 	(bus)
 )
 (connector
-	(text "FB_ADR[31..0]" (rect 1570 1944 1664 1959)(font "Arial" ))
+	(text "FB_ADR[31..0]" (rect 1570 1944 1645 1956)(font "Arial" ))
 	(pt 1664 1960)
 	(pt 1560 1960)
 	(bus)
 )
 (connector
-	(text "ACP_CLUT_RD" (rect 2026 1968 2129 1983)(font "Arial" ))
+	(text "ACP_CLUT_RD" (rect 2026 1968 2105 1980)(font "Arial" ))
 	(pt 2016 1984)
 	(pt 2112 1984)
 )
 (connector
-	(text "PIXEL_CLK" (rect 2026 2224 2101 2239)(font "Arial" ))
+	(text "PIXEL_CLK" (rect 2026 2224 2082 2236)(font "Arial" ))
 	(pt 2104 2240)
 	(pt 2016 2240)
 )
 (connector
-	(text "ST_CLUT_RD" (rect 2026 2096 2119 2111)(font "Arial" ))
+	(text "ST_CLUT_RD" (rect 2026 2096 2095 2108)(font "Arial" ))
 	(pt 2016 2112)
 	(pt 2120 2112)
 )
 (connector
-	(text "FALCON_CLUT_RDH" (rect 2026 2024 2168 2039)(font "Arial" ))
+	(text "FALCON_CLUT_RDH" (rect 2026 2024 2135 2036)(font "Arial" ))
 	(pt 2016 2040)
 	(pt 2120 2040)
 )
 (connector
-	(text "FALCON_CLUT_RDL" (rect 2026 2000 2166 2015)(font "Arial" ))
+	(text "FALCON_CLUT_RDL" (rect 2026 2000 2133 2012)(font "Arial" ))
 	(pt 2016 2016)
 	(pt 2120 2016)
 )
 (connector
-	(text "ST_CLUT_WR[1..0]" (rect 2026 2120 2152 2135)(font "Arial" ))
+	(text "ST_CLUT_WR[1..0]" (rect 2026 2120 2123 2132)(font "Arial" ))
 	(pt 2016 2136)
 	(pt 2112 2136)
 	(bus)
 )
 (connector
-	(text "CLUT_MUX_ADR[3..0]" (rect 2026 2152 2169 2167)(font "Arial" ))
+	(text "CLUT_MUX_ADR[3..0]" (rect 2026 2152 2138 2164)(font "Arial" ))
 	(pt 2016 2168)
 	(pt 2120 2168)
 	(bus)
 )
 (connector
-	(text "HSYNC" (rect 2026 2248 2075 2263)(font "Arial" ))
+	(text "HSYNC" (rect 2026 2248 2066 2260)(font "Arial" ))
 	(pt 2104 2264)
 	(pt 2016 2264)
 )
 (connector
-	(text "VSYNC" (rect 2026 2272 2073 2287)(font "Arial" ))
+	(text "VSYNC" (rect 2026 2272 2064 2284)(font "Arial" ))
 	(pt 2104 2288)
 	(pt 2016 2288)
 )
 (connector
-	(text "nBLANK" (rect 2026 2296 2080 2311)(font "Arial" ))
+	(text "nBLANK" (rect 2026 2296 2067 2308)(font "Arial" ))
 	(pt 2104 2312)
 	(pt 2016 2312)
 )
 (connector
-	(text "nSYNC" (rect 2026 2320 2073 2335)(font "Arial" ))
+	(text "nSYNC" (rect 2026 2320 2063 2332)(font "Arial" ))
 	(pt 2104 2336)
 	(pt 2016 2336)
 )
 (connector
-	(text "nPD_VGA" (rect 2026 2344 2089 2359)(font "Arial" ))
+	(text "nPD_VGA" (rect 2026 2344 2075 2356)(font "Arial" ))
 	(pt 2104 2360)
 	(pt 2016 2360)
 )
 (connector
-	(text "CLUT_OFF[3..0]" (rect 2026 2072 2129 2087)(font "Arial" ))
+	(text "CLUT_OFF[3..0]" (rect 2026 2072 2108 2084)(font "Arial" ))
 	(pt 2016 2088)
 	(pt 2112 2088)
 	(bus)
 )
 (connector
-	(text "BLITTER_ON" (rect 2026 2488 2113 2503)(font "Arial" ))
+	(text "BLITTER_ON" (rect 2026 2488 2092 2500)(font "Arial" ))
 	(pt 2096 2504)
 	(pt 2016 2504)
 )
 (connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 2026 2368 2182 2383)(font "Arial" ))
+	(text "VIDEO_RAM_CTR[15..0]" (rect 2026 2368 2149 2380)(font "Arial" ))
 	(pt 2144 2384)
 	(pt 2016 2384)
 	(bus)
 )
 (connector
-	(text "CCR[23..0]" (rect 2026 2176 2096 2191)(font "Arial" ))
+	(text "CCR[23..0]" (rect 2026 2176 2082 2188)(font "Arial" ))
 	(pt 2096 2192)
 	(pt 2016 2192)
 	(bus)
 )
 (connector
-	(text "CCSEL[2..0]" (rect 2026 2200 2105 2215)(font "Arial" ))
+	(text "CCSEL[2..0]" (rect 2026 2200 2088 2212)(font "Arial" ))
 	(pt 2016 2216)
 	(pt 2096 2216)
 	(bus)
 )
 (connector
-	(text "ACP_CLUT_WR[3..0]" (rect 2026 1944 2162 1959)(font "Arial" ))
+	(text "ACP_CLUT_WR[3..0]" (rect 2026 1944 2133 1956)(font "Arial" ))
 	(pt 2136 1960)
 	(pt 2016 1960)
 	(bus)
 )
 (connector
-	(text "FALCON_CLUT_WR[3..0]" (rect 2026 2048 2191 2063)(font "Arial" ))
+	(text "FALCON_CLUT_WR[3..0]" (rect 2026 2048 2155 2060)(font "Arial" ))
 	(pt 2144 2064)
 	(pt 2016 2064)
 	(bus)
 )
 (connector
-	(text "INTER_ZEI" (rect 2026 2400 2097 2415)(font "Arial" ))
+	(text "INTER_ZEI" (rect 2026 2400 2082 2412)(font "Arial" ))
 	(pt 2016 2416)
 	(pt 2136 2416)
 )
 (connector
-	(text "DOP_FIFO_CLR" (rect 2026 2424 2133 2439)(font "Arial" ))
+	(text "DOP_FIFO_CLR" (rect 2026 2424 2109 2436)(font "Arial" ))
 	(pt 2016 2440)
 	(pt 2128 2440)
 )
 (connector
-	(text "VIDEO_MOD_TA" (rect 2026 2520 2133 2535)(font "Arial" ))
+	(text "VIDEO_MOD_TA" (rect 2026 2520 2109 2532)(font "Arial" ))
 	(pt 2088 2536)
 	(pt 2016 2536)
 )
 (connector
-	(text "BLITTER_RUN" (rect 1546 2528 1643 2543)(font "Arial" ))
+	(text "BLITTER_RUN" (rect 1546 2528 1620 2540)(font "Arial" ))
 	(pt 1664 2544)
 	(pt 1536 2544)
 )
@@ -10434,7 +10284,7 @@ applicable agreement for further details.
 	(bus)
 )
 (connector
-	(text "VDM_SEL[3..0]" (rect 1810 1144 1905 1159)(font "Arial" ))
+	(text "VDM_SEL[3..0]" (rect 1810 1144 1885 1156)(font "Arial" ))
 	(pt 1888 1160)
 	(pt 1800 1160)
 	(bus)
@@ -10468,173 +10318,279 @@ applicable agreement for further details.
 	(pt 1920 1296)
 )
 (connector
-	(text "FIFO_RDE" (rect 1770 1272 1839 1287)(font "Arial" ))
+	(text "FIFO_RDE" (rect 1770 1272 1825 1284)(font "Arial" ))
 	(pt 1760 1288)
 	(pt 1856 1288)
 )
 (connector
-	(text "INTER_ZEI" (rect 1762 1288 1833 1303)(font "Arial" ))
+	(text "INTER_ZEI" (rect 1762 1288 1818 1300)(font "Arial" ))
 	(pt 1752 1304)
 	(pt 1856 1304)
 )
 (connector
-	(text "CLK33M" (rect 1586 2168 1641 2183)(font "Arial" ))
+	(text "CLK33M" (rect 1586 2168 1627 2180)(font "Arial" ))
 	(pt 1512 2184)
 	(pt 1664 2184)
 )
 (connector
-	(text "CLK25M" (rect 1586 2192 1641 2207)(font "Arial" ))
+	(text "CLK25M" (rect 1586 2192 1627 2204)(font "Arial" ))
 	(pt 1512 2208)
 	(pt 1664 2208)
 )
 (connector
-	(text "CLK_VIDEO" (rect 1570 2144 1649 2159)(font "Arial" ))
+	(text "CLK_VIDEO" (rect 1570 2144 1631 2156)(font "Arial" ))
 	(pt 1512 2160)
 	(pt 1664 2160)
 )
 (connector
-	(text "VIDEO_MOD_TA" (rect 258 1816 365 1831)(font "Arial" ))
+	(text "VIDEO_MOD_TA" (rect 258 1816 341 1828)(font "Arial" ))
 	(pt 264 1832)
 	(pt 360 1832)
 )
 (connector
-	(text "COLOR8" (rect 2026 1912 2085 1927)(font "Arial" ))
+	(text "COLOR8" (rect 2026 1912 2070 1924)(font "Arial" ))
 	(pt 2016 1928)
 	(pt 2120 1928)
 )
 (connector
-	(text "COLOR4" (rect 2026 1896 2085 1911)(font "Arial" ))
+	(text "COLOR4" (rect 2026 1896 2070 1908)(font "Arial" ))
 	(pt 2016 1912)
 	(pt 2120 1912)
 )
 (connector
-	(text "COLOR2" (rect 2026 1880 2085 1895)(font "Arial" ))
+	(text "COLOR2" (rect 2026 1880 2070 1892)(font "Arial" ))
 	(pt 2016 1896)
 	(pt 2120 1896)
 )
 (connector
-	(text "COLOR1" (rect 2026 1864 2085 1879)(font "Arial" ))
+	(text "COLOR1" (rect 2026 1864 2070 1876)(font "Arial" ))
 	(pt 2016 1880)
 	(pt 2120 1880)
 )
 (connector
-	(text "FIFO_RDE" (rect 2026 1736 2095 1751)(font "Arial" ))
+	(text "FIFO_RDE" (rect 2026 1736 2081 1748)(font "Arial" ))
 	(pt 2104 1752)
 	(pt 2016 1752)
 )
 (connector
-	(text "VIDEO_RECONFIG" (rect 2026 1688 2151 1703)(font "Arial" ))
+	(text "VIDEO_RECONFIG" (rect 2026 1688 2125 1700)(font "Arial" ))
 	(pt 2144 1704)
 	(pt 2016 1704)
 )
 (connector
-	(text "VR_WR" (rect 2026 1784 2076 1799)(font "Arial" ))
+	(text "VR_WR" (rect 2026 1784 2066 1796)(font "Arial" ))
 	(pt 2016 1800)
 	(pt 2112 1800)
 )
 (connector
-	(text "VR_RD" (rect 2026 1800 2074 1815)(font "Arial" ))
+	(text "VR_RD" (rect 2026 1800 2063 1812)(font "Arial" ))
 	(pt 2016 1816)
 	(pt 2112 1816)
 )
 (connector
-	(text "VR_D[8..0]" (rect 1570 2120 1638 2135)(font "Arial" ))
+	(text "VR_D[8..0]" (rect 1570 2120 1625 2132)(font "Arial" ))
 	(pt 1512 2136)
 	(pt 1664 2136)
 	(bus)
 )
 (connector
-	(text "VR_BUSY" (rect 1578 2104 1642 2119)(font "Arial" ))
+	(text "VR_BUSY" (rect 1578 2104 1629 2116)(font "Arial" ))
 	(pt 1512 2120)
 	(pt 1664 2120)
 )
 (connector
-	(text "CLR_FIFO" (rect 202 2216 270 2231)(font "Arial" ))
+	(text "CLR_FIFO" (rect 202 2216 256 2228)(font "Arial" ))
 	(pt 296 2232)
 	(pt 192 2232)
 )
 (connector
-	(text "CLR_FIFO" (rect 2026 1752 2094 1767)(font "Arial" ))
+	(text "CLR_FIFO" (rect 2026 1752 2080 1764)(font "Arial" ))
 	(pt 2016 1768)
 	(pt 2112 1768)
 )
 (connector
-	(text "CLR_FIFO" (rect 1634 1456 1702 1471)(font "Arial" ))
+	(text "CLR_FIFO" (rect 1634 1456 1688 1468)(font "Arial" ))
 	(pt 1712 1472)
 	(pt 1632 1472)
 )
 (connector
-	(text "BLITTER_DACK[4..0]" (rect 178 2864 313 2879)(font "Arial" ))
+	(text "BLITTER_DACK[4..0]" (rect 178 2864 284 2876)(font "Arial" ))
 	(pt 296 2880)
 	(pt 184 2880)
 	(bus)
 )
 (connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 154 2896 310 2911)(font "Arial" ))
+	(text "VIDEO_RAM_CTR[15..0]" (rect 154 2896 277 2908)(font "Arial" ))
 	(pt 296 2912)
 	(pt 144 2912)
 	(bus)
 )
 (connector
-	(text "BLITTER_ON" (rect 202 2920 289 2935)(font "Arial" ))
+	(text "BLITTER_ON" (rect 202 2920 268 2932)(font "Arial" ))
 	(pt 296 2936)
 	(pt 192 2936)
 )
 (connector
-	(text "BLITTER_DIN[127..0]" (rect 162 2944 300 2959)(font "Arial" ))
-	(pt 296 2960)
-	(pt 152 2960)
-	(bus)
-)
-(connector
-	(text "SR_BLITTER_DACK" (rect 778 2560 911 2575)(font "Arial" ))
-	(pt 904 2576)
-	(pt 768 2576)
-)
-(connector
-	(text "DDRCLK0" (rect 794 2544 862 2559)(font "Arial" ))
-	(pt 904 2560)
-	(pt 784 2560)
-)
-(connector
-	(text "BLITTER_DACK[4..0]" (rect 1058 2560 1193 2575)(font "Arial" ))
-	(pt 1176 2576)
-	(pt 1048 2576)
-	(bus)
-)
-(connector
-	(text "BLITTER_DOUT[127..0]" (rect 578 2744 731 2759)(font "Arial" ))
+	(text "BLITTER_DOUT[127..0]" (rect 578 2744 696 2756)(font "Arial" ))
 	(pt 712 2760)
 	(pt 568 2760)
 	(bus)
 )
 (connector
-	(text "BLITTER_ADR[31..0]" (rect 578 2776 712 2791)(font "Arial" ))
+	(text "BLITTER_ADR[31..0]" (rect 578 2776 683 2788)(font "Arial" ))
 	(pt 704 2792)
 	(pt 568 2792)
 	(bus)
 )
 (connector
-	(text "BLITTER_RUN" (rect 578 2712 675 2727)(font "Arial" ))
+	(text "BLITTER_RUN" (rect 578 2712 652 2724)(font "Arial" ))
 	(pt 672 2728)
 	(pt 568 2728)
 )
 (connector
-	(text "BLITTER_DACK[0]" (rect 778 2952 898 2967)(font "Arial" ))
-	(pt 776 2968)
-	(pt 888 2968)
-)
-(connector
-	(text "SR_BLITTER_DACK" (rect 170 2976 303 2991)(font "Arial" ))
+	(text "SR_BLITTER_DACK" (rect 170 2976 271 2988)(font "Arial" ))
 	(pt 296 2992)
 	(pt 160 2992)
 )
 (connector
-	(text "BLITTER_DIN[127..0]" (rect 1042 2944 1180 2959)(font "Arial" ))
-	(pt 1160 2960)
-	(pt 1032 2960)
+	(text "FIFO_MW[10..0]" (rect 1882 1384 1964 1396)(font "Arial" ))
+	(pt 1952 1400)
+	(pt 1872 1400)
 	(bus)
 )
+(connector
+	(text "FIFO_MW[10..0]" (rect 194 2376 276 2388)(font "Arial" ))
+	(pt 296 2392)
+	(pt 184 2392)
+	(bus)
+)
+(connector
+	(text "BLITTER_INT" (rect 578 2992 645 3004)(font "Arial" ))
+	(pt 568 3008)
+	(pt 672 3008)
+)
+(connector
+	(text "VDP_IN[63..0]" (rect 162 2944 233 2956)(font "Arial" ))
+	(pt 296 2960)
+	(pt 152 2960)
+	(bus)
+)
+(connector
+	(text "SR_BLITTER_DACK" (rect 794 2272 895 2284)(font "Arial" ))
+	(pt 920 2288)
+	(pt 784 2288)
+)
+(connector
+	(text "DDRCLK0" (rect 810 2256 861 2268)(font "Arial" ))
+	(pt 920 2272)
+	(pt 800 2272)
+)
+(connector
+	(text "BLITTER_DACK[4..0]" (rect 1074 2272 1180 2284)(font "Arial" ))
+	(pt 1192 2288)
+	(pt 1064 2288)
+	(bus)
+)
+(connector
+	(text "DDRCLK3" (rect 1290 1712 1341 1724)(font "Arial" ))
+	(pt 1288 1728)
+	(pt 1352 1728)
+)
+(connector
+	(text "SR_DDR_WR" (rect 1282 1696 1352 1708)(font "Arial" ))
+	(pt 1280 1712)
+	(pt 1352 1712)
+)
+(connector
+	(text "DDR_WR" (rect 1426 1696 1475 1708)(font "Arial" ))
+	(pt 1416 1712)
+	(pt 1480 1712)
+)
+(connector
+	(text "DDRCLK3" (rect 1170 2608 1221 2620)(font "Arial" ))
+	(pt 1160 2624)
+	(pt 1240 2624)
+)
+(connector
+	(text "VDM[3..0]" (rect 1482 2576 1531 2588)(font "Arial" ))
+	(pt 1536 2592)
+	(pt 1472 2592)
+	(bus)
+)
+(connector
+	(text "VDMP[7..4]" (rect 1170 2576 1226 2588)(font "Arial" ))
+	(pt 1160 2592)
+	(pt 1240 2592)
+	(bus)
+)
+(connector
+	(text "VDMP[3..0]" (rect 1170 2592 1226 2604)(font "Arial" ))
+	(pt 1160 2608)
+	(pt 1240 2608)
+	(bus)
+)
+(connector
+	(text "DDRCLK3" (rect 1290 1816 1341 1828)(font "Arial" ))
+	(pt 1288 1832)
+	(pt 1352 1832)
+)
+(connector
+	(text "SR_DDRWR_D_SEL" (rect 1250 1800 1355 1812)(font "Arial" ))
+	(pt 1248 1816)
+	(pt 1352 1816)
+)
+(connector
+	(text "DDRWR_D_SEL0" (rect 1426 1800 1515 1812)(font "Arial" ))
+	(pt 1416 1816)
+	(pt 1512 1816)
+)
+(connector
+	(text "VDOUT_OE" (rect 1426 1920 1485 1932)(font "Arial" ))
+	(pt 1416 1936)
+	(pt 1496 1936)
+)
+(connector
+	(text "DDR_WR" (rect 1298 1928 1347 1940)(font "Arial" ))
+	(pt 1288 1944)
+	(pt 1352 1944)
+)
+(connector
+	(text "SR_DDR_WR" (rect 1282 1912 1352 1924)(font "Arial" ))
+	(pt 1288 1928)
+	(pt 1352 1928)
+)
+(connector
+	(text "SR_FIFO_WRE" (rect 1258 2032 1337 2044)(font "Arial" ))
+	(pt 1336 2048)
+	(pt 1248 2048)
+)
+(connector
+	(text "FIFO_WRE" (rect 1490 2032 1547 2044)(font "Arial" ))
+	(pt 1480 2048)
+	(pt 1560 2048)
+)
+(connector
+	(text "DDRCLK0" (rect 1258 2016 1309 2028)(font "Arial" ))
+	(pt 1248 2032)
+	(pt 1336 2032)
+)
+(connector
+	(text "VDMP[7..0]" (rect 1082 2728 1138 2740)(font "Arial" ))
+	(pt 1072 2744)
+	(pt 1144 2744)
+	(bus)
+)
+(connector
+	(text "SR_VDMP[7..0]" (rect 842 2712 919 2724)(font "Arial" ))
+	(pt 832 2728)
+	(pt 928 2728)
+	(bus)
+)
+(connector
+	(text "DDRCLK2" (rect 858 2728 909 2740)(font "Arial" ))
+	(pt 848 2744)
+	(pt 928 2744)
+)
 (junction (pt 2984 1688))
 (junction (pt 792 1192))
 (junction (pt 792 1312))
diff --git a/FPGA_by_Fredi/Video/altdpram0_waveforms.html b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
deleted file mode 100644
index e0236fd..0000000
--- a/FPGA_by_Fredi/Video/altdpram0_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram0.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/altdpram1_waveforms.html b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
deleted file mode 100644
index 85b4369..0000000
--- a/FPGA_by_Fredi/Video/altdpram1_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/altdpram2_waveforms.html b/FPGA_by_Fredi/Video/altdpram2_waveforms.html
deleted file mode 100644
index a856bf6..0000000
--- a/FPGA_by_Fredi/Video/altdpram2_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram2.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_blitter.bsf b/FPGA_by_Fredi/Video/lpm_blitter.bsf
new file mode 100644
index 0000000..812ab9d
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_blitter.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_blitter" (rect 42 1 112 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[63..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[63..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "q[63..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[63..0]" (rect 89 50 125 63)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp b/FPGA_by_Fredi/Video/lpm_blitter.cmp
similarity index 81%
rename from FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp
rename to FPGA_by_Fredi/Video/lpm_blitter.cmp
index d428d99..295a940 100644
--- a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.cmp
+++ b/FPGA_by_Fredi/Video/lpm_blitter.cmp
@@ -13,11 +13,12 @@
 --applicable agreement for further details.
 
 
-component lpm_clshift0
+component lpm_blitter
 	PORT
 	(
-		data		: IN STD_LOGIC_VECTOR (255 DOWNTO 0);
-		distance		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
-		result		: OUT STD_LOGIC_VECTOR (255 DOWNTO 0)
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
 	);
 end component;
diff --git a/FPGA_by_Fredi/Video/lpm_blitter.inc b/FPGA_by_Fredi/Video/lpm_blitter.inc
new file mode 100644
index 0000000..875a095
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_blitter.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_blitter 
+(
+	clock,
+	data[63..0],
+	enable
+)
+
+RETURNS (
+	q[63..0]
+);
diff --git a/FPGA_by_Fredi/Video/lpm_blitter.qip b/FPGA_by_Fredi/Video/lpm_blitter.qip
new file mode 100644
index 0000000..ec4ba3f
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_blitter.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_blitter.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_blitter.cmp"]
diff --git a/FPGA_by_Fredi/Video/lpm_blitter.vhd b/FPGA_by_Fredi/Video/lpm_blitter.vhd
new file mode 100644
index 0000000..fba0b72
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_blitter.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_blitter.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_blitter IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+	);
+END lpm_blitter;
+
+
+ARCHITECTURE SYN OF lpm_blitter IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enable	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (63 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(63 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 64
+	)
+	PORT MAP (
+		enable => enable,
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "64"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_blitter_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
deleted file mode 100644
index e8242d9..0000000
--- a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for lpm_compare1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
-<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
-<P><FONT size=3></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf b/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
index 1e24640..3c8cdfc 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
@@ -21,53 +21,53 @@ applicable agreement for further details.
 (header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 160 144)
-	(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 125 31 140)(font "Arial" ))
+	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 128 25 140)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 56)
 		(input)
-		(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
 		(line (pt 0 56)(pt 16 56)(line_width 1))
 	)
 	(port
 		(pt 0 72)
 		(input)
-		(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
-		(text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
 		(line (pt 0 72)(pt 16 72)(line_width 1))
 	)
 	(port
 		(pt 0 96)
 		(input)
-		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8)))
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
 		(line (pt 0 96)(pt 16 96)(line_width 1))
 	)
 	(port
 		(pt 0 120)
 		(input)
-		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 114 37 127)(font "Arial" (font_size 8)))
 		(line (pt 0 120)(pt 16 120)(line_width 1))
 	)
 	(port
 		(pt 160 32)
 		(output)
-		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 26 141 39)(font "Arial" (font_size 8)))
 		(line (pt 160 32)(pt 144 32)(line_width 3))
 	)
 	(drawing
-		(text "(ack)" (rect 51 67 76 81)(font "Arial" ))
-		(text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" ))
+		(text "(ack)" (rect 51 67 72 79)(font "Arial" ))
+		(text "128 bits x 512 words" (rect 58 116 144 128)(font "Arial" ))
 		(line (pt 16 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 128)(line_width 1))
 		(line (pt 144 128)(pt 16 128)(line_width 1))
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd b/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
index 95486bb..55183b0 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
@@ -88,11 +88,11 @@ BEGIN
 	GENERIC MAP (
 		add_ram_output_register => "OFF",
 		intended_device_family => "Cyclone III",
-		lpm_numwords => 128,
+		lpm_numwords => 512,
 		lpm_showahead => "ON",
 		lpm_type => "scfifo",
 		lpm_width => 128,
-		lpm_widthu => 7,
+		lpm_widthu => 9,
 		overflow_checking => "OFF",
 		underflow_checking => "OFF",
 		use_eab => "ON"
@@ -119,7 +119,7 @@ END SYN;
 -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
 -- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
 -- Retrieval info: PRIVATE: Clock NUMERIC "0"
--- Retrieval info: PRIVATE: Depth NUMERIC "128"
+-- Retrieval info: PRIVATE: Depth NUMERIC "512"
 -- Retrieval info: PRIVATE: Empty NUMERIC "0"
 -- Retrieval info: PRIVATE: Full NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -147,11 +147,11 @@ END SYN;
 -- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
 -- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
 -- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
 -- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
 -- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
 -- Retrieval info: CONSTANT: USE_EAB STRING "ON"
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
deleted file mode 100644
index 467441f..0000000
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd".  The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
-<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf b/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
index 61b485b..1e46d64 100644
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2008 Altera Corporation
+Copyright (C) 1991-2010 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -68,8 +68,8 @@ applicable agreement for further details.
 	(port
 		(pt 160 72)
 		(output)
-		(text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
-		(text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
+		(text "wrusedw[10..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[10..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))
 		(line (pt 160 72)(pt 144 72)(line_width 3))
 	)
 	(port
@@ -79,15 +79,8 @@ applicable agreement for further details.
 		(text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8)))
 		(line (pt 160 96)(pt 144 96)(line_width 3))
 	)
-	(port
-		(pt 160 120)
-		(output)
-		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
-		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
-		(line (pt 160 120)(pt 144 120)(line_width 1))
-	)
 	(drawing
-		(text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" ))
+		(text "128 bits x 2048 words" (rect 53 140 144 152)(font "Arial" ))
 		(line (pt 16 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 152)(line_width 1))
 		(line (pt 144 152)(pt 16 152)(line_width 1))
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp b/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
index 08f6114..a3d9feb 100644
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
@@ -1,4 +1,4 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2010 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -23,7 +23,6 @@ component lpm_fifo_dc0
 		wrclk		: IN STD_LOGIC ;
 		wrreq		: IN STD_LOGIC ;
 		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
-		rdempty		: OUT STD_LOGIC ;
-		wrusedw		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
+		wrusedw		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
 	);
 end component;
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc b/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
index d29fb88..d8916c9 100644
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.inc
@@ -1,4 +1,4 @@
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2010 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -25,6 +25,5 @@ FUNCTION lpm_fifo_dc0
 
 RETURNS (
 	q[127..0],
-	rdempty,
-	wrusedw[8..0]
+	wrusedw[10..0]
 );
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip b/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
index e883724..5b251c2 100644
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.qip
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
-set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"]
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd b/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
index 8646d9c..e82b488 100644
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0.vhd
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2008 Altera Corporation
+--Copyright (C) 1991-2010 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -49,17 +49,15 @@ ENTITY lpm_fifo_dc0 IS
 		wrclk		: IN STD_LOGIC ;
 		wrreq		: IN STD_LOGIC ;
 		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
-		rdempty		: OUT STD_LOGIC ;
-		wrusedw		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
+		wrusedw		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
 	);
 END lpm_fifo_dc0;
 
 
 ARCHITECTURE SYN OF lpm_fifo_dc0 IS
 
-	SIGNAL sub_wire0	: STD_LOGIC ;
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (8 DOWNTO 0);
-	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (10 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (127 DOWNTO 0);
 
 
 
@@ -80,9 +78,8 @@ ARCHITECTURE SYN OF lpm_fifo_dc0 IS
 	);
 	PORT (
 			wrclk	: IN STD_LOGIC ;
-			rdempty	: OUT STD_LOGIC ;
 			rdreq	: IN STD_LOGIC ;
-			wrusedw	: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+			wrusedw	: OUT STD_LOGIC_VECTOR (10 DOWNTO 0);
 			aclr	: IN STD_LOGIC ;
 			rdclk	: IN STD_LOGIC ;
 			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
@@ -92,18 +89,17 @@ ARCHITECTURE SYN OF lpm_fifo_dc0 IS
 	END COMPONENT;
 
 BEGIN
-	rdempty    <= sub_wire0;
-	wrusedw    <= sub_wire1(8 DOWNTO 0);
-	q    <= sub_wire2(127 DOWNTO 0);
+	wrusedw    <= sub_wire0(10 DOWNTO 0);
+	q    <= sub_wire1(127 DOWNTO 0);
 
 	dcfifo_component : dcfifo
 	GENERIC MAP (
 		intended_device_family => "Cyclone III",
-		lpm_numwords => 512,
+		lpm_numwords => 2048,
 		lpm_showahead => "OFF",
 		lpm_type => "dcfifo",
 		lpm_width => 128,
-		lpm_widthu => 9,
+		lpm_widthu => 11,
 		overflow_checking => "OFF",
 		rdsync_delaypipe => 6,
 		underflow_checking => "OFF",
@@ -118,9 +114,8 @@ BEGIN
 		rdclk => rdclk,
 		wrreq => wrreq,
 		data => data,
-		rdempty => sub_wire0,
-		wrusedw => sub_wire1,
-		q => sub_wire2
+		wrusedw => sub_wire0,
+		q => sub_wire1
 	);
 
 
@@ -136,7 +131,7 @@ END SYN;
 -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
 -- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 -- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "512"
+-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
 -- Retrieval info: PRIVATE: Empty NUMERIC "1"
 -- Retrieval info: PRIVATE: Full NUMERIC "1"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -154,7 +149,7 @@ END SYN;
 -- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
 -- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
 -- Retrieval info: PRIVATE: output_width NUMERIC "128"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
 -- Retrieval info: PRIVATE: rsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
 -- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
@@ -163,11 +158,11 @@ END SYN;
 -- Retrieval info: PRIVATE: wsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
 -- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
 -- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
 -- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6"
 -- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
@@ -178,19 +173,17 @@ END SYN;
 -- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
 -- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
 -- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
--- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
 -- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
 -- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
 -- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+-- Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
 -- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
 -- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
 -- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
 -- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
 -- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
 -- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+-- Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
 -- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
deleted file mode 100644
index 3f52c1c..0000000
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for lpm_fifo_dc0.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_fifo_dc0.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd.  The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
-<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/altddio_out0.bsf b/FPGA_by_Fredi/altddio_out0.bsf
deleted file mode 100644
index 9889d79..0000000
--- a/FPGA_by_Fredi/altddio_out0.bsf
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2008 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
-	(rect 0 0 232 120)
-	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 104 25 116)(font "Arial" ))
-	(port
-		(pt 0 24)
-		(input)
-		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
-		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
-		(line (pt 0 24)(pt 88 24)(line_width 1))
-	)
-	(port
-		(pt 0 40)
-		(input)
-		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
-		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
-		(line (pt 0 40)(pt 88 40)(line_width 1))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
-		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 88 56)(line_width 1))
-	)
-	(port
-		(pt 232 24)
-		(output)
-		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
-		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
-		(line (pt 232 24)(pt 152 24)(line_width 1))
-	)
-	(drawing
-		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
-		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
-		(text "power up" (rect 92 74 129 86)(font "Arial" ))
-		(text "low" (rect 92 84 105 96)(font "Arial" ))
-		(line (pt 88 16)(pt 152 16)(line_width 1))
-		(line (pt 152 16)(pt 152 96)(line_width 1))
-		(line (pt 152 96)(pt 88 96)(line_width 1))
-		(line (pt 88 96)(pt 88 16)(line_width 1))
-	)
-)
diff --git a/FPGA_by_Fredi/blitter.tdf b/FPGA_by_Fredi/blitter.tdf
new file mode 100644
index 0000000..c92f2a8
--- /dev/null
+++ b/FPGA_by_Fredi/blitter.tdf
@@ -0,0 +1,604 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
+-- Created on Sat Jan 15 11:06:17 2011
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
+INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
+INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
+
+--CONSTANT	BL_SKEW_LF = 255;
+
+--  Title Statement (optional)
+TITLE "Blitter";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ON : INPUT;
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	DDRCLK0 : INPUT;
+	VDP_IN[63..0] : INPUT;
+	BLITTER_DACK[4..0] : INPUT;
+	SR_BLITTER_DACK : INPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_INT : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_ADR[31..0] : OUTPUT;
+	BLITTER_SIG : OUTPUT;
+	BLITTER_WR : OUTPUT;
+	BLITTER_TA : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	BLITTER_CS					:NODE;
+	BL_HRAM_CS 					:NODE;
+	BL_HRAM_BE[1..0]			:NODE;
+	BL_HRAM_OUT[15..0]			:NODE;
+	BL_DPRAM_OUT[15..0]			:NODE;
+	BL_SRC_X_INC_CS				:NODE;
+	BL_SRC_X_INC[15..0]			:DFFE;
+	SRC_XINC_NODE[31..0]		:NODE;
+	BL_SRC_Y_INC_CS				:NODE;
+	BL_SRC_Y_INC[15..0]			:DFFE;
+	SRC_YINC_NODE[31..0]		:NODE;
+	BL_ENDMASK1_CS				:NODE;
+	BL_ENDMASK1[15..0]			:DFFE;
+	BL_ENDMASK2_CS				:NODE;
+	BL_ENDMASK2[15..0]			:DFFE;
+	BL_ENDMASK3_CS				:NODE;
+	BL_ENDMASK3[15..0]			:DFFE;
+	BL_SRC_ADRH_CS				:NODE;
+	BL_SRC_ADRL_CS				:NODE;
+	BL_SRC_ADR[31..0]			:DFFE;
+	SRC_IADRH_CS				:NODE;
+	SRC_IADRL_CS				:NODE;
+	SRC_IADR[31..0]				:DFF;
+	SRC_IADR_CLR				:NODE;
+	SIINC						:NODE;
+	SRC_ADR_NODE[31..0]			:NODE;
+	BL_DST_X_INC_CS				:NODE;
+	BL_DST_X_INC[15..0]			:DFFE;
+	DST_XINC_NODE[31..0]		:NODE;
+	BL_DST_Y_INC_CS				:NODE;
+	BL_DST_Y_INC[15..0]			:DFFE;
+	DST_YINC_NODE[31..0]		:NODE;
+	BL_DST_ADRH_CS				:NODE;
+	BL_DST_ADRL_CS				:NODE;
+	BL_DST_ADR[31..0]			:DFFE;
+	DST_IADRH_CS				:NODE;
+	DST_IADRL_CS				:NODE;
+	DST_IADR[31..0]				:DFF;
+	DST_IADR_CLR				:NODE;
+	DST_ADR_NODE[31..0]			:NODE;
+	DIINC						:NODE;
+	BL_X_CNT_CS					:NODE;
+	BL_X_CNT[15..0]				:DFFE;
+	X_CNT_NODE[15..0]			:NODE;
+	BL_Y_CNT_CS					:NODE;
+	BL_Y_CNT[15..0]				:DFFE;
+	BL_HOP_CS					:NODE;
+	BL_HOP[7..0]				:DFFE;
+	BL_OP[7..0]					:DFFE;
+	BL_LN_CS					:NODE;
+	LN7CLR						:NODE;
+	BL_LN[7..0]					:DFFE;
+	BL_SKEW[7..0]				:DFFE;
+-- barell shifter
+	DIST_RIGHT[8..0]			:NODE;
+	BL_BS_SKEW[7..0]			:NODE;
+	BL_BSIN[383..0]				:NODE;
+	BL_BSOUT[383..0]			:NODE;
+	SHIFT_DIR					:NODE;
+	BL_SRC_BUF1[127..0]			:DFFE;
+	BL_SRC_BUF2[127..0]			:DFFE;
+	BL_SRC_BUF3[127..0]			:DFFE;
+	BL_DST_BUFRD[127..0]		:DFFE;	
+	BL_READ_DST					:NODE;				-- LATCH SIGNAL DST BUF RD
+	BL_READ_SRC					:NODE;				-- LATCH SIGNAL SRC BUF
+	SRC_READ					:NODE;				-- FREIGABE LATCH SIGNAL
+	NOT_DST_READ				:NODE;
+	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
+	X_INDEX_CS					:NODE;
+	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
+	X_INDEX_CLR					:NODE;
+	Y_INDEX_CS					:NODE;
+	Y_INDEX[15..0]				:DFF;				-- LAUFZEIGER Y COUNT
+	Y_INDEX_CLR					:NODE;
+	LINE_NR[3..0]				:NODE;
+	XIINC						:NODE;				-- INC INDEX SPALTE
+	YIINC						:NODE;				-- INC INDEX ZEILE
+	ZIINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
+	ZYINC						:NODE;				-- KORREKTUR ADRESSEN WENN FERTIG
+	HOP_OUT[127..0]				:NODE;
+	OP_OUT[127..0]				:NODE;
+	ENDMASK1_SHIFT[7..0]		:NODE;
+	ENDMASK2_SHIFT[7..0]		:NODE;
+	ENDMASK12_IN[143..0]		:NODE;
+	ENDMASK12_OUT[143..0]		:NODE;
+	ENDMASK23_IN[143..0]		:NODE;
+	ENDMASK23_OUT[143..0]		:NODE;
+	ENDMASK123[127..0]			:NODE;
+	DDR_RAM_FREE				:NODE;
+	SRC_DDR_ADR[31..0]			:NODE;
+	DST_DDR_ADR[31..0]			:NODE;
+	
+-- MAIN STATE MACHINE
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- wenn ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- or NOT BYT
+-- BLITTER CS
+	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";			-- FFFF8A00-7F  
+	BLITTER_TA = BLITTER_CS;
+-- REGISTER
+	-- HALFTON RAM 
+	BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50";						-- $F8A00-1F.w
+	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
+	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
+	WREN_B = B"0";
+	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	-- SRC X INC
+	BL_SRC_X_INC[].CLK = MAIN_CLK;
+	BL_SRC_X_INC[] = FB_AD[31..16];
+	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20.w
+	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
+	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- SRC Y INC
+	BL_SRC_Y_INC[].CLK = MAIN_CLK;
+	BL_SRC_Y_INC[] = FB_AD[31..16];
+	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22.w
+	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
+	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- SRC ADR HIGH
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[31..16] = FB_AD[31..16];
+	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24.w
+	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR LOW
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[15..0] = FB_AD[31..16];
+	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";				-- $F8A26.w
+	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
+	SRC_IADR[].CLK = DDRCLK0;
+	SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520";					-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521";					-- $F8A42.w
+	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
+	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	-- ENDMASK 1
+	BL_ENDMASK1[].CLK = MAIN_CLK;
+	BL_ENDMASK1[] = FB_AD[31..16];
+	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";				-- $F8A28.w
+	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 2
+	BL_ENDMASK2[].CLK = MAIN_CLK;
+	BL_ENDMASK2[] = FB_AD[31..16];
+	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";				-- $F8A2A.w
+	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 3
+	BL_ENDMASK3[].CLK = MAIN_CLK;
+	BL_ENDMASK3[] = FB_AD[31..16];
+	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";				-- $F8A2C.w
+	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
+	-- DST X INC
+	BL_DST_X_INC[].CLK = MAIN_CLK;
+	BL_DST_X_INC[] = FB_AD[31..16];
+	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";				-- $F8A2E.w
+	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
+	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- DST Y INC
+	BL_DST_Y_INC[].CLK = MAIN_CLK;
+	BL_DST_Y_INC[] = FB_AD[31..16];
+	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";				-- $F8A30.w
+	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
+	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- DST ADR HIGH
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[31..16] = FB_AD[31..16];
+	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519";				-- $F8A32.w
+	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
+	-- DST ADR LOW
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[15..0] = FB_AD[31..16];
+	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A";				-- $F8A34.w
+	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
+	DST_IADR[].CLK = DDRCLK0;
+	DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522";					-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523";					-- $F8A46.w
+	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
+	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	-- X COUNT
+	BL_X_CNT[].CLK = MAIN_CLK;
+	BL_X_CNT[] = FB_AD[31..16];
+	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";					-- $F8A36.w
+	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
+	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
+	X_INDEX[].CLK = DDRCLK0;
+	X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524";					-- $F8A48.w
+	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
+	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
+	-- Y COUNT
+	BL_Y_CNT[].CLK = MAIN_CLK;
+	BL_Y_CNT[] = FB_AD[31..16];
+	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";					-- $F8A38.w
+	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
+	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
+	Y_INDEX[].CLK = DDRCLK0;
+	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";					-- $F8A4A.w
+	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
+	-- HOP LOGIC
+	BL_HOP[].CLK = MAIN_CLK;
+	BL_HOP[] = FB_AD[31..24];
+	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A.w
+	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
+	-- OP LOGIC
+	BL_OP[].CLK = MAIN_CLK;
+	BL_OP[] = FB_AD[23..16];
+	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
+	-- LINE NUMBER BYT
+	BL_LN[].CLK = MAIN_CLK;
+	BL_LN[6..0] = FB_AD[30..24];	
+	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
+	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";						-- $F8A3C.w
+	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
+	BL_LN7.ENA = LN7CLR;
+	-- SKEW BYT
+	BL_SKEW[].CLK = MAIN_CLK;
+	BL_SKEW[] = FB_AD[23..16];
+	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						BL_HRAM_CS	    & BL_DPRAM_OUT[]
+					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
+					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
+					  # BL_SRC_ADRH_CS  & SRC_ADR_NODE[31..16]
+					  # BL_SRC_ADRL_CS  & SRC_ADR_NODE[15..0]
+					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
+					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
+					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
+					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
+					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
+					  # BL_DST_ADRH_CS  & DST_ADR_NODE[31..16]
+					  # BL_DST_ADRL_CS  & DST_ADR_NODE[15..0]
+					  # BL_X_CNT_CS 	& (BL_X_CNT[]-X_INDEX[])
+					  # BL_Y_CNT_CS 	& (BL_Y_CNT[]-Y_INDEX[])
+					  # BL_HOP_CS 		& (BL_HOP[],BL_OP[])
+					  # BL_LN_CS 		& (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])		
+					  # SRC_IADRH_CS	& SRC_IADR[31..16]
+					  # SRC_IADRL_CS	& SRC_IADR[15..0]
+					  # DST_IADRH_CS	& DST_IADR[31..16]
+					  # DST_IADRL_CS	& DST_IADR[15..0]
+					  # X_INDEX_CS		& X_INDEX[]
+					  # Y_INDEX_CS		& Y_INDEX[]
+					  ,BLITTER_CS & !nFB_OE); 											-- FFFF8A00-7F
+-----------------------------------------
+-- SRC BUFFER LADEN
+	BL_SRC_BUF1[].CLK = DDRCLK0;
+	BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF1[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]);
+	BL_SRC_BUF2[].CLK = DDRCLK0;
+	BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF2[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF2[] = BL_SRC_BUF1[];
+	BL_SRC_BUF3[].CLK = DDRCLK0;
+	BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF3[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF3[] = BL_SRC_BUF2[];
+	-- ZUORDNUNG ---------
+	IF BL_SRC_X_INC15 THEN		-- WENN NEGATIV -> REIHENFOLGE KEHREN
+		CASE BL_HOP[7..4] IS	-- SPIEGELN?
+			WHEN H"0" =>		-- LINE WEISE
+				BL_BSIN[127..0]   = BL_SRC_BUF3[];
+				BL_BSIN[255..128] = BL_SRC_BUF2[];
+				BL_BSIN[383..256] = BL_SRC_BUF1[];
+			WHEN H"1" =>		--- BIT WEISE
+				BL_BSIN[0..127]   = BL_SRC_BUF3[];
+				BL_BSIN[128..255] = BL_SRC_BUF2[];
+				BL_BSIN[256..383] = BL_SRC_BUF1[];
+			WHEN H"2" =>		-- BYT WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
+			WHEN H"3" =>		-- WORD WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
+			WHEN H"4" =>		-- LONG WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
+			WHEN OTHERS =>		-- LINE WEISE
+				BL_BSIN[127..0]   = BL_SRC_BUF3[];
+				BL_BSIN[255..128] = BL_SRC_BUF2[];
+				BL_BSIN[383..256] = BL_SRC_BUF1[];
+		END CASE;
+	ELSE						-- SONST NORMAL BEI VORWÄRTS
+		BL_BSIN[127..0]   = BL_SRC_BUF1[];
+		BL_BSIN[255..128] = BL_SRC_BUF2[];
+		BL_BSIN[383..256] = BL_SRC_BUF3[];
+	END IF;
+-- DST BUFFER READ	
+	BL_DST_BUFRD[].CLK = DDRCLK0;
+	BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST;
+	BL_DST_BUFRD[63..0].ENA   = BLITTER_DACK0 & BL_READ_DST;
+	BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
+-- barell shift *****************************************************************************
+-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
+	DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
+	IF DIST_RIGHT8 == 0 THEN 		
+		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
+		SHIFT_DIR = VCC;									-- DIR = RIGHT
+	else													
+		BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; 				-- LPM SHIFT LEFT
+		SHIFT_DIR = GND;									-- DIR = LEFT
+	end if;
+-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
+	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]);	-- wir brauchen 128bit
+-- HOP ***************************************************************************************
+	CASE BL_HOP[1..0] IS
+		WHEN H"0" =>
+					--    12345678901234567890123456789012
+			HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+		WHEN H"1" =>
+			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+		WHEN H"2" =>
+			HOP_OUT[] = BL_BSOUT[255..128];
+		WHEN OTHERS =>
+			HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]));
+	END CASE;
+-- OP *****************************************************************************************
+	CASE BL_OP[3..0] IS
+		WHEN H"0" =>
+			OP_OUT[] = H"0";
+			SRC_READ = B"0";
+		WHEN H"1" =>
+			OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"2" =>
+			OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"3" =>
+			OP_OUT[] = HOP_OUT[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"4" =>
+			OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"5" =>
+			OP_OUT[] = BL_DST_BUFRD[];
+			SRC_READ = B"0";
+		WHEN H"6" =>
+			OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"7" =>
+			OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"8" =>
+			OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"9" =>
+			OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"A" =>
+			OP_OUT[] = !BL_DST_BUFRD[];
+			SRC_READ = B"0";
+		WHEN H"B" =>
+			OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"C" =>
+			OP_OUT[] = !HOP_OUT[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"D" =>
+			OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"E" =>
+			OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN OTHERS =>
+					--   12345678901234567890123456789012
+			OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+			SRC_READ = B"0";
+	END CASE;
+------------ ENDMASKEN SETZEN ******************************************************************************																							 
+			ENDMASK1_SHIFT[3..0] = 0; 						
+			ENDMASK2_SHIFT[3..0] = 0; 						
+			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
+				IF X_INDEX[]==0 THEN															-- ENDE?	
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;	 
+				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;
+			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV
+				IF X_INDEX[]==0 THEN															-- ANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); 						-- JA -> ENDMASK 1 SETZEN 
+				ELSE		
+					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
+				END IF;		
+				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;	 
+			END IF;
+-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
+--				   1234567890123456789012345678
+	ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+	ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]);			-- IMMER rechts SCHIEBEN
+	ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
+	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
+	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
+	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
+	NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
+-- STATE MACHINE ****************************************************************************************************	
+	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
+	DDR_RAM_FREE = BLITTER_DACK[]==H"0";							-- 0 WENN FREI
+	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
+	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
+	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
+-- BLITTER MAIN STATE MACHINE  -----------------------------------------------
+	BL_SM.CLK = DDRCLK0;
+	CASE BL_SM IS
+		WHEN START =>   ------------------------- START
+			IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
+				BL_SM = NEW_LINE;
+			ELSE
+				BL_SM = START;
+			END IF;
+		WHEN NEW_LINE => ----------------------- NEU LINIE
+			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
+			BL_SM = RDSRC1;
+		WHEN RDSRC1 =>  ------------------------ READ SRC1
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					SIINC = VCC;							-- INC SRC ADR
+					BL_SM = RDSRC2;
+				ELSE	
+					BL_SM = RDSRC1;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
+		WHEN RDSRC2 =>	------------------------ READ SRC2
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					SIINC = VCC;							-- INC SRC ADR
+					BL_SM = RDDST;
+				ELSE	
+					BL_SM = RDSRC2;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
+		WHEN RDDST =>	----------------------- READ DEST
+			IF NOT_DST_READ THEN
+				BL_SM = WRDST;
+			ELSE
+				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_DST = VCC;
+				IF BLITTER_DACK0 THEN
+					BL_SM = WRDST;
+				ELSE	
+					BL_SM = RDDST;
+				END IF;
+			END IF;
+		WHEN WRDST =>	------------------- WRITE DEST
+			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+			BLITTER_WR = DDR_RAM_FREE;
+			BLITTER_SIG = DDR_RAM_FREE;
+			IF BLITTER_DACK0 THEN
+				XIINC = VCC;								-- INC X_INDEX
+				DIINC = VCC;								-- INC DEST ADR
+				BL_SM = TESTZEILENENDE;
+			ELSE	
+				BL_SM = WRDST;
+			END IF;
+		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
+			IF BL_X_CNT[]<=(X_CNT_NODE[])	 THEN			-- SCHON ZEILENENDE?	
+				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
+				BL_SM = TESTFERTIG;							-- ->
+			ELSE
+				BL_SM = RDSRC2;								-- NEIN NEXT
+			END IF;	
+		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
+			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
+			IF Y_INDEX[]>=BL_Y_CNT[] THEN					-- LETZTE ZEILE?
+				BL_SM = FERTIG;								-- JA -->
+			ELSE
+				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
+				BL_SM = NEW_LINE;							-- NEIN NEXT ->
+			END IF;
+		WHEN FERTIG => -------------------------- FERTIG
+			BLITTER_INT = VCC;								-- BLITTER INTERRUPT
+			LN7CLR = VCC;									-- BUSY BIT LÖSCHEN
+			IF BL_LN7==0 THEN								-- WARTEN BIS GELÖSCHT (GEHT NUR MIT 33MHz)
+				BL_SM = START;	
+			ELSE
+				BL_SM = FERTIG;
+			END IF;
+		WHEN OTHERS =>
+			BL_SM = FERTIG;
+	END CASE;
+END;
+
diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak
new file mode 100644
index 0000000..f06d03b
--- /dev/null
+++ b/FPGA_by_Fredi/blitter.tdf.bak
@@ -0,0 +1,604 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
+-- Created on Sat Jan 15 11:06:17 2011
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
+INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
+INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
+
+--CONSTANT	BL_SKEW_LF = 255;
+
+--  Title Statement (optional)
+TITLE "Blitter";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ON : INPUT;
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	DDRCLK0 : INPUT;
+	VDP_IN[63..0] : INPUT;
+	BLITTER_DACK[4..0] : INPUT;
+	SR_BLITTER_DACK : INPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_INT : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_ADR[31..0] : OUTPUT;
+	BLITTER_SIG : OUTPUT;
+	BLITTER_WR : OUTPUT;
+	BLITTER_TA : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	BLITTER_CS					:NODE;
+	BL_HRAM_CS 					:NODE;
+	BL_HRAM_BE[1..0]			:NODE;
+	BL_HRAM_OUT[15..0]			:NODE;
+	BL_DPRAM_OUT[15..0]			:NODE;
+	BL_SRC_X_INC_CS				:NODE;
+	BL_SRC_X_INC[15..0]			:DFFE;
+	SRC_XINC_NODE[31..0]		:NODE;
+	BL_SRC_Y_INC_CS				:NODE;
+	BL_SRC_Y_INC[15..0]			:DFFE;
+	SRC_YINC_NODE[31..0]		:NODE;
+	BL_ENDMASK1_CS				:NODE;
+	BL_ENDMASK1[15..0]			:DFFE;
+	BL_ENDMASK2_CS				:NODE;
+	BL_ENDMASK2[15..0]			:DFFE;
+	BL_ENDMASK3_CS				:NODE;
+	BL_ENDMASK3[15..0]			:DFFE;
+	BL_SRC_ADRH_CS				:NODE;
+	BL_SRC_ADRL_CS				:NODE;
+	BL_SRC_ADR[31..0]			:DFFE;
+	SRC_IADRH_CS				:NODE;
+	SRC_IADRL_CS				:NODE;
+	SRC_IADR[31..0]				:DFF;
+	SRC_IADR_CLR				:NODE;
+	SIINC						:NODE;
+	SRC_ADR_NODE[31..0]			:NODE;
+	BL_DST_X_INC_CS				:NODE;
+	BL_DST_X_INC[15..0]			:DFFE;
+	DST_XINC_NODE[31..0]		:NODE;
+	BL_DST_Y_INC_CS				:NODE;
+	BL_DST_Y_INC[15..0]			:DFFE;
+	DST_YINC_NODE[31..0]		:NODE;
+	BL_DST_ADRH_CS				:NODE;
+	BL_DST_ADRL_CS				:NODE;
+	BL_DST_ADR[31..0]			:DFFE;
+	DST_IADRH_CS				:NODE;
+	DST_IADRL_CS				:NODE;
+	DST_IADR[31..0]				:DFF;
+	DST_IADR_CLR				:NODE;
+	DST_ADR_NODE[31..0]			:NODE;
+	DIINC						:NODE;
+	BL_X_CNT_CS					:NODE;
+	BL_X_CNT[15..0]				:DFFE;
+	X_CNT_NODE[15..0]			:NODE;
+	BL_Y_CNT_CS					:NODE;
+	BL_Y_CNT[15..0]				:DFFE;
+	BL_HOP_CS					:NODE;
+	BL_HOP[7..0]				:DFFE;
+	BL_OP[7..0]					:DFFE;
+	BL_LN_CS					:NODE;
+	LN7CLR						:NODE;
+	BL_LN[7..0]					:DFFE;
+	BL_SKEW[7..0]				:DFFE;
+-- barell shifter
+	DIST_RIGHT[8..0]			:NODE;
+	BL_BS_SKEW[7..0]			:NODE;
+	BL_BSIN[383..0]				:NODE;
+	BL_BSOUT[383..0]			:NODE;
+	SHIFT_DIR					:NODE;
+	BL_SRC_BUF1[127..0]			:DFFE;
+	BL_SRC_BUF2[127..0]			:DFFE;
+	BL_SRC_BUF3[127..0]			:DFFE;
+	BL_DST_BUFRD[127..0]		:DFFE;	
+	BL_READ_DST					:NODE;				-- LATCH SIGNAL DST BUF RD
+	BL_READ_SRC					:NODE;				-- LATCH SIGNAL SRC BUF
+	SRC_READ					:NODE;				-- FREIGABE LATCH SIGNAL
+	NOT_DST_READ				:NODE;
+	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
+	X_INDEX_CS					:NODE;
+	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
+	X_INDEX_CLR					:NODE;
+	Y_INDEX_CS					:NODE;
+	Y_INDEX[15..0]				:DFF;				-- LAUFZEIGER Y COUNT
+	Y_INDEX_CLR					:NODE;
+	LINE_NR[3..0]				:NODE;
+	XIINC						:NODE;				-- INC INDEX SPALTE
+	YIINC						:NODE;				-- INC INDEX ZEILE
+	ZIINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
+	ZYINC						:NODE;				-- KORREKTUR ADRESSEN WENN FERTIG
+	HOP_OUT[127..0]				:NODE;
+	OP_OUT[127..0]				:NODE;
+	ENDMASK1_SHIFT[7..0]		:NODE;
+	ENDMASK2_SHIFT[7..0]		:NODE;
+	ENDMASK12_IN[143..0]		:NODE;
+	ENDMASK12_OUT[143..0]		:NODE;
+	ENDMASK23_IN[143..0]		:NODE;
+	ENDMASK23_OUT[143..0]		:NODE;
+	ENDMASK123[127..0]			:NODE;
+	DDR_RAM_FREE				:NODE;
+	SRC_DDR_ADR[31..0]			:NODE;
+	DST_DDR_ADR[31..0]			:NODE;
+	
+-- MAIN STATE MACHINE
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- wenn ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- or NOT BYT
+-- BLITTER CS
+	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";			-- FFFF8A00-7F  
+	BLITTER_TA = BLITTER_CS;
+-- REGISTER
+	-- HALFTON RAM 
+	BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50";						-- $F8A00-1F.w
+	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
+	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
+	WREN_B = B"0";
+	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	-- SRC X INC
+	BL_SRC_X_INC[].CLK = MAIN_CLK;
+	BL_SRC_X_INC[] = FB_AD[31..16];
+	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20.w
+	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
+	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- SRC Y INC
+	BL_SRC_Y_INC[].CLK = MAIN_CLK;
+	BL_SRC_Y_INC[] = FB_AD[31..16];
+	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22.w
+	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
+	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- SRC ADR HIGH
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[31..16] = FB_AD[31..16];
+	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24.w
+	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
+	-- SRC ADR LOW
+	BL_SRC_ADR[].CLK = MAIN_CLK;
+	BL_SRC_ADR[15..0] = FB_AD[31..16];
+	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";				-- $F8A26.w
+	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
+	SRC_IADR[].CLK = DDRCLK0;
+	SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520";					-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521";					-- $F8A42.w
+	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
+	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	-- ENDMASK 1
+	BL_ENDMASK1[].CLK = MAIN_CLK;
+	BL_ENDMASK1[] = FB_AD[31..16];
+	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";				-- $F8A28.w
+	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 2
+	BL_ENDMASK2[].CLK = MAIN_CLK;
+	BL_ENDMASK2[] = FB_AD[31..16];
+	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";				-- $F8A2A.w
+	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
+	-- ENDMASK 3
+	BL_ENDMASK3[].CLK = MAIN_CLK;
+	BL_ENDMASK3[] = FB_AD[31..16];
+	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";				-- $F8A2C.w
+	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
+	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
+	-- DST X INC
+	BL_DST_X_INC[].CLK = MAIN_CLK;
+	BL_DST_X_INC[] = FB_AD[31..16];
+	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";				-- $F8A2E.w
+	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
+	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- DST Y INC
+	BL_DST_Y_INC[].CLK = MAIN_CLK;
+	BL_DST_Y_INC[] = FB_AD[31..16];
+	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";				-- $F8A30.w
+	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
+	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
+	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	-- DST ADR HIGH
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[31..16] = FB_AD[31..16];
+	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519";				-- $F8A32.w
+	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
+	-- DST ADR LOW
+	BL_DST_ADR[].CLK = MAIN_CLK;
+	BL_DST_ADR[15..0] = FB_AD[31..16];
+	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A";				-- $F8A34.w
+	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
+	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
+	DST_IADR[].CLK = DDRCLK0;
+	DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522";					-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523";					-- $F8A46.w
+	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
+	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	-- X COUNT
+	BL_X_CNT[].CLK = MAIN_CLK;
+	BL_X_CNT[] = FB_AD[31..16];
+	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";					-- $F8A36.w
+	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
+	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
+	X_INDEX[].CLK = DDRCLK0;
+	X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524";					-- $F8A48.w
+	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
+	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
+	-- Y COUNT
+	BL_Y_CNT[].CLK = MAIN_CLK;
+	BL_Y_CNT[] = FB_AD[31..16];
+	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";					-- $F8A38.w
+	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
+	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
+	Y_INDEX[].CLK = DDRCLK0;
+	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";					-- $F8A4A.w
+	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
+	-- HOP LOGIC
+	BL_HOP[].CLK = MAIN_CLK;
+	BL_HOP[] = FB_AD[31..24];
+	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A.w
+	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
+	-- OP LOGIC
+	BL_OP[].CLK = MAIN_CLK;
+	BL_OP[] = FB_AD[23..16];
+	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
+	-- LINE NUMBER BYT
+	BL_LN[].CLK = MAIN_CLK;
+	BL_LN[6..0] = FB_AD[30..24];	
+	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
+	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";						-- $F8A3C.w
+	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
+	BL_LN7.ENA = LN7CLR;
+	-- SKEW BYT
+	BL_SKEW[].CLK = MAIN_CLK;
+	BL_SKEW[] = FB_AD[23..16];
+	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						BL_HRAM_CS	    & BL_DPRAM_OUT[]
+					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
+					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
+					  # BL_SRC_ADRH_CS  & SRC_ADR_NODE[31..16]
+					  # BL_SRC_ADRL_CS  & SRC_ADR_NODE[15..0]
+					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
+					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
+					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
+					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
+					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
+					  # BL_DST_ADRH_CS  & DST_ADR_NODE[31..16]
+					  # BL_DST_ADRL_CS  & DST_ADR_NODE[15..0]
+					  # BL_X_CNT_CS 	& (BL_X_CNT[]-X_INDEX[])
+					  # BL_Y_CNT_CS 	& (BL_Y_CNT[]-Y_INDEX[])
+					  # BL_HOP_CS 		& (BL_HOP[],BL_OP[])
+					  # BL_LN_CS 		& (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])		
+					  # SRC_IADRH_CS	& SRC_IADR[31..16]
+					  # SRC_IADRL_CS	& SRC_IADR[15..0]
+					  # DST_IADRH_CS	& DST_IADR[31..16]
+					  # DST_IADRL_CS	& DST_IADR[15..0]
+					  # X_INDEX_CS		& X_INDEX[]
+					  # Y_INDEX_CS		& Y_INDEX[]
+					  ,BLITTER_CS & !nFB_OE); 											-- FFFF8A00-7F
+-----------------------------------------
+-- SRC BUFFER LADEN
+	BL_SRC_BUF1[].CLK = DDRCLK0;
+	BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF1[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]);
+	BL_SRC_BUF2[].CLK = DDRCLK0;
+	BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF2[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF2[] = BL_SRC_BUF1[];
+	BL_SRC_BUF3[].CLK = DDRCLK0;
+	BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
+	BL_SRC_BUF3[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
+	BL_SRC_BUF3[] = BL_SRC_BUF2[];
+	-- ZUORDNUNG ---------
+	IF BL_SRC_X_INC15 THEN		-- WENN NEGATIV -> REIHENFOLGE KEHREN
+		CASE BL_HOP[7..4] IS	-- SPIEGELN?
+			WHEN H"0" =>		-- LINE WEISE
+				BL_BSIN[127..0]   = BL_SRC_BUF3[];
+				BL_BSIN[255..128] = BL_SRC_BUF2[];
+				BL_BSIN[383..256] = BL_SRC_BUF1[];
+			WHEN H"1" =>		--- BIT WEISE
+				BL_BSIN[0..127]   = BL_SRC_BUF3[];
+				BL_BSIN[128..255] = BL_SRC_BUF2[];
+				BL_BSIN[256..383] = BL_SRC_BUF1[];
+			WHEN H"2" =>		-- BYT WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
+			WHEN H"3" =>		-- WORD WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
+			WHEN H"4" =>		-- LONG WEISE
+				BL_BSIN[127..0]   = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
+				BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
+				BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
+			WHEN OTHERS =>		-- LINE WEISE
+				BL_BSIN[127..0]   = BL_SRC_BUF3[];
+				BL_BSIN[255..128] = BL_SRC_BUF2[];
+				BL_BSIN[383..256] = BL_SRC_BUF1[];
+		END CASE;
+	ELSE						-- SONST NORMAL BEI VORWÄRTS
+		BL_BSIN[127..0]   = BL_SRC_BUF1[];
+		BL_BSIN[255..128] = BL_SRC_BUF2[];
+		BL_BSIN[383..256] = BL_SRC_BUF3[];
+	END IF;
+-- DST BUFFER READ	
+	BL_DST_BUFRD[].CLK = DDRCLK0;
+	BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST;
+	BL_DST_BUFRD[63..0].ENA   = BLITTER_DACK0 & BL_READ_DST;
+	BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
+-- barell shift *****************************************************************************
+-- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
+	DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
+	IF DIST_RIGHT8 == 0 THEN 		
+		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
+		SHIFT_DIR = VCC;									-- DIR = RIGHT
+	else													
+		BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; 				-- LPM SHIFT LEFT
+		SHIFT_DIR = GND;									-- DIR = LEFT
+	end if;
+-- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
+	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]);	-- wir brauchen 128bit
+-- HOP ***************************************************************************************
+	CASE BL_HOP[1..0] IS
+		WHEN H"0" =>
+					--    12345678901234567890123456789012
+			HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+		WHEN H"1" =>
+			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
+		WHEN H"2" =>
+			HOP_OUT[] = BL_BSOUT[255..128];
+		WHEN OTHERS =>
+			HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]));
+	END CASE;
+-- OP *****************************************************************************************
+	CASE BL_OP[3..0] IS
+		WHEN H"0" =>
+			OP_OUT[] = H"0";
+			SRC_READ = B"0";
+		WHEN H"1" =>
+			OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"2" =>
+			OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"3" =>
+			OP_OUT[] = HOP_OUT[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"4" =>
+			OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"5" =>
+			OP_OUT[] = BL_DST_BUFRD[];
+			SRC_READ = B"0";
+		WHEN H"6" =>
+			OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"7" =>
+			OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"8" =>
+			OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"9" =>
+			OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"A" =>
+			OP_OUT[] = !BL_DST_BUFRD[];
+			SRC_READ = B"0";
+		WHEN H"B" =>
+			OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"C" =>
+			OP_OUT[] = !HOP_OUT[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"D" =>
+			OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN H"E" =>
+			OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1 # BL_HOP0;
+		WHEN OTHERS =>
+					--   12345678901234567890123456789012
+			OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+			SRC_READ = B"0";
+	END CASE;
+------------ ENDMASKEN SETZEN ******************************************************************************																							 
+			ENDMASK1_SHIFT[3..0] = 0; 						
+			ENDMASK2_SHIFT[3..0] = 0; 						
+			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
+				IF X_INDEX[]==0 THEN															-- ENDE?	
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;	 
+				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;
+			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV
+				IF X_INDEX[]==0 THEN															-- ANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); 						-- JA -> ENDMASK 1 SETZEN 
+				ELSE		
+					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
+				END IF;		
+				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+				ELSE					
+					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
+				END IF;	 
+			END IF;
+-- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
+--				   1234567890123456789012345678
+	ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+	ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]);			-- IMMER rechts SCHIEBEN
+	ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
+	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
+	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
+	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
+	NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
+-- STATE MACHINE ****************************************************************************************************	
+	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
+	DDR_RAM_FREE = BLITTER_DACK[]==H"0";							-- 0 WENN FREI
+	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
+	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
+	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
+-- BLITTER MAIN STATE MACHINE  -----------------------------------------------
+	BL_SM.CLK = DDRCLK0;
+	CASE BL_SM IS
+		WHEN START =>   ------------------------- START
+			IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
+				BL_SM = NEW_LINE;
+			ELSE
+				BL_SM = START;
+			END IF;
+		WHEN NEW_LINE => ----------------------- NEU LINIE
+			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
+			BL_SM = RDSRC1;
+		WHEN RDSRC1 =>  ------------------------ READ SRC1
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					SIINC = VCC;							-- INC SRC ADR
+					BL_SM = RDSRC2;
+				ELSE	
+					BL_SM = RDSRC1;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
+		WHEN RDSRC2 =>	------------------------ READ SRC2
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					SIINC = VCC;							-- INC SRC ADR
+					BL_SM = RDDST;
+				ELSE	
+					BL_SM = RDSRC2;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
+		WHEN RDDST =>	----------------------- READ DEST
+			IF NOT_READ_DST THEN
+				BL_SM = WRDST;
+			ELSE
+				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+				BLITTER_SIG = DDR_RAM_FREE;
+				BL_READ_DST = VCC;
+				IF BLITTER_DACK0 THEN
+					BL_SM = WRDST;
+				ELSE	
+					BL_SM = RDDST;
+				END IF;
+			END IF;
+		WHEN WRDST =>	------------------- WRITE DEST
+			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+			BLITTER_WR = DDR_RAM_FREE;
+			BLITTER_SIG = DDR_RAM_FREE;
+			IF BLITTER_DACK0 THEN
+				XIINC = VCC;								-- INC X_INDEX
+				DIINC = VCC;								-- INC DEST ADR
+				BL_SM = TESTZEILENENDE;
+			ELSE	
+				BL_SM = WRDST;
+			END IF;
+		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
+			IF BL_X_CNT[]<=(X_CNT_NODE[])	 THEN			-- SCHON ZEILENENDE?	
+				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
+				BL_SM = TESTFERTIG;							-- ->
+			ELSE
+				BL_SM = RDSRC2;								-- NEIN NEXT
+			END IF;	
+		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
+			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
+			IF Y_INDEX[]>=BL_Y_CNT[] THEN					-- LETZTE ZEILE?
+				BL_SM = FERTIG;								-- JA -->
+			ELSE
+				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
+				BL_SM = NEW_LINE;							-- NEIN NEXT ->
+			END IF;
+		WHEN FERTIG => -------------------------- FERTIG
+			BLITTER_INT = VCC;								-- BLITTER INTERRUPT
+			LN7CLR = VCC;									-- BUSY BIT LÖSCHEN
+			IF BL_LN7==0 THEN								-- WARTEN BIS GELÖSCHT (GEHT NUR MIT 33MHz)
+				BL_SM = START;	
+			ELSE
+				BL_SM = FERTIG;
+			END IF;
+		WHEN OTHERS =>
+			BL_SM = FERTIG;
+	END CASE;
+END;
+
diff --git a/FPGA_by_Fredi/blitter.tdf.pdf b/FPGA_by_Fredi/blitter.tdf.pdf
new file mode 100644
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diff --git a/FPGA_by_Fredi/firebee1.asm.rpt b/FPGA_by_Fredi/firebee1.asm.rpt
new file mode 100644
index 0000000..0641298
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.asm.rpt
@@ -0,0 +1,128 @@
+Assembler report for firebee1
+Thu Apr 13 11:08:24 2017
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
+  6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Thu Apr 13 11:08:24 2017 ;
+; Revision Name         ; firebee1                              ;
+; Top-level Entity Name ; firebee1                              ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C40F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                       ;
++-----------------------------------------------------------------------------+------------+---------------+
+; Option                                                                      ; Setting    ; Default Value ;
++-----------------------------------------------------------------------------+------------+---------------+
+; Generate Raw Binary File (.rbf) For Target Device                           ; On         ; Off           ;
+; Hexadecimal Output File start address                                       ; 0XE0700000 ; 0             ;
+; Use smart compilation                                                       ; Off        ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On         ; On            ;
+; Enable compact report table                                                 ; Off        ; Off           ;
+; Generate compressed bitstreams                                              ; On         ; On            ;
+; Compression mode                                                            ; Off        ; Off           ;
+; Clock source for configuration device                                       ; Internal   ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ     ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1          ; 1             ;
+; Auto user code                                                              ; Off        ; Off           ;
+; Use configuration device                                                    ; Off        ; Off           ;
+; Configuration device                                                        ; Auto       ; Auto          ;
+; Configuration device auto user code                                         ; Off        ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off        ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off        ; Off           ;
+; Hexadecimal Output File count direction                                     ; Up         ; Up            ;
+; Release clears before tri-states                                            ; Off        ; Off           ;
+; Auto-restart configuration after error                                      ; On         ; On            ;
+; Enable OCT_DONE                                                             ; Off        ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off        ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off        ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off        ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On         ; On            ;
++-----------------------------------------------------------------------------+------------+---------------+
+
+
++------------------------------+
+; Assembler Generated Files    ;
++------------------------------+
+; File Name                    ;
++------------------------------+
+; C:/FireBee/FPGA/firebee1.sof ;
+; C:/FireBee/FPGA/firebee1.rbf ;
++------------------------------+
+
+
++--------------------------------------------------------+
+; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
++----------------+---------------------------------------+
+; Option         ; Setting                               ;
++----------------+---------------------------------------+
+; Device         ; EP3C40F484C6                          ;
+; JTAG usercode  ; 0xFFFFFFFF                            ;
+; Checksum       ; 0x01072C3E                            ;
++----------------+---------------------------------------+
+
+
++--------------------------------------------------------+
+; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
++---------------------+----------------------------------+
+; Option              ; Setting                          ;
++---------------------+----------------------------------+
+; Raw Binary File     ;                                  ;
+;  Compression Ratio  ; 2                                ;
++---------------------+----------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Assembler
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Thu Apr 13 11:08:20 2017
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
+Info: Writing out detailed assembly data for power analysis
+Info: Assembler is generating device programming files
+Info: Quartus II Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 310 megabytes
+    Info: Processing ended: Thu Apr 13 11:08:24 2017
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
index 8d4f188..dc29aec 100644
--- a/FPGA_by_Fredi/firebee1.bdf
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -293,7 +293,7 @@ applicable agreement for further details.
 		(line (pt 117 12)(pt 121 8)(line_width 1))
 	)
 	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 560 1504 648 1536))
+	(annotation_block (location)(rect 520 1472 608 1504))
 )
 (pin
 	(input)
@@ -2063,6 +2063,23 @@ applicable agreement for further details.
 	)
 	(annotation_block (location)(rect 992 272 1056 288))
 )
+(pin
+	(output)
+	(rect 1848 2128 2024 2144)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "nDREQ0" (rect 90 0 133 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8)(line_width 1))
+		(line (pt 52 4)(pt 78 4)(line_width 1))
+		(line (pt 52 12)(pt 78 12)(line_width 1))
+		(line (pt 52 12)(pt 52 4)(line_width 1))
+		(line (pt 78 4)(pt 82 8)(line_width 1))
+		(line (pt 82 8)(pt 78 12)(line_width 1))
+		(line (pt 78 12)(pt 82 8)(line_width 1))
+	)
+	(annotation_block (location)(rect 2024 2112 2072 2128))
+)
 (pin
 	(bidir)
 	(rect 1840 1088 2016 1104)
@@ -2242,7 +2259,7 @@ applicable agreement for further details.
 	)
 	(flipy)
 	(text "VCC" (rect 152 7 172 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 352 1376 416 1824))
+	(annotation_block (location)(rect 112 928 176 1376))
 )
 (pin
 	(bidir)
@@ -3477,118 +3494,26 @@ applicable agreement for further details.
 		(line (pt 40 48)(pt 40 168)(line_width 1))
 	)
 )
-(block
-	(rect 1264 2944 1672 3560)
-	(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" ))	(block_io "CLK33M" (input))
-	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "nFB_BURST" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "nRSTO" (input))
-	(block_io "nFB_CS3" (input))
-	(block_io "nSRCS" (output))
-	(block_io "nSRBLE" (output))
-	(block_io "nSRBHE" (output))
-	(block_io "nSRWE" (output))
-	(block_io "nSROE" (output))
-	(block_io "DSP_INT" (output))
-	(block_io "DSP_TA" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(block_io "IO[17..0]" (bidir))
-	(block_io "SRD[15..0]" (bidir))
-	(mapper
-		(pt 408 416)
-		(bidir)
-		)
-	(mapper
-		(pt 408 392)
-		(bidir)
-		)
-	(mapper
-		(pt 408 368)
-		(bidir)
-		)
-	(mapper
-		(pt 408 320)
-		(bidir)
-		)
-	(mapper
-		(pt 408 440)
-		(bidir)
-		)
-	(mapper
-		(pt 408 344)
-		(bidir)
-		)
-	(mapper
-		(pt 408 296)
-		(bidir)
-		)
-	(mapper
-		(pt 408 40)
-		(bidir)
-		)
-	(mapper
-		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 248)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 272)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 408 72)
-		(bidir)
-		)
-	(mapper
-		(pt 408 576)
-		(bidir)
-		)
-	(mapper
-		(pt 0 320)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
+(symbol
+	(rect 840 2872 928 2920)
+	(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
+	(text "inst26" (rect 8 32 37 44)(font "Arial" ))
+	(port
+		(pt 88 24)
+		(output)
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 85 -31 152 -17)(font "Arial" (font_size 8))(invisible))
+		(line (pt 88 24)(pt 72 24)(line_width 3))
+	)
+	(drawing
+		(text "319037463" (rect 27 18 80 30)(font "Arial" ))
+		(text "32" (rect 77 25 88 37)(font "Arial" ))
+		(line (pt 16 16)(pt 72 16)(line_width 1))
+		(line (pt 72 16)(pt 72 32)(line_width 1))
+		(line (pt 72 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+	)
 )
 (block
 	(rect 1264 -48 1672 728)
@@ -3631,6 +3556,7 @@ applicable agreement for further details.
 	(block_io "BA[1..0]" (output))
 	(block_io "VIDEO_RECONFIG" (output))
 	(block_io "VR_WR" (output))
+	(block_io "BLITTER_INT" (output))
 	(block_io "VDQS[3..0]" (bidir))
 	(block_io "FB_AD[31..0]" (bidir))
 	(block_io "VD[31..0]" (bidir))
@@ -3802,137 +3728,8 @@ applicable agreement for further details.
 		(pt 0 512)
 		(bidir)
 		)
-)
-(block
-	(rect 1264 2344 1672 2904)
-	(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8)))	(text "nobody" (rect 5 546 41 558)(font "Arial" ))	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "PIC_INT" (input))
-	(block_io "E0_INT" (input))
-	(block_io "DVI_INT" (input))
-	(block_io "nPCI_INTA" (input))
-	(block_io "nPCI_INTB" (input))
-	(block_io "nPCI_INTC" (input))
-	(block_io "nPCI_INTD" (input))
-	(block_io "nMFP_INT" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "DSP_INT" (input))
-	(block_io "VSYNC" (input))
-	(block_io "HSYNC" (input))
-	(block_io "DMA_DRQ" (input))
-	(block_io "nRSTO" (input))
-	(block_io "nIRQ[7..2]" (output))
-	(block_io "INT_HANDLER_TA" (output))
-	(block_io "ACP_CONF[31..0]" (output))
-	(block_io "TIN0" (output))
-	(block_io "FB_AD[31..0]" (bidir))
 	(mapper
-		(pt 408 56)
-		(bidir)
-		)
-	(mapper
-		(pt 408 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 256)
-		(bidir)
-		)
-	(mapper
-		(pt 0 280)
-		(bidir)
-		)
-	(mapper
-		(pt 0 304)
-		(bidir)
-		)
-	(mapper
-		(pt 0 376)
-		(bidir)
-		)
-	(mapper
-		(pt 0 400)
-		(bidir)
-		)
-	(mapper
-		(pt 0 328)
-		(bidir)
-		)
-	(mapper
-		(pt 0 352)
-		(bidir)
-		)
-	(mapper
-		(pt 0 432)
-		(bidir)
-		)
-	(mapper
-		(pt 0 456)
-		(bidir)
-		)
-	(mapper
-		(pt 0 480)
-		(bidir)
-		)
-	(mapper
-		(pt 0 504)
-		(bidir)
-		)
-	(mapper
-		(pt 408 504)
-		(bidir)
-		)
-	(mapper
-		(pt 0 528)
-		(bidir)
-		)
-	(mapper
-		(pt 408 240)
-		(bidir)
-		)
-	(mapper
-		(pt 408 296)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 32)
+		(pt 408 704)
 		(bidir)
 		)
 )
@@ -3983,12 +3780,15 @@ applicable agreement for further details.
 	(block_io "nFB_OE" (input))
 	(block_io "VSYNC" (input))
 	(block_io "HSYNC" (input))
-	(block_io "DSP_INT" (input))
 	(block_io "nBLANK" (input))
 	(block_io "FDC_CLK" (input))
 	(block_io "FB_ALE" (input))
-	(block_io "ACP_CONF[31..24]" (input))
 	(block_io "HD_DD" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "VIDEO_TA" (input))
+	(block_io "ACP_CONF[31..0]" (input))
+	(block_io "BLITTER_INT" (input))
+	(block_io "DSP_INT" (input))
 	(block_io "nIDE_CS1" (output))
 	(block_io "nIDE_CS0" (output))
 	(block_io "LP_STR" (output))
@@ -4361,10 +4161,6 @@ applicable agreement for further details.
 		(pt 0 176)
 		(bidir)
 		)
-	(mapper
-		(pt 0 1216)
-		(bidir)
-		)
 	(mapper
 		(pt 408 48)
 		(bidir)
@@ -4449,6 +4245,274 @@ applicable agreement for further details.
 		(pt 408 1544)
 		(bidir)
 		)
+	(mapper
+		(pt 0 1408)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1488)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1440)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1464)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 2944 1672 3560)
+	(text "DSP" (rect 5 5 28 19)(font "Arial" (font_size 8)))	(text "Mathias_Alles" (rect 5 602 72 614)(font "Arial" ))	(block_io "CLK33M" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nSRCS" (output))
+	(block_io "nSRBLE" (output))
+	(block_io "nSRBHE" (output))
+	(block_io "nSRWE" (output))
+	(block_io "nSROE" (output))
+	(block_io "DSP_INT" (output))
+	(block_io "DSP_TA" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "IO[17..0]" (bidir))
+	(block_io "SRD[15..0]" (bidir))
+	(mapper
+		(pt 408 416)
+		(bidir)
+		)
+	(mapper
+		(pt 408 392)
+		(bidir)
+		)
+	(mapper
+		(pt 408 368)
+		(bidir)
+		)
+	(mapper
+		(pt 408 320)
+		(bidir)
+		)
+	(mapper
+		(pt 408 440)
+		(bidir)
+		)
+	(mapper
+		(pt 408 344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 40)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 408 576)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 2344 1672 2920)
+	(text "interrupt_handler" (rect 5 5 101 19)(font "Arial" (font_size 8)))	(text "nobody" (rect 5 562 41 574)(font "Arial" ))	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "PIC_INT" (input))
+	(block_io "E0_INT" (input))
+	(block_io "DVI_INT" (input))
+	(block_io "nPCI_INTA" (input))
+	(block_io "nPCI_INTB" (input))
+	(block_io "nPCI_INTC" (input))
+	(block_io "nPCI_INTD" (input))
+	(block_io "nMFP_INT" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DMA_DRQ" (input))
+	(block_io "nRSTO" (input))
+	(block_io "VIDEO_TA" (input))
+	(block_io "FPGA_DATE[31..0]" (input))
+	(block_io "nIRQ[7..2]" (output))
+	(block_io "INT_HANDLER_TA" (output))
+	(block_io "ACP_CONF[31..0]" (output))
+	(block_io "TIN0" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 408 56)
+		(bidir)
+		)
+	(mapper
+		(pt 408 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 280)
+		(bidir)
+		)
+	(mapper
+		(pt 0 304)
+		(bidir)
+		)
+	(mapper
+		(pt 0 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 400)
+		(bidir)
+		)
+	(mapper
+		(pt 0 328)
+		(bidir)
+		)
+	(mapper
+		(pt 0 352)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 0 480)
+		(bidir)
+		)
+	(mapper
+		(pt 0 504)
+		(bidir)
+		)
+	(mapper
+		(pt 408 504)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 552)
+		(bidir)
+		)
 )
 (connector
 	(text "FB_AD[31..0]" (rect 1682 2384 1749 2396)(font "Arial" ))
@@ -5365,11 +5429,6 @@ applicable agreement for further details.
 	(pt 1264 1984)
 	(pt 1144 1984)
 )
-(connector
-	(text "DSP_INT" (rect 1154 1944 1200 1956)(font "Arial" ))
-	(pt 1264 1960)
-	(pt 1144 1960)
-)
 (connector
 	(text "DMA_DRQ" (rect 1682 2096 1736 2108)(font "Arial" ))
 	(pt 1784 2112)
@@ -5385,12 +5444,6 @@ applicable agreement for further details.
 	(pt 1144 2008)
 	(pt 1264 2008)
 )
-(connector
-	(text "ACP_CONF[31..24]" (rect 1146 2064 1243 2076)(font "Arial" ))
-	(pt 1136 2080)
-	(pt 1264 2080)
-	(bus)
-)
 (connector
 	(text "LP_STR" (rect 1682 824 1722 836)(font "Arial" ))
 	(pt 1672 840)
@@ -5908,11 +5961,6 @@ applicable agreement for further details.
 	(pt 1672 2224)
 	(pt 1864 2224)
 )
-(connector
-	(text "nDREQ0" (rect 1674 2120 1717 2132)(font "Arial" ))
-	(pt 1672 2136)
-	(pt 1800 2136)
-)
 (connector
 	(text "MIDI_OLR" (rect 1682 2272 1733 2284)(font "Arial" ))
 	(pt 1672 2288)
@@ -5990,6 +6038,48 @@ applicable agreement for further details.
 	(pt 816 280)
 	(pt 712 280)
 )
+(connector
+	(text "nFB_CS3" (rect 1162 2136 1209 2148)(font "Arial" ))
+	(pt 1152 2152)
+	(pt 1264 2152)
+)
+(connector
+	(text "nDREQ0" (rect 1722 2120 1765 2132)(font "Arial" ))
+	(pt 1672 2136)
+	(pt 1848 2136)
+)
+(connector
+	(text "Video_TA" (rect 1178 2216 1224 2228)(font "Arial" ))
+	(pt 1168 2232)
+	(pt 1264 2232)
+)
+(connector
+	(text "ACP_CONF[31..0]" (rect 1146 2064 1238 2076)(font "Arial" ))
+	(pt 1136 2080)
+	(pt 1264 2080)
+	(bus)
+)
+(connector
+	(text "BLITTER_INT" (rect 1698 640 1765 652)(font "Arial" ))
+	(pt 1672 656)
+	(pt 1792 656)
+)
+(connector
+	(text "BLITTER_INT" (rect 1154 2168 1221 2180)(font "Arial" ))
+	(pt 1264 2184)
+	(pt 1144 2184)
+)
+(connector
+	(text "DSP_INT" (rect 1154 2192 1200 2204)(font "Arial" ))
+	(pt 1264 2208)
+	(pt 1144 2208)
+)
+(connector
+	(text "FPGA_DATE[31..0]" (rect 938 2880 1033 2892)(font "Arial" ))
+	(pt 928 2896)
+	(pt 1264 2896)
+	(bus)
+)
 (junction (pt 2504 760))
 (junction (pt 1856 -64))
 (junction (pt 2424 -80))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index edfa2a3..1c56ddf 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Fri Aug 28 13:39:52 2015
+Thu Apr 13 11:08:39 2017
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
index f4ccea5..33aa7d2 100644
--- a/FPGA_by_Fredi/firebee1.fit.summary
+++ b/FPGA_by_Fredi/firebee1.fit.summary
@@ -1,16 +1,16 @@
-Fitter Status : Successful - Fri Aug 28 13:39:32 2015
+Fitter Status : Successful - Thu Apr 13 11:08:12 2017
 Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
 Revision Name : firebee1
 Top-level Entity Name : firebee1
 Family : Cyclone III
 Device : EP3C40F484C6
 Timing Models : Final
-Total logic elements : 10,207 / 39,600 ( 26 % )
-    Total combinational functions : 8,661 / 39,600 ( 22 % )
-    Dedicated logic registers : 5,025 / 39,600 ( 13 % )
-Total registers : 5162
-Total pins : 295 / 332 ( 89 % )
+Total logic elements : 20,945 / 39,600 ( 53 % )
+    Total combinational functions : 19,059 / 39,600 ( 48 % )
+    Dedicated logic registers : 5,696 / 39,600 ( 14 % )
+Total registers : 5845
+Total pins : 296 / 332 ( 89 % )
 Total virtual pins : 0
-Total memory bits : 109,600 / 1,161,216 ( 9 % )
-Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % )
+Total memory bits : 355,360 / 1,161,216 ( 31 % )
+Embedded Multiplier 9-bit elements : 12 / 252 ( 5 % )
 Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.flow.rpt b/FPGA_by_Fredi/firebee1.flow.rpt
new file mode 100644
index 0000000..1bad0f9
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.flow.rpt
@@ -0,0 +1,428 @@
+Flow report for firebee1
+Sat Apr 15 23:46:36 2017
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------+
+; Flow Summary                                                                      ;
++------------------------------------+----------------------------------------------+
+; Flow Status                        ; Successful - Sat Apr 15 23:46:35 2017        ;
+; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name                      ; firebee1                                     ;
+; Top-level Entity Name              ; firebee1                                     ;
+; Family                             ; Cyclone III                                  ;
+; Device                             ; EP3C40F484C6                                 ;
+; Timing Models                      ; Final                                        ;
+; Met timing requirements            ; N/A                                          ;
+; Total logic elements               ; 22,593                                       ;
+;     Total combinational functions  ; 19,050                                       ;
+;     Dedicated logic registers      ; 5,711                                        ;
+; Total registers                    ; 5839                                         ;
+; Total pins                         ; 296                                          ;
+; Total virtual pins                 ; 0                                            ;
+; Total memory bits                  ; 355,360                                      ;
+; Embedded Multiplier 9-bit elements ; 12                                           ;
+; Total PLLs                         ; 4                                            ;
++------------------------------------+----------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 04/15/2017 23:43:13 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; firebee1            ;
++-------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                            ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+; Assignment Name                         ; Value                              ; Default Value ; Entity Name ; Section Id     ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+; COMPILER_SIGNATURE_ID                   ; 1098263457634.149229259302120      ; --            ; --          ; --             ;
+; CYCLONEII_OPTIMIZATION_TECHNIQUE        ; Speed                              ; Balanced      ; --          ; --             ;
+; FMAX_REQUIREMENT                        ; 30 ns                              ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_LATCH                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_COMPARE                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_BIDIR                      ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL_RECONFIG                    ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTSYNCRAM                         ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; ALTIOBUF                           ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CLSHIFT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CLSHIFT                        ; --            ; --          ; --             ;
+; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
+; MAX_CORE_JUNCTION_TEMP                  ; 85                                 ; --            ; --          ; --             ;
+; MIN_CORE_JUNCTION_TEMP                  ; 0                                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; C:/firebee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
+; MISC_FILE                               ; C:/FireBee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll1.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll2.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll3.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll0.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter0.bsf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter0.cmp                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg0.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram0.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri1.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri1.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram1.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri2.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri2.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri4.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri4.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant0.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant0.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant1.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux0.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux1.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux2.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant2.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant2.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altdpram2.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri6.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_bustri6.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux3.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux3.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux4.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux4.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant3.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant3.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg1.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg1.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_latch1.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_latch1.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_constant4.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg2.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg2.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_compare1.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_LONG.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_BYT.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_bustri_WORD.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff4.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff5.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_ff6.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg3.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.bsf           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.inc           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.cmp           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_bidir0.ppf           ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out0.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux5.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg5.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg6.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.bsf            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.inc            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_shiftreg4.cmp            ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out1.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.bsf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.inc             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.cmp             ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/altddio_out2.ppf             ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.bsf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.inc                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.cmp                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altddio_out3.ppf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.bsf                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.inc                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_mux6.cmp                 ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; --            ; --          ; --             ;
+; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxDZ.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxDZ.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxVDM.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_muxVDM.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.tdf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.bsf               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.inc               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll_reconfig1.cmp               ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.tdf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.bsf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.inc                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.cmp                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; altpll4.ppf                        ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux0.tdf                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux0.bsf                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux0.inc                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux0.cmp                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/altsyncram0.tdf      ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/altsyncram0.inc      ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_shiftreg0.tdf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_shiftreg0.bsf                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_shiftreg0.inc                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_shiftreg0.cmp                  ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter1.tdf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter1.bsf                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter1.inc                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_counter1.cmp                   ; --            ; --          ; --             ;
+; MISC_FILE                               ; altiobuf_bidir0.tdf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; altiobuf_bidir0.bsf                ; --            ; --          ; --             ;
+; MISC_FILE                               ; altiobuf_bidir0.inc                ; --            ; --          ; --             ;
+; MISC_FILE                               ; altiobuf_bidir0.cmp                ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux1.tdf                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux1.bsf                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux1.inc                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; lpm_mux1.cmp                       ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_blitter.bsf              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_blitter.inc              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/lpm_blitter.cmp              ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.tdf   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.inc   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.cmp   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/lpm_clshift144.tdf   ; --            ; --          ; --             ;
+; MISC_FILE                               ; Video/BLITTER/lpm_clshift144.inc   ; --            ; --          ; --             ;
+; MISC_FILE                               ; FPGA_DATE.tdf                      ; --            ; --          ; --             ;
+; MISC_FILE                               ; FPGA_DATE.bsf                      ; --            ; --          ; --             ;
+; MISC_FILE                               ; FPGA_DATE.inc                      ; --            ; --          ; --             ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE             ; 1.2V                               ; --            ; --          ; --             ;
+; PARTITION_COLOR                         ; 16764057                           ; --            ; --          ; Top            ;
+; PARTITION_FITTER_PRESERVATION_LEVEL     ; PLACEMENT_AND_ROUTING              ; --            ; --          ; Top            ;
+; PARTITION_NETLIST_TYPE                  ; SOURCE                             ; --            ; --          ; Top            ;
+; PHYSICAL_SYNTHESIS_COMBO_LOGIC          ; On                                 ; Off           ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On                                 ; Off           ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_EFFORT               ; Fast                               ; Normal        ; --          ; --             ;
+; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On                                 ; Off           ; --          ; --             ;
+; POWER_BOARD_THERMAL_MODEL               ; None (CONSERVATIVE)                ; --            ; --          ; --             ;
+; POWER_PRESET_COOLING_SOLUTION           ; No Heat Sink With Still Air        ; --            ; --          ; --             ;
+; POWER_USE_TA_VALUE                      ; 35                                 ; 25            ; --          ; --             ;
+; STATE_MACHINE_PROCESSING                ; One-Hot                            ; Auto          ; --          ; --             ;
+; TCO_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; TH_REQUIREMENT                          ; 1 ns                               ; --            ; --          ; --             ;
+; TPD_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; TSU_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS      ; Off                                ; --            ; --          ; eda_blast_fpga ;
+; USE_TIMEQUEST_TIMING_ANALYZER           ; Off                                ; On            ; --          ; --             ;
++-----------------------------------------+------------------------------------+---------------+-------------+----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                        ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:03:20     ; 1.0                     ; 355 MB              ; 00:03:21                           ;
+; Total                ; 00:03:20     ; --                      ; --                  ; 00:03:21                           ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++---------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                       ;
++----------------------+------------------+---------------+------------+----------------+
+; Module Name          ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
++----------------------+------------------+---------------+------------+----------------+
+; Analysis & Synthesis ; Vaio             ; Windows Vista ; 6.1        ; x86_64         ;
++----------------------+------------------+---------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
+
+
+
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
index 7a93fd1..aa8c768 100644
--- a/FPGA_by_Fredi/firebee1.map.summary
+++ b/FPGA_by_Fredi/firebee1.map.summary
@@ -1,14 +1,14 @@
-Analysis & Synthesis Status : Successful - Fri Aug 28 13:35:56 2015
+Analysis & Synthesis Status : Successful - Sat Apr 15 23:46:35 2017
 Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
 Revision Name : firebee1
 Top-level Entity Name : firebee1
 Family : Cyclone III
-Total logic elements : 11,642
-    Total combinational functions : 8,656
-    Dedicated logic registers : 5,028
-Total registers : 5156
-Total pins : 295
+Total logic elements : 22,593
+    Total combinational functions : 19,050
+    Dedicated logic registers : 5,711
+Total registers : 5839
+Total pins : 296
 Total virtual pins : 0
-Total memory bits : 109,600
-Embedded Multiplier 9-bit elements : 6
+Total memory bits : 355,360
+Embedded Multiplier 9-bit elements : 12
 Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.pin b/FPGA_by_Fredi/firebee1.pin
index 9f213b1..83dafe4 100644
--- a/FPGA_by_Fredi/firebee1.pin
+++ b/FPGA_by_Fredi/firebee1.pin
@@ -490,7 +490,7 @@ VDM[2]                       : U20       : output : 2.5 V             :
 VD[7]                        : U21       : bidir  : 2.5 V             :         : 5         : Y              
 VDQS[2]                      : U22       : bidir  : 2.5 V             :         : 5         : Y              
 nPD_VGA                      : V1        : output : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+nDREQ0                       : V2        : output : 3.3-V LVTTL       :         : 2         : Y              
 nPCI_INTC                    : V3        : input  : 3.3-V LVTTL       :         : 2         : Y              
 nPCI_INTB                    : V4        : input  : 3.3-V LVTTL       :         : 2         : Y              
 RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index a1993e9..a041c37 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -567,8 +567,93 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
 set_location_assignment PIN_E5 -to LPDIR
 set_location_assignment PIN_B11 -to nRSTO_MCF
-set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_clshift0.cmp
-set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift0.tdf
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_location_assignment PIN_V2 -to nDREQ0
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
 set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
 set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
 set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
@@ -738,95 +823,15 @@ set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
 set_global_assignment -name QIP_FILE altpll_reconfig1.qip
 set_global_assignment -name QIP_FILE altpll4.qip
 set_global_assignment -name QIP_FILE lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
-set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
 set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
-set_location_assignment PIN_AB12 -to CLK33MDIR
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
 set_global_assignment -name QIP_FILE lpm_counter1.qip
 set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
-set_location_assignment PIN_E12 -to MIDI_IN_PIN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
-set_instance_assignment -name PCI_IO ON -to nPCI_INTA
-set_instance_assignment -name PCI_IO ON -to nPCI_INTB
-set_instance_assignment -name PCI_IO ON -to nPCI_INTC
-set_instance_assignment -name PCI_IO ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_global_assignment -name QIP_FILE lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_blitter.qip
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift384.tdf
+set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
+set_global_assignment -name QIP_FILE FPGA_DATE.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.sim.rpt b/FPGA_by_Fredi/firebee1.sim.rpt
new file mode 100644
index 0000000..6bfa8c3
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.sim.rpt
@@ -0,0 +1,247 @@
+Simulator report for firebee1
+Fri Mar 10 13:17:46 2017
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Simulator Summary
+  3. Simulator Settings
+  4. Simulation Waveforms
+  5. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM
+  6. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
+  7. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
+  8. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
+  9. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM
+ 10. |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM
+ 11. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
+ 12. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
+ 13. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
+ 14. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
+ 15. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
+ 16. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
+ 17. |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM
+ 18. |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM
+ 19. |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM
+ 20. Coverage Summary
+ 21. Complete 1/0-Value Coverage
+ 22. Missing 1-Value Coverage
+ 23. Missing 0-Value Coverage
+ 24. Simulator INI Usage
+ 25. Simulator Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-------------------+
+; Simulator Summary ;
++------+------------+
+; Type ; Value      ;
++------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Simulator Settings                                                                                                        ;
++--------------------------------------------------------------------------------------------+--------------+---------------+
+; Option                                                                                     ; Setting      ; Default Value ;
++--------------------------------------------------------------------------------------------+--------------+---------------+
+; Simulation mode                                                                            ; Timing       ; Timing        ;
+; Start time                                                                                 ; 0 ns         ; 0 ns          ;
+; End time                                                                                   ; 2 us         ;               ;
+; Simulation results format                                                                  ; CVWF         ;               ;
+; Vector input source                                                                        ; firebee1.vwf ;               ;
+; Add pins automatically to simulation output waveforms                                      ; Off          ; On            ;
+; Check outputs                                                                              ; Off          ; Off           ;
+; Report simulation coverage                                                                 ; On           ; On            ;
+; Display complete 1/0 value coverage report                                                 ; On           ; On            ;
+; Display missing 1-value coverage report                                                    ; On           ; On            ;
+; Display missing 0-value coverage report                                                    ; On           ; On            ;
+; Detect setup and hold time violations                                                      ; Off          ; Off           ;
+; Detect glitches                                                                            ; Off          ; Off           ;
+; Disable timing delays in Timing Simulation                                                 ; Off          ; Off           ;
+; Generate Signal Activity File                                                              ; Off          ; Off           ;
+; Generate VCD File for PowerPlay Power Analyzer                                             ; Off          ; Off           ;
+; Group bus channels in simulation results                                                   ; Off          ; Off           ;
+; Preserve fewer signal transitions to reduce memory requirements                            ; On           ; On            ;
+; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE   ; INPUT_EDGE    ;
+; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off          ; Off           ;
+; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off          ;               ;
+; Perform Glitch Filtering in Timing Simulation                                              ; Auto         ; Auto          ;
+; Interconnect Delay Model Type                                                              ; Transport    ; Transport     ;
+; Cell Delay Model Type                                                                      ; Transport    ; Transport     ;
++--------------------------------------------------------------------------------------------+--------------+---------------+
+
+
++----------------------+
+; Simulation Waveforms ;
++----------------------+
+Waveform report data cannot be output to ASCII.
+Please use Quartus II to view the waveform report data.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
++-----------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
++------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
++-------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ;
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM ;
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
++----------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
++---------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
++--------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
++----------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
++-------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
++-----------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ;
++-------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++------------------+
+; Coverage Summary ;
++------+-----------+
+; Type ; Value     ;
++------+-----------+
+
+
+The following table displays output ports that toggle between 1 and 0 during simulation.
++-------------------------------------------------+
+; Complete 1/0-Value Coverage                     ;
++-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-----------+------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 1 during simulation.
++-------------------------------------------------+
+; Missing 1-Value Coverage                        ;
++-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-----------+------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 0 during simulation.
++-------------------------------------------------+
+; Missing 0-Value Coverage                        ;
++-----------+------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-----------+------------------+------------------+
+
+
++---------------------+
+; Simulator INI Usage ;
++--------+------------+
+; Option ; Usage      ;
++--------+------------+
+
+
++--------------------+
+; Simulator Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Simulator
+    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+    Info: Processing started: Fri Mar 10 13:17:43 2017
+Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
+Info: Can't find specified vector source file "C:/FireBee/FPGA/firebee1.vwf"
+Warning: Can't display state machine states -- register holding state machine bit "|firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" was synthesized away
+Error: No valid vector source file specified and default file "C:/FireBee/FPGA/firebee1.cvwf" does not exist
+Error: Quartus II Simulator was unsuccessful. 1 error, 1 warning
+    Error: Peak virtual memory: 241 megabytes
+    Error: Processing ended: Fri Mar 10 13:17:46 2017
+    Error: Elapsed time: 00:00:03
+    Error: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
index 2b4b381..4f5907a 100644
--- a/FPGA_by_Fredi/firebee1.tan.summary
+++ b/FPGA_by_Fredi/firebee1.tan.summary
@@ -3,170 +3,180 @@ Timing Analyzer Summary
 --------------------------------------------------------------------------------------
 
 Type           : Worst-case tsu
-Slack          : -10.339 ns
+Slack          : -10.689 ns
 Required Time  : 1.000 ns
-Actual Time    : 11.339 ns
-From           : FB_SIZE1
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2]
+Actual Time    : 11.689 ns
+From           : nFB_CS1
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
 From Clock     : --
 To Clock       : MAIN_CLK
-Failed Paths   : 10192
+Failed Paths   : 9930
 
 Type           : Worst-case tco
-Slack          : -14.371 ns
+Slack          : -14.089 ns
 Required Time  : 1.000 ns
-Actual Time    : 15.371 ns
-From           : interrupt_handler:nobody|RTC_ADR[0]
-To             : FB_AD[18]
+Actual Time    : 15.089 ns
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]
+To             : FB_AD[27]
 From Clock     : MAIN_CLK
 To Clock       : --
-Failed Paths   : 5354
+Failed Paths   : 7401
 
 Type           : Worst-case tpd
-Slack          : -13.264 ns
+Slack          : -14.015 ns
 Required Time  : 1.000 ns
-Actual Time    : 14.264 ns
+Actual Time    : 15.015 ns
 From           : nFB_CS1
-To             : FB_AD[18]
+To             : FB_AD[27]
 From Clock     : --
 To Clock       : --
-Failed Paths   : 538
+Failed Paths   : 546
 
 Type           : Worst-case th
-Slack          : -0.110 ns
+Slack          : -0.258 ns
 Required Time  : 1.000 ns
-Actual Time    : 1.110 ns
-From           : VD[31]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
+Actual Time    : 1.258 ns
+From           : FB_AD[20]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0~porta_datain_reg0
 From Clock     : --
 To Clock       : MAIN_CLK
-Failed Paths   : 2
+Failed Paths   : 16
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : -17.845 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO
+From Clock     : MAIN_CLK
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+Failed Paths   : 29183
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : -11.412 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]
+From Clock     : MAIN_CLK
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 25165
 
 Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -7.918 ns
+Slack          : -6.848 ns
 Required Time  : 25.00 MHz ( period = 39.999 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
 From Clock     : MAIN_CLK
 To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 4748
+Failed Paths   : 5329
+
+Type           : Clock Setup: 'MAIN_CLK'
+Slack          : -6.482 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE.T8
+From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[0]
+To Clock       : MAIN_CLK
+Failed Paths   : 43303
 
 Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : -6.799 ns
+Slack          : -6.153 ns
 Required Time  : 96.01 MHz ( period = 10.416 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
 From Clock     : MAIN_CLK
 To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 4694
-
-Type           : Clock Setup: 'MAIN_CLK'
-Slack          : -5.955 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|nBLANK
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : MAIN_CLK
-Failed Paths   : 41276
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : -5.567 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 129
+Failed Paths   : 5302
 
 Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : -4.614 ns
+Slack          : -4.613 ns
 Required Time  : 16.00 MHz ( period = 62.499 ns )
 Actual Time    : N/A
-From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4]
+From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
 To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-Failed Paths   : 2882
+Failed Paths   : 2876
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : -3.520 ns
+Slack          : -3.386 ns
 Required Time  : 66.00 MHz ( period = 15.151 ns )
 Actual Time    : N/A
 From           : FB_ALE
-To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
+To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]
 From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 29
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 2.410 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR
-To             : Video:Fredi_Aschwanden|inst90~_Duplicate_2
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 0
+Failed Paths   : 33
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
 Slack          : 2.966 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 Failed Paths   : 0
 
 Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 5.144 ns
+Slack          : 5.489 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
 Failed Paths   : 0
 
 Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
-Slack          : 26.171 ns
+Slack          : 27.221 ns
 Required Time  : 0.50 MHz ( period = 1999.998 ns )
 Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[0]
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.PARITY
 To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
 From Clock     : MAIN_CLK
 To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
 Failed Paths   : 0
 
 Type           : Clock Hold: 'MAIN_CLK'
-Slack          : -3.299 ns
+Slack          : -4.871 ns
 Required Time  : 33.00 MHz ( period = 30.303 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2]
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4]
 From Clock     : MAIN_CLK
 To Clock       : MAIN_CLK
-Failed Paths   : 529
+Failed Paths   : 764
 
 Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -0.640 ns
+Slack          : -0.116 ns
 Required Time  : 25.00 MHz ( period = 39.999 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
 From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
 To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 33
+Failed Paths   : 136
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : 0.491 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|a_graycounter_pjc:wrptr_gp|counter11a[0]
+To             : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|altsyncram_fo31:fifo_ram|ram_block12a79~porta_address_reg0
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 0
 
 Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : 0.453 ns
+Slack          : 0.500 ns
 Required Time  : 16.00 MHz ( period = 62.499 ns )
 Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[6]
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8]
 To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
 From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
 To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
@@ -182,28 +192,28 @@ From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generat
 To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
 Failed Paths   : 0
 
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
-To             : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 0
-
 Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
 Slack          : 0.502 ns
 Required Time  : 96.01 MHz ( period = 10.416 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]
+From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
 From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
 To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
 Failed Paths   : 0
 
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 1.812 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
 Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : 1.775 ns
+Slack          : 2.489 ns
 Required Time  : 66.00 MHz ( period = 15.151 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
@@ -212,22 +222,12 @@ From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generat
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
 Failed Paths   : 0
 
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 1.829 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
 Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 2.585 ns
+Slack          : 3.193 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
 From           : Video:Fredi_Aschwanden|inst90~_Duplicate_4
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
 Failed Paths   : 0
@@ -236,8 +236,8 @@ Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2
 Slack          : 4.335 ns
 Required Time  : 132.01 MHz ( period = 7.575 ns )
 Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]
 From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
 Failed Paths   : 0
@@ -250,7 +250,7 @@ From           :
 To             : 
 From Clock     : 
 To Clock       : 
-Failed Paths   : 70406
+Failed Paths   : 129984
 
 --------------------------------------------------------------------------------------
 
diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws
new file mode 100644
index 0000000..7f27155
--- /dev/null
+++ b/FPGA_by_Fredi/firebeei1.qws
@@ -0,0 +1,16 @@
+[ProjectWorkspace]
+ptn_Child1=Frames
+[ProjectWorkspace.Frames]
+ptn_Child1=ChildFrames
+[ProjectWorkspace.Frames.ChildFrames]
+ptn_Child1=Document-0
+ptn_Child2=Document-1
+ptn_Child3=Document-2
+[ProjectWorkspace.Frames.ChildFrames.Document-0]
+ptn_Child1=ViewFrame-0
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
+DocPathName=firebee1.bdf
+DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
+IsChildFrameDetached=False
+IsActiveChildFrame=False
+ptn_Child1=StateMap
diff --git a/FPGA_by_Fredi/incremental_db/README b/FPGA_by_Fredi/incremental_db/README
deleted file mode 100644
index 6191fbe..0000000
--- a/FPGA_by_Fredi/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used.  To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.cdb
deleted file mode 100644
index 02d4502eef5a779b397c54db97384993da1e0770..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.dfp
deleted file mode 100644
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.hdb
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.kpt
deleted file mode 100644
index 8376a16a777965d247e2be94522a44af87095a22..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
deleted file mode 100644
index 4107b3a..0000000
--- a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.logdb
+++ /dev/null
@@ -1,5 +0,0 @@
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.cmp.rcfdb
deleted file mode 100644
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GIT binary patch
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diff --git a/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm b/FPGA_by_Fredi/incremental_db/compiled_partitions/firebee1.root_partition.merge_hb.atm
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diff --git a/FPGA_by_Fredi/lpm_counter0_waveforms.html b/FPGA_by_Fredi/lpm_counter0_waveforms.html
deleted file mode 100644
index b166f94..0000000
--- a/FPGA_by_Fredi/lpm_counter0_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for lpm_counter0.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_counter0.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter. </P>
-<CENTER><img src=lpm_counter0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
-<P><FONT size=3></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/lpm_mux0.s19 b/FPGA_by_Fredi/lpm_mux0.s19
new file mode 100644
index 0000000..24ed413
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux0.s19
@@ -0,0 +1,185 @@
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diff --git a/FPGA_by_Fredi/lpm_mux1.bsf b/FPGA_by_Fredi/lpm_mux1.bsf
new file mode 100644
index 0000000..68b1b1c
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux1.bsf
@@ -0,0 +1,1838 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
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+		(input)
+		(text "data17x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data17x[127..0]" (rect 4 3835 78 3848)(font "Arial" (font_size 8)))
+		(line (pt 0 3848)(pt 88 3848)(line_width 3))
+	)
+	(port
+		(pt 0 3864)
+		(input)
+		(text "data16x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data16x[127..0]" (rect 4 3851 78 3864)(font "Arial" (font_size 8)))
+		(line (pt 0 3864)(pt 88 3864)(line_width 3))
+	)
+	(port
+		(pt 0 3880)
+		(input)
+		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 3867 78 3880)(font "Arial" (font_size 8)))
+		(line (pt 0 3880)(pt 88 3880)(line_width 3))
+	)
+	(port
+		(pt 0 3896)
+		(input)
+		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 3883 78 3896)(font "Arial" (font_size 8)))
+		(line (pt 0 3896)(pt 88 3896)(line_width 3))
+	)
+	(port
+		(pt 0 3912)
+		(input)
+		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 3899 78 3912)(font "Arial" (font_size 8)))
+		(line (pt 0 3912)(pt 88 3912)(line_width 3))
+	)
+	(port
+		(pt 0 3928)
+		(input)
+		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 3915 78 3928)(font "Arial" (font_size 8)))
+		(line (pt 0 3928)(pt 88 3928)(line_width 3))
+	)
+	(port
+		(pt 0 3944)
+		(input)
+		(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 3931 78 3944)(font "Arial" (font_size 8)))
+		(line (pt 0 3944)(pt 88 3944)(line_width 3))
+	)
+	(port
+		(pt 0 3960)
+		(input)
+		(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 3947 78 3960)(font "Arial" (font_size 8)))
+		(line (pt 0 3960)(pt 88 3960)(line_width 3))
+	)
+	(port
+		(pt 0 3976)
+		(input)
+		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 3963 72 3976)(font "Arial" (font_size 8)))
+		(line (pt 0 3976)(pt 88 3976)(line_width 3))
+	)
+	(port
+		(pt 0 3992)
+		(input)
+		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 3979 72 3992)(font "Arial" (font_size 8)))
+		(line (pt 0 3992)(pt 88 3992)(line_width 3))
+	)
+	(port
+		(pt 0 4008)
+		(input)
+		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 3995 72 4008)(font "Arial" (font_size 8)))
+		(line (pt 0 4008)(pt 88 4008)(line_width 3))
+	)
+	(port
+		(pt 0 4024)
+		(input)
+		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 4011 72 4024)(font "Arial" (font_size 8)))
+		(line (pt 0 4024)(pt 88 4024)(line_width 3))
+	)
+	(port
+		(pt 0 4040)
+		(input)
+		(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 4027 72 4040)(font "Arial" (font_size 8)))
+		(line (pt 0 4040)(pt 88 4040)(line_width 3))
+	)
+	(port
+		(pt 0 4056)
+		(input)
+		(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 4043 72 4056)(font "Arial" (font_size 8)))
+		(line (pt 0 4056)(pt 88 4056)(line_width 3))
+	)
+	(port
+		(pt 0 4072)
+		(input)
+		(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 4059 72 4072)(font "Arial" (font_size 8)))
+		(line (pt 0 4072)(pt 88 4072)(line_width 3))
+	)
+	(port
+		(pt 0 4088)
+		(input)
+		(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 4075 72 4088)(font "Arial" (font_size 8)))
+		(line (pt 0 4088)(pt 88 4088)(line_width 3))
+	)
+	(port
+		(pt 0 4104)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 4091 72 4104)(font "Arial" (font_size 8)))
+		(line (pt 0 4104)(pt 88 4104)(line_width 3))
+	)
+	(port
+		(pt 0 4120)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 4107 72 4120)(font "Arial" (font_size 8)))
+		(line (pt 0 4120)(pt 88 4120)(line_width 3))
+	)
+	(port
+		(pt 96 4144)
+		(input)
+		(text "sel[7..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[7..0]" (rect 100 4131 137 4144)(font "Arial" (font_size 8)))
+		(line (pt 96 4144)(pt 96 4132)(line_width 3))
+	)
+	(port
+		(pt 176 2080)
+		(output)
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 110 2067 171 2080)(font "Arial" (font_size 8)))
+		(line (pt 176 2080)(pt 104 2080)(line_width 3))
+	)
+	(drawing
+		(line (pt 88 24)(pt 88 4136)(line_width 1))
+		(line (pt 104 32)(pt 104 4128)(line_width 1))
+		(line (pt 88 24)(pt 104 32)(line_width 1))
+		(line (pt 88 4136)(pt 104 4128)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/lpm_mux1.cmp b/FPGA_by_Fredi/lpm_mux1.cmp
new file mode 100644
index 0000000..970de1c
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux1.cmp
@@ -0,0 +1,278 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component lpm_mux1
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data100x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data101x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data102x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data103x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data104x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data105x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data106x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data107x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data108x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data109x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data110x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data111x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data112x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data113x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data114x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data115x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data116x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data117x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data118x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data119x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data120x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data121x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data122x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data123x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data124x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data125x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data126x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data127x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data128x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data129x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data130x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data131x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data132x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data133x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data134x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data135x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data136x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data137x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data138x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data139x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data140x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data141x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data142x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data143x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data144x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data145x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data146x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data147x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data148x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data149x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data150x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data151x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data152x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data153x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data154x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data155x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data156x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data157x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data158x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data159x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data160x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data161x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data162x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data163x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data164x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data165x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data166x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data167x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data168x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data169x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data16x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data170x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data171x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data172x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data173x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data174x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data175x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data176x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data177x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data178x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data179x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data17x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data180x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data181x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data182x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data183x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data184x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data185x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data186x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data187x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data188x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data189x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data18x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data190x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data191x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data192x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data193x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data194x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data195x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data196x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data197x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data198x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data199x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data19x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data200x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data201x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data202x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data203x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data204x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data205x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data206x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data207x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data208x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data209x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data20x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data210x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data211x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data212x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data213x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data214x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data215x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data216x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data217x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data218x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data219x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data21x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data220x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data221x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data222x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data223x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data224x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data225x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data226x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data227x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data228x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data229x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data22x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data230x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data231x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data232x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data233x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data234x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data235x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data236x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data237x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data238x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data239x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data23x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data240x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data241x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data242x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data243x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data244x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data245x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data246x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data247x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data248x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data249x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data24x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data250x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data251x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data252x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data253x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data254x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data255x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data25x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data26x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data27x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data28x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data29x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data30x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data31x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data32x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data33x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data34x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data35x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data36x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data37x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data38x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data39x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data40x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data41x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data42x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data43x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data44x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data45x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data46x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data47x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data48x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data49x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data50x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data51x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data52x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data53x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data54x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data55x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data56x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data57x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data58x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data59x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data60x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data61x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data62x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data63x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data64x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data65x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data66x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data67x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data68x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data69x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data70x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data71x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data72x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data73x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data74x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data75x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data76x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data77x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data78x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data79x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data80x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data81x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data82x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data83x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data84x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data85x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data86x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data87x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data88x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data89x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data90x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data91x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data92x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data93x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data94x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data95x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data96x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data97x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data98x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data99x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_by_Fredi/lpm_mux1.inc b/FPGA_by_Fredi/lpm_mux1.inc
new file mode 100644
index 0000000..6411e4f
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux1.inc
@@ -0,0 +1,279 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux1 
+(
+	data0x[127..0],
+	data100x[127..0],
+	data101x[127..0],
+	data102x[127..0],
+	data103x[127..0],
+	data104x[127..0],
+	data105x[127..0],
+	data106x[127..0],
+	data107x[127..0],
+	data108x[127..0],
+	data109x[127..0],
+	data10x[127..0],
+	data110x[127..0],
+	data111x[127..0],
+	data112x[127..0],
+	data113x[127..0],
+	data114x[127..0],
+	data115x[127..0],
+	data116x[127..0],
+	data117x[127..0],
+	data118x[127..0],
+	data119x[127..0],
+	data11x[127..0],
+	data120x[127..0],
+	data121x[127..0],
+	data122x[127..0],
+	data123x[127..0],
+	data124x[127..0],
+	data125x[127..0],
+	data126x[127..0],
+	data127x[127..0],
+	data128x[127..0],
+	data129x[127..0],
+	data12x[127..0],
+	data130x[127..0],
+	data131x[127..0],
+	data132x[127..0],
+	data133x[127..0],
+	data134x[127..0],
+	data135x[127..0],
+	data136x[127..0],
+	data137x[127..0],
+	data138x[127..0],
+	data139x[127..0],
+	data13x[127..0],
+	data140x[127..0],
+	data141x[127..0],
+	data142x[127..0],
+	data143x[127..0],
+	data144x[127..0],
+	data145x[127..0],
+	data146x[127..0],
+	data147x[127..0],
+	data148x[127..0],
+	data149x[127..0],
+	data14x[127..0],
+	data150x[127..0],
+	data151x[127..0],
+	data152x[127..0],
+	data153x[127..0],
+	data154x[127..0],
+	data155x[127..0],
+	data156x[127..0],
+	data157x[127..0],
+	data158x[127..0],
+	data159x[127..0],
+	data15x[127..0],
+	data160x[127..0],
+	data161x[127..0],
+	data162x[127..0],
+	data163x[127..0],
+	data164x[127..0],
+	data165x[127..0],
+	data166x[127..0],
+	data167x[127..0],
+	data168x[127..0],
+	data169x[127..0],
+	data16x[127..0],
+	data170x[127..0],
+	data171x[127..0],
+	data172x[127..0],
+	data173x[127..0],
+	data174x[127..0],
+	data175x[127..0],
+	data176x[127..0],
+	data177x[127..0],
+	data178x[127..0],
+	data179x[127..0],
+	data17x[127..0],
+	data180x[127..0],
+	data181x[127..0],
+	data182x[127..0],
+	data183x[127..0],
+	data184x[127..0],
+	data185x[127..0],
+	data186x[127..0],
+	data187x[127..0],
+	data188x[127..0],
+	data189x[127..0],
+	data18x[127..0],
+	data190x[127..0],
+	data191x[127..0],
+	data192x[127..0],
+	data193x[127..0],
+	data194x[127..0],
+	data195x[127..0],
+	data196x[127..0],
+	data197x[127..0],
+	data198x[127..0],
+	data199x[127..0],
+	data19x[127..0],
+	data1x[127..0],
+	data200x[127..0],
+	data201x[127..0],
+	data202x[127..0],
+	data203x[127..0],
+	data204x[127..0],
+	data205x[127..0],
+	data206x[127..0],
+	data207x[127..0],
+	data208x[127..0],
+	data209x[127..0],
+	data20x[127..0],
+	data210x[127..0],
+	data211x[127..0],
+	data212x[127..0],
+	data213x[127..0],
+	data214x[127..0],
+	data215x[127..0],
+	data216x[127..0],
+	data217x[127..0],
+	data218x[127..0],
+	data219x[127..0],
+	data21x[127..0],
+	data220x[127..0],
+	data221x[127..0],
+	data222x[127..0],
+	data223x[127..0],
+	data224x[127..0],
+	data225x[127..0],
+	data226x[127..0],
+	data227x[127..0],
+	data228x[127..0],
+	data229x[127..0],
+	data22x[127..0],
+	data230x[127..0],
+	data231x[127..0],
+	data232x[127..0],
+	data233x[127..0],
+	data234x[127..0],
+	data235x[127..0],
+	data236x[127..0],
+	data237x[127..0],
+	data238x[127..0],
+	data239x[127..0],
+	data23x[127..0],
+	data240x[127..0],
+	data241x[127..0],
+	data242x[127..0],
+	data243x[127..0],
+	data244x[127..0],
+	data245x[127..0],
+	data246x[127..0],
+	data247x[127..0],
+	data248x[127..0],
+	data249x[127..0],
+	data24x[127..0],
+	data250x[127..0],
+	data251x[127..0],
+	data252x[127..0],
+	data253x[127..0],
+	data254x[127..0],
+	data255x[127..0],
+	data25x[127..0],
+	data26x[127..0],
+	data27x[127..0],
+	data28x[127..0],
+	data29x[127..0],
+	data2x[127..0],
+	data30x[127..0],
+	data31x[127..0],
+	data32x[127..0],
+	data33x[127..0],
+	data34x[127..0],
+	data35x[127..0],
+	data36x[127..0],
+	data37x[127..0],
+	data38x[127..0],
+	data39x[127..0],
+	data3x[127..0],
+	data40x[127..0],
+	data41x[127..0],
+	data42x[127..0],
+	data43x[127..0],
+	data44x[127..0],
+	data45x[127..0],
+	data46x[127..0],
+	data47x[127..0],
+	data48x[127..0],
+	data49x[127..0],
+	data4x[127..0],
+	data50x[127..0],
+	data51x[127..0],
+	data52x[127..0],
+	data53x[127..0],
+	data54x[127..0],
+	data55x[127..0],
+	data56x[127..0],
+	data57x[127..0],
+	data58x[127..0],
+	data59x[127..0],
+	data5x[127..0],
+	data60x[127..0],
+	data61x[127..0],
+	data62x[127..0],
+	data63x[127..0],
+	data64x[127..0],
+	data65x[127..0],
+	data66x[127..0],
+	data67x[127..0],
+	data68x[127..0],
+	data69x[127..0],
+	data6x[127..0],
+	data70x[127..0],
+	data71x[127..0],
+	data72x[127..0],
+	data73x[127..0],
+	data74x[127..0],
+	data75x[127..0],
+	data76x[127..0],
+	data77x[127..0],
+	data78x[127..0],
+	data79x[127..0],
+	data7x[127..0],
+	data80x[127..0],
+	data81x[127..0],
+	data82x[127..0],
+	data83x[127..0],
+	data84x[127..0],
+	data85x[127..0],
+	data86x[127..0],
+	data87x[127..0],
+	data88x[127..0],
+	data89x[127..0],
+	data8x[127..0],
+	data90x[127..0],
+	data91x[127..0],
+	data92x[127..0],
+	data93x[127..0],
+	data94x[127..0],
+	data95x[127..0],
+	data96x[127..0],
+	data97x[127..0],
+	data98x[127..0],
+	data99x[127..0],
+	data9x[127..0],
+	sel[7..0]
+)
+
+RETURNS (
+	result[127..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip b/FPGA_by_Fredi/lpm_mux1.qip
similarity index 64%
rename from FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip
rename to FPGA_by_Fredi/lpm_mux1.qip
index 737f0c0..95bd729 100644
--- a/FPGA_by_Fredi/Video/BLITTER/lpm_clshift0.qip
+++ b/FPGA_by_Fredi/lpm_mux1.qip
@@ -1,6 +1,6 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
 set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]
diff --git a/FPGA_by_Fredi/lpm_mux1.tdf b/FPGA_by_Fredi/lpm_mux1.tdf
new file mode 100644
index 0000000..2012850
--- /dev/null
+++ b/FPGA_by_Fredi/lpm_mux1.tdf
@@ -0,0 +1,1105 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux1.tdf
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_mux.inc";
+
+
+
+SUBDESIGN lpm_mux1
+(
+	data0x[127..0]	 : INPUT;
+	data100x[127..0]	 : INPUT;
+	data101x[127..0]	 : INPUT;
+	data102x[127..0]	 : INPUT;
+	data103x[127..0]	 : INPUT;
+	data104x[127..0]	 : INPUT;
+	data105x[127..0]	 : INPUT;
+	data106x[127..0]	 : INPUT;
+	data107x[127..0]	 : INPUT;
+	data108x[127..0]	 : INPUT;
+	data109x[127..0]	 : INPUT;
+	data10x[127..0]	 : INPUT;
+	data110x[127..0]	 : INPUT;
+	data111x[127..0]	 : INPUT;
+	data112x[127..0]	 : INPUT;
+	data113x[127..0]	 : INPUT;
+	data114x[127..0]	 : INPUT;
+	data115x[127..0]	 : INPUT;
+	data116x[127..0]	 : INPUT;
+	data117x[127..0]	 : INPUT;
+	data118x[127..0]	 : INPUT;
+	data119x[127..0]	 : INPUT;
+	data11x[127..0]	 : INPUT;
+	data120x[127..0]	 : INPUT;
+	data121x[127..0]	 : INPUT;
+	data122x[127..0]	 : INPUT;
+	data123x[127..0]	 : INPUT;
+	data124x[127..0]	 : INPUT;
+	data125x[127..0]	 : INPUT;
+	data126x[127..0]	 : INPUT;
+	data127x[127..0]	 : INPUT;
+	data128x[127..0]	 : INPUT;
+	data129x[127..0]	 : INPUT;
+	data12x[127..0]	 : INPUT;
+	data130x[127..0]	 : INPUT;
+	data131x[127..0]	 : INPUT;
+	data132x[127..0]	 : INPUT;
+	data133x[127..0]	 : INPUT;
+	data134x[127..0]	 : INPUT;
+	data135x[127..0]	 : INPUT;
+	data136x[127..0]	 : INPUT;
+	data137x[127..0]	 : INPUT;
+	data138x[127..0]	 : INPUT;
+	data139x[127..0]	 : INPUT;
+	data13x[127..0]	 : INPUT;
+	data140x[127..0]	 : INPUT;
+	data141x[127..0]	 : INPUT;
+	data142x[127..0]	 : INPUT;
+	data143x[127..0]	 : INPUT;
+	data144x[127..0]	 : INPUT;
+	data145x[127..0]	 : INPUT;
+	data146x[127..0]	 : INPUT;
+	data147x[127..0]	 : INPUT;
+	data148x[127..0]	 : INPUT;
+	data149x[127..0]	 : INPUT;
+	data14x[127..0]	 : INPUT;
+	data150x[127..0]	 : INPUT;
+	data151x[127..0]	 : INPUT;
+	data152x[127..0]	 : INPUT;
+	data153x[127..0]	 : INPUT;
+	data154x[127..0]	 : INPUT;
+	data155x[127..0]	 : INPUT;
+	data156x[127..0]	 : INPUT;
+	data157x[127..0]	 : INPUT;
+	data158x[127..0]	 : INPUT;
+	data159x[127..0]	 : INPUT;
+	data15x[127..0]	 : INPUT;
+	data160x[127..0]	 : INPUT;
+	data161x[127..0]	 : INPUT;
+	data162x[127..0]	 : INPUT;
+	data163x[127..0]	 : INPUT;
+	data164x[127..0]	 : INPUT;
+	data165x[127..0]	 : INPUT;
+	data166x[127..0]	 : INPUT;
+	data167x[127..0]	 : INPUT;
+	data168x[127..0]	 : INPUT;
+	data169x[127..0]	 : INPUT;
+	data16x[127..0]	 : INPUT;
+	data170x[127..0]	 : INPUT;
+	data171x[127..0]	 : INPUT;
+	data172x[127..0]	 : INPUT;
+	data173x[127..0]	 : INPUT;
+	data174x[127..0]	 : INPUT;
+	data175x[127..0]	 : INPUT;
+	data176x[127..0]	 : INPUT;
+	data177x[127..0]	 : INPUT;
+	data178x[127..0]	 : INPUT;
+	data179x[127..0]	 : INPUT;
+	data17x[127..0]	 : INPUT;
+	data180x[127..0]	 : INPUT;
+	data181x[127..0]	 : INPUT;
+	data182x[127..0]	 : INPUT;
+	data183x[127..0]	 : INPUT;
+	data184x[127..0]	 : INPUT;
+	data185x[127..0]	 : INPUT;
+	data186x[127..0]	 : INPUT;
+	data187x[127..0]	 : INPUT;
+	data188x[127..0]	 : INPUT;
+	data189x[127..0]	 : INPUT;
+	data18x[127..0]	 : INPUT;
+	data190x[127..0]	 : INPUT;
+	data191x[127..0]	 : INPUT;
+	data192x[127..0]	 : INPUT;
+	data193x[127..0]	 : INPUT;
+	data194x[127..0]	 : INPUT;
+	data195x[127..0]	 : INPUT;
+	data196x[127..0]	 : INPUT;
+	data197x[127..0]	 : INPUT;
+	data198x[127..0]	 : INPUT;
+	data199x[127..0]	 : INPUT;
+	data19x[127..0]	 : INPUT;
+	data1x[127..0]	 : INPUT;
+	data200x[127..0]	 : INPUT;
+	data201x[127..0]	 : INPUT;
+	data202x[127..0]	 : INPUT;
+	data203x[127..0]	 : INPUT;
+	data204x[127..0]	 : INPUT;
+	data205x[127..0]	 : INPUT;
+	data206x[127..0]	 : INPUT;
+	data207x[127..0]	 : INPUT;
+	data208x[127..0]	 : INPUT;
+	data209x[127..0]	 : INPUT;
+	data20x[127..0]	 : INPUT;
+	data210x[127..0]	 : INPUT;
+	data211x[127..0]	 : INPUT;
+	data212x[127..0]	 : INPUT;
+	data213x[127..0]	 : INPUT;
+	data214x[127..0]	 : INPUT;
+	data215x[127..0]	 : INPUT;
+	data216x[127..0]	 : INPUT;
+	data217x[127..0]	 : INPUT;
+	data218x[127..0]	 : INPUT;
+	data219x[127..0]	 : INPUT;
+	data21x[127..0]	 : INPUT;
+	data220x[127..0]	 : INPUT;
+	data221x[127..0]	 : INPUT;
+	data222x[127..0]	 : INPUT;
+	data223x[127..0]	 : INPUT;
+	data224x[127..0]	 : INPUT;
+	data225x[127..0]	 : INPUT;
+	data226x[127..0]	 : INPUT;
+	data227x[127..0]	 : INPUT;
+	data228x[127..0]	 : INPUT;
+	data229x[127..0]	 : INPUT;
+	data22x[127..0]	 : INPUT;
+	data230x[127..0]	 : INPUT;
+	data231x[127..0]	 : INPUT;
+	data232x[127..0]	 : INPUT;
+	data233x[127..0]	 : INPUT;
+	data234x[127..0]	 : INPUT;
+	data235x[127..0]	 : INPUT;
+	data236x[127..0]	 : INPUT;
+	data237x[127..0]	 : INPUT;
+	data238x[127..0]	 : INPUT;
+	data239x[127..0]	 : INPUT;
+	data23x[127..0]	 : INPUT;
+	data240x[127..0]	 : INPUT;
+	data241x[127..0]	 : INPUT;
+	data242x[127..0]	 : INPUT;
+	data243x[127..0]	 : INPUT;
+	data244x[127..0]	 : INPUT;
+	data245x[127..0]	 : INPUT;
+	data246x[127..0]	 : INPUT;
+	data247x[127..0]	 : INPUT;
+	data248x[127..0]	 : INPUT;
+	data249x[127..0]	 : INPUT;
+	data24x[127..0]	 : INPUT;
+	data250x[127..0]	 : INPUT;
+	data251x[127..0]	 : INPUT;
+	data252x[127..0]	 : INPUT;
+	data253x[127..0]	 : INPUT;
+	data254x[127..0]	 : INPUT;
+	data255x[127..0]	 : INPUT;
+	data25x[127..0]	 : INPUT;
+	data26x[127..0]	 : INPUT;
+	data27x[127..0]	 : INPUT;
+	data28x[127..0]	 : INPUT;
+	data29x[127..0]	 : INPUT;
+	data2x[127..0]	 : INPUT;
+	data30x[127..0]	 : INPUT;
+	data31x[127..0]	 : INPUT;
+	data32x[127..0]	 : INPUT;
+	data33x[127..0]	 : INPUT;
+	data34x[127..0]	 : INPUT;
+	data35x[127..0]	 : INPUT;
+	data36x[127..0]	 : INPUT;
+	data37x[127..0]	 : INPUT;
+	data38x[127..0]	 : INPUT;
+	data39x[127..0]	 : INPUT;
+	data3x[127..0]	 : INPUT;
+	data40x[127..0]	 : INPUT;
+	data41x[127..0]	 : INPUT;
+	data42x[127..0]	 : INPUT;
+	data43x[127..0]	 : INPUT;
+	data44x[127..0]	 : INPUT;
+	data45x[127..0]	 : INPUT;
+	data46x[127..0]	 : INPUT;
+	data47x[127..0]	 : INPUT;
+	data48x[127..0]	 : INPUT;
+	data49x[127..0]	 : INPUT;
+	data4x[127..0]	 : INPUT;
+	data50x[127..0]	 : INPUT;
+	data51x[127..0]	 : INPUT;
+	data52x[127..0]	 : INPUT;
+	data53x[127..0]	 : INPUT;
+	data54x[127..0]	 : INPUT;
+	data55x[127..0]	 : INPUT;
+	data56x[127..0]	 : INPUT;
+	data57x[127..0]	 : INPUT;
+	data58x[127..0]	 : INPUT;
+	data59x[127..0]	 : INPUT;
+	data5x[127..0]	 : INPUT;
+	data60x[127..0]	 : INPUT;
+	data61x[127..0]	 : INPUT;
+	data62x[127..0]	 : INPUT;
+	data63x[127..0]	 : INPUT;
+	data64x[127..0]	 : INPUT;
+	data65x[127..0]	 : INPUT;
+	data66x[127..0]	 : INPUT;
+	data67x[127..0]	 : INPUT;
+	data68x[127..0]	 : INPUT;
+	data69x[127..0]	 : INPUT;
+	data6x[127..0]	 : INPUT;
+	data70x[127..0]	 : INPUT;
+	data71x[127..0]	 : INPUT;
+	data72x[127..0]	 : INPUT;
+	data73x[127..0]	 : INPUT;
+	data74x[127..0]	 : INPUT;
+	data75x[127..0]	 : INPUT;
+	data76x[127..0]	 : INPUT;
+	data77x[127..0]	 : INPUT;
+	data78x[127..0]	 : INPUT;
+	data79x[127..0]	 : INPUT;
+	data7x[127..0]	 : INPUT;
+	data80x[127..0]	 : INPUT;
+	data81x[127..0]	 : INPUT;
+	data82x[127..0]	 : INPUT;
+	data83x[127..0]	 : INPUT;
+	data84x[127..0]	 : INPUT;
+	data85x[127..0]	 : INPUT;
+	data86x[127..0]	 : INPUT;
+	data87x[127..0]	 : INPUT;
+	data88x[127..0]	 : INPUT;
+	data89x[127..0]	 : INPUT;
+	data8x[127..0]	 : INPUT;
+	data90x[127..0]	 : INPUT;
+	data91x[127..0]	 : INPUT;
+	data92x[127..0]	 : INPUT;
+	data93x[127..0]	 : INPUT;
+	data94x[127..0]	 : INPUT;
+	data95x[127..0]	 : INPUT;
+	data96x[127..0]	 : INPUT;
+	data97x[127..0]	 : INPUT;
+	data98x[127..0]	 : INPUT;
+	data99x[127..0]	 : INPUT;
+	data9x[127..0]	 : INPUT;
+	sel[7..0]	 : INPUT;
+	result[127..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_mux_component : lpm_mux WITH (
+			LPM_SIZE = 256,
+			LPM_TYPE = "LPM_MUX",
+			LPM_WIDTH = 128,
+			LPM_WIDTHS = 8
+			);
+
+BEGIN
+
+	result[127..0] = lpm_mux_component.result[127..0];
+	lpm_mux_component.sel[7..0] = sel[7..0];
+	lpm_mux_component.data[255..255][127..0] = data255x[127..0];
+	lpm_mux_component.data[254..254][127..0] = data254x[127..0];
+	lpm_mux_component.data[253..253][127..0] = data253x[127..0];
+	lpm_mux_component.data[252..252][127..0] = data252x[127..0];
+	lpm_mux_component.data[251..251][127..0] = data251x[127..0];
+	lpm_mux_component.data[250..250][127..0] = data250x[127..0];
+	lpm_mux_component.data[249..249][127..0] = data249x[127..0];
+	lpm_mux_component.data[248..248][127..0] = data248x[127..0];
+	lpm_mux_component.data[247..247][127..0] = data247x[127..0];
+	lpm_mux_component.data[246..246][127..0] = data246x[127..0];
+	lpm_mux_component.data[245..245][127..0] = data245x[127..0];
+	lpm_mux_component.data[244..244][127..0] = data244x[127..0];
+	lpm_mux_component.data[243..243][127..0] = data243x[127..0];
+	lpm_mux_component.data[242..242][127..0] = data242x[127..0];
+	lpm_mux_component.data[241..241][127..0] = data241x[127..0];
+	lpm_mux_component.data[240..240][127..0] = data240x[127..0];
+	lpm_mux_component.data[239..239][127..0] = data239x[127..0];
+	lpm_mux_component.data[238..238][127..0] = data238x[127..0];
+	lpm_mux_component.data[237..237][127..0] = data237x[127..0];
+	lpm_mux_component.data[236..236][127..0] = data236x[127..0];
+	lpm_mux_component.data[235..235][127..0] = data235x[127..0];
+	lpm_mux_component.data[234..234][127..0] = data234x[127..0];
+	lpm_mux_component.data[233..233][127..0] = data233x[127..0];
+	lpm_mux_component.data[232..232][127..0] = data232x[127..0];
+	lpm_mux_component.data[231..231][127..0] = data231x[127..0];
+	lpm_mux_component.data[230..230][127..0] = data230x[127..0];
+	lpm_mux_component.data[229..229][127..0] = data229x[127..0];
+	lpm_mux_component.data[228..228][127..0] = data228x[127..0];
+	lpm_mux_component.data[227..227][127..0] = data227x[127..0];
+	lpm_mux_component.data[226..226][127..0] = data226x[127..0];
+	lpm_mux_component.data[225..225][127..0] = data225x[127..0];
+	lpm_mux_component.data[224..224][127..0] = data224x[127..0];
+	lpm_mux_component.data[223..223][127..0] = data223x[127..0];
+	lpm_mux_component.data[222..222][127..0] = data222x[127..0];
+	lpm_mux_component.data[221..221][127..0] = data221x[127..0];
+	lpm_mux_component.data[220..220][127..0] = data220x[127..0];
+	lpm_mux_component.data[219..219][127..0] = data219x[127..0];
+	lpm_mux_component.data[218..218][127..0] = data218x[127..0];
+	lpm_mux_component.data[217..217][127..0] = data217x[127..0];
+	lpm_mux_component.data[216..216][127..0] = data216x[127..0];
+	lpm_mux_component.data[215..215][127..0] = data215x[127..0];
+	lpm_mux_component.data[214..214][127..0] = data214x[127..0];
+	lpm_mux_component.data[213..213][127..0] = data213x[127..0];
+	lpm_mux_component.data[212..212][127..0] = data212x[127..0];
+	lpm_mux_component.data[211..211][127..0] = data211x[127..0];
+	lpm_mux_component.data[210..210][127..0] = data210x[127..0];
+	lpm_mux_component.data[209..209][127..0] = data209x[127..0];
+	lpm_mux_component.data[208..208][127..0] = data208x[127..0];
+	lpm_mux_component.data[207..207][127..0] = data207x[127..0];
+	lpm_mux_component.data[206..206][127..0] = data206x[127..0];
+	lpm_mux_component.data[205..205][127..0] = data205x[127..0];
+	lpm_mux_component.data[204..204][127..0] = data204x[127..0];
+	lpm_mux_component.data[203..203][127..0] = data203x[127..0];
+	lpm_mux_component.data[202..202][127..0] = data202x[127..0];
+	lpm_mux_component.data[201..201][127..0] = data201x[127..0];
+	lpm_mux_component.data[200..200][127..0] = data200x[127..0];
+	lpm_mux_component.data[199..199][127..0] = data199x[127..0];
+	lpm_mux_component.data[198..198][127..0] = data198x[127..0];
+	lpm_mux_component.data[197..197][127..0] = data197x[127..0];
+	lpm_mux_component.data[196..196][127..0] = data196x[127..0];
+	lpm_mux_component.data[195..195][127..0] = data195x[127..0];
+	lpm_mux_component.data[194..194][127..0] = data194x[127..0];
+	lpm_mux_component.data[193..193][127..0] = data193x[127..0];
+	lpm_mux_component.data[192..192][127..0] = data192x[127..0];
+	lpm_mux_component.data[191..191][127..0] = data191x[127..0];
+	lpm_mux_component.data[190..190][127..0] = data190x[127..0];
+	lpm_mux_component.data[189..189][127..0] = data189x[127..0];
+	lpm_mux_component.data[188..188][127..0] = data188x[127..0];
+	lpm_mux_component.data[187..187][127..0] = data187x[127..0];
+	lpm_mux_component.data[186..186][127..0] = data186x[127..0];
+	lpm_mux_component.data[185..185][127..0] = data185x[127..0];
+	lpm_mux_component.data[184..184][127..0] = data184x[127..0];
+	lpm_mux_component.data[183..183][127..0] = data183x[127..0];
+	lpm_mux_component.data[182..182][127..0] = data182x[127..0];
+	lpm_mux_component.data[181..181][127..0] = data181x[127..0];
+	lpm_mux_component.data[180..180][127..0] = data180x[127..0];
+	lpm_mux_component.data[179..179][127..0] = data179x[127..0];
+	lpm_mux_component.data[178..178][127..0] = data178x[127..0];
+	lpm_mux_component.data[177..177][127..0] = data177x[127..0];
+	lpm_mux_component.data[176..176][127..0] = data176x[127..0];
+	lpm_mux_component.data[175..175][127..0] = data175x[127..0];
+	lpm_mux_component.data[174..174][127..0] = data174x[127..0];
+	lpm_mux_component.data[173..173][127..0] = data173x[127..0];
+	lpm_mux_component.data[172..172][127..0] = data172x[127..0];
+	lpm_mux_component.data[171..171][127..0] = data171x[127..0];
+	lpm_mux_component.data[170..170][127..0] = data170x[127..0];
+	lpm_mux_component.data[169..169][127..0] = data169x[127..0];
+	lpm_mux_component.data[168..168][127..0] = data168x[127..0];
+	lpm_mux_component.data[167..167][127..0] = data167x[127..0];
+	lpm_mux_component.data[166..166][127..0] = data166x[127..0];
+	lpm_mux_component.data[165..165][127..0] = data165x[127..0];
+	lpm_mux_component.data[164..164][127..0] = data164x[127..0];
+	lpm_mux_component.data[163..163][127..0] = data163x[127..0];
+	lpm_mux_component.data[162..162][127..0] = data162x[127..0];
+	lpm_mux_component.data[161..161][127..0] = data161x[127..0];
+	lpm_mux_component.data[160..160][127..0] = data160x[127..0];
+	lpm_mux_component.data[159..159][127..0] = data159x[127..0];
+	lpm_mux_component.data[158..158][127..0] = data158x[127..0];
+	lpm_mux_component.data[157..157][127..0] = data157x[127..0];
+	lpm_mux_component.data[156..156][127..0] = data156x[127..0];
+	lpm_mux_component.data[155..155][127..0] = data155x[127..0];
+	lpm_mux_component.data[154..154][127..0] = data154x[127..0];
+	lpm_mux_component.data[153..153][127..0] = data153x[127..0];
+	lpm_mux_component.data[152..152][127..0] = data152x[127..0];
+	lpm_mux_component.data[151..151][127..0] = data151x[127..0];
+	lpm_mux_component.data[150..150][127..0] = data150x[127..0];
+	lpm_mux_component.data[149..149][127..0] = data149x[127..0];
+	lpm_mux_component.data[148..148][127..0] = data148x[127..0];
+	lpm_mux_component.data[147..147][127..0] = data147x[127..0];
+	lpm_mux_component.data[146..146][127..0] = data146x[127..0];
+	lpm_mux_component.data[145..145][127..0] = data145x[127..0];
+	lpm_mux_component.data[144..144][127..0] = data144x[127..0];
+	lpm_mux_component.data[143..143][127..0] = data143x[127..0];
+	lpm_mux_component.data[142..142][127..0] = data142x[127..0];
+	lpm_mux_component.data[141..141][127..0] = data141x[127..0];
+	lpm_mux_component.data[140..140][127..0] = data140x[127..0];
+	lpm_mux_component.data[139..139][127..0] = data139x[127..0];
+	lpm_mux_component.data[138..138][127..0] = data138x[127..0];
+	lpm_mux_component.data[137..137][127..0] = data137x[127..0];
+	lpm_mux_component.data[136..136][127..0] = data136x[127..0];
+	lpm_mux_component.data[135..135][127..0] = data135x[127..0];
+	lpm_mux_component.data[134..134][127..0] = data134x[127..0];
+	lpm_mux_component.data[133..133][127..0] = data133x[127..0];
+	lpm_mux_component.data[132..132][127..0] = data132x[127..0];
+	lpm_mux_component.data[131..131][127..0] = data131x[127..0];
+	lpm_mux_component.data[130..130][127..0] = data130x[127..0];
+	lpm_mux_component.data[129..129][127..0] = data129x[127..0];
+	lpm_mux_component.data[128..128][127..0] = data128x[127..0];
+	lpm_mux_component.data[127..127][127..0] = data127x[127..0];
+	lpm_mux_component.data[126..126][127..0] = data126x[127..0];
+	lpm_mux_component.data[125..125][127..0] = data125x[127..0];
+	lpm_mux_component.data[124..124][127..0] = data124x[127..0];
+	lpm_mux_component.data[123..123][127..0] = data123x[127..0];
+	lpm_mux_component.data[122..122][127..0] = data122x[127..0];
+	lpm_mux_component.data[121..121][127..0] = data121x[127..0];
+	lpm_mux_component.data[120..120][127..0] = data120x[127..0];
+	lpm_mux_component.data[119..119][127..0] = data119x[127..0];
+	lpm_mux_component.data[118..118][127..0] = data118x[127..0];
+	lpm_mux_component.data[117..117][127..0] = data117x[127..0];
+	lpm_mux_component.data[116..116][127..0] = data116x[127..0];
+	lpm_mux_component.data[115..115][127..0] = data115x[127..0];
+	lpm_mux_component.data[114..114][127..0] = data114x[127..0];
+	lpm_mux_component.data[113..113][127..0] = data113x[127..0];
+	lpm_mux_component.data[112..112][127..0] = data112x[127..0];
+	lpm_mux_component.data[111..111][127..0] = data111x[127..0];
+	lpm_mux_component.data[110..110][127..0] = data110x[127..0];
+	lpm_mux_component.data[109..109][127..0] = data109x[127..0];
+	lpm_mux_component.data[108..108][127..0] = data108x[127..0];
+	lpm_mux_component.data[107..107][127..0] = data107x[127..0];
+	lpm_mux_component.data[106..106][127..0] = data106x[127..0];
+	lpm_mux_component.data[105..105][127..0] = data105x[127..0];
+	lpm_mux_component.data[104..104][127..0] = data104x[127..0];
+	lpm_mux_component.data[103..103][127..0] = data103x[127..0];
+	lpm_mux_component.data[102..102][127..0] = data102x[127..0];
+	lpm_mux_component.data[101..101][127..0] = data101x[127..0];
+	lpm_mux_component.data[100..100][127..0] = data100x[127..0];
+	lpm_mux_component.data[99..99][127..0] = data99x[127..0];
+	lpm_mux_component.data[98..98][127..0] = data98x[127..0];
+	lpm_mux_component.data[97..97][127..0] = data97x[127..0];
+	lpm_mux_component.data[96..96][127..0] = data96x[127..0];
+	lpm_mux_component.data[95..95][127..0] = data95x[127..0];
+	lpm_mux_component.data[94..94][127..0] = data94x[127..0];
+	lpm_mux_component.data[93..93][127..0] = data93x[127..0];
+	lpm_mux_component.data[92..92][127..0] = data92x[127..0];
+	lpm_mux_component.data[91..91][127..0] = data91x[127..0];
+	lpm_mux_component.data[90..90][127..0] = data90x[127..0];
+	lpm_mux_component.data[89..89][127..0] = data89x[127..0];
+	lpm_mux_component.data[88..88][127..0] = data88x[127..0];
+	lpm_mux_component.data[87..87][127..0] = data87x[127..0];
+	lpm_mux_component.data[86..86][127..0] = data86x[127..0];
+	lpm_mux_component.data[85..85][127..0] = data85x[127..0];
+	lpm_mux_component.data[84..84][127..0] = data84x[127..0];
+	lpm_mux_component.data[83..83][127..0] = data83x[127..0];
+	lpm_mux_component.data[82..82][127..0] = data82x[127..0];
+	lpm_mux_component.data[81..81][127..0] = data81x[127..0];
+	lpm_mux_component.data[80..80][127..0] = data80x[127..0];
+	lpm_mux_component.data[79..79][127..0] = data79x[127..0];
+	lpm_mux_component.data[78..78][127..0] = data78x[127..0];
+	lpm_mux_component.data[77..77][127..0] = data77x[127..0];
+	lpm_mux_component.data[76..76][127..0] = data76x[127..0];
+	lpm_mux_component.data[75..75][127..0] = data75x[127..0];
+	lpm_mux_component.data[74..74][127..0] = data74x[127..0];
+	lpm_mux_component.data[73..73][127..0] = data73x[127..0];
+	lpm_mux_component.data[72..72][127..0] = data72x[127..0];
+	lpm_mux_component.data[71..71][127..0] = data71x[127..0];
+	lpm_mux_component.data[70..70][127..0] = data70x[127..0];
+	lpm_mux_component.data[69..69][127..0] = data69x[127..0];
+	lpm_mux_component.data[68..68][127..0] = data68x[127..0];
+	lpm_mux_component.data[67..67][127..0] = data67x[127..0];
+	lpm_mux_component.data[66..66][127..0] = data66x[127..0];
+	lpm_mux_component.data[65..65][127..0] = data65x[127..0];
+	lpm_mux_component.data[64..64][127..0] = data64x[127..0];
+	lpm_mux_component.data[63..63][127..0] = data63x[127..0];
+	lpm_mux_component.data[62..62][127..0] = data62x[127..0];
+	lpm_mux_component.data[61..61][127..0] = data61x[127..0];
+	lpm_mux_component.data[60..60][127..0] = data60x[127..0];
+	lpm_mux_component.data[59..59][127..0] = data59x[127..0];
+	lpm_mux_component.data[58..58][127..0] = data58x[127..0];
+	lpm_mux_component.data[57..57][127..0] = data57x[127..0];
+	lpm_mux_component.data[56..56][127..0] = data56x[127..0];
+	lpm_mux_component.data[55..55][127..0] = data55x[127..0];
+	lpm_mux_component.data[54..54][127..0] = data54x[127..0];
+	lpm_mux_component.data[53..53][127..0] = data53x[127..0];
+	lpm_mux_component.data[52..52][127..0] = data52x[127..0];
+	lpm_mux_component.data[51..51][127..0] = data51x[127..0];
+	lpm_mux_component.data[50..50][127..0] = data50x[127..0];
+	lpm_mux_component.data[49..49][127..0] = data49x[127..0];
+	lpm_mux_component.data[48..48][127..0] = data48x[127..0];
+	lpm_mux_component.data[47..47][127..0] = data47x[127..0];
+	lpm_mux_component.data[46..46][127..0] = data46x[127..0];
+	lpm_mux_component.data[45..45][127..0] = data45x[127..0];
+	lpm_mux_component.data[44..44][127..0] = data44x[127..0];
+	lpm_mux_component.data[43..43][127..0] = data43x[127..0];
+	lpm_mux_component.data[42..42][127..0] = data42x[127..0];
+	lpm_mux_component.data[41..41][127..0] = data41x[127..0];
+	lpm_mux_component.data[40..40][127..0] = data40x[127..0];
+	lpm_mux_component.data[39..39][127..0] = data39x[127..0];
+	lpm_mux_component.data[38..38][127..0] = data38x[127..0];
+	lpm_mux_component.data[37..37][127..0] = data37x[127..0];
+	lpm_mux_component.data[36..36][127..0] = data36x[127..0];
+	lpm_mux_component.data[35..35][127..0] = data35x[127..0];
+	lpm_mux_component.data[34..34][127..0] = data34x[127..0];
+	lpm_mux_component.data[33..33][127..0] = data33x[127..0];
+	lpm_mux_component.data[32..32][127..0] = data32x[127..0];
+	lpm_mux_component.data[31..31][127..0] = data31x[127..0];
+	lpm_mux_component.data[30..30][127..0] = data30x[127..0];
+	lpm_mux_component.data[29..29][127..0] = data29x[127..0];
+	lpm_mux_component.data[28..28][127..0] = data28x[127..0];
+	lpm_mux_component.data[27..27][127..0] = data27x[127..0];
+	lpm_mux_component.data[26..26][127..0] = data26x[127..0];
+	lpm_mux_component.data[25..25][127..0] = data25x[127..0];
+	lpm_mux_component.data[24..24][127..0] = data24x[127..0];
+	lpm_mux_component.data[23..23][127..0] = data23x[127..0];
+	lpm_mux_component.data[22..22][127..0] = data22x[127..0];
+	lpm_mux_component.data[21..21][127..0] = data21x[127..0];
+	lpm_mux_component.data[20..20][127..0] = data20x[127..0];
+	lpm_mux_component.data[19..19][127..0] = data19x[127..0];
+	lpm_mux_component.data[18..18][127..0] = data18x[127..0];
+	lpm_mux_component.data[17..17][127..0] = data17x[127..0];
+	lpm_mux_component.data[16..16][127..0] = data16x[127..0];
+	lpm_mux_component.data[15..15][127..0] = data15x[127..0];
+	lpm_mux_component.data[14..14][127..0] = data14x[127..0];
+	lpm_mux_component.data[13..13][127..0] = data13x[127..0];
+	lpm_mux_component.data[12..12][127..0] = data12x[127..0];
+	lpm_mux_component.data[11..11][127..0] = data11x[127..0];
+	lpm_mux_component.data[10..10][127..0] = data10x[127..0];
+	lpm_mux_component.data[9..9][127..0] = data9x[127..0];
+	lpm_mux_component.data[8..8][127..0] = data8x[127..0];
+	lpm_mux_component.data[7..7][127..0] = data7x[127..0];
+	lpm_mux_component.data[6..6][127..0] = data6x[127..0];
+	lpm_mux_component.data[5..5][127..0] = data5x[127..0];
+	lpm_mux_component.data[4..4][127..0] = data4x[127..0];
+	lpm_mux_component.data[3..3][127..0] = data3x[127..0];
+	lpm_mux_component.data[2..2][127..0] = data2x[127..0];
+	lpm_mux_component.data[1..1][127..0] = data1x[127..0];
+	lpm_mux_component.data[0..0][127..0] = data0x[127..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "8"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data100x 0 0 128 0 INPUT NODEFVAL data100x[127..0]
+-- Retrieval info: USED_PORT: data101x 0 0 128 0 INPUT NODEFVAL data101x[127..0]
+-- Retrieval info: USED_PORT: data102x 0 0 128 0 INPUT NODEFVAL data102x[127..0]
+-- Retrieval info: USED_PORT: data103x 0 0 128 0 INPUT NODEFVAL data103x[127..0]
+-- Retrieval info: USED_PORT: data104x 0 0 128 0 INPUT NODEFVAL data104x[127..0]
+-- Retrieval info: USED_PORT: data105x 0 0 128 0 INPUT NODEFVAL data105x[127..0]
+-- Retrieval info: USED_PORT: data106x 0 0 128 0 INPUT NODEFVAL data106x[127..0]
+-- Retrieval info: USED_PORT: data107x 0 0 128 0 INPUT NODEFVAL data107x[127..0]
+-- Retrieval info: USED_PORT: data108x 0 0 128 0 INPUT NODEFVAL data108x[127..0]
+-- Retrieval info: USED_PORT: data109x 0 0 128 0 INPUT NODEFVAL data109x[127..0]
+-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
+-- Retrieval info: USED_PORT: data110x 0 0 128 0 INPUT NODEFVAL data110x[127..0]
+-- Retrieval info: USED_PORT: data111x 0 0 128 0 INPUT NODEFVAL data111x[127..0]
+-- Retrieval info: USED_PORT: data112x 0 0 128 0 INPUT NODEFVAL data112x[127..0]
+-- Retrieval info: USED_PORT: data113x 0 0 128 0 INPUT NODEFVAL data113x[127..0]
+-- Retrieval info: USED_PORT: data114x 0 0 128 0 INPUT NODEFVAL data114x[127..0]
+-- Retrieval info: USED_PORT: data115x 0 0 128 0 INPUT NODEFVAL data115x[127..0]
+-- Retrieval info: USED_PORT: data116x 0 0 128 0 INPUT NODEFVAL data116x[127..0]
+-- Retrieval info: USED_PORT: data117x 0 0 128 0 INPUT NODEFVAL data117x[127..0]
+-- Retrieval info: USED_PORT: data118x 0 0 128 0 INPUT NODEFVAL data118x[127..0]
+-- Retrieval info: USED_PORT: data119x 0 0 128 0 INPUT NODEFVAL data119x[127..0]
+-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
+-- Retrieval info: USED_PORT: data120x 0 0 128 0 INPUT NODEFVAL data120x[127..0]
+-- Retrieval info: USED_PORT: data121x 0 0 128 0 INPUT NODEFVAL data121x[127..0]
+-- Retrieval info: USED_PORT: data122x 0 0 128 0 INPUT NODEFVAL data122x[127..0]
+-- Retrieval info: USED_PORT: data123x 0 0 128 0 INPUT NODEFVAL data123x[127..0]
+-- Retrieval info: USED_PORT: data124x 0 0 128 0 INPUT NODEFVAL data124x[127..0]
+-- Retrieval info: USED_PORT: data125x 0 0 128 0 INPUT NODEFVAL data125x[127..0]
+-- Retrieval info: USED_PORT: data126x 0 0 128 0 INPUT NODEFVAL data126x[127..0]
+-- Retrieval info: USED_PORT: data127x 0 0 128 0 INPUT NODEFVAL data127x[127..0]
+-- Retrieval info: USED_PORT: data128x 0 0 128 0 INPUT NODEFVAL data128x[127..0]
+-- Retrieval info: USED_PORT: data129x 0 0 128 0 INPUT NODEFVAL data129x[127..0]
+-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
+-- Retrieval info: USED_PORT: data130x 0 0 128 0 INPUT NODEFVAL data130x[127..0]
+-- Retrieval info: USED_PORT: data131x 0 0 128 0 INPUT NODEFVAL data131x[127..0]
+-- Retrieval info: USED_PORT: data132x 0 0 128 0 INPUT NODEFVAL data132x[127..0]
+-- Retrieval info: USED_PORT: data133x 0 0 128 0 INPUT NODEFVAL data133x[127..0]
+-- Retrieval info: USED_PORT: data134x 0 0 128 0 INPUT NODEFVAL data134x[127..0]
+-- Retrieval info: USED_PORT: data135x 0 0 128 0 INPUT NODEFVAL data135x[127..0]
+-- Retrieval info: USED_PORT: data136x 0 0 128 0 INPUT NODEFVAL data136x[127..0]
+-- Retrieval info: USED_PORT: data137x 0 0 128 0 INPUT NODEFVAL data137x[127..0]
+-- Retrieval info: USED_PORT: data138x 0 0 128 0 INPUT NODEFVAL data138x[127..0]
+-- Retrieval info: USED_PORT: data139x 0 0 128 0 INPUT NODEFVAL data139x[127..0]
+-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
+-- Retrieval info: USED_PORT: data140x 0 0 128 0 INPUT NODEFVAL data140x[127..0]
+-- Retrieval info: USED_PORT: data141x 0 0 128 0 INPUT NODEFVAL data141x[127..0]
+-- Retrieval info: USED_PORT: data142x 0 0 128 0 INPUT NODEFVAL data142x[127..0]
+-- Retrieval info: USED_PORT: data143x 0 0 128 0 INPUT NODEFVAL data143x[127..0]
+-- Retrieval info: USED_PORT: data144x 0 0 128 0 INPUT NODEFVAL data144x[127..0]
+-- Retrieval info: USED_PORT: data145x 0 0 128 0 INPUT NODEFVAL data145x[127..0]
+-- Retrieval info: USED_PORT: data146x 0 0 128 0 INPUT NODEFVAL data146x[127..0]
+-- Retrieval info: USED_PORT: data147x 0 0 128 0 INPUT NODEFVAL data147x[127..0]
+-- Retrieval info: USED_PORT: data148x 0 0 128 0 INPUT NODEFVAL data148x[127..0]
+-- Retrieval info: USED_PORT: data149x 0 0 128 0 INPUT NODEFVAL data149x[127..0]
+-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
+-- Retrieval info: USED_PORT: data150x 0 0 128 0 INPUT NODEFVAL data150x[127..0]
+-- Retrieval info: USED_PORT: data151x 0 0 128 0 INPUT NODEFVAL data151x[127..0]
+-- Retrieval info: USED_PORT: data152x 0 0 128 0 INPUT NODEFVAL data152x[127..0]
+-- Retrieval info: USED_PORT: data153x 0 0 128 0 INPUT NODEFVAL data153x[127..0]
+-- Retrieval info: USED_PORT: data154x 0 0 128 0 INPUT NODEFVAL data154x[127..0]
+-- Retrieval info: USED_PORT: data155x 0 0 128 0 INPUT NODEFVAL data155x[127..0]
+-- Retrieval info: USED_PORT: data156x 0 0 128 0 INPUT NODEFVAL data156x[127..0]
+-- Retrieval info: USED_PORT: data157x 0 0 128 0 INPUT NODEFVAL data157x[127..0]
+-- Retrieval info: USED_PORT: data158x 0 0 128 0 INPUT NODEFVAL data158x[127..0]
+-- Retrieval info: USED_PORT: data159x 0 0 128 0 INPUT NODEFVAL data159x[127..0]
+-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
+-- Retrieval info: USED_PORT: data160x 0 0 128 0 INPUT NODEFVAL data160x[127..0]
+-- Retrieval info: USED_PORT: data161x 0 0 128 0 INPUT NODEFVAL data161x[127..0]
+-- Retrieval info: USED_PORT: data162x 0 0 128 0 INPUT NODEFVAL data162x[127..0]
+-- Retrieval info: USED_PORT: data163x 0 0 128 0 INPUT NODEFVAL data163x[127..0]
+-- Retrieval info: USED_PORT: data164x 0 0 128 0 INPUT NODEFVAL data164x[127..0]
+-- Retrieval info: USED_PORT: data165x 0 0 128 0 INPUT NODEFVAL data165x[127..0]
+-- Retrieval info: USED_PORT: data166x 0 0 128 0 INPUT NODEFVAL data166x[127..0]
+-- Retrieval info: USED_PORT: data167x 0 0 128 0 INPUT NODEFVAL data167x[127..0]
+-- Retrieval info: USED_PORT: data168x 0 0 128 0 INPUT NODEFVAL data168x[127..0]
+-- Retrieval info: USED_PORT: data169x 0 0 128 0 INPUT NODEFVAL data169x[127..0]
+-- Retrieval info: USED_PORT: data16x 0 0 128 0 INPUT NODEFVAL data16x[127..0]
+-- Retrieval info: USED_PORT: data170x 0 0 128 0 INPUT NODEFVAL data170x[127..0]
+-- Retrieval info: USED_PORT: data171x 0 0 128 0 INPUT NODEFVAL data171x[127..0]
+-- Retrieval info: USED_PORT: data172x 0 0 128 0 INPUT NODEFVAL data172x[127..0]
+-- Retrieval info: USED_PORT: data173x 0 0 128 0 INPUT NODEFVAL data173x[127..0]
+-- Retrieval info: USED_PORT: data174x 0 0 128 0 INPUT NODEFVAL data174x[127..0]
+-- Retrieval info: USED_PORT: data175x 0 0 128 0 INPUT NODEFVAL data175x[127..0]
+-- Retrieval info: USED_PORT: data176x 0 0 128 0 INPUT NODEFVAL data176x[127..0]
+-- Retrieval info: USED_PORT: data177x 0 0 128 0 INPUT NODEFVAL data177x[127..0]
+-- Retrieval info: USED_PORT: data178x 0 0 128 0 INPUT NODEFVAL data178x[127..0]
+-- Retrieval info: USED_PORT: data179x 0 0 128 0 INPUT NODEFVAL data179x[127..0]
+-- Retrieval info: USED_PORT: data17x 0 0 128 0 INPUT NODEFVAL data17x[127..0]
+-- Retrieval info: USED_PORT: data180x 0 0 128 0 INPUT NODEFVAL data180x[127..0]
+-- Retrieval info: USED_PORT: data181x 0 0 128 0 INPUT NODEFVAL data181x[127..0]
+-- Retrieval info: USED_PORT: data182x 0 0 128 0 INPUT NODEFVAL data182x[127..0]
+-- Retrieval info: USED_PORT: data183x 0 0 128 0 INPUT NODEFVAL data183x[127..0]
+-- Retrieval info: USED_PORT: data184x 0 0 128 0 INPUT NODEFVAL data184x[127..0]
+-- Retrieval info: USED_PORT: data185x 0 0 128 0 INPUT NODEFVAL data185x[127..0]
+-- Retrieval info: USED_PORT: data186x 0 0 128 0 INPUT NODEFVAL data186x[127..0]
+-- Retrieval info: USED_PORT: data187x 0 0 128 0 INPUT NODEFVAL data187x[127..0]
+-- Retrieval info: USED_PORT: data188x 0 0 128 0 INPUT NODEFVAL data188x[127..0]
+-- Retrieval info: USED_PORT: data189x 0 0 128 0 INPUT NODEFVAL data189x[127..0]
+-- Retrieval info: USED_PORT: data18x 0 0 128 0 INPUT NODEFVAL data18x[127..0]
+-- Retrieval info: USED_PORT: data190x 0 0 128 0 INPUT NODEFVAL data190x[127..0]
+-- Retrieval info: USED_PORT: data191x 0 0 128 0 INPUT NODEFVAL data191x[127..0]
+-- Retrieval info: USED_PORT: data192x 0 0 128 0 INPUT NODEFVAL data192x[127..0]
+-- Retrieval info: USED_PORT: data193x 0 0 128 0 INPUT NODEFVAL data193x[127..0]
+-- Retrieval info: USED_PORT: data194x 0 0 128 0 INPUT NODEFVAL data194x[127..0]
+-- Retrieval info: USED_PORT: data195x 0 0 128 0 INPUT NODEFVAL data195x[127..0]
+-- Retrieval info: USED_PORT: data196x 0 0 128 0 INPUT NODEFVAL data196x[127..0]
+-- Retrieval info: USED_PORT: data197x 0 0 128 0 INPUT NODEFVAL data197x[127..0]
+-- Retrieval info: USED_PORT: data198x 0 0 128 0 INPUT NODEFVAL data198x[127..0]
+-- Retrieval info: USED_PORT: data199x 0 0 128 0 INPUT NODEFVAL data199x[127..0]
+-- Retrieval info: USED_PORT: data19x 0 0 128 0 INPUT NODEFVAL data19x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: data200x 0 0 128 0 INPUT NODEFVAL data200x[127..0]
+-- Retrieval info: USED_PORT: data201x 0 0 128 0 INPUT NODEFVAL data201x[127..0]
+-- Retrieval info: USED_PORT: data202x 0 0 128 0 INPUT NODEFVAL data202x[127..0]
+-- Retrieval info: USED_PORT: data203x 0 0 128 0 INPUT NODEFVAL data203x[127..0]
+-- Retrieval info: USED_PORT: data204x 0 0 128 0 INPUT NODEFVAL data204x[127..0]
+-- Retrieval info: USED_PORT: data205x 0 0 128 0 INPUT NODEFVAL data205x[127..0]
+-- Retrieval info: USED_PORT: data206x 0 0 128 0 INPUT NODEFVAL data206x[127..0]
+-- Retrieval info: USED_PORT: data207x 0 0 128 0 INPUT NODEFVAL data207x[127..0]
+-- Retrieval info: USED_PORT: data208x 0 0 128 0 INPUT NODEFVAL data208x[127..0]
+-- Retrieval info: USED_PORT: data209x 0 0 128 0 INPUT NODEFVAL data209x[127..0]
+-- Retrieval info: USED_PORT: data20x 0 0 128 0 INPUT NODEFVAL data20x[127..0]
+-- Retrieval info: USED_PORT: data210x 0 0 128 0 INPUT NODEFVAL data210x[127..0]
+-- Retrieval info: USED_PORT: data211x 0 0 128 0 INPUT NODEFVAL data211x[127..0]
+-- Retrieval info: USED_PORT: data212x 0 0 128 0 INPUT NODEFVAL data212x[127..0]
+-- Retrieval info: USED_PORT: data213x 0 0 128 0 INPUT NODEFVAL data213x[127..0]
+-- Retrieval info: USED_PORT: data214x 0 0 128 0 INPUT NODEFVAL data214x[127..0]
+-- Retrieval info: USED_PORT: data215x 0 0 128 0 INPUT NODEFVAL data215x[127..0]
+-- Retrieval info: USED_PORT: data216x 0 0 128 0 INPUT NODEFVAL data216x[127..0]
+-- Retrieval info: USED_PORT: data217x 0 0 128 0 INPUT NODEFVAL data217x[127..0]
+-- Retrieval info: USED_PORT: data218x 0 0 128 0 INPUT NODEFVAL data218x[127..0]
+-- Retrieval info: USED_PORT: data219x 0 0 128 0 INPUT NODEFVAL data219x[127..0]
+-- Retrieval info: USED_PORT: data21x 0 0 128 0 INPUT NODEFVAL data21x[127..0]
+-- Retrieval info: USED_PORT: data220x 0 0 128 0 INPUT NODEFVAL data220x[127..0]
+-- Retrieval info: USED_PORT: data221x 0 0 128 0 INPUT NODEFVAL data221x[127..0]
+-- Retrieval info: USED_PORT: data222x 0 0 128 0 INPUT NODEFVAL data222x[127..0]
+-- Retrieval info: USED_PORT: data223x 0 0 128 0 INPUT NODEFVAL data223x[127..0]
+-- Retrieval info: USED_PORT: data224x 0 0 128 0 INPUT NODEFVAL data224x[127..0]
+-- Retrieval info: USED_PORT: data225x 0 0 128 0 INPUT NODEFVAL data225x[127..0]
+-- Retrieval info: USED_PORT: data226x 0 0 128 0 INPUT NODEFVAL data226x[127..0]
+-- Retrieval info: USED_PORT: data227x 0 0 128 0 INPUT NODEFVAL data227x[127..0]
+-- Retrieval info: USED_PORT: data228x 0 0 128 0 INPUT NODEFVAL data228x[127..0]
+-- Retrieval info: USED_PORT: data229x 0 0 128 0 INPUT NODEFVAL data229x[127..0]
+-- Retrieval info: USED_PORT: data22x 0 0 128 0 INPUT NODEFVAL data22x[127..0]
+-- Retrieval info: USED_PORT: data230x 0 0 128 0 INPUT NODEFVAL data230x[127..0]
+-- Retrieval info: USED_PORT: data231x 0 0 128 0 INPUT NODEFVAL data231x[127..0]
+-- Retrieval info: USED_PORT: data232x 0 0 128 0 INPUT NODEFVAL data232x[127..0]
+-- Retrieval info: USED_PORT: data233x 0 0 128 0 INPUT NODEFVAL data233x[127..0]
+-- Retrieval info: USED_PORT: data234x 0 0 128 0 INPUT NODEFVAL data234x[127..0]
+-- Retrieval info: USED_PORT: data235x 0 0 128 0 INPUT NODEFVAL data235x[127..0]
+-- Retrieval info: USED_PORT: data236x 0 0 128 0 INPUT NODEFVAL data236x[127..0]
+-- Retrieval info: USED_PORT: data237x 0 0 128 0 INPUT NODEFVAL data237x[127..0]
+-- Retrieval info: USED_PORT: data238x 0 0 128 0 INPUT NODEFVAL data238x[127..0]
+-- Retrieval info: USED_PORT: data239x 0 0 128 0 INPUT NODEFVAL data239x[127..0]
+-- Retrieval info: USED_PORT: data23x 0 0 128 0 INPUT NODEFVAL data23x[127..0]
+-- Retrieval info: USED_PORT: data240x 0 0 128 0 INPUT NODEFVAL data240x[127..0]
+-- Retrieval info: USED_PORT: data241x 0 0 128 0 INPUT NODEFVAL data241x[127..0]
+-- Retrieval info: USED_PORT: data242x 0 0 128 0 INPUT NODEFVAL data242x[127..0]
+-- Retrieval info: USED_PORT: data243x 0 0 128 0 INPUT NODEFVAL data243x[127..0]
+-- Retrieval info: USED_PORT: data244x 0 0 128 0 INPUT NODEFVAL data244x[127..0]
+-- Retrieval info: USED_PORT: data245x 0 0 128 0 INPUT NODEFVAL data245x[127..0]
+-- Retrieval info: USED_PORT: data246x 0 0 128 0 INPUT NODEFVAL data246x[127..0]
+-- Retrieval info: USED_PORT: data247x 0 0 128 0 INPUT NODEFVAL data247x[127..0]
+-- Retrieval info: USED_PORT: data248x 0 0 128 0 INPUT NODEFVAL data248x[127..0]
+-- Retrieval info: USED_PORT: data249x 0 0 128 0 INPUT NODEFVAL data249x[127..0]
+-- Retrieval info: USED_PORT: data24x 0 0 128 0 INPUT NODEFVAL data24x[127..0]
+-- Retrieval info: USED_PORT: data250x 0 0 128 0 INPUT NODEFVAL data250x[127..0]
+-- Retrieval info: USED_PORT: data251x 0 0 128 0 INPUT NODEFVAL data251x[127..0]
+-- Retrieval info: USED_PORT: data252x 0 0 128 0 INPUT NODEFVAL data252x[127..0]
+-- Retrieval info: USED_PORT: data253x 0 0 128 0 INPUT NODEFVAL data253x[127..0]
+-- Retrieval info: USED_PORT: data254x 0 0 128 0 INPUT NODEFVAL data254x[127..0]
+-- Retrieval info: USED_PORT: data255x 0 0 128 0 INPUT NODEFVAL data255x[127..0]
+-- Retrieval info: USED_PORT: data25x 0 0 128 0 INPUT NODEFVAL data25x[127..0]
+-- Retrieval info: USED_PORT: data26x 0 0 128 0 INPUT NODEFVAL data26x[127..0]
+-- Retrieval info: USED_PORT: data27x 0 0 128 0 INPUT NODEFVAL data27x[127..0]
+-- Retrieval info: USED_PORT: data28x 0 0 128 0 INPUT NODEFVAL data28x[127..0]
+-- Retrieval info: USED_PORT: data29x 0 0 128 0 INPUT NODEFVAL data29x[127..0]
+-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
+-- Retrieval info: USED_PORT: data30x 0 0 128 0 INPUT NODEFVAL data30x[127..0]
+-- Retrieval info: USED_PORT: data31x 0 0 128 0 INPUT NODEFVAL data31x[127..0]
+-- Retrieval info: USED_PORT: data32x 0 0 128 0 INPUT NODEFVAL data32x[127..0]
+-- Retrieval info: USED_PORT: data33x 0 0 128 0 INPUT NODEFVAL data33x[127..0]
+-- Retrieval info: USED_PORT: data34x 0 0 128 0 INPUT NODEFVAL data34x[127..0]
+-- Retrieval info: USED_PORT: data35x 0 0 128 0 INPUT NODEFVAL data35x[127..0]
+-- Retrieval info: USED_PORT: data36x 0 0 128 0 INPUT NODEFVAL data36x[127..0]
+-- Retrieval info: USED_PORT: data37x 0 0 128 0 INPUT NODEFVAL data37x[127..0]
+-- Retrieval info: USED_PORT: data38x 0 0 128 0 INPUT NODEFVAL data38x[127..0]
+-- Retrieval info: USED_PORT: data39x 0 0 128 0 INPUT NODEFVAL data39x[127..0]
+-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
+-- Retrieval info: USED_PORT: data40x 0 0 128 0 INPUT NODEFVAL data40x[127..0]
+-- Retrieval info: USED_PORT: data41x 0 0 128 0 INPUT NODEFVAL data41x[127..0]
+-- Retrieval info: USED_PORT: data42x 0 0 128 0 INPUT NODEFVAL data42x[127..0]
+-- Retrieval info: USED_PORT: data43x 0 0 128 0 INPUT NODEFVAL data43x[127..0]
+-- Retrieval info: USED_PORT: data44x 0 0 128 0 INPUT NODEFVAL data44x[127..0]
+-- Retrieval info: USED_PORT: data45x 0 0 128 0 INPUT NODEFVAL data45x[127..0]
+-- Retrieval info: USED_PORT: data46x 0 0 128 0 INPUT NODEFVAL data46x[127..0]
+-- Retrieval info: USED_PORT: data47x 0 0 128 0 INPUT NODEFVAL data47x[127..0]
+-- Retrieval info: USED_PORT: data48x 0 0 128 0 INPUT NODEFVAL data48x[127..0]
+-- Retrieval info: USED_PORT: data49x 0 0 128 0 INPUT NODEFVAL data49x[127..0]
+-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
+-- Retrieval info: USED_PORT: data50x 0 0 128 0 INPUT NODEFVAL data50x[127..0]
+-- Retrieval info: USED_PORT: data51x 0 0 128 0 INPUT NODEFVAL data51x[127..0]
+-- Retrieval info: USED_PORT: data52x 0 0 128 0 INPUT NODEFVAL data52x[127..0]
+-- Retrieval info: USED_PORT: data53x 0 0 128 0 INPUT NODEFVAL data53x[127..0]
+-- Retrieval info: USED_PORT: data54x 0 0 128 0 INPUT NODEFVAL data54x[127..0]
+-- Retrieval info: USED_PORT: data55x 0 0 128 0 INPUT NODEFVAL data55x[127..0]
+-- Retrieval info: USED_PORT: data56x 0 0 128 0 INPUT NODEFVAL data56x[127..0]
+-- Retrieval info: USED_PORT: data57x 0 0 128 0 INPUT NODEFVAL data57x[127..0]
+-- Retrieval info: USED_PORT: data58x 0 0 128 0 INPUT NODEFVAL data58x[127..0]
+-- Retrieval info: USED_PORT: data59x 0 0 128 0 INPUT NODEFVAL data59x[127..0]
+-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
+-- Retrieval info: USED_PORT: data60x 0 0 128 0 INPUT NODEFVAL data60x[127..0]
+-- Retrieval info: USED_PORT: data61x 0 0 128 0 INPUT NODEFVAL data61x[127..0]
+-- Retrieval info: USED_PORT: data62x 0 0 128 0 INPUT NODEFVAL data62x[127..0]
+-- Retrieval info: USED_PORT: data63x 0 0 128 0 INPUT NODEFVAL data63x[127..0]
+-- Retrieval info: USED_PORT: data64x 0 0 128 0 INPUT NODEFVAL data64x[127..0]
+-- Retrieval info: USED_PORT: data65x 0 0 128 0 INPUT NODEFVAL data65x[127..0]
+-- Retrieval info: USED_PORT: data66x 0 0 128 0 INPUT NODEFVAL data66x[127..0]
+-- Retrieval info: USED_PORT: data67x 0 0 128 0 INPUT NODEFVAL data67x[127..0]
+-- Retrieval info: USED_PORT: data68x 0 0 128 0 INPUT NODEFVAL data68x[127..0]
+-- Retrieval info: USED_PORT: data69x 0 0 128 0 INPUT NODEFVAL data69x[127..0]
+-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
+-- Retrieval info: USED_PORT: data70x 0 0 128 0 INPUT NODEFVAL data70x[127..0]
+-- Retrieval info: USED_PORT: data71x 0 0 128 0 INPUT NODEFVAL data71x[127..0]
+-- Retrieval info: USED_PORT: data72x 0 0 128 0 INPUT NODEFVAL data72x[127..0]
+-- Retrieval info: USED_PORT: data73x 0 0 128 0 INPUT NODEFVAL data73x[127..0]
+-- Retrieval info: USED_PORT: data74x 0 0 128 0 INPUT NODEFVAL data74x[127..0]
+-- Retrieval info: USED_PORT: data75x 0 0 128 0 INPUT NODEFVAL data75x[127..0]
+-- Retrieval info: USED_PORT: data76x 0 0 128 0 INPUT NODEFVAL data76x[127..0]
+-- Retrieval info: USED_PORT: data77x 0 0 128 0 INPUT NODEFVAL data77x[127..0]
+-- Retrieval info: USED_PORT: data78x 0 0 128 0 INPUT NODEFVAL data78x[127..0]
+-- Retrieval info: USED_PORT: data79x 0 0 128 0 INPUT NODEFVAL data79x[127..0]
+-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
+-- Retrieval info: USED_PORT: data80x 0 0 128 0 INPUT NODEFVAL data80x[127..0]
+-- Retrieval info: USED_PORT: data81x 0 0 128 0 INPUT NODEFVAL data81x[127..0]
+-- Retrieval info: USED_PORT: data82x 0 0 128 0 INPUT NODEFVAL data82x[127..0]
+-- Retrieval info: USED_PORT: data83x 0 0 128 0 INPUT NODEFVAL data83x[127..0]
+-- Retrieval info: USED_PORT: data84x 0 0 128 0 INPUT NODEFVAL data84x[127..0]
+-- Retrieval info: USED_PORT: data85x 0 0 128 0 INPUT NODEFVAL data85x[127..0]
+-- Retrieval info: USED_PORT: data86x 0 0 128 0 INPUT NODEFVAL data86x[127..0]
+-- Retrieval info: USED_PORT: data87x 0 0 128 0 INPUT NODEFVAL data87x[127..0]
+-- Retrieval info: USED_PORT: data88x 0 0 128 0 INPUT NODEFVAL data88x[127..0]
+-- Retrieval info: USED_PORT: data89x 0 0 128 0 INPUT NODEFVAL data89x[127..0]
+-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
+-- Retrieval info: USED_PORT: data90x 0 0 128 0 INPUT NODEFVAL data90x[127..0]
+-- Retrieval info: USED_PORT: data91x 0 0 128 0 INPUT NODEFVAL data91x[127..0]
+-- Retrieval info: USED_PORT: data92x 0 0 128 0 INPUT NODEFVAL data92x[127..0]
+-- Retrieval info: USED_PORT: data93x 0 0 128 0 INPUT NODEFVAL data93x[127..0]
+-- Retrieval info: USED_PORT: data94x 0 0 128 0 INPUT NODEFVAL data94x[127..0]
+-- Retrieval info: USED_PORT: data95x 0 0 128 0 INPUT NODEFVAL data95x[127..0]
+-- Retrieval info: USED_PORT: data96x 0 0 128 0 INPUT NODEFVAL data96x[127..0]
+-- Retrieval info: USED_PORT: data97x 0 0 128 0 INPUT NODEFVAL data97x[127..0]
+-- Retrieval info: USED_PORT: data98x 0 0 128 0 INPUT NODEFVAL data98x[127..0]
+-- Retrieval info: USED_PORT: data99x 0 0 128 0 INPUT NODEFVAL data99x[127..0]
+-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 8 0 INPUT NODEFVAL sel[7..0]
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 255 128 0 data255x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 254 128 0 data254x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 253 128 0 data253x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 252 128 0 data252x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 251 128 0 data251x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 250 128 0 data250x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 249 128 0 data249x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 248 128 0 data248x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 247 128 0 data247x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 246 128 0 data246x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 245 128 0 data245x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 244 128 0 data244x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 243 128 0 data243x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 242 128 0 data242x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 241 128 0 data241x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 240 128 0 data240x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 239 128 0 data239x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 238 128 0 data238x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 237 128 0 data237x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 236 128 0 data236x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 235 128 0 data235x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 234 128 0 data234x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 233 128 0 data233x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 232 128 0 data232x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 231 128 0 data231x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 230 128 0 data230x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 229 128 0 data229x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 228 128 0 data228x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 227 128 0 data227x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 226 128 0 data226x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 225 128 0 data225x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 224 128 0 data224x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 223 128 0 data223x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 222 128 0 data222x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 221 128 0 data221x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 220 128 0 data220x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 219 128 0 data219x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 218 128 0 data218x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 217 128 0 data217x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 216 128 0 data216x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 215 128 0 data215x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 214 128 0 data214x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 213 128 0 data213x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 212 128 0 data212x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 211 128 0 data211x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 210 128 0 data210x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 209 128 0 data209x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 208 128 0 data208x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 207 128 0 data207x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 206 128 0 data206x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 205 128 0 data205x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 204 128 0 data204x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 203 128 0 data203x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 202 128 0 data202x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 201 128 0 data201x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 200 128 0 data200x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 199 128 0 data199x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 198 128 0 data198x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 197 128 0 data197x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 196 128 0 data196x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 195 128 0 data195x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 194 128 0 data194x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 193 128 0 data193x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 192 128 0 data192x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 191 128 0 data191x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 190 128 0 data190x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 189 128 0 data189x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 188 128 0 data188x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 187 128 0 data187x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 186 128 0 data186x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 185 128 0 data185x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 184 128 0 data184x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 183 128 0 data183x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 182 128 0 data182x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 181 128 0 data181x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 180 128 0 data180x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 179 128 0 data179x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 178 128 0 data178x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 177 128 0 data177x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 176 128 0 data176x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 175 128 0 data175x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 174 128 0 data174x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 173 128 0 data173x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 172 128 0 data172x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 171 128 0 data171x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 170 128 0 data170x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 169 128 0 data169x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 168 128 0 data168x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 167 128 0 data167x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 166 128 0 data166x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 165 128 0 data165x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 164 128 0 data164x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 163 128 0 data163x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 162 128 0 data162x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 161 128 0 data161x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 160 128 0 data160x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 159 128 0 data159x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 158 128 0 data158x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 157 128 0 data157x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 156 128 0 data156x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 155 128 0 data155x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 154 128 0 data154x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 153 128 0 data153x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 152 128 0 data152x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 151 128 0 data151x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 150 128 0 data150x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 149 128 0 data149x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 148 128 0 data148x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 147 128 0 data147x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 146 128 0 data146x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 145 128 0 data145x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 144 128 0 data144x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 143 128 0 data143x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 142 128 0 data142x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 141 128 0 data141x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 140 128 0 data140x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 139 128 0 data139x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 138 128 0 data138x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 137 128 0 data137x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 136 128 0 data136x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 135 128 0 data135x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 134 128 0 data134x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 133 128 0 data133x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 132 128 0 data132x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 131 128 0 data131x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 130 128 0 data130x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 129 128 0 data129x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 128 128 0 data128x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 127 128 0 data127x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 126 128 0 data126x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 125 128 0 data125x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 124 128 0 data124x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 123 128 0 data123x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 122 128 0 data122x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 121 128 0 data121x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 120 128 0 data120x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 119 128 0 data119x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 118 128 0 data118x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 117 128 0 data117x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 116 128 0 data116x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 115 128 0 data115x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 114 128 0 data114x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 113 128 0 data113x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 112 128 0 data112x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 111 128 0 data111x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 110 128 0 data110x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 109 128 0 data109x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 108 128 0 data108x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 107 128 0 data107x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 106 128 0 data106x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 105 128 0 data105x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 104 128 0 data104x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 103 128 0 data103x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 102 128 0 data102x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 101 128 0 data101x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 100 128 0 data100x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 99 128 0 data99x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 98 128 0 data98x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 97 128 0 data97x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 96 128 0 data96x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 95 128 0 data95x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 94 128 0 data94x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 93 128 0 data93x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 92 128 0 data92x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 91 128 0 data91x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 90 128 0 data90x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 89 128 0 data89x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 88 128 0 data88x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 87 128 0 data87x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 86 128 0 data86x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 85 128 0 data85x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 84 128 0 data84x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 83 128 0 data83x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 82 128 0 data82x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 81 128 0 data81x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 80 128 0 data80x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 79 128 0 data79x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 78 128 0 data78x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 77 128 0 data77x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 76 128 0 data76x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 75 128 0 data75x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 74 128 0 data74x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 73 128 0 data73x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 72 128 0 data72x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 71 128 0 data71x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 70 128 0 data70x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 69 128 0 data69x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 68 128 0 data68x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 67 128 0 data67x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 66 128 0 data66x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 65 128 0 data65x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 64 128 0 data64x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 63 128 0 data63x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 62 128 0 data62x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 61 128 0 data61x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 60 128 0 data60x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 59 128 0 data59x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 58 128 0 data58x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 57 128 0 data57x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 56 128 0 data56x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 55 128 0 data55x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 54 128 0 data54x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 53 128 0 data53x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 52 128 0 data52x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 51 128 0 data51x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 50 128 0 data50x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 49 128 0 data49x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 48 128 0 data48x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 47 128 0 data47x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 46 128 0 data46x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 45 128 0 data45x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 44 128 0 data44x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 43 128 0 data43x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 42 128 0 data42x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 41 128 0 data41x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 40 128 0 data40x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 39 128 0 data39x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 38 128 0 data38x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 37 128 0 data37x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 36 128 0 data36x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 35 128 0 data35x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 34 128 0 data34x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 33 128 0 data33x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 32 128 0 data32x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 31 128 0 data31x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 30 128 0 data30x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 29 128 0 data29x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 28 128 0 data28x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 27 128 0 data27x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 26 128 0 data26x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 25 128 0 data25x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 24 128 0 data24x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 23 128 0 data23x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 22 128 0 data22x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 21 128 0 data21x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 20 128 0 data20x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 19 128 0 data19x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 18 128 0 data18x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 17 128 0 data17x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 16 128 0 data16x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 8 0 sel 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/serv_req_info.txt b/FPGA_by_Fredi/serv_req_info.txt
deleted file mode 100644
index 51a4176..0000000
--- a/FPGA_by_Fredi/serv_req_info.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>VDB</sub_system>
-	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
-	<line>4101</line>
-	<callstack>
-	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
-	</callstack>
-	<error>loc &lt; m_value-&gt;size()</error>
-	<date>Tue Oct 13 17:01:46 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>loc &lt; m_value-&gt;size()
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>VDB</sub_system>
-	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
-	<line>4101</line>
-	<callstack>
-	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
-	</callstack>
-	<error>loc &lt; m_value-&gt;size()</error>
-	<date>Tue Oct 13 17:11:00 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>loc &lt; m_value-&gt;size()
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: GED</error>
-	<date>Wed Oct 14 23:17:06 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: GED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: SFW, STED</error>
-	<date>Thu Oct 15 19:23:19 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: SFW, STED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<callstack>
-	0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
-	</callstack>
-	<error>Current editor: RPW, SFW
-Current dockable window: PJN</error>
-	<date>Fri Oct 16 00:14:03 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 0X1002D196
-Current editor: RPW, SFW
-Current dockable window: PJN
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: SFW</error>
-	<date>Sat Oct 17 19:01:54 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: SFW
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>AFC</sub_system>
-	<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
-	<line>1940</line>
-	<callstack>
-	0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
-	</callstack>
-	<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
-	<date>Mon Oct 19 21:58:36 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: RPW, GED</error>
-	<date>Tue Oct 20 00:53:11 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: RPW, GED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt
deleted file mode 100644
index 0a0000b..0000000
--- a/FPGA_by_Fredi/undo_redo.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-GED
-
-	Undo Commands
-	     1.	Properties
-	     2.	Move
-	     3.	Delete
-	     4.	Delete
-	     5.	Insert Node
-	     6.	Insert Symbol
-	     7.	Delete
-	     8.	Move
-	     9.	Move
-	    10.	Paste
-	    11.	Delete
-	    12.	Insert Symbol
-	    13.	Move
-	    14.	Paste
-	    15.	Delete
-	    16.	Delete
-
-
-RPW
-
-	Undo Commands
-	     1.	||Compilation Report||Flow Summary
-
-

From 343ede8328daa2dc44f9cb8b7b14af6905c7d27f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20G=C3=A1lvez?= <dgalvez75@gmail.com>
Date: Mon, 9 Apr 2018 17:23:44 +0200
Subject: [PATCH 04/16] Sync with Fredi's source tree 18/04/2017

Blitter work.
---
 FPGA_by_Fredi/FPGA_DATE.bsf                   |   2 +-
 FPGA_by_Fredi/FPGA_DATE.tdf                   |  10 +-
 FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf  |  30 +
 .../wf68901ip_interrupts.vhd.bak              | 391 --------
 .../WF_SDC_IF/sd-card-interface_soc.vhd.bak   | 239 -----
 .../wf6850ip_ctrl_status.vhd.bak              | 214 -----
 .../wf6850ip_receive - Kopie.vhd              | 419 ---------
 .../WF_UART6850_IP/wf6850ip_receive.vhd.bak   | 425 ---------
 .../WF_UART6850_IP/wf6850ip_top_soc.vhd.bak   | 252 -----
 .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak  | 338 -------
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak    | 202 +++++
 .../interrupt_handler.tdf.bak                 | 391 ++++++++
 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt            |  20 +
 FPGA_by_Fredi/UNUSED                          |  27 +
 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak           | 659 ++++++++++++++
 FPGA_by_Fredi/Video/UNUSED                    | 267 ++++++
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       | 675 ++++++++++++++
 FPGA_by_Fredi/Video/altdpram0_wave0.jpg       | Bin 0 -> 125146 bytes
 FPGA_by_Fredi/Video/altdpram0_wave1.jpg       | Bin 0 -> 171723 bytes
 FPGA_by_Fredi/Video/altdpram0_waveforms.html  |  16 +
 FPGA_by_Fredi/Video/altdpram1_wave0.jpg       | Bin 0 -> 151954 bytes
 FPGA_by_Fredi/Video/altdpram1_wave1.jpg       | Bin 0 -> 203609 bytes
 FPGA_by_Fredi/Video/altdpram1_waveforms.html  |  16 +
 FPGA_by_Fredi/Video/altdpram2_wave0.jpg       | Bin 0 -> 152433 bytes
 FPGA_by_Fredi/Video/altdpram2_wave1.jpg       | Bin 0 -> 204342 bytes
 FPGA_by_Fredi/Video/altdpram2_waveforms.html  |  16 +
 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg    | Bin 0 -> 30655 bytes
 .../Video/lpm_compare1_waveforms.html         |  13 +
 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg      | Bin 0 -> 84085 bytes
 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html |  13 +
 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg    | Bin 0 -> 114506 bytes
 .../Video/lpm_fifo_dc0_waveforms.html         |  13 +
 FPGA_by_Fredi/altpll0_waveforms.html          |  10 -
 FPGA_by_Fredi/altpll1_waveforms.html          |  10 -
 FPGA_by_Fredi/altpll2_waveforms.html          |  10 -
 FPGA_by_Fredi/altpll3_waveforms.html          |  10 -
 FPGA_by_Fredi/blitter.tdf                     | 140 +--
 FPGA_by_Fredi/blitter.tdf.bak                 | 144 +--
 FPGA_by_Fredi/firebee1.asm.rpt                | 128 ---
 FPGA_by_Fredi/firebee1.bdf                    |   2 +-
 FPGA_by_Fredi/firebee1.done                   |   2 +-
 FPGA_by_Fredi/firebee1.fit.summary            |  16 -
 FPGA_by_Fredi/firebee1.flow.rpt               | 428 ---------
 FPGA_by_Fredi/firebee1.map.summary            |  14 -
 FPGA_by_Fredi/firebee1.rbf                    | Bin 0 -> 531802 bytes
 FPGA_by_Fredi/firebee1.sim.rpt                | 247 -----
 FPGA_by_Fredi/firebee1.sta.summary            | 857 ------------------
 FPGA_by_Fredi/firebee1.tan.summary            | 256 ------
 FPGA_by_Fredi/firebeei1.qws                   |  10 +-
 FPGA_by_Fredi/lpm_counter1_wave0.jpg          | Bin 57012 -> 0 bytes
 FPGA_by_Fredi/lpm_counter1_waveforms.html     |  13 -
 FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html     |  16 -
 FPGA_by_Fredi/serv_req_info.txt               | 115 +++
 FPGA_by_Fredi/sopc_builder_log.txt            |   0
 FPGA_by_Fredi/undo_redo.txt                   |  12 +
 55 files changed, 2659 insertions(+), 4429 deletions(-)
 create mode 100644 FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
 create mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
 create mode 100644 FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
 create mode 100644 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
 create mode 100644 FPGA_by_Fredi/UNUSED
 create mode 100644 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
 create mode 100644 FPGA_by_Fredi/Video/UNUSED
 create mode 100644 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
 create mode 100644 FPGA_by_Fredi/Video/altdpram0_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram0_wave1.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram0_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/altdpram1_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram1_wave1.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram1_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/altdpram2_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram2_wave1.jpg
 create mode 100644 FPGA_by_Fredi/Video/altdpram2_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
 create mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/altpll0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/altpll1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/altpll2_waveforms.html
 delete mode 100644 FPGA_by_Fredi/altpll3_waveforms.html
 delete mode 100644 FPGA_by_Fredi/firebee1.asm.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.fit.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.flow.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.map.summary
 create mode 100644 FPGA_by_Fredi/firebee1.rbf
 delete mode 100644 FPGA_by_Fredi/firebee1.sim.rpt
 delete mode 100644 FPGA_by_Fredi/firebee1.sta.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.tan.summary
 delete mode 100644 FPGA_by_Fredi/lpm_counter1_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/lpm_counter1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
 create mode 100644 FPGA_by_Fredi/serv_req_info.txt
 create mode 100644 FPGA_by_Fredi/sopc_builder_log.txt
 create mode 100644 FPGA_by_Fredi/undo_redo.txt

diff --git a/FPGA_by_Fredi/FPGA_DATE.bsf b/FPGA_by_Fredi/FPGA_DATE.bsf
index fd5ac89..a6c809a 100644
--- a/FPGA_by_Fredi/FPGA_DATE.bsf
+++ b/FPGA_by_Fredi/FPGA_DATE.bsf
@@ -31,7 +31,7 @@ applicable agreement for further details.
 		(line (pt 88 24)(pt 72 24)(line_width 3))
 	)
 	(drawing
-		(text "319037463" (rect 27 18 72 30)(font "Arial" ))
+		(text "402923543" (rect 27 18 72 30)(font "Arial" ))
 		(text "32" (rect 77 25 87 37)(font "Arial" ))
 		(line (pt 16 16)(pt 72 16)(line_width 1))
 		(line (pt 72 16)(pt 72 32)(line_width 1))
diff --git a/FPGA_by_Fredi/FPGA_DATE.tdf b/FPGA_by_Fredi/FPGA_DATE.tdf
index 6769853..49f319c 100644
--- a/FPGA_by_Fredi/FPGA_DATE.tdf
+++ b/FPGA_by_Fredi/FPGA_DATE.tdf
@@ -33,7 +33,7 @@
 --applicable agreement for further details.
 
 -- Clearbox generated function header
-FUNCTION FPGA_DATE_lpm_constant_d19 ()
+FUNCTION FPGA_DATE_lpm_constant_i19 ()
 RETURNS ( result[31..0]);
 
 
@@ -46,11 +46,11 @@ SUBDESIGN FPGA_DATE
 
 VARIABLE
 
-	FPGA_DATE_lpm_constant_d19_component : FPGA_DATE_lpm_constant_d19;
+	FPGA_DATE_lpm_constant_i19_component : FPGA_DATE_lpm_constant_i19;
 
 BEGIN
 
-	result[31..0] = FPGA_DATE_lpm_constant_d19_component.result[31..0];
+	result[31..0] = FPGA_DATE_lpm_constant_i19_component.result[31..0];
 END;
 
 
@@ -63,9 +63,9 @@ END;
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: Radix NUMERIC "16"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "319037463"
+-- Retrieval info: PRIVATE: Value NUMERIC "402923543"
 -- Retrieval info: PRIVATE: nBit NUMERIC "32"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "319037463"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "402923543"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf
new file mode 100644
index 0000000..4ae1da6
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf
@@ -0,0 +1,30 @@
+--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=18042017 LPM_WIDTH=32 result
+--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN FPGA_DATE_lpm_constant_i19
+( 
+	result[31..0]	:	output;
+) 
+
+BEGIN 
+	result[] = B"00011000000001000010000000010111";
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
deleted file mode 100644
index 915c271..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak
+++ /dev/null
@@ -1,391 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- ATARI MFP compatible IP Core					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- MC68901 compatible multi function port core.                 ----
-----                                                              ----
----- This is the SUSKA MFP IP core interrupt logic file.          ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
--- Revision 2K8A  2008/06/03 WF
---   Fixed Pending register logic.
--- Revision 2K9A  2009/06/20 WF
---   Fixed interrupt polarity for TA_I and TB_I.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF68901IP_INTERRUPTS is
-	port (  -- System control:
-			CLK			: in bit;
-			RESETn		: in bit;
-			
-			-- Asynchronous bus control:
-			DSn			: in bit;
-			CSn			: in bit;
-			RWn			: in bit;
-			
-			-- Data and Adresses:
-			RS			: in bit_vector(5 downto 1);
-			DATA_IN		: in bit_vector(7 downto 0);
-			DATA_OUT	: out bit_vector(7 downto 0);
-			DATA_OUT_EN	: out bit;
-
-			-- Interrupt control:
-			IACKn		: in bit;
-			IEIn		: in bit;
-			IEOn		: out bit;
-			IRQn		: out bit;
-			
-			-- Interrupt sources:
-			GP_INT		: in bit_vector(7 downto 0);
-
-			AER_4		: in bit;
-			AER_3		: in bit;
-			TAI			: in bit;
-			TBI			: in bit;
-			TA_PWM		: in bit;
-			TB_PWM		: in bit;
-			TIMER_A_INT	: in bit;
-			TIMER_B_INT	: in bit;
-			TIMER_C_INT	: in bit;
-			TIMER_D_INT	: in bit;
-
-			RCV_ERR		: in bit;
-			TRM_ERR		: in bit;
-			RCV_BUF_F	: in bit;
-			TRM_BUF_E	: in bit
-	);
-end entity WF68901IP_INTERRUPTS;
-
-architecture BEHAVIOR of WF68901IP_INTERRUPTS is
--- Interrupt state machine:
-type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
-signal INT_STATE : INT_STATES;
--- The registers:
-signal IERA			: bit_vector(7 downto 0);
-signal IERB			: bit_vector(7 downto 0);
-signal IPRA			: bit_vector(7 downto 0);
-signal IPRB			: bit_vector(7 downto 0);
-signal ISRA			: bit_vector(7 downto 0);
-signal ISRB			: bit_vector(7 downto 0);
-signal IMRA			: bit_vector(7 downto 0);
-signal IMRB			: bit_vector(7 downto 0);
-signal VR			: bit_vector(7 downto 3);
--- Interconnect:
-signal VECT_NUMBER	: bit_vector(7 downto 0);
-signal INT_SRC		: bit_vector(15 downto 0);
-signal INT_SRC_EDGE	: bit_vector(15 downto 0);
-signal INT_ENA		: bit_vector(15 downto 0);
-signal INT_MASK		: bit_vector(15 downto 0);
-signal INT_PENDING	: bit_vector(15 downto 0);
-signal INT_SERVICE	: bit_vector(15 downto 0);
-signal INT_PASS		: bit_vector(15 downto 0);
-signal INT_OUT		: bit_vector(15 downto 0);
-signal GP_INT_4		: bit;
-signal GP_INT_3		: bit;
-begin
-	-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
-	-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
-	-- to timer A and timer B.
-	-- The xor logic provides polarity control for the interrupt transition. Be aware,
-	-- that the PWM signals cause an interrupt on the opposite transition like the
-	-- respective GPIP port pins (with the same AER settings).
-    --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4;
-    --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3;
-    GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct.
-    GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3;
-
-
-	-- Interrupt source priority sorted (15 = highest):
-    INT_SRC <= 	GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & 
-    GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0);
-
-	INT_ENA 	<= IERA & IERB;
-	INT_MASK 	<= IMRA & IMRB;
-	INT_PENDING <= IPRA & IPRB;
-	INT_SERVICE <= ISRA & ISRB;
-	INT_OUT 	<= INT_PENDING and INT_MASK; -- Masking:
-
-	-- Enable the daisy chain, if there is no pending interrupt and
-	-- the interrupt state machine is not in service.
-	IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
-
-	-- Interrupt request:
-	IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
-
-	EDGE_ENA: process(RESETn, CLK)
-	-- These are the 16 edge detectors of the 16 interrupt input sources. This
-	-- process also provides the disabling or enabling via the IERA and IERB registers.
-	variable LOCK : bit_vector(15 downto 0);
-	begin
-		if RESETn = '0' then
-			INT_SRC_EDGE <= x"0000";
-			LOCK := x"0000";
-		elsif CLK = '0' and CLK' event then
-			for i in 15 downto 0 loop
-				if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then
-					LOCK(i) := '1';
-					INT_SRC_EDGE(i) <= '1';
-				elsif INT_SRC(i) = '0' then
-					LOCK(i) := '0';
-					INT_SRC_EDGE(i) <= '0';
-				else
-					INT_SRC_EDGE(i) <= '0';
-				end if;
-			end loop;
-		end if;
-	end process EDGE_ENA;
-	
-	INT_REGISTERS: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			IERA <= (others => '0');
-			IERB <= (others => '0');
-			IPRA <= (others => '0');
-			IPRB <= (others => '0');
-			ISRA <= (others => '0');
-			ISRB <= (others => '0');
-			IMRA <= (others => '0');
-			IMRB <= (others => '0');
-		elsif CLK = '1' and CLK' event then
-			if 	CSn = '0' and DSn = '0' and RWn = '0' then
-				case RS is
-					when "00011"	=> IERA <= DATA_IN; -- Enable A.
-					when "00100"	=> IERB <= DATA_IN; -- Enable B.
-					when "00101"	=>
-						-- Only a '0' can be written to the pending register.
-						for i in 7 downto 0 loop
-							if DATA_IN(i) = '0' then
-								IPRA(i) <= '0'; -- Pending A.
-							end if;
-						end loop;
-					when "00110"	=>
-						-- Only a '0' can be written to the pending register.
-						for i in 7 downto 0 loop
-							if DATA_IN(i) = '0' then
-								IPRB(i) <= '0'; -- Pending B.
-							end if;
-						end loop;
-					when "00111"	=> 
-						-- Only a '0' can be written to the in service register.
-						for i in 7 downto 0 loop
-							if DATA_IN(i) = '0' then
-								ISRA(i) <= '0'; -- In Service A.
-							end if;
-						end loop;
-					when "01000"	=>
-						-- Only a '0' can be written to the in service register.
-						for i in 7 downto 0 loop
-							if DATA_IN(i) = '0' then
-								ISRB(i) <= '0'; -- In Service B.
-							end if;
-						end loop;
-					when "01001"	=> IMRA <= DATA_IN; -- Mask A.
-					when "01010"	=> IMRB <= DATA_IN; -- Mask B.
-					when "01011"	=> VR <= DATA_IN(7 downto 3); -- Vector register.
-					when others		=> null;
-				end case;
-			end if;
-
-			-- Pending register:
-			-- set and clear bit logic.
-			for i in 15 downto 8 loop
-				if INT_SRC_EDGE(i) = '1' then
-					IPRA(i-8) <= '1';
-				elsif INT_ENA(i) = '0' then
-					IPRA(i-8) <= '0'; -- Clear by disabling the channel.
-				elsif INT_PASS(i) = '1' then
-					IPRA(i-8) <= '0'; -- Clear by passing the interrupt.
-				end if;
-			end loop;
-			for i in 7 downto 0 loop
-				if INT_SRC_EDGE(i) = '1' then
-					IPRB(i) <= '1';
-				elsif INT_ENA(i) = '0' then
-					IPRB(i) <= '0'; -- Clear by disabling the channel.
-				elsif INT_PASS(i) = '1' then
-					IPRB(i) <= '0'; -- Clear by passing the interrupt.
-				end if;
-			end loop;
-
-			-- In-Service register:
-			-- Set bit logic, VR(3) is the service register enable.
-			for i in 15 downto 8 loop
-				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
-					ISRA(i-8) <= '1';
-				end if;
-			end loop;
-			for i in 7 downto 0 loop
-				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
-					ISRB(i) <= '1';
-				end if;
-			end loop;
-		end if;
-	end process INT_REGISTERS;
-	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else 																	 '1' when INT_STATE = VECTOR_OUT else '0';
-
-	DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else
-				IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else
-				IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else
-				IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else
-				ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else
-				ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else
-				IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else
-				IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else
-				VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else
-				VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00";
-
-	P_INT_STATE	: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			INT_STATE <= SCAN;
-		elsif CLK = '1' and CLK' event then
-			case INT_STATE is
-				when SCAN =>
-					INT_PASS <= x"0000";
-					-- Automatic End of Interrupt mode. Service register disabled.
-					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
-					-- vector number (VR(7 downto 4) = x"0").
-					if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then
-						INT_STATE <= REQUEST; -- Non masked interrupt is pending.
-					-- The following 16 are the Software end of interrupt mode. Service register enabled.
-					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
-					-- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized.
-					elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then
-						if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then
-							INT_STATE <= REQUEST;
-						elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then
-							INT_STATE <= REQUEST;
-						else
-							INT_STATE <= SCAN; -- Wait for interrupt.
-						end if;
-					else
-						INT_STATE <= SCAN;
-					end if;
-				when REQUEST =>
-					if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode.
-						INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending.
-						if INT_OUT(15) = '1' then 
-							INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7.
-						elsif INT_OUT(14) = '1' then 
-							INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6.
-						elsif INT_OUT(13) = '1' then 
-							INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A.
-						elsif INT_OUT(12) = '1' then 
-							INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full.
-						elsif INT_OUT(11) = '1' then 
-							INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error.
-						elsif INT_OUT(10) = '1' then 
-							INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty.
-						elsif INT_OUT(9) = '1' then 
-							INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error.
-						elsif INT_OUT(8) = '1' then 
-							INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B.
-						elsif INT_OUT(7) = '1' then 
-							INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5.
-						elsif INT_OUT(6) = '1' then 
-							INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4.
-						elsif INT_OUT(5) = '1' then 
-							INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C.
-						elsif INT_OUT(4) = '1' then 
-							INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D.
-						elsif INT_OUT(3) = '1' then 
-							INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3.
-						elsif INT_OUT(2) = '1' then 
-							INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2.
-						elsif INT_OUT(1) = '1' then 
-							INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1.
-						elsif INT_OUT(0) = '1' then 
-							INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0.
-						end if;
-					 -- Polled interrupt mode: End of interrupt by writing to the pending registers.
-					elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then
-						INT_STATE <= SCAN;
-					else
-						INT_STATE <= REQUEST; -- Wait.
-					end if;
-				when VECTOR_OUT =>
-					INT_PASS <= x"0000";
-					if DSn = '1' or IACKn = '1' then
-						INT_STATE <= SCAN; -- Finished.
-					else
-						INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector.
-					end if;
-			end case;
-		end if;
-	end process P_INT_STATE;
-end architecture BEHAVIOR;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
deleted file mode 100644
index 0200dea..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
+++ /dev/null
@@ -1,239 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- ATARI IP Core peripheral Add-On				              ----
-----                                                              ----
----- This file is part of the FPGA-ATARI project.                 ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- This hardware provides an interface to connect to a SD-Card. ----
-----                                                              ----
----- This interface is based on the project 'SatanDisk' of        ----
----- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
----- the original code, written in VERILOG. It is provided for    ----
----- the use in a system on programmable chips (SOPC).            ----
-----                                                              ----
----- Timing: Use a clock frequency of 16MHz for this component.   ----
-----         Use the same clock frequency for the connected AVR   ----
-----         microcontroller.                                     ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2007 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
----- This hardware works with the original ATARI                  ----
----- hard dik driver.                                             ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K7A  2007/01/05 WF
---   Initial Release.
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
---
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF_SD_CARD is
-	port (
-		-- System:
-		RESETn			: in bit;
-		CLK				: in bit; -- 16MHz, see above.
-
-		-- ACSI section:		
-		ACSI_A1			: in bit;
-		ACSI_CSn		: in bit;
-		ACSI_ACKn		: in bit;
-		ACSI_INTn		: out bit;
-		ACSI_DRQn		: out bit;
-		ACSI_D_IN		: in std_logic_vector(7 downto 0);
-		ACSI_D_OUT		: out std_logic_vector(7 downto 0);
-		ACSI_D_EN		: out bit;
-
-		-- Microcontroller interface:
-		MC_DO			: in bit;
-		MC_PIO_DMAn		: in bit;
-		MC_RWn			: in bit;
-		MC_CLR_CMD		: in bit;
-		MC_DONE			: out bit;
-		MC_GOT_CMD		: out bit;
-		MC_D_IN			: in std_logic_vector(7 downto 0);
-		MC_D_OUT		: out std_logic_vector(7 downto 0);
-		MC_D_EN			: out bit
-      );
-end WF_SD_CARD;
-
-architecture BEHAVIOR of WF_SD_CARD is
-signal DATA_REG		: std_logic_vector(7 downto 0);
-signal D0_REG		: bit;
-signal INT_REG		: bit;
-signal DRQ_REG		: bit;
-signal DONE_REG		: bit;
-signal GOT_CMD_REG	: bit;
-signal HOLD			: bit;
-signal PREV_CSn		: bit;
-signal PREV_ACKn	: bit;
-begin
-	MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0');
-	MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0';
-	ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0');
--- ???:
---ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0';
-ACSI_D_EN <= '0';
-	ACSI_INTn <= INT_REG;
-	ACSI_DRQn <= DRQ_REG;
-	MC_DONE <= DONE_REG;
-	MC_GOT_CMD <= GOT_CMD_REG;
-
-	P_DATA: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			DATA_REG <= (others => '0');
-		elsif CLK = '1' and CLK' event then
-			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
-				DATA_REG <= MC_D_IN;  -- Read from AVR to ACSI.
-			end if;
-			--			
-			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
-				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
-			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
-				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
-			end if;
-		end if;
-	end process P_DATA;
-	
-	P_SYNC: process
-	begin
-		wait until CLK = '1' and CLK' event;
-		PREV_CSn <= ACSI_CSn;
-		PREV_ACKn <= ACSI_ACKn;
-	end process P_SYNC;
-
-	P_INT_DRQ: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			INT_REG <= '1'; -- No interrupt.
-			DRQ_REG <= '1'; -- No data request.
-		elsif CLK = '1' and CLK' event then
-			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
-				INT_REG <= '0'; -- Release an interrupt.
-				DRQ_REG <= '1';
-			elsif D0_REG = '0' and MC_DO = '1' then
-				INT_REG <= '1';
-				DRQ_REG <= '0'; -- Release a data request.
-			end if;
-			--
-			if MC_CLR_CMD = '1' then -- Clear done.
-				INT_REG <= '1'; -- Restore INT_REG.
-				DRQ_REG <= '1'; -- Restore DRQ_REG.
-			end if;
-			--
-			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
-				if ACSI_CSn = '0' then
-					INT_REG <= '1';
-				end if;
-				--
-				if ACSI_ACKn = '0' then
-					DRQ_REG <= '1';
-				end if;
-			end if;
-		end if;
-	end process P_INT_DRQ;
-				
-	P_HOLD: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			HOLD <= '0';
-		elsif CLK = '1' and CLK' event then
-			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
-				HOLD <= '1';
-			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
-				HOLD <= '0';
-			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
-				HOLD <= '0';
-			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
-				HOLD <= '1';
-			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
-				HOLD <= '1';
-			elsif MC_CLR_CMD = '1' then -- Clear done.
-				HOLD <= '0';
-			end if;
-		end if;
-	end process P_HOLD;
-
-	P_DONE: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			DONE_REG <= '0';
-		elsif CLK = '1' and CLK' event then
-			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
-				DONE_REG <= '1';
-			elsif MC_CLR_CMD = '1' then -- Clear done.
-				DONE_REG <= '0';
-			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
-				DONE_REG <= '0';
-			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
-				DONE_REG <= '0';
-			end if;
-		end if;
-	end process P_DONE;
-
-	P_DO_REG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			D0_REG <= '0';
-		elsif CLK = '1' and CLK' event then
-			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
-				D0_REG <= MC_DO;
-			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
-				D0_REG <= MC_DO;
-			end if;
-		end if;
-	end process P_DO_REG;
-
-	P_GOT_CMD: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			GOT_CMD_REG <= '0';
-		elsif CLK = '1' and CLK' event then
--- ?? ACSI_CSn doppelt!
---if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
-				GOT_CMD_REG <= '1'; -- If command was received.
-			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
-				GOT_CMD_REG <= '1'; -- If command was received.
-			elsif MC_CLR_CMD = '1' then -- Clear done.
-				GOT_CMD_REG <= '0';
-			end if;
-		end if;
-	end process P_GOT_CMD;
-end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
deleted file mode 100644
index 2e85cdd..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
+++ /dev/null
@@ -1,214 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- 6850 compatible IP Core    					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- UART 6850 compatible IP core                                 ----
-----                                                              ----
----- Control unit and status logic.                               ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
--- Revision 2K9A  2009/06/20 WF
---   CTRL_REG has now synchronous reset to meet preset requirements.
---   Process P_DCD has now synchronous reset to meet preset requirements.
---   IRQ_In has now synchronous reset to meet preset requirement.
--- Revision 2K9B  2009/12/24 WF
---   Fixed the interrupt logic.
---   Introduced a minor RTSn correction.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF6850IP_CTRL_STATUS is
-  port (
-		CLK			: in std_logic;
-        RESETn		: in bit;
-
-        CS			: in bit_vector(2 downto 0); -- Active if "011".
-        E			: in bit;   
-        RWn     	: in bit;
-        RS			: in bit;
-
-        DATA_IN		: in bit_vector(7 downto 0);   
-        DATA_OUT	: out bit_vector(7 downto 0);   
-		DATA_EN		: out bit;
-		
-		-- Status register stuff:
-		RDRF		: in bit;	-- Receive data register full.
-		TDRE		: in bit;	-- Transmit data register empty.
-		DCDn		: in bit;	-- Data carrier detect.
-		CTSn		: in bit;	-- Clear to send.
-		FE			: in bit;	-- Framing error.
-		OVR			: in bit;	-- Overrun error.
-		PE			: in bit;	-- Parity error.
-
-		-- Control register stuff:
-		MCLR		: buffer bit; -- Master clear (high active).
-		RTSn		: out bit; -- Request to send.
-		CDS			: out bit_vector(1 downto 0); -- Clock control.
-		WS			: out bit_vector(2 downto 0); -- Word select.
-		TC			: out bit_vector(1 downto 0); -- Transmit control.
-		IRQn		: buffer bit -- Interrupt request.
-       );                                              
-end entity WF6850IP_CTRL_STATUS;
-
-architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
-signal CTRL_REG		: bit_vector(7 downto 0);
-signal STATUS_REG	: bit_vector(7 downto 0);
-signal RIE			: bit;
-signal CTS_In		: bit;
-signal DCD_In		: bit;
-signal DCD_FLAGn	: bit;
-begin
-	CTS_In <= CTSn;  
-	DCD_In <= DCDn;  -- immer 0
-
-	STATUS_REG(7) <= not IRQn;
-	STATUS_REG(6) <= PE;
-	STATUS_REG(5) <= OVR;
-	STATUS_REG(4) <= FE;
-	STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin.
-	STATUS_REG(2) <= DCD_FLAGn;
-	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
-	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
-
-	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
-	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
-	
-	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
-	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
-
-	CDS <= CTRL_REG(1 downto 0);
-	WS <= CTRL_REG(4 downto 2);
-	TC <= CTRL_REG(6 downto 5);
-	RIE <= CTRL_REG(7);
-	
-	P_IRQ: process(CLK)
-	variable irq_v 	: std_logic_vector(3 downto 0);
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0'  or MCLR = '1' then
-				irq_v := x"0";
-				IRQn <= '1';
-			else
-				-- Transmitter interrupt:
-				if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
-					if irq_v = x"F" then
-						irq_v := irq_v + 1;
-					end if;
-				-- Receiver interrupts:
-				elsif RDRF = '1' and RIE = '1' then
-					if irq_v < 15 then
-						irq_v := irq_v + 1;
-					end if;
-				-- Overrun
-				elsif OVR = '1' and RIE = '1' then
-					if irq_v < 15 then
-						irq_v := irq_v + 1;
-					end if;
-				else
-					if irq_v > 0 then
-						irq_v := irq_v - 1;
-					end if;
-				end if;
-				if irq_v < 8 then
-					IRQn <= '1';
-				else
-					IRQn <= '0';
-				end if;
-				-- The reset of the IRQ status flag:
-				-- Clear by writing to the transmit data register.
-				-- Clear by reading the receive data register.
-			end if;
-		end if;
-	end process P_IRQ;
-	
-	CONTROL: process(CLK)
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0' then
-				CTRL_REG <= "01000000";
-			elsif CS = "011" and RWn = '0' and RS = '0' then
-				CTRL_REG <= DATA_IN;
-			end if;
-		end if;
-	end process CONTROL;	
-
-	P_DCD: process(CLK)
-	-- This process is some kind of tricky. Refer to the MC6850 data
-	-- sheet for more information.
-	variable READ_LOCK		: boolean;
-	variable DCD_RELEASE	: boolean;
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0' then
-				DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
-				READ_LOCK := true;
-				DCD_RELEASE := false;
-			elsif MCLR = '1' then
-				DCD_FLAGn <= DCD_In;
-				READ_LOCK := true;
-			elsif DCD_In = '1' then
-				DCD_FLAGn <= '1';
-			elsif CS = "011" and RWn = '1' and RS = '0' then
-				READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
-			elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
-				-- Clear if receiver status register read access.
-				-- After data register has ben read and READ_LOCK again.
-				DCD_RELEASE := true;
-				READ_LOCK := true;
-				DCD_FLAGn <= DCD_In;
-			elsif DCD_In = '0' and DCD_RELEASE = true then
-				DCD_FLAGn <= '0';
-				DCD_RELEASE := false;
-			end if;
-		end if;
-	end process P_DCD;	
-end architecture BEHAVIOR;
-
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd
deleted file mode 100644
index c6626df..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd	
+++ /dev/null
@@ -1,419 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- 6850 compatible IP Core    					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- UART 6850 compatible IP core                                 ----
-----                                                              ----
----- 6850's receiver unit.                                        ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF6850IP_RECEIVE is
-  port (
-		CLK					: in bit;
-        RESETn				: in bit;
-		MCLR				: in bit;
-
-        CS					: in bit_vector(2 downto 0);
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-
-        DATA_OUT	        : out bit_vector(7 downto 0);   
-		DATA_EN				: out bit;
-		
-		WS					: in bit_vector(2 downto 0);
-		CDS					: in bit_vector(1 downto 0);
-
-        RXCLK				: in bit;
-        RXDATA				: in bit;
-
-		RDRF				: buffer bit;
-		OVR					: out bit;
-		PE					: out bit;
-		FE					: out bit
-       );                                              
-end entity WF6850IP_RECEIVE;
-
-architecture BEHAVIOR of WF6850IP_RECEIVE is
-type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
-signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
-signal RXDATA_I		: bit;
-signal RXDATA_S		: bit;
-signal DATA_REG		: bit_vector(7 downto 0);
-signal SHIFT_REG	: bit_vector(7 downto 0);
-signal CLK_STRB		: bit;
-signal BITCNT		: std_logic_vector(2 downto 0);
-begin
-	P_SAMPLE: process
-	-- This filter provides a synchronisation to the system
-	-- clock, even for random baud rates of the received data
-	-- stream.
-	variable FLT_TMP	: integer range 0 to 2;
-	begin
-		wait until CLK = '1' and CLK' event;
-		--
-		RXDATA_I <= RXDATA;
-		--
-		if RXDATA_I = '1' and FLT_TMP < 2 then
-			FLT_TMP := FLT_TMP + 1;
-		elsif RXDATA_I = '1' then
-			RXDATA_S <= '1';
-		elsif RXDATA_I = '0' and FLT_TMP > 0 then
-			FLT_TMP := FLT_TMP - 1;
-		elsif RXDATA_I = '0' then
-			RXDATA_S <= '0';
-		end if;
-	end process P_SAMPLE;
-
-	CLKDIV: process
-	variable CLK_LOCK	: boolean;
-	variable STRB_LOCK	: boolean;
-	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
-	begin
-		wait until CLK = '1' and CLK' event;
-		if CDS = "00" then -- Divider off.
-			if RXCLK = '1' and STRB_LOCK = false then
-				CLK_STRB <= '1';
-				STRB_LOCK := true;
-			elsif RXCLK = '0' then
-				CLK_STRB <= '0';
-				STRB_LOCK := false;
-			else
-				CLK_STRB <= '0';
-			end if;
-		elsif RCV_STATE = IDLE then
-			-- Preset the CLKDIV with the start delays.
-			if CDS = "01" then
-				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
-			elsif CDS = "10" then
-				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
-			end if;
-	 		CLK_STRB <= '0';
-		else
-			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
-				CLK_DIVCNT := CLK_DIVCNT - '1';
-				CLK_STRB <= '0';
-				CLK_LOCK := true;
-			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-				--
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
-				end if;
-			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-				if STRB_LOCK = false then
-					STRB_LOCK := true;
-					CLK_STRB <= '1';
-				else
-					CLK_STRB <= '0';
-				end if;
-			elsif RXCLK = '0' then
-				CLK_LOCK := false;
-				STRB_LOCK := false;
-				CLK_STRB <= '0';
-			else
-				CLK_STRB <= '0';
-			end if;
-		end if;
-	end process CLKDIV;
-	
-	DATAREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			DATA_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				DATA_REG <= x"00";
-			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
-			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-				-- Transfer from shift- to data register only if
-				-- data register is empty (RDRF = '0').
-				DATA_REG <= SHIFT_REG;
-			end if;
-		end if;
-	end process DATAREG;	
-    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
-    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
-	
-	SHIFTREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			SHIFT_REG <= x"00";
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				SHIFT_REG <= x"00";
-			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
-				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
-			end if;
-		end if;
-	end process SHIFTREG;	
-
-	P_BITCNT: process
-	begin
-		wait until CLK = '1' and CLK' event;
-		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
-			BITCNT <= BITCNT + '1';
-		elsif RCV_STATE /= SAMPLE then
-			BITCNT <= (others => '0');
-		end if;
-	end process P_BITCNT;
-
-	FRAME_ERR: process(RESETn, CLK)
-	-- This module detects a framing error
-	-- during stop bit 1 and stop bit 2.
-	variable FE_I: bit;
-	begin
-		if RESETn = '0' then
-			FE_I := '0';
-			FE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				FE_I := '0';
-				FE <= '0';
-			elsif CLK_STRB = '1' then
-				if RCV_STATE = STOP1 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
-					FE_I := '1';
-				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
-					FE_I := '0'; -- Error resets when correct data appears.
-				end if;
-			end if;
-			if RCV_STATE = SYNC then
-				FE <= FE_I; -- Update the FE every SYNC time.
-			end if;
-		end if;
-	end process FRAME_ERR;
-
-	OVERRUN: process(RESETn, CLK)
-	variable OVR_I		: bit;
-	variable FIRST_READ	: boolean;
-	begin
-		if RESETn = '0' then
-			OVR_I := '0';
-			OVR <= '0';
-			FIRST_READ := false;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				OVR_I := '0';
-				OVR <= '0';
-				FIRST_READ := false;
-			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
-				-- Overrun appears if RDRF is '1' in this state.
-				OVR_I := RDRF;
-			end if;
-			if CS = "011" and RWn = '1' and RS = '1' then
-				-- If an overrun was detected, the concerning flag is
-				-- set when the valid data word in the receiver data
-				-- register is read. Thereafter the RDRF flag is reset
-				-- and the overrun disappears (OVR_I goes low) after 
-				-- a second read (in time) of the receiver data register.
-				if FIRST_READ = false then
-					if OVR_I = '1' then
-						OVR <= '1';
-						OVR_I := '0';
-						FIRST_READ := true;
-					else
-						OVR <= '0';
-					end if;
-				end if;	
-			else
-				FIRST_READ := false;
-			end if;
-		end if;
-	end process OVERRUN;
-	
-	PARITY_TEST: process(RESETn, CLK)
-	variable PAR_TMP	: bit;
-	variable PE_I		: bit;
-	begin
-		if RESETn = '0' then
-			PE <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				PE <= '0';
-			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
-				PE_I := '0'; -- Initialise.
-				if RCV_STATE = PARITY then
-				    for i in 1 to 7 loop
-				        if i = 1 then
-				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
-				        else
-				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
-				        end if;
-				    end loop;
-					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
-				    	PE_I := PAR_TMP xor RXDATA_S;
-					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
-						PE_I := not PAR_TMP xor RXDATA_S;
-					else -- No parity for WS = "100" and WS = "101".
-						PE_I := '0';		
-					end if;
-				end if;
-			end if;
-			-- Transmit the parity flag together with the data
-			-- In other words: no parity to the status register
-			-- when RDRF inhibits the data transfer to the
-			-- receiver data register.
-			if RCV_STATE = SYNC and RDRF = '0' then
-				PE <= PE_I;
-			elsif CS = "011" and RWn = '1' and RS = '1' then
-				PE <= '0'; -- Clear when reading the data register.
-			end if;
-		end if;
-	end process PARITY_TEST;
-
-	P_RDRF: process(RESETn, CLK)
-	-- Receive data register full flag.
-	begin
-		if RESETn = '0' then
-			RDRF <= '0';
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RDRF <= '0';
-			elsif RCV_STATE = SYNC then
-				RDRF <= '1'; -- Data register is full until now!
-			elsif CS = "011" and RWn = '1' and RS = '1' then
-				RDRF <= '0'; -- After reading the data register ...
-			end if;
-		end if;
-	end process P_RDRF;
-	
-	RCV_STATEREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			RCV_STATE <= IDLE;
-		elsif CLK = '1' and CLK' event then
-			if MCLR = '1' then
-				RCV_STATE <= IDLE;
-			else
-				RCV_STATE <= RCV_NEXT_STATE;
-			end if;
-		end if;
-	end process RCV_STATEREG;
-	
-	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
-	begin
-		case RCV_STATE is
-			when IDLE =>
-				if RXDATA_S = '0' and CDS = "00" then
-					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
-				elsif RXDATA_S = '0' and CDS = "01" then
-					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
-				elsif RXDATA_S = '0' and CDS = "10" then
-					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
-				else
-					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
-				end if;
-			when WAIT_START =>
-				if CLK_STRB = '1' then
-					if RXDATA_S = '0' then
-						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
-					else
-						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
-					end if;
-				else
-					RCV_NEXT_STATE <= WAIT_START; -- Stay.
-				end if;
-			when SAMPLE =>
-				if CLK_STRB = '1' then
-					if BITCNT < "110" and WS(2) = '0' then
-						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
-					elsif BITCNT < "111" and WS(2) = '1' then
-						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
-					elsif WS = "100" or WS = "101" then
-						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
-					else
-						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
-					end if;
-				else
-					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
-				end if;
-			when PARITY =>
-				if CLK_STRB = '1' then
-					RCV_NEXT_STATE <= STOP1;
-				else
-					RCV_NEXT_STATE <= PARITY;
-				end if;				
-			when STOP1 =>
-				if CLK_STRB = '1' then
-					if RXDATA_S = '0' then
-						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
-					elsif WS = "000" or WS = "001" or WS = "100" then
-						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
-					else
-						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
-					end if;
-				else
-					RCV_NEXT_STATE <= STOP1;
-				end if;				
-			when STOP2 =>
-				if CLK_STRB = '1' then
-					RCV_NEXT_STATE <= SYNC;
-				else
-					RCV_NEXT_STATE <= STOP2;
-				end if;				
-			when SYNC =>
-				RCV_NEXT_STATE <= IDLE;
-		end case;
-	end process RCV_STATEDEC;
-end architecture BEHAVIOR;
-
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
deleted file mode 100644
index 8877e05..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
+++ /dev/null
@@ -1,425 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- 6850 compatible IP Core    					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- UART 6850 compatible IP core                                 ----
-----                                                              ----
----- 6850's receiver unit.                                        ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF6850IP_RECEIVE is
-  port (
-		CLK					: in std_logic;
-        RESETn				: in bit;
-		MCLR				: in bit;
-
-        CS					: in bit_vector(2 downto 0);
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-
-        DATA_OUT	        : out bit_vector(7 downto 0);   
-		DATA_EN				: out bit;
-		
-		WS					: in bit_vector(2 downto 0);
-		CDS					: in bit_vector(1 downto 0);
-
-        RXCLK				: in bit;
-        RXDATA				: in bit;
-
-		RDRF				: buffer bit;
-		OVR					: out bit;
-		PE					: out bit;
-		FE					: out bit
-       );                                              
-end entity WF6850IP_RECEIVE;
-
-architecture BEHAVIOR of WF6850IP_RECEIVE is
-type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
-signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
-signal RXDATA_I		: bit;
-signal RXDATA_S		: bit;
-signal DATA_REG		: bit_vector(7 downto 0);
-signal SHIFT_REG	: bit_vector(7 downto 0);
-signal CLK_STRB		: bit;
-signal BITCNT		: std_logic_vector(2 downto 0);
-begin
-	P_SAMPLE: process(CLK)
-	-- This filter provides a synchronisation to the system
-	-- clock, even for random baud rates of the received data
-	-- stream.
-	variable FLT_TMP	: integer range 0 to 2;
-	begin
-		if rising_edge(CLK) then
-			--
-			RXDATA_I <= RXDATA;
-			--
-			if RXDATA_I = '1' and FLT_TMP < 2 then
-				FLT_TMP := FLT_TMP + 1;
-			elsif RXDATA_I = '1' then
-				RXDATA_S <= '1';
-			elsif RXDATA_I = '0' and FLT_TMP > 0 then
-				FLT_TMP := FLT_TMP - 1;
-			elsif RXDATA_I = '0' then
-				RXDATA_S <= '0';
-			end if;
-		end if;
-	end process P_SAMPLE;
-
-	CLKDIV: process(CLK)
-	variable CLK_LOCK	: boolean;
-	variable STRB_LOCK	: boolean;
-	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
-	begin
-		if rising_edge(CLK) then
-			if CDS = "00" then -- Divider off.
-				if RXCLK = '1' and STRB_LOCK = false then
-					CLK_STRB <= '1';
-					STRB_LOCK := true;
-				elsif RXCLK = '0' then
-					CLK_STRB <= '0';
-					STRB_LOCK := false;
-				else
-					CLK_STRB <= '0';
-				end if;
-			elsif RCV_STATE = IDLE then
-				-- Preset the CLKDIV with the start delays.
-				if CDS = "01" then
-					CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
-				elsif CDS = "10" then
-					CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
-				end if;
-				CLK_STRB <= '0';
-			else
-				if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
-					CLK_DIVCNT := CLK_DIVCNT - '1';
-					CLK_STRB <= '0';
-					CLK_LOCK := true;
-				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-					--
-					if STRB_LOCK = false then
-						STRB_LOCK := true;
-						CLK_STRB <= '1';
-					else
-						CLK_STRB <= '0';
-					end if;
-				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-					if STRB_LOCK = false then
-						STRB_LOCK := true;
-						CLK_STRB <= '1';
-					else
-						CLK_STRB <= '0';
-					end if;
-				elsif RXCLK = '0' then
-					CLK_LOCK := false;
-					STRB_LOCK := false;
-					CLK_STRB <= '0';
-				else
-					CLK_STRB <= '0';
-				end if;
-			end if;
-		end if;
-	end process CLKDIV;
-	
-	DATAREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' or MCLR = '1' then
-			DATA_REG <= x"00";
-		else
-			if rising_edge(CLK) then
-				if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
-					-- Transfer from shift- to data register only if
-					-- data register is empty (RDRF = '0').
-					DATA_REG <= '0' & SHIFT_REG(7 downto 1);
-				elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
-					-- Transfer from shift- to data register only if
-					-- data register is empty (RDRF = '0').
-					DATA_REG <= SHIFT_REG;
-				end if;
-			end if;
-		end if;
-	end process DATAREG;	
-    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
-    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
-	
-	SHIFTREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' or MCLR = '1' then
-			SHIFT_REG <= x"00";
-		else
-			if rising_edge(CLK) then
-				if RCV_STATE = SAMPLE and CLK_STRB = '1' then
-					SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
-				end if;
-			end if;
-		end if;
-	end process SHIFTREG;	
-
-	P_BITCNT: process(CLK)
-	begin
-		if rising_edge(CLK) then
-			if RCV_STATE = SAMPLE and CLK_STRB = '1' then
-				BITCNT <= BITCNT + '1';
-			elsif RCV_STATE /= SAMPLE then
-				BITCNT <= (others => '0');
-			end if;
-		end if;
-	end process P_BITCNT;
-
-	FRAME_ERR: process(RESETn, CLK)
-	-- This module detects a framing error
-	-- during stop bit 1 and stop bit 2.
-	variable FE_I: bit;
-	begin
-		if RESETn = '0' then
-			FE_I := '0';
-			FE <= '0';
-		else
-			if rising_edge(CLK) then
-				if MCLR = '1' then
-					FE_I := '0';
-					FE <= '0';
-				elsif CLK_STRB = '1' then
-					if RCV_STATE = STOP1 and RXDATA_S = '0' then
-						FE_I := '1';
-					elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
-						FE_I := '1';
-					elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
-						FE_I := '0'; -- Error resets when correct data appears.
-					end if;
-				end if;
-				if RCV_STATE = SYNC then
-					FE <= FE_I; -- Update the FE every SYNC time.
-				end if;
-			end if;
-		end if;
-	end process FRAME_ERR;
-
-	OVERRUN: process(RESETn, CLK)
-	variable OVR_I		: bit;
-	variable FIRST_READ	: boolean;
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0'  or MCLR = '1' then
-				OVR_I := '0';
-				OVR <= '0';
-				FIRST_READ := false;
-			else
-				if CLK_STRB = '1' and RCV_STATE = STOP1 then
-				-- Overrun appears if RDRF is '1' in this state.
-					OVR_I := RDRF;
-				end if;
-				if CS = "011" and RWn = '1' and RS = '1' then
-				-- If an overrun was detected, the concerning flag is
-				-- set when the valid data word in the receiver data
-				-- register is read. Thereafter the RDRF flag is reset
-				-- and the overrun disappears (OVR_I goes low) after 
-				-- a second read (in time) of the receiver data register.
-					if FIRST_READ = false then
-						if OVR_I = '1' then
-							OVR <= '1';
-							OVR_I := '0';
-							FIRST_READ := true;
-						else
-							OVR <= '0';
-						end if;
-					end if;
-				else
-					FIRST_READ := false;
-				end if;
-			end if;
-		end if;
-	end process OVERRUN;
-	
-	PARITY_TEST: process(RESETn,MCLR,CLK)
-	variable PAR_TMP	: bit;
-	variable PE_I		: bit;
-	begin
-		if RESETn = '0' or MCRL = '1' then
-			PE <= '0';
-		else
-			if rising_edge(CLK) then
-				if CLK_STRB = '1' then -- Sample parity on clock strobe.
-					PE_I := '0'; -- Initialise.
-					if RCV_STATE = PARITY then
-						for i in 1 to 7 loop
-							if i = 1 then
-								PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
-							else
-								PAR_TMP := PAR_TMP xor SHIFT_REG(i);
-							end if;
-						end loop;
-						if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
-							PE_I := PAR_TMP xor RXDATA_S;
-						elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
-							PE_I := not PAR_TMP xor RXDATA_S;
-						else -- No parity for WS = "100" and WS = "101".
-							PE_I := '0';	
-						end if;	
-					end if;
-				end if;
-			end if;
-			-- Transmit the parity flag together with the data
-			-- In other words: no parity to the status register
-			-- when RDRF inhibits the data transfer to the
-			-- receiver data register.
-			if RCV_STATE = SYNC and RDRF = '0' then
-				PE <= PE_I;
-			elsif CS = "011" and RWn = '1' and RS = '1' then
-				PE <= '0'; -- Clear when reading the data register.
-			end if;
-		end if;
-	end process PARITY_TEST;
-
-	P_RDRF: process(RESETn, CLK)
-	-- Receive data register full flag.
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0' or MCLR = '1' then
-				RDRF <= '0';
-			else
-				if RCV_STATE = SYNC then
-					RDRF <= '1'; -- Data register is full until now!
-				end if;
-				if CS = "011" and RWn = '1' and RS = '1' then
-					RDRF <= '0'; -- when reading the data register ...
-				end if;
-			end if;
-		end if;
-	end process P_RDRF;
-	
-	RCV_STATEREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			RCV_STATE <= IDLE;
-		else
-			if rising_edge(CLK) then
-				if MCLR = '1' then
-					RCV_STATE <= IDLE;
-				else
-					RCV_STATE <= RCV_NEXT_STATE;
-				end if;
-			end if;
-		end if;
-	end process RCV_STATEREG;
-	
-	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
-	begin
-		case RCV_STATE is
-			when IDLE =>
-				if RXDATA_S = '0' and CDS = "00" then
-					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
-				elsif RXDATA_S = '0' and CDS = "01" then
-					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
-				elsif RXDATA_S = '0' and CDS = "10" then
-					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
-				else
-					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
-				end if;
-			when WAIT_START =>
-				if CLK_STRB = '1' then
-					if RXDATA_S = '0' then
-						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
-					else
-						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
-					end if;
-				else
-					RCV_NEXT_STATE <= WAIT_START; -- Stay.
-				end if;
-			when SAMPLE =>
-				if CLK_STRB = '1' then
-					if BITCNT < "110" and WS(2) = '0' then
-						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
-					elsif BITCNT < "111" and WS(2) = '1' then
-						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
-					elsif WS = "100" or WS = "101" then
-						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
-					else
-						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
-					end if;
-				else
-					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
-				end if;
-			when PARITY =>
-				if CLK_STRB = '1' then
-					RCV_NEXT_STATE <= STOP1;
-				else
-					RCV_NEXT_STATE <= PARITY;
-				end if;				
-			when STOP1 =>
-				if CLK_STRB = '1' then
-					if RXDATA_S = '0' then
-						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
-					elsif WS = "000" or WS = "001" or WS = "100" then
-						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
-					else
-						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
-					end if;
-				else
-					RCV_NEXT_STATE <= STOP1;
-				end if;				
-			when STOP2 =>
-				if CLK_STRB = '1' then
-					RCV_NEXT_STATE <= SYNC;
-				else
-					RCV_NEXT_STATE <= STOP2;
-				end if;				
-			when SYNC =>
-				RCV_NEXT_STATE <= IDLE;
-		end case;
-	end process RCV_STATEDEC;
-end architecture BEHAVIOR;
-
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
deleted file mode 100644
index 6f80a67..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
+++ /dev/null
@@ -1,252 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- 6850 compatible IP Core     					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- UART 6850 compatible IP core                                 ----
-----                                                              ----
----- This is the top level file.                                  ----
----- Top level file for use in systems on programmable chips.     ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
---   Top level file provided for SOC (systems on programmable chips).
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF6850IP_TOP_SOC is
-  port (
-		CLK					: in bit;
-        RESETn				: in bit;
-
-        CS2n, CS1, CS0		: in bit;
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-
-        DATA_IN		        : in std_logic_vector(7 downto 0);   
-        DATA_OUT	        : out std_logic_vector(7 downto 0);   
-		DATA_EN				: out bit;
-
-        TXCLK				: in bit;
-        RXCLK				: in bit;
-        RXDATA				: in bit;
-        CTSn				: in bit;
-        DCDn				: in bit;
-        
-        IRQn				: out bit;
-        TXDATA				: out bit;   
-        RTSn				: out bit
-       );                                              
-end entity WF6850IP_TOP_SOC;
-
-architecture STRUCTURE of WF6850IP_TOP_SOC is
-component WF6850IP_CTRL_STATUS
-	port (
-		CLK			: in bit;
-        RESETn		: in bit;
-        CS			: in bit_vector(2 downto 0);
-        E			: in bit;   
-        RWn     	: in bit;
-        RS			: in bit;
-        DATA_IN		: in bit_vector(7 downto 0);   
-        DATA_OUT	: out bit_vector(7 downto 0);  
-		DATA_EN		: out bit;
-		RDRF		: in bit;
-		TDRE		: in bit;
-		DCDn		: in bit;
-		CTSn		: in bit;
-		FE			: in bit;
-		OVR			: in bit;
-		PE			: in bit;
-		MCLR		: out bit;
-		RTSn		: out bit;
-		CDS			: out bit_vector(1 downto 0);
-		WS			: out bit_vector(2 downto 0);
-		TC			: out bit_vector(1 downto 0);
-		IRQn		: out bit
-       );                                              
-end component;
-
-component WF6850IP_RECEIVE
-	port (
-		CLK					: in bit;
-        RESETn				: in bit;
-		MCLR				: in bit;
-        CS					: in bit_vector(2 downto 0);
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-        DATA_OUT	        : out bit_vector(7 downto 0);   
-		DATA_EN				: out bit;
-		WS					: in bit_vector(2 downto 0);
-		CDS					: in bit_vector(1 downto 0);
-        RXCLK				: in bit;
-        RXDATA				: in bit;
-		RDRF				: out bit;
-		OVR					: out bit;
-		PE					: out bit;
-		FE					: out bit
-       );                                              
-end component;
-
-component WF6850IP_TRANSMIT
-	port (
-		CLK					: in bit;
-        RESETn				: in bit;
-		MCLR				: in bit;
-        CS					: in bit_vector(2 downto 0);
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-        DATA_IN		        : in bit_vector(7 downto 0);   
-		CTSn				: in bit;
-		TC					: in bit_vector(1 downto 0);
-		WS					: in bit_vector(2 downto 0);
-		CDS					: in bit_vector(1 downto 0);
-        TXCLK				: in bit;
-		TDRE				: out bit;        
-        TXDATA				: out bit
-       );                                              
-end component;
-signal DATA_IN_I	: bit_vector(7 downto 0);
-signal DATA_RX		: bit_vector(7 downto 0);
-signal DATA_RX_EN	: bit;
-signal DATA_CTRL	: bit_vector(7 downto 0);
-signal DATA_CTRL_EN	: bit;
-signal RDRF_I		: bit;
-signal TDRE_I		: bit;
-signal FE_I			: bit;
-signal OVR_I		: bit;
-signal PE_I			: bit;
-signal MCLR_I		: bit;
-signal CDS_I		: bit_vector(1 downto 0);
-signal WS_I			: bit_vector(2 downto 0);
-signal TC_I			: bit_vector(1 downto 0);
-signal IRQ_In		: bit;
-begin
-	DATA_IN_I <= To_BitVector(DATA_IN);
-	DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
-	DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
-				To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
-				
-	IRQn <= '0' when IRQ_In = '0' else '1';
-
-	I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
-	port map(
-			CLK			=> CLK,
-	        RESETn		=> RESETn,
-	        CS(2)		=> CS2n,
-	        CS(1)		=> CS1,
-	        CS(0)		=> CS0,
-	        E			=> E,
-	        RWn     	=> RWn,
-	        RS			=> RS,
-	        DATA_IN		=> DATA_IN_I,
-			DATA_OUT	=> DATA_CTRL,
-			DATA_EN		=> DATA_CTRL_EN,
-			RDRF		=> RDRF_I,
-			TDRE		=> TDRE_I,
-			DCDn		=> DCDn,
-			CTSn		=> CTSn,
-			FE			=> FE_I,
-			OVR			=> OVR_I,
-			PE			=> PE_I,
-			MCLR		=> MCLR_I,
-			RTSn		=> RTSn,
-			CDS			=> CDS_I,
-			WS			=> WS_I,
-			TC			=> TC_I,
-			IRQn		=> IRQ_In
-	);                                              
-
-	I_UART_RECEIVE: WF6850IP_RECEIVE
-	port map (
-			CLK			=> CLK,
-	        RESETn		=> RESETn,
-			MCLR		=> MCLR_I,
-	        CS(2)		=> CS2n,
-	        CS(1)		=> CS1,
-	        CS(0)		=> CS0,
-	        E			=> E,
-	        RWn     	=> RWn,
-	        RS			=> RS,
-	        DATA_OUT	=> DATA_RX,
-			DATA_EN		=> DATA_RX_EN,
-			WS			=> WS_I,
-			CDS			=> CDS_I,
-			RXCLK		=> RXCLK,
-			RXDATA		=> RXDATA,
-			RDRF		=> RDRF_I,
-			OVR			=> OVR_I,
-			PE			=> PE_I,
-			FE			=> FE_I
-	);                                              
-
-	I_UART_TRANSMIT: WF6850IP_TRANSMIT
-	port map (
-			CLK			=> CLK,
-	        RESETn		=> RESETn,
-			MCLR		=> MCLR_I,
-	        CS(2)		=> CS2n,
-	        CS(1)		=> CS1,
-	        CS(0)		=> CS0,
-	        E			=> E,
-	        RWn     	=> RWn,
-	        RS			=> RS,
-	        DATA_IN		=> DATA_IN_I,
-			CTSn		=> CTSn,
-			TC			=> TC_I,
-			WS			=> WS_I,
-			CDS			=> CDS_I,
-			TDRE		=> TDRE_I,
-			TXCLK		=> TXCLK,
-			TXDATA		=> TXDATA
-	);
-end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
deleted file mode 100644
index d6953d5..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
+++ /dev/null
@@ -1,338 +0,0 @@
-----------------------------------------------------------------------
-----                                                              ----
----- 6850 compatible IP Core    					              ----
-----                                                              ----
----- This file is part of the SUSKA ATARI clone project.          ----
----- http://www.experiment-s.de                                   ----
-----                                                              ----
----- Description:                                                 ----
----- UART 6850 compatible IP core                                 ----
-----                                                              ----
----- 6850's transmitter unit.                                     ----
-----                                                              ----
-----                                                              ----
----- To Do:                                                       ----
----- -                                                            ----
-----                                                              ----
----- Author(s):                                                   ----
----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
-----                                                              ----
-----------------------------------------------------------------------
-----                                                              ----
----- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
-----                                                              ----
----- This source file may be used and distributed without         ----
----- restriction provided that this copyright statement is not    ----
----- removed from the file and that any derivative work contains  ----
----- the original copyright notice and the associated disclaimer. ----
-----                                                              ----
----- This source file is free software; you can redistribute it   ----
----- and/or modify it under the terms of the GNU Lesser General   ----
----- Public License as published by the Free Software Foundation; ----
----- either version 2.1 of the License, or (at your option) any   ----
----- later version.                                               ----
-----                                                              ----
----- This source is distributed in the hope that it will be       ----
----- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
----- PURPOSE. See the GNU Lesser General Public License for more  ----
----- details.                                                     ----
-----                                                              ----
----- You should have received a copy of the GNU Lesser General    ----
----- Public License along with this source; if not, download it   ----
----- from http://www.gnu.org/licenses/lgpl.html                   ----
-----                                                              ----
-----------------------------------------------------------------------
--- 
--- Revision History
--- 
--- Revision 2K6A  2006/06/03 WF
---   Initial Release.
--- Revision 2K6B  2006/11/07 WF
---   Modified Source to compile with the Xilinx ISE.
--- Revision 2K8A  2008/07/14 WF
---   Minor changes.
--- Revision 2K8B  2008/11/01 WF
---   Fixed the T_DRE process concerning the TDRE <= '1' setting.
---   Thanks to Lyndon Amsdon finding the bug.
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity WF6850IP_TRANSMIT is
-  port (
-		CLK					: in std_logic;
-        RESETn				: in bit;
-		MCLR				: in bit;
-
-        CS					: in bit_vector(2 downto 0);
-        E		       		: in bit;   
-        RWn              	: in bit;
-        RS					: in bit;
-
-        DATA_IN		        : in bit_vector(7 downto 0);   
-
-		CTSn				: in bit;
-
-		TC					: in bit_vector(1 downto 0);
-		WS					: in bit_vector(2 downto 0);
-		CDS					: in bit_vector(1 downto 0);
-
-        TXCLK				: in bit;
-
-		TDRE				: buffer bit;
-        TXDATA				: out bit
-       );                                              
-end entity WF6850IP_TRANSMIT;
-
-architecture BEHAVIOR of WF6850IP_TRANSMIT is
-type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
-signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
-signal CLK_STRB		: bit;
-signal DATA_REG		: bit_vector(7 downto 0);
-signal SHIFT_REG	: bit_vector(7 downto 0);
-signal BITCNT		: std_logic_vector(2 downto 0);
-signal PARITY_I		: bit;
-begin
-	-- The default condition in this statement is to ensure
-	-- to cover all possibilities for example if there is a
-	-- one hot decoding of the state machine with wrong states
-	-- (e.g. not one of the given here).
-	TXDATA <= 	'1' 			when TR_STATE = IDLE 		else
-				'1' 			when TR_STATE = LOAD_SHFT 	else
-				'0' 			when TR_STATE = START 		else
-				SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
-				PARITY_I		when TR_STATE = PARITY 		else
-				'1'				when TR_STATE = STOP1 		else
-				'1'				when TR_STATE = STOP2 		else '1';
-
-	CLKDIV: process
-	variable CLK_LOCK	: boolean;
-	variable STRB_LOCK	: boolean;
-	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
-	begin
-		if rising_edge(CLK) then
-			if CDS = "00" then -- divider off
-				if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
-					CLK_STRB <= '1';
-					STRB_LOCK := true;
-				elsif TXCLK = '1' then
-					CLK_STRB <= '0';
-					STRB_LOCK := false;
-				else
-					CLK_STRB <= '0';
-				end if;
-			elsif TR_STATE = IDLE then
-				-- preset the CLKDIV with the start delays
-				if CDS = "01" then
-					CLK_DIVCNT := "0010000"; -- div by 16 mode
-				elsif CDS = "10" then
-					CLK_DIVCNT := "1000000"; -- div by 64 mode
-				end if;
-				CLK_STRB <= '0';
-			else
-				-- Works on negative TXCLK edge:
-				if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
-					CLK_DIVCNT := CLK_DIVCNT - '1';
-					CLK_STRB <= '0';
-					CLK_LOCK := true;
-				elsif CDS = "01" and CLK_DIVCNT = "0000000" then
-					CLK_DIVCNT := "0010000"; -- Div by 16 mode.
-					if STRB_LOCK = false then
-						STRB_LOCK := true;
-						CLK_STRB <= '1';
-					else
-						CLK_STRB <= '0';
-					end if;
-				elsif CDS = "10" and CLK_DIVCNT = "0000000" then
-					CLK_DIVCNT := "1000000"; -- Div by 64 mode.
-					if STRB_LOCK = false then
-						STRB_LOCK := true;
-						CLK_STRB <= '1';
-					else
-						CLK_STRB <= '0';
-					end if;
-				elsif TXCLK = '1' then
-					CLK_LOCK := false;
-					STRB_LOCK := false;
-					CLK_STRB <= '0';
-				else
-					CLK_STRB <= '0';
-				end if;
-			end if;
-		end if;
-	end process CLKDIV;
-
-	DATAREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			DATA_REG <= x"00";
-		elsif rising_edge(CLK) then
-			if MCLR = '1' then
-				DATA_REG <= x"00";
-			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
-				DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
-			elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
-				DATA_REG <= DATA_IN; -- 8 bit data mode.
-			end if;
-		end if;
-	end process DATAREG;	
-
-	SHIFTREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			SHIFT_REG <= x"00";
-		elsif rising_edge(CLK) then
-			if MCLR = '1' then
-				SHIFT_REG <= x"00";
-			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
-				-- If during LOAD_SHIFT the transmitter data register
-				-- is empty (TDRE = '1') the shift register will not
-				-- be loaded. When additionally TC = "11", the break
-				-- character (zero data and no stop bits) is sent.
-				SHIFT_REG <= DATA_REG;
-			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
-				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
-			end if;
-		end if;
-	end process SHIFTREG;	
-
-	P_BITCNT: process(CLK)
-	-- Counter for the data bits transmitted.
-	begin
-		if rising_edge(CLK) then
-			if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
-				BITCNT <= BITCNT + '1';
-			elsif TR_STATE /= SHIFTOUT then
-				BITCNT <= "000";
-			end if;
-		end if;
-	end process P_BITCNT;
-
-	P_TDRE: process(RESETn, CLK)
-	-- Transmit data register empty flag.
-	begin
-		if rising_edge(CLK) then
-			if RESETn = '0' or MCLR = '1' then
-				TDRE <= '1';
-			else
-				if TR_NEXT_STATE = START and TR_STATE /= START then
-				-- Data has been loaded to shift register, thus data register is free again.
-				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-				-- entering the state now.
-					TDRE <= '1';
-				end if;
-				if  CS = "011" and RWn = '0' and RS = '1' then
-					TDRE <= '0';
-				end if;
-			end if;
-		end if;
-	end process P_TDRE;
-
-	PARITY_GEN: process(CLK)
-	variable PAR_TMP	: bit;
-	begin
-		if rising_edge(CLK) then
-		if TR_STATE = START then -- Calculate the parity during the start phase.
-		    for i in 1 to 7 loop
-		        if i = 1 then
-		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
-		        else
-		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
-		        end if;
-		    end loop;
-			if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
-				PARITY_I <= PAR_TMP;
-			elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
-				PARITY_I <= not PAR_TMP;
-			else -- No parity for WS = "100" and WS = "101".
-				PARITY_I <= '0';		
-			end if;
-		end if;
-		end if;
-	end process PARITY_GEN;
-
-	TR_STATEREG: process(RESETn, CLK)
-	begin
-		if RESETn = '0' then
-			TR_STATE <= IDLE;
-		else
-			if rising_edge(CLK) then
-				if MCLR = '1' then
-					TR_STATE <= IDLE;
-				else
-					TR_STATE <= TR_NEXT_STATE;
-				end if;
-			end if;
-		end if;
-	end process TR_STATEREG;
-	
-	TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)
-	begin
-		case TR_STATE is
-			when IDLE =>
-				if TDRE = '1' and TC = "11" then
-					TR_NEXT_STATE <= LOAD_SHFT;
-				elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty.
-					TR_NEXT_STATE <= LOAD_SHFT;
-				else
-					TR_NEXT_STATE <= IDLE;
-				end if;
-			when LOAD_SHFT =>
-				TR_NEXT_STATE <= START;
-			when START =>
-				if CLK_STRB = '1' then
-					TR_NEXT_STATE <= SHIFTOUT;
-				else
-					TR_NEXT_STATE <= START;
-				end if;
-			when SHIFTOUT =>
-				if CLK_STRB = '1' then
-					if BITCNT < "110" and WS(2) = '0' then
-						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
-					elsif BITCNT < "111" and WS(2) = '1' then
-						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
-					elsif WS = "100" or WS = "101" then
-						if TDRE = '1' and TC = "11" then
-							-- Break condition, do not send a stop bit.
-							TR_NEXT_STATE <= IDLE;
-						else
-							TR_NEXT_STATE <= STOP1; -- No parity check enabled.
-						end if;
-					else
-						TR_NEXT_STATE <= PARITY; -- Parity enabled.
-					end if;
-				else
-					TR_NEXT_STATE <= SHIFTOUT;
-				end if;
-			when PARITY =>
-				if CLK_STRB = '1' then
-					if TDRE = '1' and TC = "11" then
-						-- Break condition, do not send a stop bit.
-						TR_NEXT_STATE <= IDLE;
-					else
-						TR_NEXT_STATE <= STOP1; -- No parity check enabled.
-					end if;
-				else
-					TR_NEXT_STATE <= PARITY;
-				end if;				
-			when STOP1 =>
-				if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
-					TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
-				elsif CLK_STRB = '1' then
-					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
-				else
-					TR_NEXT_STATE <= STOP1;
-				end if;				
-			when STOP2 =>
-				if CLK_STRB = '1' then
-					TR_NEXT_STATE <= IDLE;
-				else
-					TR_NEXT_STATE <= STOP2;
-				end if;				
-		end case;
-	end process TR_STATEDEC;
-end architecture BEHAVIOR;
-
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
new file mode 100644
index 0000000..e7c6ae6
--- /dev/null
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo1.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END dcfifo1;
+
+
+ARCHITECTURE SYN OF dcfifo1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(3 DOWNTO 0);
+	q    <= sub_wire1(7 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 16,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 16,
+		lpm_widthu => 4,
+		lpm_widthu_r => 5,
+		lpm_width_r => 8,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "16"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "16"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
new file mode 100644
index 0000000..7e4aa32
--- /dev/null
+++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
@@ -0,0 +1,391 @@
+TITLE "INTERRUPT HANDLER UND C1287";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_LONG.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN interrupt_handler
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	MAIN_CLK : INPUT;
+	nFB_WR : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	FB_ADR[31..0] : INPUT;
+	FPGA_DATE[31..0] : INPUT;
+	PIC_INT : INPUT;
+	E0_INT : INPUT;
+	DVI_INT : INPUT;
+	nPCI_INTA : INPUT;
+	nPCI_INTB : INPUT;
+	nPCI_INTC : INPUT;
+	nPCI_INTD : INPUT;
+	nMFP_INT : INPUT;
+	nFB_OE : INPUT;
+	DSP_INT : INPUT;
+	VSYNC : INPUT;
+	HSYNC : INPUT;
+	DMA_DRQ : INPUT;
+	nRSTO : INPUT;
+	nIRQ[7..2] : OUTPUT;
+	INT_HANDLER_TA : OUTPUT;
+	ACP_CONF[31..0] : OUTPUT;
+	TIN0 : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]				:NODE;
+	INT_CTR[31..0]			:DFFE;
+	INT_CTR_CS				:NODE;
+	INT_LATCH[31..0]		:DFF;
+	INT_LATCH_CS			:NODE;
+	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR_CS			:NODE;
+	INT_IN[31..0]			:NODE;
+	INT_ENA[31..0]			:DFFE;
+	INT_ENA_CS				:NODE;
+	INT_L[9..0]				:DFF;
+	INT_LA[9..0][3..0]		:DFF;
+	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF_CS				:NODE;
+	FPGA_DATE_CS			:NODE;
+	PSEUDO_BUS_ERROR		:NODE;
+	UHR_AS					:NODE;
+	UHR_DS					:NODE;
+	RTC_ADR[5..0]			:DFFE;
+	ACHTELSEKUNDEN[2..0]	:DFFE;
+	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		:DFF;
+	INC_SEC					:NODE;
+	INC_MIN					:NODE;
+	INC_STD					:NODE;
+	INC_TAG					:NODE;
+	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
+	WINTERZEIT				:NODE;
+	SOMMERZEIT				:NODE;
+	INC_MONAT				:NODE;
+	INC_JAHR				:NODE;
+	UPDATE_ON				:NODE;
+	
+BEGIN
+-- BYT SELECT
+	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+	INT_CTR[].CLK = MAIN_CLK;
+	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
+	INT_CTR[] = FB_AD[];
+	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
+	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
+	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
+	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA[].CLRN = nRSTO;
+	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
+	INT_ENA[] = FB_AD[];
+	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
+	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
+	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
+	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+	INT_CLEAR[].CLK = MAIN_CLK;
+	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
+	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
+	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
+	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
+	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT LATCH REGISTER READ ONLY
+	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+-- INTERRUPT
+	!nIRQ2 = HSYNC 						& INT_ENA[26];
+	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
+	!nIRQ4 = VSYNC 						& INT_ENA[28];
+	!nIRQ5 = INT_LATCH[]!=H"00000000" 	& INT_ENA[29];
+	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
+	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
+
+PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
+							#  FB_ADR[19..4]==H"F8E0"			-- VME
+--							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+--							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
+							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
+							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
+							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
+--							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+--							#  FB_ADR[19..4]==H"F892"			-- DMA SOUND
+							 );
+-- IF VIDEO ADR CHANGE
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+
+-- INTERRUPT LATCH
+	INT_L[].CLK = MAIN_CLK;
+	INT_L[].CLRN = nRSTO;
+	INT_L0 = PIC_INT & INT_ENA[0];
+	INT_L1 = E0_INT & INT_ENA[1];
+	INT_L2 = DVI_INT & INT_ENA[2];
+	INT_L3 = !nPCI_INTA & INT_ENA[3];
+	INT_L4 = !nPCI_INTB & INT_ENA[4];
+	INT_L5 = !nPCI_INTC & INT_ENA[5];
+	INT_L6 = !nPCI_INTD & INT_ENA[6];
+	INT_L7 = DSP_INT & INT_ENA[7];
+	INT_L8 = VSYNC & INT_ENA[8];
+	INT_L9 = HSYNC & INT_ENA[9];
+	
+	INT_LA[][].CLK = MAIN_CLK;
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
+	FOR I IN 0 TO 9 GENERATE
+		INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
+		INT_LA[I][] = INT_LA[I][]+1 &  INT_L[I] & INT_LA[I][]<7 
+		            # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
+		            # 15            &  INT_L[I] & INT_LA[I][]>6
+		            # 0             & !INT_L[I] & INT_LA[I][]<9;
+		INT_LATCH[I].CLK = INT_LA[I][3];
+	END GENERATE;
+	
+-- INT_IN
+	INT_IN0 = PIC_INT;
+	INT_IN1 = E0_INT;
+	INT_IN2 = DVI_INT;
+	INT_IN3 = !nPCI_INTA;
+	INT_IN4 = !nPCI_INTB;
+	INT_IN5 = !nPCI_INTC;
+	INT_IN6 = !nPCI_INTD;
+	INT_IN7 = DSP_INT;
+	INT_IN8 = VSYNC;
+	INT_IN9 = HSYNC;
+	INT_IN[25..10] = H"0";
+	INT_IN26 = HSYNC; 
+	INT_IN27 = INT_CTR0; 
+	INT_IN28 = VSYNC; 
+	INT_IN29 = INT_LATCH[]!=H"00000000";
+	INT_IN30 = !nMFP_INT; 
+	INT_IN31 = DMA_DRQ; 
+--***************************************************************************************
+-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
+	ACP_CONF[].CLK = MAIN_CLK;
+	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
+	ACP_CONF[] = FB_AD[];
+	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
+	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
+	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
+	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
+--***************************************************************************************
+-- FPGA DATE HEX (ddmmyyyy)
+	FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040";		-- $4'0000/4
+--***************************************************************************************
+	
+--------------------------------------------------------------	
+-- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+----------------------------------------------------------
+	RTC_ADR[].CLK = MAIN_CLK;
+	RTC_ADR[] = FB_AD[21..16];
+	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
+	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
+	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
+	WERTE[][].CLK = MAIN_CLK;
+	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[7..0][1] = FB_AD[23..16];
+	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[7..0][3] = FB_AD[23..16];
+	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[7..0][5] = FB_AD[23..16];
+	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	FOR I IN 10 TO 63 GENERATE
+		WERTE[7..0][I] = FB_AD[23..16];
+	END GENERATE;
+	FOR I IN 0 TO 63 GENERATE
+		WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
+	END GENERATE;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	
+	PIC_INT_SYNC[0] = PIC_INT;
+	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
+	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+	UPDATE_ON = !WERTE[7][11];		
+	WERTE[6][10].CLRN = GND;	-- KEIN UIP
+	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
+	WERTE[2][11] = VCC;	-- IMMER BINARY
+	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
+	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
+	WERTE[7][13] = VCC;	-- IMMER RICHTIG
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
+	WERTE[0][13] = SOMMERZEIT;
+	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
+	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+-- ACHTELSEKUNDEN
+	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
+	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
+	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+-- SEKUNDEN
+	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
+	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+-- MINUTEN
+	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
+	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+-- STUNDEN
+	INC_STD = INC_MIN & WERTE[][2]==59;							  
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
+	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
+-- WOCHENTAG UND TAG 
+	INC_TAG = INC_STD & WERTE[][2]==23;						
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
+			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
+	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
+	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
+							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
+							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
+							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
+			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
+	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+-- MONATE
+	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
+			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
+	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+-- JAHR		   
+	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
+	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+-- TRISTATE OUTPUT
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[31..24] 
+				  #	INT_ENA_CS   & INT_ENA[31..24]
+				  #	INT_LATCH_CS & INT_LATCH[31..24]
+				  # INT_CLEAR_CS & INT_IN[31..24]
+				  # ACP_CONF_CS  & ACP_CONF[31..24]
+				  # FPGA_DATE_CS  & FPGA_DATE[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[23..16] = lpm_bustri_BYT(
+				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
+				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
+				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
+				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
+				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
+				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
+				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
+				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
+				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
+				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
+				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
+				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
+				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
+				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
+				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
+				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
+				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
+				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
+				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
+				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
+				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
+				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
+				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
+				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
+				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
+				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
+				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
+				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
+				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
+				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
+				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
+				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
+				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
+				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
+				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
+				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
+				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
+				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
+				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
+				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
+				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
+				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
+				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
+				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
+				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
+				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
+				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
+				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
+				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
+				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
+				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
+				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
+				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
+				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
+				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
+				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
+				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
+				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
+				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
+				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
+				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
+				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
+				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
+				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
+				 # (0,RTC_ADR[])			   & UHR_AS
+				 # INT_CTR_CS   & INT_CTR[23..16] 
+				 # INT_ENA_CS   & INT_ENA[23..16]
+				 # INT_LATCH_CS & INT_LATCH[23..16]
+				 # INT_CLEAR_CS & INT_IN[23..16]
+				 # ACP_CONF_CS  & ACP_CONF[23..16]
+				 # FPGA_DATE_CS  & FPGA_DATE[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[15..8] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[15..8] 
+				  #	INT_ENA_CS   & INT_ENA[15..8]
+				  #	INT_LATCH_CS & INT_LATCH[15..8]
+				  # INT_CLEAR_CS & INT_IN[15..8]
+				  # ACP_CONF_CS  & ACP_CONF[15..8]
+				  # FPGA_DATE_CS  & FPGA_DATE[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[7..0] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[7..0] 
+				  #	INT_ENA_CS   & INT_ENA[7..0]
+				  #	INT_LATCH_CS & INT_LATCH[7..0]
+				  # INT_CLEAR_CS & INT_IN[7..0]
+				  # ACP_CONF_CS  & ACP_CONF[7..0]
+				  # FPGA_DATE_CS  & FPGA_DATE[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+
+	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
+END;
+
+
diff --git a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
new file mode 100644
index 0000000..797d4f8
--- /dev/null
+++ b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
@@ -0,0 +1,20 @@
+PLL_Name	altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
+PLLJITTER	36
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
+PLLJITTER	43
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
+PLLJITTER	NA
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
+PLLJITTER	31
+PLLSPEmax	84
+PLLSPEmin	-53
+
diff --git a/FPGA_by_Fredi/UNUSED b/FPGA_by_Fredi/UNUSED
new file mode 100644
index 0000000..3a7d9e6
--- /dev/null
+++ b/FPGA_by_Fredi/UNUSED
@@ -0,0 +1,27 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=3;
+DEPTH=16;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	00  :   7;
+	01  :   6;
+	02  :   5;
+	03  :   4;
+	04  :   3;
+	05  :   2;
+	06  :   1;
+	07  :   0;
+	08  :   7;
+	09  :   6;
+	0a  :   5;
+	0b  :   4;
+	0c  :   3;
+	0d  :   2;
+	0e  :   1;
+	0f  :   0;
+END;
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
new file mode 100644
index 0000000..c688f97
--- /dev/null
+++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
@@ -0,0 +1,659 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 1000;
+CONSTANT FIFO_HWM = 2000;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[10..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111";			-- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
+			SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111";			-- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111";			-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_by_Fredi/Video/UNUSED b/FPGA_by_Fredi/Video/UNUSED
new file mode 100644
index 0000000..12f424b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/UNUSED
@@ -0,0 +1,267 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=6;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	000  :   0F;
+	001  :   0E;
+	002  :   0D;
+	003  :   0C;
+	004  :   0B;
+	005  :   0A;
+	006  :   09;
+	007  :   08;
+	008  :   07;
+	009  :   06;
+	00a  :   05;
+	00b  :   04;
+	00c  :   03;
+	00d  :   02;
+	00e  :   01;
+	00f  :   00;
+	010  :   0F;
+	011  :   0E;
+	012  :   0D;
+	013  :   0C;
+	014  :   0B;
+	015  :   0A;
+	016  :   09;
+	017  :   08;
+	018  :   07;
+	019  :   06;
+	01a  :   05;
+	01b  :   04;
+	01c  :   03;
+	01d  :   02;
+	01e  :   01;
+	01f  :   00;
+	020  :   0F;
+	021  :   0E;
+	022  :   0D;
+	023  :   0C;
+	024  :   0B;
+	025  :   0A;
+	026  :   09;
+	027  :   08;
+	028  :   07;
+	029  :   06;
+	02a  :   05;
+	02b  :   04;
+	02c  :   03;
+	02d  :   02;
+	02e  :   01;
+	02f  :   00;
+	030  :   0F;
+	031  :   0E;
+	032  :   0D;
+	033  :   0C;
+	034  :   0B;
+	035  :   0A;
+	036  :   09;
+	037  :   08;
+	038  :   07;
+	039  :   06;
+	03a  :   05;
+	03b  :   04;
+	03c  :   03;
+	03d  :   02;
+	03e  :   01;
+	03f  :   00;
+	040  :   0F;
+	041  :   0E;
+	042  :   0D;
+	043  :   0C;
+	044  :   0B;
+	045  :   0A;
+	046  :   09;
+	047  :   08;
+	048  :   07;
+	049  :   06;
+	04a  :   05;
+	04b  :   04;
+	04c  :   03;
+	04d  :   02;
+	04e  :   01;
+	04f  :   00;
+	050  :   0F;
+	051  :   0E;
+	052  :   0D;
+	053  :   0C;
+	054  :   0B;
+	055  :   0A;
+	056  :   09;
+	057  :   08;
+	058  :   07;
+	059  :   06;
+	05a  :   05;
+	05b  :   04;
+	05c  :   03;
+	05d  :   02;
+	05e  :   01;
+	05f  :   00;
+	060  :   0F;
+	061  :   0E;
+	062  :   0D;
+	063  :   0C;
+	064  :   0B;
+	065  :   0A;
+	066  :   09;
+	067  :   08;
+	068  :   07;
+	069  :   06;
+	06a  :   05;
+	06b  :   04;
+	06c  :   03;
+	06d  :   02;
+	06e  :   01;
+	06f  :   00;
+	070  :   0F;
+	071  :   0E;
+	072  :   0D;
+	073  :   0C;
+	074  :   0B;
+	075  :   0A;
+	076  :   09;
+	077  :   08;
+	078  :   07;
+	079  :   06;
+	07a  :   05;
+	07b  :   04;
+	07c  :   03;
+	07d  :   02;
+	07e  :   01;
+	07f  :   00;
+	080  :   0F;
+	081  :   0E;
+	082  :   0D;
+	083  :   0C;
+	084  :   0B;
+	085  :   0A;
+	086  :   09;
+	087  :   08;
+	088  :   07;
+	089  :   06;
+	08a  :   05;
+	08b  :   04;
+	08c  :   03;
+	08d  :   02;
+	08e  :   01;
+	08f  :   00;
+	090  :   0F;
+	091  :   0E;
+	092  :   0D;
+	093  :   0C;
+	094  :   0B;
+	095  :   0A;
+	096  :   09;
+	097  :   08;
+	098  :   07;
+	099  :   06;
+	09a  :   05;
+	09b  :   04;
+	09c  :   03;
+	09d  :   02;
+	09e  :   01;
+	09f  :   00;
+	0a0  :   0F;
+	0a1  :   0E;
+	0a2  :   0D;
+	0a3  :   0C;
+	0a4  :   0B;
+	0a5  :   0A;
+	0a6  :   09;
+	0a7  :   08;
+	0a8  :   07;
+	0a9  :   06;
+	0aa  :   05;
+	0ab  :   04;
+	0ac  :   03;
+	0ad  :   02;
+	0ae  :   01;
+	0af  :   00;
+	0b0  :   0F;
+	0b1  :   0E;
+	0b2  :   0D;
+	0b3  :   0C;
+	0b4  :   0B;
+	0b5  :   0A;
+	0b6  :   09;
+	0b7  :   08;
+	0b8  :   07;
+	0b9  :   06;
+	0ba  :   05;
+	0bb  :   04;
+	0bc  :   03;
+	0bd  :   02;
+	0be  :   01;
+	0bf  :   00;
+	0c0  :   0F;
+	0c1  :   0E;
+	0c2  :   0D;
+	0c3  :   0C;
+	0c4  :   0B;
+	0c5  :   0A;
+	0c6  :   09;
+	0c7  :   08;
+	0c8  :   07;
+	0c9  :   06;
+	0ca  :   05;
+	0cb  :   04;
+	0cc  :   03;
+	0cd  :   02;
+	0ce  :   01;
+	0cf  :   00;
+	0d0  :   0F;
+	0d1  :   0E;
+	0d2  :   0D;
+	0d3  :   0C;
+	0d4  :   0B;
+	0d5  :   0A;
+	0d6  :   09;
+	0d7  :   08;
+	0d8  :   07;
+	0d9  :   06;
+	0da  :   05;
+	0db  :   04;
+	0dc  :   03;
+	0dd  :   02;
+	0de  :   01;
+	0df  :   00;
+	0e0  :   0F;
+	0e1  :   0E;
+	0e2  :   0D;
+	0e3  :   0C;
+	0e4  :   0B;
+	0e5  :   0A;
+	0e6  :   09;
+	0e7  :   08;
+	0e8  :   07;
+	0e9  :   06;
+	0ea  :   05;
+	0eb  :   04;
+	0ec  :   03;
+	0ed  :   02;
+	0ee  :   01;
+	0ef  :   00;
+	0f0  :   0F;
+	0f1  :   0E;
+	0f2  :   0D;
+	0f3  :   0C;
+	0f4  :   0B;
+	0f5  :   0A;
+	0f6  :   09;
+	0f7  :   08;
+	0f8  :   07;
+	0f9  :   06;
+	0fa  :   05;
+	0fb  :   04;
+	0fc  :   03;
+	0fd  :   02;
+	0fe  :   01;
+	0ff  :   00;
+END;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
new file mode 100644
index 0000000..2a594ff
--- /dev/null
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
@@ -0,0 +1,675 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	H_TOTAL[11..0]				:NODE;
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+--	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_by_Fredi/Video/altdpram0_wave0.jpg b/FPGA_by_Fredi/Video/altdpram0_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/altdpram0_waveforms.html b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
new file mode 100644
index 0000000..e0236fd
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram0.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/altdpram1_wave0.jpg b/FPGA_by_Fredi/Video/altdpram1_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/altdpram1_waveforms.html b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
new file mode 100644
index 0000000..85b4369
--- /dev/null
+++ b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram1.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/altdpram2_wave0.jpg b/FPGA_by_Fredi/Video/altdpram2_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/altdpram2_wave1.jpg b/FPGA_by_Fredi/Video/altdpram2_wave1.jpg
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+++ b/FPGA_by_Fredi/Video/altdpram2_waveforms.html
@@ -0,0 +1,16 @@
+<html>
+<head>
+<title>Sample Waveforms for altdpram2.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
+<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
+<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg b/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
new file mode 100644
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diff --git a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
new file mode 100644
index 0000000..e8242d9
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for lpm_compare1.vhd </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
+<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
+<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
new file mode 100644
index 0000000..956161a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
+<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd".  The design "lpm_fifoDZ.vhd" has a depth of 512 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
+<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
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zmODU_dsYFEkKWUHue`SO%F6E)q<Wz4Tu$l7S;ZS?Ao5$|2<*m|!qelee@XjMHn4th
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z`73O4e4?gAsVjK^<0W`x8eliPfWhNGQSXjPK`)~(ZrFdDh(A*lD_8BWro|>KUs)se
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zqPOLp!GyJ=KOeEi+!6}N5eX!t+-K#VFFd=!`gEny9$U7}X2Rhroo~~3W05*^i(7LP
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zq;|O;?M;1x_wB7+w?O;Jk|=In9|XwvT2;$ayAFuAE+nODaMDK}6-nhu6=zt(GTE@*
z*qsX=3Wghd_mM6$z!!KYrb>OnM`@_;glPd_GR2|uitgsI=eqI#qFPYg#WjGalgViM
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z&a*rCGQ88=C|{D5I2es)K-H#27SVC#=MET1y*X!{h57BriRsR}qw&94eamSt-OYsm
z+Z273FD2LTMDW{wH9gc*>)upK|56!Zx7tX$T+})=s*{ARG6KBC9n2PMwe|7ECFm<s
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DLMQw4

literal 0
HcmV?d00001

diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
new file mode 100644
index 0000000..20c4da2
--- /dev/null
+++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
+<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd".  The design "lpm_fifo_dc0.vhd" has a depth of 2048 words of 128 bits each. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
+<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
+<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
+<P></P>
+</body>
+</html>
diff --git a/FPGA_by_Fredi/altpll0_waveforms.html b/FPGA_by_Fredi/altpll0_waveforms.html
deleted file mode 100644
index 80e236a..0000000
--- a/FPGA_by_Fredi/altpll0_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "altpll0.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "altpll0.vhd" </CENTER></h2>
-<P></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/altpll1_waveforms.html b/FPGA_by_Fredi/altpll1_waveforms.html
deleted file mode 100644
index 1382a12..0000000
--- a/FPGA_by_Fredi/altpll1_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "altpll1.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "altpll1.vhd" </CENTER></h2>
-<P></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/altpll2_waveforms.html b/FPGA_by_Fredi/altpll2_waveforms.html
deleted file mode 100644
index 1932527..0000000
--- a/FPGA_by_Fredi/altpll2_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "altpll2.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "altpll2.vhd" </CENTER></h2>
-<P></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/altpll3_waveforms.html b/FPGA_by_Fredi/altpll3_waveforms.html
deleted file mode 100644
index 3f6367c..0000000
--- a/FPGA_by_Fredi/altpll3_waveforms.html
+++ /dev/null
@@ -1,10 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "altpll3.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "altpll3.vhd" </CENTER></h2>
-<P></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/blitter.tdf b/FPGA_by_Fredi/blitter.tdf
index c92f2a8..740423e 100644
--- a/FPGA_by_Fredi/blitter.tdf
+++ b/FPGA_by_Fredi/blitter.tdf
@@ -70,8 +70,11 @@ SUBDESIGN BLITTER
 )
 
 VARIABLE
-	FB_B[3..0]					:NODE;
+	BYT							:NODE;
+	LONGLINE					:NODE;
+	W_ADR[18..0]				:NODE;
 	FB_16B[1..0]				:NODE;
+	W_A1						:DFFE;
 	BLITTER_CS					:NODE;
 	BL_HRAM_CS 					:NODE;
 	BL_HRAM_BE[1..0]			:NODE;
@@ -160,30 +163,27 @@ VARIABLE
 	ENDMASK23_IN[143..0]		:NODE;
 	ENDMASK23_OUT[143..0]		:NODE;
 	ENDMASK123[127..0]			:NODE;
-	DDR_RAM_FREE				:NODE;
+	ENDMASKEND[15..0]			:NODE;
 	SRC_DDR_ADR[31..0]			:NODE;
 	DST_DDR_ADR[31..0]			:NODE;
+	BLITTER_REQ					:DFF;
 	
 -- MAIN STATE MACHINE
-	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
 	
 BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- wenn ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- or NOT BYT
+-- BYT UND WORD SELECT 16 BIT
+	BYT      = !FB_SIZE1 &  FB_SIZE0;
+	LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; 	-- LONG OR LINE
+	W_A1.CLK = MAIN_CLK;
+	W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
+	W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE;			-- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST
+	W_ADR[18..1] = FB_ADR[19..2];
+	W_ADR0 = W_A1;  
+	FB_16B0 = FB_ADR[0]==0;										-- wenn ADR==0
+	FB_16B1 = FB_ADR[0]==1 # !BYT;								-- wenn ADR==1 or NOT BYT
 -- BLITTER CS
-	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";			-- FFFF8A00-7F  
+	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";				-- FFFF8A00-7F  
 	BLITTER_TA = BLITTER_CS;
 -- REGISTER
 	-- HALFTON RAM 
@@ -192,114 +192,114 @@ BEGIN
 	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
 	WREN_B = B"0";
 	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
-	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
 	-- SRC X INC
 	BL_SRC_X_INC[].CLK = MAIN_CLK;
 	BL_SRC_X_INC[] = FB_AD[31..16];
-	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20.w
+	BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510";						-- $F8A20.w
 	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
 	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- SRC Y INC
 	BL_SRC_Y_INC[].CLK = MAIN_CLK;
 	BL_SRC_Y_INC[] = FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22.w
+	BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511";						-- $F8A22.w
 	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
 	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- SRC ADR HIGH
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24.w
+	BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512";						-- $F8A24.w
 	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
 	-- SRC ADR LOW
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[15..0] = FB_AD[31..16];
-	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";				-- $F8A26.w
+	BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513";						-- $F8A26.w
 	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
 	SRC_IADR[].CLK = DDRCLK0;
-	SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520";					-- $F8A40.w
-	SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521";					-- $F8A42.w
-	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520";						-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521";						-- $F8A42.w
+	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
 	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
 	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
 	-- ENDMASK 1
 	BL_ENDMASK1[].CLK = MAIN_CLK;
 	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";				-- $F8A28.w
+	BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514";						-- $F8A28.w
 	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 2
 	BL_ENDMASK2[].CLK = MAIN_CLK;
 	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";				-- $F8A2A.w
+	BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515";						-- $F8A2A.w
 	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 3
 	BL_ENDMASK3[].CLK = MAIN_CLK;
 	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";				-- $F8A2C.w
+	BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516";						-- $F8A2C.w
 	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
 	-- DST X INC
 	BL_DST_X_INC[].CLK = MAIN_CLK;
 	BL_DST_X_INC[] = FB_AD[31..16];
-	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";				-- $F8A2E.w
+	BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517";						-- $F8A2E.w
 	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
 	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- DST Y INC
 	BL_DST_Y_INC[].CLK = MAIN_CLK;
 	BL_DST_Y_INC[] = FB_AD[31..16];
-	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";				-- $F8A30.w
+	BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518";						-- $F8A30.w
 	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
 	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- DST ADR HIGH
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519";				-- $F8A32.w
+	BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519";						-- $F8A32.w
 	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
 	-- DST ADR LOW
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[15..0] = FB_AD[31..16];
-	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A";				-- $F8A34.w
+	BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A";						-- $F8A34.w
 	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
 	DST_IADR[].CLK = DDRCLK0;
-	DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522";					-- $F8A44.w
-	DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523";					-- $F8A46.w
+	DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522";						-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523";						-- $F8A46.w
 	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
 	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
 	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
 	-- X COUNT
 	BL_X_CNT[].CLK = MAIN_CLK;
 	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";					-- $F8A36.w
+	BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B";							-- $F8A36.w
 	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
 	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
 	X_INDEX[].CLK = DDRCLK0;
-	X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524";					-- $F8A48.w
+	X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524";							-- $F8A48.w
 	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
 	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
 	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
 	-- Y COUNT
 	BL_Y_CNT[].CLK = MAIN_CLK;
 	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";					-- $F8A38.w
+	BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C";							-- $F8A38.w
 	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
 	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
 	Y_INDEX[].CLK = DDRCLK0;
-	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";					-- $F8A4A.w
+	Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525";							-- $F8A4A.w
 	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
 	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
 	-- HOP LOGIC
 	BL_HOP[].CLK = MAIN_CLK;
 	BL_HOP[] = FB_AD[31..24];
-	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A.w
+	BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D";							-- $F8A3A.w
 	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
 	-- OP LOGIC
 	BL_OP[].CLK = MAIN_CLK;
@@ -309,7 +309,7 @@ BEGIN
 	BL_LN[].CLK = MAIN_CLK;
 	BL_LN[6..0] = FB_AD[30..24];	
 	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
-	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";						-- $F8A3C.w
+	BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E";							-- $F8A3C.w
 	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
 	BL_LN7.ENA = LN7CLR;
 	-- SKEW BYT
@@ -340,8 +340,8 @@ BEGIN
 					  # DST_IADRL_CS	& DST_IADR[15..0]
 					  # X_INDEX_CS		& X_INDEX[]
 					  # Y_INDEX_CS		& Y_INDEX[]
-					  ,BLITTER_CS & !nFB_OE); 											-- FFFF8A00-7F
------------------------------------------
+					  ,BLITTER_CS & !nFB_OE); 							-- FFFF8A00-7F
+--------------------------------------------------------------------------------------
 -- SRC BUFFER LADEN
 	BL_SRC_BUF1[].CLK = DDRCLK0;
 	BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
@@ -400,7 +400,7 @@ BEGIN
 		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
 		SHIFT_DIR = VCC;									-- DIR = RIGHT
 	else													
-		BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; 				-- LPM SHIFT LEFT
+		BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; 				-- LPM SHIFT LEFT
 		SHIFT_DIR = GND;									-- DIR = LEFT
 	end if;
 -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
@@ -471,15 +471,16 @@ BEGIN
 	END CASE;
 ------------ ENDMASKEN SETZEN ******************************************************************************																							 
 			ENDMASK1_SHIFT[3..0] = 0; 						
-			ENDMASK2_SHIFT[3..0] = 0; 						
+			ENDMASK2_SHIFT[3..0] = 0; 
 			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
 				IF X_INDEX[]==0 THEN															-- ENDE?	
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0));	-- JA ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
 				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));					
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;
@@ -490,7 +491,8 @@ BEGIN
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
 				END IF;		
 				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];					
+					ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0];								-- JA: ENDMASK 3 SETZEN
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
@@ -503,13 +505,14 @@ BEGIN
 	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
 	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
 	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
-	NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
--- STATE MACHINE ****************************************************************************************************	
+	NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
+-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 	
 	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
-	DDR_RAM_FREE = BLITTER_DACK[]==H"0";							-- 0 WENN FREI
 	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
 	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
 	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
 -- BLITTER MAIN STATE MACHINE  -----------------------------------------------
 	BL_SM.CLK = DDRCLK0;
 	CASE BL_SM IS
@@ -521,11 +524,24 @@ BEGIN
 			END IF;
 		WHEN NEW_LINE => ----------------------- NEU LINIE
 			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
-			BL_SM = RDSRC1;
+			BL_SM = RDSRC0;
+		WHEN RDSRC0 =>  ------------------------ READ SRC1
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
+				BLITTER_REQ = VCC;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					BL_SM = RDSRC2;
+				ELSE	
+					BL_SM = RDSRC1;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
 		WHEN RDSRC1 =>  ------------------------ READ SRC1
 			IF SRC_READ THEN
 				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
 				IF BLITTER_DACK0 THEN
 					SIINC = VCC;							-- INC SRC ADR
@@ -539,7 +555,7 @@ BEGIN
 		WHEN RDSRC2 =>	------------------------ READ SRC2
 			IF SRC_READ THEN
 				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
 				IF BLITTER_DACK0 THEN
 					SIINC = VCC;							-- INC SRC ADR
@@ -552,21 +568,23 @@ BEGIN
 			END IF;
 		WHEN RDDST =>	----------------------- READ DEST
 			IF NOT_DST_READ THEN
-				BL_SM = WRDST;
+				BL_SM = WRDSTW1;
 			ELSE
 				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_DST = VCC;
 				IF BLITTER_DACK0 THEN
-					BL_SM = WRDST;
+					BL_SM = WRDSTW1;
 				ELSE	
 					BL_SM = RDDST;
 				END IF;
 			END IF;
+		WHEN WRDSTW1 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
+			BL_SM = WRDST;
 		WHEN WRDST =>	------------------- WRITE DEST
 			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
-			BLITTER_WR = DDR_RAM_FREE;
-			BLITTER_SIG = DDR_RAM_FREE;
+			BLITTER_WR = VCC;
+			BLITTER_REQ = VCC;
 			IF BLITTER_DACK0 THEN
 				XIINC = VCC;								-- INC X_INDEX
 				DIINC = VCC;								-- INC DEST ADR
@@ -575,7 +593,7 @@ BEGIN
 				BL_SM = WRDST;
 			END IF;
 		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
-			IF BL_X_CNT[]<=(X_CNT_NODE[])	 THEN			-- SCHON ZEILENENDE?	
+			IF X_CNT_NODE[] >= BL_X_CNT[] THEN				-- SCHON ZEILENENDE?	
 				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
 				BL_SM = TESTFERTIG;							-- ->
 			ELSE
@@ -583,7 +601,7 @@ BEGIN
 			END IF;	
 		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
 			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
-			IF Y_INDEX[]>=BL_Y_CNT[] THEN					-- LETZTE ZEILE?
+			IF Y_INDEX[] >= BL_Y_CNT[] THEN					-- LETZTE ZEILE?
 				BL_SM = FERTIG;								-- JA -->
 			ELSE
 				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak
index f06d03b..8669470 100644
--- a/FPGA_by_Fredi/blitter.tdf.bak
+++ b/FPGA_by_Fredi/blitter.tdf.bak
@@ -70,8 +70,11 @@ SUBDESIGN BLITTER
 )
 
 VARIABLE
-	FB_B[3..0]					:NODE;
+	BYT							:NODE;
+	LONGLINE					:NODE;
+	W_ADR[18..0]				:NODE;
 	FB_16B[1..0]				:NODE;
+	W_A1						:DFFE;
 	BLITTER_CS					:NODE;
 	BL_HRAM_CS 					:NODE;
 	BL_HRAM_BE[1..0]			:NODE;
@@ -160,30 +163,27 @@ VARIABLE
 	ENDMASK23_IN[143..0]		:NODE;
 	ENDMASK23_OUT[143..0]		:NODE;
 	ENDMASK123[127..0]			:NODE;
-	DDR_RAM_FREE				:NODE;
+	ENDMASKEND[15..0]			:NODE;
 	SRC_DDR_ADR[31..0]			:NODE;
 	DST_DDR_ADR[31..0]			:NODE;
+	BLITTER_REQ					:DFF;
 	
 -- MAIN STATE MACHINE
-	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDSTW2,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
 	
 BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- wenn ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- or NOT BYT
+-- BYT UND WORD SELECT 16 BIT
+	BYT      = !FB_SIZE1 &  FB_SIZE0;
+	LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; 	-- LONG OR LINE
+	W_A1.CLK = MAIN_CLK;
+	W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
+	W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE;			-- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST
+	W_ADR[18..1] = FB_ADR[19..2];
+	W_ADR0 = W_A1;  
+	FB_16B0 = FB_ADR[0]==0;										-- wenn ADR==0
+	FB_16B1 = FB_ADR[0]==1 # !BYT;								-- wenn ADR==1 or NOT BYT
 -- BLITTER CS
-	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";			-- FFFF8A00-7F  
+	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";				-- FFFF8A00-7F  
 	BLITTER_TA = BLITTER_CS;
 -- REGISTER
 	-- HALFTON RAM 
@@ -192,114 +192,114 @@ BEGIN
 	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
 	WREN_B = B"0";
 	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
-	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
 	-- SRC X INC
 	BL_SRC_X_INC[].CLK = MAIN_CLK;
 	BL_SRC_X_INC[] = FB_AD[31..16];
-	BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510";					-- $F8A20.w
+	BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510";						-- $F8A20.w
 	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
 	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- SRC Y INC
 	BL_SRC_Y_INC[].CLK = MAIN_CLK;
 	BL_SRC_Y_INC[] = FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511";					-- $F8A22.w
+	BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511";						-- $F8A22.w
 	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
 	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- SRC ADR HIGH
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512";					-- $F8A24.w
+	BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512";						-- $F8A24.w
 	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
 	-- SRC ADR LOW
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[15..0] = FB_AD[31..16];
-	BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513";				-- $F8A26.w
+	BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513";						-- $F8A26.w
 	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
 	SRC_IADR[].CLK = DDRCLK0;
-	SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520";					-- $F8A40.w
-	SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521";					-- $F8A42.w
-	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
+	SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520";						-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521";						-- $F8A42.w
+	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
 	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
 	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
 	-- ENDMASK 1
 	BL_ENDMASK1[].CLK = MAIN_CLK;
 	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514";				-- $F8A28.w
+	BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514";						-- $F8A28.w
 	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 2
 	BL_ENDMASK2[].CLK = MAIN_CLK;
 	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515";				-- $F8A2A.w
+	BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515";						-- $F8A2A.w
 	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 3
 	BL_ENDMASK3[].CLK = MAIN_CLK;
 	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516";				-- $F8A2C.w
+	BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516";						-- $F8A2C.w
 	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
 	-- DST X INC
 	BL_DST_X_INC[].CLK = MAIN_CLK;
 	BL_DST_X_INC[] = FB_AD[31..16];
-	BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517";				-- $F8A2E.w
+	BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517";						-- $F8A2E.w
 	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
 	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- DST Y INC
 	BL_DST_Y_INC[].CLK = MAIN_CLK;
 	BL_DST_Y_INC[] = FB_AD[31..16];
-	BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518";				-- $F8A30.w
+	BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518";						-- $F8A30.w
 	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
 	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
 	-- DST ADR HIGH
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519";				-- $F8A32.w
+	BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519";						-- $F8A32.w
 	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
 	-- DST ADR LOW
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[15..0] = FB_AD[31..16];
-	BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A";				-- $F8A34.w
+	BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A";						-- $F8A34.w
 	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
 	DST_IADR[].CLK = DDRCLK0;
-	DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522";					-- $F8A44.w
-	DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523";					-- $F8A46.w
+	DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522";						-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523";						-- $F8A46.w
 	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
 	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
 	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
 	-- X COUNT
 	BL_X_CNT[].CLK = MAIN_CLK;
 	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B";					-- $F8A36.w
+	BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B";							-- $F8A36.w
 	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
 	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
 	X_INDEX[].CLK = DDRCLK0;
-	X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524";					-- $F8A48.w
+	X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524";							-- $F8A48.w
 	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
 	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
 	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
 	-- Y COUNT
 	BL_Y_CNT[].CLK = MAIN_CLK;
 	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";					-- $F8A38.w
+	BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C";							-- $F8A38.w
 	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
 	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
 	Y_INDEX[].CLK = DDRCLK0;
-	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";					-- $F8A4A.w
+	Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525";							-- $F8A4A.w
 	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
 	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
 	-- HOP LOGIC
 	BL_HOP[].CLK = MAIN_CLK;
 	BL_HOP[] = FB_AD[31..24];
-	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";						-- $F8A3A.w
+	BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D";							-- $F8A3A.w
 	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
 	-- OP LOGIC
 	BL_OP[].CLK = MAIN_CLK;
@@ -309,7 +309,7 @@ BEGIN
 	BL_LN[].CLK = MAIN_CLK;
 	BL_LN[6..0] = FB_AD[30..24];	
 	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
-	BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E";						-- $F8A3C.w
+	BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E";							-- $F8A3C.w
 	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
 	BL_LN7.ENA = LN7CLR;
 	-- SKEW BYT
@@ -340,8 +340,8 @@ BEGIN
 					  # DST_IADRL_CS	& DST_IADR[15..0]
 					  # X_INDEX_CS		& X_INDEX[]
 					  # Y_INDEX_CS		& Y_INDEX[]
-					  ,BLITTER_CS & !nFB_OE); 											-- FFFF8A00-7F
------------------------------------------
+					  ,BLITTER_CS & !nFB_OE); 							-- FFFF8A00-7F
+--------------------------------------------------------------------------------------
 -- SRC BUFFER LADEN
 	BL_SRC_BUF1[].CLK = DDRCLK0;
 	BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
@@ -400,7 +400,7 @@ BEGIN
 		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
 		SHIFT_DIR = VCC;									-- DIR = RIGHT
 	else													
-		BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; 				-- LPM SHIFT LEFT
+		BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; 				-- LPM SHIFT LEFT
 		SHIFT_DIR = GND;									-- DIR = LEFT
 	end if;
 -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
@@ -471,15 +471,16 @@ BEGIN
 	END CASE;
 ------------ ENDMASKEN SETZEN ******************************************************************************																							 
 			ENDMASK1_SHIFT[3..0] = 0; 						
-			ENDMASK2_SHIFT[3..0] = 0; 						
+			ENDMASK2_SHIFT[3..0] = 0; 
 			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
 				IF X_INDEX[]==0 THEN															-- ENDE?	
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0));	-- JA ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
 				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));					
+					ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;
@@ -490,7 +491,8 @@ BEGIN
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
 				END IF;		
 				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1]));						-- JA ENDMASK 3 SETZEN 
+					ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];					
+					ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0];								-- JA: ENDMASK 3 SETZEN
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
@@ -503,13 +505,14 @@ BEGIN
 	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
 	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
 	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
-	NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1);
--- STATE MACHINE ****************************************************************************************************	
+	NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
+-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 	
 	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
-	DDR_RAM_FREE = BLITTER_DACK[]==H"0";							-- 0 WENN FREI
 	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
 	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
 	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
 -- BLITTER MAIN STATE MACHINE  -----------------------------------------------
 	BL_SM.CLK = DDRCLK0;
 	CASE BL_SM IS
@@ -521,11 +524,24 @@ BEGIN
 			END IF;
 		WHEN NEW_LINE => ----------------------- NEU LINIE
 			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
-			BL_SM = RDSRC1;
+			BL_SM = RDSRC0;
+		WHEN RDSRC0 =>  ------------------------ READ SRC1
+			IF SRC_READ THEN
+				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
+				BLITTER_REQ = VCC;
+				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
+				IF BLITTER_DACK0 THEN
+					BL_SM = RDSRC2;
+				ELSE	
+					BL_SM = RDSRC1;
+				END IF;
+			ELSE
+				BL_SM = RDDST;
+			END IF;
 		WHEN RDSRC1 =>  ------------------------ READ SRC1
 			IF SRC_READ THEN
 				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
 				IF BLITTER_DACK0 THEN
 					SIINC = VCC;							-- INC SRC ADR
@@ -539,7 +555,7 @@ BEGIN
 		WHEN RDSRC2 =>	------------------------ READ SRC2
 			IF SRC_READ THEN
 				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
 				IF BLITTER_DACK0 THEN
 					SIINC = VCC;							-- INC SRC ADR
@@ -551,22 +567,26 @@ BEGIN
 				BL_SM = RDDST;
 			END IF;
 		WHEN RDDST =>	----------------------- READ DEST
-			IF NOT_READ_DST THEN
-				BL_SM = WRDST;
+			IF NOT_DST_READ THEN
+				BL_SM = WRDSTW1;
 			ELSE
 				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
-				BLITTER_SIG = DDR_RAM_FREE;
+				BLITTER_REQ = VCC;
 				BL_READ_DST = VCC;
 				IF BLITTER_DACK0 THEN
-					BL_SM = WRDST;
+					BL_SM = WRDSTW1;
 				ELSE	
 					BL_SM = RDDST;
 				END IF;
 			END IF;
+		WHEN WRDSTW1 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
+			BL_SM = WRDSTW2;
+		WHEN WRDSTW2 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
+			BL_SM = WRDST;
 		WHEN WRDST =>	------------------- WRITE DEST
 			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
-			BLITTER_WR = DDR_RAM_FREE;
-			BLITTER_SIG = DDR_RAM_FREE;
+			BLITTER_WR = VCC;
+			BLITTER_REQ = VCC;
 			IF BLITTER_DACK0 THEN
 				XIINC = VCC;								-- INC X_INDEX
 				DIINC = VCC;								-- INC DEST ADR
@@ -575,7 +595,7 @@ BEGIN
 				BL_SM = WRDST;
 			END IF;
 		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
-			IF BL_X_CNT[]<=(X_CNT_NODE[])	 THEN			-- SCHON ZEILENENDE?	
+			IF X_CNT_NODE[] >= BL_X_CNT[] THEN				-- SCHON ZEILENENDE?	
 				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
 				BL_SM = TESTFERTIG;							-- ->
 			ELSE
@@ -583,7 +603,7 @@ BEGIN
 			END IF;	
 		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
 			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
-			IF Y_INDEX[]>=BL_Y_CNT[] THEN					-- LETZTE ZEILE?
+			IF Y_INDEX[] >= BL_Y_CNT[] THEN					-- LETZTE ZEILE?
 				BL_SM = FERTIG;								-- JA -->
 			ELSE
 				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
diff --git a/FPGA_by_Fredi/firebee1.asm.rpt b/FPGA_by_Fredi/firebee1.asm.rpt
deleted file mode 100644
index 0641298..0000000
--- a/FPGA_by_Fredi/firebee1.asm.rpt
+++ /dev/null
@@ -1,128 +0,0 @@
-Assembler report for firebee1
-Thu Apr 13 11:08:24 2017
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Assembler Summary
-  3. Assembler Settings
-  4. Assembler Generated Files
-  5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof
-  6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf
-  7. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary                                             ;
-+-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Thu Apr 13 11:08:24 2017 ;
-; Revision Name         ; firebee1                              ;
-; Top-level Entity Name ; firebee1                              ;
-; Family                ; Cyclone III                           ;
-; Device                ; EP3C40F484C6                          ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------+
-; Assembler Settings                                                                                       ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Option                                                                      ; Setting    ; Default Value ;
-+-----------------------------------------------------------------------------+------------+---------------+
-; Generate Raw Binary File (.rbf) For Target Device                           ; On         ; Off           ;
-; Hexadecimal Output File start address                                       ; 0XE0700000 ; 0             ;
-; Use smart compilation                                                       ; Off        ; Off           ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On         ; On            ;
-; Enable compact report table                                                 ; Off        ; Off           ;
-; Generate compressed bitstreams                                              ; On         ; On            ;
-; Compression mode                                                            ; Off        ; Off           ;
-; Clock source for configuration device                                       ; Internal   ; Internal      ;
-; Clock frequency of the configuration device                                 ; 10 MHZ     ; 10 MHz        ;
-; Divide clock frequency by                                                   ; 1          ; 1             ;
-; Auto user code                                                              ; Off        ; Off           ;
-; Use configuration device                                                    ; Off        ; Off           ;
-; Configuration device                                                        ; Auto       ; Auto          ;
-; Configuration device auto user code                                         ; Off        ; Off           ;
-; Generate Tabular Text File (.ttf) For Target Device                         ; Off        ; Off           ;
-; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off        ; Off           ;
-; Hexadecimal Output File count direction                                     ; Up         ; Up            ;
-; Release clears before tri-states                                            ; Off        ; Off           ;
-; Auto-restart configuration after error                                      ; On         ; On            ;
-; Enable OCT_DONE                                                             ; Off        ; Off           ;
-; Generate Serial Vector Format File (.svf) for Target Device                 ; Off        ; Off           ;
-; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off        ; Off           ;
-; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On         ; On            ;
-+-----------------------------------------------------------------------------+------------+---------------+
-
-
-+------------------------------+
-; Assembler Generated Files    ;
-+------------------------------+
-; File Name                    ;
-+------------------------------+
-; C:/FireBee/FPGA/firebee1.sof ;
-; C:/FireBee/FPGA/firebee1.rbf ;
-+------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ;
-+----------------+---------------------------------------+
-; Option         ; Setting                               ;
-+----------------+---------------------------------------+
-; Device         ; EP3C40F484C6                          ;
-; JTAG usercode  ; 0xFFFFFFFF                            ;
-; Checksum       ; 0x01072C3E                            ;
-+----------------+---------------------------------------+
-
-
-+--------------------------------------------------------+
-; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ;
-+---------------------+----------------------------------+
-; Option              ; Setting                          ;
-+---------------------+----------------------------------+
-; Raw Binary File     ;                                  ;
-;  Compression Ratio  ; 2                                ;
-+---------------------+----------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II Assembler
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Thu Apr 13 11:08:20 2017
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1
-Info: Writing out detailed assembly data for power analysis
-Info: Assembler is generating device programming files
-Info: Quartus II Assembler was successful. 0 errors, 0 warnings
-    Info: Peak virtual memory: 310 megabytes
-    Info: Processing ended: Thu Apr 13 11:08:24 2017
-    Info: Elapsed time: 00:00:04
-    Info: Total CPU time (on all processors): 00:00:05
-
-
diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
index dc29aec..beb9946 100644
--- a/FPGA_by_Fredi/firebee1.bdf
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -3506,7 +3506,7 @@ applicable agreement for further details.
 		(line (pt 88 24)(pt 72 24)(line_width 3))
 	)
 	(drawing
-		(text "319037463" (rect 27 18 80 30)(font "Arial" ))
+		(text "402923543" (rect 27 18 80 30)(font "Arial" ))
 		(text "32" (rect 77 25 88 37)(font "Arial" ))
 		(line (pt 16 16)(pt 72 16)(line_width 1))
 		(line (pt 72 16)(pt 72 32)(line_width 1))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index 1c56ddf..2f3cd55 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Thu Apr 13 11:08:39 2017
+Tue Apr 18 20:21:44 2017
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
deleted file mode 100644
index 33aa7d2..0000000
--- a/FPGA_by_Fredi/firebee1.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Apr 13 11:08:12 2017
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Device : EP3C40F484C6
-Timing Models : Final
-Total logic elements : 20,945 / 39,600 ( 53 % )
-    Total combinational functions : 19,059 / 39,600 ( 48 % )
-    Dedicated logic registers : 5,696 / 39,600 ( 14 % )
-Total registers : 5845
-Total pins : 296 / 332 ( 89 % )
-Total virtual pins : 0
-Total memory bits : 355,360 / 1,161,216 ( 31 % )
-Embedded Multiplier 9-bit elements : 12 / 252 ( 5 % )
-Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.flow.rpt b/FPGA_by_Fredi/firebee1.flow.rpt
deleted file mode 100644
index 1bad0f9..0000000
--- a/FPGA_by_Fredi/firebee1.flow.rpt
+++ /dev/null
@@ -1,428 +0,0 @@
-Flow report for firebee1
-Sat Apr 15 23:46:36 2017
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Flow Summary
-  3. Flow Settings
-  4. Flow Non-Default Global Settings
-  5. Flow Elapsed Time
-  6. Flow OS Summary
-  7. Flow Log
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary                                                                      ;
-+------------------------------------+----------------------------------------------+
-; Flow Status                        ; Successful - Sat Apr 15 23:46:35 2017        ;
-; Quartus II Version                 ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
-; Revision Name                      ; firebee1                                     ;
-; Top-level Entity Name              ; firebee1                                     ;
-; Family                             ; Cyclone III                                  ;
-; Device                             ; EP3C40F484C6                                 ;
-; Timing Models                      ; Final                                        ;
-; Met timing requirements            ; N/A                                          ;
-; Total logic elements               ; 22,593                                       ;
-;     Total combinational functions  ; 19,050                                       ;
-;     Dedicated logic registers      ; 5,711                                        ;
-; Total registers                    ; 5839                                         ;
-; Total pins                         ; 296                                          ;
-; Total virtual pins                 ; 0                                            ;
-; Total memory bits                  ; 355,360                                      ;
-; Embedded Multiplier 9-bit elements ; 12                                           ;
-; Total PLLs                         ; 4                                            ;
-+------------------------------------+----------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings                           ;
-+-------------------+---------------------+
-; Option            ; Setting             ;
-+-------------------+---------------------+
-; Start date & time ; 04/15/2017 23:43:13 ;
-; Main task         ; Compilation         ;
-; Revision Name     ; firebee1            ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings                                                                                            ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; Assignment Name                         ; Value                              ; Default Value ; Entity Name ; Section Id     ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID                   ; 1098263457634.149229259302120      ; --            ; --          ; --             ;
-; CYCLONEII_OPTIMIZATION_TECHNIQUE        ; Speed                              ; Balanced      ; --          ; --             ;
-; FMAX_REQUIREMENT                        ; 30 ns                              ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_RAM_DP+                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_LATCH                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COMPARE                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_BUSTRI                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_BIDIR                      ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTDDIO_OUT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FIFO+                          ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL_RECONFIG                    ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTPLL                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTSYNCRAM                         ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_SHIFTREG                       ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_COUNTER                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; ALTIOBUF                           ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_MUX                            ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_FF                             ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CLSHIFT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CLSHIFT                        ; --            ; --          ; --             ;
-; IP_TOOL_NAME                            ; LPM_CONSTANT                       ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 8.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; IP_TOOL_VERSION                         ; 9.1                                ; --            ; --          ; --             ;
-; MAX_CORE_JUNCTION_TEMP                  ; 85                                 ; --            ; --          ; --             ;
-; MIN_CORE_JUNCTION_TEMP                  ; 0                                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/firebee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; C:/FireBee/FPGA/firebee1.dpf       ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll1.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll2.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll3.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll0.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter0.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram0.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri1.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram1.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri2.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri4.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant0.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux0.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux1.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux2.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altdpram2.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_bustri6.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux3.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux4.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg1.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_latch1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_constant4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg2.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_compare1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_LONG.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_BYT.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_bustri_WORD.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff4.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff5.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_ff6.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg3.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.bsf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.inc           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.cmp           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_bidir0.ppf           ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out0.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux5.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg5.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg6.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.bsf            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.inc            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_shiftreg4.cmp            ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out1.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.bsf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.inc             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.cmp             ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/altddio_out2.ppf             ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.inc                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altddio_out3.ppf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.bsf                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.inc                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_mux6.cmp                 ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; --            ; --          ; --             ;
-; MISC_FILE                               ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxDZ.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_muxVDM.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.tdf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.bsf               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.inc               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll_reconfig1.cmp               ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.tdf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.bsf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.inc                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.cmp                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; altpll4.ppf                        ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux0.tdf                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux0.bsf                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux0.inc                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux0.cmp                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/altsyncram0.tdf      ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/altsyncram0.inc      ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_shiftreg0.tdf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_shiftreg0.bsf                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_shiftreg0.inc                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_shiftreg0.cmp                  ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter1.tdf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter1.bsf                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter1.inc                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_counter1.cmp                   ; --            ; --          ; --             ;
-; MISC_FILE                               ; altiobuf_bidir0.tdf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; altiobuf_bidir0.bsf                ; --            ; --          ; --             ;
-; MISC_FILE                               ; altiobuf_bidir0.inc                ; --            ; --          ; --             ;
-; MISC_FILE                               ; altiobuf_bidir0.cmp                ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux1.tdf                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux1.bsf                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux1.inc                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; lpm_mux1.cmp                       ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_blitter.bsf              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_blitter.inc              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/lpm_blitter.cmp              ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.tdf   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.inc   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/lpm_clshift384.cmp   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/lpm_clshift144.tdf   ; --            ; --          ; --             ;
-; MISC_FILE                               ; Video/BLITTER/lpm_clshift144.inc   ; --            ; --          ; --             ;
-; MISC_FILE                               ; FPGA_DATE.tdf                      ; --            ; --          ; --             ;
-; MISC_FILE                               ; FPGA_DATE.bsf                      ; --            ; --          ; --             ;
-; MISC_FILE                               ; FPGA_DATE.inc                      ; --            ; --          ; --             ;
-; NOMINAL_CORE_SUPPLY_VOLTAGE             ; 1.2V                               ; --            ; --          ; --             ;
-; PARTITION_COLOR                         ; 16764057                           ; --            ; --          ; Top            ;
-; PARTITION_FITTER_PRESERVATION_LEVEL     ; PLACEMENT_AND_ROUTING              ; --            ; --          ; Top            ;
-; PARTITION_NETLIST_TYPE                  ; SOURCE                             ; --            ; --          ; Top            ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC          ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On                                 ; Off           ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_EFFORT               ; Fast                               ; Normal        ; --          ; --             ;
-; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On                                 ; Off           ; --          ; --             ;
-; POWER_BOARD_THERMAL_MODEL               ; None (CONSERVATIVE)                ; --            ; --          ; --             ;
-; POWER_PRESET_COOLING_SOLUTION           ; No Heat Sink With Still Air        ; --            ; --          ; --             ;
-; POWER_USE_TA_VALUE                      ; 35                                 ; 25            ; --          ; --             ;
-; STATE_MACHINE_PROCESSING                ; One-Hot                            ; Auto          ; --          ; --             ;
-; TCO_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TH_REQUIREMENT                          ; 1 ns                               ; --            ; --          ; --             ;
-; TPD_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; TSU_REQUIREMENT                         ; 1 ns                               ; --            ; --          ; --             ;
-; USE_GENERATED_PHYSICAL_CONSTRAINTS      ; Off                                ; --            ; --          ; eda_blast_fpga ;
-; USE_TIMEQUEST_TIMING_ANALYZER           ; Off                                ; On            ; --          ; --             ;
-+-----------------------------------------+------------------------------------+---------------+-------------+----------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time                                                                                                        ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:03:20     ; 1.0                     ; 355 MB              ; 00:03:21                           ;
-; Total                ; 00:03:20     ; --                      ; --                  ; 00:03:21                           ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+---------------------------------------------------------------------------------------+
-; Flow OS Summary                                                                       ;
-+----------------------+------------------+---------------+------------+----------------+
-; Module Name          ; Machine Hostname ; OS Name       ; OS Version ; Processor type ;
-+----------------------+------------------+---------------+------------+----------------+
-; Analysis & Synthesis ; Vaio             ; Windows Vista ; 6.1        ; x86_64         ;
-+----------------------+------------------+---------------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
-
-
-
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
deleted file mode 100644
index aa8c768..0000000
--- a/FPGA_by_Fredi/firebee1.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Sat Apr 15 23:46:35 2017
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Total logic elements : 22,593
-    Total combinational functions : 19,050
-    Dedicated logic registers : 5,711
-Total registers : 5839
-Total pins : 296
-Total virtual pins : 0
-Total memory bits : 355,360
-Embedded Multiplier 9-bit elements : 12
-Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.rbf b/FPGA_by_Fredi/firebee1.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..57fa4418da290793ac1399a37d709d1562ba7537
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diff --git a/FPGA_by_Fredi/firebee1.sim.rpt b/FPGA_by_Fredi/firebee1.sim.rpt
deleted file mode 100644
index 6bfa8c3..0000000
--- a/FPGA_by_Fredi/firebee1.sim.rpt
+++ /dev/null
@@ -1,247 +0,0 @@
-Simulator report for firebee1
-Fri Mar 10 13:17:46 2017
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
-  1. Legal Notice
-  2. Simulator Summary
-  3. Simulator Settings
-  4. Simulation Waveforms
-  5. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM
-  6. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
-  7. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
-  8. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
-  9. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM
- 10. |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM
- 11. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
- 12. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
- 13. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM
- 14. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM
- 15. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
- 16. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM
- 17. |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM
- 18. |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM
- 19. |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM
- 20. Coverage Summary
- 21. Complete 1/0-Value Coverage
- 22. Missing 1-Value Coverage
- 23. Missing 0-Value Coverage
- 24. Simulator INI Usage
- 25. Simulator Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-
-
-
-+-------------------+
-; Simulator Summary ;
-+------+------------+
-; Type ; Value      ;
-+------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Simulator Settings                                                                                                        ;
-+--------------------------------------------------------------------------------------------+--------------+---------------+
-; Option                                                                                     ; Setting      ; Default Value ;
-+--------------------------------------------------------------------------------------------+--------------+---------------+
-; Simulation mode                                                                            ; Timing       ; Timing        ;
-; Start time                                                                                 ; 0 ns         ; 0 ns          ;
-; End time                                                                                   ; 2 us         ;               ;
-; Simulation results format                                                                  ; CVWF         ;               ;
-; Vector input source                                                                        ; firebee1.vwf ;               ;
-; Add pins automatically to simulation output waveforms                                      ; Off          ; On            ;
-; Check outputs                                                                              ; Off          ; Off           ;
-; Report simulation coverage                                                                 ; On           ; On            ;
-; Display complete 1/0 value coverage report                                                 ; On           ; On            ;
-; Display missing 1-value coverage report                                                    ; On           ; On            ;
-; Display missing 0-value coverage report                                                    ; On           ; On            ;
-; Detect setup and hold time violations                                                      ; Off          ; Off           ;
-; Detect glitches                                                                            ; Off          ; Off           ;
-; Disable timing delays in Timing Simulation                                                 ; Off          ; Off           ;
-; Generate Signal Activity File                                                              ; Off          ; Off           ;
-; Generate VCD File for PowerPlay Power Analyzer                                             ; Off          ; Off           ;
-; Group bus channels in simulation results                                                   ; Off          ; Off           ;
-; Preserve fewer signal transitions to reduce memory requirements                            ; On           ; On            ;
-; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE   ; INPUT_EDGE    ;
-; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off          ; Off           ;
-; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off          ;               ;
-; Perform Glitch Filtering in Timing Simulation                                              ; Auto         ; Auto          ;
-; Interconnect Delay Model Type                                                              ; Transport    ; Transport     ;
-; Cell Delay Model Type                                                                      ; Transport    ; Transport     ;
-+--------------------------------------------------------------------------------------------+--------------+---------------+
-
-
-+----------------------+
-; Simulation Waveforms ;
-+----------------------+
-Waveform report data cannot be output to ASCII.
-Please use Quartus II to view the waveform report data.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
-+-----------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
-+------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
-+-------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ;
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM ;
-+-----------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
-+----------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
-+---------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ;
-+--------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ;
-+----------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
-+-------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ;
-+-----------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ;
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ;
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ;
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
-Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
-
-
-+------------------+
-; Coverage Summary ;
-+------+-----------+
-; Type ; Value     ;
-+------+-----------+
-
-
-The following table displays output ports that toggle between 1 and 0 during simulation.
-+-------------------------------------------------+
-; Complete 1/0-Value Coverage                     ;
-+-----------+------------------+------------------+
-; Node Name ; Output Port Name ; Output Port Type ;
-+-----------+------------------+------------------+
-
-
-The following table displays output ports that do not toggle to 1 during simulation.
-+-------------------------------------------------+
-; Missing 1-Value Coverage                        ;
-+-----------+------------------+------------------+
-; Node Name ; Output Port Name ; Output Port Type ;
-+-----------+------------------+------------------+
-
-
-The following table displays output ports that do not toggle to 0 during simulation.
-+-------------------------------------------------+
-; Missing 0-Value Coverage                        ;
-+-----------+------------------+------------------+
-; Node Name ; Output Port Name ; Output Port Type ;
-+-----------+------------------+------------------+
-
-
-+---------------------+
-; Simulator INI Usage ;
-+--------+------------+
-; Option ; Usage      ;
-+--------+------------+
-
-
-+--------------------+
-; Simulator Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus II Simulator
-    Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-    Info: Processing started: Fri Mar 10 13:17:43 2017
-Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1
-Info: Can't find specified vector source file "C:/FireBee/FPGA/firebee1.vwf"
-Warning: Can't display state machine states -- register holding state machine bit "|firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" was synthesized away
-Error: No valid vector source file specified and default file "C:/FireBee/FPGA/firebee1.cvwf" does not exist
-Error: Quartus II Simulator was unsuccessful. 1 error, 1 warning
-    Error: Peak virtual memory: 241 megabytes
-    Error: Processing ended: Fri Mar 10 13:17:46 2017
-    Error: Elapsed time: 00:00:03
-    Error: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/FPGA_by_Fredi/firebee1.sta.summary b/FPGA_by_Fredi/firebee1.sta.summary
deleted file mode 100644
index 08274d1..0000000
--- a/FPGA_by_Fredi/firebee1.sta.summary
+++ /dev/null
@@ -1,857 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type  : Slow 1200mV 85C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -17.450
-TNS   : -16147.437
-
-Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -7.331
-TNS   : -4287.365
-
-Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -4.994
-TNS   : -47.649
-
-Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -4.588
-TNS   : -478.150
-
-Type  : Slow 1200mV 85C Model Setup 'MAIN_CLK'
-Slack : -4.230
-TNS   : -5479.268
-
-Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 2.377
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 2.892
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 3.750
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 5.312
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 497.531
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 1997.881
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -11.047
-TNS   : -9871.573
-
-Type  : Slow 1200mV 85C Model Hold 'MAIN_CLK'
-Slack : -10.882
-TNS   : -9731.628
-
-Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -5.940
-TNS   : -5.940
-
-Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.283
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.342
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.376
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 0.389
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 1.541
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 2.366
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 3.005
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 4.128
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -15.674
-TNS   : -2798.000
-
-Type  : Slow 1200mV 85C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -8.406
-TNS   : -16.812
-
-Type  : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -4.536
-TNS   : -782.022
-
-Type  : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -4.460
-TNS   : -652.825
-
-Type  : Slow 1200mV 85C Model Recovery 'MAIN_CLK'
-Slack : -3.788
-TNS   : -646.634
-
-Type  : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -2.802
-TNS   : -2.802
-
-Type  : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -1.533
-TNS   : -1.533
-
-Type  : Slow 1200mV 85C Model Recovery 'DVI_INT'
-Slack : -0.826
-TNS   : -0.826
-
-Type  : Slow 1200mV 85C Model Recovery 'E0_INT'
-Slack : -0.766
-TNS   : -0.766
-
-Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTA'
-Slack : -0.281
-TNS   : -0.281
-
-Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTD'
-Slack : -0.267
-TNS   : -0.267
-
-Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTC'
-Slack : -0.249
-TNS   : -0.249
-
-Type  : Slow 1200mV 85C Model Recovery 'nPCI_INTB'
-Slack : -0.188
-TNS   : -0.188
-
-Type  : Slow 1200mV 85C Model Recovery 'PIC_INT'
-Slack : -0.038
-TNS   : -0.038
-
-Type  : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -10.353
-TNS   : -1430.734
-
-Type  : Slow 1200mV 85C Model Removal 'MAIN_CLK'
-Slack : -10.188
-TNS   : -1400.869
-
-Type  : Slow 1200mV 85C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -2.755
-TNS   : -5.510
-
-Type  : Slow 1200mV 85C Model Removal 'PIC_INT'
-Slack : -0.526
-TNS   : -0.526
-
-Type  : Slow 1200mV 85C Model Removal 'nPCI_INTB'
-Slack : -0.361
-TNS   : -0.361
-
-Type  : Slow 1200mV 85C Model Removal 'nPCI_INTC'
-Slack : -0.295
-TNS   : -0.295
-
-Type  : Slow 1200mV 85C Model Removal 'nPCI_INTD'
-Slack : -0.274
-TNS   : -0.274
-
-Type  : Slow 1200mV 85C Model Removal 'nPCI_INTA'
-Slack : -0.256
-TNS   : -0.256
-
-Type  : Slow 1200mV 85C Model Removal 'E0_INT'
-Slack : 0.237
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Removal 'DVI_INT'
-Slack : 0.299
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : 1.026
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 1.036
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : 2.350
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.015
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'PIC_INT'
-Slack : -3.000
-TNS   : -4.134
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTB'
-Slack : -3.000
-TNS   : -4.079
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTD'
-Slack : -3.000
-TNS   : -4.070
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTC'
-Slack : -3.000
-TNS   : -4.050
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTA'
-Slack : -3.000
-TNS   : -4.038
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'DVI_INT'
-Slack : -3.000
-TNS   : -4.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'E0_INT'
-Slack : -3.000
-TNS   : -4.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 3.527
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.533
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.533
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 3.533
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 4.811
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 7.320
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 10.398
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'MAIN_CLK'
-Slack : 13.528
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 18.585
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 30.973
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 249.617
-TNS   : 0.000
-
-Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 999.882
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -15.403
-TNS   : -14377.209
-
-Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -6.421
-TNS   : -3676.693
-
-Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -4.520
-TNS   : -37.132
-
-Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -4.094
-TNS   : -426.105
-
-Type  : Slow 1200mV 0C Model Setup 'MAIN_CLK'
-Slack : -3.696
-TNS   : -4132.088
-
-Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 2.718
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 2.995
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 3.994
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 5.426
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 497.772
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 1998.168
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -9.832
-TNS   : -8727.393
-
-Type  : Slow 1200mV 0C Model Hold 'MAIN_CLK'
-Slack : -9.617
-TNS   : -8529.400
-
-Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -5.065
-TNS   : -5.065
-
-Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.254
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.297
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.335
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 0.346
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 1.517
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 2.163
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 2.766
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 4.082
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -13.902
-TNS   : -2482.848
-
-Type  : Slow 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -7.532
-TNS   : -15.064
-
-Type  : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -3.927
-TNS   : -573.408
-
-Type  : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -3.851
-TNS   : -663.617
-
-Type  : Slow 1200mV 0C Model Recovery 'MAIN_CLK'
-Slack : -3.223
-TNS   : -549.949
-
-Type  : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -2.555
-TNS   : -2.555
-
-Type  : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -1.377
-TNS   : -1.377
-
-Type  : Slow 1200mV 0C Model Recovery 'DVI_INT'
-Slack : -0.706
-TNS   : -0.706
-
-Type  : Slow 1200mV 0C Model Recovery 'E0_INT'
-Slack : -0.653
-TNS   : -0.653
-
-Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTA'
-Slack : -0.192
-TNS   : -0.192
-
-Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTD'
-Slack : -0.190
-TNS   : -0.190
-
-Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTC'
-Slack : -0.180
-TNS   : -0.180
-
-Type  : Slow 1200mV 0C Model Recovery 'nPCI_INTB'
-Slack : -0.104
-TNS   : -0.104
-
-Type  : Slow 1200mV 0C Model Recovery 'PIC_INT'
-Slack : 0.013
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -9.193
-TNS   : -1262.369
-
-Type  : Slow 1200mV 0C Model Removal 'MAIN_CLK'
-Slack : -8.978
-TNS   : -1223.454
-
-Type  : Slow 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -2.195
-TNS   : -4.390
-
-Type  : Slow 1200mV 0C Model Removal 'PIC_INT'
-Slack : -0.527
-TNS   : -0.527
-
-Type  : Slow 1200mV 0C Model Removal 'nPCI_INTB'
-Slack : -0.384
-TNS   : -0.384
-
-Type  : Slow 1200mV 0C Model Removal 'nPCI_INTC'
-Slack : -0.316
-TNS   : -0.316
-
-Type  : Slow 1200mV 0C Model Removal 'nPCI_INTD'
-Slack : -0.288
-TNS   : -0.288
-
-Type  : Slow 1200mV 0C Model Removal 'nPCI_INTA'
-Slack : -0.283
-TNS   : -0.283
-
-Type  : Slow 1200mV 0C Model Removal 'E0_INT'
-Slack : 0.170
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'DVI_INT'
-Slack : 0.223
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : 0.914
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.936
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : 2.150
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 2.663
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
-Slack : -3.000
-TNS   : -4.036
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
-Slack : -3.000
-TNS   : -4.036
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
-Slack : -3.000
-TNS   : -4.012
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
-Slack : -3.000
-TNS   : -4.002
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
-Slack : -3.000
-TNS   : -4.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'E0_INT'
-Slack : -3.000
-TNS   : -4.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
-Slack : -3.000
-TNS   : -4.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 3.517
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.528
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.529
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 3.529
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 4.909
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 7.316
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 10.392
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
-Slack : 13.634
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 18.774
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 30.967
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 249.612
-TNS   : 0.000
-
-Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 999.877
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -9.748
-TNS   : -9757.013
-
-Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -3.484
-TNS   : -1911.267
-
-Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -2.773
-TNS   : -9.357
-
-Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -2.483
-TNS   : -260.497
-
-Type  : Fast 1200mV 0C Model Setup 'MAIN_CLK'
-Slack : -1.767
-TNS   : -1399.694
-
-Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.283
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 3.689
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 4.868
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 5.744
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 498.517
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 1998.908
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -6.775
-TNS   : -6188.069
-
-Type  : Fast 1200mV 0C Model Hold 'MAIN_CLK'
-Slack : -6.521
-TNS   : -5940.597
-
-Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -3.440
-TNS   : -3.440
-
-Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 0.136
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.178
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.197
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 0.204
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 1.296
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 1.392
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 1.655
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.971
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -9.449
-TNS   : -1688.035
-
-Type  : Fast 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -4.842
-TNS   : -9.684
-
-Type  : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : -2.521
-TNS   : -370.829
-
-Type  : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -2.077
-TNS   : -353.703
-
-Type  : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -1.593
-TNS   : -1.593
-
-Type  : Fast 1200mV 0C Model Recovery 'MAIN_CLK'
-Slack : -1.560
-TNS   : -261.778
-
-Type  : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -0.866
-TNS   : -0.866
-
-Type  : Fast 1200mV 0C Model Recovery 'DVI_INT'
-Slack : -0.475
-TNS   : -0.475
-
-Type  : Fast 1200mV 0C Model Recovery 'E0_INT'
-Slack : -0.438
-TNS   : -0.438
-
-Type  : Fast 1200mV 0C Model Recovery 'PIC_INT'
-Slack : -0.086
-TNS   : -0.086
-
-Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTA'
-Slack : 0.253
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTC'
-Slack : 0.262
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTD'
-Slack : 0.263
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Recovery 'nPCI_INTB'
-Slack : 0.294
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : -6.385
-TNS   : -890.317
-
-Type  : Fast 1200mV 0C Model Removal 'MAIN_CLK'
-Slack : -6.131
-TNS   : -844.343
-
-Type  : Fast 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : -1.544
-TNS   : -3.088
-
-Type  : Fast 1200mV 0C Model Removal 'nPCI_INTB'
-Slack : -0.648
-TNS   : -0.648
-
-Type  : Fast 1200mV 0C Model Removal 'nPCI_INTD'
-Slack : -0.607
-TNS   : -0.607
-
-Type  : Fast 1200mV 0C Model Removal 'nPCI_INTA'
-Slack : -0.603
-TNS   : -0.603
-
-Type  : Fast 1200mV 0C Model Removal 'nPCI_INTC'
-Slack : -0.601
-TNS   : -0.601
-
-Type  : Fast 1200mV 0C Model Removal 'PIC_INT'
-Slack : -0.261
-TNS   : -0.261
-
-Type  : Fast 1200mV 0C Model Removal 'E0_INT'
-Slack : 0.109
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'DVI_INT'
-Slack : 0.148
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : 0.560
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 0.568
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : 1.306
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 1.739
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'PIC_INT'
-Slack : -3.000
-TNS   : -5.254
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD'
-Slack : -3.000
-TNS   : -5.059
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB'
-Slack : -3.000
-TNS   : -5.025
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC'
-Slack : -3.000
-TNS   : -5.003
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA'
-Slack : -3.000
-TNS   : -4.993
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'E0_INT'
-Slack : -3.000
-TNS   : -4.216
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'DVI_INT'
-Slack : -3.000
-TNS   : -4.207
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC'
-Slack : -1.000
-TNS   : -1.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 3.538
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 3.563
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 3.567
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 3.568
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 4.773
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]'
-Slack : 7.355
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 10.398
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK'
-Slack : 13.572
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]'
-Slack : 18.964
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]'
-Slack : 30.983
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]'
-Slack : 249.649
-TNS   : 0.000
-
-Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]'
-Slack : 999.914
-TNS   : 0.000
-
-------------------------------------------------------------
diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
deleted file mode 100644
index 4f5907a..0000000
--- a/FPGA_by_Fredi/firebee1.tan.summary
+++ /dev/null
@@ -1,256 +0,0 @@
---------------------------------------------------------------------------------------
-Timing Analyzer Summary
---------------------------------------------------------------------------------------
-
-Type           : Worst-case tsu
-Slack          : -10.689 ns
-Required Time  : 1.000 ns
-Actual Time    : 11.689 ns
-From           : nFB_CS1
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 9930
-
-Type           : Worst-case tco
-Slack          : -14.089 ns
-Required Time  : 1.000 ns
-Actual Time    : 15.089 ns
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1]
-To             : FB_AD[27]
-From Clock     : MAIN_CLK
-To Clock       : --
-Failed Paths   : 7401
-
-Type           : Worst-case tpd
-Slack          : -14.015 ns
-Required Time  : 1.000 ns
-Actual Time    : 15.015 ns
-From           : nFB_CS1
-To             : FB_AD[27]
-From Clock     : --
-To Clock       : --
-Failed Paths   : 546
-
-Type           : Worst-case th
-Slack          : -0.258 ns
-Required Time  : 1.000 ns
-Actual Time    : 1.258 ns
-From           : FB_AD[20]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0~porta_datain_reg0
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 16
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : -17.845 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO
-From Clock     : MAIN_CLK
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 29183
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : -11.412 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0]
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4]
-From Clock     : MAIN_CLK
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 25165
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -6.848 ns
-Required Time  : 25.00 MHz ( period = 39.999 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
-From Clock     : MAIN_CLK
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 5329
-
-Type           : Clock Setup: 'MAIN_CLK'
-Slack          : -6.482 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE.T8
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[0]
-To Clock       : MAIN_CLK
-Failed Paths   : 43303
-
-Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : -6.153 ns
-Required Time  : 96.01 MHz ( period = 10.416 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI
-From Clock     : MAIN_CLK
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 5302
-
-Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : -4.613 ns
-Required Time  : 16.00 MHz ( period = 62.499 ns )
-Actual Time    : N/A
-From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-Failed Paths   : 2876
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : -3.386 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 33
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 2.966 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 5.489 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
-Slack          : 27.221 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.PARITY
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
-From Clock     : MAIN_CLK
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'MAIN_CLK'
-Slack          : -4.871 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4]
-From Clock     : MAIN_CLK
-To Clock       : MAIN_CLK
-Failed Paths   : 764
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -0.116 ns
-Required Time  : 25.00 MHz ( period = 39.999 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 136
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : 0.491 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|a_graycounter_pjc:wrptr_gp|counter11a[0]
-To             : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|altsyncram_fo31:fifo_ram|ram_block12a79~porta_address_reg0
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : 0.500 ns
-Required Time  : 16.00 MHz ( period = 62.499 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
-Slack          : 0.502 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 96.01 MHz ( period = 10.416 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-To             : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 1.812 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : 2.489 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 3.193 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|inst90~_Duplicate_4
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 4.335 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Total number of failed paths
-Slack          : 
-Required Time  : 
-Actual Time    : 
-From           : 
-To             : 
-From Clock     : 
-To Clock       : 
-Failed Paths   : 129984
-
---------------------------------------------------------------------------------------
-
diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws
index 7f27155..9c279dd 100644
--- a/FPGA_by_Fredi/firebeei1.qws
+++ b/FPGA_by_Fredi/firebeei1.qws
@@ -4,13 +4,13 @@ ptn_Child1=Frames
 ptn_Child1=ChildFrames
 [ProjectWorkspace.Frames.ChildFrames]
 ptn_Child1=Document-0
-ptn_Child2=Document-1
-ptn_Child3=Document-2
 [ProjectWorkspace.Frames.ChildFrames.Document-0]
 ptn_Child1=ViewFrame-0
 [ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
-DocPathName=firebee1.bdf
-DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
+DocPathName=blitter.tdf
+DocumentCLSID={5d384c4f-893c-11d1-a087-0020affa43f2}
 IsChildFrameDetached=False
-IsActiveChildFrame=False
+IsActiveChildFrame=True
 ptn_Child1=StateMap
+[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
+AFC_IN_REPORT=False
diff --git a/FPGA_by_Fredi/lpm_counter1_wave0.jpg b/FPGA_by_Fredi/lpm_counter1_wave0.jpg
deleted file mode 100644
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diff --git a/FPGA_by_Fredi/lpm_counter1_waveforms.html b/FPGA_by_Fredi/lpm_counter1_waveforms.html
deleted file mode 100644
index a353967..0000000
--- a/FPGA_by_Fredi/lpm_counter1_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_counter1.tdf" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_counter1.tdf" </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design "lpm_counter1.tdf". The design "lpm_counter1.tdf" is a 12 bit up counter. </P>
-<CENTER><img src=lpm_counter1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing counter operation. </CENTER></P>
-<P><FONT size=3>The output port cout will be asserted at the completion of count sequence. The ports cin and cout are used to chain multiple counters together. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
deleted file mode 100644
index 12ad5c2..0000000
--- a/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd".  The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
-<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions . </P>
-<CENTER><img src=lpm_fifo_dc0_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/serv_req_info.txt b/FPGA_by_Fredi/serv_req_info.txt
new file mode 100644
index 0000000..51a4176
--- /dev/null
+++ b/FPGA_by_Fredi/serv_req_info.txt
@@ -0,0 +1,115 @@
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>VDB</sub_system>
+	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
+	<line>4101</line>
+	<callstack>
+	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
+	</callstack>
+	<error>loc &lt; m_value-&gt;size()</error>
+	<date>Tue Oct 13 17:01:46 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>loc &lt; m_value-&gt;size()
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>VDB</sub_system>
+	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
+	<line>4101</line>
+	<callstack>
+	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
+	</callstack>
+	<error>loc &lt; m_value-&gt;size()</error>
+	<date>Tue Oct 13 17:11:00 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>loc &lt; m_value-&gt;size()
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: GED</error>
+	<date>Wed Oct 14 23:17:06 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: GED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: SFW, STED</error>
+	<date>Thu Oct 15 19:23:19 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: SFW, STED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<callstack>
+	0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
+	</callstack>
+	<error>Current editor: RPW, SFW
+Current dockable window: PJN</error>
+	<date>Fri Oct 16 00:14:03 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 0X1002D196
+Current editor: RPW, SFW
+Current dockable window: PJN
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: SFW</error>
+	<date>Sat Oct 17 19:01:54 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: SFW
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>AFC</sub_system>
+	<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
+	<line>1940</line>
+	<callstack>
+	0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
+	</callstack>
+	<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
+	<date>Mon Oct 19 21:58:36 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
+<internal_error>
+	<executable>quartus.exe</executable>
+	<sub_system>unknown</sub_system>
+	<file>unknown</file>
+	<line>0</line>
+	<error>Current editor: RPW, GED</error>
+	<date>Tue Oct 20 00:53:11 2009</date>
+	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
+	<full_error>Access Violation at 00000000
+Current editor: RPW, GED
+Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
+</internal_error>
+
diff --git a/FPGA_by_Fredi/sopc_builder_log.txt b/FPGA_by_Fredi/sopc_builder_log.txt
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt
new file mode 100644
index 0000000..5c139c4
--- /dev/null
+++ b/FPGA_by_Fredi/undo_redo.txt
@@ -0,0 +1,12 @@
+GED
+
+	Undo Commands
+	     1.	Properties
+	     2.	Move
+	     3.	Paste
+	     4.	Properties
+	     5.	Properties
+	     6.	Move
+	     7.	Paste
+
+

From 3a91813da7931da594df220a713a35cd4f070684 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20G=C3=A1lvez?= <dgalvez75@gmail.com>
Date: Mon, 9 Apr 2018 17:25:52 +0200
Subject: [PATCH 05/16] Sync with Fredi's source 22/06/2017

Blitter work.
---
 FPGA_by_Fredi/DSP/DSP.vhd.bak                 |  79 --
 FPGA_by_Fredi/FPGA_DATE.bsf                   |   2 +-
 FPGA_by_Fredi/FPGA_DATE.tdf                   |  10 +-
 ...d19.tdf => FPGA_DATE_lpm_constant_e19.tdf} |   6 +-
 ...i19.tdf => FPGA_DATE_lpm_constant_f19.tdf} |   6 +-
 FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf  |  30 +
 .../FalconIO_SDCard_IDE_CF.vhd                |  92 ++-
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak    | 202 -----
 .../interrupt_handler.tdf.bak                 | 391 ---------
 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt            |  20 -
 FPGA_by_Fredi/UNUSED                          |  27 -
 .../lpm_ror128.inc}                           |  20 +-
 FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip    |   5 +
 FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf    |  92 +++
 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak           | 659 ---------------
 .../{lpm_fifoDZ.bsf => Doppelzeilen_Fifo.bsf} |   3 +-
 FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc     |  27 +
 FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip     |   5 +
 .../{lpm_fifoDZ.vhd => Doppelzeilen_Fifo.vhd} |  44 +-
 FPGA_by_Fredi/Video/UNUSED                    | 267 ------
 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 480 +++++------
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       | 482 +++++------
 FPGA_by_Fredi/Video/Video.bdf                 | 767 ++++++++++--------
 FPGA_by_Fredi/Video/altdpram0_wave0.jpg       | Bin 125146 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram0_wave1.jpg       | Bin 171723 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram0_waveforms.html  |  16 -
 FPGA_by_Fredi/Video/altdpram1_wave0.jpg       | Bin 151954 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram1_wave1.jpg       | Bin 203609 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram1_waveforms.html  |  16 -
 FPGA_by_Fredi/Video/altdpram2_wave0.jpg       | Bin 152433 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram2_wave1.jpg       | Bin 204342 -> 0 bytes
 FPGA_by_Fredi/Video/altdpram2_waveforms.html  |  16 -
 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg    | Bin 30655 -> 0 bytes
 .../Video/lpm_compare1_waveforms.html         |  13 -
 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg      | Bin 84085 -> 0 bytes
 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html |  13 -
 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg    | Bin 114506 -> 0 bytes
 .../Video/lpm_fifo_dc0_waveforms.html         |  13 -
 FPGA_by_Fredi/Video/shiftreg_dpz.bsf          |  56 ++
 FPGA_by_Fredi/Video/shiftreg_dpz.inc          |  24 +
 .../{lpm_fifoDZ.qip => shiftreg_dpz.qip}      |   8 +-
 FPGA_by_Fredi/Video/shiftreg_dpz.vhd          | 125 +++
 FPGA_by_Fredi/blitter.tdf                     | 532 ++++++------
 FPGA_by_Fredi/blitter.tdf.bak                 | 534 ++++++------
 FPGA_by_Fredi/blitter.tdf.pdf                 | Bin 78291 -> 0 bytes
 FPGA_by_Fredi/firebee1.bdf                    | 192 ++---
 FPGA_by_Fredi/firebee1.done                   |   2 +-
 FPGA_by_Fredi/firebee1.fit.summary            |  16 +
 FPGA_by_Fredi/firebee1.map.summary            |  14 +
 FPGA_by_Fredi/firebee1.qsf                    |  73 +-
 FPGA_by_Fredi/firebee1.rbf                    | Bin 531802 -> 0 bytes
 FPGA_by_Fredi/firebee1.sof                    | Bin 0 -> 1171297 bytes
 FPGA_by_Fredi/firebee1.tan.summary            | 276 +++++++
 FPGA_by_Fredi/firebeei1.qws                   |  16 -
 FPGA_by_Fredi/lpm_mux0.s19                    | 185 -----
 FPGA_by_Fredi/serv_req_info.txt               | 115 ---
 FPGA_by_Fredi/sopc_builder_log.txt            |   0
 FPGA_by_Fredi/undo_redo.txt                   |  12 -
 58 files changed, 2380 insertions(+), 3603 deletions(-)
 delete mode 100644 FPGA_by_Fredi/DSP/DSP.vhd.bak
 rename FPGA_by_Fredi/{FPGA_DATE_lpm_constant_d19.tdf => FPGA_DATE_lpm_constant_e19.tdf} (87%)
 rename FPGA_by_Fredi/{FPGA_DATE_lpm_constant_i19.tdf => FPGA_DATE_lpm_constant_f19.tdf} (87%)
 create mode 100644 FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf
 delete mode 100644 FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
 delete mode 100644 FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
 delete mode 100644 FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
 delete mode 100644 FPGA_by_Fredi/UNUSED
 rename FPGA_by_Fredi/Video/{lpm_fifoDZ.cmp => BLITTER/lpm_ror128.inc} (74%)
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip
 create mode 100644 FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf
 delete mode 100644 FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
 rename FPGA_by_Fredi/Video/{lpm_fifoDZ.bsf => Doppelzeilen_Fifo.bsf} (93%)
 create mode 100644 FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc
 create mode 100644 FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip
 rename FPGA_by_Fredi/Video/{lpm_fifoDZ.vhd => Doppelzeilen_Fifo.vhd} (80%)
 delete mode 100644 FPGA_by_Fredi/Video/UNUSED
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram0_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_wave1.jpg
 delete mode 100644 FPGA_by_Fredi/Video/altdpram2_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
 delete mode 100644 FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
 create mode 100644 FPGA_by_Fredi/Video/shiftreg_dpz.bsf
 create mode 100644 FPGA_by_Fredi/Video/shiftreg_dpz.inc
 rename FPGA_by_Fredi/Video/{lpm_fifoDZ.qip => shiftreg_dpz.qip} (63%)
 create mode 100644 FPGA_by_Fredi/Video/shiftreg_dpz.vhd
 delete mode 100644 FPGA_by_Fredi/blitter.tdf.pdf
 create mode 100644 FPGA_by_Fredi/firebee1.fit.summary
 create mode 100644 FPGA_by_Fredi/firebee1.map.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.rbf
 create mode 100644 FPGA_by_Fredi/firebee1.sof
 create mode 100644 FPGA_by_Fredi/firebee1.tan.summary
 delete mode 100644 FPGA_by_Fredi/firebeei1.qws
 delete mode 100644 FPGA_by_Fredi/lpm_mux0.s19
 delete mode 100644 FPGA_by_Fredi/serv_req_info.txt
 delete mode 100644 FPGA_by_Fredi/sopc_builder_log.txt
 delete mode 100644 FPGA_by_Fredi/undo_redo.txt

diff --git a/FPGA_by_Fredi/DSP/DSP.vhd.bak b/FPGA_by_Fredi/DSP/DSP.vhd.bak
deleted file mode 100644
index 2d4811a..0000000
--- a/FPGA_by_Fredi/DSP/DSP.vhd.bak
+++ /dev/null
@@ -1,79 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2008 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
--- Created on Tue Sep 08 16:24:57 2009
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-
---  Entity Declaration
-
-ENTITY DSP IS
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	PORT
-	(
-		CLK33M : IN STD_LOGIC;
-		MAIN_CLK : IN STD_LOGIC;
-		nFB_OE : IN STD_LOGIC;
-		nFB_WR : IN STD_LOGIC;
-		nFB_CS1 : IN STD_LOGIC;
-		nFB_CS2 : IN STD_LOGIC;
-		FB_SIZE0 : IN STD_LOGIC;
-		FB_SIZE1 : IN STD_LOGIC;
-		nFB_BURST : IN STD_LOGIC;
-		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
-		nRSTO : IN STD_LOGIC;
-		nFB_CS3 : IN STD_LOGIC;
-		nSRCS : OUT STD_LOGIC;
-		nSRBLE : OUT STD_LOGIC;
-		nSRBHE : OUT STD_LOGIC;
-		nSRWE : OUT STD_LOGIC;
-		nSROE : OUT STD_LOGIC;
-		DSP_INT : OUT STD_LOGIC;
-		DSP_TA : OUT STD_LOGIC;
-		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
-		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
-		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
-	);
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-	
-END DSP;
-
-
---  Architecture Body
-
-ARCHITECTURE DSP_architecture OF DSP IS
-
-	
-BEGIN
-	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
-	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
-	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
-	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
-	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
-	DSP_INT <= '0';
-	DSP_TA <= '0';
-	IO(17 downto 0) <= FB_ADR(18 downto 1);
-	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
-	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
-	
-	
-END DSP_architecture;
diff --git a/FPGA_by_Fredi/FPGA_DATE.bsf b/FPGA_by_Fredi/FPGA_DATE.bsf
index a6c809a..44e6599 100644
--- a/FPGA_by_Fredi/FPGA_DATE.bsf
+++ b/FPGA_by_Fredi/FPGA_DATE.bsf
@@ -31,7 +31,7 @@ applicable agreement for further details.
 		(line (pt 88 24)(pt 72 24)(line_width 3))
 	)
 	(drawing
-		(text "402923543" (rect 27 18 72 30)(font "Arial" ))
+		(text "570826775" (rect 27 18 72 30)(font "Arial" ))
 		(text "32" (rect 77 25 87 37)(font "Arial" ))
 		(line (pt 16 16)(pt 72 16)(line_width 1))
 		(line (pt 72 16)(pt 72 32)(line_width 1))
diff --git a/FPGA_by_Fredi/FPGA_DATE.tdf b/FPGA_by_Fredi/FPGA_DATE.tdf
index 49f319c..5a3bc40 100644
--- a/FPGA_by_Fredi/FPGA_DATE.tdf
+++ b/FPGA_by_Fredi/FPGA_DATE.tdf
@@ -33,7 +33,7 @@
 --applicable agreement for further details.
 
 -- Clearbox generated function header
-FUNCTION FPGA_DATE_lpm_constant_i19 ()
+FUNCTION FPGA_DATE_lpm_constant_f19 ()
 RETURNS ( result[31..0]);
 
 
@@ -46,11 +46,11 @@ SUBDESIGN FPGA_DATE
 
 VARIABLE
 
-	FPGA_DATE_lpm_constant_i19_component : FPGA_DATE_lpm_constant_i19;
+	FPGA_DATE_lpm_constant_f19_component : FPGA_DATE_lpm_constant_f19;
 
 BEGIN
 
-	result[31..0] = FPGA_DATE_lpm_constant_i19_component.result[31..0];
+	result[31..0] = FPGA_DATE_lpm_constant_f19_component.result[31..0];
 END;
 
 
@@ -63,9 +63,9 @@ END;
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: Radix NUMERIC "16"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "402923543"
+-- Retrieval info: PRIVATE: Value NUMERIC "570826775"
 -- Retrieval info: PRIVATE: nBit NUMERIC "32"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "402923543"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "570826775"
 -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
similarity index 87%
rename from FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf
rename to FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
index a611f11..de971cf 100644
--- a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_d19.tdf
+++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf
@@ -1,4 +1,4 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=13042017 LPM_WIDTH=32 result
+--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=21062017 LPM_WIDTH=32 result
 --VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
 
 
@@ -19,12 +19,12 @@
 
 
 --synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_d19
+SUBDESIGN FPGA_DATE_lpm_constant_e19
 ( 
 	result[31..0]	:	output;
 ) 
 
 BEGIN 
-	result[] = B"00010011000001000010000000010111";
+	result[] = B"00100001000001100010000000010111";
 END;
 --VALID FILE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
similarity index 87%
rename from FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf
rename to FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
index 4ae1da6..025fbc8 100644
--- a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf
+++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf
@@ -1,4 +1,4 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=18042017 LPM_WIDTH=32 result
+--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=22062017 LPM_WIDTH=32 result
 --VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
 
 
@@ -19,12 +19,12 @@
 
 
 --synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_i19
+SUBDESIGN FPGA_DATE_lpm_constant_f19
 ( 
 	result[31..0]	:	output;
 ) 
 
 BEGIN 
-	result[] = B"00011000000001000010000000010111";
+	result[] = B"00100010000001100010000000010111";
 END;
 --VALID FILE
diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf
new file mode 100644
index 0000000..55f9ec1
--- /dev/null
+++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf
@@ -0,0 +1,30 @@
+--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=05062017 LPM_WIDTH=32 result
+--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN FPGA_DATE_lpm_constant_g19
+( 
+	result[31..0]	:	output;
+) 
+
+BEGIN 
+	result[] = B"00000101000001100010000000010111";
+END;
+--VALID FILE
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
index 31728ca..7e5d3c9 100644
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
@@ -184,10 +184,14 @@ signal TDO						: STD_LOGIC;
 signal SNDCS					: STD_LOGIC;
 signal SNDCS_I					: STD_LOGIC;
 signal SNDIR_I					: STD_LOGIC;
-signal LP_DIR_X					: STD_LOGIC;
 signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
 signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
-signal nLP_STR					: STD_LOGIC;
+signal LP_STR_X					: STD_LOGIC;
+signal LP_STR_NS1				: STD_LOGIC;
+signal LP_STR_NS0				: STD_LOGIC;
+signal LP_DIR_X					: STD_LOGIC;
+signal LP_DIR_NS1				: STD_LOGIC;
+signal LP_DIR_NS0				: STD_LOGIC;
 -- DMA SOUND
 signal dma_snd_cs				: STD_LOGIC;
 signal sndmactl					: STD_LOGIC_VECTOR(7 downto 0);
@@ -298,8 +302,7 @@ FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
 FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
 				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_TA = '1' else '0';	--SNDCS = '1' or 
 SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE
-           '1' when IDE_CF_CS = '1' ELSE
-           '1' when   nFB_CS3 = '0' ELSE '0';
+           '1' when IDE_CF_CS = '1' ELSE '0';					-- DARF NICHT AKTIV SEIN BEI ZUGRIFF AUF DRIVE 0 UND 1 DA KOMMEN DIE DATEN DIREKT VOM FPGA
 nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
 nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
 
@@ -325,6 +328,22 @@ SD_CDM_D1 <= 'Z';
 ----------------------------------------------------------------------------
 -- IDE
 ----------------------------------------------------------------------------
+IDE_RES <= not ACP_CONF(25) and nRSTO; 	-- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO 
+IDE_CF_CS  	<= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 7) = x"1E000"  else '0';		-- FFF0'0000-FFF0'007F
+IDE_DRIVE0 	<= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F00099" else '0';		-- FFF0'0099 (19+80!)
+IDE_DRIVE1 	<= '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 0) = x"F000D9" else '0';		-- FFF0'00D9 (19+40+80!)
+IDE_DCS    	<= '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else 							-- FFF0'000x 0-3
+               '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0000" else			-- FFF0'000x 0-3
+			   '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else 							-- FFF0'004x 0-3
+               '1' when (nFB_CS1 = '0' OR nFB_CS3 = '0') and FB_ADR(23 downto 2) = x"3C0010" else '0';		-- FFF0'004x 0-3
+nCF_CS0    <=     FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 									-- xxxx'xx00-1F
+nCF_CS1    <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 									-- xxxx'xx20-3F
+nIDE_CS0   <=     FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 									-- xxxx'xx40-5F
+nIDE_CS1   <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 									-- xxxx'xx60-7F
+nDREQ0 <= '1';
+FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
+FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
+
 CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
 	begin
 		if nRSTO = '0' then
@@ -336,7 +355,7 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
 			end if;
 	end process CMD_REG;
 
-	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY)
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, nIDE_RD, nIDE_WR, IDE_RDY,IDE_DCS, IDE_CF_CS, FB_ADR, ACP_CONF, nFB_WR, FB_SIZE0, FB_SIZE1)
 	begin
 		case CMD_STATE is
 			when IDLE =>
@@ -453,23 +472,6 @@ CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
 				end if;
 		end case;
 	end process CMD_DECODER;
-	
-IDE_RES <= not ACP_CONF(25) and nRSTO; 	-- !!!!ACHTUNG: RESET wenn 0!!!!!!!!!!!!!!! -- IDE_RES manuel oder weil nRSTO 
-IDE_CF_CS  	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';		-- FFF0'0000-FFF0'007F
-IDE_DRIVE0 	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"99" else '0';		-- FFF0'0099 (19+80!)
-IDE_DRIVE1 	<= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 0) = x"D9" else '0';		-- FFF0'00D9 (19+40+80!)
-IDE_DCS    	<= '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0000" else 	-- FFF0'000x 0-3
-               '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"0" else			-- FFF0'000x 0-3
-			   '1' when  FB_ALE = '1' and FB_ADR(31 downto 2) = x"3FFC0010" else 	-- FFF0'004x 0-3
-               '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"10" else '0';		-- FFF0'004x 0-3
-nCF_CS0    <=     FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 			-- xxxx'xx00-1F
-nCF_CS1    <= not FB_ADR(5) or (FB_ADR(6) xor (ACP_CONF(31) xnor HD_DD)); 			-- xxxx'xx20-3F
-nIDE_CS0   <=     FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 			-- xxxx'xx40-5F
-nIDE_CS1   <= not FB_ADR(5) or (FB_ADR(6) xnor (ACP_CONF(30) xnor HD_DD)); 			-- xxxx'xx60-7F
-nDREQ0 <= '1';
-FB_AD(23 downto 20) <= ACP_CONF(19 downto 16) when IDE_DRIVE0 = '1' and nFB_OE = '0' else "ZZZZ";
-FB_AD(23 downto 20) <= ACP_CONF(23 downto 20) when IDE_DRIVE1 = '1' and nFB_OE = '0' else "ZZZZ";
-
 -----------------------------------------------------------------------------------------------------------------------------------------
 -- ACSI, SCSI UND FLOPPY WD1772 
 -------------------------------------------------------------------------------------------------------------------------------------------
@@ -915,7 +917,7 @@ KEYB_RxD <= '0' when AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' else '1';				-- TAST
 FB_AD(31 downto 24) <= DATA_OUT_ACIA_I  when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else  
 					   DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
 -- AMKB_TX: SPIKES AUSFILTERN  und sychronisieren ------------------------------------------
-	process(CLK2M, AMKB_RX, AMKB_REG)
+	process(CLK2M, AMKB_RX, AMKB_TX, AMKB_REG, CLK500k)
 	begin
 		if rising_edge(CLK500k) then
 			AMKB_TX <= AMKB_TX_sync;
@@ -995,7 +997,7 @@ MIDI_OLR <= MIDI_OUT;
 			GPIP_IN(3)			=> BLITTER_INT OR DSP_INT,
 			GPIP_IN(2)			=> not CTS,
 			GPIP_IN(1)			=> not DCD,
-			GPIP_IN(0)			=> LP_BUSY,
+			GPIP_IN(0)			=> LP_BUSY XOR ACP_CONF(1),
 			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
 			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
 			-- Interrupt control:
@@ -1032,7 +1034,8 @@ FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
 DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
          '0' when FDINT = '1' else
          '0' when SCSI_INT = '1' AND ACP_CONF(27) = '1' else '1';
- ----------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
 -- Sound
 ----------------------------------------------------------------------------
  	I_SOUND: WF2149IP_TOP_SOC
@@ -1054,8 +1057,8 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
 
 			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
 			IO_A_OUT(7)			=> nnIDE_RES,
-            IO_A_OUT(6)			=> LP_DIR_X,
-			IO_A_OUT(5)			=> nLP_STR,
+            IO_A_OUT(6)			=> LP_DIR_NS0,
+			IO_A_OUT(5)			=> LP_STR_NS0, 
 			IO_A_OUT(4)			=> DTR,
 			IO_A_OUT(3)			=> RTS,
 --			IO_A_OUT(2)			=> FDD_D1SEL,
@@ -1075,17 +1078,38 @@ SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		--
 SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
 SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
 FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
-LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
-LP_DIR <= LP_DIR_X;
-LP_STR <= not nLP_STR;
-
+LP_D <= LP_D_X when (LP_DIR_X = '0' OR ACP_CONF(2) = '0') else "ZZZZZZZZ";
+LP_STR <= LP_STR_X XOR ACP_CONF(0);
+LP_DIR <= LP_DIR_X XOR ACP_CONF(3);
+-- spikes weg ------------------------------------------
+	process(CLK2M,LP_STR_NS1,LP_STR_NS0,LP_STR_X)
+	begin
+		if rising_edge(CLK2M) then
+				LP_STR_X   <= (LP_STR_NS1 AND LP_STR_NS0) OR (LP_STR_X AND LP_STR_NS1);
+				LP_STR_NS1 <=  LP_STR_NS0; 
+			else
+				LP_STR_X   <=  LP_STR_X;
+				LP_STR_NS1 <=  LP_STR_NS1;
+			end if;
+	END PROCESS;
+	
+	process(CLK2M,LP_DIR_NS1,LP_DIR_NS0,LP_DIR_X)
+	begin
+		if rising_edge(CLK2M) then
+				LP_DIR_X   <= (LP_DIR_NS1 AND LP_DIR_NS0) OR (LP_DIR_X AND LP_DIR_NS1);
+				LP_DIR_NS1 <=  LP_DIR_NS0; 
+			else
+				LP_DIR_X   <=  LP_DIR_X;
+				LP_DIR_NS1 <=  LP_DIR_NS1;
+			end if;
+	END PROCESS;
 ----------------------------------------------------------------------------
 -- DMA Sound register
 ----------------------------------------------------------------------------
 
 dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';	-- F8900-F893F
 
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, nFB_WR, FB_B1, sndmactl)
 	begin
 		if nRSTO = '0' THEN
 			sndmactl <= x"00";
@@ -1097,7 +1121,7 @@ dma_snd_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E24" else '0';
 	END PROCESS;
 FB_AD(23 downto 16) <= sndmactl when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZ";
 
-	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs)
+	process(nRSTO,MAIN_CLK,FB_ADR(5 downto 1), dma_snd_cs, sndbashi)
 	begin
 		if nRSTO = '0' THEN
 			sndbashi <= x"00";
@@ -1220,7 +1244,6 @@ FB_AD(23 downto 16) <= sndmode when dma_snd_cs = '1' and FB_ADR(5 downto 1) = x"
 ----------------------------------------------------------------------------
 -- Paddle
 ----------------------------------------------------------------------------
-
 paddle_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3E48" else '0';	-- F9200-F923F
 
 FB_AD(31 downto 16) <= x"bfff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"0" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
@@ -1232,4 +1255,5 @@ FB_AD(31 downto 16) <= x"ffff" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"B
 FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"10" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
 FB_AD(31 downto 16) <= x"0000" when paddle_cs = '1' and FB_ADR(5 downto 1) = x"11" and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
 
+--****************************************************************
 END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
deleted file mode 100644
index e7c6ae6..0000000
--- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
+++ /dev/null
@@ -1,202 +0,0 @@
--- megafunction wizard: %LPM_FIFO+%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: dcfifo_mixed_widths 
-
--- ============================================================
--- File Name: dcfifo1.vhd
--- Megafunction Name(s):
--- 			dcfifo_mixed_widths
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 222 10/21/2009 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2009 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY dcfifo1 IS
-	PORT
-	(
-		aclr		: IN STD_LOGIC  := '0';
-		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
-		rdclk		: IN STD_LOGIC ;
-		rdreq		: IN STD_LOGIC ;
-		wrclk		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-		wrusedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
-	);
-END dcfifo1;
-
-
-ARCHITECTURE SYN OF dcfifo1 IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
-
-
-
-	COMPONENT dcfifo_mixed_widths
-	GENERIC (
-		intended_device_family		: STRING;
-		lpm_numwords		: NATURAL;
-		lpm_showahead		: STRING;
-		lpm_type		: STRING;
-		lpm_width		: NATURAL;
-		lpm_widthu		: NATURAL;
-		lpm_widthu_r		: NATURAL;
-		lpm_width_r		: NATURAL;
-		overflow_checking		: STRING;
-		rdsync_delaypipe		: NATURAL;
-		underflow_checking		: STRING;
-		use_eab		: STRING;
-		write_aclr_synch		: STRING;
-		wrsync_delaypipe		: NATURAL
-	);
-	PORT (
-			wrclk	: IN STD_LOGIC ;
-			rdreq	: IN STD_LOGIC ;
-			wrusedw	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
-			aclr	: IN STD_LOGIC ;
-			rdclk	: IN STD_LOGIC ;
-			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-			wrreq	: IN STD_LOGIC ;
-			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	wrusedw    <= sub_wire0(3 DOWNTO 0);
-	q    <= sub_wire1(7 DOWNTO 0);
-
-	dcfifo_mixed_widths_component : dcfifo_mixed_widths
-	GENERIC MAP (
-		intended_device_family => "Cyclone III",
-		lpm_numwords => 16,
-		lpm_showahead => "OFF",
-		lpm_type => "dcfifo",
-		lpm_width => 16,
-		lpm_widthu => 4,
-		lpm_widthu_r => 5,
-		lpm_width_r => 8,
-		overflow_checking => "ON",
-		rdsync_delaypipe => 5,
-		underflow_checking => "ON",
-		use_eab => "ON",
-		write_aclr_synch => "OFF",
-		wrsync_delaypipe => 5
-	)
-	PORT MAP (
-		wrclk => wrclk,
-		rdreq => rdreq,
-		aclr => aclr,
-		rdclk => rdclk,
-		wrreq => wrreq,
-		data => data,
-		wrusedw => sub_wire0,
-		q => sub_wire1
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
--- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
--- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "4"
--- Retrieval info: PRIVATE: Depth NUMERIC "16"
--- Retrieval info: PRIVATE: Empty NUMERIC "1"
--- Retrieval info: PRIVATE: Full NUMERIC "1"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
--- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
--- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: Optimize NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
--- Retrieval info: PRIVATE: UsedW NUMERIC "1"
--- Retrieval info: PRIVATE: Width NUMERIC "16"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
--- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
--- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
--- Retrieval info: PRIVATE: output_width NUMERIC "8"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: rsFull NUMERIC "0"
--- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
--- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
--- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
--- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "0"
--- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
--- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
--- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
--- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
--- Retrieval info: CONSTANT: USE_EAB STRING "ON"
--- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
--- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
--- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
--- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
--- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
--- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
--- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
--- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
--- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
--- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
--- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
--- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
--- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
--- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
--- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
--- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
--- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
deleted file mode 100644
index 7e4aa32..0000000
--- a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak
+++ /dev/null
@@ -1,391 +0,0 @@
-TITLE "INTERRUPT HANDLER UND C1287";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_LONG.inc";
-INCLUDE "lpm_bustri_BYT.inc";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN interrupt_handler
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	MAIN_CLK : INPUT;
-	nFB_WR : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	FB_ADR[31..0] : INPUT;
-	FPGA_DATE[31..0] : INPUT;
-	PIC_INT : INPUT;
-	E0_INT : INPUT;
-	DVI_INT : INPUT;
-	nPCI_INTA : INPUT;
-	nPCI_INTB : INPUT;
-	nPCI_INTC : INPUT;
-	nPCI_INTD : INPUT;
-	nMFP_INT : INPUT;
-	nFB_OE : INPUT;
-	DSP_INT : INPUT;
-	VSYNC : INPUT;
-	HSYNC : INPUT;
-	DMA_DRQ : INPUT;
-	nRSTO : INPUT;
-	nIRQ[7..2] : OUTPUT;
-	INT_HANDLER_TA : OUTPUT;
-	ACP_CONF[31..0] : OUTPUT;
-	TIN0 : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_B[3..0]				:NODE;
-	INT_CTR[31..0]			:DFFE;
-	INT_CTR_CS				:NODE;
-	INT_LATCH[31..0]		:DFF;
-	INT_LATCH_CS			:NODE;
-	INT_CLEAR[31..0]		:DFF;
-	INT_CLEAR_CS			:NODE;
-	INT_IN[31..0]			:NODE;
-	INT_ENA[31..0]			:DFFE;
-	INT_ENA_CS				:NODE;
-	INT_L[9..0]				:DFF;
-	INT_LA[9..0][3..0]		:DFF;
-	ACP_CONF[31..0]			:DFFE;
-	ACP_CONF_CS				:NODE;
-	FPGA_DATE_CS			:NODE;
-	PSEUDO_BUS_ERROR		:NODE;
-	UHR_AS					:NODE;
-	UHR_DS					:NODE;
-	RTC_ADR[5..0]			:DFFE;
-	ACHTELSEKUNDEN[2..0]	:DFFE;
-	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
-	PIC_INT_SYNC[2..0]		:DFF;
-	INC_SEC					:NODE;
-	INC_MIN					:NODE;
-	INC_STD					:NODE;
-	INC_TAG					:NODE;
-	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
-	WINTERZEIT				:NODE;
-	SOMMERZEIT				:NODE;
-	INC_MONAT				:NODE;
-	INC_JAHR				:NODE;
-	UPDATE_ON				:NODE;
-	
-BEGIN
--- BYT SELECT
-	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
-		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
-		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
-		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
-		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
-		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
-
--- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
-	INT_CTR[].CLK = MAIN_CLK;
-	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
-	INT_CTR[] = FB_AD[];
-	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
-	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
-	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
-	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
--- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
-	INT_ENA[].CLK = MAIN_CLK;
-	INT_ENA[].CLRN = nRSTO;
-	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
-	INT_ENA[] = FB_AD[];
-	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
-	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
-	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
-	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
--- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
-	INT_CLEAR[].CLK = MAIN_CLK;
-	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
-	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
-	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
-	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
-	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
--- INTERRUPT LATCH REGISTER READ ONLY
-	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
--- INTERRUPT
-	!nIRQ2 = HSYNC 						& INT_ENA[26];
-	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
-	!nIRQ4 = VSYNC 						& INT_ENA[28];
-	!nIRQ5 = INT_LATCH[]!=H"00000000" 	& INT_ENA[29];
-	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
-	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
-
-PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
-							#  FB_ADR[19..4]==H"F8E0"			-- VME
---							#  FB_ADR[19..4]==H"F920"			-- PADDLE
---							#  FB_ADR[19..4]==H"F921"			-- PADDLE
---							#  FB_ADR[19..4]==H"F922"			-- PADDLE
-							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
-							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
-							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
-							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
-							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
-							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
-							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
---							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
---							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
---							#  FB_ADR[19..4]==H"F892"			-- DMA SOUND
-							 );
--- IF VIDEO ADR CHANGE
-TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-
--- INTERRUPT LATCH
-	INT_L[].CLK = MAIN_CLK;
-	INT_L[].CLRN = nRSTO;
-	INT_L0 = PIC_INT & INT_ENA[0];
-	INT_L1 = E0_INT & INT_ENA[1];
-	INT_L2 = DVI_INT & INT_ENA[2];
-	INT_L3 = !nPCI_INTA & INT_ENA[3];
-	INT_L4 = !nPCI_INTB & INT_ENA[4];
-	INT_L5 = !nPCI_INTC & INT_ENA[5];
-	INT_L6 = !nPCI_INTD & INT_ENA[6];
-	INT_L7 = DSP_INT & INT_ENA[7];
-	INT_L8 = VSYNC & INT_ENA[8];
-	INT_L9 = HSYNC & INT_ENA[9];
-	
-	INT_LA[][].CLK = MAIN_CLK;
-	INT_LATCH[] = H"FFFFFFFF";
-	INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
-	FOR I IN 0 TO 9 GENERATE
-		INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
-		INT_LA[I][] = INT_LA[I][]+1 &  INT_L[I] & INT_LA[I][]<7 
-		            # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
-		            # 15            &  INT_L[I] & INT_LA[I][]>6
-		            # 0             & !INT_L[I] & INT_LA[I][]<9;
-		INT_LATCH[I].CLK = INT_LA[I][3];
-	END GENERATE;
-	
--- INT_IN
-	INT_IN0 = PIC_INT;
-	INT_IN1 = E0_INT;
-	INT_IN2 = DVI_INT;
-	INT_IN3 = !nPCI_INTA;
-	INT_IN4 = !nPCI_INTB;
-	INT_IN5 = !nPCI_INTC;
-	INT_IN6 = !nPCI_INTD;
-	INT_IN7 = DSP_INT;
-	INT_IN8 = VSYNC;
-	INT_IN9 = HSYNC;
-	INT_IN[25..10] = H"0";
-	INT_IN26 = HSYNC; 
-	INT_IN27 = INT_CTR0; 
-	INT_IN28 = VSYNC; 
-	INT_IN29 = INT_LATCH[]!=H"00000000";
-	INT_IN30 = !nMFP_INT; 
-	INT_IN31 = DMA_DRQ; 
---***************************************************************************************
--- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
-	ACP_CONF[].CLK = MAIN_CLK;
-	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
-	ACP_CONF[] = FB_AD[];
-	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
-	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
-	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
-	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
---***************************************************************************************
--- FPGA DATE HEX (ddmmyyyy)
-	FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040";		-- $4'0000/4
---***************************************************************************************
-	
---------------------------------------------------------------	
--- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
-----------------------------------------------------------
-	RTC_ADR[].CLK = MAIN_CLK;
-	RTC_ADR[] = FB_AD[21..16];
-	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
-	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
-	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
-	WERTE[][].CLK = MAIN_CLK;
-	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
-	WERTE[7..0][1] = FB_AD[23..16];
-	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
-	WERTE[7..0][3] = FB_AD[23..16];
-	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
-	WERTE[7..0][5] = FB_AD[23..16];
-	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
-	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
-	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
-	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
-	FOR I IN 10 TO 63 GENERATE
-		WERTE[7..0][I] = FB_AD[23..16];
-	END GENERATE;
-	FOR I IN 0 TO 63 GENERATE
-		WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
-	END GENERATE;
-	PIC_INT_SYNC[].CLK = MAIN_CLK;	
-	PIC_INT_SYNC[0] = PIC_INT;
-	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
-	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
-	UPDATE_ON = !WERTE[7][11];		
-	WERTE[6][10].CLRN = GND;	-- KEIN UIP
-	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
-	WERTE[2][11] = VCC;	-- IMMER BINARY
-	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
-	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
-	WERTE[7][13] = VCC;	-- IMMER RICHTIG
--- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
-	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
-	WERTE[0][13] = SOMMERZEIT;
-	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
-	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
--- ACHTELSEKUNDEN
-	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
-	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
-	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
--- SEKUNDEN
-	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
-	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
-	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
--- MINUTEN
-	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
-	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
-	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
--- STUNDEN
-	INC_STD = INC_MIN & WERTE[][2]==59;							  
-	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
-	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
--- WOCHENTAG UND TAG 
-	INC_TAG = INC_STD & WERTE[][2]==23;						
-	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
-			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
-	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
-	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
-							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
-							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
-							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
-	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
-			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
-	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
--- MONATE
-	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
-	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
-			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
-	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
--- JAHR		   
-	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
-	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
-	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
--- TRISTATE OUTPUT
-
-	FB_AD[31..24] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[31..24] 
-				  #	INT_ENA_CS   & INT_ENA[31..24]
-				  #	INT_LATCH_CS & INT_LATCH[31..24]
-				  # INT_CLEAR_CS & INT_IN[31..24]
-				  # ACP_CONF_CS  & ACP_CONF[31..24]
-				  # FPGA_DATE_CS  & FPGA_DATE[31..24]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[23..16] = lpm_bustri_BYT(
-				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
-				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
-				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
-				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
-				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
-				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
-				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
-				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
-				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
-				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
-				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
-				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
-				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
-				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
-				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
-				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
-				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
-				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
-				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
-				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
-				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
-				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
-				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
-				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
-				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
-				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
-				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
-				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
-				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
-				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
-				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
-				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
-				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
-				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
-				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
-				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
-				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
-				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
-				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
-				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
-				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
-				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
-				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
-				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
-				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
-				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
-				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
-				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
-				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
-				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
-				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
-				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
-				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
-				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
-				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
-				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
-				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
-				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
-				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
-				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
-				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
-				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
-				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
-				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
-				 # (0,RTC_ADR[])			   & UHR_AS
-				 # INT_CTR_CS   & INT_CTR[23..16] 
-				 # INT_ENA_CS   & INT_ENA[23..16]
-				 # INT_LATCH_CS & INT_LATCH[23..16]
-				 # INT_CLEAR_CS & INT_IN[23..16]
-				 # ACP_CONF_CS  & ACP_CONF[23..16]
-				 # FPGA_DATE_CS  & FPGA_DATE[23..16]
-				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[15..8] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[15..8] 
-				  #	INT_ENA_CS   & INT_ENA[15..8]
-				  #	INT_LATCH_CS & INT_LATCH[15..8]
-				  # INT_CLEAR_CS & INT_IN[15..8]
-				  # ACP_CONF_CS  & ACP_CONF[15..8]
-				  # FPGA_DATE_CS  & FPGA_DATE[15..8]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-	FB_AD[7..0] = lpm_bustri_BYT(
-					INT_CTR_CS   & INT_CTR[7..0] 
-				  #	INT_ENA_CS   & INT_ENA[7..0]
-				  #	INT_LATCH_CS & INT_LATCH[7..0]
-				  # INT_CLEAR_CS & INT_IN[7..0]
-				  # ACP_CONF_CS  & ACP_CONF[7..0]
-				  # FPGA_DATE_CS  & FPGA_DATE[7..0]
-				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
-
-	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
-END;
-
-
diff --git a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
deleted file mode 100644
index 797d4f8..0000000
--- a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-PLL_Name	altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
-PLLJITTER	36
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
-PLLJITTER	43
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
-PLLJITTER	NA
-PLLSPEmax	84
-PLLSPEmin	-53
-
-PLL_Name	altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
-PLLJITTER	31
-PLLSPEmax	84
-PLLSPEmin	-53
-
diff --git a/FPGA_by_Fredi/UNUSED b/FPGA_by_Fredi/UNUSED
deleted file mode 100644
index 3a7d9e6..0000000
--- a/FPGA_by_Fredi/UNUSED
+++ /dev/null
@@ -1,27 +0,0 @@
-
--- Clearbox generated Memory Initialization File (.mif)
-
-WIDTH=3;
-DEPTH=16;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	00  :   7;
-	01  :   6;
-	02  :   5;
-	03  :   4;
-	04  :   3;
-	05  :   2;
-	06  :   1;
-	07  :   0;
-	08  :   7;
-	09  :   6;
-	0a  :   5;
-	0b  :   4;
-	0c  :   3;
-	0d  :   2;
-	0e  :   1;
-	0f  :   0;
-END;
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.cmp b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.inc
similarity index 74%
rename from FPGA_by_Fredi/Video/lpm_fifoDZ.cmp
rename to FPGA_by_Fredi/Video/BLITTER/lpm_ror128.inc
index 153e7c2..5e2f10d 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.cmp
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.inc
@@ -13,14 +13,12 @@
 --applicable agreement for further details.
 
 
-component lpm_fifoDZ
-	PORT
-	(
-		aclr		: IN STD_LOGIC ;
-		clock		: IN STD_LOGIC ;
-		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
-		rdreq		: IN STD_LOGIC ;
-		wrreq		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
-	);
-end component;
+FUNCTION lpm_ror128 
+(
+	data[127..0],
+	distance[6..0]
+)
+
+RETURNS (
+	result[127..0]
+);
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip
new file mode 100644
index 0000000..0e3bd1b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ror128.cmp"]
diff --git a/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf
new file mode 100644
index 0000000..4c6928a
--- /dev/null
+++ b/FPGA_by_Fredi/Video/BLITTER/lpm_ror128.tdf
@@ -0,0 +1,92 @@
+-- megafunction wizard: %LPM_CLSHIFT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_clshift 
+
+-- ============================================================
+-- File Name: lpm_ror128.tdf
+-- Megafunction Name(s):
+-- 			lpm_clshift
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "lpm_clshift.inc";
+
+
+
+SUBDESIGN lpm_ror128
+(
+	data[127..0]	 : INPUT;
+	distance[6..0]	 : INPUT;
+	result[127..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	lpm_clshift_component : lpm_clshift WITH (
+			LPM_SHIFTTYPE = "ROTATE",
+			LPM_TYPE = "LPM_CLSHIFT",
+			LPM_WIDTH = 128,
+			LPM_WIDTHDIST = 7
+			);
+
+BEGIN
+
+	result[127..0] = lpm_clshift_component.result[127..0];
+	lpm_clshift_component.distance[6..0] = distance[6..0];
+	lpm_clshift_component.direction = VCC;
+	lpm_clshift_component.data[127..0] = data[127..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "2"
+-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
+-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
+-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
+-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "ROTATE"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ror128_inst.tdf FALSE
diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
deleted file mode 100644
index c688f97..0000000
--- a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak
+++ /dev/null
@@ -1,659 +0,0 @@
-TITLE "DDR_CTR";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_BYT.inc";
-
--- FIFO WATER MARK
-CONSTANT FIFO_LWM = 0;
-CONSTANT FIFO_MWM = 1000;
-CONSTANT FIFO_HWM = 2000;
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN DDR_CTR
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	DDR_SYNC_66M : INPUT;
-	CLR_FIFO : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ADR[31..0] : INPUT;
-	BLITTER_SIG : INPUT;
-	BLITTER_WR : INPUT;
-	DDRCLK0 : INPUT;
-	CLK33M : INPUT;
-	FIFO_MW[10..0] : INPUT;
-	VA[12..0] : OUTPUT;
-	nVWE : OUTPUT;
-	nVRAS : OUTPUT;
-	nVCS : OUTPUT;
-	VCKE : OUTPUT;
-	nVCAS : OUTPUT;
-	FB_LE[3..0] : OUTPUT;
-	FB_VDOE[3..0] : OUTPUT;
-	SR_FIFO_WRE : OUTPUT;
-	SR_DDR_FB : OUTPUT;
-	SR_DDR_WR : OUTPUT;
-	SR_DDRWR_D_SEL : OUTPUT;
-	SR_VDMP[7..0] : OUTPUT;
-	VIDEO_DDR_TA : OUTPUT;
-	SR_BLITTER_DACK : OUTPUT;
-	BA[1..0] : OUTPUT;
-	DDRWR_D_SEL1 : OUTPUT;
-	VDM_SEL[3..0] : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
-	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
-													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
-												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
-												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
-												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
-																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
-												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
-	LINE					:NODE;
-	FB_B[3..0]				:NODE;
-	VCAS					:NODE;
-	VRAS					:NODE;
-	VWE						:NODE;
-	VA_P[12..0]				:DFF;
-	BA_P[1..0]				:DFF;
-	VA_S[12..0]				:DFF;
-	BA_S[1..0]				:DFF;
-	MCS[1..0]				:DFF;
-	CPU_DDR_SYNC			:DFF;
-	DDR_SEL					:NODE;
-	DDR_CS					:DFFE;
-	DDR_CONFIG				:NODE;
-	SR_DDR_WR				:DFF;
-	SR_DDRWR_D_SEL			:DFF;
-	SR_VDMP[7..0] 			:DFF;
-	CPU_ROW_ADR[12..0]		:NODE;
-	CPU_BA[1..0]			:NODE;
-	CPU_COL_ADR[9..0]		:NODE;
-	CPU_SIG					:NODE;
-	CPU_REQ					:DFF;
-	CPU_AC					:DFF;
-	BUS_CYC					:DFF;
-	BUS_CYC_END				:NODE;
-	BLITTER_REQ				:DFF;
-	BLITTER_AC				:DFF;
-	BLITTER_ROW_ADR[12..0]	:NODE;
-	BLITTER_BA[1..0]		:NODE;
-	BLITTER_COL_ADR[9..0]	:NODE;
-	FIFO_REQ				:DFF;
-	FIFO_AC					:DFF;
-	FIFO_ROW_ADR[12..0]		:NODE;
-	FIFO_BA[1..0]			:NODE;
-	FIFO_COL_ADR[9..0]		:NODE;
-	FIFO_ACTIVE				:NODE;
-	CLR_FIFO_SYNC			:DFF;
-	CLEAR_FIFO_CNT			:DFF;
-	STOP					:DFF;
-	SR_FIFO_WRE				:DFF;
-	FIFO_BANK_OK			:DFF;
-	FIFO_BANK_NOT_OK		:NODE;
-	DDR_REFRESH_ON			:NODE;
-	DDR_REFRESH_CNT[10..0]	:DFF;
-	DDR_REFRESH_REQ			:DFF;
-	DDR_REFRESH_SIG[3..0]	:DFFE;
-	REFRESH_TIME			:DFF;
-	VIDEO_BASE_L_D[7..0]	:DFFE;
-	VIDEO_BASE_L			:NODE;
-	VIDEO_BASE_M_D[7..0]	:DFFE;
-	VIDEO_BASE_M			:NODE;
-	VIDEO_BASE_H_D[7..0]	:DFFE;
-	VIDEO_BASE_H			:NODE;
-	VIDEO_BASE_X_D[2..0]	:DFFE;
-	VIDEO_ADR_CNT[22..0]	:DFFE;
-	VIDEO_CNT_L				:NODE;
-	VIDEO_CNT_M				:NODE;
-	VIDEO_CNT_H				:NODE;
-	VIDEO_BASE_ADR[22..0]	:NODE;
-	VIDEO_ACT_ADR[26..0]	:NODE;
-	
-BEGIN
-	LINE =  FB_SIZE0 &  FB_SIZE1;
--- BYT SELECT
-	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
-	FB_REGDDR.CLK = MAIN_CLK;
-	CASE FB_REGDDR IS
-		WHEN FR_WAIT => 
-			FB_LE0   = !nFB_WR;
-			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
-				FB_REGDDR = FR_S0;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S0 =>
-			IF DDR_CS THEN
-				FB_LE0   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				IF LINE THEN							
-					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
-					FB_REGDDR = FR_S1;
-				ELSE
-					BUS_CYC_END = VCC;
-					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-					FB_REGDDR = FR_WAIT;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;	
-			END IF;
-		WHEN FR_S1 => 
-			IF DDR_CS THEN
-				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
-				FB_LE1   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				FB_REGDDR = FR_S2;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S2 => 
-			IF DDR_CS THEN
-				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
-				FB_LE2   = !nFB_WR;
-				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
-					FB_REGDDR = FR_S2;
-				ELSE
-					VIDEO_DDR_TA = VCC;
-					FB_REGDDR = FR_S3;
-				END IF;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-		WHEN FR_S3 => 
-			IF DDR_CS THEN
-				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
-				FB_LE3   = !nFB_WR;
-				VIDEO_DDR_TA = VCC;
-				BUS_CYC_END = VCC;
-				FB_REGDDR = FR_WAIT;
-			ELSE
-				FB_REGDDR = FR_WAIT;
-			END IF;
-	END CASE;
--- DDR STEUERUNG -----------------------------------------------------
--- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
-	VCKE = VIDEO_RAM_CTR0;
-	nVCS = !VIDEO_RAM_CTR1;
-	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
-	DDR_CONFIG = VIDEO_RAM_CTR3;	
-	FIFO_ACTIVE = VIDEO_RAM_CTR8;
---------------------------------
-	CPU_ROW_ADR[] = FB_ADR[26..14];
-	CPU_BA[] = FB_ADR[13..12];
-	CPU_COL_ADR[] = FB_ADR[11..2];
-	nVRAS = !VRAS;
-	nVCAS = !VCAS;
-	nVWE = !VWE;
-	SR_DDR_WR.CLK = DDRCLK0;
-	SR_DDRWR_D_SEL.CLK = DDRCLK0;
-	SR_VDMP[7..0].CLK = DDRCLK0;
-	SR_FIFO_WRE.CLK = DDRCLK0; 
-	CPU_AC.CLK = DDRCLK0;
-	FIFO_AC.CLK = DDRCLK0;
-	BLITTER_AC.CLK = DDRCLK0;
-	DDRWR_D_SEL1 = BLITTER_AC;
--- SELECT LOGIC
-	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
-	DDR_CS.CLK = MAIN_CLK;
-	DDR_CS.ENA = FB_ALE;
-	DDR_CS	 = DDR_SEL;
--- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
-	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
-			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
-			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
-	CPU_REQ.CLK = DDR_SYNC_66M;
-	CPU_REQ = CPU_SIG 
-			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
-	BUS_CYC.CLK = DDRCLK0;
-	BUS_CYC = BUS_CYC & !BUS_CYC_END;
-	-- STATE MACHINE SYNCHRONISIEREN -----------------
-	MCS[].CLK = DDRCLK0;
-	MCS0 = MAIN_CLK;
-	MCS1 = MCS0;		
-	CPU_DDR_SYNC.CLK = DDRCLK0;
-	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
-	---------------------------------------------------
-	VA_S[].CLK = DDRCLK0;
-	BA_S[].CLK = DDRCLK0;
-	VA[] =  VA_S[];
-	BA[] =  BA_S[];
-	VA_P[].CLK = DDRCLK0;
-	BA_P[].CLK = DDRCLK0;
--- DDR STATE MACHINE  -----------------------------------------------
-	DDR_SM.CLK = DDRCLK0;
-	CASE DDR_SM IS
-		WHEN DS_T1 =>
-			IF DDR_REFRESH_REQ THEN
-				DDR_SM = DS_R2;
-			ELSE
-				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
-					IF DDR_CONFIG THEN							-- JA
-						DDR_SM = DS_C2;
-					ELSE
-						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
-							VA_S[] = CPU_ROW_ADR[];
-							BA_S[] = CPU_BA[];
-							CPU_AC = VCC;
-							BUS_CYC = VCC;
-							DDR_SM = DS_T2B;
-						ELSE
-							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
-								VA_P[] = FIFO_ROW_ADR[];
-								BA_P[] = FIFO_BA[];
-								FIFO_AC = VCC;						-- VORBESETZEN
-							ELSE
-								VA_P[] = BLITTER_ROW_ADR[];
-								BA_P[] = BLITTER_BA[];
-								BLITTER_AC = VCC;					-- VORBESETZEN
-							END IF;
-							DDR_SM = DS_T2A;
-						END IF;
-					END IF;
-				ELSE
-					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
-				END IF;
-			END IF;
-			
-		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
-			IF DDR_SEL & (nFB_WR # !LINE) THEN
-				VRAS = VCC;
-				VA[] = FB_AD[26..14];
-				BA[] = FB_AD[13..12]; 
-				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
-				CPU_AC = VCC;
-				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
-			ELSE
-				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
-				VA[] = VA_P[];
-				BA[] = BA_P[]; 
-				VA_S[10] = !(FIFO_AC & FIFO_REQ);
-				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
-				FIFO_AC = FIFO_AC & FIFO_REQ;
-				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
-			END IF;	
-			DDR_SM = DS_T3;
-
-		WHEN DS_T2B =>
-			VRAS = VCC;
-			FIFO_BANK_NOT_OK = VCC;
-			CPU_AC = VCC;
-			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
-			DDR_SM = DS_T3;
-
-		WHEN DS_T3 =>
-			CPU_AC = CPU_AC;
-			FIFO_AC = FIFO_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
-				DDR_SM = DS_T4W;
-			ELSE
-				IF CPU_AC THEN										-- CPU?
-					VA_S[9..0] = CPU_COL_ADR[];
-					BA_S[] = CPU_BA[];
-					DDR_SM = DS_T4R;												 
-				ELSE
-					IF FIFO_AC THEN									-- FIFO?
-						VA_S[9..0] = FIFO_COL_ADR[];
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T4F;
-					ELSE
-						IF BLITTER_AC THEN
-							VA_S[9..0] = BLITTER_COL_ADR[];
-							BA_S[] = BLITTER_BA[];
-							DDR_SM = DS_T4R;												 
-						ELSE
-							DDR_SM = DS_N8;
-						END IF;
-					END IF;
-				END IF;
-			END IF;
--- READ			
-		WHEN DS_T4R =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
-			DDR_SM = DS_T5R;	
-			
-		WHEN DS_T5R =>
- 			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
- 				VA_S[9..0] = FIFO_COL_ADR[];
- 				VA_S[10] = GND;										-- MANUEL PRECHARGE
- 				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
- 			ELSE	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- WRITE			
-		WHEN DS_T4W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
- 			DDR_SM = DS_T5W;
-			
-		WHEN DS_T5W =>
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
-					   # BLITTER_AC & BLITTER_COL_ADR[];
-			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
-			BA_S[]  = CPU_AC     & CPU_BA[]
-				    # BLITTER_AC & BLITTER_BA[];
-			SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111";			-- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
-			SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111";			-- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
-			DDR_SM = DS_T6W;
-			
-		WHEN DS_T6W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			VCAS = VCC;															
-			VWE  = VCC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
-			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
-			SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111";			-- WENN LINE DANN ACTIV 
-			DDR_SM = DS_T7W;
-
-		WHEN DS_T7W =>								 
-			CPU_AC = CPU_AC;
-			BLITTER_AC = BLITTER_AC;
-			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
-			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
-			DDR_SM = DS_T8W;
-
-		WHEN DS_T8W =>								 
-			DDR_SM = DS_T9W;
-
-		WHEN DS_T9W =>								 
-			IF FIFO_REQ & FIFO_BANK_OK  THEN
-				VA_S[9..0] = FIFO_COL_ADR[];
-				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
-				BA_S[] = FIFO_BA[];
-				DDR_SM = DS_T6F;
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;
-			END IF;
--- FIFO READ 
-		WHEN DS_T4F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T5F;
-			
-		WHEN DS_T5F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
-					VA_S[9..0] = FIFO_COL_ADR[]+4;
-					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_S[] = FIFO_BA[];
-					DDR_SM = DS_T6F;
-				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
-				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
-			END IF;
-			
-		WHEN DS_T6F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			DDR_SM = DS_T7F;
-																							 
-		WHEN DS_T7F =>
-			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
-				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
-				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
-			ELSE
-				IF FIFO_REQ THEN
-					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
-						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
-						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
-					ELSE
-						VA_S[9..0] = FIFO_COL_ADR[]+4;
-						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
-						BA_S[] = FIFO_BA[];
-						DDR_SM = DS_T8F;
-					END IF;											 
-				ELSE
-					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
-					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
-				END IF;
-			END IF;
-			
-		WHEN DS_T8F =>
-			VCAS = VCC;															
-			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
-			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
-				DDR_SM = DS_T5F;									-- JA->
-			ELSE
-				DDR_SM = DS_T9F;
-			END IF;																	 
-			
-		WHEN DS_T9F =>
-			IF FIFO_REQ THEN
-				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
-					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
-					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
-				ELSE
- 					VA_P[9..0] = FIFO_COL_ADR[]+4;
-					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
-					BA_P[] = FIFO_BA[];
-					DDR_SM = DS_T10F;
- 				END IF;											 
-			ELSE
-				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
-				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
-			END IF;
-
-		WHEN DS_T10F =>
- 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
- 				VRAS = VCC;
- 				VA[] = FB_AD[26..14];
- 				BA[] = FB_AD[13..12]; 
- 				CPU_AC = VCC;
- 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
- 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
- 				DDR_SM = DS_T3;
- 			ELSE
-				VCAS = VCC;
-				VA[] = VA_P[];
-				BA[] = BA_P[];
-				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
-				DDR_SM = DS_T7F;
-			END IF;	
-
--- CONFIG CYCLUS
-		WHEN DS_C2 =>
-			DDR_SM = DS_C3;
-		WHEN DS_C3 =>
-			BUS_CYC = CPU_REQ;
-			DDR_SM = DS_C4;
-		WHEN DS_C4 =>
-			IF CPU_REQ THEN
-				DDR_SM = DS_C5;
-			ELSE
-				DDR_SM = DS_T1;
-			END IF;	
-		WHEN DS_C5 =>
-			DDR_SM = DS_C6;
-		WHEN DS_C6 =>
-			VA_S[] = FB_AD[12..0];
-			BA_S[] = FB_AD[14..13];
-			DDR_SM = DS_C7;
-		WHEN DS_C7 =>
-			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
-			DDR_SM = DS_N8;
--- CLOSE FIFO BANK
-		WHEN DS_CB6 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- BÄNKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_N7;
-		WHEN DS_CB8 =>
-			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
-			VRAS = VCC;									-- BÄNKE SCHLIESSEN
-			VWE = VCC;
-			DDR_SM = DS_T1;
--- REFRESH 70NS = 10 ZYCLEN
-		WHEN DS_R2 =>
-			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
-				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
-				VWE = VCC;		
-				VA[10] = VCC;
-				FIFO_BANK_NOT_OK = VCC;
-				DDR_SM = DS_R4;
-			ELSE
-				VCAS = VCC;
-				VRAS = VCC;
-				DDR_SM = DS_R3;
-			END IF;
-		WHEN DS_R3 =>
-			DDR_SM = DS_R4;
-		WHEN DS_R4 =>
-			DDR_SM = DS_R5;
-		WHEN DS_R5 =>
-			DDR_SM = DS_R6;
-		WHEN DS_R6 =>
-			DDR_SM = DS_N5;
--- LEERSCHLAUFE			
-		WHEN DS_N5 =>
-			DDR_SM = DS_N6;
-		WHEN DS_N6 =>
-			DDR_SM = DS_N7;
-		WHEN DS_N7 =>
-			DDR_SM = DS_N8;
-		WHEN DS_N8 =>
-			DDR_SM = DS_T1;
-	END CASE;
-
----------------------------------------------------------------
--- BLITTER ----------------------
------------------------------------------
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
-	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
-	BLITTER_BA1 = BLITTER_ADR13;
-	BLITTER_BA0 = BLITTER_ADR12;
-	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
-------------------------------------------------------------------------------	
--- FIFO ---------------------------------
---------------------------------------------------------
-	FIFO_REQ.CLK = DDRCLK0;
-	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
-			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
-	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
-	FIFO_BA1 	   = VIDEO_ADR_CNT9;
-	FIFO_BA0 	   = VIDEO_ADR_CNT8;
-	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
-	FIFO_BANK_OK.CLK = DDRCLK0;
-	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
-	CLR_FIFO_SYNC.CLK =DDRCLK0;
-	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
-	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
-	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
-	STOP.CLK = DDRCLK0;
-	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-	-- ZÄHLEN -----------------------------------------------
-	VIDEO_ADR_CNT[].CLK = DDRCLK0;
-	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
-	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
-					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
-	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
-	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
-	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
-	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
-	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-	-- AKTUELLE VIDEO ADRESSE
-	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
-	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
------------------------------------------------------------------------------------------
--- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
------------------------------------------------------------------------------------------
-	DDR_REFRESH_CNT[].CLK = CLK33M;
-	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
-	REFRESH_TIME.CLK = DDRCLK0;
-	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
-	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
-	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
-	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
-					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
-	DDR_REFRESH_REQ.CLK = DDRCLK0;
-	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
------------------------------------------------------------	
--- VIDEO REGISTER -----------------------
----------------------------------------------------------------------------------------------------------------------
-	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
-	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
-	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
-
-	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
-	VIDEO_BASE_M_D[] = FB_AD[23..16];
-	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
-
-	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
-	VIDEO_BASE_H_D[] = FB_AD[23..16];
-	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
-	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
-	VIDEO_BASE_X_D[] = FB_AD[26..24];
-	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
-
-	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
-	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
-	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
-					  
-	FB_AD[31..24] = lpm_bustri_BYT(
-						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
-					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
-					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
-
-	FB_AD[23..16] = lpm_bustri_BYT(
-						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
-					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
-					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
-					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
-					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
-					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
-					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
-END;
-
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.bsf
similarity index 93%
rename from FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
rename to FPGA_by_Fredi/Video/Doppelzeilen_Fifo.bsf
index 3c8cdfc..ba94be2 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.bsf
+++ b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.bsf
@@ -21,7 +21,7 @@ applicable agreement for further details.
 (header "symbol" (version "1.1"))
 (symbol
 	(rect 0 0 160 144)
-	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
+	(text "Doppelzeilen_Fifo" (rect 29 1 149 17)(font "Arial" (font_size 10)))
 	(text "inst" (rect 8 128 25 140)(font "Arial" ))
 	(port
 		(pt 0 32)
@@ -66,7 +66,6 @@ applicable agreement for further details.
 		(line (pt 160 32)(pt 144 32)(line_width 3))
 	)
 	(drawing
-		(text "(ack)" (rect 51 67 72 79)(font "Arial" ))
 		(text "128 bits x 512 words" (rect 58 116 144 128)(font "Arial" ))
 		(line (pt 16 16)(pt 144 16)(line_width 1))
 		(line (pt 144 16)(pt 144 128)(line_width 1))
diff --git a/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc
new file mode 100644
index 0000000..8490f6b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION Doppelzeilen_Fifo 
+(
+	aclr,
+	clock,
+	data[127..0],
+	rdreq,
+	wrreq
+)
+
+RETURNS (
+	q[127..0]
+);
diff --git a/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip
new file mode 100644
index 0000000..4cb4549
--- /dev/null
+++ b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Doppelzeilen_Fifo.inc"]
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.vhd
similarity index 80%
rename from FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
rename to FPGA_by_Fredi/Video/Doppelzeilen_Fifo.vhd
index 55183b0..e8b0e82 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.vhd
+++ b/FPGA_by_Fredi/Video/Doppelzeilen_Fifo.vhd
@@ -1,10 +1,10 @@
--- megafunction wizard: %LPM_FIFO+%
+-- megafunction wizard: %FIFO%
 -- GENERATION: STANDARD
 -- VERSION: WM1.0
 -- MODULE: scfifo 
 
 -- ============================================================
--- File Name: lpm_fifoDZ.vhd
+-- File Name: Doppelzeilen_Fifo.vhd
 -- Megafunction Name(s):
 -- 			scfifo
 --
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_mf;
 USE altera_mf.all;
 
-ENTITY lpm_fifoDZ IS
+ENTITY Doppelzeilen_Fifo IS
 	PORT
 	(
 		aclr		: IN STD_LOGIC ;
@@ -49,10 +49,10 @@ ENTITY lpm_fifoDZ IS
 		wrreq		: IN STD_LOGIC ;
 		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
 	);
-END lpm_fifoDZ;
+END Doppelzeilen_Fifo;
 
 
-ARCHITECTURE SYN OF lpm_fifodz IS
+ARCHITECTURE SYN OF doppelzeilen_fifo IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
 
@@ -86,10 +86,10 @@ BEGIN
 
 	scfifo_component : scfifo
 	GENERIC MAP (
-		add_ram_output_register => "OFF",
+		add_ram_output_register => "ON",
 		intended_device_family => "Cyclone III",
 		lpm_numwords => 512,
-		lpm_showahead => "ON",
+		lpm_showahead => "OFF",
 		lpm_type => "scfifo",
 		lpm_width => 128,
 		lpm_widthu => 9,
@@ -117,38 +117,38 @@ END SYN;
 -- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
 -- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
 -- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
--- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
 -- Retrieval info: PRIVATE: Clock NUMERIC "0"
 -- Retrieval info: PRIVATE: Depth NUMERIC "512"
 -- Retrieval info: PRIVATE: Empty NUMERIC "0"
 -- Retrieval info: PRIVATE: Full NUMERIC "0"
 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
--- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
 -- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
 -- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
--- Retrieval info: PRIVATE: Optimize NUMERIC "2"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
 -- Retrieval info: PRIVATE: UsedW NUMERIC "0"
 -- Retrieval info: PRIVATE: Width NUMERIC "128"
--- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
 -- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
 -- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
 -- Retrieval info: PRIVATE: output_width NUMERIC "128"
--- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
 -- Retrieval info: PRIVATE: rsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
 -- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
 -- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
 -- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
--- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
 -- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
--- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
--- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
 -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
 -- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
@@ -168,11 +168,11 @@ END SYN;
 -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
 -- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL Doppelzeilen_Fifo_wave*.jpg FALSE
 -- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_by_Fredi/Video/UNUSED b/FPGA_by_Fredi/Video/UNUSED
deleted file mode 100644
index 12f424b..0000000
--- a/FPGA_by_Fredi/Video/UNUSED
+++ /dev/null
@@ -1,267 +0,0 @@
-
--- Clearbox generated Memory Initialization File (.mif)
-
-WIDTH=6;
-DEPTH=256;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-	000  :   0F;
-	001  :   0E;
-	002  :   0D;
-	003  :   0C;
-	004  :   0B;
-	005  :   0A;
-	006  :   09;
-	007  :   08;
-	008  :   07;
-	009  :   06;
-	00a  :   05;
-	00b  :   04;
-	00c  :   03;
-	00d  :   02;
-	00e  :   01;
-	00f  :   00;
-	010  :   0F;
-	011  :   0E;
-	012  :   0D;
-	013  :   0C;
-	014  :   0B;
-	015  :   0A;
-	016  :   09;
-	017  :   08;
-	018  :   07;
-	019  :   06;
-	01a  :   05;
-	01b  :   04;
-	01c  :   03;
-	01d  :   02;
-	01e  :   01;
-	01f  :   00;
-	020  :   0F;
-	021  :   0E;
-	022  :   0D;
-	023  :   0C;
-	024  :   0B;
-	025  :   0A;
-	026  :   09;
-	027  :   08;
-	028  :   07;
-	029  :   06;
-	02a  :   05;
-	02b  :   04;
-	02c  :   03;
-	02d  :   02;
-	02e  :   01;
-	02f  :   00;
-	030  :   0F;
-	031  :   0E;
-	032  :   0D;
-	033  :   0C;
-	034  :   0B;
-	035  :   0A;
-	036  :   09;
-	037  :   08;
-	038  :   07;
-	039  :   06;
-	03a  :   05;
-	03b  :   04;
-	03c  :   03;
-	03d  :   02;
-	03e  :   01;
-	03f  :   00;
-	040  :   0F;
-	041  :   0E;
-	042  :   0D;
-	043  :   0C;
-	044  :   0B;
-	045  :   0A;
-	046  :   09;
-	047  :   08;
-	048  :   07;
-	049  :   06;
-	04a  :   05;
-	04b  :   04;
-	04c  :   03;
-	04d  :   02;
-	04e  :   01;
-	04f  :   00;
-	050  :   0F;
-	051  :   0E;
-	052  :   0D;
-	053  :   0C;
-	054  :   0B;
-	055  :   0A;
-	056  :   09;
-	057  :   08;
-	058  :   07;
-	059  :   06;
-	05a  :   05;
-	05b  :   04;
-	05c  :   03;
-	05d  :   02;
-	05e  :   01;
-	05f  :   00;
-	060  :   0F;
-	061  :   0E;
-	062  :   0D;
-	063  :   0C;
-	064  :   0B;
-	065  :   0A;
-	066  :   09;
-	067  :   08;
-	068  :   07;
-	069  :   06;
-	06a  :   05;
-	06b  :   04;
-	06c  :   03;
-	06d  :   02;
-	06e  :   01;
-	06f  :   00;
-	070  :   0F;
-	071  :   0E;
-	072  :   0D;
-	073  :   0C;
-	074  :   0B;
-	075  :   0A;
-	076  :   09;
-	077  :   08;
-	078  :   07;
-	079  :   06;
-	07a  :   05;
-	07b  :   04;
-	07c  :   03;
-	07d  :   02;
-	07e  :   01;
-	07f  :   00;
-	080  :   0F;
-	081  :   0E;
-	082  :   0D;
-	083  :   0C;
-	084  :   0B;
-	085  :   0A;
-	086  :   09;
-	087  :   08;
-	088  :   07;
-	089  :   06;
-	08a  :   05;
-	08b  :   04;
-	08c  :   03;
-	08d  :   02;
-	08e  :   01;
-	08f  :   00;
-	090  :   0F;
-	091  :   0E;
-	092  :   0D;
-	093  :   0C;
-	094  :   0B;
-	095  :   0A;
-	096  :   09;
-	097  :   08;
-	098  :   07;
-	099  :   06;
-	09a  :   05;
-	09b  :   04;
-	09c  :   03;
-	09d  :   02;
-	09e  :   01;
-	09f  :   00;
-	0a0  :   0F;
-	0a1  :   0E;
-	0a2  :   0D;
-	0a3  :   0C;
-	0a4  :   0B;
-	0a5  :   0A;
-	0a6  :   09;
-	0a7  :   08;
-	0a8  :   07;
-	0a9  :   06;
-	0aa  :   05;
-	0ab  :   04;
-	0ac  :   03;
-	0ad  :   02;
-	0ae  :   01;
-	0af  :   00;
-	0b0  :   0F;
-	0b1  :   0E;
-	0b2  :   0D;
-	0b3  :   0C;
-	0b4  :   0B;
-	0b5  :   0A;
-	0b6  :   09;
-	0b7  :   08;
-	0b8  :   07;
-	0b9  :   06;
-	0ba  :   05;
-	0bb  :   04;
-	0bc  :   03;
-	0bd  :   02;
-	0be  :   01;
-	0bf  :   00;
-	0c0  :   0F;
-	0c1  :   0E;
-	0c2  :   0D;
-	0c3  :   0C;
-	0c4  :   0B;
-	0c5  :   0A;
-	0c6  :   09;
-	0c7  :   08;
-	0c8  :   07;
-	0c9  :   06;
-	0ca  :   05;
-	0cb  :   04;
-	0cc  :   03;
-	0cd  :   02;
-	0ce  :   01;
-	0cf  :   00;
-	0d0  :   0F;
-	0d1  :   0E;
-	0d2  :   0D;
-	0d3  :   0C;
-	0d4  :   0B;
-	0d5  :   0A;
-	0d6  :   09;
-	0d7  :   08;
-	0d8  :   07;
-	0d9  :   06;
-	0da  :   05;
-	0db  :   04;
-	0dc  :   03;
-	0dd  :   02;
-	0de  :   01;
-	0df  :   00;
-	0e0  :   0F;
-	0e1  :   0E;
-	0e2  :   0D;
-	0e3  :   0C;
-	0e4  :   0B;
-	0e5  :   0A;
-	0e6  :   09;
-	0e7  :   08;
-	0e8  :   07;
-	0e9  :   06;
-	0ea  :   05;
-	0eb  :   04;
-	0ec  :   03;
-	0ed  :   02;
-	0ee  :   01;
-	0ef  :   00;
-	0f0  :   0F;
-	0f1  :   0E;
-	0f2  :   0D;
-	0f3  :   0C;
-	0f4  :   0B;
-	0f5  :   0A;
-	0f6  :   09;
-	0f7  :   08;
-	0f8  :   07;
-	0f9  :   06;
-	0fa  :   05;
-	0fb  :   04;
-	0fc  :   03;
-	0fd  :   02;
-	0fe  :   01;
-	0ff  :   00;
-END;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
index fc80715..f5588cf 100644
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
 	VR_WR : OUTPUT;
 	VR_RD : OUTPUT;
 	CLR_FIFO : OUTPUT;
+	DPZF_CLKENA: OUTPUT;
 	FB_AD[31..0] : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
@@ -80,7 +81,7 @@ VARIABLE
 	ST_CLUT						:NODE;
 	FB_B[3..0]					:NODE;
 	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE[2..0]			:DFFE;
 	ST_SHIFT_MODE_CS			:NODE;
 	FALCON_SHIFT_MODE[10..0]	:DFFE;
 	FALCON_SHIFT_MODE_CS		:NODE;
@@ -105,20 +106,19 @@ VARIABLE
 	HSYNC_START					:DFF;
 	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
 	VSYNC						:DFF;
-	VSYNC_START					:DFFE;
-	VSYNC_I[2..0]				:DFFE;
+	VSYNC_I[2..0]				:DFF;
 	nBLANK						:DFF;
 	DISP_ON						:DFF;
-	DPO_ZL						:DFFE;
+	DPO_ZL						:DFF;
 	DPO_ON						:DFF;
 	DPO_OFF						:DFF;
 	VDTRON						:DFF;
-	VDO_ZL						:DFFE;
+	VDO_ZL						:DFF;
 	VDO_ON						:DFF;
 	VDO_OFF						:DFF;
-	VHCNT[11..0]				:DFF;
+	VHCNT[12..0]				:DFF;
 	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[10..0]				:DFFE;
+	VVCNT[12..0]				:DFFE;
 	VERZ[2..0][9..0]			:DFF;
 	RAND[6..0]					:DFF;
 	RAND_ON						:NODE;
@@ -130,67 +130,63 @@ VARIABLE
 	SYNC_PIX2					:DFF;
 	CCSEL[2..0]					:DFF;
 	COLOR16						:NODE;
-	COLOR24						:NODE;
--- ATARI RESOLUTION
-	ATARI_SYNC					:NODE;	 
-	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
-	ATARI_HH_CS					:NODE;
-	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
-	ATARI_VH_CS					:NODE;
-	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
-	ATARI_HL_CS					:NODE;
-	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
-	ATARI_VL_CS					:NODE;
+	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
+	TE							:NODE;
 -- HORIZONTAL
-	RAND_LINKS[11..0]			:NODE;
-	HDIS_START[11..0]			:NODE;
-	HDIS_END[11..0]				:NODE;  
-	RAND_RECHTS[11..0]			:NODE;
-	HS_START[11..0]				:NODE;
-	H_TOTAL[11..0]				:NODE;
-	HDIS_LEN[11..0]				:NODE;
-	MULF[5..0]					:NODE;
-	VDL_HHT[11..0]				:DFFE;
+	RAND_LINKS[12..0]			:NODE;
+	HDIS_START[12..0]			:NODE;
+	STARTP[12..0]				:NODE; 
+	HDIS_END[12..0]				:NODE;  
+	RAND_RECHTS[12..0]			:NODE;
+	MULF[12..0]					:NODE;
+	HS_START[12..0]				:NODE;
+	H_TOTAL[12..0]				:NODE;
+	HDIS_LEN[12..0]				:NODE;
+	WPL[15..0]					:NODE;
+	VDL_HHT[12..0]				:DFFE;
 	VDL_HHT_CS					:NODE;
-	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE[12..0]				:DFFE;
 	VDL_HBE_CS					:NODE;
-	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB[12..0]				:DFFE;
 	VDL_HDB_CS					:NODE;
-	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE[12..0]				:DFFE;
 	VDL_HDE_CS					:NODE;
-	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB[12..0]				:DFFE;
 	VDL_HBB_CS					:NODE;
-	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS[12..0]				:DFFE;
 	VDL_HSS_CS					:NODE;
 -- VERTIKAL
-	RAND_OBEN[10..0]			:NODE; 
-	VDIS_START[10..0]			:NODE; 
-	VDIS_END[10..0]				:NODE; 
-	RAND_UNTEN[10..0]			:NODE; 
-	VS_START[10..0]				:NODE; 
-	V_TOTAL[10..0]				:NODE;  
+	RAND_OBEN[12..0]			:NODE; 
+	VDIS_START[12..0]			:NODE; 
+	VDIS_END[12..0]				:NODE; 
+	RAND_UNTEN[12..0]			:NODE; 
+	VS_START[12..0]				:NODE; 
+	V_TOTAL[12..0]				:NODE;  
 	FALCON_VIDEO				:NODE;
 	ST_VIDEO					:NODE;
 	INTER_ZEI					:DFF;
-	DOP_ZEI						:DFF;
 	DOP_FIFO_CLR				:DFF;
 	
-	VDL_VBE[10..0]				:DFFE;
+	VIDEL_CS					:NODE;
+	VDL_VBE[12..0]				:DFFE;
 	VDL_VBE_CS					:NODE;
-	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB[12..0]				:DFFE;
 	VDL_VDB_CS					:NODE;
-	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE[12..0]				:DFFE;
 	VDL_VDE_CS					:NODE;
-	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB[12..0]				:DFFE;
 	VDL_VBB_CS					:NODE;
-	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS[12..0]				:DFFE;
 	VDL_VSS_CS					:NODE;
-	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT[12..0]				:DFFE;
 	VDL_VFT_CS					:NODE;
-	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT[12..0]				:DFFE;
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+	VDL_BPP_CS					:NODE;
+	VDL_PH_CS					:NODE;
+	VDL_PV_CS					:NODE;
 
 BEGIN
 -- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
 	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
 	FB_16B1 = FB_ADR[0]==1									-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- VIDEL CS
+	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
 -- ACP CLUT --
 	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
 -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
 	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[] = FB_AD[26..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
 -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
 	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
 	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
-	-- HORIZONTAL TIMING 640x480
-	ATARI_HH[].CLK = MAIN_CLK;
-	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
-	ATARI_HH[] = FB_AD[];
-	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
-	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
-	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
-	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
-	ATARI_VH[].CLK = MAIN_CLK;
-	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
-	ATARI_VH[] = FB_AD[];
-	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
-	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
-	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
-	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
-	ATARI_HL[].CLK = MAIN_CLK;
-	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
-	ATARI_HL[] = FB_AD[];
-	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
-	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
-	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
-	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
-	ATARI_VL[].CLK = MAIN_CLK;
-	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
-	ATARI_VL[] = FB_AD[];
-	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
-	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
-	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
-	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
 -- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
 	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
 -- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
 ------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
 -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
 	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
 	FALCON_VIDEO	   = ACP_VCTR7;
+	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_VIDEO		   = ACP_VCTR6;
-	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
 	CCSEL[].CLK = PIXEL_CLK;
 	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
 			# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
 -- DIVERSE (VIDEO)-REGISTER ----------------------------
 -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
 --SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
 	BLITTER_ON = SYS_CTR3;
 --VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
 --VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- DATEN AUFLÖSUNG
+	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
+	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
+	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
 -- HORIZONTAL
 -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[27..16];
-	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[] = FB_AD[28..16];
+	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
 -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[27..16];
-	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[] = FB_AD[28..16];
+	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
 -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[27..16];
-	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[] = FB_AD[28..16];
+	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
 -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[27..16];
-	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[] = FB_AD[28..16];
+	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
 -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[27..16];
-	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[] = FB_AD[28..16];
+	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
 -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[27..16];
-	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[] = FB_AD[28..16];
+	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
 -- VERTIKAL
 -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[26..16];
-	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[] = FB_AD[28..16];
+	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
 -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[26..16];
-	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[] = FB_AD[28..16];
+	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
 -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[26..16];
-	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[] = FB_AD[28..16];
+	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
 -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[26..16];
-	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[] = FB_AD[28..16];
+	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
 -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[26..16];
-	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[] = FB_AD[28..16];
+	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
 -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[26..16];
-	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[] = FB_AD[28..16];
+	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
 -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[24..16];
-	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[] = FB_AD[28..16];
+	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
 -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS & VDL_LOF[]
-					  # VDL_LWD_CS & VDL_LWD[]
-					  #	VDL_HBE_CS & (0,VDL_HBE[])
-					  #	VDL_HDB_CS & (0,VDL_HDB[])
-					  #	VDL_HDE_CS & (0,VDL_HDE[])
-					  #	VDL_HBB_CS & (0,VDL_HBB[])
-					  #	VDL_HSS_CS & (0,VDL_HSS[])
-					  #	VDL_HHT_CS & (0,VDL_HHT[])
-					  #	VDL_VBE_CS & (0,VDL_VBE[])
-					  #	VDL_VDB_CS & (0,VDL_VDB[])
-					  #	VDL_VDE_CS & (0,VDL_VDE[])
-					  #	VDL_VBB_CS & (0,VDL_VBB[])
-					  #	VDL_VSS_CS & (0,VDL_VSS[])
-					  #	VDL_VFT_CS & (0,VDL_VFT[])
-					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS & (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
- 					  #	ATARI_HH_CS & ATARI_HH[31..16]
-					  #	ATARI_VH_CS & ATARI_VH[31..16]
-					  #	ATARI_HL_CS & ATARI_HL[31..16]
-					  #	ATARI_VL_CS & ATARI_VL[31..16]
-					  #	CCR_CS & (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
-					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
-					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
-					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
-
+					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS 				& VDL_LOF[]
+					  # VDL_LWD_CS 				& WPL[]
+					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
+					  # VDL_PH_CS  				& (0,HDIS_LEN[])
+					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
+					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
+					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
+					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
+					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
+					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
+					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
+					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
+					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
+					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
+					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
+					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
+					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
+					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
+ 					  #	CCR_CS 					& (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
  	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
-					  #	ATARI_HH_CS & ATARI_HH[15..0]
-					  #	ATARI_VH_CS & ATARI_VH[15..0]
-					  #	ATARI_HL_CS & ATARI_HL[15..0]
-					  #	ATARI_VL_CS & ATARI_VL[15..0]
- 					  #	CCR_CS & CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
-
-	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
-			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
-				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
-				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-	
--- VIDEO AUSGABE SETZEN
+ 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
+ 					  #	CCR_CS 					& CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
+	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
+-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
 	CLK17M.CLK = CLK33M;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
-	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
-			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
-----------------------------------------------------------------
+	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
+	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9];
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -----------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
-			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
-
- 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
-			# 4  & !ST_VIDEO & !VDL_VMD2
-			# 16 &  ST_VIDEO &  VDL_VMD2
-			# 32 &  ST_VIDEO & !VDL_VMD2;
-	 	
-	 	
-	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
-			   #  640 & !VDL_VMD2;
-					
--- DOPPELZEILENMODUS
-	DOP_ZEI.CLK = MAIN_CLK;
-	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
+-- MULTIPLIKATIONS FAKTOR ----------------------------------------
+ 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
+			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
+			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
+			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
+			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
+ -- BREITE IN PIXELN ------------------------------------------------	 	
+	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
+			   #  640 & !TE							& !ACP_VIDEO_ON
+			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
+	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
+-- DOPPELZEILENMODUS ---------------------------------------------
 	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
-					
-	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
-					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
-	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
-					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
-	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-					
-	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
-					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
-					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
-					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
-					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
-					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
-					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
-	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
-	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- ZÄHLER
+	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER UNGERADEN ZEILEN
+	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN FÜR DOP.ZEI.FIFO
+-- TIMING HORIZONTAL				
+	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
+	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
+					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
+	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
+					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
+					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
+	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
+					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2 + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
+	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2 + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
+-- TIMING VERTICAL 					
+	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+-- ZÄHLER ---------------------------------------------------------------------------
 	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[]-2);
+	LAST = VHCNT[]==(H_TOTAL[] - 1);
 	VHCNT[].CLK = PIXEL_CLK;
 	VHCNT[] = (VHCNT[] + 1) & !LAST;
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
 -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
 	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
 -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
-	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
 -- VERZÖGERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_START = VHCNT[]==HS_START[] - 2;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
-	VSYNC_START.ENA = LAST;
-	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
-	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
+	VSYNC_I[].CLK = PIXEL_CLK;
 	VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
 	VERZ[0][0] = DISP_ON;
---	VERZ[1][0] = HSYNC_I[]!=0;
-	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
-	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
+				# VDL_VCT6 & HSYNC_I[]==0;	
+	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
+				# VDL_VCT5 & VSYNC_I[]==0;	
 	nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
 	HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
 ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE LÖSCHEN (GENUG FRÜH DAMIT ES GEFÜLLT WERDEN KANN BIS ZUR NEUEN ÜBERTRAGUNG) 
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
 	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
index 2a594ff..0ade395 100644
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
+++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
@@ -59,6 +59,7 @@ SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
 	VR_WR : OUTPUT;
 	VR_RD : OUTPUT;
 	CLR_FIFO : OUTPUT;
+	DPZF_CLKENA: OUTPUT;
 	FB_AD[31..0] : BIDIR;
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
 )
@@ -80,7 +81,7 @@ VARIABLE
 	ST_CLUT						:NODE;
 	FB_B[3..0]					:NODE;
 	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE[2..0]			:DFFE;
 	ST_SHIFT_MODE_CS			:NODE;
 	FALCON_SHIFT_MODE[10..0]	:DFFE;
 	FALCON_SHIFT_MODE_CS		:NODE;
@@ -105,20 +106,19 @@ VARIABLE
 	HSYNC_START					:DFF;
 	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
 	VSYNC						:DFF;
-	VSYNC_START					:DFFE;
-	VSYNC_I[2..0]				:DFFE;
+	VSYNC_I[2..0]				:DFF;
 	nBLANK						:DFF;
 	DISP_ON						:DFF;
-	DPO_ZL						:DFFE;
+	DPO_ZL						:DFF;
 	DPO_ON						:DFF;
 	DPO_OFF						:DFF;
 	VDTRON						:DFF;
-	VDO_ZL						:DFFE;
+	VDO_ZL						:DFF;
 	VDO_ON						:DFF;
 	VDO_OFF						:DFF;
-	VHCNT[11..0]				:DFF;
+	VHCNT[12..0]				:DFF;
 	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[10..0]				:DFFE;
+	VVCNT[12..0]				:DFFE;
 	VERZ[2..0][9..0]			:DFF;
 	RAND[6..0]					:DFF;
 	RAND_ON						:NODE;
@@ -130,67 +130,63 @@ VARIABLE
 	SYNC_PIX2					:DFF;
 	CCSEL[2..0]					:DFF;
 	COLOR16						:NODE;
-	COLOR24						:NODE;
--- ATARI RESOLUTION
-	ATARI_SYNC					:NODE;	 
-	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
-	ATARI_HH_CS					:NODE;
-	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
-	ATARI_VH_CS					:NODE;
-	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
-	ATARI_HL_CS					:NODE;
-	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
-	ATARI_VL_CS					:NODE;
+	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
+	TE							:NODE;
 -- HORIZONTAL
-	RAND_LINKS[11..0]			:NODE;
-	HDIS_START[11..0]			:NODE;
-	HDIS_END[11..0]				:NODE;  
-	RAND_RECHTS[11..0]			:NODE;
-	HS_START[11..0]				:NODE;
-	H_TOTAL[11..0]				:NODE;
-	HDIS_LEN[11..0]				:NODE;
-	MULF[5..0]					:NODE;
-	VDL_HHT[11..0]				:DFFE;
+	RAND_LINKS[12..0]			:NODE;
+	HDIS_START[12..0]			:NODE;
+	STARTP[12..0]				:NODE; 
+	HDIS_END[12..0]				:NODE;  
+	RAND_RECHTS[12..0]			:NODE;
+	MULF[12..0]					:NODE;
+	HS_START[12..0]				:NODE;
+	H_TOTAL[12..0]				:NODE;
+	HDIS_LEN[12..0]				:NODE;
+	WPL[15..0]					:NODE;
+	VDL_HHT[12..0]				:DFFE;
 	VDL_HHT_CS					:NODE;
-	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE[12..0]				:DFFE;
 	VDL_HBE_CS					:NODE;
-	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB[12..0]				:DFFE;
 	VDL_HDB_CS					:NODE;
-	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE[12..0]				:DFFE;
 	VDL_HDE_CS					:NODE;
-	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB[12..0]				:DFFE;
 	VDL_HBB_CS					:NODE;
-	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS[12..0]				:DFFE;
 	VDL_HSS_CS					:NODE;
 -- VERTIKAL
-	RAND_OBEN[10..0]			:NODE; 
-	VDIS_START[10..0]			:NODE; 
-	VDIS_END[10..0]				:NODE; 
-	RAND_UNTEN[10..0]			:NODE; 
-	VS_START[10..0]				:NODE; 
-	V_TOTAL[10..0]				:NODE;  
+	RAND_OBEN[12..0]			:NODE; 
+	VDIS_START[12..0]			:NODE; 
+	VDIS_END[12..0]				:NODE; 
+	RAND_UNTEN[12..0]			:NODE; 
+	VS_START[12..0]				:NODE; 
+	V_TOTAL[12..0]				:NODE;  
 	FALCON_VIDEO				:NODE;
 	ST_VIDEO					:NODE;
 	INTER_ZEI					:DFF;
-	DOP_ZEI						:DFF;
 	DOP_FIFO_CLR				:DFF;
 	
-	VDL_VBE[10..0]				:DFFE;
+	VIDEL_CS					:NODE;
+	VDL_VBE[12..0]				:DFFE;
 	VDL_VBE_CS					:NODE;
-	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB[12..0]				:DFFE;
 	VDL_VDB_CS					:NODE;
-	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE[12..0]				:DFFE;
 	VDL_VDE_CS					:NODE;
-	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB[12..0]				:DFFE;
 	VDL_VBB_CS					:NODE;
-	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS[12..0]				:DFFE;
 	VDL_VSS_CS					:NODE;
-	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT[12..0]				:DFFE;
 	VDL_VFT_CS					:NODE;
-	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT[12..0]				:DFFE;
 	VDL_VCT_CS					:NODE;
 	VDL_VMD[3..0]				:DFFE;
 	VDL_VMD_CS					:NODE;
+	VDL_BPP_CS					:NODE;
+	VDL_PH_CS					:NODE;
+	VDL_PV_CS					:NODE;
 
 BEGIN
 -- BYT SELECT 32 BIT
@@ -207,6 +203,8 @@ BEGIN
 	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
 	FB_16B1 = FB_ADR[0]==1									-- ADR==1
 		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- VIDEL CS
+	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
 -- ACP CLUT --
 	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
 	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
@@ -226,11 +224,11 @@ BEGIN
 -- ST SHIFT MODE
 	ST_SHIFT_MODE[].CLK = MAIN_CLK;
 	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[] = FB_AD[26..24];
 	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
 -- FALCON SHIFT MODE
 	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
 	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
@@ -238,13 +236,13 @@ BEGIN
 	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
 	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
 	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
 	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
 	ACP_VCTR[31..8] = FB_AD[31..8];
 	ACP_VCTR[5..0] = FB_AD[5..0];
 	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
@@ -253,42 +251,8 @@ BEGIN
 	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
 	ACP_VIDEO_ON = ACP_VCTR0;
 	nPD_VGA = ACP_VCTR1;
-	-- ATARI MODUS
-	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
-	-- HORIZONTAL TIMING 640x480
-	ATARI_HH[].CLK = MAIN_CLK;
-	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
-	ATARI_HH[] = FB_AD[];
-	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
-	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
-	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
-	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 640x480
-	ATARI_VH[].CLK = MAIN_CLK;
-	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
-	ATARI_VH[] = FB_AD[];
-	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
-	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
-	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
-	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
-	-- HORIZONTAL TIMING 320x240
-	ATARI_HL[].CLK = MAIN_CLK;
-	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
-	ATARI_HL[] = FB_AD[];
-	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
-	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
-	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
-	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
-	-- VERTIKAL TIMING 320x240
-	ATARI_VL[].CLK = MAIN_CLK;
-	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
-	ATARI_VL[] = FB_AD[];
-	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
-	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
-	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
-	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
 -- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
 	VR_WR.CLK = MAIN_CLK;
 	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
 	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
@@ -299,7 +263,7 @@ BEGIN
 	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
 	VR_FRQ[] = FB_AD[23..16];
 -- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
 	VIDEO_RECONFIG.CLK = MAIN_CLK;
 	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
 ------------------------------------------------------------------------------------------------------------------------
@@ -313,11 +277,11 @@ BEGIN
 -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
 	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
 	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
 	FALCON_VIDEO	   = ACP_VCTR7;
+	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
 	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_VIDEO		   = ACP_VCTR6;
-	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
 	CCSEL[].CLK = PIXEL_CLK;
 	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
 			# B"001" & FALCON_CLUT
@@ -328,108 +292,112 @@ BEGIN
 -- DIVERSE (VIDEO)-REGISTER ----------------------------
 -- RANDFARBE
 	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
 	CCR[] = FB_AD[23..0];
 	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
 	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
 	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
 --SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
 	SYS_CTR[].CLK = MAIN_CLK;
 	SYS_CTR[6..0] = FB_AD[22..16];
 	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
-	BLITTER_ON = !SYS_CTR3;
+	BLITTER_ON = SYS_CTR3;
 --VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
 	VDL_LOF[].CLK = MAIN_CLK;
 	VDL_LOF[] = FB_AD[31..16];
 	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
 	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
 --VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
 	VDL_LWD[].CLK = MAIN_CLK;
 	VDL_LWD[] = FB_AD[31..16];
 	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
 	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- DATEN AUFLÖSUNG
+	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
+	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
+	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
 -- HORIZONTAL
 -- VDL_HHT
 	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
 	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[27..16];
-	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[] = FB_AD[28..16];
+	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
 	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
 -- VDL_HBE
 	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
 	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[27..16];
-	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[] = FB_AD[28..16];
+	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
 	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
 -- VDL_HDB
 	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
 	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[27..16];
-	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[] = FB_AD[28..16];
+	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
 	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
 -- VDL_HDE
 	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
 	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[27..16];
-	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[] = FB_AD[28..16];
+	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
 	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
 -- VDL_HBB
 	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
 	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[27..16];
-	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[] = FB_AD[28..16];
+	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
 	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
 -- VDL_HSS
 	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
 	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[27..16];
-	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[] = FB_AD[28..16];
+	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
 	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
 -- VERTIKAL
 -- VDL_VBE
 	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
 	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[26..16];
-	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[] = FB_AD[28..16];
+	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
 	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
 -- VDL_VDB
 	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
 	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[26..16];
-	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[] = FB_AD[28..16];
+	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
 	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
 -- VDL_VDE
 	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
 	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[26..16];
-	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[] = FB_AD[28..16];
+	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
 	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
 -- VDL_VBB
 	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
 	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[26..16];
-	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[] = FB_AD[28..16];
+	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
 	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
 -- VDL_VSS
 	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
 	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[26..16];
-	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[] = FB_AD[28..16];
+	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
 	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
 -- VDL_VFT
 	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
 	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[26..16];
-	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[] = FB_AD[28..16];
+	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
 	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
 -- VDL_VCT
 	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
 	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[24..16];
-	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[] = FB_AD[28..16];
+	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
 	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
 -- VDL_VMD
 	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
@@ -438,177 +406,152 @@ BEGIN
 	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
 					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS & VDL_LOF[]
-					  # VDL_LWD_CS & VDL_LWD[]
-					  #	VDL_HBE_CS & (0,VDL_HBE[])
-					  #	VDL_HDB_CS & (0,VDL_HDB[])
-					  #	VDL_HDE_CS & (0,VDL_HDE[])
-					  #	VDL_HBB_CS & (0,VDL_HBB[])
-					  #	VDL_HSS_CS & (0,VDL_HSS[])
-					  #	VDL_HHT_CS & (0,VDL_HHT[])
-					  #	VDL_VBE_CS & (0,VDL_VBE[])
-					  #	VDL_VDB_CS & (0,VDL_VDB[])
-					  #	VDL_VDE_CS & (0,VDL_VDE[])
-					  #	VDL_VBB_CS & (0,VDL_VBB[])
-					  #	VDL_VSS_CS & (0,VDL_VSS[])
-					  #	VDL_VFT_CS & (0,VDL_VFT[])
-					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS & (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
- 					  #	ATARI_HH_CS & ATARI_HH[31..16]
-					  #	ATARI_VH_CS & ATARI_VH[31..16]
-					  #	ATARI_HL_CS & ATARI_HL[31..16]
-					  #	ATARI_VL_CS & ATARI_VL[31..16]
-					  #	CCR_CS & (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
-					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
-					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
-					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
-
+					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS 				& VDL_LOF[]
+					  # VDL_LWD_CS 				& WPL[]
+					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
+					  # VDL_PH_CS  				& (0,HDIS_LEN[])
+					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
+					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
+					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
+					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
+					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
+					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
+					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
+					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
+					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
+					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
+					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
+					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
+					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
+					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
+ 					  #	CCR_CS 					& (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
  	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
-					  #	ATARI_HH_CS & ATARI_HH[15..0]
-					  #	ATARI_VH_CS & ATARI_VH[15..0]
-					  #	ATARI_HL_CS & ATARI_HL[15..0]
-					  #	ATARI_VL_CS & ATARI_VL[15..0]
- 					  #	CCR_CS & CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
-
-	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
-			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
-				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
-				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-	
--- VIDEO AUSGABE SETZEN
+ 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
+ 					  #	CCR_CS 					& CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
+	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
+-- VIDEO AUSGABE SETZEN --------------------------------------------------------------
 	CLK17M.CLK = CLK33M;
 	CLK17M = !CLK17M;
 	CLK13M.CLK = CLK25M;
 	CLK13M = !CLK13M;
-	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
-			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
---------------------------------------------------------------
--- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
-----------------------------------------------------------------
+	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
+	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9];
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -----------------------------------------------------
 	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
-			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
-			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
-			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
-			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
-
- 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
-			# 4  & !ST_VIDEO & !VDL_VMD2
-			# 16 &  ST_VIDEO &  VDL_VMD2
-			# 32 &  ST_VIDEO & !VDL_VMD2;
-	 	
-	 	
-	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
-			   #  640 & !VDL_VMD2;
-					
--- DOPPELZEILENMODUS
-	DOP_ZEI.CLK = MAIN_CLK;
-	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
+			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
+			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
+			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
+			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
+-- MULTIPLIKATIONS FAKTOR ----------------------------------------
+ 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
+			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
+			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
+			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
+			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
+ -- BREITE IN PIXELN ------------------------------------------------	 	
+	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
+			   #  640 & !TE							& !ACP_VIDEO_ON
+			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
+	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
+		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
+		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
+-- DOPPELZEILENMODUS ---------------------------------------------
 	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
-	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
 	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
-					
-	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
-					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
-	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
-					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
-					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
-	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
-					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
-					
-	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
-					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
-					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
-					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
-					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
-					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
-					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
-					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
-	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
-	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
-					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
-					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
-					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
--- ZÄHLER
+	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER UNGERADEN ZEILEN
+	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN FÜR DOP.ZEI.FIFO
+-- TIMING HORIZONTAL				
+	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
+	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
+					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
+	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
+					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
+					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
+	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
+					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
+	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
+					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
+-- TIMING VERTICAL 					
+	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
+					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
+					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
+					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
+-- ZÄHLER ---------------------------------------------------------------------------
 	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[]-2);
+	LAST = VHCNT[]==(H_TOTAL[] - 1);
 	VHCNT[].CLK = PIXEL_CLK;
 	VHCNT[] = (VHCNT[] + 1) & !LAST;
 	VVCNT[].CLK = PIXEL_CLK;
 	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
 -- DISPLAY ON OFF
 	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
-	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
 	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
 	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
 	DISP_ON.CLK = PIXEL_CLK;
 	DISP_ON = DISP_ON & !DPO_OFF 
 			# DPO_ON & DPO_ZL;
 -- DATENTRANSFER ON OFF
 	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
 	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
 	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
-	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
 	VDTRON.CLK = PIXEL_CLK;
 	VDTRON = VDTRON & !VDO_OFF
 		   # VDO_ON & VDO_ZL;
 -- VERZÖGERUNG UND SYNC	
 	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_START = VHCNT[]==HS_START[] - 2;
 	HSYNC_I[].CLK = PIXEL_CLK;
 	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
 			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_START.CLK = PIXEL_CLK;
-	VSYNC_START.ENA = LAST;
-	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
 	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
-	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
-			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
+	VSYNC_I[].CLK = PIXEL_CLK;
 	VERZ[][].CLK = PIXEL_CLK;
 	VERZ[][1] = VERZ[][0];
 	VERZ[][2] = VERZ[][1];
@@ -620,11 +563,10 @@ BEGIN
 	VERZ[][8] = VERZ[][7];
 	VERZ[][9] = VERZ[][8];
 	VERZ[0][0] = DISP_ON;
---	VERZ[1][0] = HSYNC_I[]!=0;
-	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
-	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
-				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
+				# VDL_VCT6 & HSYNC_I[]==0;	
+	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
+				# VDL_VCT5 & VSYNC_I[]==0;	
 	nBLANK.CLK = PIXEL_CLK;
 	nBLANK =  VERZ[0][8];
 	HSYNC.CLK = PIXEL_CLK;
@@ -645,10 +587,10 @@ BEGIN
 ----------------------------------------------------------
 	CLR_FIFO.CLK = PIXEL_CLK;
 	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE LÖSCHEN (GENUG FRÜH DAMIT ES GEFÜLLT WERDEN KANN BIS ZUR NEUEN ÜBERTRAGUNG) 
 	START_ZEILE.CLK = PIXEL_CLK;
 	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
 	SYNC_PIX.CLK = PIXEL_CLK;
 	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
 	SYNC_PIX1.CLK = PIXEL_CLK;
diff --git a/FPGA_by_Fredi/Video/Video.bdf b/FPGA_by_Fredi/Video/Video.bdf
index 0df55be..8b108ab 100644
--- a/FPGA_by_Fredi/Video/Video.bdf
+++ b/FPGA_by_Fredi/Video/Video.bdf
@@ -6594,64 +6594,6 @@ applicable agreement for further details.
 		(line (pt 80 296)(pt 96 288)(line_width 1))
 	)
 )
-(symbol
-	(rect 2072 1176 2232 1320)
-	(text "lpm_fifoDZ" (rect 50 1 120 17)(font "Arial" (font_size 10)))
-	(text "inst63" (rect 8 128 37 140)(font "Arial" ))
-	(port
-		(pt 0 32)
-		(input)
-		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
-		(line (pt 0 32)(pt 16 32)(line_width 3))
-	)
-	(port
-		(pt 0 56)
-		(input)
-		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
-		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
-		(line (pt 0 56)(pt 16 56)(line_width 1))
-	)
-	(port
-		(pt 0 72)
-		(input)
-		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
-		(text "rdreq" (rect 20 66 50 80)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 16 72)(line_width 1))
-	)
-	(port
-		(pt 0 96)
-		(input)
-		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
-		(text "clock" (rect 26 90 55 104)(font "Arial" (font_size 8)))
-		(line (pt 0 96)(pt 16 96)(line_width 1))
-	)
-	(port
-		(pt 0 120)
-		(input)
-		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
-		(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
-		(line (pt 0 120)(pt 16 120)(line_width 1))
-	)
-	(port
-		(pt 160 32)
-		(output)
-		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
-		(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
-		(line (pt 160 32)(pt 144 32)(line_width 3))
-	)
-	(drawing
-		(text "(ack)" (rect 51 67 75 79)(font "Arial" ))
-		(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
-		(line (pt 16 16)(pt 144 16)(line_width 1))
-		(line (pt 144 16)(pt 144 128)(line_width 1))
-		(line (pt 144 128)(pt 16 128)(line_width 1))
-		(line (pt 16 128)(pt 16 16)(line_width 1))
-		(line (pt 16 108)(pt 144 108)(line_width 1))
-		(line (pt 16 90)(pt 22 96)(line_width 1))
-		(line (pt 22 96)(pt 16 102)(line_width 1))
-	)
-)
 (symbol
 	(rect 1712 1328 1872 1496)
 	(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
@@ -6726,253 +6668,144 @@ applicable agreement for further details.
 		(line (pt 22 120)(pt 16 126)(line_width 1))
 	)
 )
-(block
-	(rect 1664 1664 2016 2600)
-	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" ))	(block_io "nRSTO" (input))
-	(block_io "MAIN_CLK" (input))
-	(block_io "nFB_CS1" (input))
-	(block_io "nFB_CS2" (input))
-	(block_io "nFB_CS3" (input))
-	(block_io "nFB_WR" (input))
-	(block_io "nFB_OE" (input))
-	(block_io "FB_SIZE0" (input))
-	(block_io "FB_SIZE1" (input))
-	(block_io "nFB_BURST" (input))
-	(block_io "FB_ADR[31..0]" (input))
-	(block_io "CLK33M" (input))
-	(block_io "CLK25M" (input))
-	(block_io "BLITTER_RUN" (input))
-	(block_io "CLK_VIDEO" (input))
-	(block_io "VR_D[8..0]" (input))
-	(block_io "VR_BUSY" (input))
-	(block_io "COLOR8" (output))
-	(block_io "ACP_CLUT_RD" (output))
-	(block_io "COLOR1" (output))
-	(block_io "FALCON_CLUT_RDH" (output))
-	(block_io "FALCON_CLUT_RDL" (output))
-	(block_io "FALCON_CLUT_WR[3..0]" (output))
-	(block_io "ST_CLUT_RD" (output))
-	(block_io "ST_CLUT_WR[1..0]" (output))
-	(block_io "CLUT_MUX_ADR[3..0]" (output))
-	(block_io "HSYNC" (output))
-	(block_io "VSYNC" (output))
-	(block_io "nBLANK" (output))
-	(block_io "nSYNC" (output))
-	(block_io "nPD_VGA" (output))
-	(block_io "FIFO_RDE" (output))
-	(block_io "COLOR2" (output))
-	(block_io "COLOR4" (output))
-	(block_io "PIXEL_CLK" (output))
-	(block_io "CLUT_OFF[3..0]" (output))
-	(block_io "BLITTER_ON" (output))
-	(block_io "VIDEO_RAM_CTR[15..0]" (output))
-	(block_io "VIDEO_MOD_TA" (output))
-	(block_io "CCR[23..0]" (output))
-	(block_io "CCSEL[2..0]" (output))
-	(block_io "ACP_CLUT_WR[3..0]" (output))
-	(block_io "INTER_ZEI" (output))
-	(block_io "DOP_FIFO_CLR" (output))
-	(block_io "VIDEO_RECONFIG" (output))
-	(block_io "VR_WR" (output))
-	(block_io "VR_RD" (output))
-	(block_io "CLR_FIFO" (output))
-	(block_io "FB_AD[31..0]" (bidir))
-	(mapper
-		(pt 352 72)
-		(bidir)
-		)
-	(mapper
-		(pt 0 272)
-		(bidir)
-		)
-	(mapper
+(symbol
+	(rect 1656 1216 1720 1296)
+	(text "DFF" (rect 1 0 19 10)(font "Arial" (font_size 6)))
+	(text "inst101" (rect 3 68 38 80)(font "Arial" ))
+	(port
+		(pt 32 80)
+		(input)
+		(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
+		(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
+		(line (pt 32 80)(pt 32 76)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(text "CLK" (rect 3 29 20 41)(font "Courier New" (bold))(invisible))
+		(line (pt 0 40)(pt 12 40)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(text "D" (rect 14 20 19 32)(font "Courier New" (bold)))
+		(line (pt 0 24)(pt 12 24)(line_width 1))
+	)
+	(port
+		(pt 32 0)
+		(input)
+		(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
+		(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
+		(line (pt 32 4)(pt 32 0)(line_width 1))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
+		(line (pt 52 24)(pt 64 24)(line_width 1))
+	)
+	(drawing
+		(line (pt 12 12)(pt 52 12)(line_width 1))
+		(line (pt 12 68)(pt 52 68)(line_width 1))
+		(line (pt 52 68)(pt 52 12)(line_width 1))
+		(line (pt 12 68)(pt 12 12)(line_width 1))
+		(line (pt 19 40)(pt 12 47)(line_width 1))
+		(line (pt 12 32)(pt 20 40)(line_width 1))
+		(circle (rect 28 4 36 12)(line_width 1))
+		(circle (rect 28 68 36 76)(line_width 1))
+	)
+)
+(symbol
+	(rect 2072 1176 2232 1320)
+	(text "Doppelzeilen_Fifo" (rect 29 1 149 17)(font "Arial" (font_size 10)))
+	(text "inst98" (rect 8 128 37 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 87 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
 		(pt 0 56)
-		(bidir)
-		)
-	(mapper
-		(pt 0 80)
-		(bidir)
-		)
-	(mapper
-		(pt 0 296)
-		(bidir)
-		)
-	(mapper
-		(pt 0 104)
-		(bidir)
-		)
-	(mapper
-		(pt 0 128)
-		(bidir)
-		)
-	(mapper
-		(pt 0 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 176)
-		(bidir)
-		)
-	(mapper
-		(pt 0 248)
-		(bidir)
-		)
-	(mapper
-		(pt 0 200)
-		(bidir)
-		)
-	(mapper
-		(pt 0 224)
-		(bidir)
-		)
-	(mapper
-		(pt 0 520)
-		(bidir)
-		)
-	(mapper
-		(pt 0 544)
-		(bidir)
-		)
-	(mapper
-		(pt 0 880)
-		(bidir)
-		)
-	(mapper
-		(pt 352 600)
-		(bidir)
-		)
-	(mapper
-		(pt 352 624)
-		(bidir)
-		)
-	(mapper
-		(pt 352 648)
-		(bidir)
-		)
-	(mapper
-		(pt 352 672)
-		(bidir)
-		)
-	(mapper
-		(pt 352 696)
-		(bidir)
-		)
-	(mapper
-		(pt 352 720)
-		(bidir)
-		)
-	(mapper
-		(pt 352 840)
-		(bidir)
-		)
-	(mapper
-		(pt 352 472)
-		(bidir)
-		)
-	(mapper
-		(pt 352 448)
-		(bidir)
-		)
-	(mapper
-		(pt 352 528)
-		(bidir)
-		)
-	(mapper
-		(pt 352 320)
-		(bidir)
-		)
-	(mapper
-		(pt 352 576)
-		(bidir)
-		)
-	(mapper
-		(pt 352 400)
-		(bidir)
-		)
-	(mapper
-		(pt 352 376)
-		(bidir)
-		)
-	(mapper
-		(pt 352 352)
-		(bidir)
-		)
-	(mapper
-		(pt 352 504)
-		(bidir)
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-		(bidir)
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-	(mapper
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-		(bidir)
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-	(mapper
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-	(mapper
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-		(bidir)
-		)
-	(mapper
-		(pt 352 776)
-		(bidir)
-		)
-	(mapper
-		(pt 352 872)
-		(bidir)
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-	(mapper
-		(pt 0 496)
-		(bidir)
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-	(mapper
-		(pt 352 88)
-		(bidir)
-		)
-	(mapper
-		(pt 352 264)
-		(bidir)
-		)
-	(mapper
-		(pt 352 248)
-		(bidir)
-		)
-	(mapper
-		(pt 352 232)
-		(bidir)
-		)
-	(mapper
-		(pt 352 216)
-		(bidir)
-		)
-	(mapper
-		(pt 352 136)
-		(bidir)
-		)
-	(mapper
-		(pt 352 40)
-		(bidir)
-		)
-	(mapper
-		(pt 352 152)
-		(bidir)
-		)
-	(mapper
-		(pt 0 472)
-		(bidir)
-		)
-	(mapper
-		(pt 0 456)
-		(bidir)
-		)
-	(mapper
-		(pt 352 104)
-		(bidir)
-		)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 55 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 66 50 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 90 55 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 114 41 128)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 26 148 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(text "128 bits x 512 words" (rect 58 116 159 128)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 128)(line_width 1))
+		(line (pt 144 128)(pt 16 128)(line_width 1))
+		(line (pt 16 128)(pt 16 16)(line_width 1))
+		(line (pt 16 108)(pt 144 108)(line_width 1))
+		(line (pt 16 90)(pt 22 96)(line_width 1))
+		(line (pt 22 96)(pt 16 102)(line_width 1))
+	)
+)
+(symbol
+	(rect 1856 1208 1920 1256)
+	(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "inst99" (rect 3 37 32 49)(font "Arial" ))
+	(port
+		(pt 0 16)
+		(input)
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
+		(line (pt 0 16)(pt 14 16)(line_width 1))
+	)
+	(port
+		(pt 0 32)
+		(input)
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible))
+		(line (pt 0 32)(pt 14 32)(line_width 1))
+	)
+	(port
+		(pt 64 24)
+		(output)
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
+		(line (pt 42 24)(pt 64 24)(line_width 1))
+	)
+	(drawing
+		(line (pt 14 12)(pt 30 12)(line_width 1))
+		(line (pt 14 37)(pt 31 37)(line_width 1))
+		(line (pt 14 12)(pt 14 37)(line_width 1))
+		(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)(line_width 1))
+	)
 )
 (block
 	(rect 296 1872 560 2536)
@@ -7300,6 +7133,259 @@ applicable agreement for further details.
 		(bidir)
 		)
 )
+(block
+	(rect 1664 1664 2016 2600)
+	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 170 19)(font "Arial" (font_size 8)))	(text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 154 934)(font "Arial" ))	(block_io "nRSTO" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nFB_BURST" (input))
+	(block_io "FB_ADR[31..0]" (input))
+	(block_io "CLK33M" (input))
+	(block_io "CLK25M" (input))
+	(block_io "BLITTER_RUN" (input))
+	(block_io "CLK_VIDEO" (input))
+	(block_io "VR_D[8..0]" (input))
+	(block_io "VR_BUSY" (input))
+	(block_io "COLOR8" (output))
+	(block_io "ACP_CLUT_RD" (output))
+	(block_io "COLOR1" (output))
+	(block_io "FALCON_CLUT_RDH" (output))
+	(block_io "FALCON_CLUT_RDL" (output))
+	(block_io "FALCON_CLUT_WR[3..0]" (output))
+	(block_io "ST_CLUT_RD" (output))
+	(block_io "ST_CLUT_WR[1..0]" (output))
+	(block_io "CLUT_MUX_ADR[3..0]" (output))
+	(block_io "HSYNC" (output))
+	(block_io "VSYNC" (output))
+	(block_io "nBLANK" (output))
+	(block_io "nSYNC" (output))
+	(block_io "nPD_VGA" (output))
+	(block_io "FIFO_RDE" (output))
+	(block_io "COLOR2" (output))
+	(block_io "COLOR4" (output))
+	(block_io "PIXEL_CLK" (output))
+	(block_io "CLUT_OFF[3..0]" (output))
+	(block_io "BLITTER_ON" (output))
+	(block_io "VIDEO_RAM_CTR[15..0]" (output))
+	(block_io "VIDEO_MOD_TA" (output))
+	(block_io "CCR[23..0]" (output))
+	(block_io "CCSEL[2..0]" (output))
+	(block_io "ACP_CLUT_WR[3..0]" (output))
+	(block_io "INTER_ZEI" (output))
+	(block_io "DOP_FIFO_CLR" (output))
+	(block_io "VIDEO_RECONFIG" (output))
+	(block_io "VR_WR" (output))
+	(block_io "VR_RD" (output))
+	(block_io "CLR_FIFO" (output))
+	(block_io "DPZF_CLKENA" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(mapper
+		(pt 352 72)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
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+	(mapper
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+		(bidir)
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+	(mapper
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+	(mapper
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+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 880)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 624)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 448)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 320)
+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 400)
+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 504)
+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 424)
+		(bidir)
+		)
+	(mapper
+		(pt 352 552)
+		(bidir)
+		)
+	(mapper
+		(pt 352 752)
+		(bidir)
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+	(mapper
+		(pt 352 776)
+		(bidir)
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+	(mapper
+		(pt 352 872)
+		(bidir)
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+	(mapper
+		(pt 0 496)
+		(bidir)
+		)
+	(mapper
+		(pt 352 88)
+		(bidir)
+		)
+	(mapper
+		(pt 352 264)
+		(bidir)
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+	(mapper
+		(pt 352 248)
+		(bidir)
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+	(mapper
+		(pt 352 232)
+		(bidir)
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+	(mapper
+		(pt 352 216)
+		(bidir)
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+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 352 40)
+		(bidir)
+		)
+	(mapper
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+		(bidir)
+		)
+	(mapper
+		(pt 0 472)
+		(bidir)
+		)
+	(mapper
+		(pt 0 456)
+		(bidir)
+		)
+	(mapper
+		(pt 352 104)
+		(bidir)
+		)
+	(mapper
+		(pt 352 800)
+		(bidir)
+		)
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 (connector
 	(text "CLUT_ADR0" (rect 2786 1272 2849 1284)(font "Arial" ))
 	(pt 2776 1288)
@@ -8629,11 +8715,6 @@ applicable agreement for further details.
 	(pt 2512 1568)
 	(pt 2512 1728)
 )
-(connector
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-	(pt 1640 1448)
-	(pt 1712 1448)
-)
 (connector
 	(text "PIXEL_CLK" (rect 1938 1424 1994 1436)(font "Arial" ))
 	(pt 1928 1440)
@@ -10289,22 +10370,6 @@ applicable agreement for further details.
 	(pt 1800 1160)
 	(bus)
 )
-(connector
-	(pt 1608 1432)
-	(pt 1608 1232)
-)
-(connector
-	(pt 1600 1432)
-	(pt 1608 1432)
-)
-(connector
-	(pt 1608 1432)
-	(pt 1712 1432)
-)
-(connector
-	(pt 1608 1232)
-	(pt 2072 1232)
-)
 (connector
 	(pt 2072 1248)
 	(pt 1944 1248)
@@ -10591,6 +10656,57 @@ applicable agreement for further details.
 	(pt 848 2744)
 	(pt 928 2744)
 )
+(connector
+	(pt 1920 1232)
+	(pt 2072 1232)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1608 1240)
+)
+(connector
+	(pt 1608 1240)
+	(pt 1656 1240)
+)
+(connector
+	(pt 1624 1256)
+	(pt 1656 1256)
+)
+(connector
+	(pt 1624 1448)
+	(pt 1624 1256)
+)
+(connector
+	(pt 1600 1432)
+	(pt 1608 1432)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1712 1432)
+)
+(connector
+	(pt 1608 1448)
+	(pt 1624 1448)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1634 1432 1690 1444)(font "Arial" ))
+	(pt 1624 1448)
+	(pt 1712 1448)
+)
+(connector
+	(pt 1720 1240)
+	(pt 1856 1240)
+)
+(connector
+	(text "DPZF_CLKENA" (rect 1754 1208 1833 1220)(font "Arial" ))
+	(pt 1856 1224)
+	(pt 1744 1224)
+)
+(connector
+	(text "DPZF_CLKENA" (rect 2026 2448 2105 2460)(font "Arial" ))
+	(pt 2128 2464)
+	(pt 2016 2464)
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 (junction (pt 2984 1688))
 (junction (pt 792 1192))
 (junction (pt 792 1312))
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 (junction (pt 3232 3024))
 (junction (pt 1968 1424))
 (junction (pt 1608 1432))
+(junction (pt 1624 1448))
diff --git a/FPGA_by_Fredi/Video/altdpram0_wave0.jpg b/FPGA_by_Fredi/Video/altdpram0_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/altdpram0_waveforms.html b/FPGA_by_Fredi/Video/altdpram0_waveforms.html
deleted file mode 100644
index e0236fd..0000000
--- a/FPGA_by_Fredi/Video/altdpram0_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram0.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram0.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram0_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/altdpram1_wave0.jpg b/FPGA_by_Fredi/Video/altdpram1_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/altdpram1_waveforms.html b/FPGA_by_Fredi/Video/altdpram1_waveforms.html
deleted file mode 100644
index 85b4369..0000000
--- a/FPGA_by_Fredi/Video/altdpram1_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram1_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
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diff --git a/FPGA_by_Fredi/Video/altdpram2_wave0.jpg b/FPGA_by_Fredi/Video/altdpram2_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/altdpram2_waveforms.html b/FPGA_by_Fredi/Video/altdpram2_waveforms.html
deleted file mode 100644
index a856bf6..0000000
--- a/FPGA_by_Fredi/Video/altdpram2_waveforms.html
+++ /dev/null
@@ -1,16 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for altdpram2.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file altdpram2.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b. </P>
-<CENTER><img src=altdpram2_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
-<CENTER><img src=altdpram2_wave1.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address. </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg b/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg
deleted file mode 100644
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diff --git a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
deleted file mode 100644
index e8242d9..0000000
--- a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for lpm_compare1.vhd </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file lpm_compare1.vhd </CENTER></h2>
-<P>The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator. </P>
-<CENTER><img src=lpm_compare1_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing comparator operation. </CENTER></P>
-<P><FONT size=3></P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg
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diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
deleted file mode 100644
index 956161a..0000000
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifoDZ.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifoDZ.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd".  The design "lpm_fifoDZ.vhd" has a depth of 512 words of 128 bits each. The fifo is in show-ahead synchronous mode.  The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
-<CENTER><img src=lpm_fifoDZ_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg
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zPg6`=L(M;q`>rS=ha<FsIjhrN|7P##aF)oXMeZRt`MwN?5<6gJLY&_b?iZXVleVM8
zeO}OPkEEvrhm<<*+q3-wpX@ePxuXjnCEh<ht8hwnnDV^!;l+;e_j1I+{2WQSuWcEh
z!S~H^HwzVsaj$iJ;HzGfjn(%CuJ701)WN5qHn5+KZVZ!OKJ2Li)9mgHVVnNnpbz2m
z3)|p3VX|^8=u0#o1_j+%>RZ)6HxZOjhb5q78)Fk7Iqt6!C;y|#o51VEnL&est4o@|
zpHM@?%>r%VmzmKi{WP%%9@QXQLBqF!wi~ZOs1|C2HCGs$I;D3Dw3e>PS_(q72;%p*
zmODU_dsYFEkKWUHue`SO%F6E)q<Wz4Tu$l7S;ZS?Ao5$|2<*m|!qelee@XjMHn4th
zOrKdePGe+yC|BBO?<8acl5~d$Q-q%grt0H|A7!^YLI5-PcWrn7!v3YQvd8A7f*Jmc
zdy1N$0vMRXSkp}%)`SGo=0Lk%Rgsxjmw?v%A0=_IG3%alr3P;Khqknj)}p0P$N|+b
z`73O4e4?gAsVjK^<0W`x8eliPfWhNGQSXjPK`)~(ZrFdDh(A*lD_8BWro|>KUs)se
zFR&rvujt#67ozrW4B8fiF^G+!xF3^M0zSlovypS>+%vKsHpU3=?cEb{Y5Sl}J@+U+
zqPOLp!GyJ=KOeEi+!6}N5eX!t+-K#VFFd=!`gEny9$U7}X2Rhroo~~3W05*^i(7LP
zOW`K^^4NO<+bpg4AtebOQ3ydKM?or#jIvN?1qmEDPX&6MX-kt3y23`VtzG2n?<V)>
zq;|O;?M;1x_wB7+w?O;Jk|=In9|XwvT2;$ayAFuAE+nODaMDK}6-nhu6=zt(GTE@*
z*qsX=3Wghd_mM6$z!!KYrb>OnM`@_;glPd_GR2|uitgsI=eqI#qFPYg#WjGalgViM
zQrQ9#`c(wFS80CT2PoaN{QE6?8fq<VVcX{Piu?SI#PP?Ffh6;G#imYQElH&e&(L=A
zFjh0tV**E<wIRLO9=goq@{B7?Gd(jMC~}H;X>2vwr0(e?l~6p1iV9C?aQwv8tIyeE
z&a*rCGQ88=C|{D5I2es)K-H#27SVC#=MET1y*X!{h57BriRsR}qw&94eamSt-OYsm
z+Z273FD2LTMDW{wH9gc*>)upK|56!Zx7tX$T+})=s*{ARG6KBC9n2PMwe|7ECFm<s
zm<#Pp8YJfG)-2n9mW2;l-?DtJDxM}d6*V}bdTl<MNqLtRqiCIe2FhQ|i{N5$%|}Cp
z@H1P!#=|GmfTj1`eWOJ7cS=jiw$t!1DCCJauUIw?M~#JTbFNbltI04jE-aFEujD{S
z=m5@e!(S<EC+kJdg=M4E*8KTI0iM-lexrn>?@E#<?{}MQtYNM7LDOiN8_{R4L|%+G
z`)0*1z%?MfGB!lN{T64oPa06-SKmAn<U%i;uxqI2dGIjZ&f!#F<4OemdZ3YSrR7b~
z#ec5>`%(NOx~MxGObKDyol(|tK7HaCWZaDWSdWE?BMM2*Tu{k)j`MrDp7CdV-W>Wb
DLMQw4

diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
deleted file mode 100644
index 20c4da2..0000000
--- a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html
+++ /dev/null
@@ -1,13 +0,0 @@
-<html>
-<head>
-<title>Sample Waveforms for "lpm_fifo_dc0.vhd" </title>
-</head>
-<body>
-<h2><CENTER>Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd" </CENTER></h2>
-<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd".  The design "lpm_fifo_dc0.vhd" has a depth of 2048 words of 128 bits each. The fifo is in legacy synchronous mode.  The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request. </P>
-<CENTER><img src=lpm_fifo_dc0_wave0.jpg> </CENTER>
-<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
-<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
-<P></P>
-</body>
-</html>
diff --git a/FPGA_by_Fredi/Video/shiftreg_dpz.bsf b/FPGA_by_Fredi/Video/shiftreg_dpz.bsf
new file mode 100644
index 0000000..aab135b
--- /dev/null
+++ b/FPGA_by_Fredi/Video/shiftreg_dpz.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "shiftreg_dpz" (rect 37 1 119 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_by_Fredi/Video/shiftreg_dpz.inc b/FPGA_by_Fredi/Video/shiftreg_dpz.inc
new file mode 100644
index 0000000..e9502e6
--- /dev/null
+++ b/FPGA_by_Fredi/Video/shiftreg_dpz.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION shiftreg_dpz 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ.qip b/FPGA_by_Fredi/Video/shiftreg_dpz.qip
similarity index 63%
rename from FPGA_by_Fredi/Video/lpm_fifoDZ.qip
rename to FPGA_by_Fredi/Video/shiftreg_dpz.qip
index 5444627..dc996ca 100644
--- a/FPGA_by_Fredi/Video/lpm_fifoDZ.qip
+++ b/FPGA_by_Fredi/Video/shiftreg_dpz.qip
@@ -1,5 +1,5 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
 set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "shiftreg_dpz.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "shiftreg_dpz.inc"]
diff --git a/FPGA_by_Fredi/Video/shiftreg_dpz.vhd b/FPGA_by_Fredi/Video/shiftreg_dpz.vhd
new file mode 100644
index 0000000..8037081
--- /dev/null
+++ b/FPGA_by_Fredi/Video/shiftreg_dpz.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: shiftreg_dpz.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY shiftreg_dpz IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END shiftreg_dpz;
+
+
+ARCHITECTURE SYN OF shiftreg_dpz IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 3
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL shiftreg_dpz_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_by_Fredi/blitter.tdf b/FPGA_by_Fredi/blitter.tdf
index 740423e..46f027c 100644
--- a/FPGA_by_Fredi/blitter.tdf
+++ b/FPGA_by_Fredi/blitter.tdf
@@ -23,6 +23,8 @@ INCLUDE "lpm_bustri_WORD.inc";
 INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
 INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
 INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
+INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
+
 
 --CONSTANT	BL_SKEW_LF = 255;
 
@@ -71,66 +73,70 @@ SUBDESIGN BLITTER
 
 VARIABLE
 	BYT							:NODE;
-	LONGLINE					:NODE;
-	W_ADR[18..0]				:NODE;
 	FB_16B[1..0]				:NODE;
-	W_A1						:DFFE;
 	BLITTER_CS					:NODE;
 	BL_HRAM_CS 					:NODE;
+	DP_RAM_CS					:NODE;
 	BL_HRAM_BE[1..0]			:NODE;
 	BL_HRAM_OUT[15..0]			:NODE;
 	BL_DPRAM_OUT[15..0]			:NODE;
 	BL_SRC_X_INC_CS				:NODE;
 	BL_SRC_X_INC[15..0]			:DFFE;
-	SRC_XINC_NODE[31..0]		:NODE;
+	SRC_ADR_INC[31..0]			:NODE;
+	SRC_XINC32[31..0]			:NODE;
 	BL_SRC_Y_INC_CS				:NODE;
 	BL_SRC_Y_INC[15..0]			:DFFE;
-	SRC_YINC_NODE[31..0]		:NODE;
+	SRC_YINC32[31..0]			:NODE;
 	BL_ENDMASK1_CS				:NODE;
 	BL_ENDMASK1[15..0]			:DFFE;
 	BL_ENDMASK2_CS				:NODE;
 	BL_ENDMASK2[15..0]			:DFFE;
 	BL_ENDMASK3_CS				:NODE;
 	BL_ENDMASK3[15..0]			:DFFE;
+	BL_ENDMASK0[15..0]			:NODE;
+	BL_ENDMASKF[15..0]			:NODE;
+	BL_ENDMASKL[15..0]			:NODE;
+	BL_ENDMASKR[15..0]			:NODE;
 	BL_SRC_ADRH_CS				:NODE;
 	BL_SRC_ADRL_CS				:NODE;
 	BL_SRC_ADR[31..0]			:DFFE;
+	SRC_OLD[27..0]				:DFFE;
 	SRC_IADRH_CS				:NODE;
 	SRC_IADRL_CS				:NODE;
 	SRC_IADR[31..0]				:DFF;
-	SRC_IADR_CLR				:NODE;
-	SIINC						:NODE;
-	SRC_ADR_NODE[31..0]			:NODE;
+	SRC_IADR_CLR				:DFF;
+	SRC_ADR32[31..0]			:NODE;
 	BL_DST_X_INC_CS				:NODE;
 	BL_DST_X_INC[15..0]			:DFFE;
-	DST_XINC_NODE[31..0]		:NODE;
+	DST_ADR_INC[31..0]			:NODE;
+	DST_XINC32[31..0]			:NODE;
 	BL_DST_Y_INC_CS				:NODE;
 	BL_DST_Y_INC[15..0]			:DFFE;
-	DST_YINC_NODE[31..0]		:NODE;
+	DST_YINC32[31..0]			:NODE;
 	BL_DST_ADRH_CS				:NODE;
 	BL_DST_ADRL_CS				:NODE;
 	BL_DST_ADR[31..0]			:DFFE;
 	DST_IADRH_CS				:NODE;
 	DST_IADRL_CS				:NODE;
 	DST_IADR[31..0]				:DFF;
-	DST_IADR_CLR				:NODE;
-	DST_ADR_NODE[31..0]			:NODE;
-	DIINC						:NODE;
+	DST_IADR_CLR				:DFF;
+	DST_ADR32[31..0]			:NODE;
 	BL_X_CNT_CS					:NODE;
 	BL_X_CNT[15..0]				:DFFE;
-	X_CNT_NODE[15..0]			:NODE;
+	X_CNT16[15..0]				:NODE;
 	BL_Y_CNT_CS					:NODE;
 	BL_Y_CNT[15..0]				:DFFE;
 	BL_HOP_CS					:NODE;
 	BL_HOP[7..0]				:DFFE;
 	BL_OP[7..0]					:DFFE;
 	BL_LN_CS					:NODE;
-	LN7CLR						:NODE;
+	BL_LN_WR					:NODE;
+	LN7_CLR						:NODE;
 	BL_LN[7..0]					:DFFE;
 	BL_SKEW[7..0]				:DFFE;
 -- barell shifter
 	DIST_RIGHT[8..0]			:NODE;
-	BL_BS_SKEW[7..0]			:NODE;
+	BS_SKEW[7..0]				:NODE;
 	BL_BSIN[383..0]				:NODE;
 	BL_BSOUT[383..0]			:NODE;
 	SHIFT_DIR					:NODE;
@@ -145,15 +151,17 @@ VARIABLE
 	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
 	X_INDEX_CS					:NODE;
 	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
-	X_INDEX_CLR					:NODE;
+	X_INDEX_CLR					:DFF;				-- X INDEX LÖSCHEN CPU WRITE
+	X_INDEX_CLR_DIR				:NODE;				-- X INDEX LÖSCHEN STATE MACHINE
+	DST_X_INC[15..0]			:NODE;				-- ANZAHL WORTE PRO DURCHLAUF
+	X_CNT_T[15..0]				:NODE;
 	Y_INDEX_CS					:NODE;
 	Y_INDEX[15..0]				:DFF;				-- LAUFZEIGER Y COUNT
-	Y_INDEX_CLR					:NODE;
+	Y_INDEX_CLR					:DFF;
 	LINE_NR[3..0]				:NODE;
-	XIINC						:NODE;				-- INC INDEX SPALTE
+	SDXINC						:DFF;				-- INC INDEX SPALTE
 	YIINC						:NODE;				-- INC INDEX ZEILE
-	ZIINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
-	ZYINC						:NODE;				-- KORREKTUR ADRESSEN WENN FERTIG
+	ZAINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
 	HOP_OUT[127..0]				:NODE;
 	OP_OUT[127..0]				:NODE;
 	ENDMASK1_SHIFT[7..0]		:NODE;
@@ -162,24 +170,22 @@ VARIABLE
 	ENDMASK12_OUT[143..0]		:NODE;
 	ENDMASK23_IN[143..0]		:NODE;
 	ENDMASK23_OUT[143..0]		:NODE;
-	ENDMASK123[127..0]			:NODE;
-	ENDMASKEND[15..0]			:NODE;
-	SRC_DDR_ADR[31..0]			:NODE;
-	DST_DDR_ADR[31..0]			:NODE;
-	BLITTER_REQ					:DFF;
+	ENDMASKM_IN[127..0]			:NODE;
+	ENDMASKM_OUT[127..0]		:NODE;
+	ROR_CNT[8..0]				:NODE;
+	ENDMASK123[127..0]			:DFF;
+	ENDMASKEND[31..0]			:NODE;
+	BLITTER_SIG					:DFF;
+	BLITTER_REQ					:NODE;
+	BL_START					:DFF;
+	BL_NOTRUN					:NODE;
 	
 -- MAIN STATE MACHINE
-	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
 	
 BEGIN
 -- BYT UND WORD SELECT 16 BIT
 	BYT      = !FB_SIZE1 &  FB_SIZE0;
-	LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; 	-- LONG OR LINE
-	W_A1.CLK = MAIN_CLK;
-	W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
-	W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE;			-- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST
-	W_ADR[18..1] = FB_ADR[19..2];
-	W_ADR0 = W_A1;  
 	FB_16B0 = FB_ADR[0]==0;										-- wenn ADR==0
 	FB_16B1 = FB_ADR[0]==1 # !BYT;								-- wenn ADR==1 or NOT BYT
 -- BLITTER CS
@@ -191,156 +197,229 @@ BEGIN
 	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
 	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
 	WREN_B = B"0";
-	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
-	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15));
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528";							-- $F8A50.w
 	-- SRC X INC
 	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[] = FB_AD[31..16];
-	BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510";						-- $F8A20.w
+	BL_SRC_X_INC[15..1] = FB_AD[31..17];
+	BL_SRC_X_INC0 = GND;
+	BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510");						-- $F8A20.w
 	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	SRC_XINC32[15..0]  = BL_SRC_X_INC[];											-- ERWEITERN AUF 32 BIT
+	SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15;									-- ERWEITERN AUF 32 BIT
 	-- SRC Y INC
 	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[] = FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511";						-- $F8A22.w
+	BL_SRC_Y_INC[15..1] = FB_AD[31..17];
+	BL_SRC_Y_INC0 = GND;
+	BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511");						-- $F8A22.w
 	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	SRC_YINC32[15..0]  = BL_SRC_Y_INC[];											-- ERWEITERN AUF 32 BIT
+	SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15;									-- ERWEITERN AUF 32 BIT
 	-- SRC ADR HIGH
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512";						-- $F8A24.w
+	BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512");						-- $F8A24.w
 	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
 	-- SRC ADR LOW
 	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..0] = FB_AD[31..16];
-	BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513";						-- $F8A26.w
+	BL_SRC_ADR[15..1] = FB_AD[31..17];
+	BL_SRC_ADR0 = GND;
+	BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513");						-- $F8A26.w
 	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
 	SRC_IADR[].CLK = DDRCLK0;
-	SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520";						-- $F8A40.w
-	SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521";						-- $F8A42.w
+	SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520");							-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521");							-- $F8A42.w
+	SRC_IADR_CLR.CLK = MAIN_CLK;
 	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
-	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
-	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
+	SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH 
 	-- ENDMASK 1
 	BL_ENDMASK1[].CLK = MAIN_CLK;
 	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514";						-- $F8A28.w
+	BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514");						-- $F8A28.w
 	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 2
 	BL_ENDMASK2[].CLK = MAIN_CLK;
 	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515";						-- $F8A2A.w
+	BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515");						-- $F8A2A.w
 	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 3
 	BL_ENDMASK3[].CLK = MAIN_CLK;
 	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516";						-- $F8A2C.w
+	BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516");						-- $F8A2C.w
 	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
 	-- DST X INC
 	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[] = FB_AD[31..16];
-	BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517";						-- $F8A2E.w
+	BL_DST_X_INC[15..1] = FB_AD[31..17];
+	BL_DST_X_INC0 = GND;
+	BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517");						-- $F8A2E.w
 	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	DST_XINC32[15..0]  = BL_DST_X_INC[];											-- ERWEITERN AUF 32 BIT
+	DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15;									-- ERWEITERN AUF 32 BIT
 	-- DST Y INC
 	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[] = FB_AD[31..16];
-	BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518";						-- $F8A30.w
+	BL_DST_Y_INC[15..1] = FB_AD[31..17];
+	BL_DST_Y_INC0 = GND;
+	BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518");						-- $F8A30.w
 	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	DST_YINC32[15..0]  = BL_DST_Y_INC[];											-- ERWEITERN AUF 32 BIT
+	DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15;									-- ERWEITERN AUF 32 BIT
 	-- DST ADR HIGH
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519";						-- $F8A32.w
+	BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519");						-- $F8A32.w
 	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
 	-- DST ADR LOW
 	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..0] = FB_AD[31..16];
-	BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A";						-- $F8A34.w
+	BL_DST_ADR[15..1] = FB_AD[31..17];
+	BL_DST_ADR0 = GND;
+	BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A");						-- $F8A34.w
 	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
 	DST_IADR[].CLK = DDRCLK0;
-	DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522";						-- $F8A44.w
-	DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523";						-- $F8A46.w
-	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
-	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
-	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522");							-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523");							-- $F8A46.w
+	DST_IADR_CLR.CLK = MAIN_CLK;					
+	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;					-- LÖSCHEN BEI WRITE
+	DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
+	DST_ADR32[] = BL_DST_ADR[] + DST_IADR[];									-- ZUGRIFFSADRESSE THEORETISCH
 	-- X COUNT
 	BL_X_CNT[].CLK = MAIN_CLK;
 	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B";							-- $F8A36.w
+	BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B");							-- $F8A36.w
 	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
 	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
 	X_INDEX[].CLK = DDRCLK0;
-	X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524";							-- $F8A48.w
-	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
-	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
-	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
+	X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524");							-- $F8A48.w
+	X_INDEX_CLR.CLK = MAIN_CLK;
+	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
+	X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
+	X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0));		-- EFFEKTIV geschrieben
+-- SCHRITTWEITEN BEI PALLETTENMOD
+	IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 4) THEN 
+		DST_X_INC[] = 1;
+		X_CNT_T[] = 0;
+		SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
+		DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
+	ELSE		
+		IF BL_SRC_X_INC[] == H"0002" THEN 
+			DST_X_INC[] = 8;
+			X_CNT_T[] = (0,DST_ADR32[3..1]);
+			SRC_ADR_INC[] = 16;						-- SRC X INC
+			DST_ADR_INC[] = 16;						-- DST X INC
+		ELSE
+			IF BL_SRC_X_INC[] == H"FFFE" THEN 
+				DST_X_INC[] = 8;
+				X_CNT_T[] = 7 - (0,DST_ADR32[3..1]);
+				SRC_ADR_INC[] = -16;				-- SRC X INC
+				DST_ADR_INC[] = -16;				-- DST X INC
+			ELSE							
+				IF BL_SRC_X_INC[] == H"0004" THEN 
+					DST_X_INC[] = 4;
+					X_CNT_T[] = (0,DST_ADR32[3..2]);
+					SRC_ADR_INC[] = 16;						-- SRC X INC
+					DST_ADR_INC[] = 16;						-- DST X INC
+				ELSE
+					IF BL_SRC_X_INC[] == H"FFFC" THEN 
+						DST_X_INC[] = 4;
+						X_CNT_T[] = 3 - (0,DST_ADR32[3..2]);
+						SRC_ADR_INC[] = -16;				-- SRC X INC
+						DST_ADR_INC[] = -16;				-- DST X INC
+					ELSE							
+						IF BL_SRC_X_INC[] == H"0008" THEN 
+							DST_X_INC[] = 2;
+							X_CNT_T[] = (0,DST_ADR32[3]);
+							SRC_ADR_INC[] = 16;						-- SRC X INC
+							DST_ADR_INC[] = 16;						-- DST X INC
+						ELSE
+							IF BL_SRC_X_INC[] == H"FFF8" THEN 
+								DST_X_INC[] = 2;
+								X_CNT_T[] = 1 - (0,DST_ADR32[3]);
+								SRC_ADR_INC[] = -16;				-- SRC X INC
+								DST_ADR_INC[] = -16;				-- DST X INC
+							ELSE							
+								DST_X_INC[] = 1;
+								X_CNT_T[] = 0;
+								SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
+								DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
+							END IF;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+		END IF;
+	END IF;
 	-- Y COUNT
 	BL_Y_CNT[].CLK = MAIN_CLK;
 	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C";							-- $F8A38.w
+	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";							-- $F8A38.w
 	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
 	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
 	Y_INDEX[].CLK = DDRCLK0;
-	Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525";							-- $F8A4A.w
-	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";							-- $F8A4A.w
+	Y_INDEX_CLR.CLK = MAIN_CLK;
+	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
 	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
 	-- HOP LOGIC
 	BL_HOP[].CLK = MAIN_CLK;
 	BL_HOP[] = FB_AD[31..24];
-	BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D";							-- $F8A3A.w
-	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
+	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";								-- $F8A3A.w
+	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;							-- $F8A3A
 	-- OP LOGIC
 	BL_OP[].CLK = MAIN_CLK;
 	BL_OP[] = FB_AD[23..16];
-	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
+	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;							-- $F8A3B
 	-- LINE NUMBER BYT
 	BL_LN[].CLK = MAIN_CLK;
-	BL_LN[6..0] = FB_AD[30..24];	
-	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
-	BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E";							-- $F8A3C.w
-	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
-	BL_LN7.ENA = LN7CLR;
+	BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E");							-- $F8A3C.w
+	BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0;									-- $F8A3C WRITE SIGNAL
+	BL_LN[6..0] = FB_AD[30..24];												-- HOG UND SMUDGE
+	BL_LN[6..0].ENA  = BL_LN_WR;													-- $F8A3C
+	BL_LN7.ENA  = BL_LN_WR # LN7_CLR;													-- $F8A3C
+	BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY 
+	BL_START.CLK = MAIN_CLK;
+	BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; 
 	-- SKEW BYT
 	BL_SKEW[].CLK = MAIN_CLK;
 	BL_SKEW[] = FB_AD[23..16];
-	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
+	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;								-- $F8A3D
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
 						BL_HRAM_CS	    & BL_DPRAM_OUT[]
 					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
 					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & SRC_ADR_NODE[31..16]
-					  # BL_SRC_ADRL_CS  & SRC_ADR_NODE[15..0]
+					  # BL_SRC_ADRH_CS  & SRC_ADR32[31..16]
+					  # BL_SRC_ADRL_CS  & SRC_ADR32[15..0]
 					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
 					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
 					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
 					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
 					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & DST_ADR_NODE[31..16]
-					  # BL_DST_ADRL_CS  & DST_ADR_NODE[15..0]
+					  # BL_DST_ADRH_CS  & DST_ADR32[31..16]
+					  # BL_DST_ADRL_CS  & DST_ADR32[15..0]
 					  # BL_X_CNT_CS 	& (BL_X_CNT[]-X_INDEX[])
 					  # BL_Y_CNT_CS 	& (BL_Y_CNT[]-Y_INDEX[])
 					  # BL_HOP_CS 		& (BL_HOP[],BL_OP[])
-					  # BL_LN_CS 		& (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])		
+					  # BL_LN_CS 		& (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[])		
 					  # SRC_IADRH_CS	& SRC_IADR[31..16]
 					  # SRC_IADRL_CS	& SRC_IADR[15..0]
 					  # DST_IADRH_CS	& DST_IADR[31..16]
 					  # DST_IADRL_CS	& DST_IADR[15..0]
 					  # X_INDEX_CS		& X_INDEX[]
 					  # Y_INDEX_CS		& Y_INDEX[]
-					  ,BLITTER_CS & !nFB_OE); 							-- FFFF8A00-7F
+					  # DP_RAM_CS		& BL_HRAM_OUT[]
+					  ,BLITTER_CS & !nFB_OE); 									-- FFFF8A00-7F
 --------------------------------------------------------------------------------------
 -- SRC BUFFER LADEN
 	BL_SRC_BUF1[].CLK = DDRCLK0;
@@ -355,34 +434,11 @@ BEGIN
 	BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
 	BL_SRC_BUF3[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
 	BL_SRC_BUF3[] = BL_SRC_BUF2[];
-	-- ZUORDNUNG ---------
+	-- ZUORDNUNG ---------------------------------------------------
 	IF BL_SRC_X_INC15 THEN		-- WENN NEGATIV -> REIHENFOLGE KEHREN
-		CASE BL_HOP[7..4] IS	-- SPIEGELN?
-			WHEN H"0" =>		-- LINE WEISE
-				BL_BSIN[127..0]   = BL_SRC_BUF3[];
-				BL_BSIN[255..128] = BL_SRC_BUF2[];
-				BL_BSIN[383..256] = BL_SRC_BUF1[];
-			WHEN H"1" =>		--- BIT WEISE
-				BL_BSIN[0..127]   = BL_SRC_BUF3[];
-				BL_BSIN[128..255] = BL_SRC_BUF2[];
-				BL_BSIN[256..383] = BL_SRC_BUF1[];
-			WHEN H"2" =>		-- BYT WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
-			WHEN H"3" =>		-- WORD WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
-			WHEN H"4" =>		-- LONG WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
-			WHEN OTHERS =>		-- LINE WEISE
-				BL_BSIN[127..0]   = BL_SRC_BUF3[];
-				BL_BSIN[255..128] = BL_SRC_BUF2[];
-				BL_BSIN[383..256] = BL_SRC_BUF1[];
-		END CASE;
+		BL_BSIN[127..0]   = BL_SRC_BUF3[];
+		BL_BSIN[255..128] = BL_SRC_BUF2[];
+		BL_BSIN[383..256] = BL_SRC_BUF1[];
 	ELSE						-- SONST NORMAL BEI VORWÄRTS
 		BL_BSIN[127..0]   = BL_SRC_BUF1[];
 		BL_BSIN[255..128] = BL_SRC_BUF2[];
@@ -395,16 +451,16 @@ BEGIN
 	BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
 -- barell shift *****************************************************************************
 -- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
-	DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
-	IF DIST_RIGHT8 == 0 THEN 		
-		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
-		SHIFT_DIR = VCC;									-- DIR = RIGHT
-	else													
-		BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; 				-- LPM SHIFT LEFT
+	DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
+	IF DIST_RIGHT8 THEN 		
+		BS_SKEW[] = 0 - DIST_RIGHT[7..0]; 					-- LPM SHIFT LEFT
 		SHIFT_DIR = GND;									-- DIR = LEFT
+	else													
+		BS_SKEW[] = DIST_RIGHT[7..0]; 						-- LPM SHIFT RIGHT
+		SHIFT_DIR = VCC;									-- DIR = RIGHT
 	end if;
 -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
-	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]);	-- wir brauchen 128bit
+	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]);	-- wir brauchen 128bit
 -- HOP ***************************************************************************************
 	CASE BL_HOP[1..0] IS
 		WHEN H"0" =>
@@ -423,47 +479,47 @@ BEGIN
 			OP_OUT[] = H"0";
 			SRC_READ = B"0";
 		WHEN H"1" =>
-			OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"2" =>
-			OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"3" =>
 			OP_OUT[] = HOP_OUT[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			SRC_READ = BL_HOP1;
 		WHEN H"4" =>
-			OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"5" =>
 			OP_OUT[] = BL_DST_BUFRD[];
 			SRC_READ = B"0";
 		WHEN H"6" =>
-			OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"7" =>
-			OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"8" =>
-			OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"9" =>
-			OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"A" =>
 			OP_OUT[] = !BL_DST_BUFRD[];
 			SRC_READ = B"0";
 		WHEN H"B" =>
-			OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"C" =>
 			OP_OUT[] = !HOP_OUT[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			SRC_READ = BL_HOP1;
 		WHEN H"D" =>
-			OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"E" =>
-			OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN OTHERS =>
 					--   12345678901234567890123456789012
 			OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
@@ -472,145 +528,167 @@ BEGIN
 ------------ ENDMASKEN SETZEN ******************************************************************************																							 
 			ENDMASK1_SHIFT[3..0] = 0; 						
 			ENDMASK2_SHIFT[3..0] = 0; 
+			ENDMASKEND[] =  DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];					
 			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
-				IF X_INDEX[]==0 THEN															-- ENDE?	
-					ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0));	-- JA ENDMASK 3 SETZEN 
+				IF X_INDEX[] == 0 THEN															-- ENDE?	
+					ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1]));							-- JA ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
-				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
-					ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));					
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN 
+				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA -> ENDMASK 1 SETZEN 
 				ELSE					
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;
-			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV
-				IF X_INDEX[]==0 THEN															-- ANFANG?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); 						-- JA -> ENDMASK 1 SETZEN 
+			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV (immer bei memcopy)
+				IF X_INDEX[] == 0 THEN															-- ANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); 							-- JA -> ENDMASK 1 SETZEN 
 				ELSE		
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
 				END IF;		
-				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
-					ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];					
-					ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0];								-- JA: ENDMASK 3 SETZEN
+				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
+					ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
 			END IF;
 -- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
---				   1234567890123456789012345678
-	ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+		BL_ENDMASK0[] = 0;
+		BL_ENDMASKF[] = -1;
+		BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15;
+		BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15;
+	CASE DST_X_INC[] IS
+		WHEN 8 => 	-- INC 2
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN 4 =>	-- INC 4
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN 2 =>	-- INC 8
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN OTHERS =>
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+	END CASE;
 	ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]);			-- IMMER rechts SCHIEBEN
-	ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
 	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
-	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
+	ROR_CNT[] = 16 * (0,DST_ADR32[3..1]);
+	ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]);
+	ENDMASK123[].CLK = DDRCLK0;
+	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[];
 	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
-	NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
+	NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
 -- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 	
 	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
 	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
-	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
-	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
+	BLITTER_SIG.CLK = DDRCLK0;
+	BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1;
 -- BLITTER MAIN STATE MACHINE  -----------------------------------------------
 	BL_SM.CLK = DDRCLK0;
+	SRC_OLD[].CLK = DDRCLK0;
+	SRC_OLD[] = SRC_ADR32[31..4];
+	SDXINC.CLK = DDRCLK0;
 	CASE BL_SM IS
 		WHEN START =>   ------------------------- START
-			IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
-				BL_SM = NEW_LINE;
+			BL_NOTRUN = VCC;			-- BLITTER NOT RUN
+			IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN	-- STARTEN?
+				BL_SM = NEW_LINE;									-- JA START
 			ELSE
-				BL_SM = START;
+				BL_SM = START;										-- NICHT STARTEN
 			END IF;
 		WHEN NEW_LINE => ----------------------- NEU LINIE
-			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
-			BL_SM = RDSRC0;
-		WHEN RDSRC0 =>  ------------------------ READ SRC1
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					BL_SM = RDSRC2;
-				ELSE	
-					BL_SM = RDSRC1;
-				END IF;
+			X_INDEX_CLR_DIR = VCC;									-- JA -> X INDEX LÖSCHEN FÜR START LINE 			
+			IF SRC_READ THEN										-- SOURCE READ NÖTIG?
+				BL_SM = RDSRC3;										-- JA							
 			ELSE
-				BL_SM = RDDST;
+				BL_SM = RDDST;										-- NEIN -> DIREKT ZU READ DEST
 			END IF;
-		WHEN RDSRC1 =>  ------------------------ READ SRC1
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					SIINC = VCC;							-- INC SRC ADR
-					BL_SM = RDSRC2;
-				ELSE	
-					BL_SM = RDSRC1;
-				END IF;
-			ELSE
-				BL_SM = RDDST;
+		WHEN RDSRC3 =>  ------------------------ READ SRC3
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15);
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDSRC2;
+			ELSE	
+				BL_SM = RDSRC3;
 			END IF;
-		WHEN RDSRC2 =>	------------------------ READ SRC2
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					SIINC = VCC;							-- INC SRC ADR
-					BL_SM = RDDST;
-				ELSE	
-					BL_SM = RDSRC2;
-				END IF;
-			ELSE
-				BL_SM = RDDST;
+		WHEN RDSRC2 =>  ------------------------- READ SRC2
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4];
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;									-- LATCH UND SB1->SB2
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDSRC1;
+			ELSE	
+				BL_SM = RDSRC2;
 			END IF;
-		WHEN RDDST =>	----------------------- READ DEST
+		WHEN RDSRC1 =>	------------------------ READ SRC1
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15);
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
+			SRC_OLD[].ENA = VCC;
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDDST;
+			ELSE	
+				BL_SM = RDSRC1;
+			END IF;
+		WHEN RDDST =>	------------------------ READ DEST
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			IF NOT_DST_READ THEN
-				BL_SM = WRDSTW1;
+				BL_SM = WRDSTW;
 			ELSE
-				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
 				BLITTER_REQ = VCC;
 				BL_READ_DST = VCC;
 				IF BLITTER_DACK0 THEN
-					BL_SM = WRDSTW1;
+					BL_SM = WRDSTW;
 				ELSE	
 					BL_SM = RDDST;
 				END IF;
 			END IF;
-		WHEN WRDSTW1 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
+		WHEN WRDSTW =>	 ------------------------ KURZ WARTEN AUF ERGEBNIS
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			BL_SM = WRDST;
-		WHEN WRDST =>	------------------- WRITE DEST
-			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+		WHEN WRDST =>	------------------------- WRITE DEST
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			BLITTER_WR = VCC;
 			BLITTER_REQ = VCC;
+			SDXINC = BLITTER_DACK2;									-- INCCREMENT SRC, DST, X_INDEX
 			IF BLITTER_DACK0 THEN
-				XIINC = VCC;								-- INC X_INDEX
-				DIINC = VCC;								-- INC DEST ADR
 				BL_SM = TESTZEILENENDE;
 			ELSE	
 				BL_SM = WRDST;
 			END IF;
 		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
-			IF X_CNT_NODE[] >= BL_X_CNT[] THEN				-- SCHON ZEILENENDE?	
-				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
-				BL_SM = TESTFERTIG;							-- ->
+			IF X_CNT16[] >= BL_X_CNT[] THEN							-- SCHON ZEILENENDE? 	
+				YIINC = VCC;										-- JA -> INC Y-INDEX
+				BL_SM = TESTFERTIG;									-- => TEST OB FERTIG
 			ELSE
-				BL_SM = RDSRC2;								-- NEIN NEXT
+				IF !SRC_READ THEN									-- KEIN SOURCE READ?
+					BL_SM = RDDST;									-- JA => LESEN UNNÖTIG ->
+				ELSE
+					IF SRC_ADR32[31..4] == SRC_OLD[] THEN			-- ADRESSE IMMER NOCH IN DER LINE?
+						BL_SM = RDDST;								-- DATEN SIND GÜLTIG -> READ DEST
+					ELSE
+						BL_SM = RDSRC1;								-- SONST NEXT SRC
+					END IF;
+				END IF;
 			END IF;	
 		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
-			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
-			IF Y_INDEX[] >= BL_Y_CNT[] THEN					-- LETZTE ZEILE?
-				BL_SM = FERTIG;								-- JA -->
+			ZAINC = VCC;											-- ZEILENENDE: INC SRC UND DST ADRESSEN 
+			IF Y_INDEX[] >= BL_Y_CNT[] THEN							-- LETZTE ZEILE?
+				BL_SM = FERTIG;										-- JA => FERTIG
 			ELSE
-				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
-				BL_SM = NEW_LINE;							-- NEIN NEXT ->
+				BL_SM = NEW_LINE;									-- NEIN => NEXT LINE
 			END IF;
 		WHEN FERTIG => -------------------------- FERTIG
-			BLITTER_INT = VCC;								-- BLITTER INTERRUPT
-			LN7CLR = VCC;									-- BUSY BIT LÖSCHEN
-			IF BL_LN7==0 THEN								-- WARTEN BIS GELÖSCHT (GEHT NUR MIT 33MHz)
+			BL_NOTRUN = VCC;										-- BLITTER NOT RUN
+			BLITTER_INT = VCC;										-- BLITTER INTERRUPT
+			LN7_CLR = VCC;											-- BUSY BIT LÖSCHEN
+			IF (BL_LN7 == 0) & (BL_START == 0) THEN			-- WARTEN BIS GELÖSCHT (SYNC MIT 33MHz)
 				BL_SM = START;	
 			ELSE
 				BL_SM = FERTIG;
diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak
index 8669470..3da6541 100644
--- a/FPGA_by_Fredi/blitter.tdf.bak
+++ b/FPGA_by_Fredi/blitter.tdf.bak
@@ -23,6 +23,8 @@ INCLUDE "lpm_bustri_WORD.inc";
 INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
 INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
 INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
+INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
+
 
 --CONSTANT	BL_SKEW_LF = 255;
 
@@ -71,66 +73,70 @@ SUBDESIGN BLITTER
 
 VARIABLE
 	BYT							:NODE;
-	LONGLINE					:NODE;
-	W_ADR[18..0]				:NODE;
 	FB_16B[1..0]				:NODE;
-	W_A1						:DFFE;
 	BLITTER_CS					:NODE;
 	BL_HRAM_CS 					:NODE;
+	DP_RAM_CS					:NODE;
 	BL_HRAM_BE[1..0]			:NODE;
 	BL_HRAM_OUT[15..0]			:NODE;
 	BL_DPRAM_OUT[15..0]			:NODE;
 	BL_SRC_X_INC_CS				:NODE;
 	BL_SRC_X_INC[15..0]			:DFFE;
-	SRC_XINC_NODE[31..0]		:NODE;
+	SRC_ADR_INC[31..0]			:NODE;
+	SRC_XINC32[31..0]			:NODE;
 	BL_SRC_Y_INC_CS				:NODE;
 	BL_SRC_Y_INC[15..0]			:DFFE;
-	SRC_YINC_NODE[31..0]		:NODE;
+	SRC_YINC32[31..0]			:NODE;
 	BL_ENDMASK1_CS				:NODE;
 	BL_ENDMASK1[15..0]			:DFFE;
 	BL_ENDMASK2_CS				:NODE;
 	BL_ENDMASK2[15..0]			:DFFE;
 	BL_ENDMASK3_CS				:NODE;
 	BL_ENDMASK3[15..0]			:DFFE;
+	BL_ENDMASK0[15..0]			:NODE;
+	BL_ENDMASKF[15..0]			:NODE;
+	BL_ENDMASKL[15..0]			:NODE;
+	BL_ENDMASKR[15..0]			:NODE;
 	BL_SRC_ADRH_CS				:NODE;
 	BL_SRC_ADRL_CS				:NODE;
 	BL_SRC_ADR[31..0]			:DFFE;
+	SRC_OLD[27..0]				:DFFE;
 	SRC_IADRH_CS				:NODE;
 	SRC_IADRL_CS				:NODE;
 	SRC_IADR[31..0]				:DFF;
-	SRC_IADR_CLR				:NODE;
-	SIINC						:NODE;
-	SRC_ADR_NODE[31..0]			:NODE;
+	SRC_IADR_CLR				:DFF;
+	SRC_ADR32[31..0]			:NODE;
 	BL_DST_X_INC_CS				:NODE;
 	BL_DST_X_INC[15..0]			:DFFE;
-	DST_XINC_NODE[31..0]		:NODE;
+	DST_ADR_INC[31..0]			:NODE;
+	DST_XINC32[31..0]			:NODE;
 	BL_DST_Y_INC_CS				:NODE;
 	BL_DST_Y_INC[15..0]			:DFFE;
-	DST_YINC_NODE[31..0]		:NODE;
+	DST_YINC32[31..0]			:NODE;
 	BL_DST_ADRH_CS				:NODE;
 	BL_DST_ADRL_CS				:NODE;
 	BL_DST_ADR[31..0]			:DFFE;
 	DST_IADRH_CS				:NODE;
 	DST_IADRL_CS				:NODE;
 	DST_IADR[31..0]				:DFF;
-	DST_IADR_CLR				:NODE;
-	DST_ADR_NODE[31..0]			:NODE;
-	DIINC						:NODE;
+	DST_IADR_CLR				:DFF;
+	DST_ADR32[31..0]			:NODE;
 	BL_X_CNT_CS					:NODE;
 	BL_X_CNT[15..0]				:DFFE;
-	X_CNT_NODE[15..0]			:NODE;
+	X_CNT16[15..0]				:NODE;
 	BL_Y_CNT_CS					:NODE;
 	BL_Y_CNT[15..0]				:DFFE;
 	BL_HOP_CS					:NODE;
 	BL_HOP[7..0]				:DFFE;
 	BL_OP[7..0]					:DFFE;
 	BL_LN_CS					:NODE;
-	LN7CLR						:NODE;
+	BL_LN_WR					:NODE;
+	LN7_CLR						:NODE;
 	BL_LN[7..0]					:DFFE;
 	BL_SKEW[7..0]				:DFFE;
 -- barell shifter
 	DIST_RIGHT[8..0]			:NODE;
-	BL_BS_SKEW[7..0]			:NODE;
+	BS_SKEW[7..0]				:NODE;
 	BL_BSIN[383..0]				:NODE;
 	BL_BSOUT[383..0]			:NODE;
 	SHIFT_DIR					:NODE;
@@ -145,15 +151,17 @@ VARIABLE
 	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
 	X_INDEX_CS					:NODE;
 	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
-	X_INDEX_CLR					:NODE;
+	X_INDEX_CLR					:DFF;				-- X INDEX LÖSCHEN CPU WRITE
+	X_INDEX_CLR_DIR				:NODE;				-- X INDEX LÖSCHEN STATE MACHINE
+	DST_X_INC[15..0]			:NODE;				-- ANZAHL WORTE PRO DURCHLAUF
+	X_CNT_T[15..0]				:NODE;
 	Y_INDEX_CS					:NODE;
 	Y_INDEX[15..0]				:DFF;				-- LAUFZEIGER Y COUNT
-	Y_INDEX_CLR					:NODE;
+	Y_INDEX_CLR					:DFF;
 	LINE_NR[3..0]				:NODE;
-	XIINC						:NODE;				-- INC INDEX SPALTE
+	SDXINC						:DFF;				-- INC INDEX SPALTE
 	YIINC						:NODE;				-- INC INDEX ZEILE
-	ZIINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
-	ZYINC						:NODE;				-- KORREKTUR ADRESSEN WENN FERTIG
+	ZAINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
 	HOP_OUT[127..0]				:NODE;
 	OP_OUT[127..0]				:NODE;
 	ENDMASK1_SHIFT[7..0]		:NODE;
@@ -162,24 +170,22 @@ VARIABLE
 	ENDMASK12_OUT[143..0]		:NODE;
 	ENDMASK23_IN[143..0]		:NODE;
 	ENDMASK23_OUT[143..0]		:NODE;
-	ENDMASK123[127..0]			:NODE;
-	ENDMASKEND[15..0]			:NODE;
-	SRC_DDR_ADR[31..0]			:NODE;
-	DST_DDR_ADR[31..0]			:NODE;
-	BLITTER_REQ					:DFF;
+	ENDMASKM_IN[127..0]			:NODE;
+	ENDMASKM_OUT[127..0]		:NODE;
+	ROR_CNT[8..0]				:NODE;
+	ENDMASK123[127..0]			:DFF;
+	ENDMASKEND[31..0]			:NODE;
+	BLITTER_SIG					:DFF;
+	BLITTER_REQ					:NODE;
+	BL_START					:DFF;
+	BL_NOTRUN					:NODE;
 	
 -- MAIN STATE MACHINE
-	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDSTW2,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
+	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
 	
 BEGIN
 -- BYT UND WORD SELECT 16 BIT
 	BYT      = !FB_SIZE1 &  FB_SIZE0;
-	LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; 	-- LONG OR LINE
-	W_A1.CLK = MAIN_CLK;
-	W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE;
-	W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE;			-- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST
-	W_ADR[18..1] = FB_ADR[19..2];
-	W_ADR0 = W_A1;  
 	FB_16B0 = FB_ADR[0]==0;										-- wenn ADR==0
 	FB_16B1 = FB_ADR[0]==1 # !BYT;								-- wenn ADR==1 or NOT BYT
 -- BLITTER CS
@@ -191,156 +197,229 @@ BEGIN
 	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
 	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
 	WREN_B = B"0";
-	LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15));
-	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15));
+	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
+	DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528";							-- $F8A50.w
 	-- SRC X INC
 	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[] = FB_AD[31..16];
-	BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510";						-- $F8A20.w
+	BL_SRC_X_INC[15..1] = FB_AD[31..17];
+	BL_SRC_X_INC0 = GND;
+	BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510");						-- $F8A20.w
 	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	SRC_XINC32[15..0]  = BL_SRC_X_INC[];											-- ERWEITERN AUF 32 BIT
+	SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15;									-- ERWEITERN AUF 32 BIT
 	-- SRC Y INC
 	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[] = FB_AD[31..16];
-	BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511";						-- $F8A22.w
+	BL_SRC_Y_INC[15..1] = FB_AD[31..17];
+	BL_SRC_Y_INC0 = GND;
+	BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511");						-- $F8A22.w
 	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	SRC_YINC32[15..0]  = BL_SRC_Y_INC[];											-- ERWEITERN AUF 32 BIT
+	SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15;									-- ERWEITERN AUF 32 BIT
 	-- SRC ADR HIGH
 	BL_SRC_ADR[].CLK = MAIN_CLK;
 	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512";						-- $F8A24.w
+	BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512");						-- $F8A24.w
 	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
 	-- SRC ADR LOW
 	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..0] = FB_AD[31..16];
-	BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513";						-- $F8A26.w
+	BL_SRC_ADR[15..1] = FB_AD[31..17];
+	BL_SRC_ADR0 = GND;
+	BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513");						-- $F8A26.w
 	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
 	SRC_IADR[].CLK = DDRCLK0;
-	SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520";						-- $F8A40.w
-	SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521";						-- $F8A42.w
+	SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520");							-- $F8A40.w
+	SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521");							-- $F8A42.w
+	SRC_IADR_CLR.CLK = MAIN_CLK;
 	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
-	SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR;
-	SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
+	SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH 
 	-- ENDMASK 1
 	BL_ENDMASK1[].CLK = MAIN_CLK;
 	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514";						-- $F8A28.w
+	BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514");						-- $F8A28.w
 	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 2
 	BL_ENDMASK2[].CLK = MAIN_CLK;
 	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515";						-- $F8A2A.w
+	BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515");						-- $F8A2A.w
 	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
 	-- ENDMASK 3
 	BL_ENDMASK3[].CLK = MAIN_CLK;
 	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516";						-- $F8A2C.w
+	BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516");						-- $F8A2C.w
 	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
 	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
 	-- DST X INC
 	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[] = FB_AD[31..16];
-	BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517";						-- $F8A2E.w
+	BL_DST_X_INC[15..1] = FB_AD[31..17];
+	BL_DST_X_INC0 = GND;
+	BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517");						-- $F8A2E.w
 	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]);	-- ERWEITERN AUF 32 BIT
+	DST_XINC32[15..0]  = BL_DST_X_INC[];											-- ERWEITERN AUF 32 BIT
+	DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15;									-- ERWEITERN AUF 32 BIT
 	-- DST Y INC
 	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[] = FB_AD[31..16];
-	BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518";						-- $F8A30.w
+	BL_DST_Y_INC[15..1] = FB_AD[31..17];
+	BL_DST_Y_INC0 = GND;
+	BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518");						-- $F8A30.w
 	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
 	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]);	-- ERWEITERN AUF 32 BIT
+	DST_YINC32[15..0]  = BL_DST_Y_INC[];											-- ERWEITERN AUF 32 BIT
+	DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15;									-- ERWEITERN AUF 32 BIT
 	-- DST ADR HIGH
 	BL_DST_ADR[].CLK = MAIN_CLK;
 	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519";						-- $F8A32.w
+	BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519");						-- $F8A32.w
 	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
 	-- DST ADR LOW
 	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..0] = FB_AD[31..16];
-	BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A";						-- $F8A34.w
+	BL_DST_ADR[15..1] = FB_AD[31..17];
+	BL_DST_ADR0 = GND;
+	BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A");						-- $F8A34.w
 	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
 	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
 	DST_IADR[].CLK = DDRCLK0;
-	DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522";						-- $F8A44.w
-	DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523";						-- $F8A46.w
-	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;			-- LÖSCHEN BEI WRITE
-	DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR;
-	DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH
+	DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522");							-- $F8A44.w
+	DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523");							-- $F8A46.w
+	DST_IADR_CLR.CLK = MAIN_CLK;					
+	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;					-- LÖSCHEN BEI WRITE
+	DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
+	DST_ADR32[] = BL_DST_ADR[] + DST_IADR[];									-- ZUGRIFFSADRESSE THEORETISCH
 	-- X COUNT
 	BL_X_CNT[].CLK = MAIN_CLK;
 	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B";							-- $F8A36.w
+	BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B");							-- $F8A36.w
 	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
 	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
 	X_INDEX[].CLK = DDRCLK0;
-	X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524";							-- $F8A48.w
-	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
-	X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; 
-	X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE
+	X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524");							-- $F8A48.w
+	X_INDEX_CLR.CLK = MAIN_CLK;
+	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
+	X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
+	X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0));		-- EFFEKTIV geschrieben
+-- SCHRITTWEITEN BEI PALLETTENMOD
+	IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 8) THEN 
+		DST_X_INC[] = 1;
+		X_CNT_T[] = 0;
+		SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
+		DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
+	ELSE		
+		IF BL_SRC_X_INC[] == H"0002" THEN 
+			DST_X_INC[] = 8;
+			X_CNT_T[] = (0,DST_ADR32[3..1]);
+			SRC_ADR_INC[] = 16;						-- SRC X INC
+			DST_ADR_INC[] = 16;						-- DST X INC
+		ELSE
+			IF BL_SRC_X_INC[] == H"FFFE" THEN 
+				DST_X_INC[] = 8;
+				X_CNT_T[] = 7 - (0,DST_ADR32[3..1]);
+				SRC_ADR_INC[] = -16;				-- SRC X INC
+				DST_ADR_INC[] = -16;				-- DST X INC
+			ELSE							
+				IF BL_SRC_X_INC[] == H"0004" THEN 
+					DST_X_INC[] = 4;
+					X_CNT_T[] = (0,DST_ADR32[3..2]);
+					SRC_ADR_INC[] = 16;						-- SRC X INC
+					DST_ADR_INC[] = 16;						-- DST X INC
+				ELSE
+					IF BL_SRC_X_INC[] == H"FFFC" THEN 
+						DST_X_INC[] = 4;
+						X_CNT_T[] = 3 - (0,DST_ADR32[3..2]);
+						SRC_ADR_INC[] = -16;				-- SRC X INC
+						DST_ADR_INC[] = -16;				-- DST X INC
+					ELSE							
+						IF BL_SRC_X_INC[] == H"0008" THEN 
+							DST_X_INC[] = 2;
+							X_CNT_T[] = (0,DST_ADR32[3]);
+							SRC_ADR_INC[] = 16;						-- SRC X INC
+							DST_ADR_INC[] = 16;						-- DST X INC
+						ELSE
+							IF BL_SRC_X_INC[] == H"FFF8" THEN 
+								DST_X_INC[] = 2;
+								X_CNT_T[] = 1 - (0,DST_ADR32[3]);
+								SRC_ADR_INC[] = -16;				-- SRC X INC
+								DST_ADR_INC[] = -16;				-- DST X INC
+							ELSE							
+								DST_X_INC[] = 1;
+								X_CNT_T[] = 0;
+								SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
+								DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
+							END IF;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+		END IF;
+	END IF;
 	-- Y COUNT
 	BL_Y_CNT[].CLK = MAIN_CLK;
 	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C";							-- $F8A38.w
+	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";							-- $F8A38.w
 	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
 	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
 	Y_INDEX[].CLK = DDRCLK0;
-	Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525";							-- $F8A4A.w
-	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;								-- LÖSCHEN BEI WRITE
+	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";							-- $F8A4A.w
+	Y_INDEX_CLR.CLK = MAIN_CLK;
+	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
 	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
 	-- HOP LOGIC
 	BL_HOP[].CLK = MAIN_CLK;
 	BL_HOP[] = FB_AD[31..24];
-	BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D";							-- $F8A3A.w
-	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;					-- $F8A3A
+	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";								-- $F8A3A.w
+	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;							-- $F8A3A
 	-- OP LOGIC
 	BL_OP[].CLK = MAIN_CLK;
 	BL_OP[] = FB_AD[23..16];
-	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;					-- $F8A3B
+	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;							-- $F8A3B
 	-- LINE NUMBER BYT
 	BL_LN[].CLK = MAIN_CLK;
-	BL_LN[6..0] = FB_AD[30..24];	
-	BL_LN7 = FB_AD31 & !LN7CLR;											-- BUSY HOG UND SMUDGE
-	BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E";							-- $F8A3C.w
-	BL_LN[].ENA  = BL_LN_CS & !nFB_WR & FB_16B0;						-- $F8A3C
-	BL_LN7.ENA = LN7CLR;
+	BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E");							-- $F8A3C.w
+	BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0;									-- $F8A3C WRITE SIGNAL
+	BL_LN[6..0] = FB_AD[30..24];												-- HOG UND SMUDGE
+	BL_LN[6..0].ENA  = BL_LN_WR;													-- $F8A3C
+	BL_LN7.ENA  = BL_LN_WR # LN7_CLR;													-- $F8A3C
+	BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY 
+	BL_START.CLK = MAIN_CLK;
+	BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; 
 	-- SKEW BYT
 	BL_SKEW[].CLK = MAIN_CLK;
 	BL_SKEW[] = FB_AD[23..16];
-	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;						-- $F8A3D
+	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;								-- $F8A3D
 --- REGISTER OUT
 	FB_AD[31..16] = lpm_bustri_WORD(
 						BL_HRAM_CS	    & BL_DPRAM_OUT[]
 					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
 					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & SRC_ADR_NODE[31..16]
-					  # BL_SRC_ADRL_CS  & SRC_ADR_NODE[15..0]
+					  # BL_SRC_ADRH_CS  & SRC_ADR32[31..16]
+					  # BL_SRC_ADRL_CS  & SRC_ADR32[15..0]
 					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
 					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
 					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
 					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
 					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & DST_ADR_NODE[31..16]
-					  # BL_DST_ADRL_CS  & DST_ADR_NODE[15..0]
+					  # BL_DST_ADRH_CS  & DST_ADR32[31..16]
+					  # BL_DST_ADRL_CS  & DST_ADR32[15..0]
 					  # BL_X_CNT_CS 	& (BL_X_CNT[]-X_INDEX[])
 					  # BL_Y_CNT_CS 	& (BL_Y_CNT[]-Y_INDEX[])
 					  # BL_HOP_CS 		& (BL_HOP[],BL_OP[])
-					  # BL_LN_CS 		& (BL_LN[7..4],Y_INDEX[3..0],BL_SKEW[])		
+					  # BL_LN_CS 		& (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[])		
 					  # SRC_IADRH_CS	& SRC_IADR[31..16]
 					  # SRC_IADRL_CS	& SRC_IADR[15..0]
 					  # DST_IADRH_CS	& DST_IADR[31..16]
 					  # DST_IADRL_CS	& DST_IADR[15..0]
 					  # X_INDEX_CS		& X_INDEX[]
 					  # Y_INDEX_CS		& Y_INDEX[]
-					  ,BLITTER_CS & !nFB_OE); 							-- FFFF8A00-7F
+					  # DP_RAM_CS		& BL_HRAM_OUT[]
+					  ,BLITTER_CS & !nFB_OE); 									-- FFFF8A00-7F
 --------------------------------------------------------------------------------------
 -- SRC BUFFER LADEN
 	BL_SRC_BUF1[].CLK = DDRCLK0;
@@ -355,34 +434,11 @@ BEGIN
 	BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
 	BL_SRC_BUF3[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
 	BL_SRC_BUF3[] = BL_SRC_BUF2[];
-	-- ZUORDNUNG ---------
+	-- ZUORDNUNG ---------------------------------------------------
 	IF BL_SRC_X_INC15 THEN		-- WENN NEGATIV -> REIHENFOLGE KEHREN
-		CASE BL_HOP[7..4] IS	-- SPIEGELN?
-			WHEN H"0" =>		-- LINE WEISE
-				BL_BSIN[127..0]   = BL_SRC_BUF3[];
-				BL_BSIN[255..128] = BL_SRC_BUF2[];
-				BL_BSIN[383..256] = BL_SRC_BUF1[];
-			WHEN H"1" =>		--- BIT WEISE
-				BL_BSIN[0..127]   = BL_SRC_BUF3[];
-				BL_BSIN[128..255] = BL_SRC_BUF2[];
-				BL_BSIN[256..383] = BL_SRC_BUF1[];
-			WHEN H"2" =>		-- BYT WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[7..0],BL_SRC_BUF3[15..8],BL_SRC_BUF3[23..16],BL_SRC_BUF3[31..24],BL_SRC_BUF3[39..32],BL_SRC_BUF3[47..40],BL_SRC_BUF3[55..48],BL_SRC_BUF3[63..56],BL_SRC_BUF3[71..64],BL_SRC_BUF3[79..72],BL_SRC_BUF3[87..80],BL_SRC_BUF3[95..88],BL_SRC_BUF3[103..96],BL_SRC_BUF3[111..104],BL_SRC_BUF3[119..112],BL_SRC_BUF3[127..120]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[7..0],BL_SRC_BUF2[15..8],BL_SRC_BUF2[23..16],BL_SRC_BUF2[31..24],BL_SRC_BUF2[39..32],BL_SRC_BUF2[47..40],BL_SRC_BUF2[55..48],BL_SRC_BUF2[63..56],BL_SRC_BUF2[71..64],BL_SRC_BUF2[79..72],BL_SRC_BUF2[87..80],BL_SRC_BUF2[95..88],BL_SRC_BUF2[103..96],BL_SRC_BUF2[111..104],BL_SRC_BUF2[119..112],BL_SRC_BUF2[127..120]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[7..0],BL_SRC_BUF1[15..8],BL_SRC_BUF1[23..16],BL_SRC_BUF1[31..24],BL_SRC_BUF1[39..32],BL_SRC_BUF1[47..40],BL_SRC_BUF1[55..48],BL_SRC_BUF1[63..56],BL_SRC_BUF1[71..64],BL_SRC_BUF1[79..72],BL_SRC_BUF1[87..80],BL_SRC_BUF1[95..88],BL_SRC_BUF1[103..96],BL_SRC_BUF1[111..104],BL_SRC_BUF1[119..112],BL_SRC_BUF1[127..120]);
-			WHEN H"3" =>		-- WORD WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[15..0],BL_SRC_BUF3[31..16],BL_SRC_BUF3[47..32],BL_SRC_BUF3[63..48],BL_SRC_BUF3[79..64],BL_SRC_BUF3[95..80],BL_SRC_BUF3[111..96],BL_SRC_BUF3[127..112]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[15..0],BL_SRC_BUF2[31..16],BL_SRC_BUF2[47..32],BL_SRC_BUF2[63..48],BL_SRC_BUF2[79..64],BL_SRC_BUF2[95..80],BL_SRC_BUF2[111..96],BL_SRC_BUF2[127..112]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[15..0],BL_SRC_BUF1[31..16],BL_SRC_BUF1[47..32],BL_SRC_BUF1[63..48],BL_SRC_BUF1[79..64],BL_SRC_BUF1[95..80],BL_SRC_BUF1[111..96],BL_SRC_BUF1[127..112]);
-			WHEN H"4" =>		-- LONG WEISE
-				BL_BSIN[127..0]   = (BL_SRC_BUF3[31..0],BL_SRC_BUF3[63..32],BL_SRC_BUF3[95..64],BL_SRC_BUF3[127..96]);
-				BL_BSIN[255..128] = (BL_SRC_BUF2[31..0],BL_SRC_BUF2[63..32],BL_SRC_BUF2[95..64],BL_SRC_BUF2[127..96]);
-				BL_BSIN[383..256] = (BL_SRC_BUF1[31..0],BL_SRC_BUF1[63..32],BL_SRC_BUF1[95..64],BL_SRC_BUF1[127..96]);
-			WHEN OTHERS =>		-- LINE WEISE
-				BL_BSIN[127..0]   = BL_SRC_BUF3[];
-				BL_BSIN[255..128] = BL_SRC_BUF2[];
-				BL_BSIN[383..256] = BL_SRC_BUF1[];
-		END CASE;
+		BL_BSIN[127..0]   = BL_SRC_BUF3[];
+		BL_BSIN[255..128] = BL_SRC_BUF2[];
+		BL_BSIN[383..256] = BL_SRC_BUF1[];
 	ELSE						-- SONST NORMAL BEI VORWÄRTS
 		BL_BSIN[127..0]   = BL_SRC_BUF1[];
 		BL_BSIN[255..128] = BL_SRC_BUF2[];
@@ -395,16 +451,16 @@ BEGIN
 	BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
 -- barell shift *****************************************************************************
 -- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
-	DIST_RIGHT[] = (16 * ((0,DST_ADR_NODE[3..1]) - (0,SRC_ADR_NODE[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
-	IF DIST_RIGHT8 == 0 THEN 		
-		BL_BS_SKEW[] = DIST_RIGHT[7..0]; 					-- LPM SHIFT RIGHT
-		SHIFT_DIR = VCC;									-- DIR = RIGHT
-	else													
-		BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; 				-- LPM SHIFT LEFT
+	DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
+	IF DIST_RIGHT8 THEN 		
+		BS_SKEW[] = 0 - DIST_RIGHT[7..0]; 					-- LPM SHIFT LEFT
 		SHIFT_DIR = GND;									-- DIR = LEFT
+	else													
+		BS_SKEW[] = DIST_RIGHT[7..0]; 						-- LPM SHIFT RIGHT
+		SHIFT_DIR = VCC;									-- DIR = RIGHT
 	end if;
 -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
-	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BL_BS_SKEW[]);	-- wir brauchen 128bit
+	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]);	-- wir brauchen 128bit
 -- HOP ***************************************************************************************
 	CASE BL_HOP[1..0] IS
 		WHEN H"0" =>
@@ -423,47 +479,47 @@ BEGIN
 			OP_OUT[] = H"0";
 			SRC_READ = B"0";
 		WHEN H"1" =>
-			OP_OUT[] = HOP_OUT[] & BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"2" =>
-			OP_OUT[] = HOP_OUT[] & !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"3" =>
 			OP_OUT[] = HOP_OUT[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			SRC_READ = BL_HOP1;
 		WHEN H"4" =>
-			OP_OUT[] = !HOP_OUT[] & BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"5" =>
 			OP_OUT[] = BL_DST_BUFRD[];
 			SRC_READ = B"0";
 		WHEN H"6" =>
-			OP_OUT[] = HOP_OUT[] $ BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"7" =>
-			OP_OUT[] = HOP_OUT[] # BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"8" =>
-			OP_OUT[] = !HOP_OUT[] & !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"9" =>
-			OP_OUT[] = !HOP_OUT[] $ BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"A" =>
 			OP_OUT[] = !BL_DST_BUFRD[];
 			SRC_READ = B"0";
 		WHEN H"B" =>
-			OP_OUT[] = HOP_OUT[] # !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"C" =>
 			OP_OUT[] = !HOP_OUT[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			SRC_READ = BL_HOP1;
 		WHEN H"D" =>
-			OP_OUT[] = !HOP_OUT[] # BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN H"E" =>
-			OP_OUT[] = !HOP_OUT[] # !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1 # BL_HOP0;
+			OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[];
+			SRC_READ = BL_HOP1;
 		WHEN OTHERS =>
 					--   12345678901234567890123456789012
 			OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
@@ -472,147 +528,167 @@ BEGIN
 ------------ ENDMASKEN SETZEN ******************************************************************************																							 
 			ENDMASK1_SHIFT[3..0] = 0; 						
 			ENDMASK2_SHIFT[3..0] = 0; 
+			ENDMASKEND[] =  DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];					
 			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
-				IF X_INDEX[]==0 THEN															-- ENDE?	
-					ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0));	-- JA ENDMASK 3 SETZEN 
+				IF X_INDEX[] == 0 THEN															-- ENDE?	
+					ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1]));							-- JA ENDMASK 3 SETZEN 
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
-				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENANFANG?	
-					ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1]));					
-					ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN 
+				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA -> ENDMASK 1 SETZEN 
 				ELSE					
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;
-			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV
-				IF X_INDEX[]==0 THEN															-- ANFANG?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); 						-- JA -> ENDMASK 1 SETZEN 
+			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV (immer bei memcopy)
+				IF X_INDEX[] == 0 THEN															-- ANFANG?	
+					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); 							-- JA -> ENDMASK 1 SETZEN 
 				ELSE		
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
 				END IF;		
-				IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN											-- SCHON ZEILENENDE?	
-					ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[];					
-					ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0];								-- JA: ENDMASK 3 SETZEN
+				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
+					ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN
 				ELSE					
 					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;	 
 			END IF;
 -- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
---				   1234567890123456789012345678
-	ENDMASK12_IN[] = (BL_ENDMASK1[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+		BL_ENDMASK0[] = 0;
+		BL_ENDMASKF[] = -1;
+		BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15;
+		BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15;
+	CASE DST_X_INC[] IS
+		WHEN 8 => 	-- INC 2
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN 4 =>	-- INC 4
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN 2 =>	-- INC 8
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+		WHEN OTHERS =>
+			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
+			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
+			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
+	END CASE;
 	ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]);			-- IMMER rechts SCHIEBEN
-	ENDMASK23_IN[] = (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK3[]);
 	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
-	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16];
+	ROR_CNT[] = 16 * (0,DST_ADR32[3..1]);
+	ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]);
+	ENDMASK123[].CLK = DDRCLK0;
+	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[];
 	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
-	NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
+	NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
 -- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 	
 	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
 	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
-	SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS SRC
-	DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15)));	-- WENN RÜCKWÄRTS NEXT ADRESS DST
-	BLITTER_REQ.CLK = DDRCLK0;
-	BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0";
+	BLITTER_SIG.CLK = DDRCLK0;
+	BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1;
 -- BLITTER MAIN STATE MACHINE  -----------------------------------------------
 	BL_SM.CLK = DDRCLK0;
+	SRC_OLD[].CLK = DDRCLK0;
+	SRC_OLD[] = SRC_ADR32[31..4];
+	SDXINC.CLK = DDRCLK0;
 	CASE BL_SM IS
 		WHEN START =>   ------------------------- START
-			IF BLITTER_ON & BL_LN7 & ((BL_X_CNT[] - X_CNT_NODE[])>0) & ((BL_Y_CNT[] - Y_INDEX[]) > 0) THEN
-				BL_SM = NEW_LINE;
+			BL_NOTRUN = VCC;			-- BLITTER NOT RUN
+			IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN	-- STARTEN?
+				BL_SM = NEW_LINE;									-- JA START
 			ELSE
-				BL_SM = START;
+				BL_SM = START;										-- NICHT STARTEN
 			END IF;
 		WHEN NEW_LINE => ----------------------- NEU LINIE
-			X_INDEX_CLR = VCC;								-- LÖSCHEN  			
-			BL_SM = RDSRC0;
-		WHEN RDSRC0 =>  ------------------------ READ SRC1
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1;
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					BL_SM = RDSRC2;
-				ELSE	
-					BL_SM = RDSRC1;
-				END IF;
+			X_INDEX_CLR_DIR = VCC;									-- JA -> X INDEX LÖSCHEN FÜR START LINE 			
+			IF SRC_READ THEN										-- SOURCE READ NÖTIG?
+				BL_SM = RDSRC3;										-- JA							
 			ELSE
-				BL_SM = RDDST;
+				BL_SM = RDDST;										-- NEIN -> DIREKT ZU READ DEST
 			END IF;
-		WHEN RDSRC1 =>  ------------------------ READ SRC1
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					SIINC = VCC;							-- INC SRC ADR
-					BL_SM = RDSRC2;
-				ELSE	
-					BL_SM = RDSRC1;
-				END IF;
-			ELSE
-				BL_SM = RDDST;
+		WHEN RDSRC3 =>  ------------------------ READ SRC3
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15);
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDSRC2;
+			ELSE	
+				BL_SM = RDSRC3;
 			END IF;
-		WHEN RDSRC2 =>	------------------------ READ SRC2
-			IF SRC_READ THEN
-				BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4];
-				BLITTER_REQ = VCC;
-				BL_READ_SRC = VCC;							-- LATCH UND SB1->SB2
-				IF BLITTER_DACK0 THEN
-					SIINC = VCC;							-- INC SRC ADR
-					BL_SM = RDDST;
-				ELSE	
-					BL_SM = RDSRC2;
-				END IF;
-			ELSE
-				BL_SM = RDDST;
+		WHEN RDSRC2 =>  ------------------------- READ SRC2
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4];
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;									-- LATCH UND SB1->SB2
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDSRC1;
+			ELSE	
+				BL_SM = RDSRC2;
 			END IF;
-		WHEN RDDST =>	----------------------- READ DEST
+		WHEN RDSRC1 =>	------------------------ READ SRC1
+			BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15);
+			BLITTER_REQ = VCC;
+			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
+			SRC_OLD[].ENA = VCC;
+			IF BLITTER_DACK0 THEN
+				BL_SM = RDDST;
+			ELSE	
+				BL_SM = RDSRC1;
+			END IF;
+		WHEN RDDST =>	------------------------ READ DEST
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			IF NOT_DST_READ THEN
-				BL_SM = WRDSTW1;
+				BL_SM = WRDSTW;
 			ELSE
-				BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
 				BLITTER_REQ = VCC;
 				BL_READ_DST = VCC;
 				IF BLITTER_DACK0 THEN
-					BL_SM = WRDSTW1;
+					BL_SM = WRDSTW;
 				ELSE	
 					BL_SM = RDDST;
 				END IF;
 			END IF;
-		WHEN WRDSTW1 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
-			BL_SM = WRDSTW2;
-		WHEN WRDSTW2 =>	------------------- WRITE DEST WAIT AUF ERGEBNIS
+		WHEN WRDSTW =>	 ------------------------ KURZ WARTEN AUF ERGEBNIS
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			BL_SM = WRDST;
-		WHEN WRDST =>	------------------- WRITE DEST
-			BLITTER_ADR[31..4] = DST_DDR_ADR[31..4];
+		WHEN WRDST =>	------------------------- WRITE DEST
+			BLITTER_ADR[31..4] = DST_ADR32[31..4];
 			BLITTER_WR = VCC;
 			BLITTER_REQ = VCC;
+			SDXINC = BLITTER_DACK2;									-- INCCREMENT SRC, DST, X_INDEX
 			IF BLITTER_DACK0 THEN
-				XIINC = VCC;								-- INC X_INDEX
-				DIINC = VCC;								-- INC DEST ADR
 				BL_SM = TESTZEILENENDE;
 			ELSE	
 				BL_SM = WRDST;
 			END IF;
 		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
-			IF X_CNT_NODE[] >= BL_X_CNT[] THEN				-- SCHON ZEILENENDE?	
-				YIINC = VCC;								-- JA -> INC Y-INDEX UND ZEILE SRC UND DEST
-				BL_SM = TESTFERTIG;							-- ->
+			IF X_CNT16[] >= BL_X_CNT[] THEN							-- SCHON ZEILENENDE? 	
+				YIINC = VCC;										-- JA -> INC Y-INDEX
+				BL_SM = TESTFERTIG;									-- => TEST OB FERTIG
 			ELSE
-				BL_SM = RDSRC2;								-- NEIN NEXT
+				IF !SRC_READ THEN									-- KEIN SOURCE READ?
+					BL_SM = RDDST;									-- JA => LESEN UNNÖTIG ->
+				ELSE
+					IF SRC_ADR32[31..4] == SRC_OLD[] THEN			-- ADRESSE IMMER NOCH IN DER LINE?
+						BL_SM = RDDST;								-- DATEN SIND GÜLTIG -> READ DEST
+					ELSE
+						BL_SM = RDSRC1;								-- SONST NEXT SRC
+					END IF;
+				END IF;
 			END IF;	
 		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
-			ZIINC = VCC;									-- INC ADRESSEN ZEILENUMBRUCH
-			IF Y_INDEX[] >= BL_Y_CNT[] THEN					-- LETZTE ZEILE?
-				BL_SM = FERTIG;								-- JA -->
+			ZAINC = VCC;											-- ZEILENENDE: INC SRC UND DST ADRESSEN 
+			IF Y_INDEX[] >= BL_Y_CNT[] THEN							-- LETZTE ZEILE?
+				BL_SM = FERTIG;										-- JA => FERTIG
 			ELSE
-				ZYINC = VCC;								-- YINC ADDIEREN ZEILENENDE
-				BL_SM = NEW_LINE;							-- NEIN NEXT ->
+				BL_SM = NEW_LINE;									-- NEIN => NEXT LINE
 			END IF;
 		WHEN FERTIG => -------------------------- FERTIG
-			BLITTER_INT = VCC;								-- BLITTER INTERRUPT
-			LN7CLR = VCC;									-- BUSY BIT LÖSCHEN
-			IF BL_LN7==0 THEN								-- WARTEN BIS GELÖSCHT (GEHT NUR MIT 33MHz)
+			BL_NOTRUN = VCC;										-- BLITTER NOT RUN
+			BLITTER_INT = VCC;										-- BLITTER INTERRUPT
+			LN7_CLR = VCC;											-- BUSY BIT LÖSCHEN
+			IF (BL_LN7 == 0) & (BL_START == 0) THEN			-- WARTEN BIS GELÖSCHT (SYNC MIT 33MHz)
 				BL_SM = START;	
 			ELSE
 				BL_SM = FERTIG;
diff --git a/FPGA_by_Fredi/blitter.tdf.pdf b/FPGA_by_Fredi/blitter.tdf.pdf
deleted file mode 100644
index eb1e459adaab8cfb4205ae37e5c0f28f3276762a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf
index beb9946..dfd4093 100644
--- a/FPGA_by_Fredi/firebee1.bdf
+++ b/FPGA_by_Fredi/firebee1.bdf
@@ -875,7 +875,7 @@ applicable agreement for further details.
 )
 (pin
 	(output)
-	(rect 1832 832 2008 848)
+	(rect 2192 832 2368 848)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "LP_STR" (rect 90 0 130 12)(font "Arial" ))
 	(pt 0 8)
@@ -888,7 +888,7 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2008 848 2096 880))
+	(annotation_block (location)(rect 2280 848 2368 880))
 )
 (pin
 	(output)
@@ -1109,7 +1109,7 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2288 1416 2376 1448))
+	(annotation_block (location)(rect 2200 1416 2288 1448))
 )
 (pin
 	(output)
@@ -1640,7 +1640,7 @@ applicable agreement for further details.
 )
 (pin
 	(output)
-	(rect 1824 3280 2000 3296)
+	(rect 2112 3280 2288 3296)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "nSRCS" (rect 90 0 126 12)(font "Arial" ))
 	(pt 0 8)
@@ -1653,11 +1653,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2000 3296 2088 3328))
+	(annotation_block (location)(rect 2200 3296 2288 3328))
 )
 (pin
 	(output)
-	(rect 1824 3304 2000 3320)
+	(rect 1992 3304 2168 3320)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "nSRBLE" (rect 90 0 131 12)(font "Arial" ))
 	(pt 0 8)
@@ -1670,11 +1670,11 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2000 3320 2088 3352))
+	(annotation_block (location)(rect 2096 3320 2184 3352))
 )
 (pin
 	(output)
-	(rect 1824 3328 2000 3344)
+	(rect 1904 3328 2080 3344)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "nSRBHE" (rect 90 0 133 12)(font "Arial" ))
 	(pt 0 8)
@@ -1691,7 +1691,7 @@ applicable agreement for further details.
 )
 (pin
 	(output)
-	(rect 1824 3352 2000 3368)
+	(rect 1816 3352 1992 3368)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "nSRWE" (rect 90 0 128 12)(font "Arial" ))
 	(pt 0 8)
@@ -1704,7 +1704,7 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2000 3368 2088 3400))
+	(annotation_block (location)(rect 1904 3368 1992 3400))
 )
 (pin
 	(output)
@@ -1742,7 +1742,7 @@ applicable agreement for further details.
 )
 (pin
 	(output)
-	(rect 1824 3376 2000 3392)
+	(rect 1768 3376 1944 3392)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "nSROE" (rect 90 0 126 12)(font "Arial" ))
 	(pt 0 8)
@@ -1755,7 +1755,7 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2000 3392 2056 3408))
+	(annotation_block (location)(rect 1856 3392 1912 3408))
 )
 (pin
 	(output)
@@ -1980,7 +1980,7 @@ applicable agreement for further details.
 )
 (pin
 	(output)
-	(rect 1832 856 2008 872)
+	(rect 2072 856 2248 872)
 	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
 	(text "LPDIR" (rect 90 0 123 12)(font "Arial" ))
 	(pt 0 8)
@@ -1993,7 +1993,7 @@ applicable agreement for further details.
 		(line (pt 82 8)(pt 78 12)(line_width 1))
 		(line (pt 78 12)(pt 82 8)(line_width 1))
 	)
-	(annotation_block (location)(rect 2008 872 2096 904))
+	(annotation_block (location)(rect 2160 872 2248 904))
 )
 (pin
 	(output)
@@ -2226,7 +2226,7 @@ applicable agreement for further details.
 )
 (pin
 	(bidir)
-	(rect 1960 808 2136 824)
+	(rect 2304 808 2480 824)
 	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
 	(text "LP_D[7..0]" (rect 90 0 143 12)(font "Arial" ))
 	(pt 0 8)
@@ -2240,7 +2240,7 @@ applicable agreement for further details.
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
 	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2136 824 2224 952))
+	(annotation_block (location)(rect 2392 824 2480 952))
 )
 (pin
 	(bidir)
@@ -2263,7 +2263,7 @@ applicable agreement for further details.
 )
 (pin
 	(bidir)
-	(rect 2104 3232 2280 3248)
+	(rect 2320 3232 2496 3248)
 	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
 	(text "IO[17..0]" (rect 90 0 133 12)(font "Arial" ))
 	(pt 0 8)
@@ -2277,11 +2277,11 @@ applicable agreement for further details.
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
 	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2280 3248 2368 3632))
+	(annotation_block (location)(rect 2408 3248 2496 3632))
 )
 (pin
 	(bidir)
-	(rect 1944 3256 2120 3272)
+	(rect 2216 3256 2392 3272)
 	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
 	(text "SRD[15..0]" (rect 90 0 145 12)(font "Arial" ))
 	(pt 0 8)
@@ -2295,7 +2295,7 @@ applicable agreement for further details.
 		(line (pt 52 8)(pt 56 12)(line_width 1))
 	)
 	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 2120 3272 2208 3512))
+	(annotation_block (location)(rect 2304 3272 2392 3512))
 )
 (pin
 	(bidir)
@@ -3506,7 +3506,7 @@ applicable agreement for further details.
 		(line (pt 88 24)(pt 72 24)(line_width 3))
 	)
 	(drawing
-		(text "402923543" (rect 27 18 80 30)(font "Arial" ))
+		(text "570826775" (rect 27 18 80 30)(font "Arial" ))
 		(text "32" (rect 77 25 88 37)(font "Arial" ))
 		(line (pt 16 16)(pt 72 16)(line_width 1))
 		(line (pt 72 16)(pt 72 32)(line_width 1))
@@ -4302,10 +4302,6 @@ applicable agreement for further details.
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 		(bidir)
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-	(mapper
-		(pt 408 440)
-		(bidir)
-		)
 	(mapper
 		(pt 408 344)
 		(bidir)
@@ -4374,6 +4370,10 @@ applicable agreement for further details.
 		(pt 0 200)
 		(bidir)
 		)
+	(mapper
+		(pt 408 440)
+		(bidir)
+		)
 )
 (block
 	(rect 1264 2344 1672 2920)
@@ -4685,31 +4685,6 @@ applicable agreement for further details.
 	(pt 1264 3048)
 	(pt 1160 3048)
 )
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-	(pt 1672 3312)
-)
-(connector
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-	(pt 1824 3336)
-	(pt 1672 3336)
-)
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-	(pt 1824 3360)
-	(pt 1672 3360)
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-(connector
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-	(pt 1824 3384)
-	(pt 1672 3384)
-)
 (connector
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 	(pt 1264 2848)
@@ -4810,18 +4785,6 @@ applicable agreement for further details.
 	(pt 2080 80)
 	(bus)
 )
-(connector
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-	(pt 1672 3240)
-	(pt 2104 3240)
-	(bus)
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-(connector
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-	(pt 1672 3264)
-	(pt 1944 3264)
-	(bus)
-)
 (connector
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@@ -5444,16 +5407,6 @@ applicable agreement for further details.
 	(pt 1144 2008)
 	(pt 1264 2008)
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-	(pt 1672 840)
-	(pt 1832 840)
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-(connector
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-	(pt 1672 864)
-	(pt 1832 864)
-)
 (connector
 	(text "nACSI_ACK" (rect 1682 928 1742 940)(font "Arial" ))
 	(pt 1672 944)
@@ -5799,18 +5752,6 @@ applicable agreement for further details.
 	(pt 1160 920)
 	(pt 1264 920)
 )
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-	(pt 1960 816)
-	(bus)
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-(connector
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-	(pt 1672 896)
-	(pt 1904 896)
-	(bus)
-)
 (connector
 	(text "SCSI_D[7..0]" (rect 1786 1056 1852 1068)(font "Arial" ))
 	(pt 1672 1072)
@@ -5877,10 +5818,6 @@ applicable agreement for further details.
 	(pt 824 440)
 	(pt 952 440)
 )
-(connector
-	(pt 1120 328)
-	(pt 920 328)
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 (connector
 	(pt 920 328)
 	(pt 920 432)
@@ -5983,10 +5920,6 @@ applicable agreement for further details.
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 	(pt 368 -16)
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-(connector
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-	(pt 1120 48)
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 (connector
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 	(pt 464 -16)
@@ -5999,10 +5932,6 @@ applicable agreement for further details.
 	(pt 400 -16)
 	(pt 400 160)
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-(connector
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-	(pt 1120 48)
-)
 (connector
 	(text "CLK25M" (rect 802 -32 843 -20)(font "Arial" ))
 	(pt 736 -16)
@@ -6080,6 +6009,77 @@ applicable agreement for further details.
 	(pt 1264 2896)
 	(bus)
 )
+(connector
+	(pt 920 328)
+	(pt 1080 328)
+)
+(connector
+	(pt 1080 328)
+	(pt 1080 48)
+)
+(connector
+	(pt 736 48)
+	(pt 1080 48)
+)
+(connector
+	(text "ACSI_D[7..0]" (rect 1754 880 1820 892)(font "Arial" ))
+	(pt 1672 896)
+	(pt 1904 896)
+	(bus)
+)
+(connector
+	(text "IO[17..0]" (rect 2178 3224 2221 3236)(font "Arial" ))
+	(pt 1672 3240)
+	(pt 2320 3240)
+	(bus)
+)
+(connector
+	(text "nSRWE" (rect 1682 3344 1720 3356)(font "Arial" ))
+	(pt 1672 3360)
+	(pt 1816 3360)
+)
+(connector
+	(text "nSRBHE" (rect 1682 3320 1725 3332)(font "Arial" ))
+	(pt 1672 3336)
+	(pt 1904 3336)
+)
+(connector
+	(text "nSRBLE" (rect 1682 3296 1723 3308)(font "Arial" ))
+	(pt 1672 3312)
+	(pt 1992 3312)
+)
+(connector
+	(text "nSRCS" (rect 1682 3272 1718 3284)(font "Arial" ))
+	(pt 1672 3288)
+	(pt 2112 3288)
+)
+(connector
+	(text "SRD[15..0]" (rect 2074 3248 2129 3260)(font "Arial" ))
+	(pt 1672 3264)
+	(pt 2216 3264)
+	(bus)
+)
+(connector
+	(text "LP_D[7..0]" (rect 2154 800 2207 812)(font "Arial" ))
+	(pt 1672 816)
+	(pt 2304 816)
+	(bus)
+)
+(connector
+	(text "LP_STR" (rect 2042 824 2082 836)(font "Arial" ))
+	(pt 1672 840)
+	(pt 2192 840)
+)
+(connector
+	(text "LP_DIR" (rect 1922 848 1960 860)(font "Arial" ))
+	(pt 1672 864)
+	(pt 2072 864)
+)
+(connector
+	(text "nSROE" (rect 1682 3368 1718 3380)(font "Arial" ))
+	(pt 1672 3384)
+	(pt 1768 3384)
+)
 (junction (pt 2504 760))
 (junction (pt 1856 -64))
 (junction (pt 2424 -80))
diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index 2f3cd55..eec570b 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Tue Apr 18 20:21:44 2017
+Thu Jun 22 14:21:02 2017
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
new file mode 100644
index 0000000..f142f9b
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Thu Jun 22 14:20:25 2017
+Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+Revision Name : firebee1
+Top-level Entity Name : firebee1
+Family : Cyclone III
+Device : EP3C40F484C6
+Timing Models : Final
+Total logic elements : 20,227 / 39,600 ( 51 % )
+    Total combinational functions : 18,217 / 39,600 ( 46 % )
+    Dedicated logic registers : 5,767 / 39,600 ( 15 % )
+Total registers : 5906
+Total pins : 296 / 332 ( 89 % )
+Total virtual pins : 0
+Total memory bits : 355,360 / 1,161,216 ( 31 % )
+Embedded Multiplier 9-bit elements : 20 / 252 ( 8 % )
+Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
new file mode 100644
index 0000000..286e23f
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Thu Jun 22 14:14:13 2017
+Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+Revision Name : firebee1
+Top-level Entity Name : firebee1
+Family : Cyclone III
+Total logic elements : 21,573
+    Total combinational functions : 18,134
+    Dedicated logic registers : 5,773
+Total registers : 5901
+Total pins : 296
+Total virtual pins : 0
+Total memory bits : 355,360
+Embedded Multiplier 9-bit elements : 20
+Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index a041c37..49b639b 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -347,7 +347,7 @@ set_global_assignment -name TPD_REQUIREMENT "1 ns"
 set_global_assignment -name TSU_REQUIREMENT "1 ns"
 set_global_assignment -name TCO_REQUIREMENT "1 ns"
 set_global_assignment -name TH_REQUIREMENT "1 ns"
-set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz"
 set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
 
 # Analysis & Synthesis Assignments
@@ -445,21 +445,6 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 	# Assignment Group Assignments
 	# ============================
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
 
 # end ASSIGNMENT_GROUP(fast)
 # --------------------------
@@ -515,12 +500,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
 set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
 set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
@@ -631,28 +610,33 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_C
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to LP_D
 set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
 set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
 set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
 set_location_assignment PIN_V2 -to nDREQ0
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name SLEW_RATE 0 -to LP_D
+set_instance_assignment -name SLEW_RATE 0 -to LP_STR
+set_instance_assignment -name SLEW_RATE 0 -to LPDIR
+set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_ror128.cmp
+set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_ror128.tdf
 set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
 set_global_assignment -name SOURCE_FILE Video/BLITTER/altsyncram0.cmp
 set_global_assignment -name AHDL_FILE Video/BLITTER/altsyncram0.tdf
@@ -715,8 +699,6 @@ set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
 set_global_assignment -name VHDL_FILE lpm_latch0.vhd
 set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
 set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
 set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
 set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
 set_global_assignment -name QIP_FILE altpll2.qip
@@ -834,4 +816,13 @@ set_global_assignment -name INCLUDE_FILE Video/BLITTER/lpm_clshift383.inc
 set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift384.qip
 set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift144.qip
 set_global_assignment -name QIP_FILE FPGA_DATE.qip
+set_global_assignment -name QIP_FILE Video/Doppelzeilen_Fifo.qip
+set_global_assignment -name QIP_FILE Video/shiftreg_dpz.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_ror128.qip
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
+set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_by_Fredi/firebee1.rbf b/FPGA_by_Fredi/firebee1.rbf
deleted file mode 100644
index 57fa4418da290793ac1399a37d709d1562ba7537..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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HcmV?d00001

diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
new file mode 100644
index 0000000..75fecaf
--- /dev/null
+++ b/FPGA_by_Fredi/firebee1.tan.summary
@@ -0,0 +1,276 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type           : Worst-case tsu
+Slack          : -10.868 ns
+Required Time  : 1.000 ns
+Actual Time    : 11.868 ns
+From           : FB_SIZE0
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
+From Clock     : --
+To Clock       : MAIN_CLK
+Failed Paths   : 9538
+
+Type           : Worst-case tco
+Slack          : -96.119 ns
+Required Time  : 1.000 ns
+Actual Time    : 97.119 ns
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
+To             : FB_AD[16]
+From Clock     : MAIN_CLK
+To Clock       : --
+Failed Paths   : 8562
+
+Type           : Worst-case tpd
+Slack          : -13.155 ns
+Required Time  : 1.000 ns
+Actual Time    : 14.155 ns
+From           : nFB_CS2
+To             : FB_AD[27]
+From Clock     : --
+To Clock       : --
+Failed Paths   : 550
+
+Type           : Worst-case th
+Slack          : -0.274 ns
+Required Time  : 1.000 ns
+Actual Time    : 1.274 ns
+From           : VD[18]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]
+From Clock     : --
+To Clock       : MAIN_CLK
+Failed Paths   : 11
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
+Slack          : -92.241 ns
+Required Time  : 25.00 MHz ( period = 39.999 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
+From Clock     : MAIN_CLK
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+Failed Paths   : 6009
+
+Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+Slack          : -90.899 ns
+Required Time  : 96.01 MHz ( period = 10.416 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
+From Clock     : MAIN_CLK
+To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+Failed Paths   : 5954
+
+Type           : Clock Setup: 'MAIN_CLK'
+Slack          : -63.646 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : 10.64 MHz ( period = 93.949 ns )
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
+From Clock     : MAIN_CLK
+To Clock       : MAIN_CLK
+Failed Paths   : 41189
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : -17.307 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_SRC_ADR[1]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO
+From Clock     : MAIN_CLK
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+Failed Paths   : 26373
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : -12.626 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_X_CNT[0]
+To             : Video:Fredi_Aschwanden|BLITTER:BLITTER|SRC_IADR[30]
+From Clock     : MAIN_CLK
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 22076
+
+Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
+Slack          : -5.032 ns
+Required Time  : 16.00 MHz ( period = 62.499 ns )
+Actual Time    : N/A
+From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+Failed Paths   : 2839
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+Slack          : -3.374 ns
+Required Time  : 66.00 MHz ( period = 15.151 ns )
+Actual Time    : N/A
+From           : FB_ALE
+To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+Failed Paths   : 33
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+Slack          : 2.966 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 3.965 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
+Slack          : 13.509 ns
+Required Time  : 2.00 MHz ( period = 499.999 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_DIR_NS1
+From Clock     : MAIN_CLK
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
+Slack          : 26.728 ns
+Required Time  : 0.50 MHz ( period = 1999.998 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
+From Clock     : MAIN_CLK
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'MAIN_CLK'
+Slack          : -6.235 ns
+Required Time  : 33.00 MHz ( period = 30.303 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]
+To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2]
+From Clock     : MAIN_CLK
+To Clock       : MAIN_CLK
+Failed Paths   : 5610
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
+Slack          : -0.919 ns
+Required Time  : 25.00 MHz ( period = 39.999 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+To             : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
+Failed Paths   : 405
+
+Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
+Slack          : 0.456 ns
+Required Time  : 16.00 MHz ( period = 62.499 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
+From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
+Slack          : 0.502 ns
+Required Time  : 2.00 MHz ( period = 499.999 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
+Slack          : 0.502 ns
+Required Time  : 0.50 MHz ( period = 1999.998 ns )
+Actual Time    : N/A
+From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
+To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
+From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
+To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
+Slack          : 0.502 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
+To             : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
+Slack          : 0.502 ns
+Required Time  : 96.01 MHz ( period = 10.416 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+To             : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
+From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
+Slack          : 1.815 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
+To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
+Slack          : 2.291 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|inst90~_Duplicate_4
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
+Slack          : 2.612 ns
+Required Time  : 66.00 MHz ( period = 15.151 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
+To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
+Failed Paths   : 0
+
+Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
+Slack          : 4.336 ns
+Required Time  : 132.01 MHz ( period = 7.575 ns )
+Actual Time    : N/A
+From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
+To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]
+From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
+Failed Paths   : 0
+
+Type           : Total number of failed paths
+Slack          : 
+Required Time  : 
+Actual Time    : 
+From           : 
+To             : 
+From Clock     : 
+To Clock       : 
+Failed Paths   : 129149
+
+--------------------------------------------------------------------------------------
+
diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws
deleted file mode 100644
index 9c279dd..0000000
--- a/FPGA_by_Fredi/firebeei1.qws
+++ /dev/null
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-S12315A05B3132372E2E305D2C0D0A09646174613837785B3132372E2E305D2C0D0A0964C6
-S12315C06174613838785B3132372E2E305D2C0D0A09646174613839785B3132372E2E30B3
-S12315E05D2C0D0A096461746138785B3132372E2E305D2C0D0A09646174613930785B31DB
-S123160032372E2E305D2C0D0A09646174613931785B3132372E2E305D2C0D0A0964617482
-S1231620613932785B3132372E2E305D2C0D0A09646174613933785B3132372E2E305D2C09
-S12316400D0A09646174613934785B3132372E2E305D2C0D0A09646174613935785B3132F8
-S1231660372E2E305D2C0D0A09646174613936785B3132372E2E305D2C0D0A09646174614E
-S12316803937785B3132372E2E305D2C0D0A09646174613938785B3132372E2E305D2C0D53
-S12316A00A09646174613939785B3132372E2E305D2C0D0A096461746139785B3132372ED0
-S12316C02E305D2C0D0A0973656C5B372E2E305D0D0A290D0A0D0A52455455524E53202850
-S11A16E00D0A09726573756C745B3132372E2E305D0D0A293B0D0AD0
-S9030000FC
diff --git a/FPGA_by_Fredi/serv_req_info.txt b/FPGA_by_Fredi/serv_req_info.txt
deleted file mode 100644
index 51a4176..0000000
--- a/FPGA_by_Fredi/serv_req_info.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>VDB</sub_system>
-	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
-	<line>4101</line>
-	<callstack>
-	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
-	</callstack>
-	<error>loc &lt; m_value-&gt;size()</error>
-	<date>Tue Oct 13 17:01:46 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>loc &lt; m_value-&gt;size()
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>VDB</sub_system>
-	<file>/quartus/db/vdb/vdb_value_bus.cpp</file>
-	<line>4101</line>
-	<callstack>
-	0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54)
-	</callstack>
-	<error>loc &lt; m_value-&gt;size()</error>
-	<date>Tue Oct 13 17:11:00 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>loc &lt; m_value-&gt;size()
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: GED</error>
-	<date>Wed Oct 14 23:17:06 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: GED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: SFW, STED</error>
-	<date>Thu Oct 15 19:23:19 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: SFW, STED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<callstack>
-	0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6)
-	</callstack>
-	<error>Current editor: RPW, SFW
-Current dockable window: PJN</error>
-	<date>Fri Oct 16 00:14:03 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 0X1002D196
-Current editor: RPW, SFW
-Current dockable window: PJN
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: SFW</error>
-	<date>Sat Oct 17 19:01:54 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: SFW
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>AFC</sub_system>
-	<file>/quartus/gcl/afc/afc_child_frame.cpp</file>
-	<line>1940</line>
-	<callstack>
-	0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a)
-	</callstack>
-	<error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])</error>
-	<date>Mon Oct 19 21:58:36 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>(bar != NULL) &amp;&amp; bar-&gt;Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0])
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
-<internal_error>
-	<executable>quartus.exe</executable>
-	<sub_system>unknown</sub_system>
-	<file>unknown</file>
-	<line>0</line>
-	<error>Current editor: RPW, GED</error>
-	<date>Tue Oct 20 00:53:11 2009</date>
-	<version>Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition</version>
-	<full_error>Access Violation at 00000000
-Current editor: RPW, GED
-Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition </full_error>
-</internal_error>
-
diff --git a/FPGA_by_Fredi/sopc_builder_log.txt b/FPGA_by_Fredi/sopc_builder_log.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt
deleted file mode 100644
index 5c139c4..0000000
--- a/FPGA_by_Fredi/undo_redo.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-GED
-
-	Undo Commands
-	     1.	Properties
-	     2.	Move
-	     3.	Paste
-	     4.	Properties
-	     5.	Properties
-	     6.	Move
-	     7.	Paste
-
-

From 38144f937c8d1fc708e20dc93189891c3dc87959 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20G=C3=A1lvez?= <dgalvez75@gmail.com>
Date: Mon, 9 Apr 2018 17:33:13 +0200
Subject: [PATCH 06/16] Create README.md

---
 FPGA_by_Fredi/README.md | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 FPGA_by_Fredi/README.md

diff --git a/FPGA_by_Fredi/README.md b/FPGA_by_Fredi/README.md
new file mode 100644
index 0000000..f0544d3
--- /dev/null
+++ b/FPGA_by_Fredi/README.md
@@ -0,0 +1,5 @@
+These FPGA's sources can be built with Quartus 9.1.
+
+This repository should be only used to sync(like a kind of mirror) with Fredi's source tree.
+
+Please for further development create a new repository and merge from here.

From 6021b6ee961c8b1780e89e934d47142fc6ad5153 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Sat, 28 Apr 2018 11:27:16 +0200
Subject: [PATCH 07/16] remove unneeded files

---
 FPGA_by_Fredi/Coldari1.qsf                    |  44 --
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       | 617 ---------------
 FPGA_by_Fredi/blitter.tdf.bak                 | 700 ------------------
 FPGA_by_Fredi/firebee1.fit.summary            |  16 -
 FPGA_by_Fredi/firebee1.map.summary            |  14 -
 FPGA_by_Fredi/firebee1.tan.summary            | 276 -------
 6 files changed, 1667 deletions(-)
 delete mode 100644 FPGA_by_Fredi/Coldari1.qsf
 delete mode 100644 FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
 delete mode 100644 FPGA_by_Fredi/blitter.tdf.bak
 delete mode 100644 FPGA_by_Fredi/firebee1.fit.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.map.summary
 delete mode 100644 FPGA_by_Fredi/firebee1.tan.summary

diff --git a/FPGA_by_Fredi/Coldari1.qsf b/FPGA_by_Fredi/Coldari1.qsf
deleted file mode 100644
index da581cf..0000000
--- a/FPGA_by_Fredi/Coldari1.qsf
+++ /dev/null
@@ -1,44 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2009 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II
-# Version 9.1 Build 222 10/21/2009 SJ Web Edition
-# Date created = 12:11:46  March 06, 2010
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Coldari1_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Stratix II"
-set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY Coldari1
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46  MARCH 06, 2010"
-set_global_assignment -name LAST_QUARTUS_VERSION 9.1
\ No newline at end of file
diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
deleted file mode 100644
index 0ade395..0000000
--- a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
+++ /dev/null
@@ -1,617 +0,0 @@
-TITLE "VIDEO MODUSE UND CLUT CONTROL";
-
--- CREATED BY FREDI ASCHWANDEN
-
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "lpm_bustri_BYT.inc";
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	nFB_BURST : INPUT;
-	FB_ADR[31..0] : INPUT;
-	CLK33M : INPUT;
-	CLK25M : INPUT;
-	BLITTER_RUN : INPUT;
-	CLK_VIDEO : INPUT;
-	VR_D[8..0] : INPUT;
-	VR_BUSY : INPUT;
-	COLOR8 : OUTPUT;
-	ACP_CLUT_RD : OUTPUT;
-	COLOR1 : OUTPUT;
-	FALCON_CLUT_RDH : OUTPUT;
-	FALCON_CLUT_RDL : OUTPUT;
-	FALCON_CLUT_WR[3..0] : OUTPUT;
-	ST_CLUT_RD : OUTPUT;
-	ST_CLUT_WR[1..0] : OUTPUT;
-	CLUT_MUX_ADR[3..0] : OUTPUT;
-	HSYNC : OUTPUT;
-	VSYNC : OUTPUT;
-	nBLANK : OUTPUT;
-	nSYNC : OUTPUT;
-	nPD_VGA : OUTPUT;
-	FIFO_RDE : OUTPUT;
-	COLOR2 : OUTPUT;
-	COLOR4 : OUTPUT;
-	PIXEL_CLK : OUTPUT;
-	CLUT_OFF[3..0] : OUTPUT;
-	BLITTER_ON : OUTPUT;
-	VIDEO_RAM_CTR[15..0] : OUTPUT;
-	VIDEO_MOD_TA : OUTPUT;
-	CCR[23..0] : OUTPUT;
-	CCSEL[2..0] : OUTPUT;
-	ACP_CLUT_WR[3..0] : OUTPUT;
-	INTER_ZEI : OUTPUT;
-	DOP_FIFO_CLR : OUTPUT;
-	VIDEO_RECONFIG : OUTPUT;
-	VR_WR : OUTPUT;
-	VR_RD : OUTPUT;
-	CLR_FIFO : OUTPUT;
-	DPZF_CLKENA: OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	CLK17M						:DFF;
-	CLK13M						:DFF;
-	ACP_CLUT_CS					:NODE;
-	ACP_CLUT					:NODE;
-	VIDEO_PLL_CONFIG_CS			:NODE;
-	VR_WR						:DFF;
-	VR_DOUT[8..0]				:DFFE;
-	VR_FRQ[7..0]				:DFFE;
-	VIDEO_PLL_RECONFIG_CS		:NODE;
-	VIDEO_RECONFIG				:DFF;
-	FALCON_CLUT_CS				:NODE;
-	FALCON_CLUT					:NODE;
-	ST_CLUT_CS					:NODE;
-	ST_CLUT						:NODE;
-	FB_B[3..0]					:NODE;
-	FB_16B[1..0]				:NODE;
-	ST_SHIFT_MODE[2..0]			:DFFE;
-	ST_SHIFT_MODE_CS			:NODE;
-	FALCON_SHIFT_MODE[10..0]	:DFFE;
-	FALCON_SHIFT_MODE_CS		:NODE;
-	CLUT_MUX_ADR[3..0]			:DFF;
-	CLUT_MUX_AV[1..0][3..0]		:DFF;
-	ACP_VCTR_CS					:NODE;
-	ACP_VCTR[31..0]				:DFFE;
-	CCR_CS						:NODE;
-	CCR[23..0]					:DFFE;
-	ACP_VIDEO_ON				:NODE;
-	SYS_CTR[6..0]				:DFFE;
-	SYS_CTR_CS					:NODE;
-	VDL_LOF[15..0]				:DFFE;
-	VDL_LOF_CS					:NODE;
-	VDL_LWD[15..0]				:DFFE;
-	VDL_LWD_CS					:NODE;
--- DIV. CONTROL REGISTER
-	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
-	HSYNC						:DFF;
-	HSYNC_I[7..0]				:DFF;
-	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
-	HSYNC_START					:DFF;
-	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
-	VSYNC						:DFF;
-	VSYNC_I[2..0]				:DFF;
-	nBLANK						:DFF;
-	DISP_ON						:DFF;
-	DPO_ZL						:DFF;
-	DPO_ON						:DFF;
-	DPO_OFF						:DFF;
-	VDTRON						:DFF;
-	VDO_ZL						:DFF;
-	VDO_ON						:DFF;
-	VDO_OFF						:DFF;
-	VHCNT[12..0]				:DFF;
-	SUB_PIXEL_CNT[6..0]			:DFFE;
-	VVCNT[12..0]				:DFFE;
-	VERZ[2..0][9..0]			:DFF;
-	RAND[6..0]					:DFF;
-	RAND_ON						:NODE;
-	FIFO_RDE					:DFF;
-	CLR_FIFO					:DFFE;
-	START_ZEILE					:DFFE;
-	SYNC_PIX					:DFF;
-	SYNC_PIX1					:DFF;
-	SYNC_PIX2					:DFF;
-	CCSEL[2..0]					:DFF;
-	COLOR16						:NODE;
-	COLOR24						:NODE;		-- IST ABER 32BIT BREIT
-	TE							:NODE;
--- HORIZONTAL
-	RAND_LINKS[12..0]			:NODE;
-	HDIS_START[12..0]			:NODE;
-	STARTP[12..0]				:NODE; 
-	HDIS_END[12..0]				:NODE;  
-	RAND_RECHTS[12..0]			:NODE;
-	MULF[12..0]					:NODE;
-	HS_START[12..0]				:NODE;
-	H_TOTAL[12..0]				:NODE;
-	HDIS_LEN[12..0]				:NODE;
-	WPL[15..0]					:NODE;
-	VDL_HHT[12..0]				:DFFE;
-	VDL_HHT_CS					:NODE;
-	VDL_HBE[12..0]				:DFFE;
-	VDL_HBE_CS					:NODE;
-	VDL_HDB[12..0]				:DFFE;
-	VDL_HDB_CS					:NODE;
-	VDL_HDE[12..0]				:DFFE;
-	VDL_HDE_CS					:NODE;
-	VDL_HBB[12..0]				:DFFE;
-	VDL_HBB_CS					:NODE;
-	VDL_HSS[12..0]				:DFFE;
-	VDL_HSS_CS					:NODE;
--- VERTIKAL
-	RAND_OBEN[12..0]			:NODE; 
-	VDIS_START[12..0]			:NODE; 
-	VDIS_END[12..0]				:NODE; 
-	RAND_UNTEN[12..0]			:NODE; 
-	VS_START[12..0]				:NODE; 
-	V_TOTAL[12..0]				:NODE;  
-	FALCON_VIDEO				:NODE;
-	ST_VIDEO					:NODE;
-	INTER_ZEI					:DFF;
-	DOP_FIFO_CLR				:DFF;
-	
-	VIDEL_CS					:NODE;
-	VDL_VBE[12..0]				:DFFE;
-	VDL_VBE_CS					:NODE;
-	VDL_VDB[12..0]				:DFFE;
-	VDL_VDB_CS					:NODE;
-	VDL_VDE[12..0]				:DFFE;
-	VDL_VDE_CS					:NODE;
-	VDL_VBB[12..0]				:DFFE;
-	VDL_VBB_CS					:NODE;
-	VDL_VSS[12..0]				:DFFE;
-	VDL_VSS_CS					:NODE;
-	VDL_VFT[12..0]				:DFFE;
-	VDL_VFT_CS					:NODE;
-	VDL_VCT[12..0]				:DFFE;
-	VDL_VCT_CS					:NODE;
-	VDL_VMD[3..0]				:DFFE;
-	VDL_VMD_CS					:NODE;
-	VDL_BPP_CS					:NODE;
-	VDL_PH_CS					:NODE;
-	VDL_PV_CS					:NODE;
-
-BEGIN
--- BYT SELECT 32 BIT
-	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
-	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
-		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
-	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
-		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
-		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
--- BYT SELECT 16 BIT
-	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
-	FB_16B1 = FB_ADR[0]==1									-- ADR==1
-		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
--- VIDEL CS
-	VIDEL_CS = !nFB_CS1 & FB_ADR[19..8]==H"F82";						-- FFF'F8200-FFF'F82FF
--- ACP CLUT --
-	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
-	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
-	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
-	CLUT_TA.CLK = MAIN_CLK;
-	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
---FALCON CLUT --
-	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
-	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
-	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
-	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
--- ST CLUT --
-	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
-	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
-	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
--- ST SHIFT MODE
-	ST_SHIFT_MODE[].CLK = MAIN_CLK;
-	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
-	ST_SHIFT_MODE[] = FB_AD[26..24];
-	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
-	COLOR1 = ST_SHIFT_MODE[]==B"010" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
-	COLOR2 = ST_SHIFT_MODE[]==B"001" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
-	COLOR4 = ST_SHIFT_MODE[]==B"000" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
--- FALCON SHIFT MODE
-	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
-	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
-	FALCON_SHIFT_MODE[] = FB_AD[26..16];
-	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
-	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
-	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
-	COLOR1  = FALCON_SHIFT_MODE[] == H"400" & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR4  = FALCON_SHIFT_MODE[] == H"000" & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR8  = FALCON_SHIFT_MODE[] == H"010" & FALCON_VIDEO & !ACP_VIDEO_ON;
-	COLOR16 = FALCON_SHIFT_MODE[] == H"100" & FALCON_VIDEO & !ACP_VIDEO_ON;
--- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN
-	ACP_VCTR[].CLK = MAIN_CLK;
-	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $F000'0400
-	ACP_VCTR[31..8] = FB_AD[31..8];
-	ACP_VCTR[5..0] = FB_AD[5..0];
-	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
-	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
-	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
-	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
-	ACP_VIDEO_ON = ACP_VCTR0;
-	nPD_VGA = ACP_VCTR1;
--- VIDEO PLL CONFIG
-	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $F000'0600-7FF ->6/2 WORD RESP LONG ONLY
-	VR_WR.CLK = MAIN_CLK;
-	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
-	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
-	VR_DOUT[].CLK = MAIN_CLK;
-	VR_DOUT[].ENA = !VR_BUSY;
-	VR_DOUT[] = VR_D[];
-	VR_FRQ[].CLK = MAIN_CLK;
-	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
-	VR_FRQ[] = FB_AD[23..16];
--- VIDEO PLL RECONFIG
-	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $F000'0800 
-	VIDEO_RECONFIG.CLK = MAIN_CLK;
-	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
-------------------------------------------------------------------------------------------------------------------------
-	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
--------------- COLOR MODE IM ACP SETZEN	
-	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
-	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
-	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
--- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
-	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
-	ACP_VCTR[7..6].ENA = (FALCON_SHIFT_MODE_CS # ST_SHIFT_MODE_CS) & !nFB_WR;
-	FALCON_VIDEO	   = ACP_VCTR7;
-	ST_VIDEO		   = ACP_VCTR6 & !ACP_VCTR7;
-	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
-	ST_CLUT            = ST_VIDEO     & !ACP_VIDEO_ON & !COLOR1;
-	CCSEL[].CLK = PIXEL_CLK;
-	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
-			# B"001" & FALCON_CLUT
-			# B"100" & ACP_CLUT
-			# B"101" & COLOR16
-			# B"110" & COLOR24
-			# B"111" & RAND_ON;
--- DIVERSE (VIDEO)-REGISTER ----------------------------
--- RANDFARBE
-	CCR[].CLK = MAIN_CLK;
-	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";								-- $F004'0404/4
-	CCR[] = FB_AD[23..0];
-	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
-	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
-	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
---SYS CTR
-	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $FFFF'8006
-	SYS_CTR[].CLK = MAIN_CLK;
-	SYS_CTR[6..0] = FB_AD[22..16];
-	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
-	BLITTER_ON = SYS_CTR3;
---VDL_LOF
-	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $F820E/2
-	VDL_LOF[].CLK = MAIN_CLK;
-	VDL_LOF[] = FB_AD[31..16];
-	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
-	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
---VDL_LWD
-	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $F8210/2
-	VDL_LWD[].CLK = MAIN_CLK;
-	VDL_LWD[] = FB_AD[31..16];
-	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
-	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
--- DATEN AUFLÖSUNG
-	VDL_BPP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C109";						-- $F8212: BITS PER PIXEL
-	VDL_PH_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10A";						-- $F8214: BREITE IN PIXE
-	VDL_PV_CS  = !nFB_CS1 & FB_ADR[19..1]==H"7C10B";						-- $F8216: BREITE IN PIXE
--- HORIZONTAL
--- VDL_HHT
-	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
-	VDL_HHT[].CLK = MAIN_CLK;
-	VDL_HHT[] = FB_AD[28..16];
-	VDL_HHT[12..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
-	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
--- VDL_HBE
-	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
-	VDL_HBE[].CLK = MAIN_CLK;
-	VDL_HBE[] = FB_AD[28..16];
-	VDL_HBE[12..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
-	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
--- VDL_HDB
-	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
-	VDL_HDB[].CLK = MAIN_CLK;
-	VDL_HDB[] = FB_AD[28..16];
-	VDL_HDB[12..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
-	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
--- VDL_HDE
-	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
-	VDL_HDE[].CLK = MAIN_CLK;
-	VDL_HDE[] = FB_AD[28..16];
-	VDL_HDE[12..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
-	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
--- VDL_HBB
-	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
-	VDL_HBB[].CLK = MAIN_CLK;
-	VDL_HBB[] = FB_AD[28..16];
-	VDL_HBB[12..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
-	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
--- VDL_HSS
-	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
-	VDL_HSS[].CLK = MAIN_CLK;
-	VDL_HSS[] = FB_AD[28..16];
-	VDL_HSS[12..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
-	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
--- VERTIKAL
--- VDL_VBE
-	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
-	VDL_VBE[].CLK = MAIN_CLK;
-	VDL_VBE[] = FB_AD[28..16];
-	VDL_VBE[12..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
-	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
--- VDL_VDB
-	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
-	VDL_VDB[].CLK = MAIN_CLK;
-	VDL_VDB[] = FB_AD[28..16];
-	VDL_VDB[12..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
-	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
--- VDL_VDE
-	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
-	VDL_VDE[].CLK = MAIN_CLK;
-	VDL_VDE[] = FB_AD[28..16];
-	VDL_VDE[12..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
-	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
--- VDL_VBB
-	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
-	VDL_VBB[].CLK = MAIN_CLK;
-	VDL_VBB[] = FB_AD[28..16];
-	VDL_VBB[12..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
-	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
--- VDL_VSS
-	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
-	VDL_VSS[].CLK = MAIN_CLK;
-	VDL_VSS[] = FB_AD[28..16];
-	VDL_VSS[12..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
-	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
--- VDL_VFT
-	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
-	VDL_VFT[].CLK = MAIN_CLK;
-	VDL_VFT[] = FB_AD[28..16];
-	VDL_VFT[12..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
-	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
--- VDL_VCT
-	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
-	VDL_VCT[].CLK = MAIN_CLK;
-	VDL_VCT[] = FB_AD[28..16];
-	VDL_VCT[12..8].ENA 	= VDL_VCT_CS & !nFB_WR & FB_B0;
-	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
--- VDL_VMD
-	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
-	VDL_VMD[].CLK = MAIN_CLK;
-	VDL_VMD[] = FB_AD[19..16];
-	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						ST_SHIFT_MODE_CS 		& (B"00000",ST_SHIFT_MODE[],H"FF") 
-					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
-					  # SYS_CTR_CS 				& (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0])	 
-					  # VDL_LOF_CS 				& VDL_LOF[]
-					  # VDL_LWD_CS 				& WPL[]
-					  # VDL_BPP_CS 				& (0 + (32 & COLOR24) + (16 & COLOR16) + (8 & COLOR8) + (4 & COLOR4) + (1 & COLOR1))
-					  # VDL_PH_CS  				& (0,HDIS_LEN[])
-					  # VDL_PV_CS  				& (0,(VDIS_END[] - VDIS_START[] + 1))
-					  #	VDL_HBE_CS 				& (0,VDL_HBE[])
-					  #	VDL_HDB_CS 				& (0,VDL_HDB[])
-					  #	VDL_HDE_CS 				& (0,VDL_HDE[])
-					  #	VDL_HBB_CS 				& (0,VDL_HBB[])
-					  #	VDL_HSS_CS 				& (0,VDL_HSS[])
-					  #	VDL_HHT_CS 				& (0,VDL_HHT[])
-					  #	VDL_VBE_CS 				& (0,VDL_VBE[])
-					  #	VDL_VDB_CS 				& (0,VDL_VDB[])
-					  #	VDL_VDE_CS 				& (0,VDL_VDE[])
-					  #	VDL_VBB_CS 				& (0,VDL_VBB[])
-					  #	VDL_VSS_CS 				& (0,VDL_VSS[])
-					  #	VDL_VFT_CS 				& (0,VDL_VFT[])
-					  #	VDL_VCT_CS 				& (0,VDL_VCT[])			 
-					  #	VDL_VMD_CS 				& (0,VDL_VMD[])
- 					  #	ACP_VCTR_CS 			& ACP_VCTR[31..16]
- 					  #	CCR_CS 					& (0,CCR[23..16])
- 					  #	VIDEO_PLL_CONFIG_CS 	& (0,VR_DOUT[])
- 					  #	VIDEO_PLL_RECONFIG_CS 	& (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
-					  ,(ACP_VCTR_CS # CCR_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VIDEL_CS # SYS_CTR_CS) & !nFB_OE);
- 	FB_AD[15..0] = lpm_bustri_WORD(
- 					   	ACP_VCTR_CS 			& ACP_VCTR[15..0]
- 					  #	CCR_CS 					& CCR[15..0]
- 					  ,(ACP_VCTR_CS # CCR_CS) & !nFB_OE);
-	VIDEO_MOD_TA = CLUT_TA # ACP_VCTR_CS # SYS_CTR_CS # VIDEL_CS;
--- VIDEO AUSGABE SETZEN --------------------------------------------------------------
-	CLK17M.CLK = CLK33M;
-	CLK17M = !CLK17M;
-	CLK13M.CLK = CLK25M;
-	CLK13M = !CLK13M;
-	TE = VDL_VMD2 & !VDL_VCT0 # !VDL_VMD2 & VDL_VCT0;		-- 1 WENN HALBE FREQUENZ UND 320*... (200.240.400.480)
-	PIXEL_CLK = CLK13M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
-			#	CLK17M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
-			#	CLK25M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
-			#	CLK33M    & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
-			#	CLK25M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	CLK33M    &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#	CLK_VIDEO &  ACP_VIDEO_ON & ACP_VCTR[9];
--- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -----------------------------------------------------
-	HSY_LEN[].CLK = MAIN_CLK;		
-	HSY_LEN[] = 19 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 &  TE
-			#	25 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 &  TE
-			#	38 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  VDL_VCT2 & !TE
-			#	50 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VCT2 & !TE
-			#	38 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
-			#	50 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
-			#   VR_FRQ[] &  ACP_VIDEO_ON & ACP_VCTR[9];					-- hsync puls length in pixeln=frequenz/ = ca. 1us
--- MULTIPLIKATIONS FAKTOR ----------------------------------------
- 	MULF[] =  1  & !ST_VIDEO & ( TE #  VDL_VCT0)
-			# 2  & !ST_VIDEO &  !TE & !VDL_VCT0
-			# 4  &  ST_VIDEO &   TE &  VDL_VCT0
-			# 8  &  ST_VIDEO & ( TE & !VDL_VCT0 # !TE &  VDL_VCT0)							-- WENN ST_VIDEO VORTEILER *8
-			# 16 &  ST_VIDEO &  !TE & !VDL_VCT0;
- -- BREITE IN PIXELN ------------------------------------------------	 	
-	HDIS_LEN[] =  320 &  TE							& !ACP_VIDEO_ON
-			   #  640 & !TE							& !ACP_VIDEO_ON
-			   # (HDIS_END[] - HDIS_START[] + 1)	&  ACP_VIDEO_ON;
-	WPL[] = VDL_LWD[]						  		& !ACP_VIDEO_ON
-		  # (0,HDIS_LEN[12..4])		& COLOR1  		&  ACP_VIDEO_ON
-		  # (0,HDIS_LEN[12..1])		& COLOR8  		&  ACP_VIDEO_ON
-		  #	(0,HDIS_LEN[]) 			& COLOR16 		&  ACP_VIDEO_ON
-		  #	(0,HDIS_LEN[],B"0")		& COLOR24 		&  ACP_VIDEO_ON;
--- DOPPELZEILENMODUS ---------------------------------------------
-	INTER_ZEI.CLK = PIXEL_CLK;
-	INTER_ZEI =  VDL_VMD0 & (FALCON_VIDEO # ST_VIDEO) & (VVCNT0!=VDIS_START0) & DPZF_CLKENA;	-- EINSCHIEBEZEILE BEI UNGERADEN ZEILEN AB DISPLAY START UND NICHT AM ANFANG WEGEN DATATSHIFTOUT
-	DOP_FIFO_CLR.CLK = PIXEL_CLK;
-	DOP_FIFO_CLR =  INTER_ZEI & (VHCNT[]==HS_START[]);			-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER UNGERADEN ZEILEN
-	DPZF_CLKENA = VVCNT[] > 4;									-- FIFO DATASHIFTOUT UNTERBINDEN FÜR DOP.ZEI.FIFO
--- TIMING HORIZONTAL				
-	STARTP[] = RAND_LINKS[] + RAND_RECHTS[] - HDIS_LEN[];							-- 2x MITTE SCREEN
-	RAND_LINKS[] 	=  VDL_HBE[] 								&  ACP_VIDEO_ON
-					# ((VDL_HBE[] + 1) * MULF[])				& !ACP_VIDEO_ON; 	--  
-	HDIS_START[] 	=  VDL_HDB[] 								&  ACP_VIDEO_ON
-					# ((RAND_LINKS[] + 1) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	-- MONITOR GANZ RECHTS
-					# (((0,STARTP[12..1]) + 1) 	&  VDL_VCT0)	& !ACP_VIDEO_ON;  	-- RGB/TV EINMITTEN ZWISCHEN BLANKS
-	HDIS_END[]	 	=  VDL_HDE[] 								&  ACP_VIDEO_ON
-					# (HDIS_START[] + HDIS_LEN[] - 1) 			& !ACP_VIDEO_ON; 	--  
-	RAND_RECHTS[] 	=  VDL_HBB[] 								&  ACP_VIDEO_ON
-					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HBB[]) * MULF[] + 1)& !ACP_VIDEO_ON; 	--  
-	HS_START[]		=  VDL_HSS[] 								&  ACP_VIDEO_ON
-					# ((VDL_HHT[] + (2 & !ST_VIDEO) + VDL_HSS[]) * MULF[] + 1)& !ACP_VIDEO_ON; 			--  
-	H_TOTAL[] 		=  VDL_HHT[] 								&  ACP_VIDEO_ON
-					# ((VDL_HHT[] + 2) * 2 * MULF[])			& !ACP_VIDEO_ON; 			--  
--- TIMING VERTICAL 					
-	RAND_OBEN[]		=  VDL_VBE[]								&  ACP_VIDEO_ON
-					# ((0,VDL_VBE[12..1]) 		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# (VDL_VBE[]	 	 		&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-	VDIS_START[]	=  VDL_VDB[]								&  ACP_VIDEO_ON
-					# (((0,VDL_VDB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# ((   VDL_VDB[]       + 1) &  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-	VDIS_END[]		=  VDL_VDE[]								&  ACP_VIDEO_ON
-					# ((0,VDL_VDE[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# (   VDL_VDE[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-	RAND_UNTEN[]	=  VDL_VBB[]								&  ACP_VIDEO_ON
-					# (((0,VDL_VBB[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# ((   VDL_VBB[]	   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-	VS_START[]		=  VDL_VSS[]								&  ACP_VIDEO_ON
-					# ((0,VDL_VSS[12..1])		& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# (   VDL_VSS[]				&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
-	V_TOTAL[] 		=  VDL_VFT[]								&  ACP_VIDEO_ON
-					# (((0,VDL_VFT[12..1]) + 1)	& !VDL_VCT0)	& !ACP_VIDEO_ON 	 
-					# ((VDL_VFT[]		   + 1)	&  VDL_VCT0)	& !ACP_VIDEO_ON; 	 
--- ZÄHLER ---------------------------------------------------------------------------
-	LAST.CLK = PIXEL_CLK;
-	LAST = VHCNT[]==(H_TOTAL[] - 1);
-	VHCNT[].CLK = PIXEL_CLK;
-	VHCNT[] = (VHCNT[] + 1) & !LAST;
-	VVCNT[].CLK = PIXEL_CLK;
-	VVCNT[].ENA = LAST;
-	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]);
--- DISPLAY ON OFF
-	DPO_ZL.CLK = PIXEL_CLK;
-	DPO_ZL = (VVCNT[]>RAND_OBEN[]) & (VVCNT[]<RAND_UNTEN[]);		-- ON OFF
-	DPO_ON.CLK = PIXEL_CLK;
-	DPO_ON = VHCNT[]==RAND_LINKS[] - 1;									-- BESSER EINZELN WEGEN TIMING
-	DPO_OFF.CLK = PIXEL_CLK;
-	DPO_OFF = VHCNT[]==(RAND_RECHTS[] - 2);
-	DISP_ON.CLK = PIXEL_CLK;
-	DISP_ON = DISP_ON & !DPO_OFF 
-			# DPO_ON & DPO_ZL;
--- DATENTRANSFER ON OFF
-	VDO_ON.CLK = PIXEL_CLK;
-	VDO_ON = VHCNT[]==(HDIS_START[] - 2);								-- BESSER EINZELN WEGEN TIMING
-	VDO_OFF.CLK = PIXEL_CLK;
-	VDO_OFF = VHCNT[]==(HDIS_END[] - 1);
-	VDO_ZL.CLK = PIXEL_CLK;
-	VDO_ZL = (VVCNT[]>=(VDIS_START[])) & (VVCNT[]<=VDIS_END[]);		-- ON OFF
-	VDTRON.CLK = PIXEL_CLK;
-	VDTRON = VDTRON & !VDO_OFF
-		   # VDO_ON & VDO_ZL;
--- VERZÖGERUNG UND SYNC	
-	HSYNC_START.CLK = PIXEL_CLK;
-	HSYNC_START = VHCNT[]==HS_START[] - 2;
-	HSYNC_I[].CLK = PIXEL_CLK;
-	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
-			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
-	VSYNC_I[].CLK = PIXEL_CLK;
-	VSYNC_I[] = VVCNT[12..1]==VS_START[12..1];						-- VSYNC BEI VS_START 2 ZEILEN LANG		
-	VSYNC_I[].CLK = PIXEL_CLK;
-	VERZ[][].CLK = PIXEL_CLK;
-	VERZ[][1] = VERZ[][0];
-	VERZ[][2] = VERZ[][1];
-	VERZ[][3] = VERZ[][2];
-	VERZ[][4] = VERZ[][3];
-	VERZ[][5] = VERZ[][4];
-	VERZ[][6] = VERZ[][5];
-	VERZ[][7] = VERZ[][6];
-	VERZ[][8] = VERZ[][7];
-	VERZ[][9] = VERZ[][8];
-	VERZ[0][0] = DISP_ON;
-	VERZ[1][0] = !VDL_VCT6 & HSYNC_I[]!=0
-				# VDL_VCT6 & HSYNC_I[]==0;	
-	VERZ[2][0] = !VDL_VCT5 & VSYNC_I[]!=0
-				# VDL_VCT5 & VSYNC_I[]==0;	
-	nBLANK.CLK = PIXEL_CLK;
-	nBLANK =  VERZ[0][8];
-	HSYNC.CLK = PIXEL_CLK;
-	HSYNC  =  VERZ[1][9];
-	VSYNC.CLK = PIXEL_CLK;
-	VSYNC  =  VERZ[2][9];
-	nSYNC  = GND;
--- RANDFARBE MACHEN ------------------------------------
-	RAND[].CLK = PIXEL_CLK;
-	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
-	RAND[1] = RAND[0];
-	RAND[2] = RAND[1];
-	RAND[3] = RAND[2];
-	RAND[4] = RAND[3];
-	RAND[5] = RAND[4];
-	RAND[6] = RAND[5];
-	RAND_ON = RAND[6];
-----------------------------------------------------------
-	CLR_FIFO.CLK = PIXEL_CLK;
-	CLR_FIFO.ENA = LAST;
-	CLR_FIFO = VVCNT[]==(VDIS_END[] + 2);	-- FIFO  NACH ENDE ANZEIGE LÖSCHEN (GENUG FRÜH DAMIT ES GEFÜLLT WERDEN KANN BIS ZUR NEUEN ÜBERTRAGUNG) 
-	START_ZEILE.CLK = PIXEL_CLK;
-	START_ZEILE.ENA = LAST;
-	START_ZEILE = VVCNT[]==1;										-- ZEILE 1
-	SYNC_PIX.CLK = PIXEL_CLK;
-	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SYNC_PIX1.CLK = PIXEL_CLK;
-	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SYNC_PIX2.CLK = PIXEL_CLK;
-	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
-	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
-	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
-	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
-	FIFO_RDE.CLK = PIXEL_CLK;	
-	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
-			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
-			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
-			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
-			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
-			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
-			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
-	
-	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
-	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
-	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
-	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
-	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
-END;
diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak
deleted file mode 100644
index 3da6541..0000000
--- a/FPGA_by_Fredi/blitter.tdf.bak
+++ /dev/null
@@ -1,700 +0,0 @@
--- WARNING: Do NOT edit the input and output ports in this file in a text
--- editor if you plan to continue editing the block that represents it in
--- the Block Editor! File corruption is VERY likely to occur.
-
--- Copyright (C) 1991-2010 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
-
--- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
--- Created on Sat Jan 15 11:06:17 2011
-INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
-INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
-INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
-INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
-
-
---CONSTANT	BL_SKEW_LF = 255;
-
---  Title Statement (optional)
-TITLE "Blitter";
-
-
---  Parameters Statement (optional)
-
--- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
--- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
-
-
---  Subdesign Section
-
-SUBDESIGN BLITTER
-(
-	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
-	nRSTO : INPUT;
-	MAIN_CLK : INPUT;
-	FB_ALE : INPUT;
-	nFB_WR : INPUT;
-	nFB_OE : INPUT;
-	FB_SIZE0 : INPUT;
-	FB_SIZE1 : INPUT;
-	VIDEO_RAM_CTR[15..0] : INPUT;
-	BLITTER_ON : INPUT;
-	FB_ADR[31..0] : INPUT;
-	nFB_CS1 : INPUT;
-	nFB_CS2 : INPUT;
-	nFB_CS3 : INPUT;
-	DDRCLK0 : INPUT;
-	VDP_IN[63..0] : INPUT;
-	BLITTER_DACK[4..0] : INPUT;
-	SR_BLITTER_DACK : INPUT;
-	BLITTER_RUN : OUTPUT;
-	BLITTER_INT : OUTPUT;
-	BLITTER_DOUT[127..0] : OUTPUT;
-	BLITTER_ADR[31..0] : OUTPUT;
-	BLITTER_SIG : OUTPUT;
-	BLITTER_WR : OUTPUT;
-	BLITTER_TA : OUTPUT;
-	FB_AD[31..0] : BIDIR;
-	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
-)
-
-VARIABLE
-	BYT							:NODE;
-	FB_16B[1..0]				:NODE;
-	BLITTER_CS					:NODE;
-	BL_HRAM_CS 					:NODE;
-	DP_RAM_CS					:NODE;
-	BL_HRAM_BE[1..0]			:NODE;
-	BL_HRAM_OUT[15..0]			:NODE;
-	BL_DPRAM_OUT[15..0]			:NODE;
-	BL_SRC_X_INC_CS				:NODE;
-	BL_SRC_X_INC[15..0]			:DFFE;
-	SRC_ADR_INC[31..0]			:NODE;
-	SRC_XINC32[31..0]			:NODE;
-	BL_SRC_Y_INC_CS				:NODE;
-	BL_SRC_Y_INC[15..0]			:DFFE;
-	SRC_YINC32[31..0]			:NODE;
-	BL_ENDMASK1_CS				:NODE;
-	BL_ENDMASK1[15..0]			:DFFE;
-	BL_ENDMASK2_CS				:NODE;
-	BL_ENDMASK2[15..0]			:DFFE;
-	BL_ENDMASK3_CS				:NODE;
-	BL_ENDMASK3[15..0]			:DFFE;
-	BL_ENDMASK0[15..0]			:NODE;
-	BL_ENDMASKF[15..0]			:NODE;
-	BL_ENDMASKL[15..0]			:NODE;
-	BL_ENDMASKR[15..0]			:NODE;
-	BL_SRC_ADRH_CS				:NODE;
-	BL_SRC_ADRL_CS				:NODE;
-	BL_SRC_ADR[31..0]			:DFFE;
-	SRC_OLD[27..0]				:DFFE;
-	SRC_IADRH_CS				:NODE;
-	SRC_IADRL_CS				:NODE;
-	SRC_IADR[31..0]				:DFF;
-	SRC_IADR_CLR				:DFF;
-	SRC_ADR32[31..0]			:NODE;
-	BL_DST_X_INC_CS				:NODE;
-	BL_DST_X_INC[15..0]			:DFFE;
-	DST_ADR_INC[31..0]			:NODE;
-	DST_XINC32[31..0]			:NODE;
-	BL_DST_Y_INC_CS				:NODE;
-	BL_DST_Y_INC[15..0]			:DFFE;
-	DST_YINC32[31..0]			:NODE;
-	BL_DST_ADRH_CS				:NODE;
-	BL_DST_ADRL_CS				:NODE;
-	BL_DST_ADR[31..0]			:DFFE;
-	DST_IADRH_CS				:NODE;
-	DST_IADRL_CS				:NODE;
-	DST_IADR[31..0]				:DFF;
-	DST_IADR_CLR				:DFF;
-	DST_ADR32[31..0]			:NODE;
-	BL_X_CNT_CS					:NODE;
-	BL_X_CNT[15..0]				:DFFE;
-	X_CNT16[15..0]				:NODE;
-	BL_Y_CNT_CS					:NODE;
-	BL_Y_CNT[15..0]				:DFFE;
-	BL_HOP_CS					:NODE;
-	BL_HOP[7..0]				:DFFE;
-	BL_OP[7..0]					:DFFE;
-	BL_LN_CS					:NODE;
-	BL_LN_WR					:NODE;
-	LN7_CLR						:NODE;
-	BL_LN[7..0]					:DFFE;
-	BL_SKEW[7..0]				:DFFE;
--- barell shifter
-	DIST_RIGHT[8..0]			:NODE;
-	BS_SKEW[7..0]				:NODE;
-	BL_BSIN[383..0]				:NODE;
-	BL_BSOUT[383..0]			:NODE;
-	SHIFT_DIR					:NODE;
-	BL_SRC_BUF1[127..0]			:DFFE;
-	BL_SRC_BUF2[127..0]			:DFFE;
-	BL_SRC_BUF3[127..0]			:DFFE;
-	BL_DST_BUFRD[127..0]		:DFFE;	
-	BL_READ_DST					:NODE;				-- LATCH SIGNAL DST BUF RD
-	BL_READ_SRC					:NODE;				-- LATCH SIGNAL SRC BUF
-	SRC_READ					:NODE;				-- FREIGABE LATCH SIGNAL
-	NOT_DST_READ				:NODE;
-	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
-	X_INDEX_CS					:NODE;
-	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
-	X_INDEX_CLR					:DFF;				-- X INDEX LÖSCHEN CPU WRITE
-	X_INDEX_CLR_DIR				:NODE;				-- X INDEX LÖSCHEN STATE MACHINE
-	DST_X_INC[15..0]			:NODE;				-- ANZAHL WORTE PRO DURCHLAUF
-	X_CNT_T[15..0]				:NODE;
-	Y_INDEX_CS					:NODE;
-	Y_INDEX[15..0]				:DFF;				-- LAUFZEIGER Y COUNT
-	Y_INDEX_CLR					:DFF;
-	LINE_NR[3..0]				:NODE;
-	SDXINC						:DFF;				-- INC INDEX SPALTE
-	YIINC						:NODE;				-- INC INDEX ZEILE
-	ZAINC						:NODE;				-- INC ADRESSEN ZEILENUMBRUCH
-	HOP_OUT[127..0]				:NODE;
-	OP_OUT[127..0]				:NODE;
-	ENDMASK1_SHIFT[7..0]		:NODE;
-	ENDMASK2_SHIFT[7..0]		:NODE;
-	ENDMASK12_IN[143..0]		:NODE;
-	ENDMASK12_OUT[143..0]		:NODE;
-	ENDMASK23_IN[143..0]		:NODE;
-	ENDMASK23_OUT[143..0]		:NODE;
-	ENDMASKM_IN[127..0]			:NODE;
-	ENDMASKM_OUT[127..0]		:NODE;
-	ROR_CNT[8..0]				:NODE;
-	ENDMASK123[127..0]			:DFF;
-	ENDMASKEND[31..0]			:NODE;
-	BLITTER_SIG					:DFF;
-	BLITTER_REQ					:NODE;
-	BL_START					:DFF;
-	BL_NOTRUN					:NODE;
-	
--- MAIN STATE MACHINE
-	BL_SM						:MACHINE WITH STATES(START,NEW_LINE,RDSRC3,RDSRC2,RDSRC1,RDDST,WRDSTW,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG);	
-	
-BEGIN
--- BYT UND WORD SELECT 16 BIT
-	BYT      = !FB_SIZE1 &  FB_SIZE0;
-	FB_16B0 = FB_ADR[0]==0;										-- wenn ADR==0
-	FB_16B1 = FB_ADR[0]==1 # !BYT;								-- wenn ADR==1 or NOT BYT
--- BLITTER CS
-	BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14";				-- FFFF8A00-7F  
-	BLITTER_TA = BLITTER_CS;
--- REGISTER
-	-- HALFTON RAM 
-	BL_HRAM_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C50";						-- $F8A00-1F.w
-	BL_HRAM_BE1 = BL_HRAM_CS & FB_16B0;
-	BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1;
-	WREN_B = B"0";
-	LINE_NR[] = BL_LN[3..0] + ((Y_INDEX[3..0] & !BL_DST_X_INC15) - (Y_INDEX[3..0] & BL_DST_X_INC15));
-	(BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B);
-	DP_RAM_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C528";							-- $F8A50.w
-	-- SRC X INC
-	BL_SRC_X_INC[].CLK = MAIN_CLK;
-	BL_SRC_X_INC[15..1] = FB_AD[31..17];
-	BL_SRC_X_INC0 = GND;
-	BL_SRC_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C510");						-- $F8A20.w
-	BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_X_INC[7..0].ENA  = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
-	SRC_XINC32[15..0]  = BL_SRC_X_INC[];											-- ERWEITERN AUF 32 BIT
-	SRC_XINC32[31..16] = H"FFFF" & BL_SRC_X_INC15;									-- ERWEITERN AUF 32 BIT
-	-- SRC Y INC
-	BL_SRC_Y_INC[].CLK = MAIN_CLK;
-	BL_SRC_Y_INC[15..1] = FB_AD[31..17];
-	BL_SRC_Y_INC0 = GND;
-	BL_SRC_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C511");						-- $F8A22.w
-	BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_SRC_Y_INC[7..0].ENA  = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
-	SRC_YINC32[15..0]  = BL_SRC_Y_INC[];											-- ERWEITERN AUF 32 BIT
-	SRC_YINC32[31..16] = H"FFFF" & BL_SRC_Y_INC15;									-- ERWEITERN AUF 32 BIT
-	-- SRC ADR HIGH
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[31..16] = FB_AD[31..16];
-	BL_SRC_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C512");						-- $F8A24.w
-	BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
-	-- SRC ADR LOW
-	BL_SRC_ADR[].CLK = MAIN_CLK;
-	BL_SRC_ADR[15..1] = FB_AD[31..17];
-	BL_SRC_ADR0 = GND;
-	BL_SRC_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C513");						-- $F8A26.w
-	BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_SRC_ADR[7..0].ENA  = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
-	SRC_IADR[].CLK = DDRCLK0;
-	SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520");							-- $F8A40.w
-	SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521");							-- $F8A42.w
-	SRC_IADR_CLR.CLK = MAIN_CLK;
-	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
-	SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
-	SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH 
-	-- ENDMASK 1
-	BL_ENDMASK1[].CLK = MAIN_CLK;
-	BL_ENDMASK1[] = FB_AD[31..16];
-	BL_ENDMASK1_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C514");						-- $F8A28.w
-	BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK1[7..0].ENA  = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 2
-	BL_ENDMASK2[].CLK = MAIN_CLK;
-	BL_ENDMASK2[] = FB_AD[31..16];
-	BL_ENDMASK2_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C515");						-- $F8A2A.w
-	BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK2[7..0].ENA  = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
-	-- ENDMASK 3
-	BL_ENDMASK3[].CLK = MAIN_CLK;
-	BL_ENDMASK3[] = FB_AD[31..16];
-	BL_ENDMASK3_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C516");						-- $F8A2C.w
-	BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
-	BL_ENDMASK3[7..0].ENA  = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
-	-- DST X INC
-	BL_DST_X_INC[].CLK = MAIN_CLK;
-	BL_DST_X_INC[15..1] = FB_AD[31..17];
-	BL_DST_X_INC0 = GND;
-	BL_DST_X_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C517");						-- $F8A2E.w
-	BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_X_INC[7..0].ENA  = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
-	DST_XINC32[15..0]  = BL_DST_X_INC[];											-- ERWEITERN AUF 32 BIT
-	DST_XINC32[31..16] = H"FFFF" & BL_DST_X_INC15;									-- ERWEITERN AUF 32 BIT
-	-- DST Y INC
-	BL_DST_Y_INC[].CLK = MAIN_CLK;
-	BL_DST_Y_INC[15..1] = FB_AD[31..17];
-	BL_DST_Y_INC0 = GND;
-	BL_DST_Y_INC_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C518");						-- $F8A30.w
-	BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
-	BL_DST_Y_INC[7..0].ENA  = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
-	DST_YINC32[15..0]  = BL_DST_Y_INC[];											-- ERWEITERN AUF 32 BIT
-	DST_YINC32[31..16] = H"FFFF" & BL_DST_Y_INC15;									-- ERWEITERN AUF 32 BIT
-	-- DST ADR HIGH
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[31..16] = FB_AD[31..16];
-	BL_DST_ADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C519");						-- $F8A32.w
-	BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
-	-- DST ADR LOW
-	BL_DST_ADR[].CLK = MAIN_CLK;
-	BL_DST_ADR[15..1] = FB_AD[31..17];
-	BL_DST_ADR0 = GND;
-	BL_DST_ADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51A");						-- $F8A34.w
-	BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
-	BL_DST_ADR[7..0].ENA  = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
-	DST_IADR[].CLK = DDRCLK0;
-	DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522");							-- $F8A44.w
-	DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523");							-- $F8A46.w
-	DST_IADR_CLR.CLK = MAIN_CLK;					
-	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;					-- LÖSCHEN BEI WRITE
-	DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
-	DST_ADR32[] = BL_DST_ADR[] + DST_IADR[];									-- ZUGRIFFSADRESSE THEORETISCH
-	-- X COUNT
-	BL_X_CNT[].CLK = MAIN_CLK;
-	BL_X_CNT[] = FB_AD[31..16];
-	BL_X_CNT_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51B");							-- $F8A36.w
-	BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
-	BL_X_CNT[7..0].ENA  = BL_X_CNT_CS & !nFB_WR & FB_16B1;
-	X_INDEX[].CLK = DDRCLK0;
-	X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524");							-- $F8A48.w
-	X_INDEX_CLR.CLK = MAIN_CLK;
-	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
-	X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
-	X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0));		-- EFFEKTIV geschrieben
--- SCHRITTWEITEN BEI PALLETTENMOD
-	IF (BL_SRC_X_INC[] != BL_DST_X_INC[]) # (BL_X_CNT[] < 8) THEN 
-		DST_X_INC[] = 1;
-		X_CNT_T[] = 0;
-		SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
-		DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
-	ELSE		
-		IF BL_SRC_X_INC[] == H"0002" THEN 
-			DST_X_INC[] = 8;
-			X_CNT_T[] = (0,DST_ADR32[3..1]);
-			SRC_ADR_INC[] = 16;						-- SRC X INC
-			DST_ADR_INC[] = 16;						-- DST X INC
-		ELSE
-			IF BL_SRC_X_INC[] == H"FFFE" THEN 
-				DST_X_INC[] = 8;
-				X_CNT_T[] = 7 - (0,DST_ADR32[3..1]);
-				SRC_ADR_INC[] = -16;				-- SRC X INC
-				DST_ADR_INC[] = -16;				-- DST X INC
-			ELSE							
-				IF BL_SRC_X_INC[] == H"0004" THEN 
-					DST_X_INC[] = 4;
-					X_CNT_T[] = (0,DST_ADR32[3..2]);
-					SRC_ADR_INC[] = 16;						-- SRC X INC
-					DST_ADR_INC[] = 16;						-- DST X INC
-				ELSE
-					IF BL_SRC_X_INC[] == H"FFFC" THEN 
-						DST_X_INC[] = 4;
-						X_CNT_T[] = 3 - (0,DST_ADR32[3..2]);
-						SRC_ADR_INC[] = -16;				-- SRC X INC
-						DST_ADR_INC[] = -16;				-- DST X INC
-					ELSE							
-						IF BL_SRC_X_INC[] == H"0008" THEN 
-							DST_X_INC[] = 2;
-							X_CNT_T[] = (0,DST_ADR32[3]);
-							SRC_ADR_INC[] = 16;						-- SRC X INC
-							DST_ADR_INC[] = 16;						-- DST X INC
-						ELSE
-							IF BL_SRC_X_INC[] == H"FFF8" THEN 
-								DST_X_INC[] = 2;
-								X_CNT_T[] = 1 - (0,DST_ADR32[3]);
-								SRC_ADR_INC[] = -16;				-- SRC X INC
-								DST_ADR_INC[] = -16;				-- DST X INC
-							ELSE							
-								DST_X_INC[] = 1;
-								X_CNT_T[] = 0;
-								SRC_ADR_INC[] = SRC_XINC32[];		-- SRC X INC
-								DST_ADR_INC[] = DST_XINC32[];		-- DST X INC
-							END IF;
-						END IF;
-					END IF;
-				END IF;
-			END IF;
-		END IF;
-	END IF;
-	-- Y COUNT
-	BL_Y_CNT[].CLK = MAIN_CLK;
-	BL_Y_CNT[] = FB_AD[31..16];
-	BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C";							-- $F8A38.w
-	BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
-	BL_Y_CNT[7..0].ENA  = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
-	Y_INDEX[].CLK = DDRCLK0;
-	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";							-- $F8A4A.w
-	Y_INDEX_CLR.CLK = MAIN_CLK;
-	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
-	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
-	-- HOP LOGIC
-	BL_HOP[].CLK = MAIN_CLK;
-	BL_HOP[] = FB_AD[31..24];
-	BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D";								-- $F8A3A.w
-	BL_HOP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B0;							-- $F8A3A
-	-- OP LOGIC
-	BL_OP[].CLK = MAIN_CLK;
-	BL_OP[] = FB_AD[23..16];
-	BL_OP[7..0].ENA  = BL_HOP_CS & !nFB_WR & FB_16B1;							-- $F8A3B
-	-- LINE NUMBER BYT
-	BL_LN[].CLK = MAIN_CLK;
-	BL_LN_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C51E");							-- $F8A3C.w
-	BL_LN_WR = BL_LN_CS & !nFB_WR & FB_16B0;									-- $F8A3C WRITE SIGNAL
-	BL_LN[6..0] = FB_AD[30..24];												-- HOG UND SMUDGE
-	BL_LN[6..0].ENA  = BL_LN_WR;													-- $F8A3C
-	BL_LN7.ENA  = BL_LN_WR # LN7_CLR;													-- $F8A3C
-	BL_LN7 = FB_AD31 & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; -- BUSY 
-	BL_START.CLK = MAIN_CLK;
-	BL_START = BL_LN7 & !BL_LN_CS & BLITTER_ON & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) & !LN7_CLR; 
-	-- SKEW BYT
-	BL_SKEW[].CLK = MAIN_CLK;
-	BL_SKEW[] = FB_AD[23..16];
-	BL_SKEW[].ENA  = BL_LN_CS & !nFB_WR & FB_16B1;								-- $F8A3D
---- REGISTER OUT
-	FB_AD[31..16] = lpm_bustri_WORD(
-						BL_HRAM_CS	    & BL_DPRAM_OUT[]
-					  # BL_SRC_X_INC_CS & BL_SRC_X_INC[]
-					  # BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
-					  # BL_SRC_ADRH_CS  & SRC_ADR32[31..16]
-					  # BL_SRC_ADRL_CS  & SRC_ADR32[15..0]
-					  # BL_ENDMASK1_CS  & BL_ENDMASK1[]
-					  # BL_ENDMASK2_CS  & BL_ENDMASK2[]
-					  # BL_ENDMASK3_CS  & BL_ENDMASK3[]
-					  # BL_DST_X_INC_CS & BL_DST_X_INC[]
-					  # BL_DST_Y_INC_CS & BL_DST_Y_INC[]
-					  # BL_DST_ADRH_CS  & DST_ADR32[31..16]
-					  # BL_DST_ADRL_CS  & DST_ADR32[15..0]
-					  # BL_X_CNT_CS 	& (BL_X_CNT[]-X_INDEX[])
-					  # BL_Y_CNT_CS 	& (BL_Y_CNT[]-Y_INDEX[])
-					  # BL_HOP_CS 		& (BL_HOP[],BL_OP[])
-					  # BL_LN_CS 		& (BL_LN7 # !BL_NOTRUN,BL_LN[6..0],BL_SKEW[])		
-					  # SRC_IADRH_CS	& SRC_IADR[31..16]
-					  # SRC_IADRL_CS	& SRC_IADR[15..0]
-					  # DST_IADRH_CS	& DST_IADR[31..16]
-					  # DST_IADRL_CS	& DST_IADR[15..0]
-					  # X_INDEX_CS		& X_INDEX[]
-					  # Y_INDEX_CS		& Y_INDEX[]
-					  # DP_RAM_CS		& BL_HRAM_OUT[]
-					  ,BLITTER_CS & !nFB_OE); 									-- FFFF8A00-7F
---------------------------------------------------------------------------------------
--- SRC BUFFER LADEN
-	BL_SRC_BUF1[].CLK = DDRCLK0;
-	BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
-	BL_SRC_BUF1[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
-	BL_SRC_BUF1[] = (VDP_IN[],VDP_IN[]);
-	BL_SRC_BUF2[].CLK = DDRCLK0;
-	BL_SRC_BUF2[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
-	BL_SRC_BUF2[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
-	BL_SRC_BUF2[] = BL_SRC_BUF1[];
-	BL_SRC_BUF3[].CLK = DDRCLK0;
-	BL_SRC_BUF3[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC;
-	BL_SRC_BUF3[63..0].ENA   = BLITTER_DACK0 & BL_READ_SRC;
-	BL_SRC_BUF3[] = BL_SRC_BUF2[];
-	-- ZUORDNUNG ---------------------------------------------------
-	IF BL_SRC_X_INC15 THEN		-- WENN NEGATIV -> REIHENFOLGE KEHREN
-		BL_BSIN[127..0]   = BL_SRC_BUF3[];
-		BL_BSIN[255..128] = BL_SRC_BUF2[];
-		BL_BSIN[383..256] = BL_SRC_BUF1[];
-	ELSE						-- SONST NORMAL BEI VORWÄRTS
-		BL_BSIN[127..0]   = BL_SRC_BUF1[];
-		BL_BSIN[255..128] = BL_SRC_BUF2[];
-		BL_BSIN[383..256] = BL_SRC_BUF3[];
-	END IF;
--- DST BUFFER READ	
-	BL_DST_BUFRD[].CLK = DDRCLK0;
-	BL_DST_BUFRD[127..64].ENA = BLITTER_DACK1 & BL_READ_DST;
-	BL_DST_BUFRD[63..0].ENA   = BLITTER_DACK0 & BL_READ_DST;
-	BL_DST_BUFRD[] = (VDP_IN[],VDP_IN[]);
--- barell shift *****************************************************************************
--- SOURCE SHIFT RIGHT = LPM_CSHIFT RIGTH ;SKEW SHIFT: IF FXRS==0 THEN RIGHT ELSE LEFT
-	DIST_RIGHT[] = (16 * ((0,DST_ADR32[3..1]) - (0,SRC_ADR32[3..1]))) + (!BL_SKEW7 &  (0,BL_SKEW[3..0])) - (BL_SKEW7 & (0,BL_SKEW[3..0]));
-	IF DIST_RIGHT8 THEN 		
-		BS_SKEW[] = 0 - DIST_RIGHT[7..0]; 					-- LPM SHIFT LEFT
-		SHIFT_DIR = GND;									-- DIR = LEFT
-	else													
-		BS_SKEW[] = DIST_RIGHT[7..0]; 						-- LPM SHIFT RIGHT
-		SHIFT_DIR = VCC;									-- DIR = RIGHT
-	end if;
--- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert!
-	BL_BSOUT[] = lpm_clshift384(BL_BSIN[], SHIFT_DIR , BS_SKEW[]);	-- wir brauchen 128bit
--- HOP ***************************************************************************************
-	CASE BL_HOP[1..0] IS
-		WHEN H"0" =>
-					--    12345678901234567890123456789012
-			HOP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-		WHEN H"1" =>
-			HOP_OUT[] = (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]);
-		WHEN H"2" =>
-			HOP_OUT[] = BL_BSOUT[255..128];
-		WHEN OTHERS =>
-			HOP_OUT[] = (BL_BSOUT[255..128] & (BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[],BL_HRAM_OUT[]));
-	END CASE;
--- OP *****************************************************************************************
-	CASE BL_OP[3..0] IS
-		WHEN H"0" =>
-			OP_OUT[] = H"0";
-			SRC_READ = B"0";
-		WHEN H"1" =>
-			OP_OUT[] = HOP_OUT[] AND BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"2" =>
-			OP_OUT[] = HOP_OUT[] AND !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"3" =>
-			OP_OUT[] = HOP_OUT[];
-			SRC_READ = BL_HOP1;
-		WHEN H"4" =>
-			OP_OUT[] = !HOP_OUT[] AND BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"5" =>
-			OP_OUT[] = BL_DST_BUFRD[];
-			SRC_READ = B"0";
-		WHEN H"6" =>
-			OP_OUT[] = HOP_OUT[] XOR BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"7" =>
-			OP_OUT[] = HOP_OUT[] OR BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"8" =>
-			OP_OUT[] = !HOP_OUT[] AND !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"9" =>
-			OP_OUT[] = !HOP_OUT[] XOR BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"A" =>
-			OP_OUT[] = !BL_DST_BUFRD[];
-			SRC_READ = B"0";
-		WHEN H"B" =>
-			OP_OUT[] = HOP_OUT[] OR !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"C" =>
-			OP_OUT[] = !HOP_OUT[];
-			SRC_READ = BL_HOP1;
-		WHEN H"D" =>
-			OP_OUT[] = !HOP_OUT[] OR BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN H"E" =>
-			OP_OUT[] = !HOP_OUT[] OR !BL_DST_BUFRD[];
-			SRC_READ = BL_HOP1;
-		WHEN OTHERS =>
-					--   12345678901234567890123456789012
-			OP_OUT[] = H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-			SRC_READ = B"0";
-	END CASE;
------------- ENDMASKEN SETZEN ******************************************************************************																							 
-			ENDMASK1_SHIFT[3..0] = 0; 						
-			ENDMASK2_SHIFT[3..0] = 0; 
-			ENDMASKEND[] =  DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];					
-			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
-				IF X_INDEX[] == 0 THEN															-- ENDE?	
-					ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1]));							-- JA ENDMASK 3 SETZEN 
-				ELSE					
-					ENDMASK2_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
-				END IF;	 
-				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1]));							-- JA -> ENDMASK 1 SETZEN 
-				ELSE					
-					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
-				END IF;
-			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV (immer bei memcopy)
-				IF X_INDEX[] == 0 THEN															-- ANFANG?	
-					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); 							-- JA -> ENDMASK 1 SETZEN 
-				ELSE		
-					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN->ENDMASK1  AUF ENDMASK2 SETZEN 
-				END IF;		
-				IF (X_CNT16[] + DST_X_INC[]) >= BL_X_CNT[] THEN									-- SCHON ZEILENENDE?	
-					ENDMASK2_SHIFT[7..4] = 8 - (0,(ENDMASKEND[3..1]));							-- JA: ENDMASK 3 SETZEN
-				ELSE					
-					ENDMASK2_SHIFT[7..4] = 0;													-- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN 
-				END IF;	 
-			END IF;
--- ENDMASKEN -- barell shifter 144 bit, direction 0 = links 1 = rechts
-		BL_ENDMASK0[] = 0;
-		BL_ENDMASKF[] = -1;
-		BL_ENDMASKL[] = BL_ENDMASK1[] & !BL_DST_X_INC15 # BL_ENDMASK3[] & BL_DST_X_INC15;
-		BL_ENDMASKR[] = BL_ENDMASK3[] & !BL_DST_X_INC15 # BL_ENDMASK1[] & BL_DST_X_INC15;
-	CASE DST_X_INC[] IS
-		WHEN 8 => 	-- INC 2
-			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
-			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[],BL_ENDMASKF[]);
-			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
-		WHEN 4 =>	-- INC 4
-			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
-			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[]);
-			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
-		WHEN 2 =>	-- INC 8
-			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
-			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
-			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
-		WHEN OTHERS =>
-			ENDMASK12_IN[] = (BL_ENDMASKL[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[]);
-			ENDMASKM_IN[]  =               (BL_ENDMASKF[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[],BL_ENDMASK0[]);
-			ENDMASK23_IN[] =               (BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASK2[],BL_ENDMASKR[]);
-	END CASE;
-	ENDMASK12_OUT[] = lpm_clshift144(ENDMASK12_IN[],1,ENDMASK1_SHIFT[]);			-- IMMER rechts SCHIEBEN
-	ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]);			-- IMMER LINKS SCHIEBEN	
-	ROR_CNT[] = 16 * (0,DST_ADR32[3..1]);
-	ENDMASKM_OUT[] = lpm_ror128(ENDMASKM_IN[],ROR_CNT[6..0]);
-	ENDMASK123[].CLK = DDRCLK0;
-	ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16] & ENDMASKM_OUT[];
-	BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[]));
-	NOT_DST_READ = ((BL_OP[3..0] == H"0") # (BL_OP[3..0] == H"3") # (BL_OP[3..0] == H"C") # (BL_OP[3..0] == H"F")) & (ENDMASK123[] == H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");
--- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 	
-	BLITTER_RUN = BLITTER_ON;										-- BLITTER IST DA!
-	BLITTER_ADR[3..0] = H"0";										-- IMMER LINE
-	BLITTER_SIG.CLK = DDRCLK0;
-	BLITTER_SIG = BLITTER_REQ & !BLITTER_DACK0 & !BLITTER_DACK1;
--- BLITTER MAIN STATE MACHINE  -----------------------------------------------
-	BL_SM.CLK = DDRCLK0;
-	SRC_OLD[].CLK = DDRCLK0;
-	SRC_OLD[] = SRC_ADR32[31..4];
-	SDXINC.CLK = DDRCLK0;
-	CASE BL_SM IS
-		WHEN START =>   ------------------------- START
-			BL_NOTRUN = VCC;			-- BLITTER NOT RUN
-			IF BLITTER_ON & BL_START & (BL_X_CNT[] > X_CNT16[]) & (BL_Y_CNT[] > Y_INDEX[]) THEN	-- STARTEN?
-				BL_SM = NEW_LINE;									-- JA START
-			ELSE
-				BL_SM = START;										-- NICHT STARTEN
-			END IF;
-		WHEN NEW_LINE => ----------------------- NEU LINIE
-			X_INDEX_CLR_DIR = VCC;									-- JA -> X INDEX LÖSCHEN FÜR START LINE 			
-			IF SRC_READ THEN										-- SOURCE READ NÖTIG?
-				BL_SM = RDSRC3;										-- JA							
-			ELSE
-				BL_SM = RDDST;										-- NEIN -> DIREKT ZU READ DEST
-			END IF;
-		WHEN RDSRC3 =>  ------------------------ READ SRC3
-			BLITTER_ADR[31..4] = SRC_ADR32[31..4] - 1 + (2 & BL_SRC_X_INC15);
-			BLITTER_REQ = VCC;
-			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
-			IF BLITTER_DACK0 THEN
-				BL_SM = RDSRC2;
-			ELSE	
-				BL_SM = RDSRC3;
-			END IF;
-		WHEN RDSRC2 =>  ------------------------- READ SRC2
-			BLITTER_ADR[31..4] = SRC_ADR32[31..4];
-			BLITTER_REQ = VCC;
-			BL_READ_SRC = VCC;									-- LATCH UND SB1->SB2
-			IF BLITTER_DACK0 THEN
-				BL_SM = RDSRC1;
-			ELSE	
-				BL_SM = RDSRC2;
-			END IF;
-		WHEN RDSRC1 =>	------------------------ READ SRC1
-			BLITTER_ADR[31..4] = SRC_ADR32[31..4] + 1 - (2 & BL_SRC_X_INC15);
-			BLITTER_REQ = VCC;
-			BL_READ_SRC = VCC;								-- LATCH UND SB1->SB2
-			SRC_OLD[].ENA = VCC;
-			IF BLITTER_DACK0 THEN
-				BL_SM = RDDST;
-			ELSE	
-				BL_SM = RDSRC1;
-			END IF;
-		WHEN RDDST =>	------------------------ READ DEST
-			BLITTER_ADR[31..4] = DST_ADR32[31..4];
-			IF NOT_DST_READ THEN
-				BL_SM = WRDSTW;
-			ELSE
-				BLITTER_REQ = VCC;
-				BL_READ_DST = VCC;
-				IF BLITTER_DACK0 THEN
-					BL_SM = WRDSTW;
-				ELSE	
-					BL_SM = RDDST;
-				END IF;
-			END IF;
-		WHEN WRDSTW =>	 ------------------------ KURZ WARTEN AUF ERGEBNIS
-			BLITTER_ADR[31..4] = DST_ADR32[31..4];
-			BL_SM = WRDST;
-		WHEN WRDST =>	------------------------- WRITE DEST
-			BLITTER_ADR[31..4] = DST_ADR32[31..4];
-			BLITTER_WR = VCC;
-			BLITTER_REQ = VCC;
-			SDXINC = BLITTER_DACK2;									-- INCCREMENT SRC, DST, X_INDEX
-			IF BLITTER_DACK0 THEN
-				BL_SM = TESTZEILENENDE;
-			ELSE	
-				BL_SM = WRDST;
-			END IF;
-		WHEN TESTZEILENENDE =>	----------------- ZEILENDE?
-			IF X_CNT16[] >= BL_X_CNT[] THEN							-- SCHON ZEILENENDE? 	
-				YIINC = VCC;										-- JA -> INC Y-INDEX
-				BL_SM = TESTFERTIG;									-- => TEST OB FERTIG
-			ELSE
-				IF !SRC_READ THEN									-- KEIN SOURCE READ?
-					BL_SM = RDDST;									-- JA => LESEN UNNÖTIG ->
-				ELSE
-					IF SRC_ADR32[31..4] == SRC_OLD[] THEN			-- ADRESSE IMMER NOCH IN DER LINE?
-						BL_SM = RDDST;								-- DATEN SIND GÜLTIG -> READ DEST
-					ELSE
-						BL_SM = RDSRC1;								-- SONST NEXT SRC
-					END IF;
-				END IF;
-			END IF;	
-		WHEN TESTFERTIG =>	--------------------- TEST AUF FERTIG
-			ZAINC = VCC;											-- ZEILENENDE: INC SRC UND DST ADRESSEN 
-			IF Y_INDEX[] >= BL_Y_CNT[] THEN							-- LETZTE ZEILE?
-				BL_SM = FERTIG;										-- JA => FERTIG
-			ELSE
-				BL_SM = NEW_LINE;									-- NEIN => NEXT LINE
-			END IF;
-		WHEN FERTIG => -------------------------- FERTIG
-			BL_NOTRUN = VCC;										-- BLITTER NOT RUN
-			BLITTER_INT = VCC;										-- BLITTER INTERRUPT
-			LN7_CLR = VCC;											-- BUSY BIT LÖSCHEN
-			IF (BL_LN7 == 0) & (BL_START == 0) THEN			-- WARTEN BIS GELÖSCHT (SYNC MIT 33MHz)
-				BL_SM = START;	
-			ELSE
-				BL_SM = FERTIG;
-			END IF;
-		WHEN OTHERS =>
-			BL_SM = FERTIG;
-	END CASE;
-END;
-
diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary
deleted file mode 100644
index f142f9b..0000000
--- a/FPGA_by_Fredi/firebee1.fit.summary
+++ /dev/null
@@ -1,16 +0,0 @@
-Fitter Status : Successful - Thu Jun 22 14:20:25 2017
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Device : EP3C40F484C6
-Timing Models : Final
-Total logic elements : 20,227 / 39,600 ( 51 % )
-    Total combinational functions : 18,217 / 39,600 ( 46 % )
-    Dedicated logic registers : 5,767 / 39,600 ( 15 % )
-Total registers : 5906
-Total pins : 296 / 332 ( 89 % )
-Total virtual pins : 0
-Total memory bits : 355,360 / 1,161,216 ( 31 % )
-Embedded Multiplier 9-bit elements : 20 / 252 ( 8 % )
-Total PLLs : 4 / 4 ( 100 % )
diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary
deleted file mode 100644
index 286e23f..0000000
--- a/FPGA_by_Fredi/firebee1.map.summary
+++ /dev/null
@@ -1,14 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Jun 22 14:14:13 2017
-Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-Revision Name : firebee1
-Top-level Entity Name : firebee1
-Family : Cyclone III
-Total logic elements : 21,573
-    Total combinational functions : 18,134
-    Dedicated logic registers : 5,773
-Total registers : 5901
-Total pins : 296
-Total virtual pins : 0
-Total memory bits : 355,360
-Embedded Multiplier 9-bit elements : 20
-Total PLLs : 4
diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary
deleted file mode 100644
index 75fecaf..0000000
--- a/FPGA_by_Fredi/firebee1.tan.summary
+++ /dev/null
@@ -1,276 +0,0 @@
---------------------------------------------------------------------------------------
-Timing Analyzer Summary
---------------------------------------------------------------------------------------
-
-Type           : Worst-case tsu
-Slack          : -10.868 ns
-Required Time  : 1.000 ns
-Actual Time    : 11.868 ns
-From           : FB_SIZE0
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 9538
-
-Type           : Worst-case tco
-Slack          : -96.119 ns
-Required Time  : 1.000 ns
-Actual Time    : 97.119 ns
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
-To             : FB_AD[16]
-From Clock     : MAIN_CLK
-To Clock       : --
-Failed Paths   : 8562
-
-Type           : Worst-case tpd
-Slack          : -13.155 ns
-Required Time  : 1.000 ns
-Actual Time    : 14.155 ns
-From           : nFB_CS2
-To             : FB_AD[27]
-From Clock     : --
-To Clock       : --
-Failed Paths   : 550
-
-Type           : Worst-case th
-Slack          : -0.274 ns
-Required Time  : 1.000 ns
-Actual Time    : 1.274 ns
-From           : VD[18]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]
-From Clock     : --
-To Clock       : MAIN_CLK
-Failed Paths   : 11
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -92.241 ns
-Required Time  : 25.00 MHz ( period = 39.999 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
-From Clock     : MAIN_CLK
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 6009
-
-Type           : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : -90.899 ns
-Required Time  : 96.01 MHz ( period = 10.416 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
-From Clock     : MAIN_CLK
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 5954
-
-Type           : Clock Setup: 'MAIN_CLK'
-Slack          : -63.646 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : 10.64 MHz ( period = 93.949 ns )
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF
-From Clock     : MAIN_CLK
-To Clock       : MAIN_CLK
-Failed Paths   : 41189
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : -17.307 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_SRC_ADR[1]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO
-From Clock     : MAIN_CLK
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 26373
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : -12.626 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_X_CNT[0]
-To             : Video:Fredi_Aschwanden|BLITTER:BLITTER|SRC_IADR[30]
-From Clock     : MAIN_CLK
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 22076
-
-Type           : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : -5.032 ns
-Required Time  : 16.00 MHz ( period = 62.499 ns )
-Actual Time    : N/A
-From           : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-Failed Paths   : 2839
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : -3.374 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : FB_ALE
-To             : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 33
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 2.966 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 3.965 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
-Slack          : 13.509 ns
-Required Time  : 2.00 MHz ( period = 499.999 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_DIR_NS1
-From Clock     : MAIN_CLK
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
-Slack          : 26.728 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|PARITY_I
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX
-From Clock     : MAIN_CLK
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'MAIN_CLK'
-Slack          : -6.235 ns
-Required Time  : 33.00 MHz ( period = 30.303 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2]
-To             : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2]
-From Clock     : MAIN_CLK
-To Clock       : MAIN_CLK
-Failed Paths   : 5610
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]'
-Slack          : -0.919 ns
-Required Time  : 25.00 MHz ( period = 39.999 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-To             : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]
-Failed Paths   : 405
-
-Type           : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]'
-Slack          : 0.456 ns
-Required Time  : 16.00 MHz ( period = 62.499 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0
-From Clock     : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-To Clock       : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]'
-Slack          : 0.502 ns
-Required Time  : 2.00 MHz ( period = 499.999 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|LP_STR_X
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]'
-Slack          : 0.502 ns
-Required Time  : 0.50 MHz ( period = 1999.998 ns )
-Actual Time    : N/A
-From           : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-To             : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]
-From Clock     : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-To Clock       : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
-To             : Video:Fredi_Aschwanden|BLITTER:BLITTER|FERTIG
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]'
-Slack          : 0.502 ns
-Required Time  : 96.01 MHz ( period = 10.416 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-To             : Video:Fredi_Aschwanden|Doppelzeilen_Fifo:inst98|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8]
-From Clock     : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-To Clock       : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]'
-Slack          : 1.815 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]
-To             : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]'
-Slack          : 2.291 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|inst90~_Duplicate_4
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]'
-Slack          : 2.612 ns
-Required Time  : 66.00 MHz ( period = 15.151 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-To             : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]
-Failed Paths   : 0
-
-Type           : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]'
-Slack          : 4.336 ns
-Required Time  : 132.01 MHz ( period = 7.575 ns )
-Actual Time    : N/A
-From           : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]
-To             : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]
-From Clock     : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-To Clock       : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]
-Failed Paths   : 0
-
-Type           : Total number of failed paths
-Slack          : 
-Required Time  : 
-Actual Time    : 
-From           : 
-To             : 
-From Clock     : 
-To Clock       : 
-Failed Paths   : 129149
-
---------------------------------------------------------------------------------------
-

From eb3e4140028e9c5153f47f741d6a5e6022a20880 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:11:34 +0200
Subject: [PATCH 08/16] fix capitalization in include path name

---
 FPGA_by_Fredi/blitter.tdf | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/FPGA_by_Fredi/blitter.tdf b/FPGA_by_Fredi/blitter.tdf
index 46f027c..6042b64 100644
--- a/FPGA_by_Fredi/blitter.tdf
+++ b/FPGA_by_Fredi/blitter.tdf
@@ -20,10 +20,10 @@
 -- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
 -- Created on Sat Jan 15 11:06:17 2011
 INCLUDE "lpm_bustri_WORD.inc";
-INCLUDE "VIDEO/BLITTER/lpm_clshift384.INC";
-INCLUDE "VIDEO/BLITTER/altsyncram0.INC";
-INCLUDE "VIDEO/BLITTER/lpm_clshift144.inc";
-INCLUDE "VIDEO/BLITTER/lpm_ror128.inc";
+INCLUDE "Video/BLITTER/lpm_clshift384.inc";
+INCLUDE "Video/BLITTER/altsyncram0.inc";
+INCLUDE "Video/BLITTER/lpm_clshift144.inc";
+INCLUDE "Video/BLITTER/lpm_ror128.inc";
 
 
 --CONSTANT	BL_SKEW_LF = 255;
@@ -151,8 +151,8 @@ VARIABLE
 	WREN_B						:NODE;				-- WR ENA HALFTONE RAM
 	X_INDEX_CS					:NODE;
 	X_INDEX[15..0]				:DFF;				-- LAUFZEIGER X COUNT
-	X_INDEX_CLR					:DFF;				-- X INDEX LÖSCHEN CPU WRITE
-	X_INDEX_CLR_DIR				:NODE;				-- X INDEX LÖSCHEN STATE MACHINE
+	X_INDEX_CLR					:DFF;				-- X INDEX L�SCHEN CPU WRITE
+	X_INDEX_CLR_DIR				:NODE;				-- X INDEX L�SCHEN STATE MACHINE
 	DST_X_INC[15..0]			:NODE;				-- ANZAHL WORTE PRO DURCHLAUF
 	X_CNT_T[15..0]				:NODE;
 	Y_INDEX_CS					:NODE;
@@ -235,7 +235,7 @@ BEGIN
 	SRC_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C520");							-- $F8A40.w
 	SRC_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C521");							-- $F8A42.w
 	SRC_IADR_CLR.CLK = MAIN_CLK;
-	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- LÖSCHEN BEI WRITE
+	SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR;				-- L�SCHEN BEI WRITE
 	SRC_IADR[] = (((SRC_IADR[] + (SRC_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * SRC_XINC32[]) + SRC_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & SRC_READ & !SRC_IADR_CLR;
 	SRC_ADR32[] = BL_SRC_ADR[] + SRC_IADR[];							-- ZUGRIFFSADRESSE THEORETISCH 
 	-- ENDMASK 1
@@ -291,7 +291,7 @@ BEGIN
 	DST_IADRH_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C522");							-- $F8A44.w
 	DST_IADRL_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C523");							-- $F8A46.w
 	DST_IADR_CLR.CLK = MAIN_CLK;					
-	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;					-- LÖSCHEN BEI WRITE
+	DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR;					-- L�SCHEN BEI WRITE
 	DST_IADR[] = (((DST_IADR[] + (DST_ADR_INC[] & SDXINC)) & !ZAINC) + ((((((0,BL_X_CNT[]) - 1) * DST_XINC32[]) + DST_YINC32[]) * (0,Y_INDEX[])) & ZAINC)) & !DST_IADR_CLR;
 	DST_ADR32[] = BL_DST_ADR[] + DST_IADR[];									-- ZUGRIFFSADRESSE THEORETISCH
 	-- X COUNT
@@ -303,7 +303,7 @@ BEGIN
 	X_INDEX[].CLK = DDRCLK0;
 	X_INDEX_CS = !nFB_CS1 & (FB_ADR[19..1] == H"7C524");							-- $F8A48.w
 	X_INDEX_CLR.CLK = MAIN_CLK;
-	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
+	X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR;										-- L�SCHEN BEI WRITE
 	X_INDEX[] = ((X_INDEX[] & !ZAINC) + (DST_X_INC[] & SDXINC) + (BL_X_CNT[] & ZAINC)) & !X_INDEX_CLR & !X_INDEX_CLR_DIR;
 	X_CNT16[] = X_INDEX[] - (X_CNT_T[] & (X_INDEX[]!=0));		-- EFFEKTIV geschrieben
 -- SCHRITTWEITEN BEI PALLETTENMOD
@@ -369,7 +369,7 @@ BEGIN
 	Y_INDEX[].CLK = DDRCLK0;
 	Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525";							-- $F8A4A.w
 	Y_INDEX_CLR.CLK = MAIN_CLK;
-	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;										-- LÖSCHEN BEI WRITE
+	Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR;										-- L�SCHEN BEI WRITE
 	Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR;
 	-- HOP LOGIC
 	BL_HOP[].CLK = MAIN_CLK;
@@ -439,7 +439,7 @@ BEGIN
 		BL_BSIN[127..0]   = BL_SRC_BUF3[];
 		BL_BSIN[255..128] = BL_SRC_BUF2[];
 		BL_BSIN[383..256] = BL_SRC_BUF1[];
-	ELSE						-- SONST NORMAL BEI VORWÄRTS
+	ELSE						-- SONST NORMAL BEI VORW�RTS
 		BL_BSIN[127..0]   = BL_SRC_BUF1[];
 		BL_BSIN[255..128] = BL_SRC_BUF2[];
 		BL_BSIN[383..256] = BL_SRC_BUF3[];
@@ -529,7 +529,7 @@ BEGIN
 			ENDMASK1_SHIFT[3..0] = 0; 						
 			ENDMASK2_SHIFT[3..0] = 0; 
 			ENDMASKEND[] =  DST_ADR32[] + (0,(BL_X_CNT[] - X_INDEX[]) - 1) * DST_XINC32[];					
-			IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV
+			IF BL_DST_X_INC15 THEN ---------------------------- R�CKW�RTS X_INC NEGATIV
 				IF X_INDEX[] == 0 THEN															-- ENDE?	
 					ENDMASK2_SHIFT[7..4] = 8 - (0,(DST_ADR32[3..1]));							-- JA ENDMASK 3 SETZEN 
 				ELSE					
@@ -540,7 +540,7 @@ BEGIN
 				ELSE					
 					ENDMASK1_SHIFT[7..4] = 0;													-- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN 
 				END IF;
-			ELSE	------------------------------------------- VORWÄRTS X_INC POSITIV (immer bei memcopy)
+			ELSE	------------------------------------------- VORW�RTS X_INC POSITIV (immer bei memcopy)
 				IF X_INDEX[] == 0 THEN															-- ANFANG?	
 					ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR32[3..1])); 							-- JA -> ENDMASK 1 SETZEN 
 				ELSE		
@@ -602,8 +602,8 @@ BEGIN
 				BL_SM = START;										-- NICHT STARTEN
 			END IF;
 		WHEN NEW_LINE => ----------------------- NEU LINIE
-			X_INDEX_CLR_DIR = VCC;									-- JA -> X INDEX LÖSCHEN FÜR START LINE 			
-			IF SRC_READ THEN										-- SOURCE READ NÖTIG?
+			X_INDEX_CLR_DIR = VCC;									-- JA -> X INDEX L�SCHEN F�R START LINE 			
+			IF SRC_READ THEN										-- SOURCE READ N�TIG?
 				BL_SM = RDSRC3;										-- JA							
 			ELSE
 				BL_SM = RDDST;										-- NEIN -> DIREKT ZU READ DEST
@@ -668,10 +668,10 @@ BEGIN
 				BL_SM = TESTFERTIG;									-- => TEST OB FERTIG
 			ELSE
 				IF !SRC_READ THEN									-- KEIN SOURCE READ?
-					BL_SM = RDDST;									-- JA => LESEN UNNÖTIG ->
+					BL_SM = RDDST;									-- JA => LESEN UNN�TIG ->
 				ELSE
 					IF SRC_ADR32[31..4] == SRC_OLD[] THEN			-- ADRESSE IMMER NOCH IN DER LINE?
-						BL_SM = RDDST;								-- DATEN SIND GÜLTIG -> READ DEST
+						BL_SM = RDDST;								-- DATEN SIND G�LTIG -> READ DEST
 					ELSE
 						BL_SM = RDSRC1;								-- SONST NEXT SRC
 					END IF;
@@ -687,8 +687,8 @@ BEGIN
 		WHEN FERTIG => -------------------------- FERTIG
 			BL_NOTRUN = VCC;										-- BLITTER NOT RUN
 			BLITTER_INT = VCC;										-- BLITTER INTERRUPT
-			LN7_CLR = VCC;											-- BUSY BIT LÖSCHEN
-			IF (BL_LN7 == 0) & (BL_START == 0) THEN			-- WARTEN BIS GELÖSCHT (SYNC MIT 33MHz)
+			LN7_CLR = VCC;											-- BUSY BIT L�SCHEN
+			IF (BL_LN7 == 0) & (BL_START == 0) THEN			-- WARTEN BIS GEL�SCHT (SYNC MIT 33MHz)
 				BL_SM = START;	
 			ELSE
 				BL_SM = FERTIG;

From 02834eaa01b70c39f6712fa8d35862534571ef76 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:12:26 +0200
Subject: [PATCH 09/16] fix DOS path names

---
 FPGA_by_Fredi/firebee1.qsf | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index 49b639b..f39fabc 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -753,8 +753,8 @@ set_global_assignment -name SOURCE_FILE altpll1.cmp
 set_global_assignment -name BDF_FILE firebee1.bdf
 set_global_assignment -name QIP_FILE altpll0.qip
 set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd"
-set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd"
+set_global_assignment -name VHDL_FILE "FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd"
+set_global_assignment -name VHDL_FILE "DSP/DSP.vhd"
 set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
 set_global_assignment -name QIP_FILE Video/altdpram0.qip
 set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
@@ -777,7 +777,7 @@ set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
 set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
 set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
 set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf"
+set_global_assignment -name AHDL_FILE "Interrupt_Handler/interrupt_handler.tdf"
 set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
 set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
 set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip

From 1b90408416f34f578d4771565f207575a7c86d77 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:12:52 +0200
Subject: [PATCH 10/16] add .gitignore and Makefile

---
 FPGA_by_Fredi/.gitignore |  5 +++++
 FPGA_by_Fredi/Makefile   | 39 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 FPGA_by_Fredi/.gitignore
 create mode 100644 FPGA_by_Fredi/Makefile

diff --git a/FPGA_by_Fredi/.gitignore b/FPGA_by_Fredi/.gitignore
new file mode 100644
index 0000000..2c3691b
--- /dev/null
+++ b/FPGA_by_Fredi/.gitignore
@@ -0,0 +1,5 @@
+
+db
+incremental_db
+*.rpt
+*.summary
diff --git a/FPGA_by_Fredi/Makefile b/FPGA_by_Fredi/Makefile
new file mode 100644
index 0000000..ce95a1b
--- /dev/null
+++ b/FPGA_by_Fredi/Makefile
@@ -0,0 +1,39 @@
+SHELL=/bin/csh
+
+ifeq ($(OS),Windows_NT)
+	ALTPATH=c:/opt/altera/9.1sp2/quartus/bin64
+else
+	ALTPATH=/opt/altera/9.1sp2/quartus/bin
+endif
+BITSTREAM=output_files/$(PROJ).sof
+BUILD_DIR=.
+
+PROJ=firebee1
+
+all: synthesis fitter assembler timing_analyzer eda
+
+precmd:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_sh $(ALTOPT) -t precmd.tcl)
+
+synthesis:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_map --read_settings_files=on --write_settings_files=off $(ALTOPT) $(PROJ) -c $(PROJ))
+
+fitter:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_fit --read_settings_files=off --write_settings_files=off $(ALTOPT) $(PROJ) -c $(PROJ))
+
+assembler:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_asm --read_settings_files=off --write_settings_files=off $(ALTOPT) $(PROJ) -c $(PROJ))
+
+timing_analyzer:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_sta $(ALTOPT) $(PROJ))
+
+eda:
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_eda --simulation --read_settings_files=off --write_settings_files=off $(ALTOPT) $(PROJ) -c $(PROJ))
+
+# program the beast
+p: $(BITSTREAM)
+	(cd $(BUILD_DIR); $(ALTPATH)/quartus_pgm $(ALTOPT) -m JTAG -o P\;$(BITSTREAM)@1)
+
+.PHONY: clean
+clean:
+	(cd $(BUILD_DIR); rm -rf db incremental_db)

From bbc93f9498f9b6b836e9d815195a71d2662a63ee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:17:14 +0200
Subject: [PATCH 11/16] add more generated files to .gitignore

---
 FPGA_by_Fredi/.gitignore | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/FPGA_by_Fredi/.gitignore b/FPGA_by_Fredi/.gitignore
index 2c3691b..0d96d94 100644
--- a/FPGA_by_Fredi/.gitignore
+++ b/FPGA_by_Fredi/.gitignore
@@ -3,3 +3,7 @@ db
 incremental_db
 *.rpt
 *.summary
+*.sof
+*.rbf
+PLLJ_PLLSPE_INFO.txt
+

From cc0a0fb8bf4d53dce586d800774131f3c8b1fbef Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:20:40 +0200
Subject: [PATCH 12/16] fix (potential) typo in .qpf naming

---
 FPGA_by_Fredi/Makefile                        |   2 +-
 FPGA_by_Fredi/firebee1.pin                    | 557 ------------------
 FPGA_by_Fredi/{firebeei1.qpf => firebee1.qpf} |  54 +-
 FPGA_by_Fredi/firebee1.sof                    | Bin 1171297 -> 0 bytes
 4 files changed, 32 insertions(+), 581 deletions(-)
 delete mode 100644 FPGA_by_Fredi/firebee1.pin
 rename FPGA_by_Fredi/{firebeei1.qpf => firebee1.qpf} (60%)
 delete mode 100644 FPGA_by_Fredi/firebee1.sof

diff --git a/FPGA_by_Fredi/Makefile b/FPGA_by_Fredi/Makefile
index ce95a1b..5878caf 100644
--- a/FPGA_by_Fredi/Makefile
+++ b/FPGA_by_Fredi/Makefile
@@ -8,7 +8,7 @@ endif
 BITSTREAM=output_files/$(PROJ).sof
 BUILD_DIR=.
 
-PROJ=firebee1
+PROJ=firebeei1
 
 all: synthesis fitter assembler timing_analyzer eda
 
diff --git a/FPGA_by_Fredi/firebee1.pin b/FPGA_by_Fredi/firebee1.pin
deleted file mode 100644
index 83dafe4..0000000
--- a/FPGA_by_Fredi/firebee1.pin
+++ /dev/null
@@ -1,557 +0,0 @@
- -- Copyright (C) 1991-2010 Altera Corporation
- -- Your use of Altera Corporation's design tools, logic functions 
- -- and other software and tools, and its AMPP partner logic 
- -- functions, and any output files from any of the foregoing 
- -- (including device programming or simulation files), and any 
- -- associated documentation or information are expressly subject 
- -- to the terms and conditions of the Altera Program License 
- -- Subscription Agreement, Altera MegaCore Function License 
- -- Agreement, or other applicable license agreement, including, 
- -- without limitation, that your use is for the sole purpose of 
- -- programming logic devices manufactured by Altera and sold by 
- -- Altera or its authorized distributors.  Please refer to the 
- -- applicable agreement for further details.
- -- 
- -- This is a Quartus II output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus II input file. This file cannot be used
- -- to make Quartus II pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus II help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC            : No Connect. This pin has no internal connection to the device.
- -- DNU           : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
- -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
- --                 of its bank.
- --					Bank 1:		3.3V
- --					Bank 2:		3.3V
- --					Bank 3:		3.3V
- --					Bank 4:		2.5V
- --					Bank 5:		2.5V
- --					Bank 6:		3.0V
- --					Bank 7:		3.3V
- --					Bank 8:		3.0V
- -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- --					It can also be used to report unused dedicated pins. The connection
- --					on the board for unused dedicated pins depends on whether this will
- --					be used in a future design. One example is device migration. When
- --					using device migration, refer to the device pin-tables. If it is a
- --					GND pin in the pin table or if it will not be used in a future design
- --					for another purpose the it MUST be connected to GND. If it is an unused
- --					dedicated pin, then it can be connected to a valid signal on the board
- --					(low, high, or toggling) if that signal is required for a different
- --					revision of the design.
- -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
- --					This pin should be connected to GND. It may also be connected  to a
- --					valid signal  on the board  (low, high, or toggling)  if that signal
- --					is required for a different revision of the design.
- -- GND*          : Unused  I/O  pin.   For transceiver I/O banks, connect each pin marked GND*
- --           	    either individually through a 10k Ohm resistor to GND or tie all pins
- --           	    together and connect through a single 10k Ohm resistor to GND.
- --           	    For non-transceiver I/O banks, connect each pin marked GND* directly to GND
- --           	    or leave it unconnected.
- -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
-CHIP  "firebee1"  ASSIGNED TO AN: EP3C40F484C6
-
-Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND                          : A1        : gnd    :                   :         :           :                
-VCCIO8                       : A2        : power  :                   : 3.0V    : 8         :                
-LP_D[6]                      : A3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nSRBLE                       : A4        : output : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[1]                       : A5        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[3]                        : A6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[1]                        : A7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[0]                        : A8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[10]                      : A9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[9]                       : A10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-DVI_INT                      : A11       : input  : 3.3-V LVTTL       :         : 8         : Y              
-nDACK1                       : A12       : input  : 3.3-V LVTTL       :         : 7         : Y              
-IO[16]                       : A13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[14]                       : A14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[9]                        : A15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA1                     : A16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-YM_QA                        : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
-TxD                          : A18       : output : 3.3-V LVTTL       :         : 7         : Y              
-DCD                          : A19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nRD_DATA                     : A20       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
-GND                          : A22       : gnd    :                   :         :           :                
-nPCI_INTA                    : AA1       : input  : 3.3-V LVTTL       :         : 2         : Y              
-PIC_INT                      : AA2       : input  : 3.3-V LVTTL       :         : 2         : Y              
-FB_AD[2]                     : AA3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[6]                     : AA4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[8]                     : AA5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
-FB_AD[15]                    : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[22]                    : AA8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[25]                    : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[31]                    : AA10      : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : AA11      :        :                   :         : 3         :                
-GND+                         : AA12      :        :                   :         : 4         :                
-VD[18]                       : AA13      : bidir  : 2.5 V             :         : 4         : Y              
-VD[25]                       : AA14      : bidir  : 2.5 V             :         : 4         : Y              
-VDQS[0]                      : AA15      : bidir  : 2.5 V             :         : 4         : Y              
-VDM[0]                       : AA16      : output : 2.5 V             :         : 4         : Y              
-nDDR_CLK                     : AA17      : output : 2.5 V             :         : 4         : Y              
-VA[12]                       : AA18      : output : 2.5 V             :         : 4         : Y              
-BA[1]                        : AA19      : output : 2.5 V             :         : 4         : Y              
-VA[7]                        : AA20      : output : 2.5 V             :         : 4         : Y              
-VA[6]                        : AA21      : output : 2.5 V             :         : 5         : Y              
-VA[4]                        : AA22      : output : 2.5 V             :         : 5         : Y              
-GND                          : AB1       : gnd    :                   :         :           :                
-VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
-FB_AD[3]                     : AB3       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[7]                     : AB4       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[9]                     : AB5       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : AB6       : gnd    :                   :         :           :                
-FB_AD[16]                    : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[23]                    : AB8       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[26]                    : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-CLK24M576                    : AB10      : output : 3.3-V LVTTL       :         : 3         : Y              
-GND+                         : AB11      :        :                   :         : 3         :                
-CLK33MDIR                    : AB12      : input  : 3.3-V LVTTL       :         : 4         : Y              
-VD[29]                       : AB13      : bidir  : 2.5 V             :         : 4         : Y              
-VD[26]                       : AB14      : bidir  : 2.5 V             :         : 4         : Y              
-VD[24]                       : AB15      : bidir  : 2.5 V             :         : 4         : Y              
-VD[23]                       : AB16      : bidir  : 2.5 V             :         : 4         : Y              
-DDR_CLK                      : AB17      : output : 2.5 V             :         : 4         : Y              
-nVCAS                        : AB18      : output : 2.5 V             :         : 4         : Y              
-VA[9]                        : AB19      : output : 2.5 V             :         : 4         : Y              
-VA[8]                        : AB20      : output : 2.5 V             :         : 4         : Y              
-VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
-GND                          : AB22      : gnd    :                   :         :           :                
-ACSI_D[0]                    : B1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-MIDI_TLR                     : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[5]                      : B3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nSRBHE                       : B4        : output : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[0]                       : B5        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[4]                        : B6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[2]                        : B7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nSRCS                        : B8        : output : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[8]                       : B9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[11]                      : B10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nRSTO_MCF                    : B11       : input  : 3.3-V LVTTL       :         : 8         : Y              
-nDACK0                       : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
-IO[17]                       : B13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[15]                       : B14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[10]                       : B15       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA0                     : B16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-SD_DATA2                     : B17       : input  : 3.3-V LVTTL       :         : 7         : Y              
-RTS                          : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
-RI                           : B19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nSDSEL                       : B20       : output : 3.3-V LVTTL       :         : 7         : Y              
-VB[5]                        : B21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[4]                        : B22       : output : 3.0-V LVTTL       :         : 6         : Y              
-ACSI_D[4]                    : C1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[3]                    : C2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-LP_D[2]                      : C3        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-LP_D[1]                      : C4        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-GND                          : C5        : gnd    :                   :         :           :                
-SRD[2]                       : C6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[7]                        : C7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[6]                        : C8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-GND                          : C9        : gnd    :                   :         :           :                
-SRD[4]                       : C10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-GND                          : C11       : gnd    :                   :         :           :                
-GND                          : C12       : gnd    :                   :         :           :                
-IO[11]                       : C13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C14       : gnd    :                   :         :           :                
-SD_CLK                       : C15       : output : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C16       : gnd    :                   :         :           :                
-nDCHG                        : C17       : input  : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : C18       : gnd    :                   :         :           :                
-TRACK00                      : C19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VB[6]                        : C20       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[3]                        : C21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[2]                        : C22       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
-ACSI_D[5]                    : D2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : D3        : gnd    :                   :         :           :                
-VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
-VCCIO8                       : D5        : power  :                   : 3.0V    : 8         :                
-LP_D[4]                      : D6        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7        :        :                   :         : 8         :                
-GND                          : D8        : gnd    :                   :         :           :                
-VCCIO8                       : D9        : power  :                   : 3.0V    : 8         :                
-SRD[12]                      : D10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-VCCIO8                       : D11       : power  :                   : 3.0V    : 8         :                
-VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
-IO[12]                       : D13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
-DTR                          : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
-nWR_GATE                     : D17       : output : 3.3-V LVTTL       :         : 7         : Y              
-VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
-nWP                          : D19       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VB[7]                        : D20       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[7]                        : D21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[6]                        : D22       : output : 3.0-V LVTTL       :         : 6         : Y              
-SCSI_D[1]                    : E1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
-ACSI_D[2]                    : E3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4        :        :                   :         : 1         :                
-LPDIR                        : E5        : output : 3.0-V LVCMOS      :         : 8         : Y              
-LP_STR                       : E6        : output : 3.0-V LVCMOS      :         : 8         : Y              
-LP_D[3]                      : E7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-VCCIO8                       : E8        : power  :                   : 3.0V    : 8         :                
-IO[5]                        : E9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[6]                       : E10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nDREQ1                       : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
-MIDI_IN_PIN                  : E12       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-IO[13]                       : E13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-SD_CMD_D1                    : E14       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-YM_QC                        : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
-nINDEX                       : E16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
-GNDA2                        : E18       : gnd    :                   :         :           :                
-VCCIO6                       : E19       : power  :                   : 3.0V    : 6         :                
-GND                          : E20       : gnd    :                   :         :           :                
-VG[2]                        : E21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[1]                        : E22       : output : 3.0-V LVTTL       :         : 6         : Y              
-SCSI_D[3]                    : F1        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[2]                    : F2        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : F3        : gnd    :                   :         :           :                
-VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
-GNDA3                        : F5        : gnd    :                   :         :           :                
-VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
-LP_D[0]                      : F7        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nSRWE                        : F8        : output : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[5]                       : F9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[13]                      : F10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-nSROE                        : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
-GND                          : F12       : gnd    :                   :         :           :                
-SD_CD_DATA3                  : F13       : bidir  : 3.3-V LVTTL       :         : 7         : Y              
-nSTEP                        : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
-DSA_D                        : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
-HD_DD                        : F16       : input  : 3.3-V LVTTL       :         : 7         : Y              
-nSYNC                        : F17       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VCCA2                        : F18       : power  :                   : 2.5V    :           :                
-PIXEL_CLK_PAD                : F19       : output : 3.0-V LVTTL       :         : 6         : Y              
-nIRQ[4]                      : F20       : output : 3.0-V LVCMOS      :         : 6         : Y              
-nIRQ[2]                      : F21       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VR[7]                        : F22       : output : 3.0-V LVTTL       :         : 6         : Y              
-GND+                         : G1        :        :                   :         : 1         :                
-MAIN_CLK                     : G2        : input  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[5]                    : G3        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[4]                    : G4        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[1]                    : G5        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCA3                        : G6        : power  :                   : 2.5V    :           :                
-LP_BUSY                      : G7        : input  : 3.3-V LVTTL       :         : 8         : Y              
-LP_D[7]                      : G8        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[14]                      : G9        : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-IO[8]                        : G10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[3]                       : G11       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-VCCINT                       : G12       : power  :                   : 1.2V    :           :                
-YM_QB                        : G13       : output : 3.3-V LVTTL       :         : 7         : Y              
-nWR                          : G14       : output : 3.3-V LVTTL       :         : 7         : Y              
-nSTEP_DIR                    : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
-nMOT_ON                      : G16       : output : 3.3-V LVTTL       :         : 7         : Y              
-nBLANK_PAD                   : G17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[0]                        : G18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VCCIO6                       : G19       : power  :                   : 3.0V    : 6         :                
-GND                          : G20       : gnd    :                   :         :           :                
-E0_INT                       : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
-IDE_INT                      : G22       : input  : 3.3-V LVTTL       :         : 6         : Y              
-nSCSI_C_D                    : H1        : input  : 3.3-V LVTTL       :         : 1         : Y              
-nSCSI_MSG                    : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
-GND                          : H3        : gnd    :                   :         :           :                
-VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
-MIDI_OLR                     : H5        : output : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[7]                    : H6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-ACSI_D[6]                    : H7        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8        :        :                   :         : 1         :                
-VCCINT                       : H9        : power  :                   : 1.2V    :           :                
-SRD[15]                      : H10       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-SRD[7]                       : H11       : bidir  : 3.0-V LVCMOS      :         : 8         : Y              
-GND                          : H12       : gnd    :                   :         :           :                
-GND                          : H13       : gnd    :                   :         :           :                
-CTS                          : H14       : input  : 3.3-V LVTTL       :         : 7         : Y              
-RxD                          : H15       : input  : 3.3-V LVTTL       :         : 7         : Y              
-VG[5]                        : H16       : output : 3.0-V LVTTL       :         : 6         : Y              
-VB[1]                        : H17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[3]                        : H18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VG[0]                        : H19       : output : 3.0-V LVTTL       :         : 6         : Y              
-nIRQ[3]                      : H20       : output : 3.0-V LVCMOS      :         : 6         : Y              
-VR[3]                        : H21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[2]                        : H22       : output : 3.0-V LVTTL       :         : 6         : Y              
-CLKUSB                       : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J2        :        :                   :         : 1         :                
-nSCSI_I_O                    : J3        : input  : 3.3-V LVTTL       :         : 1         : Y              
-nACSI_INT                    : J4        : input  : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J5        :        :                   :         : 1         :                
-SCSI_D[0]                    : J6        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_DIR                     : J7        : output : 3.3-V LVTTL       :         : 1         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : J8        :        :                   :         : 1         :                
-GND                          : J9        : gnd    :                   :         :           :                
-VCCINT                       : J10       : power  :                   : 1.2V    :           :                
-VCCINT                       : J11       : power  :                   : 1.2V    :           :                
-VCCINT                       : J12       : power  :                   : 1.2V    :           :                
-VCCINT                       : J13       : power  :                   : 1.2V    :           :                
-VCCINT                       : J14       : power  :                   : 1.2V    :           :                
-GND                          : J15       : gnd    :                   :         :           :                
-VCCINT                       : J16       : power  :                   : 1.2V    :           :                
-VG[4]                        : J17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[6]                        : J18       : output : 3.0-V LVTTL       :         : 6         : Y              
-GND                          : J19       : gnd    :                   :         :           :                
-VCCIO6                       : J20       : power  :                   : 3.0V    : 6         :                
-VR[1]                        : J21       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[0]                        : J22       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_DATA0~ / RESERVED_INPUT : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
-~ALTERA_DCLK~ / RESERVED_INPUT : K2        : input  : 3.3-V LVTTL       :         : 1         : N              
-GND                          : K3        : gnd    :                   :         :           :                
-VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
-nCONFIG                      : K5        :        :                   :         : 1         :                
-nSTATUS                      : K6        :        :                   :         : 1         :                
-nACSI_DRQ                    : K7        : input  : 3.3-V LVTTL       :         : 1         : Y              
-SCSI_D[7]                    : K8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCINT                       : K9        : power  :                   : 1.2V    :           :                
-GND                          : K10       : gnd    :                   :         :           :                
-GND                          : K11       : gnd    :                   :         :           :                
-GND                          : K12       : gnd    :                   :         :           :                
-GND                          : K13       : gnd    :                   :         :           :                
-VCCINT                       : K14       : power  :                   : 1.2V    :           :                
-VCCINT                       : K15       : power  :                   : 1.2V    :           :                
-GND                          : K16       : gnd    :                   :         :           :                
-VR[4]                        : K17       : output : 3.0-V LVTTL       :         : 6         : Y              
-VR[5]                        : K18       : output : 3.0-V LVTTL       :         : 6         : Y              
-VSYNC_PAD                    : K19       : output : 3.0-V LVTTL       :         : 6         : Y              
-MSEL3                        : K20       :        :                   :         : 6         :                
-HSYNC_PAD                    : K21       : output : 3.0-V LVTTL       :         : 6         : Y              
-~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22       : output : 3.0-V LVTTL       :         : 6         : N              
-TMS                          : L1        : input  :                   :         : 1         :                
-TCK                          : L2        : input  :                   :         : 1         :                
-nCE                          : L3        :        :                   :         : 1         :                
-TDO                          : L4        : output :                   :         : 1         :                
-TDI                          : L5        : input  :                   :         : 1         :                
-ACSI_DIR                     : L6        : output : 3.3-V LVTTL       :         : 2         : Y              
-PIC_AMKB_RX                  : L7        : input  : 3.3-V LVTTL       :         : 2         : Y              
-SCSI_D[6]                    : L8        : bidir  : 3.3-V LVTTL       :         : 1         : Y              
-VCCINT                       : L9        : power  :                   : 1.2V    :           :                
-GND                          : L10       : gnd    :                   :         :           :                
-GND                          : L11       : gnd    :                   :         :           :                
-GND                          : L12       : gnd    :                   :         :           :                
-GND                          : L13       : gnd    :                   :         :           :                
-VCCINT                       : L14       : power  :                   : 1.2V    :           :                
-GND                          : L15       : gnd    :                   :         :           :                
-VCCINT                       : L16       : power  :                   : 1.2V    :           :                
-MSEL2                        : L17       :        :                   :         : 6         :                
-MSEL1                        : L18       :        :                   :         : 6         :                
-VCCIO6                       : L19       : power  :                   : 3.0V    : 6         :                
-GND                          : L20       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L21       :        :                   :         : 6         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : L22       :        :                   :         : 6         :                
-nACSI_RESET                  : M1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nACSI_CS                     : M2        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_ATN                    : M3        : output : 3.3-V LVTTL       :         : 2         : Y              
-nACSI_ACK                    : M4        : output : 3.3-V LVTTL       :         : 2         : Y              
-IDE_RES                      : M5        : output : 3.3-V LVTTL       :         : 2         : Y              
-ACSI_A1                      : M6        : output : 3.3-V LVTTL       :         : 2         : Y              
-SCSI_PAR                     : M7        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_SEL                    : M8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : M9        : power  :                   : 1.2V    :           :                
-GND                          : M10       : gnd    :                   :         :           :                
-GND                          : M11       : gnd    :                   :         :           :                
-GND                          : M12       : gnd    :                   :         :           :                
-GND                          : M13       : gnd    :                   :         :           :                
-VCCINT                       : M14       : power  :                   : 1.2V    :           :                
-VCCINT                       : M15       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
-MSEL0                        : M17       :        :                   :         : 6         :                
-CONF_DONE                    : M18       :        :                   :         : 6         :                
-SD_WP                        : M19       : input  : 3.3-V LVTTL       :         : 5         : Y              
-SD_CARD_DEDECT               : M20       : input  : 3.3-V LVTTL       :         : 5         : Y              
-VD[1]                        : M21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[0]                        : M22       : bidir  : 2.5 V             :         : 5         : Y              
-AMKB_TX                      : N1        : output : 3.3-V LVCMOS      :         : 2         : Y              
-nSCSI_ACK                    : N2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : N3        : gnd    :                   :         :           :                
-VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
-nRP_LDS                      : N5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_RST                    : N6        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[7]                      : N7        : output : 3.3-V LVTTL       :         : 2         : Y              
-nSCSI_BUSY                   : N8        : bidir  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : N9        : power  :                   : 1.2V    :           :                
-GND                          : N10       : gnd    :                   :         :           :                
-GND                          : N11       : gnd    :                   :         :           :                
-GND                          : N12       : gnd    :                   :         :           :                
-GND                          : N13       : gnd    :                   :         :           :                
-VCCINT                       : N14       : power  :                   : 1.2V    :           :                
-GND                          : N15       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
-VD[12]                       : N17       : bidir  : 2.5 V             :         : 5         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
-LED_FPGA_OK                  : N19       : output : 2.5 V             :         : 5         : Y              
-VD[15]                       : N20       : bidir  : 2.5 V             :         : 5         : Y              
-~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21       : input  : 2.5 V             :         : 5         : N              
-~ALTERA_DEV_OE~ / RESERVED_INPUT : N22       : input  : 2.5 V             :         : 5         : N              
-nIDE_RD                      : P1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIDE_WR                      : P2        : output : 3.3-V LVTTL       :         : 2         : Y              
-nROM3                        : P3        : output : 3.3-V LVTTL       :         : 2         : Y              
-nRP_UDS                      : P4        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[5]                      : P5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nPCI_INTD                    : P6        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nIRQ[6]                      : P7        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : P8        : gnd    :                   :         :           :                
-VCCINT                       : P9        : power  :                   : 1.2V    :           :                
-VCCINT                       : P10       : power  :                   : 1.2V    :           :                
-VCCINT                       : P11       : power  :                   : 1.2V    :           :                
-VCCINT                       : P12       : power  :                   : 1.2V    :           :                
-VCCINT                       : P13       : power  :                   : 1.2V    :           :                
-VCCINT                       : P14       : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
-VD[10]                       : P17       : bidir  : 2.5 V             :         : 5         : Y              
-VCCIO5                       : P18       : power  :                   : 2.5V    : 5         :                
-GND                          : P19       : gnd    :                   :         :           :                
-VD[13]                       : P20       : bidir  : 2.5 V             :         : 5         : Y              
-VD[4]                        : P21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[2]                        : P22       : bidir  : 2.5 V             :         : 5         : Y              
-nIDE_CS1                     : R1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nIDE_CS0                     : R2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : R3        : gnd    :                   :         :           :                
-VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
-TIN0                         : R5        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_OE                       : R6        : input  : 3.3-V LVTTL       :         : 2         : Y              
-FB_ALE                       : R7        : input  : 3.3-V LVTTL       :         : 2         : Y              
-VCCINT                       : R8        : power  :                   : 1.2V    :           :                
-GND                          : R9        : gnd    :                   :         :           :                
-VCCINT                       : R10       : power  :                   : 1.2V    :           :                
-GND                          : R11       : gnd    :                   :         :           :                
-VCCINT                       : R12       : power  :                   : 1.2V    :           :                
-GND                          : R13       : gnd    :                   :         :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
-VD[5]                        : R17       : bidir  : 2.5 V             :         : 5         : Y              
-VD[9]                        : R18       : bidir  : 2.5 V             :         : 5         : Y              
-VD[6]                        : R19       : bidir  : 2.5 V             :         : 5         : Y              
-VD[3]                        : R20       : bidir  : 2.5 V             :         : 5         : Y              
-VD[11]                       : R21       : bidir  : 2.5 V             :         : 5         : Y              
-VD[14]                       : R22       : bidir  : 2.5 V             :         : 5         : Y              
-WP_CF_CARD                   : T1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-GND+                         : T2        :        :                   :         : 2         :                
-nFB_BURST                    : T3        : input  : 3.3-V LVTTL       :         : 2         : Y              
-CLK25M                       : T4        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_WR                       : T5        : input  : 3.3-V LVTTL       :         : 2         : Y              
-VCCA1                        : T6        : power  :                   : 2.5V    :           :                
-nFB_TA                       : T7        : output : 3.3-V LVTTL       :         : 2         : Y              
-nFB_CS1                      : T8        : input  : 3.3-V LVTTL       :         : 3         : Y              
-nFB_CS2                      : T9        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[20]                    : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[24]                    : T11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[16]                       : T12       : bidir  : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : T13       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
-VDQS[3]                      : T16       : bidir  : 2.5 V             :         : 4         : Y              
-VDM[3]                       : T17       : output : 2.5 V             :         : 5         : Y              
-nVCS                         : T18       : output : 2.5 V             :         : 5         : Y              
-VCCIO5                       : T19       : power  :                   : 2.5V    : 5         :                
-GND                          : T20       : gnd    :                   :         :           :                
-nMASTER                      : T21       : input  : 3.3-V LVTTL       :         : 5         : Y              
-TOUT0                        : T22       : input  : 3.3-V LVTTL       :         : 5         : Y              
-nSCSI_DRQ                    : U1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nROM4                        : U2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : U3        : gnd    :                   :         :           :                
-VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
-GNDA1                        : U5        : gnd    :                   :         :           :                
-VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
-FB_SIZE0                     : U8        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[12]                    : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[21]                    : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[27]                    : U11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[31]                       : U12       : bidir  : 2.5 V             :         : 4         : Y              
-VD[20]                       : U13       : bidir  : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
-VCKE                         : U15       : output : 2.5 V             :         : 4         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : U16       :        :                   :         : 4         :                
-RESERVED_INPUT_WITH_WEAK_PULLUP : U17       :        :                   :         : 4         :                
-VCCA4                        : U18       : power  :                   : 2.5V    :           :                
-VA[11]                       : U19       : output : 2.5 V             :         : 5         : Y              
-VDM[2]                       : U20       : output : 2.5 V             :         : 5         : Y              
-VD[7]                        : U21       : bidir  : 2.5 V             :         : 5         : Y              
-VDQS[2]                      : U22       : bidir  : 2.5 V             :         : 5         : Y              
-nPD_VGA                      : V1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nDREQ0                       : V2        : output : 3.3-V LVTTL       :         : 2         : Y              
-nPCI_INTC                    : V3        : input  : 3.3-V LVTTL       :         : 2         : Y              
-nPCI_INTB                    : V4        : input  : 3.3-V LVTTL       :         : 2         : Y              
-RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
-nFB_CS3                      : V6        : input  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[5]                     : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[13]                    : V8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[18]                    : V9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[19]                    : V10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[28]                    : V11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VD[30]                       : V12       : bidir  : 2.5 V             :         : 4         : Y              
-VD[27]                       : V13       : bidir  : 2.5 V             :         : 4         : Y              
-VD[19]                       : V14       : bidir  : 2.5 V             :         : 4         : Y              
-VD[21]                       : V15       : bidir  : 2.5 V             :         : 4         : Y              
-VDM[1]                       : V16       : output : 2.5 V             :         : 4         : Y              
-VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
-GNDA4                        : V18       : gnd    :                   :         :           :                
-VCCIO5                       : V19       : power  :                   : 2.5V    : 5         :                
-GND                          : V20       : gnd    :                   :         :           :                
-VA[10]                       : V21       : output : 2.5 V             :         : 5         : Y              
-VD[8]                        : V22       : bidir  : 2.5 V             :         : 5         : Y              
-nCF_CS1                      : W1        : output : 3.3-V LVTTL       :         : 2         : Y              
-nCF_CS0                      : W2        : output : 3.3-V LVTTL       :         : 2         : Y              
-GND                          : W3        : gnd    :                   :         :           :                
-VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
-VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
-FB_AD[4]                     : W6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[10]                    : W7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[14]                    : W8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
-FB_AD[29]                    : W10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
-VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
-VD[28]                       : W13       : bidir  : 2.5 V             :         : 4         : Y              
-VD[22]                       : W14       : bidir  : 2.5 V             :         : 4         : Y              
-VDQS[1]                      : W15       : bidir  : 2.5 V             :         : 4         : Y              
-VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
-nVRAS                        : W17       : output : 2.5 V             :         : 4         : Y              
-VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
-BA[0]                        : W19       : output : 2.5 V             :         : 5         : Y              
-VA[0]                        : W20       : output : 2.5 V             :         : 5         : Y              
-VA[2]                        : W21       : output : 2.5 V             :         : 5         : Y              
-VA[1]                        : W22       : output : 2.5 V             :         : 5         : Y              
-IDE_RDY                      : Y1        : input  : 3.3-V LVTTL       :         : 2         : Y              
-AMKB_RX                      : Y2        : input  : 3.3-V LVCMOS      :         : 2         : Y              
-FB_AD[0]                     : Y3        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_SIZE1                     : Y4        : input  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y5        : gnd    :                   :         :           :                
-FB_AD[1]                     : Y6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[11]                    : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-FB_AD[17]                    : Y8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y9        : gnd    :                   :         :           :                
-FB_AD[30]                    : Y10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
-GND                          : Y11       : gnd    :                   :         :           :                
-GND                          : Y12       : gnd    :                   :         :           :                
-VD[17]                       : Y13       : bidir  : 2.5 V             :         : 4         : Y              
-VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
-GND                          : Y15       : gnd    :                   :         :           :                
-GND                          : Y16       : gnd    :                   :         :           :                
-nVWE                         : Y17       : output : 2.5 V             :         : 4         : Y              
-GND                          : Y18       : gnd    :                   :         :           :                
-VCCIO5                       : Y19       : power  :                   : 2.5V    : 5         :                
-GND                          : Y20       : gnd    :                   :         :           :                
-VA[5]                        : Y21       : output : 2.5 V             :         : 5         : Y              
-VA[3]                        : Y22       : output : 2.5 V             :         : 5         : Y              
diff --git a/FPGA_by_Fredi/firebeei1.qpf b/FPGA_by_Fredi/firebee1.qpf
similarity index 60%
rename from FPGA_by_Fredi/firebeei1.qpf
rename to FPGA_by_Fredi/firebee1.qpf
index 8ab6c97..2a5950d 100644
--- a/FPGA_by_Fredi/firebeei1.qpf
+++ b/FPGA_by_Fredi/firebee1.qpf
@@ -1,23 +1,31 @@
-# Copyright (C) 1991-2008 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "8.1"
-DATE = "10:07:29  September 03, 2009"
-
-
-# Revisions
-
-PROJECT_REVISION = "firebee1"
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 08:19:01  August 28, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.1"
+DATE = "08:19:01  August 28, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "firebee1"
+PROJECT_REVISION = "firebeei1"
diff --git a/FPGA_by_Fredi/firebee1.sof b/FPGA_by_Fredi/firebee1.sof
deleted file mode 100644
index 62e417c0d1f5dfa7defbdbb3ec1fa8d711f5a2d0..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 1171297
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z-k<xx$A0$b{v!R*579gR!oT{_4}auCAEO`t(8vDbhyTLQ&<}jq_t4#+`|w9TNZ<Q?
zM|AYP-~G0?fA`ytzUPR3^g|!}*FXGIAEM(A{M4VPx6zNjoBqWQ{Up8fgCG7`F;h$R
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From b5e9e10bc371acb68f01cf1db63bbf9b18a1f714 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:21:59 +0200
Subject: [PATCH 13/16] fix typo in .qpf and Makefile

---
 FPGA_by_Fredi/Makefile     | 2 +-
 FPGA_by_Fredi/firebee1.qpf | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/FPGA_by_Fredi/Makefile b/FPGA_by_Fredi/Makefile
index 5878caf..ce95a1b 100644
--- a/FPGA_by_Fredi/Makefile
+++ b/FPGA_by_Fredi/Makefile
@@ -8,7 +8,7 @@ endif
 BITSTREAM=output_files/$(PROJ).sof
 BUILD_DIR=.
 
-PROJ=firebeei1
+PROJ=firebee1
 
 all: synthesis fitter assembler timing_analyzer eda
 
diff --git a/FPGA_by_Fredi/firebee1.qpf b/FPGA_by_Fredi/firebee1.qpf
index 2a5950d..c5def26 100644
--- a/FPGA_by_Fredi/firebee1.qpf
+++ b/FPGA_by_Fredi/firebee1.qpf
@@ -28,4 +28,3 @@ DATE = "08:19:01  August 28, 2019"
 # Revisions
 
 PROJECT_REVISION = "firebee1"
-PROJECT_REVISION = "firebeei1"

From 18fcbbd7de8753a958bd4fa482fb032e7325c7e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 08:36:19 +0200
Subject: [PATCH 14/16] add .pin file type

---
 FPGA_by_Fredi/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/FPGA_by_Fredi/.gitignore b/FPGA_by_Fredi/.gitignore
index 0d96d94..29069b4 100644
--- a/FPGA_by_Fredi/.gitignore
+++ b/FPGA_by_Fredi/.gitignore
@@ -5,5 +5,6 @@ incremental_db
 *.summary
 *.sof
 *.rbf
+*.pin
 PLLJ_PLLSPE_INFO.txt
 

From d50983a69b3683586f001663648003955720f8c1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 16:34:31 +0200
Subject: [PATCH 15/16] add more file extensions of generated files

---
 FPGA_by_Fredi/.gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/FPGA_by_Fredi/.gitignore b/FPGA_by_Fredi/.gitignore
index 29069b4..56c4ab3 100644
--- a/FPGA_by_Fredi/.gitignore
+++ b/FPGA_by_Fredi/.gitignore
@@ -6,5 +6,7 @@ incremental_db
 *.sof
 *.rbf
 *.pin
+*.smsg
+*.jdi
 PLLJ_PLLSPE_INFO.txt
 

From fab65c7718da1a3512514840e121e8b2a8aeb94c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 28 Aug 2019 16:35:08 +0200
Subject: [PATCH 16/16] remove generated files from git

---
 FPGA_by_Fredi/firebee1.done | 2 +-
 FPGA_by_Fredi/firebee1.qsf  | 2 +-
 FPGA_by_Fredi/firebee1.qws  | 4 ----
 3 files changed, 2 insertions(+), 6 deletions(-)
 delete mode 100644 FPGA_by_Fredi/firebee1.qws

diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done
index eec570b..33428b5 100644
--- a/FPGA_by_Fredi/firebee1.done
+++ b/FPGA_by_Fredi/firebee1.done
@@ -1 +1 @@
-Thu Jun 22 14:21:02 2017
+Wed Aug 28 16:04:24 2019
diff --git a/FPGA_by_Fredi/firebee1.qsf b/FPGA_by_Fredi/firebee1.qsf
index f39fabc..98e45e8 100644
--- a/FPGA_by_Fredi/firebee1.qsf
+++ b/FPGA_by_Fredi/firebee1.qsf
@@ -41,7 +41,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name LAST_QUARTUS_VERSION 8.1
 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
 
 # Pin & Location Assignments
diff --git a/FPGA_by_Fredi/firebee1.qws b/FPGA_by_Fredi/firebee1.qws
deleted file mode 100644
index ed1a121..0000000
--- a/FPGA_by_Fredi/firebee1.qws
+++ /dev/null
@@ -1,4 +0,0 @@
-[ProjectWorkspace]
-ptn_Child1=Frames
-[ProjectWorkspace.Frames]
-ptn_Child1=ChildFrames